X9400YS24M-2.7 [XICOR]
Digital Potentiometer, 4 Func, 2500ohm, 3-wire Serial Control Interface, 64 Positions, PDSO24, PLASTIC, SOIC-24;
| 型号： | X9400YS24M-2.7 |
| 厂家： | 
XICOR INC. |
| 描述： | Digital Potentiometer, 4 Func, 2500ohm, 3-wire Serial Control Interface, 64 Positions, PDSO24, PLASTIC, SOIC-24 光电二极管 转换器 电阻器 |
| 文件： | 总22页 (文件大小：116K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Noise/Low Power
X9400
Quad Nonvolatile Digitally Controlled Potentiometer
FEATURES
DESCRIPTION
• Quad – Four Separate Pots
• 64 Resistor Taps/Pot
• SPI Serial Interface
• Wiper Resistance, 150Ω Typical
• Four Non-Volatile Data Registers for Each Pot
• Non-Volatile Storage of Wiper Position
• Standby Current < 1µA Max (Total Package)
The X9400 digital potentiometer contains 4 separate
10KΩ potentiometers with a digitally programmable
wiper position to one of 64 taps on each pot. The wiper
position is determined by a serial digital code that is
received on the SPI serial port that is common to all four
ports.The 63 individual resistors in each pot are all equal
creating a linear taper from one end of the pot to the
other. There are also four 6 bit non-volatile data registers
associated with each pot for storing system data and the
most recent wiper position. Powering up the device
• V
= 2.7V to 5.5V Operation
CC
V+ = 2.7V to 5.5V
V– = –2.7V to –5.5V
• 10KΩ, 2.5KΩ Total Pot Resistance
• 100 yr. Data Retention
• 24-Lead SOIC, 24-Lead TSSOP, and 24-Lead
XBGA Packages
causes the contents of R register of each pot to be
loaded into the Wiper Counter register restoring the last
known wiper position for each pot.
0
FUNCTIONAL DIAGRAM
POT 0
R0 R1
R2 R3
VH0
R0 R1
R2 R3
WIPER
VH2
WIPER
COUNTER
REGISTER
(WCR)
RESISTOR
ARRAY
POT2
COUNTER
REGISTER
(WCR)
VL0
HOLD
VL2
CS
SCK
SO
VW0
VW2
INTERFACE
AND
CONTROL
SI
8
CIRCUITRY
A0
A1
VW1
VH1
DATA
VW3
VH3
WP
R0 R1
R2 R3
R0 R1
R2 R3
WIPER
COUNTER
REGISTER
(WCR)
WIPER
COUNTER
REGISTER
(WCR)
RESISTOR
ARRAY
POT1
RESISTOR
ARRAY
POT3
VL1
VL3
Xicor, Inc. 2000 Patents Pending
7061-1.1 2/28/00 EP
Characteristics subject to change without notice 1 of 22
X9400
PIN DESCRIPTIONS
serial sequence. To pause, HOLD must be brought LOW
while SCK is LOW. To resume communication, HOLD is
brought HIGH, again while SCK is LOW. If the pause
feature is not used, HOLD should be held HIGH at all
times.
Host Interface Pins
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
Device Address (A –A )
0
1
The address inputs are used to set the least significant 2
bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with the
X9400. A maximum of 4 devices may occupy the SPI
serial bus.
Serial Input
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
Serial Clock (SCK)
Potentiometer Pins
The SCK input is used to clock data into and out of the
X9400.
V (V – V ), V (V – V )
H H0 H3 L L0 L3
The VH and VL inputs are equivalent to the terminal
connections on either end of
potentiometer.
a
mechanical
Chip Select (CS)
When CS is HIGH, the X9400 is deselected and the SO
pin is at high impedance, and (unless an internal write
cycle is underway) the device will be in the standby state.
CS LOW enables the X9400, placing it in the active
power mode. It should be noted that after a power-up, a
HIGH to LOW transition on CS is required prior to the
start of any operation.
V
(V
– V
)
W
W0
W3
The wiper outputs are equivalent to the wiper output of a
mechanical potentiometer.
Hardware Write Protect Input (WP)
The WP pin when LOW prevents nonvolatile writes to the
Wiper Counter Registers.
Hold (HOLD)
Analog Supplies (V+, V-)
HOLD is used in conjunction with the CS pin to select the
device. Once the part is selected and a serial sequence
is underway, HOLD may be used to pause the serial
communication with the controller without resetting the
The analog Supplies V+, V- are the supply voltages for
the EEPot analog section.
PIN CONFIGURATION
TSSOP
DIP/SOIC
XBGA
VCC
VL0
VH0
VW0
CS
1
2
24
23
22
21
20
19
18
17
16
15
V+
SI
1
2
24
23
22
21
20
19
18
17
16
15
WP
CS
V
1
2
3
4
VL3
VH3
VW3
A
A
V
V
V
L1
CS
1
W0
1
A
B
C
D
E
F
3
V
3
L1
W0
V
SI
W1
WP
L0
V
4
4
V
V
H1
H0
L0
A
0
5
5
V
V
W1
V
CC
V
V V
H1 SS
H0
SO
WP
SI
6
V
6
SS
CC
X9400
X9400
V
V
H2
V+
V
V-
H3
7
HOLD
SCK
VL2
V–
W2
7
V+
V
A
1
V
8
8
L3
SO HOLD V
L3
W2
VL1
VH1
VW1
9
V
V
V
9
H3
W3
0
H2
10
V
L2
VH2
V
W3
A SCK V
0
10
L2
SCK
11
12
14
13
11
12
VW2
V-
14
13
A
Top View–Bumps Down
V
HOLD
SO
SS
Characteristics subject to change without notice 2 of 22
X9400
PIN NAMES
These switches are controlled by a wiper counter register
(WCR). The six bits of the WCR are decoded to select,
and enable, one of sixty-four switches.
Symbol
SCK
Description
Serial Clock
Wiper Counter Register (WCR)
SI, SO
A -A
Serial Data
The X9400 contains four wiper counter registers, one for
each EEPOT potentiometer. The WCR is equivalent to a
serial-in, parallel-out register/counter with its outputs
decoded to select one of sixty-four switches along its
resistor array. The contents of the WCR can be altered in
four ways: it may be written directly by the host via the
write wiper counter register instruction (serial load); it
may be written indirectly by transferring the contents of
one of four associated data registers via the XFR data
register or global XFR data register instructions (parallel
load); it can be modified one step at a time by the
increment/decrement instruction. Finally, it is loaded with
the contents of its data register zero (R0) upon power-up.
Device Address
0
1
V
V
V
,
Potentiometers
(terminal equivalent)
H0– H3
V
L0– L3
Potentiometers
(wiper equivalent)
V
V
W0– W1
WP
Hardware Write Protection
Analog and Voltage Follower
Supplies
V+,V-
V
System Supply Voltage
System Ground
CC
Vss
NC
No Connection
The wiper counter register is a volatile register; that is, its
contents are lost when the X9400 is powered-down.
Although the register is automatically loaded with the
value in R0 upon power-up, this may be different from the
value present at power-down.
DEVICE DESCRIPTION
The X9400 is
a
highly integrated microcircuit
incorporating four resistor arrays and their associated
registers and counters and the serial interface logic
providing direct communication between the host and the
EEPOT potentiometers.
Data Registers
Each potentiometer has four 6-bit nonvolatile data
registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four data registers and the associated Wiper Counter
Register. All operations changing data in one of the data
registers is a nonvolatile operation and will take a
maximum of 10ms.
Serial Interface
The X9400 supports the SPI interface hardware
conventions. The device is accessed via the SI input with
data clocked in on the rising SCK. CS must be LOW and
the HOLD and WP pins must be HIGH during the entire
operation.
If the application does not require storage of multiple
settings for the potentiometer, the data registers can be
used as regular memory locations for system parameters
or user preference data.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
Array Description
Table 1. Data Register Detail
The X9400 is comprised of four resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array are
equivalent to the fixed terminals of a mechanical
(MSB)
D5
(LSB)
D0
D4
NV
D3
NV
D2
NV
D1
NV
NV
NV
potentiometer (V and V inputs).
H
L
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper (V )
W
output. Within each individual array only one switch may
be turned on at a time.
Characteristics subject to change without notice 3 of 22
X9400
Figure 1. Detailed Potentiometer Block Diagram
(One of Four Arrays)
SERIAL DATA PATH
V
H
SERIAL
BUS
INPUT
FROM INTERF ACE
CIRCUITR Y
C
O
U
N
T
REGISTER 0
REGISTER 2
REGISTER 1
8
6
PARALLEL
BUS
INPUT
E
R
WIPER
COUNTER
REGISTER
(WCR)
D
E
C
O
D
E
REGISTER 3
INC/DEC
LOGIC
IF WCR = 00[H] THEN VW = VL
UP/DN
UP/DN
IF WCR = 3F[H] THEN VW = VH
V
L
MODIFIED SCK
CLK
V
W
Write in Process
Figure 2. Identification Byte Format
The contents of the data registers are saved to
nonvolatile memory when the CS pin goes from LOW to
HIGH after a complete write sequence is received by the
device. The progress of this internal write operation can
be monitored by a write in process bit (WIP). The WIP bit
is read with a read status command.
DEVICE TYPE
IDENTIFIER
0
1
0
1
0
0
A1
A0
DEVICEADDRESS
INSTRUCTIONS
Identification (ID) Byte
Instruction Byte
The first byte sent to the X9400 from the host, following a
CS going HIGH to LOW, is called the Identification byte.
The most significant four bits of the slave address are a
device type identifier, for the X9400 this is fixed as
0101[B] (refer to Figure 2).
The next byte sent to the X9400 contains the instruction
and register pointer information.The four most significant
bits are the instruction. The next four bits point to one of
the four pots and, when applicable, they point to one of
four associated registers. The format is shown below in
Figure 3.
The two least significant bits in the ID byte select one of
four devices on the bus. The physical device address is
Figure 3. Instruction Byte Format
defined by the state of the A -A input pins. The X9400
0
1
compares the serial data stream with the address input
state; a successful compare of both address bits is
required for the X9400 to successfully continue the
REGISTER
SELECT
command sequence. The A –A inputs can be actively
0
1
I3
I2
I1
I0
R1 R0
P1
P0
driven by CMOS input signals or tied to V or V
.
CC
SS
The remaining two bits in the slave byte must be set to 0.
INSTRUCTIONS
POT SELECT
Characteristics subject to change without notice 4 of 22
X9400
The four high order bits of the instruction byte specify the
Five instructions require a three-byte sequence to
complete. These instructions transfer data between the
host and the X9400; either between the host and one of
the data registers or directly between the host and the
Wiper Counter Register.These instructions are:
operation. The next two bits (R and R ) select one of the
1
0
four registers that is to be acted upon when a register
oriented instruction is issued.The last two bits (P1 and P )
0
selects which one of the four potentiometers is to be
affected by the instruction.
• Read Wiper Counter Register - read the current wiper
position of the selected pot,
Four of the ten instructions are two bytes in length and
end with the transmission of the instruction byte. These
instructions are:
• Write Wiper Counter Register - change current wiper
position of the selected pot,
• XFR Data Register to Wiper Counter Register - This
transfers the contents of one specified Data Register to
the associated Wiper Counter Register.
• Read Data Register - read the contents of the selected
data register;
• Write Data Register - write a new value to the selected
data register.
• XFR Wiper Counter Register to Data Register - This
transfers the contents of the specified Wiper Counter
Register to the specified associated Data Register.
• Read Status -This command returns the contents of the
WIP bit which indicates if the internal write cycle is in
progress.
• Global XFR Data Register to Wiper Counter Register -
This transfers the contents of all specified Data
Registers to the associated Wiper Counter Registers.
The sequence of these operations is shown in Figure 5
and Figure 6.
• Global XFR Wiper Counter Register to Data Register -
This transfers the contents of all Wiper Counter
Registers to the specified associated Data Registers.
The final command is Increment/Decrement. It is different
from the other commands, because it’s length is
indeterminate. Once the command is issued, the master
can clock the selected wiper up and/or down in one
resistor segment steps; thereby, providing a fine tuning
The basic sequence of the two byte instructions is
illustrated in Figure 4. These two-byte instructions
exchange data between the WCR and one of the data
registers. A transfer from a data register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position.The response of the wiper to
capability to the host. For each SCK clock pulse (t
)
HIGH
while SI is HIGH, the selected wiper will move one resistor
segment towards the V terminal. Similarly, for each SCK
H
clock pulse while SI is LOW, the selected wiper will move
this action will be delayed by t
. A transfer from the
WRL
one resistor segment towards the V terminal. A detailed
L
WCR (current wiper position), to a data register is a write
to nonvolatile memory and takes a minimum of t to
illustration of the sequence and timing for this operation
are shown in Figure 7 and Figure 8.
WR
complete. The transfer can occur between one of the four
potentiometers and one of its associated registers; or it
may occur globally, where the transfer occurs between all
potentiometers and one associated register.
Characteristics subject to change without notice 5 of 22
X9400
Figure 4. Two-Byte Command Sequence
CS
SCK
SI
0
1
0
1
0
0
A1 A0
I3 I2
I1 I0 R1 R0 P1 P0
Figure 5. Three-Byte Command Sequence (Write)
CS
SCL
SI
0
0
0
1
0
1
A1 A0
I3 I2
I1 I0 R1 R0 P1 P0
0
0
D5 D4 D3 D2 D1 D0
Figure 6. Three-Byte Command Sequence (Read)
CS
SCL
SI
Don’t Care
0
0
0
1
0
1
A1 A0
I3 I2
I1 I0
R1 R0 P1 P0
S0
0
0
D5 D4 D3 D2 D1 D0
Figure 7. Increment/Decrement Command Squence
CS
SCK
SI
P1
0
1
0
1
0
0
A1 A0
I3 I2
I1 I0
0
0
P0
I
I
D
E
C
1
I
D
E
C
n
N
C
1
N
C
2
N
C
n
Characteristics subject to change without notice 6 of 22
X9400
Figure 8. Increment/Decrement Timing Limits
t
WRID
SCK
SI
VOLTAGE OUT
V
W
INC/DEC CMD ISSUED
Table 1. Instruction Set
Instruction
Instruction Set
I
I
I
I
R
R
P
P
Operation
3
2
1
0
1
0
1
0
Read the contents of the Wiper Counter
Register pointed to by P -P
Read Wiper Counter
Register
P
P
1
1
1
1
0
0
0
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
Write new value to the Wiper Counter
Register pointed to by P -P
Write Wiper Counter
Register
P
P
P
P
P
P
0
0
1
1
1
0
0
0
1
0
Read the contents of the Data Register
pointed to by P -P and R –R
R
R
Read Data Register
Write Data Register
1
1
0
0
1
0
1
0
Write new value to the Data Register
pointed to by P -P and R –R
R
R
1
0
1
0
Transfer the contents of the Data Register
pointed to by R –R to the Wiper Counter
XFR Data Register to
Wiper Counter Register
R
R
P
P
1
1
0
1
1
0
1
0
1
1
0
0
Register pointed to by P -P
1
0
Transfer the contents of the Wiper Counter
Register pointed to by P -P to the
XFR Wiper Counter
Register to Data Register
R
R
R
R
R
R
P
P
1
0
1
1
0
0
1
0
0
0
1
0
1
0
1
1
1
0
0
0
Register pointed to by R –R
1
0
Transfer the contents of all four Data
Registers pointed to by R –R to their
Global XFR Data Register
to Wiper Counter Register
0
0
1
0
respective Wiper Counter Register
Transfer the contents of all Wiper Counter
Registers to their respective data Registers
Global XFR WiperCounter
Register to Data Register
0
0
pointed to by R –R
1
0
Enable Increment/decrement of the Wiper
Counter Register pointed to by P -P
Increment/Decrement
Wiper Counter Register
P
P
0
0
0
0
1
1
0
0
1
0
0
1
1
0
Read the status of the internal write cycle,
by checking the WIP bit.
Read Status (WIP bit)
0
0
0
1
Characteristics subject to change without notice 7 of 22
X9400
Instruction Format
Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master.
(2) WPx refers to wiper position data in the Counter Register
(2) “I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
(3) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
Read Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
WCR
addresses
wiper position
(sent by X9400 on SO)
CS
CS
Falling
Edge
Rising
Edge
W W W W W W
0 0 P P P P P P
A A
P P
0
1
0
1
0
0
1
0
0
1
0
0
1
0
1
0
5
4 3 2 1 0
Write Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
WCR
addresses
Data Byte
(sent by Host on SI)
CS
CS
Falling
Edge
Rising
Edge
W W W W W W
0 P P P P P P
A A
P P
0
1
0
1
0
0
1
0
1
0
0
0
0
1
0
1
0
5
4 3 2 1 0
Read Data Register (DR)
device type
identifier
device
addresses
instruction DR and WCR
opcode addresses
Data Byte
(sent by X9400 on SO)
CS
CS
Falling
Edge
Rising
Edge
W W W W W W
0 0 P P P P P P
A A
R
1
R
0
P
1
P
0
0
1
0
1
0
0
1
0
1
1
1
0
5
4 3 2 1 0
Write Data Register (DR)
device type
identifier
device
addresses
instruction DR and WCR
Data Byte
(sent by host on SI)
opcode
addresses
CS
Falling
Edge
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
W W W W W W
0 0 P P P P P P
5 4 3 2 1 0
A A
1 0
R
1
R
0
P
1
P
0
0 1 0 1 0 0
1 1 0 0
Transfer Data Register (DR) to Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction DR and WCR
CS
Falling
Edge
CS
Rising
Edge
opcode
addresses
A A
1 0
R
1
R
0
P
1
P
0
0 1 0 1 0 0
1 1 0 1
Characteristics subject to change without notice 8 of 22
X9400
Transfer Wiper Counter Register (WCR) to Data Register (DR)
device type
identifier
device
addresses
instruction DR and WCR
CS
Falling
Edge
CS
Rising
Edge
opcode
addresses
HIGH-VOLTAGE
WRITE CYCLE
A A
1 0
R
1
R
0
P
1
P
0
0 1 0 1 0 0
1 1 1 0
Increment/Decrement Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
WCR
increment/decrement
CS
Falling
Edge
CS
Rising
Edge
addresses (sent by master on SDA)
A A
1
P P I/ I/
1 0 D D
I/ I/
D D
0
1
0
1
0
0
0
0
1
0
X X
.
.
.
.
0
Global Transfer Data Register (DR) to Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
DR
addresses
CS
Falling
Edge
CS
Rising
Edge
A A
1
R R
1 0
0
1
0
1
0
0
0
0
0
1
0 0
0
Global Transfer Wiper Counter Register (WCR) to Data Register (DR)
device type
identifier
device
addresses
instruction
opcode
DR
addresses
CS
Falling
Edge
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
A A
1 0
R R
0 0
1 0
0 1 0 1 0 0
1 0 0 0
Read Status
device type
identifier
device
addresses
instruction
opcode
wiper
addresses
Data Byte
(sent by X9400 on SO)
CS
CS
Falling
Edge
Rising
Edge
W
I
P
A A
0
1
0
1
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
Characteristics subject to change without notice 9 of 22
X9400
ABSOLUTE MAXIMUM RATINGS
COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those listed
in the operational sections of this specification) is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Temperature under bias.......................... –65°C to +135°C
Storage temperature............................... –65°C to +150°C
Voltage on SCK, SCL or any address input
with respect to V ....................................–1V to +7V
SS
Voltage on V+ (referenced to V )................................10V
SS
Voltage on V- (referenced to V )............................... -10V
SS
(V+) – (V-)......................................................................12V
Any V .............................................................................V+
H
Any V ...............................................................................V-
L
Lead temperature (soldering, 10 seconds) ..............300°C
RECOMMENDED OPERATING CONDITIONS
Temp
Commercial
Industrial
Min.
0°C
Max.
+70°C
+85°C
Device
X9400
Supply Voltage (V ) Limits
CC
5V ±10%
–40°C
X9400-2.7
2.7V to 5.5V
ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
R
Parameter
End to end resistance
Power rating
Min. Typ. Max. Units
Test Conditions
25°C, each pot
–20
+20
50
%
mW
mA
Ω
TOTAL
I
Wiper current
–3
+3
W
R
Wiper resistance
150
250
+5.5
+5.5
-4.5
-2.7
V+
Wiper Current = ± 1mA
W
X9400
+4.5
+2.7
-5.5
-5.5
V-
Vv+
Voltage on V+ Pin
Voltage on V- Pin
V
V
X9400-2.7
X9400
Vv-
X9400-2.7
V
Voltage on any V or V Pin
V
dBV
%
TERM
H
L
Noise
-120
1.6
Ref: 1kHz
Resolution
Absolute linearity (1)
Relative linearity (2)
MI(3)
MI(3)
–1
+1
V
– V
w(n)(actual)
w(n)(expected)
]
–0.2
+0.2
V – [V
w(n + 1) w(n) + MI
Temperature coefficient
±300
ppm/°C
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (V – V )/63, single pot
H
L
Characteristics subject to change without notice 10 of 22
X9400
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
V
supply current
f
= 2MHz, SO = Open,
CC
SCK
I
400
µA
CC1
(Active)
Other Inputs = V
SS
V
supply current
f
= 2MHz, SO = Open,
CC
SCK
I
1
mA
CC2
(Nonvolatile Write)
Other Inputs = V
SS
I
I
I
V
current (standby)
1
µA
µA
µA
V
SCK = SI = V , Addr. = V
SS SS
SB
CC
Input leakage current
Output leakage current
Input HIGH voltage
Input LOW voltage
Output LOW voltage
10
10
V
V
= V to V
SS CC
LI
IN
= V to V
CC
LO
OUT
SS
V
V
V
V
x 0.7
V
+ 0.5
IH
IL
CC
CC
–0.5
V
x 0.1
V
CC
0.4
V
I
= 3mA
OL
OL
ENDURANCE AND DATA RETENTION
Parameter
Minimum endurance
Data retention
Min.
Units
100,000
100
Data changes per register
years
CAPACITANCE
Symbol
Test
Max.
Units
pF
Test Conditions
(4)
OUT
Output capacitance (SO)
8
6
V
= 0V
C
OUT
(4)
IN
Input capacitance (A0, A1, SI, and SCK)
pF
V
= 0V
C
IN
POWER-UP TIMING
Symbol
Parameter
Min.
1
Max.
1
Units
ms
(5)
PUR
Power-up to initiation of read operation
Power-up to initiation of write operation
t
t
(5)
PUW
5
5
ms
(7)
CC
V
Power up ramp
0.2
50
V/msec
t V
CC
R
A.C. TEST CONDITIONS
EQUIVALENT A.C. LOAD CIRCUIT
V
x 0.1 to V x 0.9
CC
5V
2.7V
Input Pulse Levels
CC
Input rise and fall times
Input and output timing level
10ns
1533Ω
V
x 0.5
CC
SDA OUTPUT
Notes: (4) This parameter is periodically sampled and not 100%
tested
(5) t
and t
are the delays required from the time the
100pF
100pF
PUR
PUW
third (last) power supply (Vcc, V+ or V-) is stable until the
specific instruction can be issued. These parameters are
periodically sampled and not 100% tested.
(6) The power supply sequence should be V , V-, V , V+
SS
CC
with no slope reversals on V
,
CC
(7) This is not a tested or guaranteed parameter and should be
used as a guideline.
Characteristics subject to change without notice 11 of 22
X9400
AC TIMING
Symbol
Parameter
Min.
Max.
Units
MHz
ns
f
SSI/SPI clock frequency
SSI/SPI clock cycle time
SSI/SPI clock high time
SSI/SPI clock low time
Lead time
2.0
SCK
t
500
200
200
250
250
50
CYC
t
ns
WH
t
ns
WL
t
ns
LEAD
t
Lag time
ns
LAG
t
SI, SCK, HOLD and CS input setup time
SI, SCK, HOLD and CS input hold time
SI, SCK, HOLD and CS input rise time
SI, SCK, HOLD and CS input fall time
SO output disable time
ns
SU
t
50
ns
H
t
2
µs
µs
ns
RI
t
2
FI
t
0
0
500
100
DIS
t
SO output valid time
ns
V
t
SO output hold time
ns
HO
t
SO output rise time
50
50
ns
RO
t
SO output fall time
ns
FO
t
HOLD time
400
100
100
ns
HOLD
t
HOLD setup time
ns
HSU
t
HOLD hold time
ns
HH
t
HOLD low to output in High Z
HOLD high to output in Low Z
100
100
ns
HZ
t
ns
LZ
Noise suppression time constant at
SI, SCK, HOLD and CS inputs
T
I
20
ns
t
CS deselect time
2
0
0
µs
ns
ns
CS
t
WP, A0 and A1 setup time
WP, A0 and A1 hold time
WPASU
t
WPAH
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
Parameter
Typ.
Max.
Units
t
High-voltage write cycle time (store instructions)
5
10
ms
WR
Characteristics subject to change without notice 12 of 22
X9400
EEPOT TIMING
Symbol
Parameter
Min. Max. Units
t
t
Wiper response time after the third (last) power supply is stable
Wiper response time after instruction issued (all load instructions)
10
10
µs
µs
WRPO
WRL
Wiper response time from an active SCL/SCK edge (increment/decrement
instruction)
t
450
ns
WRID
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
.
Characteristics subject to change without notice 13 of 22
X9400
TIMING DIAGRAMS
Input Timing
t
CS
CS
t
t
t
LAG
LEAD
CYC
SCK
...
WH
t
RI
t
t
t
t
t
FI
WL
SU
H
...
MSB
LSB
SI
High Impedance
SO
Output Timing
CS
SCK
SO
...
...
t
t
t
DIS
V
HO
MSB
LSB
ADDR
SI
Hold Timing
CS
t
t
HH
HSU
SCK
...
t
t
FO
RO
SO
t
t
LZ
HZ
SI
t
HOLD
HOLD
Characteristics subject to change without notice 14 of 22
X9400
EEPOT Timing (for All Load Instructions)
CS
SCK
...
...
t
WRL
MSB
LSB
SI
VWx
High Impedance
SO
EEPOT Timing (for Increment/Decrement Instruction)
CS
SCK
VWx
...
t
WRID
...
ADDR
Inc/Dec
...
SI
Inc/Dec
High Impedance
SO
Write Protect and Device Address Pins Timing
(Any Instruction)
CS
t
t
WPAH
WPASU
WP
A0
A1
Characteristics subject to change without notice 15 of 22
X9400
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
+V
R
V
R
V
W
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Application Circuits
Noninverting Amplifier
Voltage Regulator
V
+
–
S
V
V
V (REG)
O
317
O
IN
R
1
R
2
I
adj
R
R
1
2
V
= (1+R /R )V
V
(REG) = 1.25V (1+R /R )+I
R
O
2
1
S
O
2
1
adj
2
Offset Voltage Adjustment
Comparator with Hysterisis
R
R
2
1
V
–
+
S
V
V
S
O
100KΩ
–
+
V
O
TL072
R
R
1
2
10KΩ
10KΩ
+12V
V
V
= {R /(R +R )} V (max)
1 1 2 O
UL
10KΩ
-12V
= {R /(R +R )} V (min)
LL
1 1 2 O
Characteristics subject to change without notice 16 of 22
X9400
Application Circuits (continued)
Attenuator
Filter
C
V
+
–
S
R
V
R
2
O
1
3
–
+
R
V
O
V
S
R
R
2
R
4
All R = 10kΩ
S
R
1
G
= 1 + R /R
2 1
V
= G V
S
O
O
fc = 1/(2πRC)
-1/2 ≤ G ≤ +1/2
Inverting Amplifier
Equivalent L-R Circuit
R
R
2
1
V
S
R
2
C
1
–
+
V
+
–
S
V
O
R
R
1
Z
IN
V
= G V
S
O
G = - R /R
2
1
3
Z
= R + s R (R + R ) C = R + s Leq
2 2 1 3 1 2
IN
(R + R ) >> R
1
3
2
Function Generator
C
R
R
1
2
–
+
–
+
R
R
}
}
A
B
frequency R , R , C
1
2
amplitude R , R
A
B
Characteristics subject to change without notice 17 of 22
X9400
PACKAGING INFORMATION
24-Lead Plastic Dual In-Line Package Type P
1.265 (32.13)
1.230 (31.24)
0.557 (14.15)
0.530 (13.46)
PIN 1 INDEX
PIN 1
0.080 (2.03)
0.065 (1.65)
1.100 (27.94)
REF.
0.162 (4.11)
0.140 (3.56)
SEATING
PLANE
0.030 (0.76)
0.015 (0.38)
0.150 (3.81)
0.125 (3.18)
0.110 (2.79)
0.090 (2.29)
0.065 (1.65)
0.040 (1.02)
0.022 (0.56)
0.014 (0.36)
0.625 (15.87)
0.600 (15.24)
0°
TYP.0.010 (0.25)
15°
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
Characteristics subject to change without notice 18 of 22
X9400
PACKAGING INFORMATION
24-Lead Plastic Small Outline Gull Wing Package Type S
0.290 (7.37)
0.299 (7.60)
0.393 (10.00)
0.420 (10.65)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.020 (0.50)
0.598 (15.20)
0.610 (15.49)
(4X) 7°
0.092 (2.35)
0.105 (2.65)
0.003 (0.10)
0.012 (0.30)
0.050 (1.27)
0.050" TYPICAL
0.010 (0.25)
0.020 (0.50)
X 45°
0.050"
TYPICAL
0° – 8°
0.009 (0.22)
0.013 (0.33)
0.420"
0.015 (0.40)
0.050 (1.27)
0.030" TYPICAL
24 PLACES
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice 19 of 22
X9400
PACKAGING INFORMATION
24-Lead Plastic, TSSOP Package Type V
.026 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.303 (7.70)
.311 (7.90)
.047 (1.20)
.0075 (.19)
.002 (.06)
.0118 (.30)
.005 (.15)
.010 (.25)
Gage Plane
0° – 8°
Seating Plane
.020 (.50)
.030 (.75)
DetailA (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice 20 of 22
X9400
24-ball BGA (X9400WC)
a
a
l
j
m
1
2
3
4
4
3
2
1
A
B
C
D
E
F
A
B
C
D
E
F
k
b
b
f
Top View (Bump Side Down)
Bottom View (Bump Side Up)
Note: Drawing not to scale
d
= Die Oridentation mark
c
e
Side View (Bump Side Down)
Millimeters
Nom.
Inches
Symbol
Min
Max
2.635
3.854
0.763
0.470
0.293
0.388
Min
Nom.
Max
Package Body Dimension X
Package Body Dimension Y
Package Height
a
b
c
d
e
f
2.575
3.794
0.697
0.444
0.253
0.360
2.605
3.824
0.750
0.457
0.273
0.374
0.10138
0.14937
0.02744
0.01748
0.00996
0.01417
0.10256
0.15055
0.02674
0.01799
0.01075
0.01472
0.10374
0.15173
0.03004
0.01850
0.01154
0.01528
Package Body Thickness
Ball Height
Ball Diameter
Total Ball Count
g
h
i
24
4
Ball Count X Axis
Ball Count Y Axis
Pins Pitch XAxis
6
j
0.5
0.5
Pins Pitch Y Axis
k
Edge to Ball Center (Corner)
Distance Along X
l
0.523
0.632
0.553
0.662
0.583
0.692
0.02057
0.02488
0.02175
0.02606
0.02293
0.02724
Edge to Ball Center (Corner)
Distance Along Y
m
Characteristics subject to change without notice 21 of 22
X9400
ORDERING INFORMATION
X9400
Y
P
T
V
V
Limits
CC
Device
Blank = 5V ±10%
–2.7 = 2.7 to 5.5V
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
Package
S24 = 24-Lead SOIC
V24 = 24-Lead TSSOP
Z24 = 24-Lead XBGA
Potentiometer Organization
Pot 0 Pot 1 Pot 2 Pot 3
W =
Y =
10KΩ 10KΩ 10KΩ 10KΩ
2.5KΩ 2.5KΩ 2.5KΩ 2.5KΩ
PART MARK CONVENTION
24 Lead XBGA
X9400WZ24I-2.7
X9400WZ24
Top Mark
XABM
XABN
X9400YZ24
XABZ
X9400YZ24I-2.7
XABY
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and
prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc.
All others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461;
4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880;
5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents
pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error
detection and correction, redundancy and back-up features to prevent such an occurence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure
to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice 22 of 22
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