X9401WB24I-2.7 [XICOR]
QUAD 10K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, BGA24, BUMP, CSP-24;
| 型号： | X9401WB24I-2.7 |
| 厂家： | 
XICOR INC. |
| 描述： | QUAD 10K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, BGA24, BUMP, CSP-24 转换器 电阻器 |
| 文件： | 总21页 (文件大小：163K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APPLICATION NOTES
A V A I L A B L E
AN99 • AN115 • AN120 • AN124 • AN133 • AN134
Low Noise/Low Power/SPI Bus
Preliminary Information
X9401
Quad, 64 Tap, Digitally Controlled Potentiometer (XDCP™)
FEATURES
DESCRIPTION
• Quad–4 separate pots, 64 taps/pot
• Nonvolatile storage of wiper position
• Four Nonvolatile Data Registers for Each Pot
• 16-bytes of EEPROM memory
The X9401 integrates 4 digitally controlled potentiome-
ters (XDCP) on a monolithic CMOS integrated
microcircuit.
The digitally controlled potentiometer is implemented
using 64 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI bus
interface. Each potentiometer has associated with it a
volatile Wiper Counter Register (WCR) and 4 nonvola-
tile Data Registers (DR0:DR3) that can be directly
written to and read by the user. The contents of the
WCR controls the position of the wiper on the resistor
array through the switches. Power up recalls the con-
tents of DR0 to the WCR.
• SPI serial interface
• R
= 10kΩ
Total
• Wiper resistance = 150Ω typical
• Standby current < 1µA (total package)
• Operating current < 400µA max.
• V
= 2.7V to 5V
CC
• Packages–24-lead TSSOP, SOIC, CSP (Chip
Scale Package)
• 100 year data retention
The XDCP can be used as a three-terminal potentiom-
eter or as a two-terminal variable resistor in a wide
variety of applications including control, parameter
adjustments, and signal processing.
BLOCK DIAGRAM
Pot 0
V
V
CC
SS
R0 R1
R2 R3
V
/R
R0 R1
R2 R3
H0 H0
Wiper
Counter
Register
(WCR)
Wiper
Counter
Register
(WCR)
V
/R
H2 H2
Resistor
Array
Pot 2
V
/R
L0 L0
HOLD
V
/R
L2 L2
CS
SCK
SO
SI
V
/R
W0 W0
V
/R
W2 W2
Interface
and
Control
8
Circuitry
A0
A1
V
/R
W1 W1
Data
V
V
/R
W3 W3
WP
R0 R1
R2 R3
R0 R1
R2 R3
V
/R
Wiper
Counter
Register
(WCR)
H1 H1
/R
Resistor
Array
Pot 1
Wiper
Counter
Register
(WCR)
H3 H3
Resistor
Array
Pot 3
V
/R
L1 L1
V
/R
L3 L3
Characteristics subject to change without notice. 1 of 21
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X9401 – Preliminary Information
PIN DESCRIPTIONS
Host Interface Pins
Serial Output (SO)
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select the
device. Once the part is selected and a serial sequence is
underway, HOLD may be used to pause the serial com-
munication with the controller without resetting the serial
sequence. To pause, HOLD must be brought LOW while
SCK is LOW. To resume communication, HOLD is
brought HIGH, again while SCK is LOW. If the pause fea-
ture is not used, HOLD should be held HIGH at all times.
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
Serial Input
Device Address (A –A )
0
1
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
The address inputs are used to set the least significant 2 bits
of the 8-bit slave address. A match in the slave address
serial data stream must be made with the address input
in order to initiate communication with the X9401. A
maximum of 4 devices may occupy the SPI serial bus.
Serial Clock (SCK)
The SCK input is used to clock data into and out of the
X9401.
Potentiometer Pins
V (V –V ), V (V –V ), R (R –R ),
H
H0 H3
L
L0 L3
H
H0
H3
Chip Select (CS)
R (R –R )
L
L0
L3
When CS is HIGH, the X9401 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9401, placing it in
the active power mode. It should be noted that after a
power-up, a HIGH to LOW transition on CS is required
prior to the start of any operation.
The V /R and V /R inputs are equivalent to the terminal
H
H
L
L
connections on either end of a mechanical potentiometer.
V
(V –V ), R (R –R
)
W3
W
W0 W3
W
W0
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.
Hardware Write Protect Input (WP)
The WP pin when LOW prevents nonvolatile writes to
the Wiper Counter Registers.
PIN CONFIGURATION
SOIC
CSP
TSSOP
1
2
3
4
NC
V
V
WP
SI
1
2
24
23
22
21
20
19
18
17
16
15
1
2
24
23
22
21
20
19
18
17
16
15
CC
/R
V
/R
CS
V
A
L3 L3
L0 L0
1
V
/R
V
V
/R
A
CS
W0 W0
L1 L1
1
A
B
C
D
E
F
/R
V
V
A
/R
V
/R
3
V
/R
W0 W0
H3 H3
3
H0 H0
L1 L1
V /R
H1 H1
V
/R
/R
V
V
V
/R
/R
SI
WP
V
/R
L0 L0
W1 W1
4
H0 H0
W3 W3
4
W0 W0
CS
V
/R
W1 W1
/R
5
5
L0 L0
0
V
V
V
/R
V
V
/R
V
SS
CC
H0 H0
H1 H1
V
SO
SS
WP
6
6
CC
X9401
X9401
SI
NC
HOLD
SCK
7
NC
V
/R
/R
7
NC
NC
H3 H3 H2 H2
V
/R
A
1
/R
W2 W2
8
8
L3 L3
HOLD V /R
W2 W2
V
/R
SO
L3 L3
V
V
/R
V
/R
H2 H2
V
/R
9
V
V
/R
9
L2 L2
L1 L1
H3 H3
V
/R
/R
/R
10
L2 L2
H2 H2
10
V
/R
W3 W3
H1 H1
V
/R
A
SCK
V /R
L2 L2
W3 W3
0
V
/R
A
14
13
SCK
14
13
V
/R
W2 W2
11
12
0
11
12
W1 W1
V
HOLD
Top View–Bumps Down
NC
SS
SO
Characteristics subject to change without notice. 2 of 21
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X9401 – Preliminary Information
PIN NAMES
These switches are controlled by a Wiper Counter
Register (WCR). The six bits of the WCR are decoded
to select, and enable, one of sixty-four switches.
Symbol
Description
Serial Clock
SCK
Wiper Counter Register (WCR)
SI, SO
Serial Data
The X9401 contains four Wiper Counter Registers,
one for each XDCP potentiometer. The WCR is equiv-
alent to a serial-in, parallel-out register/counter with its
outputs decoded to select one of sixty-four switches
along its resistor array. The contents of the WCR can
be altered in four ways: it may be written directly by the
host via the Write Wiper Counter Register instruction
(serial load); it may be written indirectly by transferring
the contents of one of four associated data registers
via the XFR Data Register or Global XFR Data Regis-
ter instructions (parallel load); it can be modified one
step at a time by the Increment/Decrement instruction.
Finally, it is loaded with the contents of its data register
zero (R0) upon power-up.
A -A
Device Address
0
1
V
V
/R –V /R
,
Potentiometers (terminal
equivalent)
H0 H0 H3 H3
/R –V /R
L0 L0 L3 L3
V
/R –V /R
Potentiometers (wiper
equivalent)
W0 W0 W1 W1
WP
Hardware Write Protection
System Supply Voltage
System Ground
V
V
CC
SS
NC
No Connection
DEVICE DESCRIPTION
The X9401 is a highly integrated microcircuit incorpo-
rating four resistor arrays and their associated regis-
ters and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9401 is powered-
down. Although the register is automatically loaded
with the value in R upon power-up, this may be differ-
0
ent from the value present at power-down. The wiper
Serial Interface
position must be stored in R to insure restoring the
0
wiper position after power-up.
The X9401 supports the SPI interface hardware con-
ventions. The device is accessed via the SI input with
data clocked in on the rising SCK. CS must be LOW
and the HOLD and WP pins must be HIGH during the
entire operation.
Data Registers
Each potentiometer has four 6-bit nonvolatile data reg-
isters. These can be read or written directly by the
host. Data can also be transferred between any of the
four data registers and the associated Wiper Counter
Register. All operations changing data in one of the
data registers is a nonvolatile operation and will take a
maximum of 10ms.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
Array Description
If the application does not require storage of multiple
settings for the potentiometer, the data registers can
be used as memory locations for system parameters
or user preference data.
The X9401 is comprised of four resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (V /R and V /R inputs).
H
H
L
L
Data Register Detail
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(V /R ) output. Within each individual array only one
(MSB)
D5
(LSB)
D0
D4
NV
D3
NV
D2
NV
D1
NV
W
W
switch may be turned on at a time.
NV
NV
Characteristics subject to change without notice. 3 of 21
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X9401 – Preliminary Information
Detailed Potentiometer Block Diagram
(One of Four Arrays)
Serial Data Path
Serial
Bus
Input
V /R
H H
From Interface
Circuitry
C
o
u
n
t
Register 0
Register 2
Register 1
8
6
Parallel
Bus
Input
e
r
Wiper
D
e
c
o
d
e
Register 3
Counter
Register
(WCR)
INC/DEC
Logic
If WCR = 00[H] then V /R = V /R
W
W
L
L
UP/DN
UP/DN
If WCR = 3F[H] then V /R = V /R
H
W
W
H
V /R
Modified SCL
L
L
CLK
V
/R
W
W
Write in Process
continue the command sequence. The A –A inputs
0 1
can be actively driven by CMOS input signals or tied to
or V
The contents of the Data Registers are saved to non-
volatile memory when the CS pin goes from LOW to
HIGH after a complete write sequence is received by
the device. The progress of this internal write opera-
tion can be monitored by a Write In Process bit (WIP).
The WIP bit is read with a Read Status command.
V
.
SS
CC
The remaining two bits in the slave byte must be set to 0.
Figure 1. Identification Byte Format
Device Type
Identifier
INSTRUCTIONS
Identification (ID) Byte
0
1
0
1
0
0
A1
A0
The first byte sent to the X9401 from the host, follow-
ing a CS going HIGH to LOW, is called the Identifica-
tion byte. The most significant four bits of the slave
address are a device type identifier, for the X9401 this
is fixed as 0101[B] (refer to Figure 1).
Device Address
Instruction Byte
The next byte sent to the X9401 contains the instruc-
tion and register pointer information. The four most
significant bits are the instruction. The next four bits
point to one of the four pots and, when applicable, they
point to one of four associated registers. The format is
shown below in Figure 2.
The two least significant bits in the ID byte select one
of four devices on the bus. The physical device
address is defined by the state of the A -A input pins.
0
1
The X9401 compares the serial data stream with the
address input state; a successful compare of both
address bits is required for the X9401 to successfully
Characteristics subject to change without notice. 4 of 21
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X9401 – Preliminary Information
Figure 2. Instruction Byte Format
Five instructions require a three-byte sequence to com-
plete. These instructions transfer data between the host
and the X9401; either between the host and one of the
data registers or directly between the host and the
Wiper Counter Register.These instructions are:
Register
Select
I3
I2
I1
I0
R1 R0
P1
P0
– Read Wiper Counter Register— read the current
wiper position of the selected pot,
Pot Select
Instructions
– Write Wiper Counter Register—change current wiper
position of the selected pot,
The four high order bits of the instruction byte specify
the operation. The next two bits (R and R ) select one
– Read Data Register—read the contents of the
selected data register;
1
0
of the four registers that is to be acted upon when a
register oriented instruction is issued. The last two bits
(P1 and P ) selects which one of the four potentiome-
– Write Data Register—write a new value to the
selected data register.
0
ters is to be affected by the instruction.
– Read Status—This command returns the contents of
the WIP bit which indicates if the internal write cycle
is in progress.
Four of the ten instructions are two bytes in length and
end with the transmission of the instruction byte. These
instructions are:
The sequence of these operations is shown in Figure 4
and Figure 5.
– XFR Data Register to Wiper Counter Register—This
transfers the contents of one specified Data Register
to the associated Wiper Counter Register.
The final command is Increment/Decrement. It is differ-
ent from the other commands, because it’s length is
indeterminate. Once the command is issued, the mas-
ter can clock the selected wiper up and/or down in one
resistor segment steps; thereby, providing a fine tuning
– XFR Wiper Counter Register to Data Register—This
transfers the contents of the specified Wiper Counter
Register to the specified associated Data Register.
capability to the host. For each SCK clock pulse (t
)
HIGH
– Global XFR Data Register to Wiper Counter Register —
This transfers the contents of all specified Data Reg-
isters to the associated Wiper Counter Registers.
while SI is HIGH, the selected wiper will move one
resistor segment towards the V /R terminal. Similarly,
H
H
for each SCK clock pulse while SI is LOW, the selected
wiper will move one resistor segment towards the V /R
terminal. A detailed illustration of the sequence and tim-
ing for this operation are shown in Figure 6 and Figure 7.
– Global XFR Wiper Counter Register to Data Register—
This transfers the contents of all Wiper Counter Reg-
isters to the specified associated Data Registers.
L
L
The basic sequence of the two byte instructions is illus-
trated in Figure 3. These two-byte instructions exchange
data between the WCR and one of the data registers. A
transfer from a data register to a WCR is essentially a
write to a static RAM, with the static RAM controlling the
wiper position. The response of the wiper to this action
will be delayed by t
. A transfer from the WCR (cur-
WRL
rent wiper position), to a data register is a write to nonvol-
atile memory and takes a minimum of t to complete.
WR
The transfer can occur between one of the four potenti-
ometers and one of its associated registers; or it may
occur globally, where the transfer occurs between all
potentiometers and one associated register.
Characteristics subject to change without notice. 5 of 21
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X9401 – Preliminary Information
Figure 3. Two-Byte Command Sequence
CS
SCK
SI
0
1
0
1
0
0
A1 A0
I3 I2
I1 I0 R1 R0 P1 P0
Figure 4. Three-Byte Command Sequence (Write)
CS
SCL
SI
0
0
0
1
0
1
A1 A0
I3 I2
I1 I0 R1 R0 P1 P0
0
0
D5 D4 D3 D2 D1 D0
Figure 5. Three-Byte Command Sequence (Read)
CS
SCL
SI
Don’t Care
0
0
0
1
0
1
A1 A0
I3 I2
I1 I0 R1 R0 P1 P0
S0
0
0
D5 D4 D3 D2 D1 D0
Figure 6. Increment/Decrement Command Sequence
CS
SCK
SI
P1
0
1
0
1
0
0
A1 A0
I3 I2
I1 I0
0
0
P0
I
I
D
E
C
1
I
D
E
C
n
N
C
1
N
C
2
N
C
n
Characteristics subject to change without notice. 6 of 21
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X9401 – Preliminary Information
Figure 7. Increment/Decrement Timing Limits
t
WRID
SCK
SI
Voltage Out
V
/R
W
W
INC/DEC CMD Issued
Table 1. Instruction Set
Instruction Set
Instruction
Read Wiper Counter Register
I
I
I
I
R
0
R
0
P
P
Operation
Read the contents of the Wiper Counter Register
3
2
1
0
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
P
P
1
0
pointed to by P -P
1
0
Write Wiper Counter Register
Read Data Register
0
0
P
P
P
P
P
P
P
P
Write new value to the Wiper Counter Register
1
1
1
1
0
0
0
0
pointed to by P -P
1
0
R
R
Read the contents of the Data Register pointed to
by P -P and R –R
1
1
1
0
0
0
1
0
1
0
Write Data Register
R
R
R
R
Write new value to the Data Register pointed to by
P -P and R –R
1
0
1
0
XFR Data Register to Wiper
Counter Register
Transfer the contents of the Data Register pointed
to by R –R to the Wiper Counter Register pointed
1
0
to by P -P
1
0
XFR Wiper Counter Register
to Data Register
1
0
1
1
0
0
1
0
0
0
1
0
R
R
R
R
R
R
P
P
Transfer the contents of the Wiper Counter Register
1
1
1
0
0
0
1
0
pointed to by P -P to the Register pointed to by
1
0
R –R
1
0
Global XFR Data Register to
Wiper Counter Register
0
0
Transfer the contents of the Data Registers pointed
to by R –R of all four pots to their respective Wiper
1
0
Counter Register
Global XFR Wiper Counter
Register to Data Register
0
0
Transfer the contents of all Wiper Counter Regis-
ters to their respective data Registers pointed to by
R –R of all four pots
1
0
Increment/Decrement Wiper
Counter Register
0
0
0
1
1
0
0
1
0
0
P
P
Enable Increment/decrement of the Wiper Counter
1
0
Register pointed to by P -P
1
0
Read Status (WIP bit)
0
0
0
1
Read the status of the internal write cycle, by
checking the WIP bit.
Characteristics subject to change without notice. 7 of 21
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X9401 – Preliminary Information
Instruction Format
Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master.
(2) WPx refers to wiper position data in the Counter Register
(3) “I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
(4) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
Read Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
WCR
addresses
wiper position
(sent by X9401 on SO)
CS
CS
Falling
Edge
Rising
Edge
W W W W W W
0 0 P P P P P P
A A
P
1
P
0
0
1
0
1
0
0
1
0
0
1
0
0
1
0
5
4 3 2 1 0
Write Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
WCR
addresses
Data Byte
(sent by Host on SI)
CS
CS
Falling
Edge
Rising
Edge
W W W W W W
0 0 P P P P P P
A A
P
1
P
0
0
1
0
1
0
0
1
0
1
0
0
0
1
0
5
4 3 2 1 0
Read Data Register (DR)
device type
identifier
device
addresses
instruction DR and WCR
opcode addresses
Data Byte
(sent by X9401 on SO)
CS
CS
Falling
Edge
Rising
Edge
W W W W W W
0 0 P P P P P P
A A
R
1
R
0
P
1
P
0
0
1
0
1
0
0
1
0
1
1
1
0
5
4 3 2 1 0
Write Data Register (DR)
device type
identifier
device
addresses
instruction DR and WCR
opcode addresses
Data Byte
(sent by host on SI)
CS
Falling
Edge
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
W W W W W W
0 P P P P P P
A A
1
R
1
R
0
P
1
P
0
0
1
0
1
0
0
1
1
0
0
0
0
5
4 3 2 1 0
Transfer Data Register (DR) to Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction DR and WCR
opcode addresses
CS
Falling
Edge
CS
Rising
Edge
A A
1
R
1
R
0
P
1
P
0
0
1
0
1
0
0
1 1 0 1
0
Characteristics subject to change without notice. 8 of 21
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X9401 – Preliminary Information
Transfer Wiper Counter Register (WCR) to Data Register (DR)
device type
identifier
device
addresses
instruction DR and WCR
opcode addresses
CS
Falling
Edge
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
A A
1
R
1
R
0
P
1
P
0
0
1
0
1
0
0
1 1 1 0
0
Increment/Decrement Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
WCR
increment/decrement
CS
Falling
Edge
CS
Rising
Edge
addresses (sent by master on SDA)
A A
1
P P I/ I/
1 0 D D
I/ I/
D D
0
1
0
1
0
0
0
0
1
0
X X
.
.
.
.
0
Global Transfer Data Register (DR) to Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
DR
addresses
CS
Falling
Edge
CS
Rising
Edge
A A
1
R R
1 0
0
1
0
1
0
0
0
0
0
1
0 0
0
Global Transfer Wiper Counter Register (WCR) to Data Register (DR)
device type
identifier
device
addresses
instruction
opcode
DR
addresses
CS
Falling
Edge
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
A A
1
R R
1 0
0
1
0
1
0
0
1
0
0
0
0 0
0
Read Status
device type
identifier
device
addresses
instruction
opcode
wiper
addresses
Data Byte
(sent by X9401 on SO)
CS
CS
Falling
Edge
Rising
Edge
W
I
P
A A
0
1
0
1
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
Characteristics subject to change without notice. 9 of 21
REV 1.9 4/13/04
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X9401 – Preliminary Information
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias.................... –65°C to +135°C
Storage temperature......................... –65°C to +150°C
Voltage on SCK, SCL or any address
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this specifica-
tion) is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect device
reliability.
input with respect to V ........................ –1V to +7V
SS
∆V = |(V –V )|......................................................5.5V
H
L
Lead temperature (soldering, 10 seconds)........ 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
Max.
+70°C
+85°C
Device
X9401
Supply Voltage (V ) Limits
CC
5V 10%
–40°C
X9401-2.7
2.7V to 5.5V
ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
Parameter
End to end resistance
Power rating
Min.
Typ.
Max.
+20
50
Unit
%
Test Condition
25°C, each pot
R
–20
TOTAL
mW
mA
I
Wiper current
–6
+6
W
R
Wiper resistance
150
500
Ω
Wiper Current = 3mA
= 0V
W
V
Voltage on any V or V Pin
V
V
V
V
SS
TERM
H
L
SS
CC
Noise
-120
1.6
dBV
%
Ref: 1kHz
Resolution
Absolute linearity (1)
Relative linearity (2)
–1
–0.2
+1
+0.2
MI(3)
MI(3)
ppm/°C
V
—V
w(n)(actual)
w(n)(expected)
]
V
—[V
w(n) + MI
w(n + 1)
Temperature coefficient of R
Ratiometric temp. coefficient
Potentiometer capacitances
300
TOTAL
20 ppm/°C
pF
C /C /C
10/10/25
0.1
See Macro model
V = V to V . Device is in
IN
stand-by mode.
H
L
W
I
R , R , R leakage current
10
µA
AL
H
L
W
SS
CC
POWER UP AND DOWN REQUIREMENTS
The are no restrictions on the power-up or power-down conditions of V
and the voltages applied to the poten-
CC
tiometer pins provided that V is always more positive than or equal to V , V , and V , i.e., V ≥ V , V , V .
CC
H
L
W
CC
H
L
W
The V power-up spec is always in effect.
CC
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used
as a potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potenti-
ometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (V –V )/63, single pot
H
L
Characteristics subject to change without notice. 10 of 21
REV 1.9 4/13/04
www.xicor.com
X9401 – Preliminary Information
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
I
V
V
supply current (active)
400
µA
f = 2MHz, SO = Open,
SCK
CC1
CC
Other Inputs = V
SS
I
supply current (nonvola-
1
1
mA
µA
f
= 2MHz, SO = Open,
CC2
CC
SCK
tile write)
Other Inputs = V
SS
I
V
current (standby)
SCK = SI = V , Addr. = V
,
SB
CC
SS
SS
CS = V
CC
I
Input leakage current
Output leakage current
Input HIGH voltage
Input LOW voltage
Output LOW voltage
10
10
µA
µA
V
V
V
= V to V
SS CC
LI
IN
I
= V to V
SS CC
LO
OUT
V
V
x 0.7
V
+ 0.5
IH
CC
CC
V
–0.5
V
x 0.1
CC
V
IL
V
0.4
V
I
= 3mA
OL
OL
ENDURANCE AND DATA RETENTION
Parameter
Minimum endurance
Data retention
Min.
100,000
100
Unit
Data changes per bit per register
years
CAPACITANCE
Symbol
Test
Output capacitance (SO)
Input capacitance (A0, A1, SI, and SCK)
Max.
Unit
pF
Test Condition
= 0V
(4)
C
8
6
V
OUT
OUT
(4)
C
pF
V
= 0V
IN
IN
POWER-UP TIMING
Symbol
Parameter
V Power-up rate
CC
Min.
Max.
Unit
V/ms
ms
(6)
t V
0.2
50
1
r
CC
(5)
t
Power-up to initiation of read operation
Power-up to initiation of write operation
PUR
(5)
t
5
ms
PUW
A.C. TEST CONDITIONS
EQUIVALENT A.C. LOAD CIRCUIT
Input pulse levels
V
x 0.1 to V x 0.9
CC
CC
SPICE Macro Model
Input rise and fall times
Input and output timing level
10ns
5V
1533Ω
R
V
x 0.5
TOTAL
CC
R
R
L
H
Notes: (4) This parameter is periodically sampled and not 100%
C
SDA
Output
C
C
L
10pF
W
L
tested
(5) t
and t
are the delays required from the time the
PUW
PUR
25pF
100pF
(last) power supply (V -) is stable until the specific
CC
10pF
instruction can be issued. These parameters are periodi-
cally sampled and not 100% tested.
R
W
(6) This is not a tested or guaranteed parameter and should
be used only as a guideline.
Characteristics subject to change without notice. 11 of 21
REV 1.9 4/13/04
www.xicor.com
X9401 – Preliminary Information
AC TIMING
Symbol
Parameter
Min.
Max.
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
f
SSI/SPI clock frequency
SSI/SPI clock cycle rime
SSI/SPI clock high rime
SSI/SPI clock low time
Lead time
2.0
SCK
CYC
t
500
200
200
250
250
50
t
WH
t
WL
t
LEAD
t
Lag time
LAG
t
SI, SCK, HOLD and CS input setup time
SI, SCK, HOLD and CS input hold time
SI, SCK, HOLD and CS input rise time
SI, SCK, HOLD and CS input fall time
SO output disable time
SU
t
50
H
t
2
RI
t
2
FI
t
0
0
500
100
DIS
t
SO output valid time
V
t
SO output hold time
HO
t
SO output rise time
50
50
RO
t
SO output fall time
FO
t
HOLD time
400
100
100
HOLD
t
HOLD setup time
HSU
t
HOLD hold time
HH
t
HOLD low to output in high Z
HOLD high to output in low Z
Noise suppression time constant at SI, SCK, HOLD and CS inputs
CS deselect time
100
100
20
HZ
t
LZ
T
I
t
2
0
0
CS
t
WP, A0 and A1 setup time
WP, A0 and A1 hold time
WPASU
t
WPAH
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol Parameter
Typ.
Max.
Unit
t
High-voltage write cycle time (store instructions)
5
10
ms
WR
XDCP TIMING
Symbol
Parameter
Min. Max. Unit
t
Wiper response time after the third (last) power supply is stable
Wiper response time after instruction issued (all load instructions)
10
10
µs
µs
ns
WRPO
t
WRL
t
Wiper response time from an active SCL/SCK edge (increment/decrement instruction)
450
WRID
Characteristics subject to change without notice. 12 of 21
REV 1.9 4/13/04
www.xicor.com
X9401 – Preliminary Information
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
TIMING DIAGRAMS
Input Timing
t
CS
CS
t
t
t
LAG
LEAD
CYC
SCK
...
WH
t
t
FI
t
RI
t
t
t
WL
SU
H
...
MSB
LSB
SI
High Impedance
SO
Output Timing
CS
SCK
SO
...
...
t
t
t
DIS
V
HO
MSB
LSB
ADDR
SI
Characteristics subject to change without notice. 13 of 21
REV 1.9 4/13/04
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X9401 – Preliminary Information
Hold Timing
CS
t
t
HH
HSU
SCK
SO
...
t
t
FO
RO
t
t
LZ
HZ
SI
t
HOLD
HOLD
XDCP Timing (for All Load Instructions)
CS
SCK
...
...
t
WRL
MSB
LSB
SI
V
/R
W
W
High Impedance
SO
XDCP Timing (for Increment/Decrement Instruction)
CS
SCK
...
t
WRID
...
V
/R
W
W
...
ADDR
Inc/Dec
SI
Inc/Dec
High Impedance
SO
Characteristics subject to change without notice. 14 of 21
REV 1.9 4/13/04
www.xicor.com
X9401 – Preliminary Information
Write Protect and Device Address Pins Timing
(Any Instruction)
CS
t
t
WPAH
WPASU
WP
A0
A1
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
+V
R
V
R
V /R
W
W
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Characteristics subject to change without notice. 15 of 21
REV 1.9 4/13/04
www.xicor.com
X9401 – Preliminary Information
Application Circuits
Noninverting Amplifier
Voltage Regulator
V
+
–
S
V
V
V (REG)
O
317
O
IN
R
1
R
2
I
adj
R
R
1
2
V
= (1+R /R )V
V
(REG) = 1.25V (1+R /R )+I
R
O
2
1
S
O
2
1
adj
2
Offset Voltage Adjustment
Comparator with Hysteresis
R
R
2
1
V
–
+
S
V
V
S
O
–
+
100KΩ
V
O
TL072
R
R
1
2
10KΩ
10KΩ
V
V
= {R /(R +R )} V (max)
1 1 2 O
UL
LL
10KΩ
= {R /(R +R )} V (min)
1
1
2
O
+5V
Attenuator
Filter
C
V
+
–
S
R
V
R
2
O
1
3
–
R
V
O
V
+
S
R
R
2
R
4
All R = 10kΩ
S
R
1
G
= 1 + R /R
2 1
V
= G V
S
O
O
fc = 1/(2pRC)
-1/2 ≤ G ≤ +1/2
Characteristics subject to change without notice. 16 of 21
REV 1.9 4/13/04
www.xicor.com
X9401 – Preliminary Information
Application Circuits (continued)
Inverting Amplifier
Equivalent L-R Circuit
R
R
2
1
V
S
R
2
C
1
–
+
V
+
–
S
V
O
R
R
1
3
Z
IN
V = G V
O
S
G = - R /R
2
1
Z
= R + s R (R + R ) C = R + s Leq
2 2 1 3 1 2
IN
(R + R ) >> R
1
3
2
Function Generator
C
R
R
1
2
–
–
+
+
R
R
}
}
A
B
frequency ∝ R , R , C
1
2
amplitude ∝ R , R
A
B
Characteristics subject to change without notice. 17 of 21
REV 1.9 4/13/04
www.xicor.com
X9401 – Preliminary Information
PACKAGING INFORMATION
24-Lead Plastic Small Outline Gull Wing Package Type S
0.393 (10.00)
0.290 (7.37)
0.299 (7.60)
0.420 (10.65)
Pin 1 Index
Pin 1
0.014 (0.35)
0.020 (0.50)
0.598 (15.20)
0.610 (15.49)
(4X) 7°
0.092 (2.35)
0.105 (2.65)
0.003 (0.10)
0.012 (0.30)
0.050 (1.27)
0.050"Typical
0.010 (0.25)
0.020 (0.50)
X 45°
0.050"
Typical
0° – 8°
0.009 (0.22)
0.013 (0.33)
0.420"
0.015 (0.40)
0.050 (1.27)
0.030" Typical
24 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 18 of 21
REV 1.9 4/13/04
www.xicor.com
X9401 – Preliminary Information
PACKAGING INFORMATION
24-Lead Plastic, TSSOP Package Type V
.026 (.65) BSC
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.303 (7.70)
.311 (7.90)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.06)
.005 (.15)
.010 (.25)
Gage Plane
(7.72)
(4.16)
0°–8°
Seating Plane
.020 (.50)
.030 (.75)
(1.78)
(0.42)
Detail A (20X)
(0.65)
ALL MEASUREMENTS ARE TYPICAL
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 19 of 21
REV 1.9 4/13/04
www.xicor.com
X9401 – Preliminary Information
PACKAGING INFORMATION
24-Bump Chip Scale Package (CSP B24)
Package Outline Drawing
a
d
f
A4 A3 A2 A1
B4 B3 B2 B1
C4 C3 C2 C1
D4 D3 D2 D1
E4 E3 E2 E1
j
b
F4 F3 F2 F1
k
m
e
l
Top View (Sample Marking)
Bottom View (Bumped Side)
Side View
e
c
Side View
Package Dimensions
Ball Matrix:
Min
Nominal Max
Millimeters
X9401W/X9401Y
Symbol
4
3
A1
2
1
Package Width
a
b
c
d
e
f
2.595
3.814
0.644
0.444
0.220
0.310
2.625
3.844
0.677
0.457
0.240
0.330
0.5
2.655
A
B
C
D
E
F
RL1
RW1
VSS
NC
CS
RW0
RL0
VCC
NC
Package Length
3.874
0.710
0.470
0.260
0.350
SI
WP
RH0
RH3
SO
A0
Package Height
RH1
RH2
HOLD
SCK
Body Thickness
Ball Height
RW2
RL2
RL3
RW3
Ball Diameter
Ball Pitch – Width
Ball Pitch – Length
Ball to Edge Spacing – Width
Ball to Edge Spacing – Length
j
k
l
0.5
0.538
0.647
0.563
0.672
0.588
0.697
m
Characteristics subject to change without notice. 20 of 21
REV 1.9 4/13/04
www.xicor.com
X9401 – Preliminary Information
ORDERING INFORMATION
X9401
Y
P
T
V
V
Limits
CC
Device
Blank = 5V 10%
–2.7 = 2.7 to 5.5V
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
Package
S24 = 24-Lead SOIC
V24 = 24-Lead TSSOP
B24 = 24 Lead CSP
Potentiometer Organization
Pot 0 Pot 1 Pot 2 Pot 3
W =
Y =
10KW 10KW 10KW 10KW
2.5KΩ 2.5KΩ 2.5KΩ 2.5KΩ
©Xicor, Inc. 2003 Patents Pending
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 21 of 21
REV 1.9 4/13/04
www.xicor.com
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