X9410WS24 [XICOR]
Dual Digitally Controlled Potentiometer; 双通道数字控制电位器
| 型号： | X9410WS24 |
| 厂家： | 
XICOR INC. |
| 描述： | Dual Digitally Controlled Potentiometer |
| 文件： | 总21页 (文件大小：124K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APPLICATION NOTES
A V A I L A B L E
AN99 • AN115 • AN120 • AN124 • AN133 • AN134 • AN135
Low Noise/Low Power/SPI Bus
X9410
Dual Digitally Controlled Potentiometer (XDCP™)
FEATURES
DESCRIPTION
• Two potentiometers in one package
• SPI serial interface
• Register oriented format
—Direct read/write/transfer wiper positions
—Store as many as four positions per
potentiometer
The X9410 integrates two digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated microcircuit.
The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI bus
interface. Each potentiometer has associated with it a
volatile Wiper Counter Register (WCR) and 4
nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the
resistor array through the switches. Power up recalls
the contents of DR0 to the WCR.
• Power supplies
—V
= 2.7V to 5.5V
CC
—V+ = 2.7V to 5.5V
—V– = –2.7V to –5.5V
• Low power CMOS
—Standby current < 1µA
• High reliability
—Endurance–100,000 data changes per bit per
register
—Register data retention–100 years
• 8-bytes of nonvolatile EEPROM memory
• 10KΩ resistor arrays
• Resolution: 64 taps each pot
• 24-lead TSSOP, 24-lead SOIC and 24-pin plastic
DIP packages
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
BLOCK DIAGRAM
Pot 0
V
V+
V-
CC
R0 R1
R2 R3
V
/R
H0 H0
Wiper
Counter
Register
(WCR)
V
SS
V
V
/R
L0 L0
HOLD
CS
SCK
SO
/R
W0 W0
Interface
and
Control
SI
8
Circuitry
A0
A1
V
V
/R
W1 W1
Pot 1
Data
WP
R0 R1
R2 R3
/R
Wiper
Counter
Register
(WCR)
H1 H1
Resistor
Array
Pot1
V
/R
L1 L1
Characteristics subject to change without notice. 1 of 21
REV 1.1 10/6/00
www.xicor.com
X9410
PIN DESCRIPTIONS
Host Interface Pins
Serial Output (SO)
V /R (V /R —V /R
)
W
W
W0 W0
W1 W1
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
Hardware Write Protect Input (WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
Serial Input
Analog Supplies (V+, V-)
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
The analog supplies V+, V- are the supply voltages for
the XDCP analog section.
PIN CONFIGURATION
Serial Clock (SCK)
DIP/SOIC
The SCK input is used to clock data into and out of the
X9410.
V
1
2
24
23
22
21
20
19
18
17
16
15
V+
CC
V
/R
NC
NC
NC
L0 L0
Chip Select (CS)
V
/R
3
H0 H0
/R
When CS is HIGH, the X9410 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9410, placing it in
the active power mode. It should be noted that after a
power-up, a HIGH to LOW transition on CS is required
prior to the start of any operation.
V
4
W0 W0
CS
A
0
5
SO
WP
SI
6
X9410
7
HOLD
SCK
A
1
8
V
/R
9
NC
NC
L1 L1
V
/R
10
H1 H1
Hold (HOLD)
V
/R
W1 W1
11
12
14
13
NC
V-
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must be
brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.
V
SS
TSSOP
SI
1
2
24
23
22
21
20
19
18
17
16
15
WP
CS
A
1
V
/R
3
V
V
V
/R
L1 L1
/R
W0 W0
V
4
/R
H1 H1
/R
H0 H0
/R
5
V
L0 L0
W1 W1
V
Device Address (A –A )
SS
V
6
0
1
CC
X9410
NC
NC
NC
7
NC
NC
NC
The address inputs are used to set the least significant
2 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9410. A maximum of 4 devices may occupy the
SPI serial bus.
8
9
10
V-
V+
SCK
11
12
14
13
A
0
HOLD
SO
Potentiometer Pins
V /R (V /R —V /R ), V /R (V /R —V /R )
H
H
H0 H0
H1 H1
L
L
L0 L0
L1 L1
The V /R and V /R inputs are equivalent to the terminal
H
H
L
L
connections on either end of a mechanical potentiometer.
Characteristics subject to change without notice. 2 of 21
REV 1.1 10/6/00
www.xicor.com
X9410
PIN NAMES
These switches are controlled by a Wiper Counter
Register (WCR). The six bits of the WCR are decoded
to select, and enable, one of sixty-four switches.
Symbol
Description
Serial Clock
SCK
S , S
Wiper Counter Register (WCR)
Serial Data
I
O
1
The X9410 contains two Wiper Counter Registers, one
for each XDCP potentiometer. The WCR is equivalent
to a serial-in, parallel-out register/counter with its
outputs decoded to select one of sixty-four switches
along its resistor array. The contents of the WCR can
be altered in four ways: it may be written directly by the
host via the Write Wiper Counter Register instruction
(serial load); it may be written indirectly by transferring
the contents of one of four associated Data Registers
via the XFR Data Register or Global XFR Data
Register instructions (parallel load); it can be modified
one step at a time by the Increment/ Decrement
instruction. Finally, it is loaded with the contents of its
Data Register zero (DR0) upon power-up.
A -A
Device Address
0
V
V
/R –V /R
,
Potentiometer Pins
(terminal equivalent)
H0 H0 H1 H1
/R –V /R
L0 L0 L1 L1
V
/R –V /R
Potentiometer Pin
(wiper equivalent)
W0 W0 W1 W1
WP
Hardware Write Protection
Analog Supplies
V+,V-
V
System Supply Voltage
System Ground
CC
V
SS
NC
No Connection
DEVICE DESCRIPTION
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9410 is powered-
down. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.
The X9410 is
a
highly integrated microcircuit
incorporating two resistor arrays and their associated
registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.
Data Registers
Serial Interface
Each potentiometer has four 6-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the
Data Registers is a nonvolatile operation and will take a
maximum of 10ms.
The X9410 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH during
the entire operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
Array Description
The X9410 is comprised of two resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (V /R and V /R inputs).
Data Register Detail
(MSB)
D5
(LSB)
D0
D4
NV
D3
NV
D2
NV
D1
NV
H
H
L
L
NV
NV
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(V /R ) output. Within each individual array only one
W
W
switch may be turned on at a time.
Characteristics subject to change without notice. 3 of 21
REV 1.1 10/6/00
www.xicor.com
X9410
Figure 1. Detailed Potentiometer Block Diagram
(One of Two Arrays)
Serial Data Path
Serial
Bus
Input
V /R
H H
From Interface
Circuitry
C
o
u
n
t
Register 0
Register 2
Register 1
8
6
Parallel
Bus
Input
e
r
Wiper
D
e
c
o
d
e
Register 3
Counter
Register
(WCR)
INC/DEC
Logic
If WCR = 00[H] then V /R = V /R
W
W
L
L
UP/DN
UP/DN
If WCR = 3F[H] then V /R = V /R
H
W
W
H
V /R
Modified SCL
L
L
CLK
V
/R
W
W
Write in Process
required for the X9410 to successfully continue the
command sequence. The A –A inputs can be actively
0
1
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW
to HIGH after a complete write sequence is received by
the device. The progress of this internal write operation
can be monitored by a Write In Process bit (WIP). The
WIP bit is read with a Read Status command.
driven by CMOS input signals or tied to V or V
.
CC
SS
The remaining two bits in the ID byte must be set to 0.
Figure 2. Identification Byte Format
Device Type
Identifier
INSTRUCTIONS
Identification (ID) Byte
0
1
0
1
0
0
A1
A0
The first byte sent to the X9410 from the host, following
a CS going HIGH to LOW, is called the Identification
byte. The most significant four bits of the slave address
are a device type identifier, for the X9410 this is fixed
as 0101[B] (refer to Figure 2).
Device Address
Instruction Byte
The next byte sent to the X9410 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next four
bits point to one of the two pots and when applicable
they point to one of four associated registers. The
format is shown below in Figure 3.
The two least significant bits in the ID byte select one of
four devices on the bus. The physical device address is
defined by the state of the A -A input pins. The X9410
0
1
compares the serial data stream with the address input
state; a successful compare of both address bits is
Characteristics subject to change without notice. 4 of 21
REV 1.1 10/6/00
www.xicor.com
X9410
Figure 3. Instruction Byte Format
is a write to nonvolatile memory and takes a minimum
of t to complete. The transfer can occur between
one of the two potentiometers and one of its associated
registers; or it may occur globally, where the transfer
occurs between both potentiometers and one
associated register.
WR
Register
Select
I3
I2
I1
I0
R1 R0
0
P0
Five instructions require a three-byte sequence to
complete. These instructions transfer data between the
host and the X9410; either between the host and one
of the data registers or directly between the host and
the Wiper Counter Register.These instructions are:
Pot Select
Instructions
The four high order bits of the instruction byte specify
the operation. The next two bits (R and R ) select one
1
0
of the four registers that is to be acted upon when a
– Read Wiper Counter Register—read the current
wiper position of the selected pot,
register oriented instruction is issued. The last bit (P )
0
selects which one of the two potentiometers is to be
affected by the instruction.
– Write Wiper Counter Register—change current wiper
position of the selected pot,
Four of the ten instructions are two bytes in length and
end with the transmission of the instruction byte. These
instructions are:
– Read Data Register—read the contents of the
selected data register;
– Write Data Register—write a new value to the
selected data register.
– XFR Data Register to Wiper Counter Register—This
transfers the contents of one specified Data Register
to the associated Wiper Counter Register.
– Read Status—This command returns the contents of
the WIP bit which indicates if the internal write cycle
is in progress.
– XFR Wiper Counter Register to Data Register—This
transfers the contents of the specified Wiper Counter
Register to the specified associated Data Register.
The sequence of these operations is shown in Figure 5
and Figure 6.
– Global XFR Data Register to Counter Register—This
transfers the contents of both specified Data Registers
to the associated Wiper Counter Registers.
The final command is Increment/Decrement. It is
different from the other commands because it’s length
is indeterminate. Once the command is issued, the
master can clock the selected wiper up and/or down in
one resistor segment steps, thereby providing a fine
tuning capability to the host. For each SCK clock pulse
– Global XFR Wiper Counter Register to Data Register—
This transfers the contents of both Wiper Counter
Registers to the specified associated Data Registers.
The basic sequence of the two byte instructions is
illustrated in Figure 4. These two-byte instructions
exchange data between the WCR and one of the data
registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
(t
) while SI is HIGH, the selected wiper will move
HIGH
one resistor segment towards the V /R terminal.
Similarly, for each SCK clock pulse while SI is LOW, the
selected wiper will move one resistor segment towards
the V /R terminal. A detailed illustration of the
sequence and timing for this operation are shown in
Figures 7-8.
H
H
L
L
wiper to this action will be delayed by t
. A transfer
WRL
from the WCR (current wiper position), to a data register
Characteristics subject to change without notice. 5 of 21
REV 1.1 10/6/00
www.xicor.com
X9410
Figure 4. Two-Byte Instruction Sequence
CS
SCK
SI
0
1
0
1
0
0
A1 A0 I3 I2
I1 I0 R1 R0
0
P0
Figure 5. Three-Byte Instruction Sequence (Write)
CS
SCL
SI
0
0
0
1
0
1
A1 A0
I3 I2
I1 I0 R1 R0
0
P0
0
0
D5 D4 D3 D2 D1 D0
Figure 6. Three-Byte Instruction Sequence (Read)
CS
SCL
SI
Don’t Care
0
0
0
1
0
1
A1 A0
I3 I2
I1 I0 R1 R0
0
P0
S0
0
0
D5 D4 D3 D2 D1 D0
Figure 7. Increment/Decrement Instruction Sequence
CS
SCK
SI
0
1
0
1
0
0
A1 A0
I3 I2
I1 I0
0
0
0
P0
I
I
D
E
C
1
I
D
E
C
n
N
C
1
N
C
2
N
C
n
Characteristics subject to change without notice. 6 of 21
REV 1.1 10/6/00
www.xicor.com
X9410
Figure 8. Increment/Decrement Timing Limits
t
WRID
SCK
SI
Voltage Out
V
/R
W
W
INC/DEC CMD Issued
Table 1. Instruction Set
Instruction
Instruction Set
I
I
I
I
R
R
P
P
Operation
Read the contents of the Wiper Counter Register
pointed to by P
3
2
1
0
1
0
1
0
Read Wiper Counter
Register
1
1
1
1
1
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
0
0
P
0
0
Write Wiper Counter
Register
0
0
0
0
0
0
P
P
P
P
Write new value to the Wiper Counter Register
pointed to by P
0
0
0
0
0
Read Data Register
R
R
Read the contents of the Data Register pointed to
by P and R –R
1
1
1
0
0
0
0
1
0
Write Data Register
R
R
R
R
Write new value to the Data Register pointed to
by P and R –R
0
1
0
XFR Data Register to
Wiper Counter Register
Transfer the contents of the Data Register pointed
to by R –R to the Wiper Counter Register pointed
1
0
0
to by P
XFR Wiper Counter
Register to Data Register
1
0
1
1
0
0
1
0
0
0
1
0
R
R
R
R
R
R
0
0
0
P
Transfer the contents of the Wiper Counter
Register pointed to by P to the Register pointed
1
1
1
0
0
0
0
0
to by R –R
1
0
Global XFR Data Register
to Wiper Counter Register
0
Transfer the contents of the Data Registers
pointed to by R –R of both pots to their
1
0
respective Wiper Counter Register
Global XFR Wiper
Counter Register to Data
Register
0
Transfer the contents of all Wiper Counter
Registers to their respective data Registers
pointed to by R –R of both pots
1
0
Increment/Decrement
Wiper Counter Register
0
0
0
1
1
0
0
1
0
0
0
0
P
Enable Increment/decrement of the Wiper
Counter Register pointed to by P
0
0
Read Status (WIP bit)
0
0
1
Read the status of the internal write cycle, by
checking the WIP bit.
Characteristics subject to change without notice. 7 of 21
REV 1.1 10/6/00
www.xicor.com
X9410
Instruction Format
Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master.
(2) WPx refers to wiper position data in the Counter Register
(2) “I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
(3) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
Read Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
WCR
addresses
wiper position
(sent by X9410 on SO)
CS
CS
Falling
Edge
Rising
Edge
W W W W W W
0 0 P P P P P P
A A
P
0
0
1
0
1
0
0
1
0
0
1
0
0
0
1
0
5
4 3 2 1 0
Write Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
WCR
addresses
Data Byte
(sent by Host on SI)
CS
CS
Falling
Edge
Rising
Edge
W W W W W W
0 P P P P P P
A A
P
0
0
1
0
1
0
0
1
0
1
0
0
0
0
0
1
0
5
4 3 2 1 0
Read Data Register (DR)
device type
identifier
device
addresses
instruction DR and WCR
opcode addresses
Data Byte
(sent by X9410 on SO)
CS
CS
Falling
Edge
Rising
Edge
W W W W W W
0 0 P P P P P P
A A
R
1
R
0
P
0
0
1
0
1
0
0
1
0
1
1
0
1
0
5
4 3 2 1 0
Write Data Register(DR)
device type
identifier
device
addresses
instruction DR and WCR
Data Byte
(sent by host on SI)
opcode
addresses
CS
Falling
Edge
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
W W W W W W
0 0 P P P P P P
5 4 3 2 1 0
A A
1 0
R
1
R
0
0
P
0
0 1 0 1 0 0
1 1 0 0
Transfer Data Register (DR) to Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction DR and WCR
CS
Falling
Edge
CS
Rising
Edge
opcode
addresses
A A
1 0
R
1
R
0
0
P
0
0 1 0 1 0 0
1 1 0 1
Characteristics subject to change without notice. 8 of 21
REV 1.1 10/6/00
www.xicor.com
X9410
Transfer Wiper Counter Register (WCR) to Data Register (DR)
device type
identifier
device
addresses
instruction DR and WCR
opcode addresses
CS
Falling
Edge
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
D D
R
R
0
P
0
0 1 0 1 0 0 A A 1 1 1 0
1 0
0
1
Increment/Decrement Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
WCR
increment/decrement
CS
Falling
Edge
CS
Rising
Edge
addresses (sent by master on SDA)
A A
1
P
I/ I/
I/ I/
D D
0
1
0
1
0
0
0
0
1
0
X X
0
.
.
.
.
0
0 D D
Global Transfer Data Register (DR) to Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
DR
addresses
CS
Falling
Edge
CS
Rising
Edge
A A
1
R R
1 0
0
1
0
1
0
0
0
0
0
1
0 0
0
Global Transfer Wiper Counter Register (WCR) to Data Register (DR)
device type
identifier
device
addresses
instruction
opcode
DR
addresses
CS
Falling
Edge
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
A A
1 0
R R
0 0
1 0
0 1 0 1 0 0
1 0 0 0
Read Status
device type
identifier
device
addresses
instruction
opcode
wiper
addresses
Data Byte
(sent by X9410 on SO)
CS
CS
Falling
Edge
Rising
Edge
W
I
P
A A
0
1
0
1
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
Characteristics subject to change without notice. 9 of 21
REV 1.1 10/6/00
www.xicor.com
X9410
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias ....................–65°C to +135°C
Storage temperature .........................–65°C to +150°C
Voltage on SCK, SCL or any address
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this
specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
input with respect to V .........................–1V to +7V
SS
Voltage on V+ (referenced to V ) ........................ 10V
SS
Voltage on V- (referenced to V ).........................-10V
SS
(V+) – (V-).............................................................. 10V
Any V /R ............................................................... V+
H
H
Any V /R ................................................................. V-
L
L
Lead temperature (soldering, 10 seconds).........300°C
I
(10 seconds) ............................................... ±12mA
W
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
Max.
+70°C
+85°C
Device
X9410
Supply Voltage (V ) Limits
CC
5V ±10%
–40°C
X9410-2.7
2.7V to 5.5V
ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
R
Parameter
End to end resistance
Power rating
Min.
Typ.
Max. Unit
Test Conditions
±20
50
%
mW
mA
Ω
TOTAL
25°C, each pot
I
Wiper current
±6
W
R
Wiper resistance
150
40
250
100
+5.5
+5.5
-4.5
-2.7
V+
Wiper Current = ± 1mA, V = 3V
CC
W
Ω
Wiper Current = ± 1mA, V = 5V
CC
Vv+
Vv-
Voltage on V+ pin
Voltage on V- pin
X9410
+4.5
+2.7
-5.5
-5.5
V-
V
X9410-2.7
X9410
V
X9410-2.7
V
Voltage on any V /R or V /R pin
V
dBV
%
TERM
H
H
L
L
Noise
Resolution (4)
-140
1.6
Ref: 1kHz
Absolute linearity (1)
Relative linearity (2)
±1
MI(3)
MI(3)
ppm/°C
V
—V
w(n)(actual)
w(n)(expected)
]
±0.2
V
—[V
w(n) + MI
w(n + 1)
Temperature coefficient of R
±300
TOTAL
Ratiometric Temperature Coefficient
Potentiometer Capacitances
±20 ppm/°C
pF
C /C /C
W
10/10/25
See Circuit #3
H
L
Notes: (1) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used
as a potentiometer.
(2) Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a poten-
tiometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (V –V )/63, single pot
H
L
(4) Individual array resolution.
Characteristics subject to change without notice. 10 of 21
REV 1.1 10/6/00
www.xicor.com
X9410
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
I
V
V
supply current (active)
400
µA
f = 2MHz, SO = Open,
SCK
CC1
CC
Other Inputs = V
SS
I
supply current (nonvolatile
1
mA
f
= 2MHz, SO = Open,
CC2
CC
SCK
write)
Other Inputs = V
SS
I
V
current (standby)
1
µA
µA
µA
V
SCK = SI = V , Addr. = V
SS SS
SB
CC
I
Input leakage current
Output leakage current
Input HIGH voltage
Input LOW voltage
Output LOW voltage
10
10
V
V
= V to V
SS CC
LI
IN
I
= V to V
SS CC
LO
OUT
V
V
x 0.7
V
+ 0.5
IH
CC
CC
V
–0.5
V
x 0.1
CC
V
IL
V
0.4
V
I
= 3mA
OL
OL
ENDURANCE AND DATA RETENTION
Parameter
Minimum endurance
Data retention
Min.
100,000
100
Unit
Data changes per bit per register
Years
CAPACITANCE
Symbol
Test
Max.
Unit
pF
Test Conditions
= 0V
(5)
OUT
C
Output capacitance (SO)
8
6
V
OUT
(5)
IN
C
Input capacitance (A0, A1, SI, and SCK)
pF
V
= 0V
IN
POWER-UP TIMING
Symbol
Parameter
Min.
1
Max.
1
Unit
ms
(6)
PUR
t
Power-up to initiation of read operation
Power-up to initiation of write operation
(6)
PUW
t
5
5
ms
t V
V
Power up ramp
0.2
50
V/msec
R CC
CC
POWER-UP AND POWER-DOWN
EQUIVALENT A.C. LOAD CIRCUIT
There are no restrictions on the power-up or power-
5V
2.7V
down sequencing of the bias supplies V , V+, and V–
CC
provided that all three supplies reach their final values
within 1msec of each other. However, at all times, the
voltages on the potentiometer pins must be less than
V+ and more than V–. The recall of the wiper position
from nonvolatile memory is not in effect until all
supplies reach their final value.
1533Ω
SDA Output
100pF
100pF
Characteristics subject to change without notice. 11 of 21
REV 1.1 10/6/00
www.xicor.com
X9410
A.C. TEST CONDITIONS
Test Circuit #3 SPICE Macro Model
Input pulse levels
V
x 0.1 to V x 0.9
CC
CC
R
TOTAL
Input rise and fall times
Input and output timing level
10ns
R
R
L
H
C
V
x 0.5
L
CC
C
H
C
W
10pF
Notes: (5) This parameter is periodically sampled and not 100%
tested
10pF
25pF
(6) t
and t
are the delays required from the time the
PUW
PUR
third (last) power supply (V , V+ or V-) is stable until the
CC
specific instruction can be issued. These parameters are
periodically sampled and not 100% tested.
R
W
AC TIMING
Symbol
Parameter
Min. Max.
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
f
SSI/SPI clock frequency
SSI/SPI clock cycle time
SSI/SPI clock high time
SSI/SPI clock low time
Lead time
2.0
SCK
CYC
t
500
200
200
250
250
50
t
WH
t
WL
t
LEAD
t
Lag time
LAG
t
SI, SCK, HOLD and CS input setup time
SI, SCK, HOLD and CS input hold time
SI, SCK, HOLD and CS input rise time
SI, SCK, HOLD and CS input fall time
SO output disable time
SU
t
50
H
t
2
RI
t
2
FI
t
0
0
500
100
DIS
t
SO output valid time
V
t
SO output hold time
HO
t
SO output rise time
50
50
RO
t
SO output fall time
FO
t
HOLD time
400
100
100
HOLD
t
HOLD setup time
HSU
t
HOLD hold time
HH
t
HOLD low to output in high Z
HOLD high to output in low Z
100
100
20
HZ
t
LZ
T
Noise suppression time constant at SI, SCK, HOLD and CS inputs
CS deselect time
I
t
2
0
0
CS
WPASU
t
WP, A0 and A1 setup time
t
WP, A0 and A1 hold time
WPAH
Characteristics subject to change without notice. 12 of 21
REV 1.1 10/6/00
www.xicor.com
X9410
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
Parameter
Typ.
Max.
Unit
t
High-voltage write cycle time (store instructions)
5
10
ms
WR
XDCP TIMING
Symbol
Parameter
Min. Max. Unit
t
Wiper response time after the third (last) power supply is stable
Wiper response time after instruction issued (all load instructions)
10
10
µs
µs
ns
WRPO
t
WRL
t
Wiper response time from an active SCL/SCK edge (increment/decrement instruction)
450
WRID
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
TIMING DIAGRAMS
Input Timing
t
CS
CS
t
t
t
LAG
LEAD
CYC
SCK
...
WH
t
t
FI
t
RI
t
t
t
WL
SU
H
...
MSB
LSB
SI
High Impedance
SO
Characteristics subject to change without notice. 13 of 21
REV 1.1 10/6/00
www.xicor.com
X9410
Output Timing
CS
SCK
SO
...
...
t
t
t
DIS
V
HO
MSB
LSB
ADDR
SI
Hold Timing
CS
t
t
HH
HSU
SCK
SO
...
t
t
FO
RO
t
t
LZ
HZ
SI
t
HOLD
HOLD
XDCP Timing (for All Load Instructions)
CS
SCK
...
...
t
WRL
MSB
LSB
SI
V
/R
W
W
High Impedance
SO
Characteristics subject to change without notice. 14 of 21
REV 1.1 10/6/00
www.xicor.com
X9410
XDCP Timing (for Increment/Decrement Instruction)
CS
SCK
...
t
WRID
V
/R
...
...
W
W
ADDR
Inc/Dec
SI
Inc/Dec
High Impedance
SO
Write Protect and Device Address Pins Timing
(Any Instruction)
CS
t
t
WPAH
WPASU
WP
A0
A1
Characteristics subject to change without notice. 15 of 21
REV 1.1 10/6/00
www.xicor.com
X9410
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
V
R
V
R
V
/R
W
W
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Application Circuits
Noninverting Amplifier
Voltage Regulator
V
+
–
S
V
V
V (REG)
O
317
O
IN
R
1
R
2
I
adj
R
R
1
2
V
= (1+R /R )V
V
(REG) = 1.25V (1+R /R )+I
R
adj
O
2
1
S
O
2
1
2
Offset Voltage Adjustment
Comparator with Hysteresis
R
R
2
1
V
–
+
S
V
V
S
O
100KΩ
–
+
V
O
TL072
R
R
1
2
10KΩ
10KΩ
+12V
V
V
= {R /(R +R )} V (max)
1 1 2 O
UL
LL
10KΩ
-12V
= {R /(R +R )} V (min)
1
1
2
O
Characteristics subject to change without notice. 16 of 21
REV 1.1 10/6/00
www.xicor.com
X9410
Application Circuits (continued)
Attenuator
Filter
C
V
+
–
S
R
R
1
2
–
R
V
O
V
+
S
R
3
R
2
R
4
All R = 10kΩ
S
R
1
G
= 1 + R /R
2 1
V
= G V
S
O
O
fc = 1/(2πRC)
-1/2 ≤ G ≤ +1/2
Inverting Amplifier
Equivalent L-R Circuit
R
R
2
1
V
S
R
2
C
1
–
+
V
+
–
S
V
O
R
R
1
3
Z
IN
V
= G V
S
O
G = -R /R
2
1
Z
= R + s R (R + R ) C = R + s Leq
2 2 1 3 1 2
IN
(R + R ) >> R
1
3
2
Function Generator
C
R
R
1
2
–
+
–
+
R
R
}
}
A
B
frequency R , R , C
1
2
amplitude R , R
A
B
Characteristics subject to change without notice. 17 of 21
REV 1.1 10/6/00
www.xicor.com
X9410
PACKAGING INFORMATION
24-Lead Plastic Dual In-Line Package Type P
1.265 (32.13)
1.230 (31.24)
0.557 (14.15)
0.530 (13.46)
Pin 1 Index
Pin 1
0.080 (2.03)
0.065 (1.65)
1.100 (27.94)
Ref.
0.162 (4.11)
0.140 (3.56)
Seating
Plane
0.030 (0.76)
0.015 (0.38)
0.150 (3.81)
0.125 (3.18)
0.110 (2.79)
0.090 (2.29)
0.065 (1.65)
0.040 (1.02)
0.022 (0.56)
0.014 (0.36)
0.625 (15.87)
0.600 (15.24)
0°
Typ. 0.010 (0.25)
15°
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
Characteristics subject to change without notice. 18 of 21
REV 1.1 10/6/00
www.xicor.com
X9410
PACKAGING INFORMATION
24-Lead Plastic Small Outline Gull Wing Package Type S
0.393 (10.00)
0.290 (7.37)
0.299 (7.60)
0.420 (10.65)
Pin 1 Index
Pin 1
0.014 (0.35)
0.020 (0.50)
0.598 (15.20)
0.610 (15.49)
(4X) 7°
0.092 (2.35)
0.105 (2.65)
0.003 (0.10)
0.012 (0.30)
0.050 (1.27)
0.050"Typical
0.010 (0.25)
0.020 (0.50)
X 45°
0.050"
Typical
0° – 8°
0.009 (0.22)
0.013 (0.33)
0.420"
0.015 (0.40)
0.050 (1.27)
0.030" Typical
24 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 19 of 21
REV 1.1 10/6/00
www.xicor.com
X9410
PACKAGING INFORMATION
24-Lead Plastic, TSSOP Package Type V
.026 (.65) BSC
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.303 (7.70)
.311 (7.90)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.06)
.005 (.15)
.010 (.25)
Gage Plane
(7.72)
(4.16)
0°–8°
Seating Plane
.020 (.50)
.030 (.75)
(1.78)
(0.42)
Detail A (20X)
(0.65)
ALL MEASUREMENTS ARE TYPICAL
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 20 of 21
REV 1.1 10/6/00
www.xicor.com
X9410
Ordering Information
X9410
Y
P
T
V
V
Limits
CC
Device
Blank = 5V ±10%
–2.7 = 2.7 to 5.5V
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
Package
P24 = 24-Lead Plastic DIP
S24 = 24-Lead SOIC
V24 = 24-Lead TSSOP
Potentiometer Organization
Pot 0 Pot 1
W =
10KΩ 10KΩ
©Xicor, Inc. 2000 Patents Pending
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 21 of 21
REV 1.1 10/6/00
www.xicor.com
相关型号：
X9410WS24-2.7T1
DUAL 10K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO24, PLASTIC, SOIC-24
RENESAS
X9410WS24I-2.7T1
DUAL 10K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO24, PLASTIC, SOIC-24
RENESAS
X9410WS24IT1
DUAL 10K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO24, 0.300 INCH, PLASTIC, MS-013AD, SOIC-24
RENESAS
X9410WS24IT1
Digital Potentiometer, 2 Func, 10000ohm, 3-wire Serial Control Interface, 64 Positions, CMOS, PDSO24, PLASTIC, SOIC-24
XICOR
X9410WS24IZ
DUAL 10K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO24, 0.300 INCH, GREEN, PLASTIC, MS-013AD, SOIC-24
RENESAS
©2020 ICPDF网 联系我们和版权申明