X9428UPM-2.7 [XICOR]
Digital Potentiometer, 1 Func, 50000ohm, 2-wire Serial Control Interface, 64 Positions, CMOS, PDIP16, PLASTIC, DIP-16;
| 型号： | X9428UPM-2.7 |
| 厂家： | 
XICOR INC. |
| 描述： | Digital Potentiometer, 1 Func, 50000ohm, 2-wire Serial Control Interface, 64 Positions, CMOS, PDIP16, PLASTIC, DIP-16 光电二极管 转换器 电阻器 |
| 文件： | 总16页 (文件大小：79K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Noise/Low Power
Advanced Information
X9428
XDCP™ Digitally Controlled Potentiometer
FEATURES
DESCRIPTION
• Two-Wire Serial Interface
• Hardware Write Protection, WP
• Register Oriented Format
—Directly Read/Write Wiper Position
—Store as Many as Four Positions
• Power Supplies
The X9428 nonvolatile XDCP, digitally controlled
potentiometer contains a resistor array, composed of
63 resistive elements. Between each element and at
either end are tap points accessible to the wiper ele-
ments. The position of the wiper element on the array
is controlled by the user through the two wire serial
bus interface.
—VCC = 2.7V to 5.5V
—V+ = 2.7V to 5.5V
—V– = –2.7V to –5.5V
• Direct Write Cell
—Endurance - 100,000 Data Changes per
Register
—Register Data Retention - 100 years
• 16 Bytes of E2PROM memory
• 3 Resistor Array Values
—2K Ohms to 50K Ohms Mask Programmable
• Resolution: 64 Taps each Pot
• 24-Pin Plastic DIP, 24-Lead TSSOP and
24-Lead SOIC Packages
The resistor array has associated with it a nonvolatile
control latch and four 6 bit data registers that can be
directly written and read by the user. The contents of
the control latch controls the position of the resistor
array/wiper.
• Low Power CMOS
—Standby Current < 1µA
FUNCTIONAL DIAGRAM
R0 R1
VH
WIPER
COUNTER
REGISTER
(WCR)
VL
R2 R3
SCL
VW
SDA
A0
A1
A2
A3
INTERFACE
AND
CONTROL
CIRCUITRY
8
DATA
Xicor, Inc. 1994, 1995, 1996 Patents Pending
70290-1.1 9/23/99 EP
Characteristics subject to change without notice
1
X9428
PIN DESCRIPTIONS
Analog Supply V+, V-
The Analog Supply V+, V- are the supply voltages for
the XDCP analog section.
Host Interface Pins
Serial Clock (SCL)
The SCL input is used to clock data into and out of the
X9428.
PIN CONFIGURATION
DIP/SOIC
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical val-
ues, refer to the guidelines for calculating typical val-
ues on the bus pull-up resistors graph.
V+
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
A2
NC
A0
V
V
L
NC
A1
H
V
W
SCL
NC
V–
SDA
WP
X9428
Device Address (A –A )
0
3
V
SS
The Address inputs are used to set the least signifi-
cant 4 bits of the 8-bit slave address. A match in the
slave address serial data stream must be made with
the Address input in order to initiate communication
with the X9428. A maximum of 16 devices may occupy
the 2-wire serial bus.
PIN NAMES
Symbol
SCL
Description
Serial Clock
Serial Data
Potentiometer Pins
SDA
V (V – V ), V (V – V )
L1
H
H0
H1
L
L0
A0-A2
Device Address
The VH and VL inputs are equivalent to the terminal
connections on either end of a mechanical potentiom-
eter.
Potentiometers
V , V
H
L
(terminal equivalent)
Potentiometers
V
W
V
(V
– V )
W1
(Wiper equivalent)
W
W0
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer and the non-inverting
input of the voltage follower.
WP
Hardware Write Protection
Analog and Voltage Follower
Supplys
V+,V-
VCC
Vss
NC
System Supply Voltage
System Ground
Hardware Write Protect Input WP
The WP pin when low prevents nonvolatile writes to
the wiper and voltage follower control latchs.
No Connection
2
X9428
PRINCIPLES OF OPERATION
Array Description
The X9428 is comprised a resistor array containing 63
discrete resistive segments that are connected in
series. The physical ends of each array are equivalent
to the fixed terminals of a mechanical potentiometer
The X9428 is a highly integrated microcircuit incorpo-
rating a resistor array and associated registers and
counters and the serial interface logic providing direct
communication between the host and XDCP.
(V and V inputs).
H
L
Serial Interface
At both ends of the array and between each resistor
segment is a CMOS switch connected to the wiper
The X9428 supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device
as the receiver. The device controlling the transfer is a
master and the device being controlled is the slave.
The master will always initiate data transfers and pro-
vide the clock for both transmit and receive opera-
tions. Therefore, the X9428 will be considered a slave
device in all applications.
(V ) output. Within the array only one switch may be
W
turned on at a time. These switches are controlled by
a nonvolatile control latch (NCL). The six bits of the
NCL are decoded to select, and enable, one of sixty-
four switches.
The NCL may be written directly, or it can be changed
by transferring the contents of one of four associated
data registers into the NCL. These data registers and
the NCL can be read and written by the host system.
Clock and Data Conventions
Data states on the SDA line can change only during
Device Addressing
SCL LOW periods (t
). SDA state changes during
LOW
SCL HIGH are reserved for indicating start and stop
conditions.
Following a start condition the master must output the
address of the slave it is accessing. The most signifi-
cant four bits of the slave address are the device type
identifier (refer to Figure 1 below). For the X9428 this
is fixed as 0101[B].
Start Condition
All commands to the X9428 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (t
). The X9428 continuously
HIGH
Figure 1. Slave Address
monitors the SDA and SCL lines for the start condition
and will not respond to any command until this condi-
tion is met.
DEVICE TYPE
IDENTIFIER
Stop Condition
0
1
0
1
A3
A2
A1
A0
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA while
SCL is HIGH.
DEVICE ADDRESS
Acknowledge
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.
The next four bits of the slave address are the device
address. The physical device address is defined by
the state of the A0-A2 inputs. The X9428 compares
the serial data stream with the address input state; a
successful compare of all four address bits is required
for the X9428 to respond with an acknowledge. The
A –A inputs can be actively driven by CMOS input
0
2
signals or tied to V or V
.
CC
SS
The X9428 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the com-
mand byte. If the command is followed by a data byte
the X9428 will respond with a final acknowledge.
3
X9428
Acknowledge Polling
Instruction Structure
The disabling of the inputs, during the internal non-vol-
atile write operation, can be used to take advantage of
the typical 5ms E2PROM write cycle time. Once the
stop condition is issued to indicate the end of the non-
volatile write command the X9428 initiates the internal
write cycle. ACK polling can be initiated immediately.
This involves issuing the start condition followed by
the device slave address. If the X9428 is still busy with
the write operation no ACK will be returned. If the
X9428 has completed the write operation an ACK will
be returned and the master can then proceed with the
next operation.
The next byte sent to the X9428 contains the instruc-
tion and register pointer information as shown in Fig-
ure 2.
Figure 2. Instruction Byte Format
REGISTER
SELECT
I3
I2
I1
I0
R1
R0
X
X
RESERVED
INSTRUCTIONS
Flow 1. ACK Polling Sequence
The four high order bits define the instruction. The
next two bits (R1 and R0) select one of the four regis-
ters that is to be acted upon when a register oriented
instruction is issued. The last two bits are reserved
and not used.
NONVOLATILE WRITE
COMMAND COMPLETED
ENTER ACK POLLING
Four of the nine instructions end with the transmission
of the instruction byte. The basic sequence is illus-
trated in Figure 3. These two-byte instructions
exchange data between the Control Latch and one of
the data registers. A transfer from a data register to a
Control Latch is essentially a write to a static RAM.
The response of the wiper to this action will be
ISSUE
START
ISSUE SLA VE
ISSUE ST OP
ADDRESS
delayed t
. A transfer from Control Latch current
STPWV
ACK
NO
wiper position, to a data register is a write to nonvola-
tile memory and takes a minimum of t to complete.
RETURNED?
WR
The transfer can occur between the potentiometer and
its associated registers.
YES
Four instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9428; either between the host and
one of the data registers or directly between the host
and the Control Latch. These instructions are: Read
Control Latch, read the current wiper position of the
pot Write Control Latch, change current wiper position
of the pot Read Data Register, read the contents of
the selected nonvolatile register; Write Data Register,
write a new value to the selected data register. The
sequence of operations is shown in Figure 4.
NO
FURTHER
OPERATION?
YES
ISSUE
INSTRUCTION
ISSUE ST OP
PROCEED
PROCEED
4
X9428
Figure 3. Two-Byte Command Sequence
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
A
C
K
I3 I2
I1 I0 R1 R0
X
X
A
C
K
S
T
O
P
while SDA is HIGH, the wiper will move one resistor
The Increment/Decrement command is different from
the other commands. Once the command is issued
and the X9428 has responded with an acknowledge,
the master can clock the wiper up and/or down in one
segment steps; thereby, providing a fine tuning capa-
segment towards the V terminal. Similarly, for each
H
SCL clock pulse while SDA is LOW, the wiper will
move one resistor segment towards the V terminal. A
L
detailed illustration of the sequence and timing for this
operation are shown in Figures 5 and 6 respectively.
bility to the host. For each SCL clock pulse (t
)
HIGH
Table 1. Instruction Set
Instruction Set
I
I
I
I
R
R
0
Instruction
X
X
Operation
3
2
1
0
1
ReadthecontentsoftheControlLatchpointedto
Read Control Latch
1
1
1
1
0
0
0
1
0
1
1
0
1
0
1
0
N/A N/A N/A N/A
N/A N/A N/A N/A
1/0 1/0 N/A N/A
1/0 1/0 N/A N/A
by P –P
1
0
Write new value to the Control Latch pointed to
by P –P
Write Control Latch
Read Data Register
Write Data Register
1
0
Read the contents of the Register pointed to by
P –P and R –R
1
0
1
0
Write new value to the Register pointed to by
P –P and R –R
1
0
1
0
Transfer the contents of the Register pointed
to by P –P and R –R to its associated
Control Latch
XFR Data Register to
Control Latch
1
1
0
1
1
0
0
1
0
1
0
1
1/0 1/0 N/A N/A
1/0 1/0 N/A N/A
1/0 1/0 N/A N/A
1
0
1
0
Transfer the contents of the Control Latch
pointed to by P –P to the Register pointed
XFR Control Latch to
Data Register
1
0
to by R –R
1
0
Transfer the contents of all four Data Registers
pointed to by R –R to their respective Control
Global XFR Data Reg-
ister to Control Latch
1
0
Latch
Transfer the contents of all Control Latchs to their
respective data Registers pointed to by R –R
Global XFR Control
1
0
0
0
0
1
0
0
1/0 1/0 N/A N/A
N/A N/A N/A N/A
Latch to Data Register
1
0
EnableIncrement/decrementoftheControlLatch
pointed to by P –P
Increment/Decrement
Wiper
1
0
Notes: (7) 1/0 = data is one or zero
(8) N/A = Not applicable or don't care; that is, a data register is not involved in the operation and need not be addressed (typical)
5
X9428
Figure 4. Three-Byte Command Sequence
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
A
C
K
I3 I2
I1 I0
R1 R0
X
X
A
C
K
CM DW D5 D4 D3 D2 D1 D0
A
C
K
S
T
O
P
Figure 5. Increment/Decrement Command Squence
SCL
SDA
X
X
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
A
C
K
I3 I2
I1 I0 R1 R0
X
X
A
C
K
I
I
D
E
C
1
S
T
I
D
N
C
1
N
C
2
N
C
n
E
C
n
O
P
Figure 6. Increment/Decrement Timing Limits
INC/DEC
CMD
ISSUED
t
CLWV
SCL
SDA
VOLTAGE OUT
V
W
6
X9428
Figure 7. Acknowledge Response from Receiver
SCL FROM
MASTER
1
8
9
DATA
OUTPUT
FROM
TRANSMITTER
DATA
OUTPUT
FROM
RECEIVER
START
ACKNOWLEDGE
Figure 8. Detailed Potentiometer Block Diagram
SERIAL DATA PATH
V
SERIAL
BUS
INPUT
H
FROM INTERFACE
CIRCUITRY
C
O
U
N
T
REGISTER 0
REGISTER 2
REGISTER 1
8
6
PARALLEL
BUS
INPUT
E
R
WIPER
COUNTER
REGISTER
D
E
C
O
D
E
REGISTER 3
INC/DEC
LOGIC
IF WCR = 00[H]THEN VW = VL
IF WCR = 3F[H]THEN VW = VH
UP/DN
UP/DN
V
V
L
MODIFIED SCL
CLK
W
7
X9428
DETAILED OPERATION
Register Descriptions
The XDCP is controlled by the serial interface and is
associated with a Control Latch and four data regis-
ters. A detailed discussion of the register organization
and array operation follows.
Wiper Register, WR (6-bit), non-volatile:
WP5
NV
WP4
NV
WP3
NV
WP2
NV
WP1
NV
WP0
NV
Control Latch
(MSB)
(LSB)
The X9428 Control Latch for the XDCP can be envi-
sioned as a 6-bit parallel and serial load counter with
its outputs decoded to select one of sixty-four switches
along its resistor array. The contents of the Control
Latch can be altered in four ways: it may be written
directly by the host via the Write Control Latch instruc-
tion (serial load); it may be written indirectly by trans-
ferring the contents of one of four associated data
registers via the XFR Data Register instruction (paral-
lel load); it can be modified one step at a time by the
Increment/ Decrement instruction and it is loaded with
the contents of its data register zero (R0) upon power-
up.
• {WP5~WP0}: This is used to store one of the 64
wiper position (0 ~ 63).
The Control Latch is a volatile register; that is, its con-
tents are lost when the X9428 is powered-down.
Although the register is automatically loaded with the
value in R0 upon power-up, it should be noted this
may be different from the value present at power-
down.
Data Registers
The potentiometer has four nonvolatile data registers.
These can be read or written directly by the host and
data can be transferred between any of the four data
registers and the control latch. It should be noted all
operations changing data in one of these registers is a
nonvolatile operation and will take a maximum of
10ms.
If the application does not require storage of multiple
settings for the potentiometer, these registers can be
used as regular memory locations that could possibly
store system parameters or user preference data.
8
X9428
Instruction Format
Notes: (1) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave.
Notes: (2) “DA3 ~ DA0”: stands for the device addresses sent by the master.
Notes: (3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
Notes: (4) “I”: stands for the increment operation, SDA held high during active SCL phase (high).
Notes: (5) “D”: stands for the decrement operation, SDA held low during active SCL phase (high).
Notes: (6) In dual XDCP devices, “P1” is a “0” for testing purpose but physically it is a “don’t care” condition.
Read Wiper Control Latch (RW)
device type
identifier
device
instruction
opcode
wiper
wiper position
S
T
A
R
T
S
A
C
K
S
A
C
K
M
A
S
T
addresses
addresses
(sent by slave on SDA)
D
A
3
D
A
2
D
A
1
D
A
0
W W W W W W
C O
0
1
0
1
1
0
0
1
X
X
X
X
0
0
P
5
P
4
P
3
P
2
P
1
P
0
K
P
Load Wiper Control Latch (LW)
device type
identifier
device
instruction
opcode
wiper
addresses
wiper position
S
T
A
R
T
S
A
C
K
S
A
C
K
S
A
S
T
addresses
(sent by master on SDA)
D
A
3
D
A
2
D
A
1
D
A
0
W W W W W W
C O
0
1
0
1
1
0
1
0
X
X
X
X
X
X
P
5
P
4
P
3
P
2
P
1
P
0
K
P
Read Wiper Register (RR)
device type
identifier
device
instruction
opcode
wiper
addresses
wiper position
(sent by slave on SDA)
S
T
A
R
T
S
A
C
K
S
A
C
K
M
A
S
T
addresses
D
A
3
D
A
2
D
A
1
D
A
0
W W W W W W
C O
R
R
0
0
1
0
1
1
0
1
1
X
X
0
0
P
5
P
4
P
3
P
2
P
1
P
0
K
P
1
Store Wiper Register (SR)
device type
identifier
device
instruction
opcode
wiper
wiper position
S
T
A
R
T
S
S
A
C
K
S S
addresses
addresses
(sent by master on SDA)
A
C
K
A
T
HIGH-VOLTAGE
WRITE CYCLE
D D D D
W W W W W W
C O
R
R
0
0
1
0
1
A
3
A
2
A
1
A
0
1
1
0
0
X
X
X
X
P
5
P
4
P
3
P
2
P
1
P
0
K
P
1
Load Wiper Register to Wiper Latch (LRW)
device type
identifier
device
instruction
opcode
wiper
addresses
S
T
A
R
T
S
A
C
K
S
A
S
addresses
T
D D D D
C O
R
R
0
0
1
0
1
A
3
A
2
A
1
A
0
1
1
0
1
X X
K
P
1
9
X9428
Store Wiper Latch to Wiper Register (SWR)
device type
identifier
device
instruction
opcode
wiper
S
T
A
R
T
S
A
C
K
S
A
S
T
addresses
addresses
HIGH-VOLTAGE
WRITE CYCLE
D
A
3
D
A
2
D
A
1
D
A
0
C O
R
1
R
0
0
1
0
1
1
1
1
0
X X
K
P
Increment/Decrement Wiper Latch (INCDEC)
device type
identifier
device
instruction
opcode
wiper
addresses
increment/decrement
S
T
A
R
T
S
A
C
K
S
S
T
O
P
addresses
(sent by master on SDA)
A
C
K
D
A
3
D
A
2
D
A
1
D
A
0
I/ I/
I/ I/
D D
0
1
0
1
0
0
1
0
X
X
X
X
.
.
.
.
D
D
SYMBOL TABLE
Figure 9. Guidelines for Calculating Typical Values
of Bus Pull-Up Resistors
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
120
V
CC MAX
R
=
=1.8KΩ
MIN
I
100
80
OL MIN
May change
from Low to
High
Will change
from Low to
High
t
R
R
=
MAX
C
BUS
MAX.
May change
from High to
Low
Will change
from High to
Low
60
40
20
0
RESISTANCE
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
MIN.
RESISTANCE
N/A
Center Line
is High
Impedance
0
20 40 60 80 100 120
BUS CAPACITANCE (pF)
10
X9428
*COMMENT
ABSOLUTE MAXIMUM RATINGS*
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation
of the device at these or any other conditions above
those listed in the operational sections of this specifi-
cation is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect
device reliability.
Temperature under Bias–65°C to +135°C
Storage Temperature–65°C to +150°C
Voltage on SCK, SCL or any Address Input
with Respect to V –1V to +7V
SS
Voltage on any V or V Referenced to V ±8V
H
L
SS
∆V = |V –V |16V
V+, V- ±6V
H
L
Lead Temperature (Soldering, 10 seconds)300°C
RECOMMENDED OPERATING CONDITIONS
Temp
Commercial
Industrial
Min.
0°C
Max.
+70°C
+85°C
Supply Voltage
X9428
Limits
5V ±10%
–40°C
X9428-2.7
2.7V to 5.5V
ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
Parameter
End to End Resistance
Power Rating
Min.
Typ.
Max.
+20
50
Units
Test Conditions
25°C, each pot
R
–20
%
mW
mA
Ω
TOTAL
I
Wiper Current
–3
+3
W
R
Wiper Resistance
Voltage on V+ Pin
Voltage on V- Pin
150
250
+5.5
-2.7
V+
Wiper Current = ± 1mA
W
Vv+
Vv-
2.7
-5.5
V-
V
V
V
Voltage on any V or V Pin
V
TERM
H
L
Noise
Resolution (4)
<-120
1.6
dB/\/Hz
%
Ref: 1V
Absolute Linearity (1)
Relative Linearity (2)
MI(3)
MI(3)
–1
+1
V
V
– V
w(n)(actual)
– [V
w(n + 1) w(n) + MI
w(n)(expected)
–0.2
+0.2
]
Temperature Coefficient
±300
ppm/°C
11
X9428
D.C. OPERATING CHARACTERISTICS(Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
f
= 100KHz, SDA = Open,
V
Supply Current
SCL
CC
I
3
1
mA
CC
Other Inputs = V
(Active)
SS
I
I
I
V
Current (Standby)
µA
µA
µA
V
SCL = SDA = V , Addr. = V
CC SS
SB
CC
Input Leakage Current
Output Leakage Current
Input HIGH Voltage
Input LOW Voltage
10
10
V
V
= V to V
SS CC
LI
IN
= V to V
CC
LO
OUT
SS
V
V
V
V
x 0.7
V
V
x 0.5
IH
IL
CC
CC
–0.5
x 0.1
V
CC
Output LOW Voltage
0.4
V
I
= 3mA
OL
OL
Notes: (1) AbsoluteLinearityisutilizedtodetermineactualwipervoltageversusexpectedvoltageasdeterminedbywiperpositionwhenused
as a potentiometer.
(2) Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (V – V )/63, single pot
H
L
(4) Max. = all four arrays cascaded together, Typical = individual array resolutions.
ENDURANCE AND DATA RETENTION
Parameter
Minimum Endurance
Data Retention
Min.
100,000
100
Units
Data Changes per Register
Years
CAPACITANCE
Symbol
Test
Max.
Units
pF
Test Conditions
(5)
Input/Output Capacitance (SDA)
8
6
V
= 0V
= 0V
C
I/O
I/O
(5)
Input Capacitance (A0, A1, A2, A3, and SCL)
pF
V
IN
C
IN
POWER-UP TIMING
Symbol
Parameter
Max.
Units
ms
(6)
Power-up to Initiation of Read Operation
Power-up to Initiation of Write Operation
1
5
t
t
PUR
(6)
ms
PUW
A.C. TEST CONDITIONS
EQUIVALENT A.C. LOAD CIRCUIT
2.7V
5V
V
x 0.1 to V x 0.9
CC
Input Pulse Levels
CC
Input Rise and Fall Times
Input and Output Timing Level
10ns
1533Ω
V
x 0.5
CC
SDA OUTPUT
Notes: (5) This parameter is periodically sampled and not 100%
tested
100pF
(6) t
and t
are the delays required from the time
PUW
PUR
V
is stable until the specified operation can be initi-
CC
ated.
These parameters are periodically sampled and not
100% tested.
12
X9428
AC TIMING
Symbol
Parameter
Min.
Max.
Units
KHz
nS
f
I2C Clock Frequency
I2C Clock Cycle Time
I2C Clock High Time
I2C Clock Low Time
Start Setup Time
400
SCL
t
2500
600
1300
600
600
600
100
0
CYC
t
nS
HIGH
t
nS
LOW
t
t
t
t
t
t
t
t
t
nS
SU:STA
HD:STA
SU:STO
SU:DAT
HD:DAT (4)
R (3)
Start Hold Time
nS
Stop Setup Time
nS
SDA Data Input Setup Time
SDA Data Input Hold Time
SCL and SDA Rise Time
SCL and SDA Fall Time
nS
nS
300
300
900
nS
nS
F (3)
SCL Low to SDA Data Output Valid Time
SDA Data Output Hold Time
100
50
nS
AA
nS
DH
T
I2C Noise Suppression Time Constant at
SCL and SDA inputs
50
nS
I
t
t
t
Bus Free Time (Prior to Any Transmission)
WP, A0, A1, A2 Setup Time
1300
nS
nS
nS
BUF
0
0
SU:WPA
HD:WPA
WP, A0, A1, A2 Hold Time
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
Parameter
Typ.
Max.
Units
t
High-voltage Write Cycle Time (Store Instructions)
5
10
mS
WR
EEPOT TIMING
Symbol
Parameter
Min. Max. Units
t
t
t
Wiper Response Time After The Third (Last) Power Supply Is Stable
Wiper Response Time After Instruction Issued (All Load Instructions)
10
10
10
uS
uS
uS
WRPO (2)
WRL
Wiper Response Time From An Active SCL/SCK Edge (Increment/Decrement
Instruction)
WRID
Notes: (7) t
and t
are the delays required from the time the third (last) power supply (Vcc, V+ or V-) is stable until the specific
POW
POR
instruction can be issued. These parameters are periodically sampled and not 100% tested.
(8) The bias order of power supply (Vcc, V+ and V-) don’t care.
(9) A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the
falling edge of SCL.
13
X9428
TIMING DIAGRAMS
I2C Timing
Figure 10. START and STOP Timing
g
(START)
(STOP)
t
t
F
R
SCL
t
t
t
SU:STO
SU:STA
HD:STA
t
t
R
F
SDA
Figure 11. Input Timing
t
t
CYC
HIGH
SCL
SDA
t
LOW
t
t
t
BUF
SU:DAT
HD:DAT
Figure 12. Output Timing
SCL
SDA
t
t
DH
AA
Figure 13. XDCP Timing (for All Load Instructions)
(STOP)
SCL
SDA
VWx
LSB
t
WRL
14
X9428
Figure 14. XDCP Timing (for Increment/Decrement Instruction)
SCL
Wiper Register Address
Inc/Dec
Inc/Dec
SDA
VWx
t
WRID
Figure 15. Write Protect and Device Address Pins Timing
(START)
SCL
(STOP)
...
(Any Instruction)
...
SDA
...
t
t
SU:WPA
HD:WPA
WP
A0, A1
A2
15
X9428
ORDERING INFORMATION
X9428
Y
P
T
V
V
Limits
CC
Device
Blank = 5V ±10%
–2.7 = 2.7 to 5.5V
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
Package
P = 16-Lead Plastic DIP
S = 16-Lead SOIC
V = 16-Lead TSSOP
Potentiometer Organization
Y = 2K
W = 10K
U = 50K
M = 2K
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc.
makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the
described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the
right to discontinue production and change specifications and prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967;
4,883, 976. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prevent such an occurence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1.
2.
Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or
sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury to the user.
A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause
the failure of the life support device or system, or to affect its safety or effectiveness.
16
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