X9430WV24I [XICOR]
Dual Digitally Controlled Potentiometer (XDCP⑩) with Operational Amplifier; 双数控电位器（ XDCP⑩ ）与运算放大器
| 型号： | X9430WV24I |
| 厂家： | 
XICOR INC. |
| 描述： | Dual Digitally Controlled Potentiometer (XDCP⑩) with Operational Amplifier |
| 文件： | 总21页 (文件大小：793K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminar
X9430
Digitally Controlled Potentiometer (XDCP™) with Operational Amplifier
FEATURES
DESCRIPTION
• Two CMOS voltage operational amplifiers
• Two digitally controlled potentiometers
• Can be combined or used separately
• Amplifiers
—Low voltage operation
—V+/V- = ±2.7V to ±5.5V
—Rail-to-rail CMOS performance
—1MHz gain bandwidth product
• Digitally controlled potentiometer
—Dual 64 tap potentiometers
The X9430 is a monolithic CMOS IC that incorporates
two operational amplifiers and two nonvolatile digitally
controlled potentiometers. The amplifiers are CMOS
differential input voltage operational amplifiers with
near rail-to-rail outputs. All pins for the two amplifiers
are brought out of the package to allow combining
them with the potentiometers or using them as com-
plete stand-alone amplifiers.
The digitally controlled potentiometers consist of a
series string of 63 polycrystalline resistors that behave
as standard integrated circuit resistors. The SPI serial
port, common to both pots, allows the user to program
the connection of the wiper output to any of the resistor
nodes in the series string. The wiper position is saved
in the on board E2 memory to allow for nonvolatile res-
toration of the wiper position.
—R
= 10k¾
total
—SPI serial interface
—V = 2.7V to 5.5V
CC
A wide variety of applications can be implemented
using the potentiometers and the amplifiers. A typical appli-
cation is to implement the amplifier as a wiper buffer in
circuits that use the potentiometer as a voltage refer-
ence. The potentiometer can also be combined with
the amplifier yielding a digitally programmable gain
amplifier or programmable current source.
BLOCK DIAGRAM
V
R
R R
H0 L0
CC
W0
V+
HOLD
V
V
NI0
Control and
Memory
+
–
CS
SCK
SO
SI
A1
A0
OUT0
WCR0
V
V
INV0
NI1
+
–
V
OUT1
INV1
WCR1
V
WP
R
R
R
V
V–
W1
L1 H1
SS
Characteristics subject to change without notice. 1 of 21
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X9430 – Preliminary Information
PIN DESCRIPTIONS
Host Interface Pins
Serial Output (SO)
Device Address (A –A )
0 1
The address inputs are used to set the least significant
2 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9430. A maximum of 4 devices may occupy the
SPI serial bus.
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked
out by the falling edge of the serial clock.
Potentiometer Pins1
Serial Input (SI)
R (R –R ), R (R –R )
L1
H
H0
H1
L
L0
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the device are
input on this pin. Data is latched by the rising edge of
the serial clock.
The R and R inputs are equivalent to the terminal
H
L
connections on either end of a mechanical potentiom-
eter.
Serial Clock (SCK)
R
(R –R
)
W1
W
W0
The SCK input is used to clock data into and out of the
X9430.
The wiper output is equivalent to the wiper output of a
mechanical potentiometer.
Chip Select (CS)
Amplifier and Device Pins
When CS is HIGH, the X9430 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9430, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
Amplifier Input Voltage V (0,1) and V (0,1)
NI
INV
V
and V
are inputs to the noninverting (+) and
INV
NI
inverting (-) inputs of the operational amplifiers.
Amplifier Output Voltage V (0,1)
OUT
V
is the voltage output pin of the operational ampli-
OUT
fier.
Hardware Write Protect Input WP
The WP pin when low prevents nonvolatile writes to
the wiper counter register.
Analog Supplies V+, V-
The Analog Supplies V+, V- are the supply voltages for
the XDCP analog section and the operational amplifi-
ers.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume com-
munication, HOLD is brought HIGH, again while SCK
is LOW. If the pause feature is not used, HOLD should
be held HIGH at all times.
System Supply V
and Ground V
SS
CC
The system supply V
to bias the interface and control circuits.
and its reference V is used
SS
CC
1.
Alternate designations for R , R , R are V , V , V
H L W H L W
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X9430 – Preliminary Information
PIN CONFIGURATION
PIN NAMES
Symbol
Description
Serial Clock
SOIC
SCK
SI
V
1
V+
V
CC
24
23
22
21
20
19
18
17
16
15
Serial Input
Serial Output
Device Address
Chip Select
Hold
R
2
L0
OUT0
R
R
SO
3
V
V
H0
NI0
4
W0
CS
A0-A1
CS
INV0
5
A0
WP
6
S0
X9430
HOLD
SI
7
HOLD
SCK
A1
8
R
R
V
–R , R –R
L1
Potentiometers (terminal
equivalent)
H0
H1
L0
R
9
V
L1
INV1
10
11
R
V
–R
Potentiometers (wiper
equivalent)
H1
NI1
W0
W1
R
W1
14
13
V
OUT1
V
12
SS
, V
Amplifier Input Voltages
Amplifier Outputs
V-
NI(0,1) INV(0,1)
V
V
OUT0, OUT1
WP
Hardware Write Protection
TSSOP
V+,V-
Analog and Voltage Amplifier
Supplies
HOLD
SO
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
15
A
0
SCK
V
V
V
System/Digital Supply Voltage
System Ground
CC
SS
V
INV0
INV1
V
V
V
NI0
NI1
V
OUT0
V+
OUT1
V-
V
PRINCIPLES OF OPERATION
X9430
V
CC
SS
The X9430 is an integrated microcircuit incorporating two
digitally controlled potentiometers, two operational
amplifiers and their associated registers and counters;
and the serial interface logic providing direct communica-
tion between the host and the digitally controlled
potentiometers.
R
R
R
R
L0
W1
H1
L1
R
H0
R
W0
10
CS
11
12
A
14
13
1
WP
SI
Serial Interface
The X9430 supports the SPI interface hardware con-
ventions. The device is accessed via the SI input with
data clocked in on the rising edge of SCK. CS must be
LOW and the HOLD and WP pins must be HIGH dur-
ing the entire operation.
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X9430 – Preliminary Information
Potentiometer/Array Description
The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
data registers into the WCR. These data registers and
the WCR can be read and written by the host system.
The X9430 is comprised of two resistor arrays and two
operational amplifiers. Each array contains 63 discrete
resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
Operational Amplifier
terminals of a mechanical potentiometer (R and R ).
H
L
The voltage operational amplifiers are CMOS rail-to-rail
output general purpose amplifiers. They are designed
to operate from dual (±) power supplies. The amplifiers
may be configured like any standard amplifier. All pins
are externally available to allow connection with the
potentiometers or as stand alone amplifiers.
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(R ) output. Within each individual array only one
W
switch may be turned on at a time. These switches are
controlled by a volatile wiper counter register (WCR).
The six bits of the WCR are decoded to select, and
enable, one of sixty-four switches.
V
H (0,1)
(DR0-DR3)
0,1
WCR
0,1
V
HOLD
CC
V
L (0,1)
Control and
Memory
V
V
CS
SCK
SO
SI
W (0,1)
INV (0,1)
WCR0
V
N (0,1)
A1
WCR1
A0
+
–
V
(DR0-DR3)
OUT (0,1)
0,1
V
WP
SS
Detailed Block Diagram
(One of 2 Circuits)
Write in Process
INSTRUCTIONS AND PROGRAMMING
Identification (ID) Byte
The contents of the data registers are saved to nonvol-
atile memory when the CS pin goes from LOW to
HIGH after a complete write sequence is received by
the device. The progress of this internal write opera-
tion can be monitored by a write in process bit (WIP).
The WIP bit is read with a read status command.
The first byte sent to the X9430 from the host, follow-
ing a CS going HIGH to LOW, is called the identifica-
tion byte. The most significant four bits of the slave
address are a device type identifier, for the X9430 this
is fixed as 0101[B] (refer to Figure 1).
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X9430 – Preliminary Information
The two least significant bits in the ID byte select one of
four devices on the bus. The physical device address is
The basic sequence of the two byte instructions is illus-
trated in Figure 3. These two-byte instructions
exchange data between a wiper counter register and
one of the four data registers associated with each. A
transfer from a data register to a wiper counter register
is essentially a write to a static RAM. The response of
defined by the state of the A -A input pins. The X9430
0
1
compares the serial data stream with the address input
state; a successful compare of both address bits is
required for the X9430 to successfully continue the
command sequence. The A –A inputs can be actively
the wiper to this action will be delayed t
. A transfer
0
1
WRL
driven by CMOS input signals or tied to V or V
.
from the wiper counter register (current wiper position)
to a data register is a write to nonvolatile memory and
CC
SS
The remaining two bits in the slave byte must be set to 0.
takes a minimum of t
to complete. The transfer can
WR
occur between one of the two potentiometers and one
of its associated registers; or it may occur globally,
wherein the transfer occurs between both of the poten-
tiometers and one of their associated registers.
Figure 1. Identification Byte Format
Device Type
Identifier
Five instructions require a three-byte sequence to com-
plete. These instructions transfer data between the
host and the X9430; either between the host and one
of the data registers or directly between the host and
the Wiper Counter and Registers. These instructions
are: 1) Read Wiper Counter Register, read the current
wiper position of the selected pot 2) Write Wiper
Counter Register, i.e. change current wiper position of
the selected pot; 3) Read Data Register, read the con-
tents of the selected nonvolatile register; 4) Write Data
Register, write a new value to the selected data register;
5)Read Status, returns the contents of the WIP bit which
indicates if an internal write cycle is in progress.
0
1
0
1
0
0
A1
A0
Device Address
Instruction Byte
The next byte sent to the X9430 contains the instruc-
tion and register pointer information. The four most sig-
nificant bits are the instruction. The next four bits point
to one of the WCRs of the two pots, and when applica-
ble, they point to one of four associated data registers.
The format is shown below in Figure 2.
The sequence of these operations is shown in Figure 4
and Figure 5.
Figure 2. Instruction Byte Format
Register
Select
The final command is Increment/Decrement. It is differ-
ent from the other commands, because it’s length is
indeterminate. Once the command is issued, the mas-
ter can clock the selected wiper up and/or down in one
resistor segment steps; thereby, providing a fine tuning
I3
I2
I1
I0
R1 R0
0
P0
capability to the host. For each SCK clock pulse (t
while SI is HIGH, the selected wiper will move one
)
HIGH
Instructions
WCR Select
resistor segment towards the V terminal. Similarly, for
each SCK clock pulse while SI is LOW, the selected
H
The four high order bits of the instruction byte specify
the operation. The next two bits (R and R ) select one
of the four registers that is to be acted upon when a
1
0
wiper will move one resistor segment towards the V
L
terminal. A detailed illustration of the sequence and
timing for this operation are shown in Figure 6 and
Figure 7.
register oriented instruction is issued. The last bit (P )
0
selects which one of the two potentiometers is to be
affected by the instruction.
Four of the ten instructions are two bytes in length and
end with the transmission of the instruction byte.
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X9430 – Preliminary Information
Figure 3. Two Byte Command Sequence
CS
SCK
SI
0
1
0
1
0
0
A1 A0
I3 I2
I1 I0 R1 R0
0
P0
Figure 4. Three-Byte Command Sequence (Write)
CS
SCK
SI
0
0
0
1
0
1
A1 A0
I3 I2
I1 I0 R1 R0 0 P0
0
0
D5 D4 D3 D2 D1 D0
Figure 5. Three-Byte Command Sequence(Read)
CS
SCK
SI
Don’t Care
0
0
0
1
0
1
A1 A0
I3 I2
I1 I0 R1 R0 0 P0
S0
0
0
D5 D4 D3 D2 D1 D0
Figure 6. Increment/Decrement Command Sequence
CS
SCK
SI
0
0
1
0
1
0
0
A1 A0
I3 I2
I1 I0
0
0
P0
I
I
D
E
C
1
I
D
E
C
n
N
C
1
N
C
2
N
C
n
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X9430 – Preliminary Information
Figure 7. Increment/Decrement Timing
t
WRID
SCK
SI
V
OUT
V
W
INC/DEC CMD Issued
REGISTER OPERATION
resistor array. The contents of the wiper counter register
can be altered in four ways: it may be written directly by
the host via the write WCR instruction (serial load); it
may be written indirectly by transferring the contents of
one of four associated data registers (DR) via the XFR
data register instruction (parallel load); it can be modi-
fied one step at a time by the increment/decrement
instruction (WCR only). Finally, it may be loaded with
the contents of its associated data register zero (R0)
upon power-up.
Both digitally controlled potentiometers share the serial
interface and share a common architecture. Each
potentiometer is associated with a wiper counter regis-
ter (WCR), and four data registers. Figure 8 illustrates
the control, registers, and system features of the
device.
Figure 8. System Block Diagram
The wiper counter register is a volatile register; that is,
its contents are lost when the X9430 is powered-down.
Although the registers are automatically loaded with
the value in R0 upon power-up, it should be noted this
may be different from the value present at power-down.
V
H (0,1)
(DR0-DR3)
WCR
0,1
V
0,1
HOLD
CC
V
L (0,1)
Control and
Memory
V
V
CS
SCK
SO
SI
A1
A0
W (0,1)
INV (0,1)
WCR0
V
N (0,1)
Data Registers (DR)
WCR1
Each potentiometer has four nonvolatile data registers
(DR). These can be read or written directly by the host
and data can be transferred between any of the four
data registers and the WCR. It should be noted all
operations changing data in one of these registers is a
nonvolatile operation and will take a maximum of 10ms.
+
–
V
OUT (0,1)
V
WP
SS
Detailed Block Diagram
Wiper Counter (WCR) and Analog Control
Registers (ACR)
If the application does not require storage of multiple set-
tings for the potentiometer, these registers can be used
as regular memory locations that could store system
parameters or user preference data.
The X9430 contains two wiper counter registers, one
for each XDCP. The wiper counter register is equivalent
to a serial-in, parallel-out counter with its outputs
decoded to select one of sixty-four switches along its
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X9430 – Preliminary Information
REGISTER DESCRIPTIONS AND MEMORY MAP
Memory Map
Wiper Counter Register (WCR)
WP5 WP4 WP3 WP2 WP1 WP0
(volatile) (LSB)
0
0
WCRO
DR0
WCR1
DR0
WP0-WP5 identify wiper position.
DR1
DR1
Data Registers (DR, R0-R3)
DR2
DR2
Wiper Position or User Data
(Nonvolatile)
DR3
DR3
Instruction Format
Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master.
(2) WPx refers to wiper position data in the Wiper Counter Register
(3) “I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
(4) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
Read Wiper Counter Register (WCR)
Read the contents of the Wiper Counter Register pointed to by P -P
1
0
device type
identifier
device
addresses
instruction
opcode
WCR
addresses
wiper position
(sent by X9430 on SO)
CS
CS
Falling
Edge
Rising
Edge
W W W W W W
0 0 P P P P P P
A A
P
0
0
1
0
1
0
0
1
0
0
1
0
0
0
1
0
5
4 3 2 1 0
Write Wiper Counter Register (WCR)
Write new value to the Wiper Counter Register pointed to by P -P
1
0
device type
identifier
device
addresses
instruction
opcode
WCR
addresses
Data Byte
(sent by Host on SI)
CS
CS
Falling
Edge
Rising
Edge
W W W W W W
0 0 P P P P P P
A A
P
0
0
1
0
1
0
0
1
0
1
0
0
0
0
1
0
5
4 3 2 1 0
Read Data Register (DR)
Read the contents of the Register pointed to by P -P and R -R
0
1
0
1
device type
identifier
device
addresses
instruction
opcode
DR/WCR
addresses
Data Byte
(sent by X9430 on SO)
CS
CS
Falling
Edge
Rising
Edge
W W W W W W
0 0 P P P P P P
A A
R
1
R
0
P
0
0
1
0
1
0
0
1
0
1
1
0
1
0
5
4 3 2 1 0
Write Data Register (DR)
Write new value to the Register pointed to by P -P and R -R
0
1
instruction
opcode
0
1
device type
identifier
device
addresses
DR/WCR
addresses
Data Byte
(sent by host on SI)
CS
Falling
Edge
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
W W W W W W
0 P P P P P P
A A
1
R
1
R
0
0
P
0
0
1
0
1
0
0
1
1
0
0
0
0
5
4 3 2 1 0
Characteristics subject to change without notice. 8 of 21
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X9430 – Preliminary Information
Transfer Data Register (DR) to Wiper Counter Register (WCR)
Transfer the contents of the Register pointed to by R -R to the WCR
1
0
device type
identifier
device
addresses
instruction
opcode
DR/WCR
addresses
CS
Falling
Edge
CS
Rising
P
Edge
A A
1
R
1
R
0
0
1
0
1
0
0
1
1
0
1
0
0
0
Transfer Wiper Counter Register (WCR) to Data Register (DR)
Transfer the contents of the WCR to the Register pointed to by R -R
1
0
device type
identifier
device
addresses
instruction
opcode
DR/WCR
addresses
CS
Falling
Edge
CS
Rising
P
Edge
HIGH-VOLTAGE
WRITE CYCLE
A A
1
R
1
R
0
0
1
0
1
0
0
1
1
1
0
0
0
0
P : 0-WCR0, 1-WCR1
0
Increment/Decrement Wiper Counter Register (WCR)
Enable Increment/decrement of the WCR pointed to by P -P
1
0
device type
identifier
device
addresses
instruction
opcode
WCR
increment/decrement
CS
Falling
Edge
CS
Rising
Edge
addresses (sent by master on SDA)
A A
1
P
0
I/ I/
D D
I/ I/
D D
0
1
0
1
0
0
0
0
1
0
X X
0
.
.
.
.
0
Global Transfer Data Register (DR) to Wiper Counter Register (WCR)
Transfer the contents of all four Data Registers pointed to by R -R to their respective WCR
1
0
device type
identifier
device
addresses
instruction
opcode
DR
addresses
CS
Falling
Edge
CS
Rising
Edge
A
1
A
0
R R
1 0
0
1
0
1
0
0
0
0
0
1
0 0
Global Transfer Wiper Counter Register (WCR) to Data Register (DR)
Transfer the contents of all WCRs to their respective data Registers pointed to by R -R
1
0
device type
identifier
device
addresses
instruction
opcode
DR
addresses
CS
Falling
Edge
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
A A
1
R R
1 0
0
1
0
1
0
0
1
0
0
0
0 0
0
Read Status
Returns the contents of the WIP bit which indicates if an internal write cycle is in progress
device type
identifier
device
addresses
instruction
opcode
wiper
addresses
Data Byte
(sent by X9430 on SO)
CS
CS
Falling
Edge
Rising
Edge
W
I
P
A A
0
1
0
1
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
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X9430 – Preliminary Information
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias ....................–65°C to +135°C
Storage temperature .........................–65°C to +150°C
Voltage on SCK, SCL or any
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification)
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reli-
ability.
address input with respect to V ...........–1V to +7V
SS
Voltage on V+ (referenced to V ) ........................+7V
SS
Voltage on V- (referenced to V ) ..........................-7V
SS
(V+) – (V-).............................................................. 10V
Any V ....................................................................V+
H
Any V ...................................................................... V-
L
Lead temperature (soldering, 10 seconds)........ 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
Max.
+70°C
+85°C
Device
X9430
Supply Voltage (V ) Limits
CC
5V ±10%
–40°C
X9430-2.7
2.7V to 5.5V
POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
R
Parameter
End to end resistance
Power rating
Min. Typ. Max.
Unit
%
Test Conditions
–20
+20
50
TOTAL
mW
mA
¾
25°C, each pot
I
Wiper current
–3
+3
W
R
Wiper resistance
40
100
250
+5.5
+5.5
-4.5
-2.7
V+
V+ = 5V, V- = -5V, I = 3mA
W
W
100
¾
V+ = 2.7V, V- = -2.7V, I = 1mA
W
Vv+
Vv-
Voltage on V+ pin
Voltage on V- pin
X9430
+4.5
+2.7
-5.5
-5.5
V-
V
X9430-2.7
X9430
V
X9430-2.7
V
Voltage on any R or R pin
V
dBv
TERM
H
L
Noise
Resolution (4)
-100
1.6
Ref: 1V
%
Absolute linearity (1)
Relative linearity (2)
–1
+1
MI(3)
MI(3)
V
V
–V
w(n)(actual) w(n)(expected)
–0.2
+0.2
–[V
]
w(n) + MI
w(n + 1)
Temperature coefficient of R
±300
ppm/°C
ppm/°C
TOTAL
Ratiometric temperature coefficient
±20
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used
as a potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potenti-
ometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (R –R )/63, single pot (=LSB)
H
L
(4) Individual array resolutions
Characteristics subject to change without notice. 10 of 21
REV 1.0 6/20/00
www.xicor.com
X9430 – Preliminary Information
AMPLIFIER ELECTRICAL CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified.)
Industrial
Commercial
Symbol
Parameter
Condition
Min. Typ. Max. Min. Typ. Max.
Unit
mV
V
Input Offset Voltage
V+/V- ±3V to ±5V
1
3
1
2
OS
TC
InputOffsetVoltageTemp. V+/V- ±3V to ±5V
Coefficient
-10
-10
µV/°C
VOS
I
Input bias current
Input offset current
V+/V- ±3V to ±5V
V+/V- ±3V to ±5V
50
25
50
25
pA
pA
dB
B
I
OS
CMRR
Common mode
rejection ratio
V
= -1V to +1V
70
70
V-
70
70
V-
CM
PSRR
Power supply
rejection ratio
V+/V- ±3V to ±5V
T = 25°C
dB
V
Input common mode
voltage range
V+
V+
V
CM
j
A
Large signal voltage gain
Output voltage swing
V
= -1V to + 1V
30
50
30
50
V/mV
V
O
V
V-
V+
+0.1
+0.1
V
V
O
-.15
-.15
I
Output current
Supply current
V+/V- = ±5.5V
V+/V- = ±3.3V
50
30
50
30
mA
mA
O
I
V+/V- = ±5.0V
V+/V- = ±3.0V
3
3
mA
mA
S
1.5
1.5
GB
SR
Gain-bandwidth prod
Slew rate
R = 100k, C = 50pf
1.0
1.5
80
1.0
1.5
80
MHz
V/µsec
Deg.
L
L
R = 100k, C = 50pf
L
L
Φ
Phase margin
R = 100k,
L
M
C = 50pf
L
V+ and V- (±5V to ±3V) are the amplifier power supplies. The amplifiers are specified with dual power supplies.
and V are the logic supplies. All ratings are over the temperature range for the Industrial (-40 to + 85°C) and
V
CC
SS
Commercial (0 to 70°C) versions of the part unless specified differently.
Characteristics subject to change without notice. 11 of 21
REV 1.0 6/20/00
www.xicor.com
X9430 – Preliminary Information
POTENTIOMETER D.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
I
V
V
supply current (active)
400
µA
f = 2MHz, SO = Open,
SCK
CC1
CC
CC
Other Inputs = V
SS
I
supply current (nonvolatile
1
mA
f
= 2MHz, SO = Open,
SCK
CC2
write)
Other Inputs = V
SS
I
V
current (standby)
1
µA
µA
µA
V
SCK = SI = V , Addr. = V
SS SS
SB
CC
I
Input leakage current
Output leakage current
Input HIGH voltage
Input LOW voltage
Output LOW voltage
10
10
V
V
= V to V
SS CC
LI
IN
I
= V to V
SS CC
LO
OUT
V
V
x 0.7
V
+ 0.5
CC
IH
CC
V
–0.5
V
x 0.1
V
IL
CC
V
0.4
V
I
= 3mA
OL
OL
ENDURANCE AND DATA RETENTION
Parameter
Minimum endurance
Data retention
Min.
Unit
100,000
100
Data changes per register
years
CAPACITANCE
Symbol
Test
Output capacitance (SO)
Typ.
Max. Unit Test Conditions
(5)
C
8
6
pF
pF
pF
V
= 0V
OUT
OUT
(5)
C
Input capacitance (A0, A1, SI, WP, HOLD and SCK)
Potentiometer capacitance
V
= 0V
IN
IN
C | C | C
W
10/10/
L
H
POWER-UP TIMING
Symbol
Parameter
Max.
Unit
(6)
t
Power-up to initiation of read operation
Power-up to initiation of write operation
1
5
ms
ms
PUR
(6)
t
PUW
(7) The power-up order of power supplies are V , V+
CC
A.C. TEST CONDITIONS
and V-.
Input pulse levels
V
x 0.1 to V x 0.9
CC
CC
SPICE Macro Model
Input rise and fall times
Input and output timing level
10ns
V
x 0.5
CC
R
TOTAL
R
R
L
H
Notes: (5) This parameter is periodically sampled and not 100%
C
L
C
C
tested.
W
H
(6) t
and t
are the delays required from the time the
PUW
PUR
third (last) power supply (V , V+ or V-) is stable until
CC
the specific instruction can be issued. These parameters
are
periodically sampled and not 100% tested.
R
W
Characteristics subject to change without notice. 12 of 21
REV 1.0 6/20/00
www.xicor.com
X9430 – Preliminary Information
AC TIMING
Symbol
Parameter
Min.
Max.
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
f
SSI/SPI clock frequency
SSI/SPI clock cycle time
SSI/SPI clock high time
SSI/SPI clock low time
Lead time
2.0
SCK
CYC
t
500
200
200
250
250
50
t
WH
t
WL
t
LEAD
t
Lag time
LAG
t
SI, SCK, HOLD and CS input setup time
SI, SCK, HOLD and CS input hold time
SI, SCK, HOLD and CS input rise time
SI, SCK, HOLD and CS input fall time
SO output disable time
SU
t
50
H
t
2
RI
t
2
FI
t
0
0
500
200
DIS
t
SO output valid time
V
t
SO output hold time
HO
RO
t
SO output rise time
50
50
t
SO output fall time
FO
t
HOLD time
400
100
100
HOLD
t
HOLD setup time
HSU
t
HOLD hold time
HH
t
HOLD low to output in high Z
HOLD high to output in low Z
Noise suppression time constant at SI, SCK, HOLD and CS inputs
CS deselect time
100
100
20
HZ
t
LZ
T
I
t
2
0
0
CS
t
WP, A0 and A1 setup time
WP, A0 and A1 hold time
WPASU
t
WPAH
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol Parameter
High-voltage write cycle time (store instructions)
Typ.
Max.
Unit
t
5
10
ms
WR
V
RAMP (sample tested)
CC
Symbol
trV
Parameter
Typ.
Max.
Unit
V
power—up rate
.2
50
V/ms
CC
CC
Characteristics subject to change without notice. 13 of 21
REV 1.0 6/20/00
www.xicor.com
X9430 – Preliminary Information
DCP Timing
Symbol
Parameter
Min. Max. Unit
t
Wiper response time after the third (last) power supply is stable
10
10
10
µs
µs
µs
WRPO
t
Wiper response time after instruction issued (all load instructions)
Wiper response time from an active SCL/SCK edge (increment/decrement instruction)
WRL
t
WRID
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
TIMING DIAGRAMS
Input Timing
t
CS
CS
t
t
t
LAG
LEAD
CYC
SCK
...
WH
t
t
FI
t
RI
t
t
t
WL
SU
H
...
MSB
LSB
SI
High Impedance
SO
Characteristics subject to change without notice. 14 of 21
REV 1.0 6/20/00
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X9430 – Preliminary Information
Output Timing
CS
SCK
...
...
t
t
t
DIS
V
HO
MSB
LSB
SO
SI
ADDR
Hold Timing
CS
t
t
HH
HSU
SCK
SO
...
t
t
FO
RO
t
t
LZ
HZ
SI
t
HOLD
HOLD
DCP Timing (for All Load Instructions)
CS
SCK
...
...
t
WRL
MSB
LSB
SI
VWx
High Impedance
SO
Characteristics subject to change without notice. 15 of 21
REV 1.0 6/20/00
www.xicor.com
X9430 – Preliminary Information
DCP Timing (for Increment/Decrement Instruction)
CS
SCK
VWx
...
t
WRID
...
...
ADDR
Inc/Dec
SI
Inc/Dec
High Impedance
SO
Write Protect and Device Address Pins Timing
(Any Instruction)
CS
t
t
WPAH
WPASU
WP
A0
A1
Characteristics subject to change without notice. 16 of 21
REV 1.0 6/20/00
www.xicor.com
X9430 – Preliminary Information
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
+V
R
V
R
V
W
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Application Circuits
Noninverting Amplifier
Voltage Regulator
V
+
–
S
V
V
V (REG)
O
317
O
IN
R
1
R
2
I
adj
R
R
1
2
V
= (1+R /R )V
V
(REG) = 1.25V (1+R /R )+I
R
adj
O
2
1
S
O
2
1
2
Offset Voltage Adjustment
Comparator with Hysterisis
R
R
2
1
V
–
+
S
V
V
S
O
100KΩ
–
+
V
O
TL072
R
R
1
2
10KΩ
10KΩ
+12V
V
V
= {R /(R +R )} V (max)
1 1 2 O
UL
LL
10KΩ
-12V
= {R /(R +R )} V (min)
1
1
2
O
Characteristics subject to change without notice. 17 of 21
REV 1.0 6/20/00
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X9430 – Preliminary Information
Application Circuits (continued)
Attenuator
Filter
C
V
+
–
S
R
V
R
R
2
O
1
–
+
R
V
O
V
S
3
R
2
R
4
All R = 10kΩ
S
R
1
G
= 1 + R /R
2 1
V
= G V
S
O
O
fc = 1/(2pRC)
-1/2 ð G ð +1/2
Inverting Amplifier
Equivalent L-R Circuit
R
R
2
1
V
S
R
2
C
1
–
+
V
+
–
S
V
O
R
R
1
Z
IN
V = G V
O
S
3
G = - R /R
2
1
Z
= R + s R (R + R ) C = R + s Leq
2 2 1 3 1 2
IN
(R + R ) >> R
1
3
2
Function Generator
C
R
R
1
2
–
+
–
+
R
R
}
}
A
B
frequency µ R , R , C
1
2
amplitude µ R , R
A
B
Characteristics subject to change without notice. 18 of 21
REV 1.0 6/20/00
www.xicor.com
X9430 – Preliminary Information
PACKAGING INFORMATION
24-Lead Plastic Small Outline Gull Wing Package Type S
0.393 (10.00)
0.290 (7.37)
0.299 (7.60)
0.420 (10.65)
Pin 1 Index
Pin 1
0.014 (0.35)
0.020 (0.50)
0.598 (15.20)
0.610 (15.49)
(4X) 7°
0.092 (2.35)
0.105 (2.65)
0.003 (0.10)
0.012 (0.30)
0.050 (1.27)
0.050"Typical
0.010 (0.25)
0.020 (0.50)
X 45°
0.050"
Typical
0° – 8°
0.009 (0.22)
0.013 (0.33)
0.420"
0.015 (0.40)
0.050 (1.27)
0.030" Typical
24 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 19 of 21
REV 1.0 6/20/00
www.xicor.com
X9430 – Preliminary Information
PACKAGING INFORMATION
24-Lead Plastic, TSSOP Package Type V
.026 (.65) BSC
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.303 (7.70)
.311 (7.90)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.06)
.005 (.15)
.010 (.25)
Gage Plane
(7.72)
(4.16)
0°–8°
Seating Plane
.020 (.50)
.030 (.75)
(1.78)
(0.42)
Detail A (20X)
(0.65)
ALL MEASUREMENTS ARE TYPICAL
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 20 of 21
REV 1.0 6/20/00
www.xicor.com
X9430 – Preliminary Information
Ordering Information
X9430
Y
P
T
V
V
Limits
CC
Device
Blank = 5V ±10%
–2.7 = 2.7 to 5.5V
Temperature Range
Blank = Commercial = 0 to +70°C
I = Industrial = –40 to +85°C
Package
S24 = 24-Lead SOIC
V24 = 24-Lead TSSOP
Potentiometer Organization
Pot 0 Pot 1
W =
10K¾ 10K¾
©Xicor, Inc. 2000 Patents Pending
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 21 of 21
REV 1.0 6/20/00
www.xicor.com
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