X9438WS24-2.7T1 [XICOR]
Digital Potentiometer, 2 Func, CMOS, PDSO24, PLASTIC, SOIC-24;
| 型号： | X9438WS24-2.7T1 |
| 厂家： | 
XICOR INC. |
| 描述： | Digital Potentiometer, 2 Func, CMOS, PDSO24, PLASTIC, SOIC-24 光电二极管 转换器 |
| 文件： | 总19页 (文件大小：117K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary Information
Programmable Analog
X9438
Dual Programmable Operational Amplifier
FEATURES
DESCRIPTION
• Two CMOS Rail To RailOperational Amplifiers
• Two Digitally Controlled Potentiometers
• Can Be Combined or Used Separately
• Amplifiers;
—Low Voltage Operation
—V+/V- = ±2.7V to ±5.5V
—Rail-to-Rail CMOS Performance
—1MHz Gain Bandwidth Product
• Digitally Controlled Potentiometers
—Dual 64 Tap potentiometers
The X9438 is a monolithic CMOS IC that incorporates
two operational amplifiers and two nonvolatile digitally
controlled potentiometers. The amplifiers are CMOS
differential input voltage operational amplifiers with rail-
to-rail outputs. All pins for the two amplifiers are brought
out of the package to allow combining them with the
potentiometers or using them as complete stand-alone
amplifiers.
The digitally controlled potentiometers consist of a series
string of 63 polycrystalline resistors that behave as
standard integrated circuit resistors. The two-wire serial
port, common to both pots, allows the user to program
the connection of the wiper output to any of the resistor
nodes in the series string. The wiper position is saved in
the on board E2 memory to allow for nonvolatile
restoration of the wiper position.
—R
= 10kΩ
total
—Two-wire serial interface
—V = 2.7V to 5.5V
CC
A wide variety of applications can be implemented using
the potentiometers and the amplifiers. A typical
application is to implement the amplifier as a wiper buffer
in circuits that use the potentiometer as a voltage
reference. The potentiometer can also be combined with
the amplifier yielding a digitally programmable gain
amplifier or programmable current source.
FUNCTIONAL DIAGRAM
V
R
R
R
H0 L0
CC
W0
V+
V
V
NI0
CONTROL AND
MEMORY
+
Ð
SCL
SDA
A3
A2
A1
A0
OUT0
WCR0
V
V
INV0
NI1
+
Ð
V
OUT1
INV1
WP
WCR1
V
R
R
R
L1 H1
V
VÐ
W1
SS
Xicor, Inc. 1998 Patents Pending
9900-2013.1 10/18/99 PS
Characteristics subject to change without notice
1
X9438
Preliminary
PIN DESCRIPTIONS
Analog Supplies V+, V-
The Analog Supplies V+, V- are the supply voltages for
the XDCP analog section and the operational amplifiers.
Host Interface Pins
Serial Clock (SCL)
System Supply V
and Ground V
.
The SCL input is used to clock data into and out of the
X9438.
CC
SS
The system supply V and its reference V is used to
CC
SS
bias the interface and control circuits.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and
out of the device. It is an open drain output and may be
wire-ORed with any number of open drain or open
collector outputs. An open drain output requires the use
of a pull-up resistor.
PIN CONFIGURATION
TSSOP
SOIC
V
1
V+
V
NC
A
3
CC
1
24
23
22
21
20
19
18
17
16
15
24
A
0
R
SCL
V
2
L0
2
23
22
21
20
19
18
17
16
15
OUT0
V
R
3
INV0
V
V
H0
3
INV1
NI0
Device Address (A –A )
0
3
V
R
NI0
4
V
V
W0
4
INV0
NI1
The address inputs are used to set the least significant 4
bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with the
X9438. A maximum of 16 devices may share the same
2-wire serial bus.
V
A
2
5
OUT0
5
A0
OUT1
WP
V-
V
V+
6
NC
6
X9438
X9438
V
SDA
7
CC
7
A
3
SS
A1
R
8
SCL
V
8
R
R
R
L0
W1
H1
L1
R
R
9
9
H0
L1
INV1
R
W0
10
11
R
10
11
V
H1
NI1
Potentiometer Pins(1)
R
W1
A
2
14
13
A
14
V
1
OUT1
V
R (R – R ), R (R – R
)
SS
12
WR
13
12
H
H0
H1
L
L0
L1
SDA
V-
The R and R inputs are equivalent to the terminal
H
L
connections on either end of
a
mechanical
potentiometer.
PIN NAMES
R
(R
– R
)
W
W0
W1
Symbol
SCL
Description
The wiper output is equivalent to the wiper output of a
mechanical potentiometer.
Serial Clock
Serial Data
SDA
Amplifier and Device Pins
A0-A3
Device Address
Amplifier Input Voltage V (0,1) and V (0,1)
NI
INV
R
–R
,
Potentiometers
(terminal equivalent)
H0
H1
L1
V
and V
are inputs to the noninverting (+) and
NI
INV
R –R
L0
inverting (-) inputs of the operational amplifiers.
Potentiometers
(wiper equivalent)
R
–R
W1
W0
Amplifier Output Voltage V (0,1)
OUT
V
is the voltage output pin of the operational
OUT
V
V
,
NI(0,1)
amplifier.
Amplifier Input Voltages
Amplifier Outputs
INV(0,1)
Hardware Write Protect Input WP
V
V
OUT0,
OUT1
The WP pin, when low, prevents non-volatile writes to the
wiper counter registers.
WP
Hardware Write Protection
Analog and Voltage Amplifier
Supplies
V+,V-
System/Digital Supply
Voltage
V
V
CC
SS
System Ground
No Connection
NC
(1) Alternate designations for R , R , R are V , V , V
W
H
L
W
H
L
2
X9438
Preliminary
PRINCIPLES OF OPERATION
The X9438 will respond with an acknowledge after
recognition of a start condition and its slave address and
once again after successful receipt of the command byte.
If the command is followed by a data byte the X9438 will
respond with a final acknowledge.
The X9438 is an integrated microcircuit incorporating two
resistor arrays, two operational amplifiers and their
associated registers and counters; and the serial
interface logic providing direct communication between
the host and the digitally-controlled potentiometers and
operational amplifiers.
Operational Amplifier
The voltage operational amplifiers are CMOS rail-to-rail
output general purpose amplifiers. They are designed to
operate from dual (±) power supplies.The amplifiers may
be configured like any standard amplifier. All pins are
externally available to allow connections with the
potentiometers or as stand alone amplifiers.
Serial Interface
The X9438 supports a bidirectional bus oriented
protocol.The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as
the receiver. The device controlling the transfer is a
master and the device being controlled is the slave. The
master will always initiate data transfers and provide the
clock for both transmit and receive operations. Therefore,
the X9438 will be considered a slave device in all
applications.
Potentiometer/Array Description
The X9438 is comprised of two resistor arrays and two
operational amplifiers. Each array contains 63 discrete
resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (R and R
inputs).
H
L
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW periods (t
). SDA state changes during SCL
At both ends of each array and between each resistor
LOW
HIGH are reserved for indicating start and stop
conditions.
segment is a CMOS switch connected to the wiper (R )
W
output. Within each individual array only one switch may
be turned on at a time. These switches are controlled by
a volatile wiper counter register (WCR). The six bits of
the WCR are decoded to select, and enable, one of sixty-
four switches.
Start Condition
All commands to the X9438 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (t
). The X9438 continuously
HIGH
The WCR may be written directly, or it can be changed by
transferring the contents of one of four associated data
registers into the WCR. These data registers and the
WCR can be read and written by the host system.
monitors the SDA and SCL lines for the start condition
and will not respond to any command until this condition
is met.
Stop Condition
INSTRUCTIONS AND PROGRAMMING
Device Addressing
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH.
Following a start condition the master must output the
address of the slave it is accessing. The most significant
four bits of the slave address are the device type identifier
(refer to Figure 1 below). For the X9438 this is fixed as
0101.
Acknowledge
Acknowledge is a software convention used to provide a
positive handshake between the master and slave devices
on the bus to indicate the successful receipt of data. The
transmitting device, either the master or the slave, will
release the SDA bus after transmitting eight bits. The
master generates a ninth clock cycle and during this
period the receiver pulls the SDA line LOW to
acknowledge that it successfully received the eight bits of
data.
Figure 1. Address/Identification Byte Format
DEVICE TYPE
IDENTIFIER
A3
A2
A1
A0
0
1
0
1
DEVICEADDRESS
3
X9438
Preliminary
The next four bits of the slave address are the device
address. The physical device address is defined by the
state of the A0-A3 inputs.The X9438 compares the serial
data stream with the address input state; a successful
compare of all four address bits is required for the X9438
Instruction Structure
The byte following the address contains the instruction
and register pointer information.The four most significant
bits are the instruction. The next four bits point to one of
the WCRs of the two pots and when applicable they point
to one of the four WCRs associated data registers. The
format is shown below in Figure 2.
to respond with an acknowledge. The A –A inputs can
0
3
be actively driven by CMOS input signals or tied to V
CC
or V
.
SS
Figure 2. Instruction Byte Format
Acknowledge Polling
REGISTER
SELECT
The disabling of the inputs, during the internal non-
volatile write operation, can be used to take advantage of
the typical 5ms EEPROM write cycle time. Once the stop
condition is issued to indicate the end of the non-volatile
write command the X9438 initiates the internal write
cycle. ACK polling (Flow 1) can be initiated immediately.
This involves issuing the start condition followed by the
device slave address. If the X9438 is still busy with the
write operation no ACK will be returned. If the X9438 has
completed the write operation an ACK will be returned
and the master can then proceed with the next operation.
I3
I2
I1
I0
R1 R0
0
P0
WCR SELECT
INSTRUCTIONS
The four high order bits define the instruction. The next
two bits (R1 and R0) select one of the four registers that
is to be acted upon when a register oriented instruction is
issued. The last bit (P0) selects which one of the two
potentiometers is to be affected by the instruction.
Four of the nine instructions end with the transmission of
the instruction byte. The basic sequence is illustrated in
Figure 3. These two-byte instructions exchange data
between the Wiper Counter Register and one of the data
registers. A transfer from a data register to a Wiper
Counter Register is essentially a write to a static RAM.
The response of the wiper to this action will be delayed
Flow 1. ACK Polling Sequence
NONVOLATILE WRITE
COMMAND COMPLETED
ENTERACK POLLING
ISSUE
START
t
. A transfer from the Wiper Counter Register
WRL
(current wiper position) to a data register is a write to
non-volatile memory and takes a minimum of t to
ISSUE SLAVE
ISSUE STOP
ADDRESS
WR
complete. The transfer can occur between one of the two
potentiometers and one of its associated registers; or it
may occur globally, wherein the transfer occurs between
all of the potentiometers and one of their associated
registers.
ACK
NO
RETURNED?
YES
NO
FURTHER
OPERATION?
Four instructions require a three-byte sequence to
complete. The basic sequence is illustrated in Figure 4.
These instructions transfer data between the host and
the X9438; either between the host and one of the data
registers or directly between the host and the Wiper
Counter and Analog Control Registers. These
instructions are: 1) Read Wiper Counter Register or read
the current wiper position of the selected pot, 2) Write
Wiper Counter Register, i.e. change current wiper
position of the selected pot ; 3) Read Data Register, read
the contents of the selected non-volatile register; 4)
Write Data Register, write a new value to the selected
data register. The bit structures of the instructions are
shown in Figure 6.
YES
ISSUE
INSTRUCTION
ISSUE STOP
PROCEED
PROCEED
4
X9438
Preliminary
Figure 3. Two-Byte Command Sequence
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
A
C
K
I3 I2
I1 I0 R1 R0
0
P0
A
C
K
S
T
O
P
Figure 4. Three-Byte Command Sequence
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
A
C
K
I3 I2
I1 I0
R1 R0
0
P0
A
C
K
D5 D4 D3 D2 D1 D0
A
C
K
S
T
O
P
The Increment/Decrement command is different from the
other commands. Once the command is issued and the
X9438 has responded with an acknowledge, the master
can clock the selected wiper up and/or down in one
segment steps; thereby, providing a fine tuning capability
is HIGH, the selected wiper will move one resistor
segment towards the V terminal. Similarly, for each SCL
H
clock pulse while SDA is LOW, the selected wiper will
move one resistor segment towards the V terminal. A
L
detailed illustration of the sequence for this operation is
shown in Figure 5.
to the host. For each SCL clock pulse (t
) while SDA
HIGH
Figure 5. Increment/Decrement Command Sequence
SCL
SDA
X
0
X
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
A
C
K
I3 I2
I1 I0 R1 R0
P0
A
C
K
I
I
D
E
C
1
S
T
O
P
I
D
E
C
n
N
C
1
N
C
2
N
C
n
5
X9438
Preliminary
FIGURE 6. INSTRUCTION SET
Read Wiper Counter Register (WCR)
Read the contents of the Wiper Counter Register P .
0
S device type
device
addresses
instruction
opcode
WCR
addresses
register data
(sent by slave on SDA)
S
A
C
K
S
A
C
K
M S
A T
C O
K P
T
A
R
T
identifier
A A A A
P
0
D D D D D D
5 4 3 2 1 0
0
1
0
1
1
0
0
1
0
0
0
0 0
3
2
1
0
P0: 0-WCR0, 1-WCR1
Write Wiper Counter Register (WCR)
Write new value to the Wiper Counter Register P .
0
S device type
device
addresses
instruction
opcode
WCR
addresses
register data
S
S
A
C
K
S S
A T
C O
K P
T
A
R
T
identifier
(sent by master on SDA)
A
C
K
A A A A
P
0
D D D D D D
5 4 3 2 1 0
0
1
0
1
1
0
1
0
0
0
0
0 0
3
2
1
0
P0: 0-WCR0, 1-WCR1
Read Data Register (DR)
Read the contents of the Register pointed to by P and R -R .
0
1
0
S device type
device
addresses
instruction WCR/DR
register data
(sent by master on SDA)
S
A
C
K
S
M S
A T
C O
K P
T
A
R
T
identifier
opcode
addresses
A
C
K
A A A A
R R
P
0
D D D D D D
5 4 3 2 1 0
0
1
0
1
1
0
1
1
0
0 0
3
2
1
0
1
0
R1 R0: 00-R0, 10-R1
01-R2, 11-R3
Write Data Register (DR)
Write new value to the Register pointed to by P and R -R .
0
1
0
S device type
device
addresses
instruction
opcode
WCR/DR
addresses
register data
S
S
A
C
K
S S
T
A
R
T
identifier
(sent by master on SDA)
A
C
K
A T HIGH-VOLTAGE
C O WRITE CYCLE
K P
5 4 3 2 1 0
A A A A
R
1
R
0
0
P
0
D D D D D D
0
1
0
1
1
1
0
0
0 0
3
2
1
0
Definitions:
SACK – Slave acknowledge, MACK – Master acknowledge, I/D – Increment/Decrement (1/0), R – Register,
P – Potentiomenter
6
X9438
Preliminary
FIGURE 6. INSTRUCTION SET (continued)
Transfer Data Register to Wiper Counter Register
Transfer the contents of the Register pointed to by R -R to the WCR pointed to by P .
1
0
0
S
T
A
R
T
device type
identifier
device
addresses
instruction
opcode
WCR/DR
addresses
S
A
C
K
S S
A
T
C O
K P
A A A A
R R
P
0
0
1
0
1
1
1
0
1
0
3
2
1
0
1
0
Transfer Wiper Counter Register to Data Register
Transfer the contents of the WCR pointed to by P to the Register pointed to by R -R .
0
1
0
S
T
A
R
T
device type
identifier
device
addresses
instruction
opcode
WCR/DR
addresses
S
A
C
K
S S
A
T
HIGH-VOLTAGE
C O WRITE CYCLE
K P
A A A A
R R
1 0
P
0
0
1
0
1
1
1
1
0
0
3
2
1
0
Global Transfer Data Register to Wiper Counter Register
Transfer the contents of all four Data Registers pointed to by R -R to their respective WCR.
1
0
S
T
A
R
T
device type
identifier
device
addresses
instruction
opcode
DR
addresses
S
A
C
K
S S
A
T
C O
K P
A A A A
R R
1 0
0
1
0
1
0
0
0
1
0 0
3
2
1
0
Global Transfer Wiper Counter Register to Data Register
Transfer the contents of all WCRs to their respective data Registers pointed to by R -R .
1
0
S
T
A
R
T
device type
identifier
device
addresses
instruction
opcode
DR
addresses
S
A
C
K
S S
A
T
HIGH-VOLTAGE
WRITE CYCLE
C O
K P
A A A A
R R
1 0
0
1
0
1
1
0
0
0
0 0
3
2
1
0
Increment/Decrement Wiper Counter Register
Enable Increment/decrement of the WCR pointed to by P .
0
S
T
A
R
T
device type
identifier
device
addresses
instruction
opcode
WCR
addresses
increment/decrement
(sent by master on SDA)
S
A
C
K
S
S
T
O
P
A
C
K
A A A A
P
0
I/ I/
D D
I/ I/
D D
0
1
0
1
0
0
1
0
0
0
0
.
.
.
.
3
2 1 0
P0: 0 or 1 only.
7
X9438
Preliminary
REGISTER OPERATION
The Wiper Counter Register is a volatile register; that is,
its contents are lost when the X9438 is powered-down.
Although the registers are automatically loaded with the
value in R0 upon power-up, it should be noted this may
be different from the value present at power-down.
Both digitally controlled potentiometers share the serial
interface and share a common architecture. Each
potentiometer is associated with a Wiper Counter
Register (WCR), and four Data Registers. Figure 7
illustrates the control, registers, and system features of
the device.
Data Registers (DR)
Each potentiometer has four non-volatile data registers
(DR). These can be read or written directly by the host
and data can be transferred between any of the four data
registers and the WCR. It should be noted all operations
changing data in one of these registers is a non-volatile
operation and will take a maximum of 10ms.
R
H (0,1)
(DR0-DR3)
0,1 WCR
0,1
WP
R
R
L (0,1)
SCL
SDA
A0
A1
A2
W (0,1)
INTERFACE
AND
CONTROL
V
V
INV (0,1)
If the application does not require storage of multiple
settings for the potentiometer, these registers can be
used as regular memory locations that could store
system parameters or user preference data.
NI (0,1)
CIRCUITRY
A3
+
Ð
V
OUT (0,1)
REGISTER DESCRIPTIONS AND MEMORY MAP
Memory Map
Figure 7. System Block Diagram
WCRO
DR0
WCR1
DR0
Wiper Counter (WCR) and Analog Control
Registers (ACR)
DR1
DR1
The X9438 contains two Wiper Counter Registers, one
for each XDCP.The Wiper Counter Register is equivalent
to a serial-in, parallel-out counter with its outputs decoded
to select one of sixty-four switches along its resistor array.
The contents of the Wiper Counter Register can be
altered in four ways: it may be written directly by the host
via the Write WCR instruction (serial load); it may be
written indirectly by transferring the contents of one of
four associated data registers (DR) via the XFR Data
Register instruction (parallel load); it can be modified one
step at a time by the Increment/ Decrement instruction
(WCR only). Finally, it is loaded with the contents of its
data register zero (R0) upon power-up.
DR2
DR2
DR3
DR3
Wiper Counter Register (WCR)
0
0
WP5 WP4 WP3 WP2 WP1 WP0
(volatile) (LSB)
WP0-WP5 identify wiper position.
Data Registers (DR, R0-R3)
Wiper Position or User Data
(Nonvolatile)
8
X9438
Preliminary
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
listed in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Temperature under Bias .........................–65°C to +135°C
Storage Temperature..............................–65°C to +150°C
Voltage on SDA, SCL or any Address Input
with Respect to V ......................................–1V to +7V
SS
Voltage on any V+ (referenced to V )....................... +7V
SS
Voltage on any V- (referenced to V )......................... -7V
SS
(V+) – (V-) .............................................................................10V
Any R .......................................................................... V+
H
Any R ........................................................................... V-
L
Lead Temperature (Soldering, 10 seconds)............ 300°C
RECOMMENDED OPERATING CONDITIONS
Device
X9438
X9438-2.7
Supply Voltage (V ) Limits
Temp
Commercial
Industrial
Min.
0°C
Max.
+70°C
+85°C
CC
5V ±10%
2.7V to 5.5V
–40°C
POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Parameter
End to End Resistance
Power Rating
Min. Typ. Max. Units
Test Conditions
Symbol
R
–20
+20
50
%
mW
mA
Ω
TOTAL
25°C, each pot
I
Wiper Current
–3
+3
W
V
V
= 5V, Wiper Current = 3mA
= 2.7, Wiper Current = 1mA
40
100
CC
CC
R
Wiper Resistance
W
100
250
+5.5
+5.5
-4.5
-2.7
V+
Ω
X9438
+4.5
+2.7
-5.5
-5.5
V-
Vv+
Vv-
Voltage on V+ Pin
Voltage on V- Pin
V
V
X9438-2.7
X9438
X9438-2.7
V
Voltage on any R or R Pin
H L
V
dBv
%
TERM
Noise
Resolution (4)
-120
1.6
Ref: 1V
Absolute Linearity (1)
Relative Linearity (2)
MI(3)
MI(3)
V
– V
w(n)(expected)
–1
+1
w(n)(actual)
V
– [V
]
–0.2
+0.2
w(n + 1)
w(n) + MI
Temperature Coefficient of R
±300
ppm/°C
TOTAL
Ratiometric Temperature
Coefficient
±20 ppm/°C
Notes: (1) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
(2) Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (R – R )/63, single pot (=LSB)
H
L
(4) Individual array resolutions
9
X9438
Preliminary
AMPLIFIER ELECTRICAL CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified.)
Industrial
Commercial
Symbol
Parameter
Condition
Min
Typ Max Min Typ Max Units
V
Input Offset Voltage
V+/V- ±3V to ±5V
1
3
1
2
mV
OS
Input Offset Voltage
Temp. Coefficient
TC
V+/V- ±3V to ±5V
-10
-10
µV/°C
VOS
I
Input Bias Current
Input Offset Current
V+/V- ±3V to ±5V
V+/V- ±3V to ±5V
50
25
50
25
pA
pA
B
I
OS
Common Mode
Rejection Ratio
V
= -1V to +1V
CMRR
PSRR
70
70
70
70
dB
dB
CM
Power Supply
Rejection Ratio
V+/V- ±3V to ±5V
Input Common Mode
Voltage Range
V
T = 25°C
V-
V+
V-
V+
V
CM
j
Large Signal
Voltage Gain
A
V = -1V to + 1V
30
50
30
50
V/mV
V
O
V-
V+
V
V
V
Output Voltage Swing
Output Current
+0.1
+0.1
O
-.15
-.15
V+/V- = ±5.5V
V+/V- = ±3.3V
50
30
50
30
mA
mA
I
O
V+/V- = ±5.0V
V+/V- = ±3.0V
3
3
mA
mA
I
Supply Current
S
1.5
1.5
R = 100k,
L
GB
SR
Gain-Bandwidth Prod
Slew Rate
1.0
1.5
80
1.0
1.5
80
MHz
V/µsec
Deg.
C = 50pf
L
R = 100k,
L
C = 50pf
L
R = 100k,
L
Φ
Phase Margin
M
C = 50pf
L
V+ and V- (±5V to ±3V) are the amplifier power supplies.The amplifiers are specified with dual power supplies.V and
CC
V
is the logic supply. All ratings are over the temperature range for the Industrial (-40 to + 85°C) and Commercial (0 to
SS
70°C) versions of the part unless specified differently.
10
X9438
Preliminary
SYSTEM/DIGITAL D.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
= 400KHz, SDA = Open,
Other Inputs = V
SS
V
Supply Current
(Active)
Current (Standby)
f
SCL
CC
I
400
µA
CC
1
10
10
10
µA
µA
µA
V
I
I
I
V
SCL = SDA = V , Addr. = V
CC SS
SB
CC
Input Leakage Current
Output Leakage Current
Input HIGH Voltage
Input LOW Voltage
V
V
= V to V
SS CC
LI
IN
= V to V
CC
LO
OUT
SS
V
x 0.7
V
+0.5
V
V
V
CC
CC
V
IH
IL
–0.5
x
V
CC
0.4
V
Output LOW Voltage
I
= 3mA
OL
OL
ENDURANCE AND DATA RETENTION
Parameter
Minimum Endurance
Data Retention
Min.
Units
100,000
100
Data Changes per Bit per Register
Years
CAPACITANCE
Symbol
Test
Input/Output Capacitance (SDA)
Typical
Units
pF
Test Conditions
8
6
V
= 0V
= 0V
C
C
I/O
I/O
pF
V
IN
Input Capacitance (A0, A1, A2, A3, and
Potentiometer Capacitance
IN
10/10/25
pF
see SPICE model
C | C | C
W
L
H
POWER-UP TIMING AND SEQUENCE
Power Up Sequence(1): (1) V
(2) V+ and V–
CC
Power Down Sequence: no limitation
A.C. TEST CONDITIONS
R
V
x 0.1 to V x 0.9
CC
TOTAL
Input Pulse Levels
CC
R
L
R
H
C
L
Input Rise and Fall Times
10ns
C
C
W
H
Input and Output Timing
Level
V
x 0.5
CC
Notes: (1) Applicable to recall and power consumption applications
R
W
EQUIVALENT A.C. LOAD CIRCUIT
SPICE Macromodel
5V
2.7V
1533W
100pF
SDA OUTPUT
100pF
11
X9438
Preliminary
TIMING DIAGRAMS
FIGURE 4. START and STOP Timing
g
(START)
(STOP)
t
t
F
R
SCL
t
t
t
SU:STO
SU:STA
HD:STA
t
t
R
F
SDA
FIGURE 5. Input Timing
t
t
CYC
HIGH
SCL
SDA
t
LOW
t
t
t
BUF
SU:DAT
HD:DAT
FIGURE 6. Output Timing
SCL
SDA
t
t
DH
AA
FIGURE 7. DCP Timing (for All Load Instructions)
(STOP)
SCL
SDA
RWx
LSB
t
WRL
12
X9438
Preliminary
FIGURE 1. DCP Timing (for Increment/Decrement Instruction)
SCL
Wiper Register Address
Inc/Dec
Inc/Dec
SDA
RWx
t
WRID
FIGURE 2. Write Protect and Device Address Pins Timing
(START)
SCL
(STOP)
...
(Any Instruction)
...
SDA
...
t
t
SU:WPA
HD:WPA
WP
A0, A1
A2, A3
13
X9438
Preliminary
AC TIMING
Symbol
Parameter
Min.
Max.
400
Units
kHz
ns
f
t
t
t
t
t
t
t
t
t
t
t
t
Clock Frequency
SCL
Clock Cycle Time
2500
600
CYC
Clock High Time
ns
HIGH
Clock Low Time
1300
600
ns
LOW
Start Setup Time
ns
SU:STA
HD:STA
SU:STO
SU:DAT
Start Hold Time
600
ns
Stop Setup Time
600
ns
SDA Data Input Setup Time
SDA Data Input Hold Time
SCL and SDA Rise Time
SCL and SDA Fall Time
100
ns
(4)
0/30
ns
HD:DAT
300
300
900
ns
R
ns
F
SCL Low to SDA Data Output Valid Time
SDA Data Output Hold Time
100
50
ns
AA
DH
ns
T
Noise Suppression Time Constant at
SCL and SDA inputs
50
ns
I
t
t
t
Bus Free Time (Prior to Any Transmission)
WP, A0, A1, A2 and A3 Setup Time
WP, A0, A1, A2 and A3 Hold Time
1300
ns
ns
ns
BUF
0
0
SU:WPA
HD:WPA
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
Parameter
Typ.
5
Max.
10
Units
ms
t
High-voltage Write Cycle Time (Store Instructions)
WR
DCP TIMING
Symbol
Parameter
Min.
Max. Units
10 µs
t
Wiper Response Time After Instruction Issued (All Load Instructions)
WRL
Notes: (4) V = 5V/2.7V
CC
V
RAMP (sample tested)
CC
Symbol
trV
Parameter
Typ.
Max.
Units
V/mSec
V
Power—Up Rate
.2
50
CC
CC
14
X9438
Preliminary
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
+V
R
V
R
V
W
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Application Circuits
Noninverting Amplifier
Voltage Regulator
V
+
–
S
V
V
V (REG)
O
317
O
IN
R
1
R
2
I
adj
R
R
1
2
V
= (1+R /R )V
V
(REG) = 1.25V (1+R /R )+I
R
O
2
1
S
O
2
1
adj 2
Offset Voltage Adjustment
Comparator with Hysterisis
R
R
2
1
V
–
+
S
V
V
S
O
100KΩ
–
+
V
O
TL072
R
R
1
2
10KΩ
10KΩ
+12V
V
V
= {R /(R +R )} V (max)
1 1 2 O
UL
LL
10KΩ
-12V
= {R /(R +R )} V (min)
1
1
2
O
15
X9438
Preliminary
BASIC APPLICATIONS (continued)
I to V Converter
Attenuator
R
3
R
R
R
R
2
1
3
2
R
1
Ð
+
V
O
Ð
+
V
S
V
O
R
4
R
R
= R = R
3 4
1
2
= 2R
1
V /I = -R (1 + R /R ) + R
O S
3
2
1
2
V
= G V
S
O
-1/2 ≤ G ≤ +1/2
Phase Shifter
Absolute Value Amplifier with Gain
2R
R
1
R
1
Ð
+
V
V
S
S
V
R
R
R
R
O
1
Ð
+
Ð
+
C
V
O
R
A
A
2
1
R
1
V
= |V |
S
O
R
V /V = 180°–2tan-1ωRC
O
S
Function Generator
C
R
R
1
2
Ð
+
Ð
+
R
R
}
}
A
B
frequency R , R , C
1
2
amplitude R , R
A
B
16
X9438
Preliminary
PACKAGING INFORMATION
24-LEAD PLASTIC, TSSOP PACKAGE TYPE V
.026 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.303 (7.70)
.311 (7.90)
.047 (1.20)
.0075 (.19)
.002 (.06)
.0118 (.30)
.005 (.15)
.010 (.25)
Gage Plane
0° Ð 8°
Seating Plane
.020 (.50)
.030 (.75)
DetailA (20X)
.031 (.80)
.041 (1.05)
See Detail ÒAÓ
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
17
X9438
Preliminary
PACKAGING INFORMATION
24-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.290 (7.37)
0.299 (7.60)
0.393 (10.00)
0.420 (10.65)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.020 (0.50)
0.598 (15.20)
0.610 (15.49)
(4X) 7¡
0.092 (2.35)
0.105 (2.65)
0.003 (0.10)
0.012 (0.30)
0.050 (1.27)
0.050" TYPICAL
0.010 (0.25)
0.020 (0.50)
X 45¡
0.050"
TYPICAL
0¡ Ð 8¡
0.009 (0.22)
0.013 (0.33)
0.420"
0.015 (0.40)
0.050 (1.27)
0.030" TYPICAL
24 PLACES
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
7023 FRM F14
18
X9438
Preliminary
ORDERING INFORMATION
X9438
Y
P
T
V
V
Limits
CC
Device
Blank = 5V ±10%
–2.7 = 2.7 to 5.5V
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
Package
S24 = 24-Lead SOIC
V24 = 24-Lead TSSOP
Potentiometer Organization
Pot 0
Pot 1
W = 10KΩ 10KΩ
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemniÞcation provisions appearing in its Terms of Sale only. Xicor, Inc.
makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the
described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or Þtness for any purpose. Xicor, Inc. reserves the
right to discontinue production and change speciÞcations and prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967;
4,883, 976. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prevent such an occurence.
XicorÕs products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain
life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably
expected to result in a signiÞcant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system, or to affect its safety or effectiveness.
19
相关型号：
X9438WS24I
DUAL 10K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO24, PLASTIC, SOIC-24
RENESAS
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