X9523B20I-A [XICOR]
Digital Potentiometer, 1 Func, CMOS, PBGA20, BGA-20;
| 型号： | X9523B20I-A |
| 厂家： | 
XICOR INC. |
| 描述： | Digital Potentiometer, 1 Func, CMOS, PBGA20, BGA-20 转换器 |
| 文件： | 总31页 (文件大小：187K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Hot Pluggable
Preliminary Information
X9523
Laser Diode Control for Fiber Optic Modules
Dual DCP, POR, Dual Voltage Monitors
FEATURES
DESCRIPTION
• Two Digitally Controlled Potentiometers (DCPs)
—100 Tap - 10 kΩ
The X9523 combines two Digitally Controlled Potentiome-
ters (DCPs), V1 / Vcc Power On Reset (POR) circuitry, qnd
two programmable voltage monitor inputs with software and
hardware indicators. All functions of the X9523 are
accessed by an industry standard 2-Wire serial interface.
—256 Tap - 100 kΩ
—Nonvolatile
—Write Protect Function
• 2-Wire industry standard Serial Interface
• Power On Reset (POR) Circuitry
—Programmable Threshold Voltage
—Software Selectable reset timeout
—Manual Reset
• Two Supplementary Voltage Monitors
—Programmable Threshold Voltages
• Single Supply Operation
—2.7 V to 5.5 V
The DCPs of the X9523 may be utilized to control the bias
and modulation currents of the laser diode in a Fiber Optic
module. The programmable POR circuit may be used to
ensure that V1 / Vcc is stable before power is applied to the
laser diode / module. The programmable voltage monitors
may be used for monitoring various module alarm levels.
The features of the X9523 are ideally suited to simplifying
the design of fiber optic modules . The integration of these
functions into one package significantly reduces board
area, cost and increases reliability of laser diode modules.
• Hot Pluggable
• 20 Pin packages
—XBGATM
—TSSOP
BLOCK DIAGRAM
R
R
R
H1
W1
L1
WIPER
COUNTER
REGISTER
PROTECT LOGIC
WP
7 - BIT
NONVOLATILE
MEMORY
DATA
REGISTER
8
SDA
COMMAND
DECODE &
R
CONSTAT
REGISTER
H2
WIPER
COUNTER
REGISTER
CONTROL
SCL
R
R
W2
L2
LOGIC
THRESHOLD
RESET LOGIC
8 - BIT
NONVOLATILE
MEMORY
MR
2
V3RO
V2RO
V1RO
V3
-
+
VTRIP3
VTRIP2
VTRIP1
V2
-
+
POWER ON /
LOW VOLTAGE
RESET
V1 / Vcc
+
-
GENERATION
©2000 Xicor Inc., Patents Pending
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X9523 – Preliminary Information
DETAILED DEVICE DESCRIPTION
Two supplementary Voltage Monitor circuits continuously
compare their inputs to individual trip voltages. If an input
voltage exceeds it’s associated trip level, a hardware out-
put (V3RO, V2RO) are allowed to go HIGH. If the input
voltage becomes lower than it’s associated trip level, the
corresponding output is driven LOW. A corresponding
binary representation of the two monitor circuit outputs
(V2RO and V3RO) are also stored in latched, volatile
(CONSTAT) register bits. The status of these two monitor
outputs can be read out via the 2-wire serial port.
The X9523 combines two Xicor Digitally Controlled
Potentiometer (DCP) devices, V1 / Vcc power on reset
control, V1 / Vcc low voltage reset control, and two sup-
plementary voltage monitors in one package. These func-
tions are suited to the control, support, and monitoring of
various system parameters in fiber optic modules. The
combination of the X9523 fucntionality lowers system
cost, increases reliability, and reduces board space
requirements using Xicor’s unique XBGA™ packaging.
Xicor’s unique circuits allow for all internal trip voltages to
be individually programmed with high accuracy.This gives
the designer great flexibility in changing system parame-
ters, either at the time of manufacture, or in the field.
Two high resolution DCPs allow for the “set-and-forget”
adjustment of Laser Driver IC parameters such as Laser
Diode Bias and Modulation Currents.
Applying voltage to V activates the Power On Reset cir-
CC
The device features a 2-Wire interface and software pro-
tocol allowing operation on an I2C™ compatible serial
bus.
cuit which allows the V1RO output to go HIGH, until the
supply the supply voltage stabilizes for a period of time
(selectable via software). The V1RO output then goes
LOW. The Low Voltage Reset circuitry allows the V1RO
output to go HIGH when V
falls below the minimum
CC
V
trip point. V1RO remains HIGH until V
returns to
CC
CC
proper operating level. A Manual Reset (MR) input allows
the user to externally trigger the V1RO output (HIGH).
PIN CONFIGURATION
XBGA
20 Pin TSSOP
1
2
3
4
V1 / Vcc
V1RO
R
R
20
19
18
17
H2
1
2
3
4
W2
V2RO V1 / Vcc
R
R
L2
W2
A
B
C
D
E
R
V3
V3RO
V2RO
V2
NC
L2
V2
R
H2
V1RO
V3
V3RO WP
5
6
16
15
14
13
12
11
NC
NC
NC
MR
NC
WP
R
SCL
MR
H1
7
8
NC
SCL
R
H1
R
V
R
SDA
W1
SS
L1
SDA
9
R
W1
V
R
SS
10
L1
Top View – Bumps Down
NOT TO SCALE
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X9523 – Preliminary Information
PIN ASSIGNMENT
Pin
1
XBGA
B3
Name
Function
R
Connection to end of resistor array for (the 256 Tap) DCP 2.
H2
R
2
A3
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 2.
Connection to other end of resistor array for (the 256 Tap) DCP2.
V3 Voltage Monitor Input. V3 is the input to a non-inverting voltage comparator circuit.
w2
R
3
A4
L2
When the V3 input is higher than the V
threshold voltage, V3RO makes a transition
4
5
B4
C3
V3
TRIP3
to a HIGH level. Connect V3 to V when not used.
SS
V3 RESET Output. This open drain output makes a transition to a HIGH level when V3 is
greater than V
and goes LOW when V3 is less than VTRIP3. There is no delay cir-
V3RO
TRIP3
cuitry on this pin. The V3RO pin requires the use of an external “pull-up” resistor.
Manual Reset. MR is a TTL level compatible input. Pulling the MR pin active (HIGH) ini-
tiates a reset cycle to the V1RO pin (V1 / Vcc RESET Output pin).V1RO will remain HIGH
for time t
after MR has returned to it’s normally LOW state. The reset time can be se-
6
7
D3
C4
MR
purst
lected using bits POR1 and POR0 in the CONSTAT Register.The MR pin requires the use
of an external “pull-down” resistor.
Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write
Protection is enabled. In the enabled state, this pin prevents all nonvolatile “write” opera-
tions. Also, when the Write Protection is enabled, and the device DCP Write Lock feature is
active (i.e. the DCP Write Lock bit is “1”), then no “write” (volatile or nonvolatile) operations
can be performedon the wiper position of any of the integrated Digitally Controlled Potenti-
ometers (DCPs). The WP pin uses an internal “pull-down” resistor, thus if left floating the
write protection feature is disabled.
WP
Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing
for data input and output.
8
9
D4
E4
SCL
Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and
out of the device. The SDA pin input buffer is always active (not gated). This pin requires
an external pull up resistor.
SDA
Vss
10
11
12
13
E1
E3
E2
D1
Ground.
R
Connection to other end of resistor for (the 100 Tap) DCP 1.
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 1
Connection to end of resistor array for (the 100 Tap) DCP 1.
V2 Voltage Monitor Input. V2 is the input to a non-inverting voltage comparator circuit.
L1
R
w1
R
H1
When the V2 input is greater than theV
threshold voltage, V2RO makes a transition
17
18
B1
A1
V2
TRIP2
to a HIGH level. Connect V2 to V when not used.
SS
V2 RESET Output. This open drain output makes a transition to a HIGH level when V2 is
greater than V
, and goes LOW when V2 is less than V
.There is no power up
TRIP2
TRIP2
V2RO
reset delay circuitry on this pin. The V2RO pin requires the use of an external “pull-up” re-
sistor.
V1 / Vcc RESET Output.This is an active HIGH, open drain output which becomes active
whenever V1 / Vcc falls below V
. V1RO becomes active on power up and remains
after the power supply stabilizes (t can be changed by varying
purst
TRIP1
active for a time t
purst
19
20
B2
A2
V1RO
the POR0 and POR1 bits of the internal control register). The V1RO pin requires the use
of an external “pull-up” resistor.The V1RO pin can be forced active (HIGH) using the man-
ual reset (MR) input pin.
V1 / Vcc
NC
Supply Voltage.
No Connect
14, 15,
16,
C1, C2,
D2
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X9523 – Preliminary Information
SCL
SDA
Data Stable
Data Change
Data Stable
Figure 1. Valid Data Changes on the SDA Bus
PRINCIPLES OF OPERATION
SERIAL INTERFACE
Serial Stop Condition
All communications must be terminated by a STOP condi-
tion, which is a LOW to HIGH transition of SDA while SCL
is HIGH. The STOP condition is also used to place the
device into the Standby power mode after a read
sequence. A STOP condition can only be issued after the
transmitting device has released the bus. See Figure 2.
Serial Interface Conventions
The device supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter, and the receiving device as the
receiver. The device controlling the transfer is called the
master and the device being controlled is called the slave.
The master always initiates data transfers, and provides
the clock for both transmit and receive operations. There-
fore, the X9523 operates as a slave in all applications.
Serial Acknowledge
An ACKNOWLEDGE (ACK) is a software convention
used to indicate a successful data transfer. The transmit-
ting device, either master or slave, will release the bus
after transmitting eight bits. During the ninth clock cycle,
the receiver will pull the SDA line LOW to ACKNOWL-
EDGE that it received the eight bits of data. Refer to Fig-
ure 3.
Serial Clock and Data
Data states on the SDA line can change only while SCL is
LOW. SDA state changes while SCL is HIGH are
reserved for indicating START and STOP conditions. See
Figure 1.On power up of the X9523, the SDA pin is in the
input mode.
The device will respond with an ACKNOWLEDGE after
recognition of a START condition if the correct Device
Identifier bits are contained in the Slave Address Byte. If a
write operation is selected, the device will respond with an
ACKNOWLEDGE after the receipt of each subsequent
eight bit word.
Serial Start Condition
All commands are preceded by the START condition,
which is a HIGH to LOW transition of SDA while SCL is
HIGH. The device continuously monitors the SDA and
SCL lines for the START condition and does not respond
to any command until this condition has been met. See
Figure 2.
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
ACKNOWLEDGE. If an ACKNOWLEDGE is detected
and no STOP condition is generated by the master, the
device will continue to transmit data.The device will termi-
SCL
SDA
Start
Stop
Figure 2. Valid Start and Stop Conditions
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X9523 – Preliminary Information
SCL
from
Master
1
8
9
Data Output
from
Transmitter
Data Output
from
Receiver
Start
Acknowledge
Figure 3. Acknowledge Response From Receiver
nate further data transmissions if an ACKNOWLEDGE is
not detected. The master must then issue a STOP condi-
tion to place the device into a known state.
—The next three bits (SA3 - SA1) are the Internal Device
Address bits. Setting these bits to 111 internally selects
the DCP structures in the X9523.The CONSTAT Regis-
ter may be selected using the Internal Device Address
010.
DEVICE INTERNAL ADDRESSING
Addressing Protocol Overview
—The Least Significant Bit of the Slave Address (SA0)
Byte is the R/W bit. This bit defines the operation to be
performed on the device being addressed (as defined
in the bits SA3 - SA1). When the R/W bit is “1”, then a
READ operation is selected. A “0” selects a WRITE
operation (Refer to Figure 4.)
The user addressable internal components of the X9523
can be split up into two main parts:
—Two Digitally Controlled Potentiometers (DCPs)
—Control and Status (CONSTAT) Register
Depending upon the operation to be performed on each
of these individual parts, a 1, 2 or 3 Byte protocol is used.
All operations however must begin with the Slave Address
Byte being issued on the SDA pin. The Slave address
selects the part of the X9523 to be addressed, and speci-
fies if a Read or Write operation is to be performed.
SA7 SA6
SA3 SA2
SA5 SA4
SA1
SA0
R/W
1 0 1 0
READ /
WRITE
INTERNAL
DEVICE TYPE
IDENTIFIER
DEVICE
It should be noted that in order to perform a write opera-
tion to a DCP, the Write Enable Latch (WEL) bit must first
be set (See “WEL: Write Enable Latch (Volatile)” on
page 10.).
ADDRESS
Internally Addressed
Device
Internal Address
(SA3 - SA1)
CONSTAT Register
DCP
010
111
Slave Address Byte
Following a START condition, the master must output a
Slave Address Byte (Refer to Figure 4.). This byte con-
sists of three parts:
RESERVED
All Others
—The Device Type Identifier which consists of the most
significant four bits of the Slave Address (SA7 - SA4).
The Device Type Identifier must always be set to 1010
in order to select the X9523.
Bit SA0
Operation
WRITE
0
1
READ
Figure 4. Slave Address Format
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X9523 – Preliminary Information
Nonvolatile Write Acknowledge Polling
After a nonvolatile write command sequence (for either
the Non Volatile Memory of a DCP (NVM), or the CON-
STAT Register) has been correctly issued (including the
final STOP condition), the X9523 initiates an internal high
voltage write cycle.This cycle typically requires 5 ms. Dur-
ing this time, no further Read or Write commands can be
issued to the device.Write Acknowledge Polling is used to
determine when this high voltage write cycle has been
completed.
R
N
Hx
WIPER
COUNTER
REGISTER
(WCR)
“WIPER”
FET
SWITCHES
RESISTOR
ARRAY
DECODER
To perform acknowledge polling, the master issues a
START condition followed by a Slave Address Byte. The
Slave Address issued must contain a valid Internal Device
Address. The LSB of the Slave Address (R/W) can be set
to either 1 or 0 in this case. If the device is still busy with
the high voltage cycle then no ACKNOWLEDGE will be
returned. If the device has completed the write operation,
an ACKNOWLEDGE will be returned and the host can
then proceed with a read or write operation. (Refer to
Figure 5.).
2
1
0
NON
VOLATILE
MEMORY
(NVM)
R
R
Lx
Wx
Figure 6. DCP Internal Structure
DIGITALLY CONTROLLED POTENTIOMETERS
DCP Functionality
Byte load completed
by issuing STOP.
Enter ACK Polling
The X9523 includes two independent resistor arrays.
These arrays respectively contain 99 and 255 discrete
resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
Issue START
terminals of a mechanical potentiometer (R and R
inputs - where x = 1,2).
Hx
Lx
Issue Slave Address
Byte (Read or Write)
Issue STOP
At both ends of each array and between each resistor
segment there is a CMOS switch connected to the wiper
NO
(R ) output.Within each individual array, only one switch
x
w
ACK
returned?
may be turned on at any one time. These switches are
controlled by the Wiper Counter Register (WCR) (See
Figure 6).The WCR is a volatile register.
YES
On power up of the X9523, wiper position data is auto-
matically loaded into the WCR from its associated Non
Volatile Memory (NVM) Register. The Table below shows
the Initial Values of the DCP WCR’s before the contents of
the NVM is loaded into the WCR.
High Voltage Cycle
complete. Continue
command sequence?
NO
Issue STOP
YES
DCP
R / 100 TAP
Initial Values Before Recall
V / TAP = 0
Continue normal
Read or Write
command sequence
1
L
R / 256 TAP
V / TAP = 255
H
2
PROCEED
The data in the WCR is then decoded to select and
enable one of the respective FET switches. A “make
before break” sequence is used internally for the FET
Figure 5.
Acknowledge Polling Sequence
Characteristics subject to change without notice. 6 of 31
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X9523 – Preliminary Information
V1 / Vcc
V1 / Vcc (Max.)
V
TRIP1
t
t
trans
purst
t
0
Maximum Wiper Recall time
Figure 7. DCP Power up
switches when the wiper is moved from one tap position
to another.
WCR only. The contents of the associated NVM register
remains unchanged. Therefore, when V1 / Vcc to the
device is powered down then back up, the “wiper position”
reverts to that last position written to the DCP using a
nonvolatile write operation.
Hot Pluggability
Figure 7 shows a typical waveform that the X9523 might
experience in a Hot Pluggable situation. On power up, V1
/ Vcc applied to the X9523 may exhibit some amount of
ringing, before it settles to the required value.
Both volatile and nonvolatile write operations are
executed using a three byte command sequence: (DCP)
Slave Address Byte, Instruction Byte, followed by a Data
Byte (See Figure 9)
The device is designed such that the wiper terminal (R
)
Wx
is recalled to the correct position (as per the last stored in
the DCP NVM), when the voltage applied to V1 / Vcc
A DCP Read operation allows the user to “read out” the
current “wiper position” of the DCP, as stored in the
associated WCR. This operation is executed using the
Random Address Read command sequence, consisting
of the (DCP) Slave Address Byte followed by an
Instruction Byte and the Slave Address Byte again (Refer
to Figure 10.).
exceeds V
for a time exceeding t
(the Power On
purst
TRIP1
Reset time, set in the CONSTAT Register - See “CON-
TROL AND STATUS REGISTER” on page 10.).
Therefore, if t
trans
is defined as the time taken for V1 / Vcc
to settle above V
(Figure 7): then the desired wiper
TRIP1
terminal position is recalled by (a maximum) time: t
+
trans
is determined by sys-
t
. It should be noted that t
purst
trans
Instruction Byte
tem hot plug conditions.
While the Slave Address Byte is used to select the DCP
devices, an Instruction Byte is used to determine which
DCP is being addressed.
DCP Operations
In total there are three operations that can be performed
on any internal DCP structure:
The Instruction Byte (Figure 8) is valid only when the
Device Type Identifier and the Internal Device Address
bits of the Slave Address are set to 1010111. In this
case, the two Least Significant Bit’s (I1 - I0) of the
Instruction Byte are used to select the particular DCP (0
- 2). In the case of a Write to any of the DCPs (i.e. the LSB
of the Slave Address is 0), the Most Significant Bit of the
Instruction Byte (I7), determines the Write Type (WT) per-
formed.
—DCP Nonvolatile Write
—DCP Volatile Write
—DCP Read
A nonvolatile write to a DCP will change the “wiper
position” by simultaneously writing new data to the
associated WCR and NVM. Therefore, the new “wiper
position” setting is recalled into the WCR after V1 / Vcc of
the X9523 is powered down and then powered back up.
If WT is “1”, then a Nonvolatile Write to the DCP occurs. In
this case, the “wiper position” of the DCP is changed by
simultaneously writing new data to the associated WCR
and NVM. Therefore, the new “wiper position” setting is
A volatile write operation to a DCP however, changes the
“wiper position” by writing new data to the associated
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X9523 – Preliminary Information
returned by the X9523 after the Slave Address, if it has
been received correctly.
I7
I6
0
I5
0
I4
0
I3
0
I2
0
I1
P1
I0
P0
WT
Next, an Instruction Byte is issued on SDA. Bits P1 and
P0 of the Instruction Byte determine which WCR is to be
written, while the WT bit determines if the Write is to be
volatile or nonvolatile. If the Instruction Byte format is
valid, another ACKNOWLEDGE is then returned by the
X9523.
WRITE TYPE
DCP SELECT
WT†
Description
Select a Volatile Write operation to be performed
on the DCP pointed to by bits P1 and P0
Following the Instruction Byte, a Data Byte is issued to the
X9523 over SDA. The Data Byte contents is latched into
the WCR of the DCP on the first rising edge of the clock
signal, after the LSB of the Data Byte (D0) has been
issued on SDA (See Figure 29).
0
Select a Nonvolatile Write operation to be per-
formed on the DCP pointed to by bits P1 and P0
1
†
This bit has no effect when a Read operation is being performed.
The Data Byte determines the “wiper position” (which
FET switch of the DCP resistive array is switched ON) of
the DCP. The maximum value for the Data Byte depends
upon which DCP is being addressed (see Table below).
Figure 8. Instruction Byte Format
recalled into the WCR after V1 / Vcc of the X9523 has
been powered down then powered back up.
P1- P0
DCPx
# Taps
Max. Data Byte
0
0
1
1
0
1
0
1
RESERVED
If WT is “0” then a DCP Volatile Write is performed. This
operation changes the DCP “wiper position” by writing
new data to the associated WCR only.The contents of the
associated NVM register remains unchanged. Therefore,
when V1 / Vcc to the device is powered down then back
up, the “wiper position” reverts to that last written to the
DCP using a nonvolatile write operation.
x=1
x=2
100
256
Refer to Appendix 1
FFh
RESERVED
Using a Data Byte larger than the values specified above
results in the “wiper terminal” being set to the highest tap
position. The “wiper position” does NOT roll-over to the
lowest tap position.
DCP Write Operation
A write to DCPx (x=1,2) can be performed using the three
byte command sequence shown in Figure 9.
For DCP2 (256 Tap), the Data Byte maps one to one to
the “wiper position” of the DCP “wiper terminal”. There-
fore, the Data Byte 00001111 (15 ) corresponds to set-
ting the “wiper terminal” to tap position 15. Similarly, the
Data Byte 00011100 (28 ) corresponds to setting the
In order to perform a write operation on a particular DCP,
the Write Enable Latch (WEL) bit of the CONSTAT Regis-
ter must first be set (See “WEL: Write Enable Latch (Vola-
tile)” on page 10.)
10
10
“wiper terminal” to tap position 28. The mapping of the
Data Byte to “wiper position” data for DCP1 (100 Tap), is
shown in “APPENDIX 1”. An example of a simple C lan-
The Slave Address Byte 10101110 specifies that a Write
to a DCP is to be conducted. An ACKNOWLEDGE is
1
0
1
0
1
1
1
0
D7 D6 D5 D4 D3 D2 D1 D0
DATA BYTE
S
T
A
R
T
A
C
K
WT
0
0
0
0
0
P1 P0
A
C
K
A
C
K
S
T
O
P
SLAVE ADDRESS BYTE
INSTRUCTION BYTE
Figure 9. DCP Write Command Sequence
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X9523 – Preliminary Information
WRITE Operation
READ Operation
S
t
S
t
S
t
o
p
Signals from
the Master
Instruction
Byte
Slave
Slave
Address
a
r
a
r
Address
Data Byte
t
t
SDA Bus
P
0
10101110 W 00000 P1
10101111
T
A
C
K
A
C
K
A
C
K
Signals from
the Slave
DCPx
x = 1
-
“Dummy” write
x = 2
LSB
MSB
“-” = DON’T CARE
Figure 10. DCP Read Sequence
guage function which “translates” between the tap posi-
tion (decimal) and the Data Byte (binary) for DCP1, is
given in “APPENDIX 2”.
The master issues the START condition and the Slave
Address Byte 10101110 which specifies that a “dummy”
write” is to be conducted. This “dummy” write operation
sets which DCP is to be read (in the preceding Read
operation). An ACKNOWLEDGE is returned by the
X9523 after the Slave Address if received correctly. Next,
an Instruction Byte is issued on SDA. Bits P1-P0 of the
Instruction Byte determine which DCP “wiper position” is
to be read. In this case, the state of the WT bit is “don’t
care”. If the Instruction Byte format is valid, then another
ACKNOWLEDGE is returned by the X9523.
It should be noted that all writes to any DCP of the X9523
are random in nature.Therefore, the Data Byte of consec-
utive write operations to any DCP can differ by an arbi-
trary number of bits. Also, setting the bits P1=1, P0=1 is a
reserved sequence, and will result in no ACKNOWL-
EDGE after sending an Instruction Byte on SDA.
The factory default setting of all “wiper position” settings is
with 00h stored in the NVM of the DCPs. This corre-
Following this ACKNOWLEDGE, the master immediately
issues another START condition and a valid Slave
address byte with the R/W bit set to 1. Then the X9523
issues an ACKNOWLEDGE followed by Data Byte, and
finally, the master issues a STOP condition. The Data
Byte read in this operation, corresponds to the “wiper
position” (value of the WCR) of the DCP pointed to by bits
P1 and P0.
sponds to having the “wiper teminal” R
(x=1,2) at the
WX
“lowest” tap position, Therefore, the resistance between
and R is a minimum (essentially only the Wiper
R
WX
LX
Resistance, R ).
W
DCP Read Operation
A read of DCPx (x=1,2) can be performed using the three
byte random read command sequence shown in Figure
10.
S
t
a
r
WRITE Operation
S
t
o
p
Signals from
the Master
Address
Byte
Slave
Address
Data
Byte
t
SDA Bus
0 1
0 0
0
1
0 0
A
C
K
A
C
K
A
C
K
Internal
Signalsfrom
the Slave
Device
Address
Figure 11. EEPROM Byte Write Sequence
Characteristics subject to change without notice. 9 of 31
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X9523 – Preliminary Information
The WEL bit is a volatile latch that powers up in the dis-
abled, LOW (0) state.The WEL bit is enabled / set by writ-
ing 00000010 to the CONSTAT register. Once enabled,
the WEL bit remains set to “1” until either it is reset to “0”
(by writing 00000000 to the CONSTAT register) or until
the X9523 powers down, and then up again.
CS3
CS7 CS6
CS4
0
CS5
CS2 CS1 CS0
POR1
NV
V2OS V3OS
DWLK RWEL
NV
WEL
POR0
NV
Writes to the WEL bit do not cause an internal high volt-
age write cycle. Therefore, the device is ready for another
operation immediately after a STOP condition is executed
in the CONSTAT Write command sequence (See Figure
13).
Bit(s)
Description
POR1
V2OS
V1OS
CS4
Power On Reset bit
V2 Output Status flag
V1 Output Status flag
RWEL: Register Write Enable Latch (Volatile)
Always set to “0” (RESERVED)
Sets the DCP Write Lock
Register Write Enable Latch bit
Write Enable Latch bit
The RWEL bit controls the (CONSTAT) Register Write
Enable status of the X9523. Therefore, in order to write to
any of the bits of the CONSTAT Register (except WEL),
the RWEL bit must first be set to “1”. The RWEL bit is a
volatile bit that powers up in the disabled, LOW (“0”) state.
DWLK
RWEL
WEL
POR0
Power On Reset bit
NOTE: Bits labelled NV are nonvolatile (See “CONTROLAND STATUS REGISTER”).
It must be noted that the RWEL bit can only be set, once
the WEL bit has first been enabled (See "CONSTAT Reg-
ister Write Operation").
Figure 12. CONSTAT Register Format
The RWEL bit will reset itself to the default “0” state, in
one of two cases:
It should be noted that when reading out the data byte for
DCP1 (100 Tap), the upper most significant bit is an
“unknown”. For DCP2 (256 Tap) however, all bits of the
data byte are relevant (See Figure 10).
—After a successful write operation to any bits of the
CONSTAT register has been completed (See Figure
13).
CONTROL AND STATUS REGISTER
—When the X9523 is powered down.
The Control and Status (CONSTAT) Register provides the
user with a mechanism for changing and reading the sta-
tus of various parameters of the X9523 (See Figure 12).
DWLK: DCP Write Lock bit - (Nonvolatile)
The DCP Write Lock bit (DWLK) is used to inhibit a DCP
write operation (changing the “wiper position”).
The CONSTAT register is a combination of both volatile
and nonvolatile bits. The nonvolatile bits of the CONSTAT
register retain their stored values even when V1 / Vcc is
powered down, then powered back up. The volatile bits
however, will always power up to a known logic state “0”
(irrespective of their value at power down).
When the DCP Write Lock bit of the CONSTAT register is
set to “1”, then the “wiper position” of the DCPs cannot be
changed - i.e. DCP write operations cannot be conducted:
DWLK
DCP Write Operation Permissible
A detailed description of the function of each of the CON-
STAT register bits follows:
0
1
YES (Default)
NO
WEL:Write Enable Latch (Volatile)
The factory default setting for this bit is DWLK= 0.
The WEL bit controls the Write Enable status of the entire
X9523 device. This bit must first be enabled before ANY
write operation (to DCPs, or the CONSTAT register). If the
WEL bit is not first enabled, then ANY proceeding (volatile
or nonvolatile) write operation to DCPs or the CONSTAT
register, is aborted and no ACKNOWLEDGE is issued
after a Data Byte.
IMPORTANT NOTE: If the Write Protect (WP) pin of the
X9523 is active (HIGH), then nonvolatile write operations
to the DCPs are inhibited, irrespective of the DCP Write
Lock bit setting (See "WP:Write Protection Pin").
Characteristics subject to change without notice. 10 of 31
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X9523 – Preliminary Information
SCL
SDA
CS0
CS2CS1
1
CS7 CS6
S
T
A
R
T
1
0
1
0
0
1
0
R/W A
1
1
1
1
1
1
1
A
C
K
CS5 CS4 CS3
A
C
K
S
T
O
P
C
K
SLAVE ADDRESS BYTE
ADDRESS BYTE
CONSTAT REGISTER DATA IN
Figure 13. CONSTAT Register Write Command Sequence
POR1, POR0: Power On Reset bits - (Nonvolatile)
Once the VxOS bits have been set to “1”, they will be
reset to “0” if:
Applying voltage to V activates the Power On Reset cir-
CC
cuit which holds V1RO output HIGH, until the supply volt-
—The device is powered down, then back up,
age stabilizes above the V
threshold for a period of
TRIP1
—The corresponding VxRO output becomes LOW.
time, t
(See Figure 25).
PURST
The Power On Reset bits, POR1 and POR0 of the CON-
STAT register determine the t delay time of the
Power On Reset circuitry (See "VOLTAGE MONITORING
FUNCTIONS"). These bits of the CONSTAT register are
nonvolatile, and therefore power up to the last written
state.
CONSTAT Register Write Operation
PURST
The CONSTAT register is accessed using the Slave
Address set to 1010010 (Refer to Figure 4.). Following the
Slave Address Byte, access to the CONSTAT register
requires an Address Byte which must be set to FFh. Only
one data byte is allowed to be written for each CONSTAT
register Write operation. The user must issue a STOP,
after sending this byte to the register, to initiate the nonvol-
atile cycle that stores the DWLK, POR1 and POR0 bits.
The X9523 will not ACKNOWLEDGE any data bytes writ-
ten after the first byte is entered (Refer to Figure 13.).
The nominal Power On Reset delay time can be selected
from the following table, by writing the appropriate bits to
the CONSTAT register:
Power on Reset delay (t
)
POR1 POR0
PUV1RO
0
0
1
1
0
1
0
1
50ms
100ms (Default)
200ms
When writing to the CONSTAT register, the bit CS4 must
always be set to “0”. Writing a “1” to bit CS4 of the CON-
STAT register is a reserved operation.
300ms
Prior to writing to the CONSTAT register, the WEL and
RWEL bits must be set using a two step process, with the
whole sequence requiring 3 steps
The default for these bits are POR1 = 0, POR0 = 1.
—Write a 02H to the CONSTAT Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation preceded by
a START and ended with a STOP).
V2OS, V3OS:Voltage Monitor Status Bits (Volatile)
Bits V2OS and V3OS of the CONSTAT register are
latched, volatile flag bits which indicate the status of the
Voltage Monitor reset output pins V2RO and V3RO.
—Write a 06H to the CONSTAT Register to set the Regis-
ter Write Enable Latch (RWEL) AND the WEL bit. This
is also a volatile cycle. The zeros in the data byte are
required. (Operation preceded by a START and ended
with a STOP).
At power up the VxOS (x=2,3) bits default to the value “0”.
These bits can be set to a “1” by writing the appropriate
value to the CONSTAT register. To provide consistency
between the VxRO and VxOS however, the status of the
VxOS bits can only be set to a “1” when the correspond-
ing VxRO output is HIGH.
Characteristics subject to change without notice. 11 of 31
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X9523 – Preliminary Information
READ Operation
WRITE Operation
S
t
S
t
S
t
o
p
Signals from
the Master
Slave
Address
Address
Byte
Slave
Address
a
r
a
r
t
t
CS7 … CS0
SDA Bus
0
1
10 1 0 0 1 0
1 0 1 0 0 1 0
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Data
“Dummy”Write
Figure 14. CONSTAT Register Read Command Sequence
—Write a one byte value to the CONSTAT Register that
has all the bits set to the desired state. The CONSTAT
register can be represented as qxyst01r in binary,
where xy are the Voltage Monitor Output Status (V2OS
and V3OS) bits, t is the DCP Write Lock (DWLK) bit,
CONSTAT Register Read Operation
The contents of the CONSTAT Register can be read at
any time by performing a random read (See Figure 14).
Using the Slave Address Byte set to 10100101, and an
Address Byte of FFh. Only one byte is read by each regis-
ter read operation. The X9523 resets itself after the first
byte is read. The master should supply a STOP condition
to be consistent with the bus protocol.
and qr are the Power On Reset delay time (t
)
PUV1RO
control bits (POR1 - POR0). This operation is pro-
ceeded by a START and ended with a STOP bit. Since
this is a nonvolatile write cycle, it will typically take 5ms
to complete.The RWEL bit is reset by this cycle and the
sequence must be repeated to change the nonvolatile
bits again. If bit 2 is set to ‘1’ in this third step (qxys t11r)
then the RWEL bit is set, but the V2OS, V3OS, POR1,
POR0, and DWLK bits remain unchanged. Writing a
second byte to the control register is not allowed. Doing
so aborts the write operation and the X9523 does not
return an ACKNOWLEDGE.
After setting the WEL and / or the RWEL bit(s) to a “1”, a
CONSTAT register read operation may occur, without
interrupting a proceeding CONSTAT register write opera-
tion.
When performing a read operation on the CONSTAT reg-
isterm, bit CS4 will always return a “0” value.
DATA PROTECTION
For example, a sequence of writes to the device CON-
STAT register consisting of [02H, 06H, 02H] will reset all of
the nonvolatile bits in the CONSTAT Register to “0”.
There are a number of levels of data protection features
designed into the X9523. Any write to the device first
requires setting of the WEL bit in the CONSTAT register. A
write to the CONSTAT register itself, further requires the
setting of the RWEL bit. DCP Write Lock protection of the
device enables the user to inhibit writes to all the DCPs.
One further level of data protection in the X9523, is incor-
porated in the form of the Write Protection pin.
It should be noted that a write to any nonvolatile bit of
CONSTAT register will be ignored if the Write Protect pin
of the X9523 is active (HIGH) (See "WP: Write Protection
Pin").
X9522 Write Permission Status
Write to CONSTAT Register
DWLK
WP
Permitted
(DCP Write Lock (Write Protect pin DCP Volatile Write
DCP Nonvolatile
bit status)
status)
Permitted
Write Permitted
Volatile Bits
YES
Nonvolatile Bits
1
0
1
0
1
1
0
0
NO
NO
NO
NO
NO
YES
YES
NO
NO
YES
YES
YES
YES
YES
YES
Characteristics subject to change without notice. 12 of 31
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X9523 – Preliminary Information
Is is recommended to stop communication to the device
while while V1RO is HIGH. Also, setting the Manual Reset
(MR) pin HIGH overrides the Power On / Low Voltage
circuitry and forces the V1RO output pin HIGH (See
"Manual Reset").
WP:Write Protection Pin
When the Write Protection (WP) pin is active (HIGH), it
disables nonvolatile write operations to the X9523.
The table below (X9523 Write Permission Status) sum-
marizes the effect of the WP pin (and DCP Write Lock), on
the write permission status of the device.
Manual Reset
The V1RO output can be forced HIGH externally using
the Manual Reset (MR) input. MR is a de-bounced, TTL
compatible input, and so it may be operated by connect-
ing a push-button directly from V1 / Vcc to the MR pin.
Additional Data Protection Features
In addition to the preceding features, the X9523 also
incorporates the following data protection functionality:
—The proper clock count and data bit sequence is
required prior to the STOP bit in order to start a nonvol-
atile write cycle.
V1RO remains HIGH for time t
after MR has
PURST
returned to its LOW state (See Figure 15). An external
“pull down” resistor is required to hold this pin (nor-
mally) LOW.
VOLTAGE MONITORING FUNCTIONS
V1 / Vcc Monitoring
V2 monitoring
The X9523 asserts the V2RO output HIGH if the volt-
age V2 exceeds the corresponding V
threshold
The X9523 monitors the supply voltage and drives the
V1RO output HIGH (using an external “pull up” resistor) if
TRIP2
(See Figure 16). The bit V2OS in the CONSTAT regis-
ter is then set to a “0” (assuming that it has been set to
“1” after system initilization).
V1 / Vcc is lower than V
threshold. The V1RO out-
TRIP1
put will remain HIGH until V1 / Vcc exceeds V
for
TRIP1
a minimum time of t
pin is driven to a LOW state. See Figure 25.
. After this time, the V1RO
PURST
The V2RO output may remain active HIGH with V
down to 1V.
CC
For the Power On / Low Voltage Reset function of the
X9523, the V1RO output may be driven HIGH down to a
V3 monitoring
The X9523 asserts the V3RO output HIGH if the volt-
age V3 exceeds the corresponding V threshold
(See Figure 16). The bit V3OS in the CONSTAT regis-
ter is then set to a “0” (assuming that it has been set to
“1” after system initilization).
V1 / Vcc of 1V (V
). See Figure 25. Another feature
RVALID
of the X9523, is that the value of t
may be selected
PURST
TRIP3
in software via the CONSTAT register (See “POR1,
POR0: Power On Reset bits - (Nonvolatile)” on page 11.).
The V3RO output may remain active HIGH with V
down to 1V.
CC
V1 / Vcc
V
TRIP1
0 Volts
V
THRESHOLDS (X=1,2,3)
TRIPX
The X9523 is shipped with pre-programmed threshold
(V ) voltages. In applications where the required
thresholds are different from the default values, or if a
higher precision / tolerance is required, the X9523 trip
points may be adjusted by the user, using the steps
detailed below.
TRIPx
MR
0 Volts
0 Volts
V1RO
Setting a V
Voltage (x=1,2,3)
TRIPx
There are two procedures used to set the threshold
voltages (V ), depending if the threshold voltage to
t
PURST
TRIPx
Figure 15. Manual Reset Response
be stored is higher or lower than the present value. For
example, if the present V is 2.9 V and the new
TRIPx
V
is 3.2 V, the new voltage can be stored directly
TRIPx
Characteristics subject to change without notice. 13 of 31
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X9523 – Preliminary Information
V
V1 / Vcc
V2, V3
TRIPx
V
P
WP
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
SCL
00h
SDA
A0h †
†
Data Byte †
01h sets V
TRIP1
†
S
T
A
R
T
09h sets V
†
TRIP2
†
0Dh sets V
All others Reserved.
TRIP3
Figure 17. Setting V
to a higher level (x=1,2,3).
TRIPx
into the V
cell. If however, the new setting is to be
V
. The STOP bit following a valid write operation
TRIPx
TRIPx
lower than the present setting, then it is necessary to
“reset” the V voltage before setting the new value.
initiates the programming sequence. Pin WP must then
be brought LOW to complete the operation (See Figure
18). The user does not have to set the WEL bit in the
CONSTAT register before performing this write
sequence.
TRIPx
Setting a Higher V
Voltage (x=1,2,3)
TRIPx
threshold to a new voltage which is
To set a V
TRIPx
higher than the present threshold, the user must apply
the desired V threshold voltage to the corre-
sponding input pin (V1 / Vcc, V2 or V3). Then, a pro-
gramming voltage (Vp) must be applied to the WP pin
before a START condition is set up on SDA. Next, issue
on the SDA pin the Slave Address A0h, followed by the
Setting a Lower V
Voltage (x=1,2,3).
TRIPx
TRIPx
In order to set V
to a lower voltage than the
TRIPx
present value, then V
ing to the procedure described below. Once V
has been “reset”, then V
must first be “reset” accord-
TRIPx
TRIPx
can be set to the desired
TRIPx
voltage using the procedure described in “Setting a
Higher V Voltage”.
Byte Address 01h for V
, 09h for V
, and 0Dh
TRIP1
TRIP2
for V
, and a 00h Data Byte in order to program
TRIPx
TRIP3
V
P
WP
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
SCL
00h †
SDA
A0h†
†
03h Resets VTRIP1
Data Byte
S
T
A
R
T
†
0Bh Resets VTRIP2
†
0Fh Resets VTRIP3
†
All others Reserved.
Figure 18. Resetting the V
Level
TRIPx
Characteristics subject to change without notice. 14 of 31
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X9523 – Preliminary Information
the device, and then applying a test voltage higher than
the desired threshold voltage, to the input pin of the volt-
V
TRIPx
age monitor circuit whose V
was programmed. For
TRIPx
Vx
0V
example, if V
was set to a desired level of 3.0 V,
TRIP2
then a test voltage of 3.4 V may be applied to the voltage
monitor input pin V2. In the case of setting of V then
only V1 / Vcc need be applied. In all cases, care should
be taken not to exceed the maximum input voltage limits.
TRIP1
VxRO
0V
V1 / Vcc
After applying the test voltage to the voltage monitor input
pin, the test voltage can be decreased (either in discrete
steps, or continuously) until the output of the voltage mon-
itor circuit changes state. At this point, the error between
the actual / measured, and desired threshold levels is cal-
culated.
V
TRIP1
0 Volts
(x = 2,3)
Figure 16. Voltage Monitor Response
For example, the desired threshold for V
is set to 3.0
TRIP2
V, and a test voltage of 3.4 V was applied to the input pin
V2 (after applying power to V1 / Vcc). The input voltage is
decreased, and found to trip the associated output level of
pin V2RO from a LOW to a HIGH, when V2 reaches 3.09
V. From this, it can be calculated that the programming
error is 3.09 - 3.0 = 0.09 V.
Resetting the V
Voltage (x=1,2,3).
TRIPx
voltage, apply the programming volt-
To reset a V
TRIPx
age (Vp) to the WP pin before a START condition is set
up on SDA. Next, issue on the SDA pin the Slave
Address A0h followed by the Byte Address 03h for
V
, 0Bh for V
, and 0Fh for V
, followed
TRIP1
TRIP2
TRIP3
If the error between the desired and measured V
is
TRIPx
by 00h for the Data Byte in order to reset V
. The
TRIPx
less than the maximum desired error, then the program-
ming process may be terminated. If however, the error is
greater than the maximum desired error, then another
STOP bit following a valid write operation initiates the
programming sequence. Pin WP must then be brought
LOW to complete the operation (See Figure 18).The
user does not have to set the WEL bit in the CONSTAT
register before performing this write sequence.
iteration of the V
programming sequence can be
TRIPx
performed (using the calculated error) in order to further
increase the accuracy of the threshold voltage.
After being reset, the value of V
nal value of 1.7V.
becomes a nomi-
TRIPx
If the calculated error is greater than zero, then the V
TRIPx
must first be “reset”, and then programmed to the a value
equal to the previously set V minus the calculated
TRIPx
V
Accuracy (x=1,2,3).
error. If it is the case that the error is less than zero, then
the V must be programmed to a value equal to the
TRIPx
The accuracy with which the V
thresholds are set,
TRIPx
previously set V
lated error.
TRIPx
plus the absolute value of the calcu-
can be controlled using the iterative process shown in
Figure 19.
TRIPx
Continuing the previous example, we see that the calcu-
lated error was 0.09V. Since this is greater than zero, we
If the desired threshold is less that the present threshold
voltage, then it must first be “reset” (See "Resetting the
VTRIPx Voltage (x=1,2,3).").
must first “reset” the V
threshold, then apply a volt-
TRIP2
age equal to the last previously programmed voltage,
minus the last previously calculated error. Therefore, we
The desired threshold voltage is then applied to the
appropriate input pin (V1 / Vcc, V2 or V3) and the pro-
must apply V
= 2.91 V to pin V2 and execute the
TRIP2
cedure described in Section “Setting a Higher V
Voltage“ must be followed.
TRIPx
programming sequence (See "Setting a Higher VTRIPx
Voltage (x=1,2,3)").
Once the desired V
between the desired and (new) actual set threshold can
be determined. This is achieved by applying V1 / Vcc to
threshold has been set, the error
TRIPx
Using this process, the desired accuracy for a particular
V
threshold may be attained using a successive
TRIPx
number of iterations.
Characteristics subject to change without notice. 15 of 31
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X9523 – Preliminary Information
Note: X = 1,2,3.
V
Programming
TRIPx
Let: MDE = Maximum Desired Error
MDE+
NO
Desired V
<
TRIPx
present value?
Acceptable
Error Range
Desired Value
MDE–
YES
Execute
Error = Actual – Desired
V
Reset
TRIPx
Sequence
Set Vx = desired V
TRIPx
Execute
TRIPx
Sequence
New Vx applied =
Old Vx applied - | Error |
New Vx applied =
Old Vx applied + | Error |
Set Higher V
Execute
Apply Vcc & Voltage
> Desired V to Vx
Reset V
TRIPx
TRIPx
Sequence
Decrease Vx
Output
switches?
NO
YES
Actual V
TRIPx
Error < MDE–
Error >MDE+
- Desired V
TRIPx
= Error
| Error | < | MDE |
DONE
Figure 19. V
Setting / Reset Sequence (x=1,2,3)
TRIPx
Characteristics subject to change without notice. 16 of 31
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X9523 – Preliminary Information
ABSOLUTE MAXIMUM RATINGS
Parameter
Temperature under Bias
Min.
–65
–65
–1.0
–1.0
Max.
+135
+150
+15
Units
°C
°C
V
Storage Temperature
Voltage on WP pin (With respect to Vss)
Voltage on other pins (With respect to Vss)
+7
V
V1 / Vcc
5
V
| Voltage on R – Voltage on R | (x=0,1,2. Referenced to Vss)
D.C. Output Current (SDA,V1RO,V2RO,V3RO)
Hx
Lx
0
mA
°C
V
Lead Temperature (Soldering, 10 seconds)
300
Supply Voltage Limits (Applied V1 / Vcc voltage, referenced to Vss)
2.7
5.5
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
0
Max.
70
Units
°C
Commercial
Industrial
–40
+85
°C
NOTE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of the device at these or any other conditions above those listed
in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability
Figure 20. Equivalent A.C. Circuit
V1 / Vcc = 5V
2300Ω
SDA
V2RO
V3RO
100pF
V1RO
Figure 21. DCP SPICE Macromodel
R
TOTAL
R
R
Hx
Lx
C
L
C
H
10pF
R
W
C
10pF
W
25pF
(x=0,1,2)
R
Wx
Characteristics subject to change without notice. 17 of 31
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X9523 – Preliminary Information
TIMING DIAGRAMS
Figure 22. Bus Timing
t
t
t
t
F
HIGH
LOW
R
SCL
t
SU:DAT
t
t
t
SU:STO
SU:STA
HD:DAT
t
HD:STA
SDA IN
t
t
t
BUF
A
DH
SDA OUT
Figure 23. WP Pin Timing
START
SCL
Clk 1
Clk 9
SDA IN
WP
t
t
HD:WP
SU:WP
Figure 24. Write Cycle Timing
SCL
8th bit of last byte
ACK
SDA
t
WC
Stop
Condition
Start
Condition
Characteristics subject to change without notice. 18 of 31
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X9523 – Preliminary Information
Figure 25. Power-Up and Power-Down Timing
t
t
F
R
V1 / Vcc
0 Volts
V
TRIP1
t
PURST
t
PURST
t
RPD
V1RO
0 Volts
MR
0 Volts
Figure 26. Manual Reset Timing Diagram
MR
t
MRPW
0 Volts
t
t
PURST
MRD
V1RO
0 Volts
V1 / Vcc
V1 / Vcc
V
TRIP1
Figure 27. V2,V3Timing Diagram
t
t
Fx
Rx
Vx
V
TRIPx
t
t
RPDx
RPDx
t
RPDx
0 Volts
t
RPDx
VxRO
0 Volts
V1 / Vcc
V
TRIP1
V
RVALID
0 Volts
Note : x = 2,3.
Characteristics subject to change without notice. 19 of 31
REV 1.1.6 9/14/01
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X9523 – Preliminary Information
Figure 28. V
Programming Timing Diagram (x=1,2,3).
TRIPX
V1 / Vcc, V2, V3
V
TRIPx
t
t
TSU
THD
V
P
WP
t
VPS
t
VPO
SCL
SDA
t
wc
00h
t
VPH
NOTE : V1/Vcc must be greater than V2, V3 when programming.
Figure 29. DCP “Wiper Position”Timing
Rwx (x=0,1,2)
R
wx(n+1)
R
wx(n)
R
wx(n-1)
t
wr
Time
n = tap position
SCL
SDA
1
0
1
0
1
1
1
0
D7 D6 D5 D4 D3 D2 D1 D0
DATA BYTE
S
T
A
R
T
A
C
K
WT
0
0
0
0
0
P1 P0
A
C
K
A
C
K
S
T
O
P
SLAVE ADDRESS BYTE
INSTRUCTION BYTE
Characteristics subject to change without notice. 20 of 31
REV 1.1.6 9/14/01
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X9523 – Preliminary Information
D.C. OPERATING CHARACTERISTICS
Symbol
Parameter
Min Typ
Max
Unit
Test Conditions / Notes
Current into V
Pin
CC
(X9523: Active)
Read memory array (3)
Write nonvolatile memory
f
= 400KHz
ICC1(1)
SCL
0.4
1.5
mA
V
= V
CC
SDA
Current into V
Pin
CC
MR = Vss
WP = Vss or Open/Floating
V
else f
(X9523:Standby)
ICC2(2)
µA
30.0
30.0
With 2-Wire bus activity (3)
No 2-Wire bus activity
=V (when no bus activity
SCL
CC
= 400kHz)
SCL
V
IN (4) = GND to V
CC.
0.1
0.1
10
1
µA
µA
Input Leakage Current (SCL, SDA, MR)
Input Leakage Current (WP)
I
I
LI
VOUT (5) = GND to V
CC.
Output Leakage Current (SDA, V1RO,
V2RO, V3RO)
10
µA
LO
X9523 is in Standby(2)
V
V
V
V
Programming Range
2.75
1.8
4.70
4.70
V
V
TRIP1PR
TRIP1
TRIPx
Programming Range (x=2,3)
TRIPxPR
2.95 3.0
4.65 4.7
3.05
4.75
Factory shipped default option A
Factory shipped default option B
Pre - programmed V
Pre - programmed V
Pre - programmed V
threshold
threshold
threshold
V
V
V
TRIP1 (6)
TRIP2 (6)
TRIP3 (6)
V
V
V
TRIP1
TRIP2
TRIP3
1.75 1.8
2.95 3.0
1.85
3.05
Factory shipped default option A
Factory shipped default option B
1.75 1.8
2.95 3.0
1.85
3.05
Factory shipped default option A
Factory shipped default option B
V
=V =V
V2 Input leakage current
V3 Input leakage current
1
1
SDA SCL CC
I
µA
Vx
Others=GND or V
CC
V (7)
Input LOW Voltage (SCL, SDA, WP, MR)
Input HIGH Voltage (SCL,SDA, WP, MR)
-0.5
2.0
0.8
V
V
IL
V
CC
V
V
IH (7)
+0.5
V1RO, V2RO, V3RO, SDA Output Low
Voltage
I
= 2.0mA
0.4
V
OLx
SINK
Notes: 1. The device enters the Active state after any START, and remains active until: 9 clock cycles later if the Device Select Bits in the
Slave Address Byte are incorrect; 200nS after a STOP ending a read operation; or t after a STOP ending a write operation.
WC
Notes: 2. The device goes into Standby: 200nS after any STOP, except those that initiate a high voltage write cycle; t
after a STOP that
WC
initiates a high voltage cycle; or 9 clock cycles after any START that is not followed by the correct Device Select Bits in the Slave
Address Byte.
Notes: 3. Current through external pull up resistor not included.
Notes: 4.
Notes: 5.
V
= Voltage applied to input pin.
IN
V
= Voltage applied to output pin.
OUT
Notes: 6. See “ORDERING INFORMATION” on page 31.
Notes: 7. Min. and V Max. are for reference only and are not tested
V
IL
IH
Characteristics subject to change without notice. 21 of 31
REV 1.1.6 9/14/01
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X9523 – Preliminary Information
A.C. CHARACTERISTICS (See Figure 22, Figure 23, Figure 24)
400kHz
Symbol
Parameter
Min
Max
Units
f
t
t
t
t
t
t
t
t
t
t
t
0
400
KHz
SCL Clock Frequency
SCL
IN (5)
50
0.1
1.3
1.3
0.6
0.6
0.6
100
0
ns
µs
µs
µs
µs
µs
µs
ns
µs
µs
ns
ns
ns
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus free before start of new transmission
Clock LOW Time
0.9
AA
BUF
LOW
Clock HIGH Time
HIGH
SU:STA
HD:STA
SU:DAT
HD:DAT
SU:STO
DH
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
Data In Hold Time
0.6
50
Stop Condition Setup Time
Data Output Hold Time
t (5)
300
300
SDA and SCL Rise Time
20 +.1Cb (2)
R
t (5)
SDA and SCL Fall Time
WP Setup Time
20 +.1Cb (2)
F
t
0.6
0
µs
µs
pF
SU:WP
t
WP Hold Time
HD:WP
400
Cb
Capacitive load for each bus line
A.C.TEST CONDITIONS
Input Pulse Levels
0.1V
CC
to 0.9V
CC
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
10ns
0.5V
CC
See Figure 20
NONVOLATILE WRITE CYCLE TIMING
Symbol
Parameter
Min.
Typ.(1)
Max.
Units
tWC(4)
Nonvolatile Write Cycle Time
5
10
ms
CAPACITANCE (T = 25˚C, F = 1.0 MHZ, V = 5V)
A
CC
Symbol
Parameter
Max
Units
Test Conditions
= 0V
V
C
OUT (5)
Output Capacitance (SDA, V1RO, V2RO, V3RO)
Input Capacitance (SCL, WP, MR)
8
pF
pF
OUT
V
= 0V
C
IN (5)
6
IN
Notes: 1. Typical values are for T = 25˚C and V
Notes: 2. Cb = total capacitance of one bus line in pF.
= 5.0V
A
CC
Notes: 3. Over recommended operating conditions, unless otherwise specified
Notes: 4.
t
is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write
WC
cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Notes: 5. This parameter is not 100% tested.
Characteristics subject to change without notice. 22 of 31
REV 1.1.6 9/14/01
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X9523 – Preliminary Information
POTENTIOMETER CHARACTERISTICS
Limits
Symbol
Parameter
Min.
–20
Vss
Vss
Typ.
Max.
Units
%
Test Conditions/Notes
R
End to End Resistance Tolerance
+20
TOL
V
R Terminal Voltage (x=0,1,2)
H
V
V
RHx
CC
V
R Terminal Voltage (x=0,1,2)
L
V
V
RLx
CC
R
= 10 KΩ (DCP0,
= 100 KΩ (DCP2)
TOTAL
10
5
mW
mW
Ω
DCP1)
P
R
Power Rating (1)
R
TOTAL
I
= 1mA, V = 5 V, V
=
W
CC
RHx
200
300
400
400
Vcc, V
= Vss (x=0,1,2).
RLx
I
= 1mA, V = 3.3 V, V
=
W
CC
RHx
R
DCP Wiper Resistance
700
Ω
W
Vcc, V
= Vss (x=0,1,2),
RLx
I
= 1mA, V = 2.7 V, V
=
W
CC
RHx
1000
4.4
Ω
Vcc, V
= Vss (x=0,1,2)
RLx
I
Wiper Current
Noise
mA
W
mV /
sqt(Hz)
R
R
= 10 kΩ (DCP0, DCP1)
TOTAL
mV /
sqt(Hz)
= 100 kΩ (DCP2)
TOTAL
R
R
R
R
– R
-1
+1
Absolute Linearity (2)
Relative Linearity (3)
MI(4)
MI(4)
w(n)(actual)
w(n)(expected)
]
w(n)+MI
– [R
-0.2
+0.2
w(n+1)
= 10 kΩ (DCP0, DCP1)
= 100 kΩ (DCP2)
300
300
ppm/°C
ppm/°C
pF
TOTAL
TOTAL
R
Temperature Coefficient
TOTAL
C /C /
Potentiometer Capacitances
Wiper Response time
10/10/
25
H
L
See Figure 21.
See Figure 29.
C
W
t
200
µs
wr
Notes: 1. Power Rating between the wiper terminal R
and the end terminals R or R - for ANY tap position n, (x=0,1,2).
HX LX
WX(n)
Notes: 2. Absolute Linearity is utilized to determine actual wiper resistance versus, expected resistance = (R
(actual) – R
(expected))
wx(n)
wx(n)
=
1 Ml Maximum (x=0,1,2).
Notes: 3. Relative Linearity is a measure of the error in step size between taps = R
– [R
+ Ml] = 0.2 Ml (x=0,1,2)
wx(n)
Wx(n+1)
Notes: 4. 1 Ml = Minimum Increment = R
/ (Number of taps in DCP - 1).
TOT
Notes: 5. Typical values are for T = 25°C and nominal supply voltage.
A
Notes: 6. This parameter is periodically sampled and not 100% tested.
Characteristics subject to change without notice. 23 of 31
REV 1.1.6 9/14/01
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X9523 – Preliminary Information
V
(X=1,2,3) PROGRAMMING PARAMETERS (See Figure 28)
TRIPX
Parameter
Description
Min
10
Typ
Max
Units
µs
t
V
V
V
V
V
Program Enable Voltage Setup time
VPS
TRIPx
TRIPx
TRIPx
TRIPx
TRIPx
t
Program Enable Voltage Hold time
Setup time
10
µs
VPH
t
10
µs
TSU
t
Hold (stable) time
10
µs
THD
Program Enable Voltage Off time
(Between successive adjustments)
t
1
ms
VPO
t
V
TRIPx
Write Cycle time
5
10
15
ms
V
wc
V
P
Programming Voltage
Initial V Program Voltage accuracy
10
TRIPx
V
ta1(1)
ta2(1)
-0.1
+0.2
+25
+25
V
(Vx applied - V
) (Programmed at 25oC.)
TRIPx
Subsequent V
Program Voltage accuracy
. Programmed at 25oC.)
TRIPx
TRIPx
V
-25
-25
+10
+10
mV
mV
[(Vx applied - V ) - V
ta1
V
Program variation after programming (-40 - 85oC).
TRIP
V
tv
(Programmed at 25oC.)
Notes: 1. This parameter is not 100% tested.
Characteristics subject to change without notice. 24 of 31
REV 1.1.6 9/14/01
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X9523 – Preliminary Information
V1RO,V2RO,V3RO OUTPUT TIMING. (See Figure 25, Figure 26, Figure 27)
Symbol
Description
Condition
Min.
25
Typ.
50
Max.
75
Units
ms
POR1= 0, POR0= 0
POR1= 0, POR0= 1
POR1= 1, POR0= 0
POR1= 1, POR0= 1
50
100
200
300
150
300
450
ms
t
t
Power On Reset delay time
PURST
100
150
ms
ms
(M26R)D(2)
MR to V1RO propagation delay
MR pulse width
5
µs
See (1),(2),(4).
t
500
ns
MRDPW
V1 / Vcc, V2, V3 to V1RO,
V2RO, V3RO propagation
delay (respectively)
t
20
µs
RPDx
t
V1 / Vcc, V2, V3 Fall Time
V1 / Vcc, V2, V3 Rise Time
20
20
mV/µs
mV/µs
Fx
t
Rx
V1 / Vcc for V1RO, V2RO,
V3RO Valid (3).
V
1
V
RVALID
Notes: 1. See Figure 26 for timing diagram.
Notes: 2. See Figure 20 for equivalent load.
Notes: 3. This parameter describes the lowest possible V1 / Vcc level for which the outputs V1RO, V2RO, and V3RO will be correct with
respect to their inputs (V1 / Vcc, V2, V3).
Notes: 4. From MR rising edge crossing V , to V1RO rising edge crossing V
.
IH
OH
Characteristics subject to change without notice. 25 of 31
REV 1.1.6 9/14/01
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X9523 – Preliminary Information
APPENDIX 1
DCP1 (100 Tap) Tap position to Data Byte translation Table
Data Byte
Tap
Position
Decimal
Binary
0
1
0
1
0000 0000
0000 0001
.
.
.
.
.
.
23
24
25
26
23
24
56
55
0001 0111
0001 1000
0011 1000
0011 0111
.
.
.
.
.
.
48
49
50
51
33
32
64
65
0010 0001
0010 0000
0100 0000
0100 0001
.
.
.
.
.
.
73
74
75
76
87
88
0101 0111
0101 1000
0111 1000
0111 0111
120
119
.
.
.
.
.
.
98
99
97
96
0110 0001
0110 0000
Characteristics subject to change without notice. 26 of 31
REV 1.1.6 9/14/01
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X9523 – Preliminary Information
APPENDIX 2
DCP1 (100 Tap) tap position to Data Byte translation algorithm example. (Example 1)
unsigned DCP1_TAP_Position(int tap_pos)
{
int block;
int i;
int offset;
int wcr_val;
offset= 0;
block = tap_pos / 25;
if (block < 0) return ((unsigned)0);
else if (block <= 3)
{
switch(block)
{ case (0): return ((unsigned)tap_pos) ;
case (1):
{
wcr_val = 56;
offset = tap_pos - 25;
for (i=0; i<= offset; i++) wcr_val-- ;
return ((unsigned)++wcr_val);
}
case (2):
{
wcr_val = 64;
offset = tap_pos - 50;
for (i=0; i<= offset; i++) wcr_val++ ;
return ((unsigned)--wcr_val);
}
case (3):
{
wcr_val = 120;
offset = tap_pos - 75;
for (i=0; i<= offset; i++) wcr_val-- ;
return ((unsigned)++wcr_val);
}
}
}
return((unsigned)01100000);
}
Characteristics subject to change without notice. 27 of 31
REV 1.1.6 9/14/01
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X9523 – Preliminary Information
APPENDIX 2
DCP1 (100 Tap) tap position to Data Byte translation algorithm example. (Example 2)
unsigned DCP100_TAP_Position(int tap_pos)
{
/* optional range checking
*/ if (tap_pos < 0) return ((unsigned)0);
else if (tap_pos >99) return ((unsigned) 96);
/* set to min val */
/* set to max val */
/* 100 Tap DCP encoding formula */
if (tap_pos > 74)
return ((unsigned) (195 - tap_pos));
else if (tap_pos > 49)
return ((unsigned) (14 + tap_pos));
else if (tap_pos > 24)
return ((unsigned) (81 - tap_pos));
else return (tap_pos);
}
Characteristics subject to change without notice. 28 of 31
REV 1.1.6 9/14/01
www.xicor.com
X9523 – Preliminary Information
20 Ball BGA (X9523)
a
a
l
j
m
1
2
3
4
4
3
2
1
A
B
C
D
E
A
B
C
D
E
b
b
k
f
Top View (Bump Side Down)
Bottom View (Bump Side Up)
Note: Drawing not to scale
= Die Orientation mark
d
c
Ball Matrix
e
4
3
2
V1/VCC
V1RO
NC
1
Side View (Bump Side Down)
A
B
C
D
E
RL2
V3
RW2
RH2
V3RO
MR
V2RO
V2
WP
SCL
SDA
NC
NC
RH1
VSS
RL1
RW1
Millimeters
Nom
Inches
Symbol
Min
Max
Min
Nom
Max
Package Body Dimension X
Package Body Dimension Y
Package Height
a
b
c
d
e
f
2.524
3.794
0.654
0.444
0.210
0.316
2.554
3.824
0.682
0.457
0.225
0.326
0.5
2.584
3.854
0.710
0.470
0.240
0.336
0.09938
0.14938
0.02575
0.01748
0.00827
0.01244
0.10056
0.15056
0.02685
0.01799
0.00886
0.01283
0.01969
0.01969
0.10174
0.15174
0.02795
0.01850
0.00945
0.01323
Body Thickness
Ball Height
Ball Diameter
Ball Pitch – X Axis
Ball Pitch – Y Axis
j
k
0.5
Ball to Edge Spacing –
Distance Along X
l
0.497
0.882
0.527
0.912
0.557
0.942
0.01957
0.03473
0.02075
0.03591
0.02193
0.03709
Ball to Edge Spacing –
Distance Along Y
m
Characteristics subject to change without notice. 29 of 31
REV 1.1.6 9/14/01
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X9523 – Preliminary Information
20-LEAD PLASTIC, TSSOP PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.252 (6.4)
.260 (6.6)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
(7.72)
(4.16)
.010 (.25)
Gage Plane
0° – 8°
Seating Plane
(1.78)
(0.42)
.019 (.50)
.029 (.75)
DetailA (20X)
(0.65)
ALL MEASUREMENTS ARE TYPICAL
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 30 of 31
REV 1.1.6 9/14/01
www.xicor.com
X9523 – Preliminary Information
ORDERING INFORMATION
y
-
X9523
P
T
Preset (Factory Shipped)V
Threshold Levels (x=1,2,3)
TRIPx
Device
A = Optimized for 3.3 V system monitoring †
B = Optimized for 5 V system monitoring †
Temperature Range
I = Industrial -40°C to +85°C
Package
V20 = 20-Lead TSSOP
B20 = 20-Lead XBGA
XBGA PART MARK CONVENTION
20 Lead XBGA
X9523B20I-A
X9523B20I-B
Top Mark
XACO
XACS
†
For details of preset threshold values, See "D.C. OPERATING CHARACTERISTICS"
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and
prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc.
All others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461;
4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880;
5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents
pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error
detection and correction, redundancy and back-up features to prevent such an occurence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure
to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 31 of 31
REV 1.1.6 9/14/01
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