X98027 [XICOR]
PRELIMINARY INFORMATION; 初步信息
| 型号： | X98027 |
| 厂家： | 
XICOR INC. |
| 描述： | PRELIMINARY INFORMATION |
| 文件： | 总1页 (文件大小：105K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Key Features
X98027
– Resolutions Up To QXGA 60Hz
– 250ps Long Term Jitter
– 64 Phase Choices
275MHz Triple Video Digitizer
with Digital PLL
– Zero Offset Error/Offset Drift
PRELIMINARY INFORMATION
FEATURES
DESCRIPTION
• 275MSPS maximum conversion rate
• 64 interpixel sampling positions
• Low long-term PLL clock jitter (250ps p-p @ 275MSPS)
• Programmable input bandwidth (100MHz to 780MHz)
• 2 channel input multiplexer
The X98027 3-channel, 8-bit Analog Front End (AFE) contains
all the components necessary to digitize analog RGB or YUV
graphics signals from personal computers, workstations and
video set-top boxes. The fully differential analog design provides
high PSRR and dynamic performance to meet the strigent
requirements of the graphics display industry. The 275MSPS
conversion rate supports resolutions up to QXGA at 60Hz
refresh rate, while the front end's high input bandwidth ensures
sharp images at the highest resolution.
• RGB and YUV 4:2:2 output formats
• 4 embedded voltage regulators allow operation from
single 3.3V supply and enhance performance, isolation
• Completely independent 8 bit gain/10 bit offset control
• CSYNC and SOG support
To minimize noise, the X98027's analog section features 2 sets
of pseudo-differential RGB inputs with programmable input
bandwidth, as well as internal DC restore clamping (including
mid-scale clamping for YUV signals). This is followed by the
programmable gain/offset stage and the three 275MSPS
Analog-to-Digital Converters (ADCs). All necessary reference
voltages are internally generated.
• Trilevel Sync detection
• 1180mW typical PD @ 275MSPS
APPLICATIONS
• LCD Monitors and Projectors
• Digital TVs
• Plasma Display Panels
• RGB Graphics Processing
• Scan Converters
The X98027's digital PLL generates a pixel clock from the analog
source's HSYNC or SOG (Sync-On-Green) signals. Pixel clock
output frequencies range from 10MHz to 275MHz with long-term
clock jitter less than 250ps peak to peak.
BLOCK DIAGRAM
VCLAMP
Auto Black
Level
Compensation
Offset
DAC
10
RIN
1
2
VIN
+
-
8
8
RP[7:0]
RS[7:0]
8
8
8
8 bit ADC
PGA
PGA
PGA
+
+
+
VIN
RIN
VCLAMP
Auto Black
Level
Compensation
Offset
DAC
10
GIN
1
VIN
+
-
8
8
RGBGND
1
GP[7:0]
GS[7:0]
8 bit ADC
VIN
GIN2
RGBGND2
VCLAMP
Auto Black
Level
Compensation
Offset
DAC
10
BIN
1
2
VIN
+
-
8
8
BP[7:0]
BS[7:0]
8 bit ADC
VIN
BIN
DATACLK
DATACLK
SOGIN
1
SOGIN
2
HSYNCIN
1
Sync
Processing
AFE Configuration
and Control
HSOUT
VSOUT
HSYNCIN
2
1
VSYNCIN
VSYNCIN
2
HSYNCOUT
VSYNCOUT
CLOCKINV
Digital PLL
XTALIN
XTALCLKOUT
XTALOUT
SCL
SDA
Serial
Interface
SADDR
Characteristics subject to change without notice
REV 0.7 9/21/03
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