5962-9951401QXB_技术文档

0

QPRO Series Configuration

PROMs (XQ) including

R

Radiation-Hardened Series (XQR)

0

2

DS062 (v3.0) February 8, 2000

Preliminary Product Specification

Features

Description

•

XQ1701L/XQR1701L

The QPRO™ series XQ1701L are Xilinx 3.3V high-density

configuration PROMs. The XQR1701L are radiation hard-

ened. These devices are manufactured on Xilinx QML certi-

fied manufacturing lines utilizing epitaxial substrates and

TID lot qualification (per method 1019).

QML Certified

Configuration one-time programmable (OTP) read-only

memory designed to store configuration bitstreams of

Xilinx FPGA devices

When the FPGA is in Master Serial mode, it generates a

configuration clock that drives the PROM. A short access

time after the rising clock edge, data appears on the PROM

•

Simple interface to the FPGA; requires only one user

I/O pin

•

Cascadable for storing longer or multiple bitstreams

DATA output pin that is connected to the FPGA D pin. The

IN

Programmable reset polarity (active High or active

Low) for compatibility with different FPGA solutions

FPGA generates the appropriate number of clock pulses to

complete the configuration. Once configured, it disables the

PROM. When the FPGA is in Slave Serial mode, the PROM

and the FPGA must both be clocked by an incoming signal.

Figure 1 shows a simplied block diagram.

•

Supports XQ4000XL/Virtex fast configuration mode

(15.0 MHz)

•

Available in 44-pin ceramic LCC (M grade) package

Available in 20-pin SOIC package (XQ1701L only)

Multiple devices can be concatenated by using the CEO

output to drive the CE input of the following device. The

clock inputs and the DATA outputs of all PROMs in this

chain are interconnected. All devices are compatible and

can be cascaded with other members of the family.

Programming support by leading programmer

manufacturers.

•

Design support using the Xilinx Alliance and

Foundation series software packages.

For device programming, either the Xilinx Alliance or Foun-

dation series development system compiles the FPGA

design file into a standard Hex format, which is then trans-

ferred to most commercial PROM programmers.

•

XQR1701L (only)

•

Fabricated on Epitaxial Silicon to improve latch

performance (parts are immune to Single Event

Latch-up)

•

Single Event Bit Upset immune

Total Dose tolerance in excess of 50K rads(Si)

All lots subjected to TID Lot Qualification in accordance

with method 1019 (dose rate ~9.0 rads(Si)/sec)

•

XQ1701L (only)

•

Also available under the following Standard Microcircuit

Drawing (SMD): 5962-9951401. For more information

contact hte Defense Supply Center Columbus (DSCC):

http://www.dscc.dla.mil/Programs/Smcr/

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

.

DS062 (v3.0) February 8, 2000

www.xilinx.com

1

Preliminary Product Specification

1-800-255-7778

R

QPRO Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR)

V

CC

V

PP

GND

RESET/

CEO

CE

OE

or

OE/

RESET

Address Counter

CLK

TC

EPROM

Cell

OE

Output

DATA

Matrix

DS027_01_021500

Figure 1: Simplified Block Diagram (does not show programming circuit)

Pin Description

DATA

CE

Data output is in a high-impedance state when either CE or

OE are inactive. During programming, the DATA pin is I/O.

Note that OE can be programmed to be either active High or

active Low.

When High, this pin disables the internal address counter,

puts the DATA output in a high-impedance state, and forces

the device into low-I standby mode.

CC

CEO

CLK

Chip Enable output, to be connected to the CE input of the

next PROM in the daisy chain. This output is Low when the

CE and OE inputs are both active AND the internal address

counter has been incremented beyond its Terminal Count

(TC) value. In other words: when the PROM has been read,

CEO will follow CE as long as OE is active. When OE goes

inactive, CEO stays High until the PROM is reset. Note that

OE can be programmed to be either active High or active

Low.

Each rising edge on the CLK input increments the internal

address counter, if both CE and OE are active.

RESET/OE

When High, this input holds the address counter reset and

puts the DATA output in a high-impedance state. The polar-

ity of this input pin is programmable as either RESET/OE or

OE/RESET. To avoid confusion, this document describes

the pin as RESET/OE, although the opposite polarity is pos-

sible on all devices. When RESET is active, the address

counter is held at "0", and puts the DATA output in a

high-impedance state. The polarity of this input is program-

mable. The default is active High RESET, but the preferred

option is active Low RESET, because it can be driven by the

FPGAs INIT pin.

V_PP

Programming voltage. No overshoot above the specified

max voltage is permitted on this pin. For normal read oper-

ation, this pin must be connected to V . Failure to do so

CC

may lead to unpredictable, temperature-dependent opera-

tion and severe problems in circuit debugging. Do not leave

V

floating!

PP

The polarity of this pin is controlled in the programmer inter-

face. This input pin is easily inverted using the Xilinx

HW-130 Programmer. Third-party programmers have differ-

ent methods to invert this pin.

V_CCand GND

Positive supply and ground pins.

2

www.xilinx.com

1-800-255-7778

DS062 (v3.0) February 8, 2000

Preliminary Product Specification

R

QPRO Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR)

next PROM in a daisy chain (if any).

PROM Pinouts

•

The RESET/OE input of all PROMs is best driven by

the INIT output of the lead FPGA device. This

connection assures that the PROM address counter is

reset before the start of any (re)configuration, even

Pin Name

44-Pin CLCC

DATA

2

5

when a reconfiguration is initiated by a V

glitch.

CLK

CC

Other methods—such as driving RESET/OE from LDC

or system reset—assume the PROM internal

power-on-reset is always in step with the FPGAs

internal power-on-reset. This may not be a safe

assumption.

RESET/OE (OE/RESET)

19

21

3, 24

27

41

44

CE

GND

CEO

•

The PROM CE input can be driven from either the LDC

or DONE pins. Using LDC avoids potential contention

V

PP

CC

on the D pin.

IN

The CE input of the lead (or only) PROM is driven by

the DONE output of the lead FPGA device, provided

that DONE is not permanently grounded. Otherwise,

LDC can be used to drive CE, but must then be

unconditionally High during user operation. CE can

also be permanently tied Low, but this keeps the DATA

output active and causes an unnecessary supply

current of 10 mA maximum.

Capacity

Devices

Configuration Bits

XQR1701L

XQ1701L

1,048,576

FPGA Master Serial Mode Summary

Xilinx FPGAs and Compatible PROMs.

The I/O and logic functions of the Configurable Logic Block

(CLB) and their associated interconnections are established

by a configuration program. The program is loaded either

automatically upon power up, or on command, depending

on the state of the three FPGA mode pins. In Master Serial

mode, the FPGA automatically loads the configuration pro-

gram from an external memory. The Xilinx PROMs have

been designed for compatibility with the Master Serial

mode.

XQ(R)1701L

Device

Configuration Bits

393,632

PROMs

XQ(R)4013XL

XQ(R)4036XL

XQ(R)4062XL

XQ(R)4013XL

XQ(R)4036XL

XQ(R)4062XL

XQV(R)300

1

2

1

2

4

6

832,528

1,433,864

393,632

Upon power-up or reconfiguration, an FPGA enters the

Master Serial mode whenever all three of the FPGA

mode-select pins are Low (M0=0, M1=0, M2=0). Data is

read from the PROM sequentially on a single data line. Syn-

chronization is provided by the rising edge of the temporary

signal CCLK, which is generated during configuration.

832,528

1,433,864

1,751,840

3,608,000

6,127,776

XQV(R)600

Master Serial Mode provides a simple configuration inter-

face. Only a serial data line and two control lines are

required to configure an FPGA. Data from the PROM is

read sequentially, accessed via the internal address and bit

counters which are incremented on every valid rising edge

of CCLK.

XQV(R)1000

Controlling PROMs

Connecting the FPGA device with the PROM.

•

The DATA output(s) of the of the PROM(s) drives the

input of the lead FPGA device.

If the user-programmable, dual-function D pin on the

D

IN

FPGA is used only for configuration, it must still be held at a

defined level during normal operation. The Xilinx FPGA

families take care of this automatically with an on-chip

default pull-up resistor.

•

The Master FPGA CCLK output drives the CLK input(s)

of the PROM(s).

The CEO output of a PROM drives the CE input of the

DS062 (v3.0) February 8, 2000

Preliminary Product Specification

www.xilinx.com

1-800-255-7778

3

R

QPRO Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR)

contentions inside the FPGA and on its output pins. This

method must, therefore, never be used when there is any

chance of external reset during configuration.

Programming the FPGA With Counters

Unchanged Upon Completion

When multiple FPGA-configurations for a single FPGA are

stored in a PROM, the OE pin should be tied Low. Upon

power-up, the internal address counters are reset and con-

figuration begins with the first program stored in memory.

Since the OE pin is held Low, the address counters are left

unchanged after configuration is complete. Therefore, to

reprogram the FPGA with another program, the DONE line

is pulled Low and configuration begins at the last value of

the address counters.

Cascading Configuration PROMs

For multiple FPGAs configured as a daisy-chain, or for

future FPGAs requiring larger configuration memories, cas-

caded PROMs provide additional memory. After the last bit

from the first PROM is read, the next clock signal to the

PROM asserts its CEO output Low and disables its DATA

line. The second PROM recognizes the Low level on its CE

input and enables its DATA output. See Figure 2.

This method fails if a user applies RESET during the FPGA

configuration process. The FPGA aborts the configuration

and then restarts a new configuration, as intended, but the

PROM does not reset its address counter, since it never

saw a High level on its OE input. The new configuration,

therefore, reads the remaining data in the PROM and inter-

prets it as preamble, length count etc. Since the FPGA is

the master, it issues the necessary number of CCLK pulses,

After configuration is complete, the address counters of all

cascaded PROMs are reset if the FPGA RESET pin goes

Low, assuming the PROM reset polarity option has been

inverted.

To reprogram the FPGA with another program, the DONE

line goes Low and configuration begins where the address

counters had stopped. In this case, avoid contention

24

up to 16 million (2 ) and DONE goes High. However, the

between DATA and the configured I/O use of D .

IN

FPGA configuration will be completely wrong, with potential

4

www.xilinx.com

1-800-255-7778

DS062 (v3.0) February 8, 2000

Preliminary Product Specification

R

QPRO Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR)

Vcc

DOUT

OPTIONAL

Daisy-chained

FPGAs with

Different

configurations

OPTIONAL

FPGA

Slave FPGAs

with Identical

Configurations

MODES*

V

CC

3.3V

4.7K

V

PP

V

CC

PP

DATA

CLK

DATA

CLK

DIN

CCLK

DONE

INIT

Cascaded

Serial

Memory

RESET

PROM

CE

CEO

CE

OE/RESET

* For mode pin connections,

refer to the appropriate FPGA data sheet.

(Low Resets the Address Pointer)

CCLK

(Output)

D

IN

D

OUT

(Output)

DS027_02_060100

Figure 2: Master Serial Mode. The one-time-programmable PROM supports automatic loading of configuration programs.

Multiple devices can be cascaded to support additional FPGAs. An early DONE inhibits the PROM data output one CCLK

cycle before the FPGA I/Os become active.

DS062 (v3.0) February 8, 2000

www.xilinx.com

5

Preliminary Product Specification

1-800-255-7778

R

QPRO Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR)

Standby Mode

Programming

The PROM enters a low-power standby mode whenever CE

is asserted High. The output remains in a high-impedance

state regardless of the state of the OE input.

The devices can be programmed on programmers supplied

by Xilinx or qualified third-party vendors. The user must

ensure that the appropriate programming algorithm and the

latest version of the programmer software are used. The

wrong choice can permanently damage the device.

Table 1: Truth Table for Control Inputs

Control Inputs

Outputs

RESET

CE

Internal Address

DATA

CEO

I

CC

(1)

Inactive

Low

If address < TC : increment

Active

High-Z

High

Low

Active

Reduced

(1)

If address > TC : don’t change

Active

Inactive

Active

Low

High

Held reset

Not changing

Held reset

High-Z

High

Active

Standby

Notes:

1. The XC1700 RESET input has programmable polarity

1. TC = Terminal Count = highest address value. TC + 1 = address 0.

Radiation Characteristics (XQR1701L only)

Symbol

TID

Description

Min

Max

Units

Total ionizing dose, Method 1019

50K

rads(Si)

2

SEL

Single event latch-up.

0

(cm /Device)

2

Heavy ion saturation cross section, LET > 120 MeV cm /mg

1

2

SEU

Single event bit upset.

(cm /Bit)

Heavy ion saturation cross section

2

LET > 120 MeV cm /mg

-5

2

SEFI

Single event functional interupt,

1.2e

(cm /Device)

2

Heavy ion saturation cross section,

10% saturated intercept at LET = 6.0 MeV cm /mg

2

Notes:

2

1. Single Event Effects testing was performed with heavy ion to a maximum LET of 120 MeV-cm /mg.

6

www.xilinx.com

DS062 (v3.0) February 8, 2000

1-800-255-7778

Preliminary Product Specification

R

QPRO Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR)

Absolute Maximum Ratings

Symbol

Description

Supply voltage relative to GND

Conditions

–0.5 to +4.0

–0.5 to +12.5

Units

V

CC

PP

Supply voltage relative to GND

V

Input voltage relative to GND

–0.5 to V +0.5

V

IN

CC

V

Voltage applied to High-Z output

Storage temperature (ambient)

–0.5 to V +0.5

V

TS

CC

T

–65 to +150

°C

STG

SOL

Maximum soldering temperature (10s @ 1/16 in.)

+260

Notes:

1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions

is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

Operating Conditions

Symbol

Description

Supply voltage relative to GND

Min

Max

Units

(1)

V

Military

3.0

3.6

V

CC

ceramic package (T = –55°C to +125°C)

C

plastic package (T = –55°C to +125°C)

J

Notes:

1. During normal read operation V_PPMUST be connected to V

CC.

DC Characteristics Over Operating Condition

Symbol

Description

Min

Max

Units

V

High-level input voltage

Low-level input voltage

High-level output voltage (I

2

V

CC

IH

V

0

0.8

-

V

IL

V

= –3 mA)

OH

2.4

V

OH

V

Low-level output voltage (I = +3 mA)

-

0.4

10

100

300

3

V

OL

I

Supply current, active mode (at maximum frequency)

Supply current, standby mode (XQ1701L)

-

mA

µA

mA

µA

pF

CCA

CCS

I

-

(1)

CCS

I

Supply current, standby mode

(XQR1701L )

Pre-rad (TID)

Post-rad (TID)

-

I

Input or output leakage current

–10

10

L

C

Input capacitance (V = GND, f = 1.0 MHz)

-

IN

C

Output capacitance (V = GND, f = 1.0 MHz)

IN

OUT

Notes:

1.

I

, Standby Current is measured at +125°C for pre-radiation specifications and at room temperature for post-radiation

CCS

specifications.

DS062 (v3.0) February 8, 2000

www.xilinx.com

7

Preliminary Product Specification

1-800-255-7778

R

QPRO Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR)

AC Characteristics Over Operating Condition

CE

T

HCE

SCE

RESET/OE

CLK

T

HOE

T

HC

LC

T

CYC

T

DF

OE

T

CAC

OH

T

CE

DATA

T

OH

DS027_03_021500

XQ(R)1701L

Symbol

Description

Min

-

Max

Units

ns

T

OE to data delay

CE to data delay

30

45

50

-

OE

CE

-

ns

T

CLK to data delay

-

ns

CAC

(2,3)

T

CE or OE to data float delay

Data hold from CE, OE, or CLK

Clock periods

-

ns

DF

(3)

T

0

ns

OH

T

67

25

0

-

ns

CYC

(3)

T

CLK Low time

-

ns

LC

(3)

T

CLK High time

-

ns

HC

T

CE setup time to CLK (to guarantee proper counting)

CE hold time to CLK (to guarantee proper counting)

OE hold time (guarantees counters are reset)

-

ns

SCE

HCE

HOE

-

ns

T

25

-

ns

Notes:

1. AC test load = 50 pF

2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.

3. Guaranteed by design, not tested.

4. All AC parameters are measured with V = 0.0V and V = 3.0V.

IL

IH

8

www.xilinx.com

DS062 (v3.0) February 8, 2000

1-800-255-7778

Preliminary Product Specification

R

QPRO Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR)

AC Characteristics Over Operating Condition When Cascading

RESET/OE

CE

CLK

T

CDF

Last Bit

First Bit

DATA

CEO

T

OOE

OCK

T

OCE

T

OCE

DS027_04_021500

Symbol

Description

Min

Max

50

Units

ns

(2,3)

T

CLK to data float delay

-

CDF

OCK

OCE

OOE

(3)

T

CLK to CEO delay

30

ns

(3)

CE to CEO delay

35

ns

(3)

T

RESET/OE to CEO delay

30

ns

Notes:

1. AC test load = 50 pF

2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.

3. Guaranteed by design, not tested.

4. All AC parameters are measured with V = 0.0V and V = 3.0V.

IL

IH

DS062 (v3.0) February 8, 2000

www.xilinx.com

9

Preliminary Product Specification

1-800-255-7778

R

QPRO Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR)

Ordering Information

XQR1701L CC44 M

Device Number

Operating Range/Processing

XQ1701L

XQR1701L

M = Military (T = –55° to +125°C)

C

Package Type

QML certified to MIL-PRF-38535

CC44 = 44-pin Ceramic Chip Carrier

SO20 = 20-pin Plastic Small Outline Package

N = Military Plastic (T = –55° to +125°C)

J

5962 9951401 Q Y A

Generic Standard

Lead Finish

Microcircuit Drawing

(SMD)

A = Solder Dip

B = Solder Plate

Device Type

Package Type

XQ1701L

Y

X

= 44-pin Ceramic Chip Carrier

= 20-pin Plastic Small Outline Package

QML Certified

Valid Ordering Combinations

XQ1701LCC44M

XQ1701LSO20N

XQR1701LCC44M

Revision History

The following table shows the revision history for this document.

Date

Version

1.0

Revision

04/20/00

06/01/00

Initial Release

2.0

Combined XQR1700L Rad-Hard and XQ1701L devices, added XQ1704L and updated

format.

02/08/01

3.0

Removed the XQ1704L and XQR1704L

10

www.xilinx.com

DS062 (v3.0) February 8, 2000

1-800-255-7778

Preliminary Product Specification


型号：	5962-9951401QXB
厂家：	XILINX, INC
描述：	Configuration Memory, 1MX1, PDSO20, PLASTIC, SOIC-20 光电二极管内存集成电路
文件：	总10页 (文件大小：92K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

5962-9951401QXB [XILINX]

相关型号：

5962-9951401QXX

5962-9951401QYA

5962-9951401QYX

5962-9951501VGA

5962-9951501VPA

5962-9951701VZA

5962-9951703VZA

5962-9951703VZX

5962-9951801HUA

5962-9951801HUC

5962-9951801HXA

5962-9951801HXC