W1D256M72R8B-3.75AE-FB1 [XILINX]
256MX8 DDR DRAM MODULE, 0.5ns, DMA240, MO-237, DIMM-240;
| 型号： | W1D256M72R8B-3.75AE-FB1 |
| 厂家： | 
XILINX, INC |
| 描述： | 256MX8 DDR DRAM MODULE, 0.5ns, DMA240, MO-237, DIMM-240 动态存储器 双倍数据速率 |
| 文件： | 总11页 (文件大小：255K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DDR2-400, 533
Single Rank, x8 Registered SDRAM DIMMs
256MB - W1D32M72R8
512MB - W1D64M72R8
1GB
2GB
- W1D128M72R8
- W1D256M72R8 (Preliminary*)
Features:
Figure 1: Available layouts
Layout A:
•
240-pin Registered ECC DDR2 SDRAM Dual-In-
Line Memory Module for DDR2-400 and DDR2-533
JEDEC standard VDD=1.8V (+/- 0.1V) power
supply
One rank 256MB, 512MB, 1GB, and 2GB
Modules are built with 18 x8 DDR2 SDRAM
devices in a 60-ball FBGA package
ECC error detection and correction
Programmable CAS Latency of 3 and 4; Burst
Length of 4 and 8
Auto Refresh and Self Refresh Mode
OCD (Off-Chip Driver Impedance Adjustment) and
ODT (On-Die Termination)
SPD (Serial Presence Detect) with EEPROM
All input/output are SSTL_18 compatible
All contacts are gold plated
•
1.181"
•
•
Layout B:
•
•
1.0"
•
•
Front view of double-sided DIMM (see detail physical dimensions
at the back)
•
•
•
•
Speed Grades:
Speed Grade
-5
-3.75
Units
One clock delay for register
Module Speed Grade
PC2-3200 PC2-4200
Speed @ CL3
Speed @ CL4
Speed @ CL5
400
400
-
-
MHz
MHz
MHz
533
533
Note: See Product ordering for full naming guide
Description:
The following specification covers the W1D32M72R8, W1D64M72R8, W1D128M72R8, and W1D256M72R8
family of Single-Rank Registered ECC DDR2 modules using x8 FBGA SDRAMs. Please reference Figure 1 for
available layout configurations and the product ordering guide on the final page of this specification for available
options including speed grade and silicon manufacturer.
Address Summary Table:
256MB
32M x 72
8k
512MB
64M x 72
8K
1GB
128M x 72
8K
2GB
256M x 72
8K
Module Configuration
Refresh
Device Configuration
32M x 8
(9 components)
A0-A13
A0-A9
64M x 8
(9 components)
A0-A13
A0-A9
128M x 8
(9 components)
A0-A14
A0-A9
256M x 8
(9 components)
A0-A14
A0-A9
Row Addressing
Column Addressing
Module Rank
1
1
1
1
*Specifications are for reference purposes only and are subject to change by Wintec without notice.
DDR2_RDIMM_1 rank_x8_spec
Rev. 1.0 - December, 04
Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice.
2004 Wintec Industries, Inc.
1
DDR2-400, 533
Single Rank, x8 Registered SDRAM DIMMs
Pin Configuration:
Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
Pin Symbol
1
2
VREF
VSS
DQ0
DQ1
VSS
31 DQ19
32 VSS
61
62 VDDQ
63 A2
64 VDD
KEY
A4
91
VSS
121
VSS
DQ4
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
VSS
DQ28
DQ29
VSS
DM3/DQS12
NC/DQS12#
VSS
DQ30
DQ31
VSS
181
182
183
184
VDDQ
A3
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
DM5/DQS14
NC/DQS14#
VSS
92 DQS5# 122
3
33 DQ24
34 DQ25
93
94
95
96
97
98
99
100
DQS5 123
DQ5
A1
4
VSS
DQ42
DQ43
VSS
124
125
126
127
128
129
130
131
132
133
VSS
VDD
DQ46
5
35
VSS
KEY
DQ47
DM0/DQS9
NC/DQS9#
VSS
6
DQS0# 36 DQS3# 65 VSS
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
CK0
CK0#
VDD
VSS
7
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
37 DQS3
38 VSS
39 DQ26
40 DQ27
66 VSS
67 VDD
DQ52
8
DQ48
DQ49
VSS
DQ6
DQ53
9
68
NC
DQ7
A0
VSS
10
11
12
13
14
69 VDD
VSS
VDD
RFU
41
42
43
44
VSS
CB0
CB1
VSS
70 A10/AP 101
SA2
DQ12
DQ13
VSS
CB4
CB5
VSS
BA1
RFU
NC,TEST1
VSS
71
72 VDDQ 103
73 WE#
BA0
102
VDDQ
RAS#
S0#
VDDQ
ODT0
A13
VSS
DM6/DQS15
NC/DQS15#
VSS
104 DQS6# 134
DM1/DQS10
NC/DQS10#
VSS
DM8/DQS17
NC/DQS17#
VSS
15 DQS1# 45 DQS8# 74 CAS# 105 DQS6 135
16 DQS1
17 VSS
18 RESET# 48
NC
VSS
21 DQ10
22 DQ11
VSS
24 DQ16
25 DQ17
VSS
27 DQS2# 57
28 DQS2
29 VSS
30 DQ18
46 DQS8
75 VDDQ 106
76 S1# 107
77 ODT1 108
78 VDDQ 109
79 VSS
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
136
137
138
139
140
141
142
DQ54
47
VSS
CB2
CB3
VSS
RFU
CB6
DQ55
RFU
CB7
VDD
VSS
VSS
19
20
49
50
VSS
VSS
DQ60
110
DQ14
DQ15
VSS
VDDQ
CKE1
VDD
DQ36
DQ37
VSS
DM4/DQS13
NC/DQS13#
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQ61
51 VDDQ
52 CKE0
80 DQ32 111
81 DQ33 112
VSS
DM7/DQS16
NC/DQS16#
VSS
23
53
54 A16,BA2 83 DQS4# 114 DQS7 144
VDD
82 VSS
113 DQS7# 143
DQ20
DQ21
VSS
DM2/DQS11
NC/DQS11#
VSS
A15
A14
VDDQ
A12
A9
VDD
A8
A6
55
NC
84 DQS4 115
85 VSS 116
86 DQ34 117
87 DQ35 118
88 VSS
89 DQ40 120
90 DQ41
VSS
DQ58
DQ59
VSS
SDA
SCL
145
146
147
148
149
150
DQ62
26
56 VDDQ
DQ63
A11
A7
VDD
A5
VSS
58
59
60
238 VDDSPD
119
DQ22
DQ23
239
240
SA0
SA1
NC - No Connect, RFU - Reserved for Future Use
1.
2.
3.
The Test pin (Pin 102) is reserved for bus analysis and is not connected on normal memory modules
CKE1 and S1# pin are used for dual-rank Registered DIMM
A13 (Pin 196) is for 512MB and above DIMM.
Pin Locations:
Front View
64
185
65
184
Pin 1
120
Pin 240
121
Back View
240-pin DIMM
DDR2_RDIMM_1 rank_x8_spec
Rev. 1.0 - December, 04
Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice.
2004 Wintec Industries, Inc.
2
DDR2-400, 533
Single Rank, x8 Registered SDRAM DIMMs
Functional Block Diagram:
Single Rank 32M x 72 (256MB), 64M x 72 (512MB), 128M x 72 (1GB), and 256M x 72 (2GB) DDR2 Registered
SDRAM DIMM (x8 organization)
RCS0#
DQS4
DQS4#
DQS0
DQS0#
DM4/DQS13
DM0/DQS9
NU/
DM/ CS# DQS# DQS
NU/
DM/ CS# DQS# DQS
DQS9#
RDQS# RDQS
DQS13#
RDQS# RDQS
U0
U4
DQ[0:7]
DQ[32:39]
8
8
DQS5
DQS1
DQS5#
DQS1#
DM5/DQS14
DM1/DQS10
NU/
DM/ CS# DQS# DQS
NU/
DM/ CS# DQS# DQS
DQS14#
RDQS# RDQS
DQS10#
RDQS# RDQS
U5
U1
DQ[40:47]
DQ[8:15]
8
8
DQS6
DQS2
DQS6#
DQS2#
DM6/DQS15
DM2/DQS11
NU/
DM/ CS# DQS# DQS
NU/
DM/ CS# DQS# DQS
DQS15#
RDQS# RDQS
DQS11#
RDQS# RDQS
U6
U2
DQ[48:55]
DQ[16:23]
8
8
DQS7
DQS3
DQS3#
DQS7#
DM7/DQS16
DM3/DQS12
NU/
DM/ CS# DQS# DQS
NU/
DM/ CS# DQS# DQS
DQS16#
RDQS# RDQS
DQS12#
RDQS# RDQS
U7
U3
DQ[56:63]
DQ[24:31]
8
8
DQS8
DQS8#
DM8/DQS17
VDDSPD
NU/
DM/ CS# DQS# DQS
To SPD
DQS17#
RDQS# RDQS
VDD/VDDQ
To U0 - U8
To U0 - U8
To U0 - U8
U8
VREF
CB[0:7]
Vss
8
SERIAL PD
SDA
SCL
A0
SA0
A1 A2
BA0-BA1
A0-A13
RAS#
RBA0-RBA1 -> BA0-BA1 to U0 - U8
RA0-RA13 -> A0-A13 to U0 - U8
RRAS# -> RAS# to U0 - U8
RCAS# -> CAS# to U0 - U8
RWE# -> WE# to U0 - U8
RCKE0 -> CKE0 to U0 - U8
RODT0 -> ODT0 to U0 - U8
RS0# -> CS0# to U0 - U8
SA1 SA2
R
E
G
I
CAS#
WE#
S
T
E
R
CK to U0 - U8
P
L
L
CK0
CKE0
CK# to U0 - U8
CK0#
ODT0
CS0#*
RESET#
CK to all registers
CK# to all registers
RESET#
RST#
Note:
1. *) CS0# connects to DCS# of Register 1 and CSR# of Register 2;
CSR# of Register 1 and DCS# of Register 2 connects to VDD
2. DQ/DM/DQS, address and control resistor values are 22 Ohms.
DDR2_RDIMM_1 rank_x8_spec
Rev. 1.0 - December, 04
Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice.
2004 Wintec Industries, Inc.
3
DDR2-400, 533
Single Rank, x8 Registered SDRAM DIMMs
Absolute Maximum Ratings:
Exposure to stresses greater than these absolute maximum rating conditions for extended periods may affect
reliability of the module.
Symbol
Parameter
Min Max Units
VDD
VDD supply voltage relative to VSS
-1.0
-0.5
-0.5
-0.5
-55
0
2.3
2.3
2.3
2.3
+100
+55
5
V
V
VDD
VDD
Q
L
VDDQ supply voltage relative to VSS
VDDL supply voltage relative to VSS
V
V
VIN, VOUT Voltage on any pin relative to VSS
TSTG
TOPR
IIL
Storage temperature (Tcase)
°C
°C
µA
µA
Operating Temperature (Ambient)
Input Leakage Current; Any input 0V ≤ VIN ≤ 0.95V
Output Leakage Current; 0V ≤ VOUT ≤ VDDQ; DQS and ODT are disabled
-5
-5
IOL
5
DC Operating Conditions:
Parameter
Symbol
Min
1.7
Nom
1.8
Max
Units Notes
Supply Voltage
VDD
1.9
1.9
V
V
1
4
4
2
3
VDDL Supply Voltage
I/O Supply Voltage
I/O Reference Voltage
I/O Termination Voltage (system)
VDD
L
Q
1.7
1.8
VDD
1.7
1.8
1.9
V
VREF
VTT
0.49 x VDD
Q
0.50 x VDD
Q
0.51 x VDD
Q
V
VREF - 40
VREF
VREF + 40
mV
NOTE:
1.
VDD and VDDQ must keep track of each other. VDDQ cannot exceed the value of VDD
2. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same
3. TT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to
V
be set equal to VREF and must track variations in the DC level of VREF
4. VDDQ must tracks VDD; and VDDL tracks VDD
Input/Output Capacitance:
VDD = +1.8V ± 0.1V, VDDQ = +1.8V ± 0.1V, VREF = VSS, f =100MHz, 0°C<TOPR <+55°C, VOUT(DC) = VDDQ/2
Parameter
Symbol
Min
Max
Units
CCK
1.0
2.0
pF
Input Capacitance: CK,
CK
CDCK
CI
-
1.0
0.25
2.0
pF
pF
Delta Input Capacitance: CK,
CK
Input Capacitance: BA0, BA1, A0-A12,
,
,
CS RAS
,
, CKE, ODT
CAS WE
Delta Input Capacitance: BA0, BA1, A0-A12,
CDI
-
0.25
pF
,
CS
,
,
, CKE, ODT
RAS CAS WE
Input/Output Capacitance: DQs, DQS, DM, NF
Delta Input/Output Capacitance: DQs, DQS, DM, NF
CIO
CDIO
3.0
-
4.0
0.5
pF
pF
DDR2_RDIMM_1 rank_x8_spec
Rev. 1.0 - December, 04
Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice.
2004 Wintec Industries, Inc.
4
DDR2-400, 533
Single Rank, x8 Registered SDRAM DIMMs
IDD Specifications and Conditions (256MB - 32Mx8, 9 components):
Symbol
DRAM IC
-5
-3.75
Units
Parameter
Manufacturer*
DDR2-400
DDR2-533
IDD0
Operating Current
MT
INF
SAM
MT
675
N/A
1265
765
720
N/A
1420
810
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD1
Operating Current
INF
SAM
MT
N/A
1330
32
N/A
1540
45
IDD2P
IDD2Q
IDD2N
IDD3P
Precharge Power-Down Current
Precharge Quiet Standby Current
Precharge Standby Current
INF
SAM
MT
N/A
495
N/A
535
189
225
INF
SAM
MT
N/A
665
N/A
715
225
270
INF
SAM
MT
N/A
670
N/A
730
Active Power-Down Standby Current
MRS(12) = 0
135
171
INF
SAM
MT
N/A
720
N/A
750
Active Power-Down Standby Current
MRS(12) = 1
63
81
INF
SAM
MT
N/A
365
N/A
375
IDD3N
IDD4W
IDD4R
IDD5B
IDD6
Active Standby Current
Operating Current Burst Write
Operating Current Burst Read
Burst Auto-Refresh Current
Self Refresh Current
288
351
INF
SAM
MT
N/A
1065
1125
N/A
1635
990
N/A
1180
1440
N/A
2115
1260
N/A
1840
1530
N/A
2005
27
INF
SAM
MT
INF
SAM
MT
N/A
1520
1485
N/A
1900
27
N/A
485
2070
N/A
2885
INF
SAM
MT
INF
SAM
MT
N/A
555
2160
N/A
2975
IDD7
Operating Current
INF
SAM
Note:
DRAM IC Manufacturer* - MT = Micron, INF = Infineon, SAM=Samsung
DDR2_RDIMM_1 rank_x8_spec
Rev. 1.0 - December, 04
Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice.
2004 Wintec Industries, Inc.
5
DDR2-400, 533
Single Rank, x8 Registered SDRAM DIMMs
IDD Specifications and Conditions (512MB - 64Mx8, 9 components):
Symbol
DRAM IC
-5
-3.75
Units
Parameter
Manufacturer*
DDR2-400
DDR2-533
IDD0
Operating Current
MT
INF
SAM
MT
TBD
745
TBD
918
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
1265
TBD
790
1420
TBD
1008
1540
TBD
369
IDD1
Operating Current
INF
SAM
MT
1330
TBD
286
IDD2P
IDD2Q
IDD2N
IDD3P
Precharge Power-Down Current
Precharge Quiet Standby Current
Precharge Standby Current
INF
SAM
MT
495
535
TBD
475
TBD
603
INF
SAM
MT
665
715
TBD
538
TBD
639
INF
SAM
MT
670
730
Active Power-Down Standby Current
MRS(12) = 0
TBD
367
TBD
477
INF
SAM
MT
720
750
Active Power-Down Standby Current
MRS(12) = 1
TBD
295
TBD
378
INF
SAM
MT
365
375
IDD3N
IDD4W
IDD4R
IDD5B
IDD6
Active Standby Current
Operating Current Burst Write
Operating Current Burst Read
Burst Auto-Refresh Current
Self Refresh Current
TBD
565
TBD
693
INF
SAM
MT
1065
TBD
925
1180
TBD
1188
2340
TBD
1143
2020
TBD
1503
2275
TBD
36
INF
SAM
MT
1725
TBD
880
INF
SAM
MT
1655
TBD
1330
2125
TBD
36
INF
SAM
MT
INF
SAM
MT
490
560
IDD7
Operating Current
TBD
1420
3020
TBD
1593
3155
INF
SAM
Note:
DRAM IC Manufacturer* - MT = Micron, INF = Infineon, SAM=Samsung
DDR2_RDIMM_1 rank_x8_spec
Rev. 1.0 - December, 04
Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice.
2004 Wintec Industries, Inc.
6
DDR2-400, 533
Single Rank, x8 Registered SDRAM DIMMs
Electrical Characteristics and AC Timings:
VDD = +1.8V ± 0.1V, VDDQ = +1.8V ± 0.1V, VREF = VSS, f =100MHz, 0°C<TOPR <+55°C, VOUT(DC) = VDDQ/2
Symbol
-5
-3.75
Units
Parameter
DDR2-400
DDR2-533
MIN
MAX
MIN
MAX
tAC
-600
-500
+600
-500
-450
+500 ps
+450 ps
DQ output access time from CK/
CK
tDQSCK
+500
DQS output access time from CK/
CK
CK high-level width
CK low-level width
CK half period
tCH
tCL
tHP
0.45
0.45
0.55
0.55
-
0.45
0.45
0.55
0.55
-
tCK
tCK
ps
MIN
(tCH,
tCL)
MIN
(tCH,
tCL)
Clock cycle time
tCK CL=3
5,000
CL=4 & 5 5,000
8,000
8,000
5,000
3,750
8,000 ps
8,000 ps
DQ and DM input hold time
DQ and DM input setup time
tDH
tDS
400
400
0.6
-
-
-
350
350
0.6
-
-
-
ps
ps
Control & Address input pulse width for tIPW
tCK
each input
DQ and DM input pulse width for each tDIPW
input
0.35
-
0.35
-
tCK
ps
-
tACmax
-
tACmax
Data-out high-impedance time from
tHZ
CK/
CK
Data-out low-impedance time from
CK/
tACmin
tACmax
tACmin
tACmax
tLZ
ps
ps
CK
DQS-DQ skew for DQS and associated DQ tDQSQ
signals
-
350
-
300
Data hold skew factor
tQHS
tQH
-
450
-
-
400
-
ps
ps
Data output hold time from DQS
tHP-
tHP-
tQHS
WL-0.25
tQHS
WL-0.25
Write command to 1st DQS latching
transition
DQS input low/high pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
tDQSS
WL+
0.25
-
-
-
-
WL+ tCK
0.25
tDQSL/H
tDSS
0.35
0.2
0.2
2
0.35
0.2
0.2
2
-
-
-
-
tCK
tCK
tCK
tCK
tDSH
Mode register set command cycle time tMRD
Write preamble setup time
Write preamble
tWPRES
0
-
0
-
-
ps
tWPRE
tWPST
tRPRE
tRPST
tRAS
tRC
0.25
0.40
0.9
0.4
45
-
0.25
0.40
0.9
0.4
45
tCK
tCK
tCK
tCK
Write postamble
0.60
0.60
1.1
0.6
Read preamble
Read postamble
Active to Precharge command
Active to Active command period
Refresh to Refresh command interval
Active to Read/Write delay
Precharge command period
1.1
0.6
70,000
70,000 ns
60
-
-
-
-
60
-
-
-
-
ns
ns
ns
ns
tRFC
tRCD
tRP
105
15
105
15
15
15
DDR2_RDIMM_1 rank_x8_spec
Rev. 1.0 - December, 04
Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice.
2004 Wintec Industries, Inc.
7
DDR2-400, 533
Single Rank, x8 Registered SDRAM DIMMs
VDD = +1.8V ± 0.1V, VDDQ = +1.8V ± 0.1V, VREF = VSS, f =100MHz, 0°C<TOPR <+55°C, VOUT(DC) = VDDQ/2
Symbol
-5
-3.75
Units
Parameter
DDR2-400
DDR2-533
MIN
MAX
MIN
MAX
Active bank A to Active bank B command tRRD
7.5
2
-
7.5
2
15
-
ns
tCK
ns
tCK
tCCD
tWR
A to
B command period
CAS
CAS
Write recovery time
15
-
-
WR+tRP
-
WR+tRP
-
Auto Precharge write recovery + Precharge tDAL
time
Internal Write to Read command delay
tWTR
10
7.5
2
-
-
-
7.5
7.5
2
-
-
-
ns
Internal Read to Precharge command delay tRTP
Exit precharge power down to any non-Read tXP
command
ns
tCK
Exit Self-Refresh to Read command
tXSRD
200
-
200
-
tCK
ns
tRFC+10
-
tRFC+10
-
Exit Self-Refresh to non-Read command tXSNR
CKE minimum high and low pulse width tCKE
3
-
-
3
-
0
-
tCK
µs
Average periodic refresh interval
OCD drive mode output delay
tREFI
tOIT
tDELAY
7.8
7.8
0
12
12
ns
ns
tIS+tCK
+tIH
-
tIS+tCK
+tIH
-
CKE low to CK,
uncertainty
CK
Note: These parameters are applicable for all 3 chip manufacturers, Micron, Infineon, and Samsung.
DDR2_RDIMM_1 rank_x8_spec
Rev. 1.0 - December, 04
Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice.
2004 Wintec Industries, Inc.
8
DDR2-400, 533
Single Rank, x8 Registered SDRAM DIMMs
Physical Dimensions – Layout A:
Layout A: DDR2 Registered DIMM Raw Card A
One physical rank, 9 components x8 organised
240
184 185
Pin 121
BACK
5.250/(133.35±0.15)
5.171/(131.35)
0.106/(2.7) Max
0.1575/(4.0)
1.181/(30.0)
PLL
64
0.039/
(1.0)
0.05/
Pin 1
0.10/(2.54)
0.118/(3.0)
120
0.25/(6.35)
2.55/(64.77)
65
0.050±0.004/
(1.27±0.1)
(1.27)
1.95/(49.5)
5.014/(127.35)
SIDE
FRONT
Note:
1. Dimensions are in inches/(mm)
2. Outline dimensions and tolerances are in accordance with the JEDEC standard (MO-237)
DDR2_RDIMM_1 rank_x8_spec
Rev. 1.0 - December, 04
Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice.
2004 Wintec Industries, Inc.
9
DDR2-400, 533
Single Rank, x8 Registered SDRAM DIMMs
Physical Dimensions – Layout B:
Layout B: 1" height DDR2 Registered DIMM Raw Card A
One physical rank, 9 components x8 organised
240
184 185
Pin 121
BACK
5.250/(133.35±0.15)
5.171/(131.35)
0.106/(2.7) Max
0.1575/(4.0)
1.0/(25.4)
PLL
64
0.039/
(1.0)
0.05/
Pin 1
0.050±0.004/
(1.27±0.1)
0.10/(2.54)
0.118/(3.0)
120
0.25/(6.35)
2.55/(64.77)
65
(1.27)
1.95/(49.5)
5.014/(127.35)
SIDE
FRONT
Note:
1. Dimensions are in inches/(mm)
2. Outline dimensions and tolerances are in accordance with the JEDEC standard (MO-237)
DDR2_RDIMM_1 rank_x8_spec
Rev. 1.0 - December, 04
Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice.
2004 Wintec Industries, Inc.
10
DDR2-400, 533
Single Rank, x8 Registered SDRAM DIMMs
Product Ordering Guide:
256MB - W1D32M72R8
512MB - W1D64M72R8
1GB
2GB
- W1D128M72R8
- W1D256M72R8 (Preliminary*)
DDR II Product Ordering Guide
W 1 D 32 M 72 R 8 A - 5A E - P A 1
PCB Rev. Control
Initial release
1st Revision
2nd Revision
Blank
1
2
Die Rev. Control
A
B
A Die
B Die
DRAM IC Vendor
P
Q
H
F
J
Samsung
Infineon
Micron
Promos/Vitelic
Nanya
Options
E
L
P
R
Industrial Temp
Custom Labeling
Low Power
Reduced SPD Program
Contact Us:
Wintec Industries
Module S peed
Data Rate Mo dule Bandwidth
Co mpo nent
Speed Grade
OEM & Industrial Solutions
4280 Technology Drive
Fremont, CA 94538
Ph: 510-360-6246
5A
3.75A
400-333
533-444
PC2-3200
PC2-4200
Fx: 510-770-9338
oemsales@wintecind.com
PCB Layout
See Front page/Module Dimension for details
http://www.wintecind.com/oem
DDR2_RDIMM_1 rank_x8_spec
Rev. 1.0 - December, 04
Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice.
2004 Wintec Industries, Inc.
11
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