XA2C64A-8VQG44Q
更新时间：2024-09-18 18:15:23
品牌：XILINX
描述：Flash PLD, 7.5ns, 64-Cell, CMOS, PQFP44, 10 X 10 MM, 0.80 MM PITCH, VQFP-44
概述
规格参数
数据手册
替代型号XA2C64A-8VQG44Q 概述
Flash PLD, 7.5ns, 64-Cell, CMOS, PQFP44, 10 X 10 MM, 0.80 MM PITCH, VQFP-44 CPLD芯片 可编程逻辑器件
XA2C64A-8VQG44Q 规格参数
| 是否无铅： | 不含铅 | 是否Rohs认证： | 符合 |
| 生命周期： | Active | 零件包装代码： | QFP |
| 包装说明： | TQFP, TQFP44,.47SQ,32 | 针数： | 44 |
| Reach Compliance Code： | compliant | ECCN代码： | EAR99 |
| HTS代码： | 8542.39.00.01 | Factory Lead Time： | 12 weeks |
| 风险等级： | 1.6 | 其他特性： | REAL DIGITAL DESIGN TECHNOLOGY |
| 系统内可编程： | YES | JESD-30 代码： | S-PQFP-G44 |
| JESD-609代码： | e3 | JTAG BST： | YES |
| 长度： | 10 mm | 湿度敏感等级： | 3 |
| 专用输入次数： | I/O 线路数量： | 33 | |
| 宏单元数： | 64 | 端子数量： | 44 |
| 最高工作温度： | 125 °C | 最低工作温度： | -40 °C |
| 组织： | 0 DEDICATED INPUTS, 33 I/O | 输出函数： | MACROCELL |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | TQFP |
| 封装等效代码： | TQFP44,.47SQ,32 | 封装形状： | SQUARE |
| 封装形式： | FLATPACK, THIN PROFILE | 峰值回流温度（摄氏度）： | 260 |
| 电源： | 1.5/3.3,1.8 V | 可编程逻辑类型： | FLASH PLD |
| 传播延迟： | 7.5 ns | 认证状态： | Not Qualified |
| 筛选级别： | AEC-Q100 | 座面最大高度： | 1.2 mm |
| 子类别： | Programmable Logic Devices | 最大供电电压： | 1.9 V |
| 最小供电电压： | 1.7 V | 标称供电电压： | 1.8 V |
| 表面贴装： | YES | 技术： | CMOS |
| 温度等级： | AUTOMOTIVE | 端子面层： | Matte Tin (Sn) |
| 端子形式： | GULL WING | 端子节距： | 0.8 mm |
| 端子位置： | QUAD | 处于峰值回流温度下的最长时间： | 30 |
| 宽度： | 10 mm | Base Number Matches： | 1 |
XA2C64A-8VQG44Q 数据手册
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XA2C64A CoolRunner-II
Automotive CPLD
0
0
DS553 (v1.1) May 5, 2007
Product Specification
Refer to the CoolRunner™-II Automotive CPLD family data
sheet for architecture description.
Features
•
AEC-Q100 device qualification and full PPAP support
available in both I-grade and extended temperature
Q-grade
WARNING: Programming temperature range of
TA = 0° C to +70° C.
•
Guaranteed to meet full electrical specifications over
TA = -40° C to +105° C with TJ Maximum = +125° C
Description
(Q-grade)
The CoolRunner-II Automotive 64-macrocell device is
designed for both high performance and low power applica-
tions. This lends power savings to high-end communication
equipment and high speed to battery operated devices. Due
to the low power stand-by and dynamic operation, overall
system reliability is improved
•
•
Optimized for 1.8V systems
Industry’s best 0.18 micron CMOS CPLD
-
-
Optimized architecture for effective logic synthesis
Multi-voltage I/O operation — 1.5V to 3.3V
•
•
Available in the following package options
This device consists of four Function Blocks inter-con-
nected by a low power Advanced Interconnect Matrix (AIM).
The AIM feeds 40 true and complement inputs to each
Function Block. The Function Blocks consist of a 40 by 56
P-term PLA and 16 macrocells which contain numerous
configuration bits that allow for combinational or registered
modes of operation.
-
-
-
44-pin VQFP with 33 user I/O
100-pin VQFP with 64 user I/O
Pb-free only for all packages
Advanced system features
-
Fastest in system programming
1.8V ISP using IEEE 1532 (JTAG) interface
·
-
-
-
-
IEEE1149.1 JTAG Boundary Scan Test
Optional Schmitt-trigger input (per pin)
Two separate I/O banks
RealDigital™ 100% CMOS product term
generation
Additionally, these registers can be globally reset or preset
and configured as a D or T flip-flop or as a D latch. There
are also multiple clock signals, both global and local product
term types, configured on a per macrocell basis. Output pin
configurations include slew rate limit, bus hold, pull-up,
open drain and programmable grounds. A Schmitt trigger
input is available on a per input pin basis. In addition to stor-
ing macrocell output states, the macrocell registers may be
configured as "direct input" registers to store signals directly
from input pins.
-
-
Flexible clocking modes
·
Optional DualEDGE triggered registers
Global signal options with macrocell control
·
Multiple global clocks with phase selection per
macrocell
·
·
Multiple global output enables
Global set/reset
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as
a synchronous clock source. Macrocell registers can be
individually configured to power up to the zero or one state.
A global set/reset control line is also available to asynchro-
nously set or reset selected registers during operation.
Additional local clock, synchronous clock-enable, asynchro-
nous set/reset and output enable signals can be formed
using product terms on a per-macrocell or per-Function
Block basis.
-
Efficient control term clocks, output enables and
set/resets for each macrocell and shared across
function blocks
Advanced design security
Optional bus-hold, 3-state or weak pullup on
selected I/O pins
Open-drain output option for Wired-OR and LED
drive
Optional configurable grounds on unused I/Os
Mixed I/O voltages compatible with 1.5V, 1.8V,
2.5V, and 3.3V logic levels
-
-
-
-
-
A DualEDGE flip-flop feature is also available on a per mac-
rocell basis. This feature allows high performance synchro-
nous operation based on lower frequency clocking to help
reduce the total power consumption of the device.
-
PLA architecture
·
·
Superior pinout retention
100% product term routability across function
block
The CoolRunner-II Automotive 64-macrocell CPLD is I/O
compatible with standard LVTTL and LVCMOS18,
LVCMOS25, and LVCMOS33 (see Table 1). This device is
-
Hot pluggable
© 2006, 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS553 (v1.1) May 5, 2007
www.xilinx.com
1
Product Specification
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XA2C64A CoolRunner-II Automotive CPLD
also 1.5V I/O compatible with the use of Schmitt-trigger
inputs.
Supported I/O Standards
The CoolRunner-II Automotive 64-macrocell features both
LVCMOS and LVTTL I/O implementations. See Table 1 for
I/O standard voltages. The LVTTL I/O standard is a general
purpose EIA/JEDEC standard for 3.3V applications that use
an LVTTL input buffer and Push-Pull output buffer. The
LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications.
CoolRunner-II Automotive CPLDs are also 1.5V I/O com-
patible with the use of Schmitt-trigger inputs.
Another feature that eases voltage translation is I/O bank-
ing. Two I/O banks are available on the CoolRunner-II Auto-
motive 64-macrocell device that permit easy interfacing to
3.3V, 2.5V, 1.8V, and 1.5V devices.
RealDigital Design Technology
Xilinx CoolRunner-II Automotive CPLDs are fabricated on a
0.18 micron process technology which is derived from lead-
ing edge FPGA product development. CoolRunner-II Auto-
motive CPLDs employ RealDigital, a design technique that
makes use of CMOS technology in both the fabrication and
design methodology. RealDigital design technology
employs a cascade of CMOS gates to implement sum of
products instead of traditional sense amplifier methodology.
Due to this technology, Xilinx CoolRunner-II Automotive
CPLDs achieve both high performance and low power oper-
ation.
Table 1: I/O Standards for XA2C64A
IOSTANDARD Attribute Output VCCIO Input VCCIO
LVTTL
3.3
3.3
2.5
1.8
1.5
3.3
3.3
2.5
1.8
1.5
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15(1)
(1) LVCMOS15 requires Schmitt-trigger inputs.
15
10
5
0
50
100
150
0
Frequency (MHz)
DS553_01_092106
Figure 1: ICC vs Frequency
Table 2: ICC vs Frequency (LVCMOS 1.8V TA = 25°C)(1)
Frequency (MHz)
0
25
50
75
100
150
Typical ICC (mA)
0.017
1.8
3.7
5.5
7.48
11.0
Notes:
1. 16-bit up/down, Resetable binary counter (one counter per function block).
2
www.xilinx.com
DS553 (v1.1) May 5, 2007
Product Specification
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XA2C64A CoolRunner-II Automotive CPLD
Absolute Maximum Ratings
Symbol
Description
Supply voltage relative to ground
Supply voltage for output drivers
Value
Units
V
VCC
–0.5 to 2.0
–0.5 to 4.0
–0.5 to 4.0
–0.5 to 4.0
–0.5 to 4.0
–0.5 to 4.0
–65 to +150
+125
VCCIO
V
(2)
VJTAG
JTAG input voltage limits
V
VCCAUX
JTAG input supply voltage
Input voltage relative to ground(1)
Voltage applied to 3-state output(1)
Storage Temperature (ambient)
Junction Temperature
V
(1)
VIN
V
(1)
VTS
V
(3)
VSTG
°C
°C
TJ
Notes:
1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easiest to achieve. During transitions,
the device pins may undershoot to –2.0v or overshoot to +4.5V, provided this over or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA.
2. Valid over commercial temperature range.
3. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb free
packages, see XAPP427.
Recommended Operating Conditions
Symbol
Parameter
Min
1.7
1.7
Max
1.9
Units
VCC
Supply voltage for internal logic
and input buffers
Industrial TA = –40°C to +85°C
V
V
Q-Grade TA = -40° C to +105° C
TJ Maximum = +125° C
1.9
VCCIO
Supply voltage for output drivers @ 3.3V operation
Supply voltage for output drivers @ 2.5V operation
Supply voltage for output drivers @ 1.8V operation
Supply voltage for output drivers @ 1.5V operation
JTAG programming pins
3.0
2.3
1.7
1.4
1.7
3.6
2.7
1.9
1.6
3.6
V
V
V
V
V
VCCAUX
DC Electrical Characteristics (Over Recommended Operating Conditions)
Symbol
ICCSB
Parameter
Standby current Industrial
Standby current Q-grade
Dynamic current
Test Conditions
VCC = 1.9V, VCCIO = 3.6V
VCC = 1.9V, VCCIO = 3.6V
f = 1 MHz
Typical
Max.
Units
μA
43
43
-
165
700
1.50
7
ICCSB
μA
(1)
ICC
mA
mA
pF
f = 50 MHz
-
CJTAG
CCLK
CIO
JTAG input capacitance
Global clock input capacitance
I/O capacitance
f = 1 MHz
-
10
f = 1 MHz
-
12
pF
f = 1 MHz
-
10
pF
(2)
IIL
Input leakage current
I/O High-Z leakage
VIN = 0V or VCCIO to 3.9V
VIN = 0V or VCCIO to 3.9V
-
+/–10
+/–10
μA
(2)
IIH
-
μA
Notes:
1. 16-bit up/down, Resetable binary counter (one counter per function block) tested at VCC=VCCIO= 1.9V.
DS553 (v1.1) May 5, 2007
www.xilinx.com
3
Product Specification
R
XA2C64A CoolRunner-II Automotive CPLD
LVCMOS 3.3V and LVTTL 3.3V DC Voltage Specifications
Symbol
VCCIO
VIH
Parameter
Input source voltage
High level input voltage
Low level input voltage
Test Conditions
Min.
Max.
3.6
3.9
0.8
-
Units
V
3.0
2
V
VIL
–0.3
V
VOH
High level output voltage,
Industrial grade
IOH = –8 mA, VCCIO = 3V
OH = –0.1 mA, VCCIO = 3V
VCCIO – 0.4V
V
I
VCCIO – 0.2V
-
V
High level output voltage,
Q-grade
I
OH = –4 mA, VCCIO = 3V
VCCIO – 0.4V
-
V
I
OH = –0.1 mA, VCCIO = 3V
IOL = 8 mA, VCCIO = 3V
IOL = 0.1 mA, VCCIO = 3V
VCCIO – 0.2V
-
V
VOL
Low level output voltage,
Industrial grade
-
-
-
-
0.4
0.2
0.4
0.2
V
V
Low level output voltage,
Q-grade
IOL = 4 mA, VCCIO = 3V
V
I
OL = 0.1 mA, VCCIO = 3V
V
LVCMOS 2.5V DC Voltage Specifications
Symbol
VCCIO
VIH
Parameter
Input source voltage
High level input voltage
Low level input voltage
Test Conditions
Min.
2.3
Max.
Units
V
2.7
1.7
VCCIO + 0.3(1)
V
VIL
–0.3
0.7
-
V
VOH
High level output voltage,
Industrial grade
IOH = –8 mA, VCCIO = 2.3V
VCCIO – 0.4V
V
I
OH = –0.1 mA, VCCIO = 2.3V VCCIO – 0.2V
OH = –4 mA, VCCIO = 2.3V VCCIO – 0.4V
OH = –0.1 mA, VCCIO = 2.3V VCCIO – 0.2V
-
V
High level output voltage,
Q-grade
I
-
V
I
-
V
VOL
Low level output voltage,
Industrial grade
IOL = 8 mA, VCCIO = 2.3V
OL = 0.1 mA, VCCIO = 2.3V
-
-
-
-
0.4
0.2
0.4
0.2
V
I
I
V
Low level output voltage, Q-grade
I
OL = 4 mA, VCCIO = 2.3V
V
OL = 0.1 mA, VCCIO = 2.3V
V
1. The VIH Max value represents the JEDEC specification for LVCMOS25. The CoolRunner-II input buffer can tolerate up
to 3.9V without physical damage.
4
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DS553 (v1.1) May 5, 2007
Product Specification
R
XA2C64A CoolRunner-II Automotive CPLD
LVCMOS 1.8V DC Voltage Specifications
Symbol
VCCIO
VIH
Parameter
Input source voltage
High level input voltage
Low level input voltage
Test Conditions
Min.
Max.
Units
V
-
1.7
1.9
-
0.65 x VCCIO VCCIO + 0.3(1)
V
VIL
-
–0.3
0.35 x VCCIO
V
VOH
High level output voltage,
Industrial grade
IOH = –8 mA, VCCIO = 1.7V
OH = –0.1 mA, VCCIO = 1.7V
VCCIO – 0.45
-
-
V
I
VCCIO – 0.2
V
High level output voltage, Q-grade
I
OH = –4 mA, VCCIO = 1.7V
VCCIO – 0.45
-
V
I
OH = –0.1 mA, VCCIO = 1.7V
IOL = 8 mA, VCCIO = 1.7V
IOL = 0.1 mA, VCCIO = 1.7V
VCCIO – 0.2
-
V
VOL
Low level output voltage, Industrial
grade
-
-
-
-
0.45
0.2
0.45
0.2
V
V
Low level output voltage, Q-grade
I
OL = 4 mA, VCCIO = 1.7V
V
IOL = 0.1 mA, VCCIO = 1.7V
V
1. The VIH Max value represents the JEDEC specification for LVCMOS18. The CoolRunner-II input buffer can tolerate up
to 3.9V without physical damage.
(1)
LVCMOS 1.5V DC Voltage Specifications
Symbol
VCCIO
VT+
Parameter
Test Conditions
Min.
Max.
Units
V
Input source voltage
-
1.4
1.6
Input hysteresis threshold voltage
-
0.5 x VCCIO
0.8 x VCCIO
V
VT-
-
0.2 x VCCIO
0.5 x VCCIO
V
VOH
High level output voltage,
Industrial grade
IOH = –8 mA, VCCIO = 1.4V
OH = –0.1 mA, VCCIO = 1.4V
VCCIO – 0.45
-
-
V
I
VCCIO – 0.2
V
High level output voltage, Q-grade
I
OH = –4 mA, VCCIO = 1.4V
VCCIO – 0.45
-
V
I
OH = –0.1 mA, VCCIO = 1.4V
IOL = 8 mA, VCCIO = 1.4V
VCCIO – 0.2
-
V
VOL
Low level output voltage, Industrial
grade
-
-
-
-
0.4
0.2
0.4
0.2
V
I
OL = 0.1 mA, VCCIO = 1.4V
OL = 4 mA, VCCIO = 1.4V
OL = 0.1 mA, VCCIO = 1.4V
V
Low level output voltage, Q-grade
I
V
I
V
Notes:
1. Hysteresis used on 1.5V inputs.
Schmitt Trigger Input DC Voltage Specifications
Symbol
VCCIO
VT+
Parameter
Test Conditions
Min.
1.4
Max.
3.9
Units
Input source voltage
-
-
-
V
V
V
Input hysteresis threshold voltage
0.5 x VCCIO
0.2 x VCCIO
0.8 x VCCIO
0.5 x VCCIO
VT-
DS553 (v1.1) May 5, 2007
www.xilinx.com
5
Product Specification
R
XA2C64A CoolRunner-II Automotive CPLD
AC Electrical Characteristics Over Recommended Operating Conditions
-7
-8
Symbol
TPD1
Parameter
Propagation delay single p-term
Min.
-
Max.
Min.
-
Max. Units
6.7
6.7
ns
ns
TPD2
TSUD
TSU1
TSU2
THD
Propagation delay OR array
-
7.5
-
7.5
Direct input register clock setup time
Setup time (single p-term)
3.3
2.5
3.3
0.0
0.0
-
-
3.3
2.8
3.6
0.0
0.0
-
-
ns
-
-
ns
Setup time (OR array)
-
-
-
-
ns
Direct input register hold time
P-term hold time
ns
TH
-
-
ns
TCO
Clock to output
6.0
300
159
141
118
108
-
6.0
300
152
135
114
104
-
ns
FTOGGLE
Internal toggle rate(1)
-
-
MHz
MHz
MHz
MHz
MHz
ns
(1)
FSYSTEM1
Maximum system frequency(2)
Maximum system frequency(2)
Maximum external frequency(3)
Maximum external frequency(3)
Direct input register p-term clock setup time
P-term clock setup time (single p-term)
P-term clock setup time (OR array)
Direct input register p-term clock hold time
P-term clock hold
-
-
(2)
(2)
FSYSTEM2
-
-
(3)
FEXT1
-
-
(3)
FEXT2
-
-
TPSUD
TPSU1
TPSU2
TPHD
TPH
1.7
0.9
1.7
1.4
2.7
-
1.7
0.9
1.7
1.4
2.7
-
-
-
ns
-
-
ns
-
-
ns
-
-
ns
TPCO
P-term clock to output
8.4
10.0
11.0
11.0
9.7
8.3
-
8.4
10.0
11.0
11.0
9.7
8.3
-
ns
TOE/TOD
TPOE/TPOD
TMOE/TMOD
Global OE to output enable/disable
P-term OE to output enable/disable
Macrocell driven OE to output enable/disable
P-term set/reset to output valid
Global set/reset to output valid
Register clock enable setup time
Register clock enable hold time
Global clock pulse width High or Low
P-term pulse width High or Low
Asynchronous preset/reset pulse width (High or Low)
Configuration time
-
-
ns
-
-
ns
-
-
ns
TPAO
TAO
-
-
ns
-
-
ns
TSUEC
THEC
3.7
0.0
2.2
7.5
7.5
-
3.7
0.0
2.2
7.5
7.5
-
ns
-
-
ns
TCW
-
-
ns
TPCW
TAPRPW
TCONFIG
Notes:
-
-
ns
-
-
ns
(4)
50.0
50
μs
1. FTOGGLE is the maximum frequency of a dual edge triggered T flip-flop with output enabled.
2. FSYSTEM (1/TCYCLE) is the internal operating frequency for a device fully populated with 16-bit up/down, Resetable binary counter
(one counter per function block).
3.
FEXT (1/TSU1+TCO) is the maximum external frequency.
4. Typical configuration current during TCONFIG is 2.3 mA.
6
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DS553 (v1.1) May 5, 2007
Product Specification
R
XA2C64A CoolRunner-II Automotive CPLD
Internal Timing Parameters
-7
-8
Symbol
Buffer Delays
TIN
Parameter(1)
Min.
Max.
Min.
Max.
Units
Input buffer delay
-
-
-
-
-
-
-
2.4
4.0
2.5
3.5
3.9
2.8
6.1
-
-
-
-
-
-
-
2.4
3.7
2.5
3.5
3.9
2.8
6.1
ns
ns
ns
ns
ns
ns
ns
TDIN
Direct data register input delay
Global clock buffer delay
Global set/reset buffer delay
Global 3-state buffer delay
Output buffer delay
TGCK
TGSR
TGTS
TOUT
TEN
Output buffer enable/disable delay
P-term Delays
TCT
Control term delay
-
-
-
2.5
0.8
0.8
-
-
-
2.5
0.8
0.8
ns
ns
ns
TLOGI1
TLOGI2
Macrocell Delay
TPDI
Single P-term delay adder
Multiple P-term delay adder
Input to output valid
-
-
0.7
2.5
-
-
-
0.7
2.5
-
ns
ns
ns
ns
ns
ns
ns
ns
TLDI
Setup before clock (transparent latch)
Setup before clock
TSUI
1.8
0.0
1.3
0.0
-
2.1
0.0
1.3
0.0
-
THI
Hold after clock
-
-
TECSU
TECHO
TCOI
Enable clock setup time
Enable clock hold time
Clock to output valid
-
-
-
-
0.7
2.0
0.7
2.0
TAOI
Set/reset to output valid
-
-
Feedback Delays
TF
Feedback delay
-
-
3.0
1.7
-
-
3.0
1.7
ns
ns
TOEM
Macrocell to global OE delay
I/O Standard Time Adder Delays 1.5VCMOS
THYS15
TOUT15
TSLEW15
Hysteresis input adder
Output adder
-
-
-
6.0
1.5
6.0
-
-
-
6.0
1.5
6.0
ns
ns
ns
Output slew rate adder
I/O Standard Time Adder Delays 1.8V CMOS
THYS18
TOUT18
TSLEW
Hysteresis input adder
Output adder
-
-
-
4.0
0.0
5.0
-
-
-
4.0
0.0
5.0
ns
ns
ns
Output slew rate adder
DS553 (v1.1) May 5, 2007
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7
Product Specification
R
XA2C64A CoolRunner-II Automotive CPLD
Internal Timing Parameters (Continued)
-7
-8
Symbol
Parameter(1)
Min.
Max.
Min.
Max.
Units
I/O Standard Time Adder Delays 2.5V CMOS
TIN25
Standard input adder
Hysteresis input adder
Output adder
-
-
-
-
0.6
3.0
0.9
5.0
-
-
-
-
0.7
3.0
1.0
5.5
ns
ns
ns
ns
THYS25
TOUT25
TSLEW25
Output slew rate adder
I/O Standard Time Adder Delays 3.3V CMOS/TTL
TIN33
Standard input adder
Hysteresis input adder
Output adder
-
-
-
-
0.6
3.0
1.4
5.0
-
-
-
-
0.8
3.0
1.7
6.6
ns
ns
ns
ns
THYS33
TOUT33
TSLEW33
Output slew rate adder
(1) 1.5 ns input pin signal rise/fall.
8
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DS553 (v1.1) May 5, 2007
Product Specification
R
XA2C64A CoolRunner-II Automotive CPLD
Switching Characteristics
Typical I/O Output Curves
VCC = VCCIO = 1.8V, T = 25oC
Vdde1
1.5V
5.5
1.8V
2.5V
3.3V
5.0
4.5
4.0
3.5
3.0
Vo Output Volts
1
2
4
8
16
Figure 4: Typical I/O Output Curves
Number of Outputs Switching
DS092_02_092302
Figure 2: Derating Curve for TPD
AC Test Circuit
V
CC
R
1
Device
Under Test
Test Point
R
C
L
2
Output Type
LVTTL33
R
R
2
235Ω
275Ω
C
L
1
268Ω
275Ω
188Ω
112.5Ω
150Ω
35 pF
35 pF
35 pF
35 pF
35 pF
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
Notes:
188Ω
112.5Ω
150Ω
1. C includes test fixtures and probe capacitance.
L
2. 1.5 nsec maximum rise/fall times on inputs.
DS092_03_092302
Figure 3: AC Load Circuit
DS553 (v1.1) May 5, 2007
Product Specification
www.xilinx.com
9
R
XA2C64A CoolRunner-II Automotive CPLD
Pin Descriptions
Function Block
Macrocell
VQG44
VQG100
13
12
11
10
9
I/O Banking
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
1
1
2
38
37
36
-
1
1
3
1
4
1
5
-
1
6
-
8
1
7
-
7
1
8
-
6
1(GTS1)
9
34
33
32
31
30
-
4
1(GTS0)
10
11
12
13
14
15
16
1
3
1(GTS3)
2
1(GTS2)
1
1(GSR)
99
97
94
92
14
15
16
17
18
19
22
23
24
27
28
29
30
32
33
34
1
1
-
1
-
2
39
40
-
2
2
2
3
2
4
-
2
5
41
42
43
44
-
2
6
2(GCK0)
7
2(GCK1)
8
2
9
2(GCK2)
10
11
12
13
14
15
16
1
2
2
2
2
2
2
-
2
3
-
-
-
10
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DS553 (v1.1) May 5, 2007
Product Specification
R
XA2C64A CoolRunner-II Automotive CPLD
Pin Descriptions (Continued)
Function Block
Macrocell
VQG44
VQG100
91
90
89
81
79
78
77
76
74
72
71
70
68
67
64
61
35
36
37
39
40
41
42
43
49
50
52
53
55
56
58
60
I/O Banking
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
1
2
29
28
27
-
3
4
5
-
6
23
-
7
8
-
9
-
10
11
12
13
14
15
16
1
22
21
20
-
19
18
-
5
2
6
3
-
4
-
5
-
6
-
7
8
8
-
9
-
10
11
12
13
14
15
16
-
12
-
13
14
16
-
1. GTS = global output enable, GSR = global set reset, GCK = global clock.
2. GCK, GSR, and GTS pins can also be used for general purpose I/O.
DS553 (v1.1) May 5, 2007
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11
Product Specification
R
XA2C64A CoolRunner-II Automotive CPLD
XA2C64A Global, JTAG, Power/Ground and No Connect Pins
Pin Type
PC44
17
VQ44
11
QFG48
23
CP56
K10
J10
A6
VQ100
48
TCK
TDI
15
9
21
45
TDO
TMS
30
24
40
83
16
10
22
K9
47
VCCAUX (JTAG supply
voltage)
41
35
3
D3
5
Power internal (VCC
)
21
13
15
7
29
19
G8
H6
26,57
38, 51
Power bank 1 I/O (VCCIO1
Power bank 2 I/O (VCCIO2
Ground
)
)
32
26
42
C6
88, 98
10, 23, 31
4,17,25
16, 31, 41
H4, F8, C7
21, 31, 62, 69, 84,100
No connects
20, 25, 44, 46, 54, 59, 63,
65, 66, 73, 75, 80, 82, 85,
86, 87, 93, 95, 96
Total user I/O
33
33
37
45
64
Ordering Information
Ind. (I)(1)
Device Ordering No. Pin/Ball
and Part Marking No. Spacing (C/Watt) (C/Watt)
θJA
θJC
Package Body
Dimensions
Package Type
I/O
Hi-T (Q)
XA2C64A-7VQG44I
XA2C64A-8VQG44Q
XA2C64A-7VQG100I
0.8mm
0.8mm
0.5mm
46.6
46.6
53.2
53.2
8.2
8.2
Very Thin Quad Flat
Pack; Pb-free
10mm x 10mm
33
I
Very Thin Quad Flat
Pack; Pb-free
10mm x 10mm
14mm x 14mm
14mm x 14mm
33
64
64
Q
I
14.6
14.6
Very Thin Quad Flat
Pack; Pb-free
XA2C64A-8VQG100Q 0.5mm
Very Thin Quad Flat
Pack; Pb-free
Q
Notes:
1. I = Industrial (TA = –40° C to +85° C); Q = Automotive (TA = -40° C to +105° C with TJ Maximum = +125° C).
Pb- XA2C64A -7 VQ 44
G
I
Free Example:
Device
Speed Grade
Package Type
-Free
Pb
Number of Pins
Temperature Range
12
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DS553 (v1.1) May 5, 2007
Product Specification
R
XA2C64A CoolRunner-II Automotive CPLD
Device Part Marking
R
Device Type
Package
XA2Cxxx
VQG44
This line not
related to device
part number
7 I
Speed
Operating Range
Part marking for non-chip scale package
Figure 5: Sample Package with Part Marking
Package Pinout Diagrams
I/O(1)
33
I/O(2)
I/O
I/O
GND
I/O
I/O
1
2
3
4
5
6
7
8
I/O(1)
32
I/O(1)
31
I/O(3)
30
VQG44
Top View
I/O
29
I/O
28
I/O
27
V
CCIO1
I/O
TDI
TMS
TCK
V
26
25
24
23
CCIO2
9
10
11
GND
TDO
I/O
(1) - Global Output Enable
(2) - Global Clock
(3) - Global Set/Reset
Figure 6: VQG44 Package
DS553 (v1.1) May 5, 2007
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13
Product Specification
R
XA2C64A CoolRunner-II Automotive CPLD
(1)
(1)
(1)
(1)
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
I/O
NC
I/O
I/O
I/O
GND
I/O
I/O
NC
NC
I/O
NC
GND
I/O
I/O
NC
I/O
Vcc
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
V
AUX
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VQG100
Top View
GND
(2)
I/O
(2)
I/O
I/O
NC
VCCIO1
(1) - Global Output Enable
(2) - Global Clock
(3) - Global Set/Reset
Figure 12: VQ100 Package
CoolRunner-II Automotive Requirements and Recommendations
outputs, it is required that an LED anode is sourced
through a resistor externally to VCC. Consequently, this
will give the brightest solution.
Requirements
The following requirements are for all automotive applica-
tions:
5. Avoid pull-down resistors. Always use external pull-up
resistors if external termination is required. This is
because the CoolRunner-II Automotive CPLD, which
includes some I/O driving circuits beyond the input and
output buffers, may have contention with external
pull-down resistors, and, consequently, the I/O will not
switch as expected.
1. Use a monotonic, fast ramp power supply to power up
CoolRunner-II . A VCC ramp time of less than 1 ms is
required.
2. Do not float I/O pins during device operation. Floating
I/O pins can increase ICC as input buffers will draw
1-2 mA per floating input. In addition, when I/O pins are
floated, noise can propagate to the center of the CPLD.
I/O pins should be appropriately terminated with
bus-hold or pull-up. Unused I/Os can also be configured
as CGND (programmable GND).
6. Do not drive I/Os pins above the VCCIO assigned to its
I/O bank.
a. The current flow can go into VCCIO and affect a user
voltage regulator.
3. Do not drive I/O pins without VCC/VCCIO powered.
b. It can also increase undesired leakage current
associated with the device.
4. Sink current when driving LEDs. Because all Xilinx
CPLDs have N-channel pull-down transistors on
14
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DS553 (v1.1) May 5, 2007
Product Specification
R
XA2C64A CoolRunner-II Automotive CPLD
c. If done for too long, it can reduce the life of the
device.
internals with INTEST, identifying stuck pins, and
inspecting programming patterns (if not secured).
7. Do not rely on the I/O states before the CPLD
configures. During power up, the CPLD I/Os may be
affected by internal or external signals.
3. CoolRunner-II Automotive CPLDs work with any power
sequence, but it is preferable to power the VCCI
(internal VCC) before the VCCIO for the applications in
which any glitches from device I/Os are unwanted.
8. Use a voltage regulator which can provide sufficient
current during device power up. As a rule of thumb, the
regulator needs to provide at least three times the peak
current while powering up a CPLD in order to guarantee
the CPLD can configure successfully.
4. Do not disregard report file warnings. Software
identifies potential problems when compiling, so the
report file is worth inspecting to see exactly how your
design is mapped onto the logic.
9. Ensure external JTAG terminations for TMS, TCK, TDI,
TDO should comply with the IEEE 1149.1. All Xilinx
CPLDs have internal weak pull-ups on TDI, TMS, and
TCK.
5. Understand the Timing Report. This report file provides
a speed summary along with warnings. Read the timing
file (*.tim) carefully. Analyze key signal chains to
determine limits to given clock(s) based on logic
analysis.
10. Attach all CPLD VCC and GND pins in order to have
necessary power and ground supplies around the
CPLD.
6. Review Fitter Report equations. Equations can be
shown in ABEL-like format, or can also be displayed in
Verilog or VHDL formats. The Fitter Report also
includes switch settings that are very informative of
other device behaviors.
11. Decouple all VCC and VCCIO pins with capacitors of
0.01 μF and 0.1 μF closest to the pins for each
VCC/VCCIO-GND pair.
7. Let design software define pinouts if possible. Xilinx
CPLD software works best when it selects the I/O pins
and manages resources for users. It can spread signals
around and improve pin-locking. If users must define
pins, plan resources in advance.
12. Configure I/Os properly. CoolRunner-II Automotive
CPLDs have I/O banks; therefore, signals must be
assigned to appropriate banks (LVCMOS33,
LVCMOS18 …)
Recommendations
8. Perform a post-fit simulation for all speeds to identify
any possible problems (such as race conditions) that
might occur when fast-speed silicon is used instead of
slow-speed silicon.
The following recommendations are for all automotive appli-
cations.
1. Use strict synchronous design (only one clocking event)
if possible. A synchronous system is more robust than
an asynchronous one.
9. Distribute SSOs (Simultaneously Switching Outputs)
evenly around the CPLD to reduce switching noise.
10. Terminate high speed outputs to eliminate noise caused
by very fast rising/falling edges.
2. Include JTAG stakes on the PCB. JTAG stakes can be
used to test the part on the PCB. They add benefit in
reprogramming part on the PCB, inspecting chip
Automotive Warranty Disclaimer
THIS WARRANTY DOES NOT EXTEND TO ANY IMPLEMENTATION IN AN APPLICATION OR ENVIRONMENT THAT IS
NOT CONTAINED WITHIN XILINX SPECIFICATIONS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE AND ARE
NOT WARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS. FURTHER, PRODUCTS ARE NOT WARRANTED
FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF THE VEHICLE UNLESS THERE IS A FAIL-SAFE OR
REDUNDANCY FEATURE AND ALSO A WARNING SIGNAL TO THE OPERATOR OF THE VEHICLE UPON FAILURE.
USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO APPLICABLE
LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT LIABILITY.
DS553 (v1.1) May 5, 2007
www.xilinx.com
15
Product Specification
R
XA2C64A CoolRunner-II Automotive CPLD
Additional Information
Additional information is available for the following CoolRunner-II topics:
•
•
•
•
•
•
•
XAPP784: Bulletproof CPLD Design Practices
XAPP375: Timing Model
To access these and all application notes with their associ-
ated reference designs, click the following link and scroll
down the page until you find the document you want:
XAPP376: Logic Engine
CoolRunner-II Data Sheets and Application Notes
Device Packages
XAPP378: Advanced Features
XAPP382: I/O Characteristics
XAPP389: Powering CoolRunner-II
XAPP399: Assigning VREF Pins
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revision
10/31/06
05/05/07
Initial Xilinx release.
1.1
Change to VIH specification for 3.3V, 2.5V and 1.8V LVCMOS.
16
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DS553 (v1.1) May 5, 2007
Product Specification
XA2C64A-8VQG44Q CAD模型
引脚图
封装焊盘图
XA2C64A-8VQG44Q 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| XC2C64A-5VQG44C | XILINX | Flash PLD, 5ns, 64-Cell, CMOS, PQFP44, 10 X 10 MM, 0.80 MM PITCH, LEAD FREE, VQFP-44 | 完全替代 |
|
| XC2C64A-7VQG44C | XILINX | Flash PLD, 7.5ns, 64-Cell, CMOS, PQFP44, 10 X 10 MM, 0.80 MM PITCH, LEAD FREE, VQFP-44 | 完全替代 |
|
XA2C64A-8VQG44Q 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| XA2S100E-6TQ144I | XILINX | Field Programmable Gate Array, 600 CLBs, 357MHz, 2700-Cell, CMOS, PQFP144, PLASTIC, TQFP-144 | 获取价格 |
|
| XA2S100E-6TQ144Q | XILINX | Field Programmable Gate Array, 600 CLBs, 357MHz, 2700-Cell, CMOS, PQFP144, PLASTIC, TQFP-144 | 获取价格 |
|
| XA2S150E-6FT256I | XILINX | Field Programmable Gate Array, 864 CLBs, 357MHz, 3888-Cell, CMOS, PBGA256, FBGA-256 | 获取价格 |
|
| XA2S150E-6FT256Q | XILINX | Field Programmable Gate Array, 864 CLBs, 357MHz, 3888-Cell, CMOS, PBGA256, FBGA-256 | 获取价格 |
|
| XA2S200E-6FT256I | XILINX | Field Programmable Gate Array, 1176 CLBs, 357MHz, 5292-Cell, CMOS, PBGA256, FBGA-256 | 获取价格 |
|
| XA2S200E-6FT256Q | XILINX | 暂无描述 | 获取价格 |
|
| XA2S300E-6FT256I | XILINX | Field Programmable Gate Array, 1536 CLBs, 357MHz, 6912-Cell, CMOS, PBGA256, FBGA-256 | 获取价格 |
|
| XA2S300E-6FT256Q | XILINX | Field Programmable Gate Array, 1536 CLBs, 357MHz, 6912-Cell, CMOS, PBGA256, FBGA-256 | 获取价格 |
|
| XA2S50E-6TQ144I | XILINX | Field Programmable Gate Array, 384 CLBs, 357MHz, 1728-Cell, CMOS, PQFP144, PLASTIC, TQFP-144 | 获取价格 |
|
| XA2S50E-6TQ144Q | XILINX | Field Programmable Gate Array, 384 CLBs, 357MHz, 1728-Cell, CMOS, PQFP144, PLASTIC, TQFP-144 | 获取价格 |
|
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