XA3S1200E-4TQG144Q_技术文档

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XA Spartan-3E Automotive

FPGA Family Data Sheet

0

DS635 (v2.0) September 9, 2009

Product Specification

Summary

The Xilinx® Automotive (XA) Spartan®-3E family of FPGAs

is specifically designed to meet the needs of high-volume,

cost-sensitive automotive electronics applications. The

five-member family offers densities ranging from 100,000 to

1.6 million system gates, as shown in Table 1.

-

Enhanced Double Data Rate (DDR) support

DDR SDRAM support up to 266 Mb/s

•

Abundant, flexible logic resources

-

Densities up to 33,192 logic cells, including

optional shift register or distributed RAM support

Efficient wide multiplexers, wide logic

Fast look-ahead carry logic

Enhanced 18 x 18 multipliers with optional pipeline

IEEE 1149.1/1532 JTAG programming/debug port

-

Introduction

XA devices are available in both extended-temperature

Q-Grade (–40°C to +125°C T ) and I-Grade (–40°C to

J

+100°C T ) and are qualified to the industry recognized

J

•

Hierarchical SelectRAM™ memory architecture

-

AEC-Q100 standard.

Up to 648 Kbits of fast block RAM

Up to 231 Kbits of efficient distributed RAM

The XA Spartan-3E family builds on the success of the ear-

lier XA Spartan-3 family by increasing the amount of logic

per I/O, significantly reducing the cost per logic cell. New

features improve system performance and reduce the cost

of configuration. These XA Spartan-3E FPGA enhance-

ments, combined with advanced 90 nm process technology,

deliver more functionality and bandwidth per dollar than was

previously possible, setting new standards in the program-

mable logic industry.

Up to eight Digital Clock Managers (DCMs)

-

Clock skew elimination (delay locked loop)

Frequency synthesis, multiplication, division

High-resolution phase shifting

Wide frequency range (5 MHz to over 300 MHz)

•

Eight global clocks plus eight additional clocks per

each half of device, plus abundant low-skew routing

Configuration interface to industry-standard PROMs

-

Complete Xilinx ISE® and WebPACK™ software

support

MicroBlaze™ and PicoBlaze™ embedded processor

cores

Because of their exceptionally low cost, XA Spartan-3E

FPGAs are ideally suited to a wide range of automotive

applications, including infotainment, driver information, and

driver assistance modules.

Low-cost, space-saving SPI serial Flash PROM

x8 or x8/x16 parallel NOR Flash PROM

•

The XA Spartan-3E family is a superior alternative to mask

programmed ASICs and ASSPs. FPGAs avoid the high ini-

tial mask set costs and lengthy development cycles, while

also permitting design upgrades in the field with no hard-

ware replacement necessary because of its inherent pro-

grammability, an impossibility with conventional ASICs and

ASSPs with their inflexible hardware architecture.

Fully compliant 32-/64-bit 33 MHz PCI™ technology

support

Low-cost QFP and BGA packaging options

-

Common footprints support easy density migration

Refer to Spartan-3E FPGA Family: Complete Data Sheet

(DS312) for a full product description, AC and DC specifica-

tions, and package pinout descriptions. Any values shown

specifically in this XA Spartan-3E Automotive FPGA Family

data sheet override those shown in DS312.

Features

•

Very low-cost, high-performance logic solution for

high-volume automotive applications

•

Proven advanced 90-nanometer process technology

Multi-voltage, multi-standard SelectIO™ interface pins

For information regarding reliability qualification, refer to

RPT081 (Xilinx Spartan-3E Family Automotive Qualification

Report) and RPT012 (Spartan-3/3E UMC-12A 90 nm Qual-

ification Report).

-

Up to 376 I/O pins or 156 differential signal pairs

LVCMOS, LVTTL, HSTL, and SSTL single-ended

signal standards

-

3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling

622+ Mb/s data transfer rate per I/O

True LVDS, RSDS, mini-LVDS, differential

HSTL/SSTL differential I/O

countries. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.

DS635 (v2.0) September 9, 2009

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Product Specification

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Key Feature Differences from Commercial XC Devices

•

AEC-Q100 device qualification and full production part

approval process (PPAP) documentation support

available in both extended temperature I- and

Q-Grades

Spartan-3E FPGA product line.

XA Spartan-3E devices are available in Step 1 only.

JTAG configuration frequency reduced from 30 MHz to

25 MHz.

•

Guaranteed to meet full electrical specification over the

•

Platform Flash is not supported within the XA family.

XA Spartan-3E devices are available in Pb-free

packaging only.

MultiBoot is not supported in XA versions of this

product.

T = –40°C to +125°C temperature range (Q-Grade)

J

•

XA Spartan-3E devices are available in the -4 speed

grade only.

PCI-66 is not supported in the XA Spartan-3E FPGA

product line.

•

The XA Spartan-3E device must be power cycled prior

to reconfiguration.

The readback feature is not supported in the XA

Table 1: Summary of XA Spartan-3E FPGA Attributes

CLB Array

(One CLB = Four Slices)

Equivalent

Logic

Block

RAM

bits⁽¹⁾

Maximum

Maximum Differential

System

Gates

Total

Distributed

RAM bits⁽¹⁾

Dedicated

Multipliers DCMs User I/O

Device

Cells

Rows Columns CLBs

Slices

I/O Pairs

XA3S100E

XA3S250E

XA3S500E

XA3S1200E

100K

250K

2,160

5,508

22

34

16

26

240

612

960

15K

38K

72K

4

2

4

108

172

40

68

2,448

216K

12

500K

10,476

19,512

33,192

46

60

76

34

46

58

1,164

2,168

3,688

4,656

8,672

73K

136K

231K

360K

504K

648K

20

28

36

4

8

190

304

376

77

1200K

124

156

XA3S1600E 1600K

14,752

Notes:

1. By convention, one Kb is equivalent to 1,024 bits.

Architectural Overview

The XA Spartan-3E family architecture consists of five fun-

damental programmable functional elements:

•

Digital Clock Manager (DCM) Blocks provide

self-calibrating, fully digital solutions for distributing,

delaying, multiplying, dividing, and phase-shifting clock

signals.

•

Configurable Logic Blocks (CLBs) contain flexible

Look-Up Tables (LUTs) that implement logic plus

storage elements used as flip-flops or latches. CLBs

perform a wide variety of logical functions as well as

store data.

These elements are organized as shown in Figure 1. A ring

of IOBs surrounds a regular array of CLBs. Each device has

two columns of block RAM except for the XA3S100E, which

has one column. Each RAM column consists of several

18-Kbit RAM blocks. Each block RAM is associated with a

dedicated multiplier. The DCMs are positioned in the center

with two at the top and two at the bottom of the device. The

XA3S100E has only one DCM at the top and bottom, while

the XA3S1200E and XA3S1600E add two DCMs in the mid-

dle of the left and right sides.

•

Input/Output Blocks (IOBs) control the flow of data

between the I/O pins and the internal logic of the

device. Each IOB supports bidirectional data flow plus

3-state operation. Supports a variety of signal

standards, including four high-performance differential

standards. Double Data-Rate (DDR) registers are

included.

•

Block RAM provides data storage in the form of

18-Kbit dual-port blocks.

Multiplier Blocks accept two 18-bit binary numbers as

inputs and calculate the product.

The XA Spartan-3E family features a rich network of traces

that interconnect all five functional elements, transmitting

signals among them. Each functional element has an asso-

ciated switch matrix that permits multiple connections to the

routing.

DS635 (v2.0) September 9, 2009

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Product Specification

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Notes:

1. The XA3S1200E and XA3S1600E have two additional DCMs on both the left and right sides as

indicated by the dashed lines. The XA3S100E has only one DCM at the top and one at the bottom.

Figure 1: XA Spartan-3E Family Architecture

Configuration

I/O Capabilities

XA Spartan-3E FPGAs are programmed by loading config-

uration data into robust, reprogrammable, static CMOS con-

figuration latches (CCLs) that collectively control all

functional elements and routing resources. The FPGA’s

configuration data is stored externally in a PROM or some

other non-volatile medium, either on or off the board. After

applying power, the configuration data is written to the

FPGA using any of five different modes:

The XA Spartan-3E FPGA SelectIO interface supports

many popular single-ended and differential standards.

Table 2 shows the number of user I/Os as well as the num-

ber of differential I/O pairs available for each device/pack-

age combination.

XA Spartan-3E FPGAs support the following single-ended

standards:

•

3.3V low-voltage TTL (LVTTL)

•

Serial Peripheral Interface (SPI) from an

industry-standard SPI serial Flash

Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V,

1.5V, or 1.2V

•

Byte Peripheral Interface (BPI) Up or Down from an

industry-standard x8 or x8/x16 parallel NOR Flash

•

3V PCI at 33 MHz

HSTL I and III at 1.8V, commonly used in memory

applications

•

Slave Serial, typically downloaded from a processor

Slave Parallel, typically downloaded from a processor

Boundary Scan (JTAG), typically downloaded from a

processor or system tester.

•

SSTL I at 1.8V and 2.5V, commonly used for memory

applications

DS635 (v2.0) September 9, 2009

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Product Specification

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XA Spartan-3E FPGAs support the following differential

standards:

•

Differential HSTL (1.8V, Types I and III)

Differential SSTL (2.5V and 1.8V, Type I)

2.5V LVPECL inputs

•

LVDS

Bus LVDS

mini-LVDS

RSDS

Table 2: Available User I/Os and Differential (Diff) I/O Pairs

Package

VQG100

16 x 16

CPG132

8 x 8

TQG144

22 x 22

PQG208

28 x 28

FTG256

17 x 17

FGG400

21 x 21

FGG484

23 x 23

Size (mm)

Device

User

Diff

User

Diff

User

Diff

User

Diff

User

Diff

User

Diff

User

Diff

66

(7)

30

(2)

83

(11)

35

(2)

108

(28)

40

(4)

XA3S100E

XA3S250E

XA3S500E

XA3S1200E

-

66

(7)

30

(2)

92

(7)

41

(2)

108

(28)

40

(4)

158

(32)

65

(5)

172

(40)

68

(8)

-

92

(7)

41

(2)

158

(32)

65

(5)

190

(41)

77

(8)

-

190

(40)

77

(8)

304

(72)

124

(20)

-

304

(72)

124

(20)

376

(82)

156

(21)

XA3S1600E

Notes:

-

1. All XA Spartan-3E devices provided in the same package are pin-compatible as further described in Module 4: Pinout Descriptions of

DS312.

2. The number shown in bold indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the number

of input-only pins.

DS635 (v2.0) September 9, 2009

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Product Specification

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Package Marking

Figure 2 provides a top marking example for XA Spartan-3E

FPGAs in the quad-flat packages. Figure 3 shows the top

marking for XA Spartan-3E FPGAs in BGA packages

except the 132-ball chip-scale package (CPG132). The

markings for the BGA packages are nearly identical to those

for the quad-flat packages, except that the marking is

rotated with respect to the ball A1 indicator. Figure 4 shows

the top marking for XA Spartan-3E FPGAs in the CPG132

package.

Note: No marking is shown for stepping.

Mask Revision Code

Fabrication Code

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Process Technology

SPARTAN

Device Type

XA3S250E^TM

Date Code

Lot Code

Package

PQG208AGQ0525

D1234567A

Speed Grade

4I

Temperature Range

Pin P1

DS635-1_02_082807

Figure 2: XA Spartan-3E FPGA QFP Package Marking Example

Mask Revision Code

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BGA Ball A1

Fabrication Code

Process Code

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SPARTAN

Device Type

XA3S250E^TM

FTG256AGQ0525

D1234567A

4I

Date Code

Lot Code

Package

FTG256AGQ0525

Speed Grade

Temperature Range

DS635_03_082807

Figure 3: XA Spartan-3E FPGA BGA Package Marking Example

Ball A1

Device Type

3S250E

F1234567-0525

PHILIPPINES

Lot Code

Date Code

Temperature Range

Package

C6 = CPG132

C6AGQ

4I

Speed Grade

Process Code

Mask Revision Code

Fabrication Code

DS635_04_082807

Figure 4: XA Spartan-3E FPGA CPG132 Package Marking Example

DS635 (v2.0) September 9, 2009

Product Specification

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Ordering Information

XA Spartan-3E FPGAs are available in Pb-free packaging

options for all device/package combinations. All devices are

in Pb-free packages only, with a “G” character to the order-

ing code. All devices are available in either I-Grade or

Q-Grade temperature ranges. Only the -4 speed grade is

available for the XA Spartan-3E family. See Table 2 for valid

device/package combinations.

Pb-Free Packaging

Example: XA3S250E -4 FT G 256

I

Device Type

Temperature Range:

I = I-Grade (T_J= –40^oC to 100^oC)

Q = Q-Grade (T_J= –40^oC to 125^oC)

Number of Pins

Speed Grade

Package Type

Pb-free

DS635_06_121608

Device

Speed Grade

-4 Only

Package Type / Number of Pins

Temperature Range (T_J)

I-Grade (–40°C to 100°C)

Q-Grade (–40°C to 125°C)

XA3S100E

XA3S250E

XA3S500E

XA3S1200E

XA3S1600E

VQG100 100-pin Very Thin Quad Flat Pack (VQFP)

CPG132 132-ball Chip-Scale Package (CSP)

TQG144 144-pin Thin Quad Flat Pack (TQFP)

PQG208 208-pin Plastic Quad Flat Pack (PQFP)

I

Q

FTG256

256-ball Fine-Pitch Thin Ball Grid Array (FTBGA)

FGG400 400-ball Fine-Pitch Ball Grid Array (FBGA)

FGG484 484-ball Fine-Pitch Ball Grid Array (FBGA)

DS635 (v2.0) September 9, 2009

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Product Specification

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Power Supply Specifications

Table 3: Supply Voltage Thresholds for Power-On Reset

Symbol

Description

Min

0.4

0.8

0.4

Max

1.0

Units

V

Threshold for the V

supply

V

CCINTT

CCINT

V

2.0

1.0

CCAUXT

CCAUX

V

Bank 2 supply

CCO

CCO2T

Notes:

1.

V

, V

, and V

supplies to the FPGA can be applied in any order. However, the FPGA’s configuration source (SPI Flash, parallel

CCINT CCAUX

CCO

NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration source.

2. To ensure successful power-on, V

no dips at any point.

, V

Bank 2, and V

supplies must rise through their respective threshold-voltage ranges with

CCINT CCO

CCAUX

Table 4: Supply Voltage Ramp Rate

Symbol

Description

Min

0.2

Max

50

Units

ms

V

Ramp rate from GND to valid V

supply level

CCINTR

CCINT

V

50

ms

CCAUXR

CCAUX

V

Bank 2 supply level

CCO

50

ms

CCO2R

Notes:

1.

V

, V

, and V

supplies to the FPGA can be applied in any order. However, the FPGA’s configuration source (SPI Flash, parallel

CCINT CCAUX

CCO

NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration source.

2. To ensure successful power-on, V

no dips at any point.

, V

Bank 2, and V

supplies must rise through their respective threshold-voltage ranges with

CCINT CCO

CCAUX

Table 5: Supply Voltage Levels Necessary for Preserving RAM Contents

Symbol Description

level required to retain RAM data

Min

1.0

2.0

Units

V

DRINT

CCINT

V

level required to retain RAM data

DRAUX

CCAUX

Notes:

1. RAM contents include configuration data.

DS635 (v2.0) September 9, 2009

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DC Specifications

Table 6: General Recommended Operating Conditions

Symbol

Description

Min

–40

Nominal

Max

100

Units

T

Junction temperature

I-Grade

25

° C

J

Q-Grade

–40

25

125

° C

V

Internal supply voltage

Output driver supply voltage

Auxiliary supply voltage

1.140

1.100

2.375

-

1.200

1.260

3.465

2.625

10

V

CCINT

(1)

V

-

V

CCO

2.500

CCAUX

(2)

ΔV

Voltage variance on V

when using a DCM

-

mV/ms

V

CCAUX

(3,4,5,6)

CCAUX

V

Input voltage extremes to avoid I/O, Input-only, and

turning on I/O protection diodes Dual-Purpose pins

–0.5

–

V

+ 0.5

CCO

IN

(3)

(4)

Dedicated pins

–0.5

–

V

+ 0.5

V

CCAUX

(7)

T

Input signal transition time

500

ns

IN

Notes:

1. This V

range spans the lowest and highest operating voltages for all supported I/O standards. Table 9 lists the recommended V

CCO

range specific to each of the single-ended I/O standards, and Table 11 lists that specific to the differential standards.

2. Only during DCM operation is it recommended that the rate of change of V not exceed 10 mV/ms.

CCAUX

3. Each of the User I/O and Dual-Purpose pins is associated with one of the four banks’ V

rails. Meeting the V limit ensures that the

IN

CCO

internal diode junctions that exist between these pins and their associated V

Ratings in DS312).

and GND rails do not turn on. See Absolute Maximum

CCO

4. All Dedicated pins (PROG_B, DONE, TCK, TDI, TDO, and TMS) draw power from the V

rail (2.5V). Meeting the V max limit ensures

IN

CCAUX

that the internal diode junctions that exist between each of these pins and the V

and GND rails do not turn on.

CCAUX

5. Input voltages outside the recommended range is permissible provided that the I input clamp diode rating is met and no more than 100 pins

IK

exceed the range simultaneously. See Absolute Maximum Ratings in DS312).

6. See XAPP459, "Eliminating I/O Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins."

7. Measured between 10% and 90% V

. Follow Signal Integrity recommendations.

CCO

General DC Characteristics for I/O Pins

Table 7: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins

Symbol

Description

Test Conditions

Min

Typ

Max Units

I

Leakage current at User I/O,

Input-only, Dual-Purpose, and

Dedicated pins

Driver is in a high-impedance state,

–10

–

+10

μA

L

V

= 0V or V

max, sample-tested

IN

CCO

(2)

I

Current through pull-up resistor at

User I/O, Dual-Purpose, Input-only,

and Dedicated pins

V

= 0V, V

= 3.3V

= 2.5V

= 1.8V

= 1.5V

= 1.2V

–0.36

–0.22

–0.10

–0.06

–0.04

2.4

–

–1.24

–0.80

–0.42

–0.27

–0.22

10.8

mA

kΩ

RPU

IN

CCO

(2)

PU

R

Equivalent pull-up resistor value at

User I/O, Dual-Purpose, Input-only,

V

= 0V, V

= 3.0V to 3.465V

= 2.3V to 2.7V

CCO

IN

CCO

V

= 0V, V

2.7

11.8

IN

and Dedicated pins (based on I

per Note 2)

RPU

= 1.7V to 1.9V

=1.4V to 1.6V

CCO

4.3

20.2

CCO

V

= 0V, V

5.0

25.9

IN

V

= 0V, V

= 1.14V to 1.26V

CCO

5.5

32.0

IN

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Table 7: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins (Continued)

Symbol

Description

Test Conditions

= V

Min

Typ

Max Units

(2)

I

Current through pull-down resistor at

User I/O, Dual-Purpose, Input-only,

and Dedicated pins

V

0.10

–

0.75

mA

RPD

IN

CCO

(2)

PD

R

Equivalent pull-down resistor value at

User I/O, Dual-Purpose, Input-only,

V

= V

= 3.0V to 3.45V

= 2.3V to 2.7V

= 1.7V to 1.9V

= 1.4V to 1.6V

4.0

3.0

2.3

1.8

1.5

–10

–

34.5

27.0

19.0

16.0

12.6

+10

10

kΩ

μA

pF

Ω

IN

CCO

V

= V

IN

CCO

and Dedicated pins (based on I

per Note 2)

RPD

V

–

V

= V

= 1.14V to 1.26V

CCO

–

IN

I

V

current per pin

All V

levels

–

REF

CCO

C

R

Input capacitance

-

–

IN

Resistance of optional differential

termination circuit within a differential

I/O pair. Not available on Input-only

pairs.

V

Min ≤V_ICM≤V

Max

–

120

–

DT

OCM

V

Min ≤V ≤V Max

OD

ID

OD

V

= 2.5V

CCO

Notes:

1. The numbers in this table are based on the conditions set forth in Table 6.

2. This parameter is based on characterization. The pull-up resistance R = V

/ I

. The pull-down resistance R = V / I

.

PU

CCO RPU

PD

IN RPD

Table 8: Quiescent Supply Current Characteristics

Q-Grade

Symbol

Description

Quiescent V

Device

XA3S100E

I-Grade Maximum

Maximum

Units

mA

I

36

104

145

324

457

1.5

2.5

58

158

300

500

750

2.0

3.0

4.0

CCINTQ

CCINT

supply current

XA3S250E

XA3S500E

XA3S1200E

XA3S1600E

XA3S100E

XA3S250E

XA3S500E

XA3S1200E

XA3S1600E

I

Quiescent V

CCO

supply current

CCOQ

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Table 8: Quiescent Supply Current Characteristics (Continued)

Q-Grade

Symbol

Description

Quiescent V

Device

XA3S100E

I-Grade Maximum

Maximum

Units

mA

I

13

26

34

59

86

22

43

CCAUXQ

CCAUX

supply current

XA3S250E

XA3S500E

XA3S1200E

XA3S1600E

mA

63

mA

100

150

mA

Notes:

1. The numbers in this table are based on the conditions set forth in Table 6.

2. Quiescent supply current is measured with all I/O drivers in a high-impedance state and with all pull-up/pull-down resistors at the I/O pads

disabled. Typical values are characterized using typical devices at room temperature (T of 25°C at V = 1.2 V, V = 3.3V, and

J

CCINT

CCO

V

= 2.5V). The maximum limits are tested for each device at the respective maximum specified junction temperature and at maximum

CCAUX

voltage limits with V

= 1.26V, V

= 3.465V, and V

= 2.625V. The FPGA is programmed with a “blank” configuration data file

CCINT

CCO

CCAUX

(i.e., a design with no functional elements instantiated). For conditions other than those described above, (e.g., a design including functional

elements), measured quiescent current levels may be different than the values in the table. For more accurate estimates for a specific

design, use the Xilinx XPower tools.

3. There are two recommended ways to estimate the total power consumption (quiescent plus dynamic) for a specific design: a) The

Spartan-3E XPower Estimator provides quick, approximate, typical estimates, and does not require a netlist of the design. b) XPower

Analyzer uses a netlist as input to provide maximum estimates as well as more accurate typical estimates.

4. The maximum numbers in this table indicate the minimum current each power rail requires in order for the FPGA to power-on successfully.

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Single-Ended I/O Standards

Table 9: Recommended Operating Conditions for User I/Os Using Single-Ended Standards

(2)

V

for Drivers

V

IH

CCO

REF

IL

IOSTANDARD

Attribute

Min (V) Nom (V) Max (V) Min (V)

Nom (V)

Max (V)

0.8

Min (V)

2.0

LVTTL

3.0

2.3

1.65

1.4

1.1

3.0

1.7

2.3

3.3

2.5

1.8

1.5

1.2

3.3

1.8

2.5

3.465

2.7

(4)

LVCMOS33

LVCMOS25

LVCMOS18

LVCMOS15

LVCMOS12

PCI33_3

0.8

2.0

(4,5)

0.7

1.7

V

is not used for

REF

1.95

1.6

0.4

0.8

these I/O standards

0.4

0.8

1.3

0.4

0.7

3.465

1.9

0.3 * V

0.5 * V

CCO

HSTL_I_18

0.8

-

0.9

1.1

-

V

- 0.1

V

+ 0.1

REF

HSTL_III_18

SSTL18_I

SSTL2_I

1.9

0.833

1.15

0.900

1.25

0.969

1.35

V

- 0.125

V

+ 0.125

REF

2.7

V

Notes:

1. Descriptions of the symbols used in this table are as follows:

V

– the supply voltage for output drivers

– the reference voltage for setting the input switching threshold

– the input voltage that indicates a Low logic level

– the input voltage that indicates a High logic level

CCO

REF

IL

IH

2. The V

rails supply only output drivers, not input circuits.

CCO

3. For device operation, the maximum signal voltage (V max) may be as high as V max. See Table 72 in DS312.

IH

IN

4. There is approximately 100 mV of hysteresis on inputs using LVCMOS33 and LVCMOS25 I/O standards.

5. All Dedicated pins (PROG_B, DONE, TCK, TDI, TDO, and TMS) use the LVCMOS25 standard and draw power from the V

rail (2.5V).

CCAUX

The Dual-Purpose configuration pins use the LVCMOS standard before the User mode. When using these pins as part of a standard 2.5V

configuration interface, apply 2.5V to the V lines of Banks 0, 1, and 2 at power-on as well as throughout configuration.

CCO

6. For information on PCI IP solutions, see www.xilinx.com/pci.

DS635 (v2.0) September 9, 2009

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Product Specification

11

R

Table 10: DC Characteristics of User I/Os Using

Single-Ended Standards (Continued)

Table 10: DC Characteristics of User I/Os Using

Single-Ended Standards

Test

Conditions

Logic Level

Characteristics

Test

Conditions

Logic Level

Characteristics

V_OL

Max (V)

V_OH

Min (V)

V_OL

Max (V)

V_OH

Min (V)

IOSTANDARD

Attribute

I_OL

(mA) (mA)

I_OH

IOSTANDARD

Attribute

I_OL

(mA) (mA)

I_OH

LVCMOS12⁽³⁾

PCI33_3⁽⁴⁾

HSTL_I_18

HSTL_III_18

SSTL18_I

2

–2

0.4

V_CCO- 0.4

90% V_CCO

V_CCO- 0.4

V_TT+ 0.475

LVTTL⁽³⁾

2

4

6

8

2

4

–2

–4

0.4

2.4

1.5

8

–0.5 10% V_CCO

–8

0.4

6

–6

24

6.7

8.1

8

–8

V_TT– 0.475

–6.7

12

16

2

12

16

2

–12

–16

–2

SSTL2_I

–8.1 V_TT– 0.61

V_TT+ 0.61

LVCMOS33⁽³⁾

0.4

V_CCO– 0.4

Notes:

1. The numbers in this table are based on the conditions set forth in

Table 6 and Table 9.

4

–4

2. Descriptions of the symbols used in this table are as follows:

6

–6

I_OL– the output current condition under which V_OLis tested

I_OH– the output current condition under which V_OHis tested

V_OL– the output voltage that indicates a Low logic level

V_OH– the output voltage that indicates a High logic level

V_CCO– the supply voltage for output drivers

8

–8

12

16

2

12

16

2

–12

–16

–2

V_TT– the voltage applied to a resistor termination

LVCMOS25⁽³⁾

0.4

V_CCO– 0.4

3. For the LVCMOS and LVTTL standards: the same V and V

OL

OH

limits apply for both the Fast and Slow slew attributes.

4

–4

4. Tested according to the relevant PCI specifications. For

information on PCI IP solutions, see www.xilinx.com/pci.

6

–6

8

–8

12

2

12

2

–12

–2

LVCMOS18⁽³⁾

LVCMOS15⁽³⁾

0.4

V_CCO– 0.4

4

–4

6

–6

8

–8

2

–2

V_CCO– 0.4

4

–4

6

–6

DS635 (v2.0) September 9, 2009

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Product Specification

12

R

Differential I/O Standards

Table 11: Recommended Operating Conditions for User I/Os Using Differential Signal Standards

V_CCOfor Drivers⁽¹⁾

V_ID

V_ICM

IOSTANDARD

Attribute

Min

(mV)

Nom

(mV)

Max

(mV)

Min (V)

Nom (V)

2.50

Max (V)

Min (V)

0.30

0.5

Nom (V)

Max (V)

2.20

2.2

LVDS_25

2.375

2.625

100

200

100

350

600

1.25

BLVDS_25

2.50

350

600

1.25

MINI_LVDS_25

LVPECL_25⁽²⁾

RSDS_25

2.50

-

600

-

Inputs Only

2.50

800

1000

1.2

2.0

2.375

1.7

2.625

1.9

200

-

0.3

1.20

1.4

DIFF_HSTL_I_18

DIFF_HSTL_III_18

DIFF_SSTL18_I

DIFF_SSTL2_I

1.8

-

0.8

-

1.1

1.7

1.8

1.9

0.8

1.1

1.7

1.8

1.9

0.7

1.1

2.3

2.5

2.7

1.0

1.5

Notes:

1. The V

rails supply only differential output drivers, not input circuits.

CCO

2.

V

inputs are not used for any of the differential I/O standards.

REF

Table 12: DC Characteristics of User I/Os Using Differential Signal Standards

V_OD

ΔV_OD

Min Max

(mV) (mV)

V_OCM

ΔV_OCM

V_OH

V_OL

IOSTANDARD

Attribute

Min

(mV)

Typ

(mV)

Max

(mV)

Min

(V)

Typ

(V)

Max

(V)

Min

Max

Min

(V)

Max

(V)

(mV)

LVDS_25

250

300

100

–

350

–

450

600

400

–

1.125

–

1.20

–

1.375

–

BLVDS_25

–

1.0

1.1

–

1.4

–

MINI_LVDS_25

RSDS_25

50

–

50

–

DIFF_HSTL_I_18

DIFF_HSTL_III_18

DIFF_SSTL18_I

DIFF_SSTL2_I

–

V_CCO– 0.4

0.4

–

V_TT+ 0.475 V_TT– 0.475

V_TT+ 0.61 V_TT– 0.61

–

Notes:

1. The numbers in this table are based on the conditions set forth in Table 6, and Table 11.

2. Output voltage measurements for all differential standards are made with a termination resistor (R ) of 100Ωacross the N and P pins of the

T

differential signal pair. The exception is for BLVDS, shown in Figure 5 below.

3. At any given time, no more than two of the following differential output standards may be assigned to an I/O bank: LVDS_25, RSDS_25,

MINI_LVDS_25

DS635 (v2.0) September 9, 2009

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Product Specification

13

R

1/4th of Bourns

Part Number

CAT16-LV4F12

1/4th of Bourns

Part Number

CAT16-PT4F4

VCCO = 2.5V

Z

0

= 50Ω

165Ω

140Ω

100Ω

Z

165Ω

DS635_05_082807

Figure 5: External Termination Resistors for BLVDS Transmitter and BLVDS Receiver

Switching Characteristics

I/O Timing

Table 13: Pin-to-Pin Clock-to-Output Times for the IOB Output Path

-4 Speed

Grade

Symbol

Description

Conditions

Device

Max

Units

Clock-to-Output Times

(2)

XA3S100E

XA3S250E

XA3S500E

XA3S1200E

XA3S1600E

XA3S100E

XA3S250E

XA3S500E

XA3S1200E

XA3S1600E

T

When reading from the Output

Flip-Flop (OFF), the time from

the active transition on the

Global Clock pin to data

appearing at the Output pin. The

DCM is used.

LVCMOS25 , 12mA

2.79

3.45

3.46

3.45

5.92

5.43

5.51

5.94

6.05

ns

ICKOFDCM

output drive, Fast slew rate,

(3)

with DCM

(2)

T

When reading from OFF, the

LVCMOS25 , 12mA

ICKOF

time from the active transition on output drive, Fast slew rate,

the Global Clock pin to data

appearing at the Output pin. The

DCM is not used.

without DCM

Notes:

1. The numbers in this table are tested using the methodology presented in Table 19 and are based on the operating conditions set forth in

Table 6 and Table 9.

2. This clock-to-output time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or a

standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. If the former is true, add the appropriate

Input adjustment from Table 17. If the latter is true, add the appropriate Output adjustment from Table 18.

3. DCM output jitter is included in all measurements.

4. For minimums, use the values reported by the Xilinx timing analyzer.

DS635 (v2.0) September 9, 2009

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Product Specification

14

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Table 14: Pin-to-Pin Setup and Hold Times for the IOB Input Path (System Synchronous)

-4 Speed

Grade

IFD_

DELAY_

Symbol

Setup Times

T_PSDCM

Description

Conditions

VALUE=

Device

Min

Units

When writing to the Input Flip-Flop LVCMOS25⁽²⁾

,

0

XA3S100E

XA3S250E

XA3S500E

XA3S1200E

XA3S1600E

XA3S100E

XA3S250E

XA3S500E

XA3S1200E

XA3S1600E

2.98

2.59

2.58

2.59

3.58

3.91

4.02

5.52

4.46

ns

(IFF), the time from the setup of

data at the Input pin to the active

transition at a Global Clock pin.

The DCM is used. No Input Delay

is programmed.

IFD_DELAY_VALUE = 0,

with DCM⁽⁴⁾

When writing to IFF, the time from LVCMOS25⁽²⁾

the setup of data at the Input pin to IFD_DELAY_VALUE =

an active transition at the Global

Clock pin. The DCM is not used.

The Input Delay is programmed.

,

2

3

2

5

4

T_PSFD

default software setting

Hold Times

When writing to IFF, the time from LVCMOS25⁽³⁾

,

0

XA3S100E

XA3S250E

XA3S500E

XA3S1200E

XA3S1600E

XA3S100E

XA3S250E

XA3S500E

XA3S1200E

XA3S1600E

–0.52

0.14

ns

T_PHDCM

the active transition at the Global

Clock pin to the point when data

must be held at the Input pin. The

DCM is used. No Input Delay is

programmed.

IFD_DELAY_VALUE = 0,

with DCM⁽⁴⁾

0.14

0.15

0.14

When writing to IFF, the time from LVCMOS25⁽³⁾

,

2

3

2

5

4

–0.24

–0.32

–0.49

–0.63

–0.39

T_PHFD

the active transition at the Global

Clock pin to the point when data

must be held at the Input pin. The

DCM is not used. The Input Delay

is programmed.

IFD_DELAY_VALUE =

default software setting

Notes:

1. The numbers in this table are tested using the methodology presented in Table 19 and are based on the operating conditions set forth in

Table 6 and Table 9.

2. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data

Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from Table 17. If this is true of the data Input, add the

appropriate Input adjustment from the same table.

3. This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data

Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from Table 17. If this is true of the data Input, subtract

the appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clock’s

active edge.

4. DCM output jitter is included in all measurements.

DS635 (v2.0) September 9, 2009

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Product Specification

15

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Table 15: Setup and Hold Times for the IOB Input Path

-4

Speed

Grade

IFD_

DELAY_

VALUE

Symbol

Description

Conditions

Device

Min

Units

Setup Times

T_IOPICK

Time from the setup of data at the Input

LVCMOS25⁽²⁾

,

0

All

2.12

ns

pin to the active transition at the ICLK input IFD_DELAY_VALUE = 0

of the Input Flip-Flop (IFF). No Input Delay

is programmed.

T_IOPICKD

Time from the setup of data at the Input

pin to the active transition at the IFF’s ICLK IFD_DELAY_VALUE =

input. The Input Delay is programmed. default software setting

LVCMOS25⁽²⁾

,

2

3

2

5

4

XA3S100E

XA3S250E

XA3S500E

XA3S1200E

XA3S1600E

6.49

6.85

7.01

8.67

7.69

ns

Hold Times

T_IOICKP

Time from the active transition at the IFF’s LVCMOS25⁽²⁾

,

0

All

–0.76

ns

ICLK input to the point where data must be IFD_DELAY_VALUE = 0

held at the Input pin. No Input Delay is

programmed.

T_IOICKPD

Time from the active transition at the IFF’s LVCMOS25⁽²⁾

ICLK input to the point where data must be IFD_DELAY_VALUE =

,

2

3

2

5

4

XA3S100E

XA3S250E

XA3S500E

XA3S1200E

XA3S1600E

–3.93

–3.51

–3.74

–4.30

–4.14

ns

held at the Input pin. The Input Delay is

programmed.

default software setting

Set/Reset Pulse Width

T_{RPW_IOB}Minimum pulse width to SR control input

on IOB

All

1.80

ns

Notes:

1. The numbers in this table are tested using the methodology presented in Table 19 and are based on the operating conditions set forth in

Table 6 and Table 9.

2. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the

appropriate Input adjustment from Table 17.

3. These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract

the appropriate Input adjustment from Table 17. When the hold time is negative, it is possible to change the data before the clock’s active

edge.

DS635 (v2.0) September 9, 2009

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Product Specification

16

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Table 16: Propagation Times for the IOB Input Path

-4Speed

Grade

IFD_

DELAY_

VALUE

Symbol

Description

Conditions

Device

Max

Units

Propagation Times

(2)

T

The time it takes for data to

LVCMOS25

,

0

All

2.25

ns

IOPLI

travel from the Input pin through IFD_DELAY_VALUE = 0

the IFF latch to the I output with

no input delay programmed

(2)

2

3

2

5

4

XA3S100E

XA3S250E

XA3S500E

XA3S1200E

XA3S1600E

5.97

6.33

6.49

8.15

7.16

ns

T

The time it takes for data to

LVCMOS25 ,

IOPLID

travel from the Input pin through IFD_DELAY_VALUE =

the IFF latch to the I output with default software setting

the input delay programmed

Notes:

1. The numbers in this table are tested using the methodology presented in Table 19 and are based on the operating conditions set forth in

Table 6 and Table 9.

2. This propagation time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. When this is

true, add the appropriate Input adjustment from Table 17.

Table 17: Input Timing Adjustments by IOSTANDARD

Convert Input Time from

LVCMOS25 to the Following

Signal Standard

Add the

Adjustment Below

Convert Input Time from

LVCMOS25 to the Following

Signal Standard

Add the

Adjustment Below

(IOSTANDARD)

-4 Speed Grade

Units

(IOSTANDARD)

-4 Speed Grade

Units

Single-Ended Standards

LVTTL

Differential Standards

LVDS_25

0.43

0

ns

0.49

0.39

0.49

0.27

0.49

0.30

0.32

ns

LVCMOS33

LVCMOS25

LVCMOS18

LVCMOS15

LVCMOS12

PCI33_3

BLVDS_25

MINI_LVDS_25

LVPECL_25

0.98

0.63

0.27

0.42

0.12

0.17

0.30

0.15

RSDS_25

DIFF_HSTL_I_18

DIFF_HSTL_III_18

DIFF_SSTL18_I

DIFF_SSTL2_I

HSTL_I_18

HSTL_III_18

SSTL18_I

Notes:

1. The numbers in this table are tested using the methodology

presented in Table 19 and are based on the operating conditions

set forth in Table 6, Table 9, and Table 11.

SSTL2_I

2. These adjustments are used to convert input path times originally

specified for the LVCMOS25 standard to times that correspond to

other signal standards.

DS635 (v2.0) September 9, 2009

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Product Specification

17

R

Table 18: Output Timing Adjustments for IOB (Continued)

Table 18: Output Timing Adjustments for IOB

Add the

Adjustment

Below

Convert Output Time from

LVCMOS25 with 12mA Drive and

Fast Slew Rate to the Following

Signal Standard (IOSTANDARD)

Adjustment

Below

Convert Output Time from

LVCMOS25 with 12mA Drive and

Fast Slew Rate to the Following

Signal Standard (IOSTANDARD)

-4 Speed

Grade

-4 Speed

Grade

Units

ns

Units

LVCMOS18

Slow

2 mA

4 mA

6 mA

8 mA

2 mA

4 mA

6 mA

8 mA

2 mA

4 mA

6 mA

2 mA

4 mA

6 mA

2 mA

5.24

3.21

2.49

1.90

4.15

2.13

1.14

0.75

4.68

3.97

3.11

3.38

2.70

1.53

6.63

4.44

0.34

0.55

0.46

0.25

–0.20

Single-Ended Standards

LVTTL

Slow

Fast

Slow

Fast

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

2 mA

4 mA

6 mA

8 mA

12 mA

2 mA

4 mA

6 mA

8 mA

12 mA

5.41

2.41

1.90

0.67

0.70

0.43

5.00

1.96

1.45

0.34

0.30

5.29

1.89

1.04

0.69

0.42

0.43

4.87

1.52

0.39

0.34

0.30

4.21

2.26

1.52

1.08

0.68

3.67

1.72

0.46

0.21

0

ns

Fast

LVCMOS15

LVCMOS12

Slow

Fast

LVCMOS33

Slow

Fast

HSTL_I_18

HSTL_III_18

PCI33_3

SSTL18_I

SSTL2_I

Differential Standards

LVDS_25

–0.55

0.04

ns

BLVDS_25

MINI_LVDS_25

LVPECL_25

–0.56

Input Only

–0.48

0.42

LVCMOS25

Slow

Fast

RSDS_25

DIFF_HSTL_I_18

DIFF_HSTL_III_18

DIFF_SSTL18_I

DIFF_SSTL2_I

0.55

0.40

0.44

Notes:

1. The numbers in this table are tested using the methodology

presented in Table 19 and are based on the operating conditions

set forth in Table 6, Table 9, and Table 11.

2. These adjustments are used to convert output- and

three-state-path times originally specified for the LVCMOS25

standard with 12 mA drive and Fast slew rate to times that

correspond to other signal standards. Do not adjust times that

measure when outputs go into a high-impedance state.

DS635 (v2.0) September 9, 2009

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Product Specification

18

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Table 19: Test Methods for Timing Measurement at I/Os

Inputs and

Outputs

Inputs

Outputs

Signal Standard

(IOSTANDARD)

V_REF(V)

V_L(V)

V_H(V)

R_T(Ω)

V_T(V)

V_M(V)

Single-Ended

LVTTL

-

0

3.3

1M

25

0

1.4

1.65

1.25

0.9

LVCMOS33

LVCMOS25

LVCMOS18

LVCMOS15

LVCMOS12

PCI33_3

0

2.5

0

1.8

0

1.5

0

0.75

0.6

1.2

0

Rising

Falling

Note 3

0

0.94

2.03

V_REF

25

3.3

0.9

1.8

0.9

1.25

HSTL_I_18

HSTL_III_18

SSTL18_I

SSTL2_I

0.9

1.1

V

_REF– 0.5

V_REF+ 0.5

V_REF+ 0.75

50

V_REF– 0.5

V_REF– 0.75

50

0.9

50

1.25

50

Differential

LVDS_25

-

V_ICM– 0.125

V_ICM– 0.3

V_ICM– 0.1

V_REF– 0.5

V_ICM+ 0.125

V_ICM+ 0.3

V_ICM+ 0.1

V_REF+ 0.5

50

1M

50

1M

50

1.2

0

V_ICM

BLVDS_25

MINI_LVDS_25

LVPECL_25

1.2

0

RSDS_25

1.2

0.9

1.8

0.9

1.25

DIFF_HSTL_I_18

DIFF_HSTL_III_18

DIFF_SSTL18_I

DIFF_SSTL2_I

Notes:

1. Descriptions of the relevant symbols are as follows:

V

– The reference voltage for setting the input switching threshold

– The common mode input voltage

– Voltage of measurement point on signal transition

REF

ICM

M

V – Low-level test voltage at Input pin

L

V

– High-level test voltage at Input pin

H

R – Effective termination resistance, which takes on a value of 1MΩ when no parallel termination is required

T

V – Termination voltage

T

2. The load capacitance (C ) at the Output pin is 0 pF for all signal standards.

L

3. According to the PCI specification.

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Product Specification

19

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Configurable Logic Block Timing

Table 20: CLB (SLICEM) Timing

-4 Speed Grade

Symbol

Description

Min

Max

Units

Clock-to-Output Times

T

When reading from the FFX (FFY) Flip-Flop, the time from the active

transition at the CLK input to data appearing at the XQ (YQ) output

CKO

-

0.60

ns

Setup Times

T

Time from the setup of data at the F or G input to the active transition

at the CLK input of the CLB

AS

0.52

1.81

-

ns

T

Time from the setup of data at the BX or BY input to the active

transition at the CLK input of the CLB

DICK

Hold Times

T

Time from the active transition at the CLK input to the point where

data is last held at the F or G input

AH

0

-

ns

T

Time from the active transition at the CLK input to the point where

data is last held at the BX or BY input

CKDI

Clock Timing

T

F

The High pulse width of the CLB’s CLK signal

The Low pulse width of the CLK signal

Toggle frequency (for export control)

0.80

0

-

ns

CH

CL

572

MHz

TOG

Propagation Times

T

The time it takes for data to travel from the CLB’s F (G) input to the X

(Y) output

ILO

-

0.76

-

ns

Set/Reset Pulse Width

T

The minimum allowable pulse width, High or Low, to the CLB’s SR

input

RPW_CLB

1.80

Notes:

1. The numbers in this table are based on the operating conditions set forth in Table 6.

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Table 21: CLB Distributed RAM Switching Characteristics

-4

Symbol

Description

Min

Max

Units

Clock-to-Output Times

T

Time from the active edge at the CLK input to data appearing on the

distributed RAM output

SHCKO

-

2.35

ns

Setup Times

T

Setup time of data at the BX or BY input before the active transition at the

CLK input of the distributed RAM

DS

0.46

0.52

0.40

-

ns

T

Setup time of the F/G address inputs before the active transition at the CLK

input of the distributed RAM

AS

T

Setup time of the write enable input before the active transition at the CLK

input of the distributed RAM

WS

Hold Times

T

Hold time of the BX, BY data inputs after the active transition at the CLK

input of the distributed RAM

DH

0.15

0

-

ns

T

Hold time of the F/G address inputs or the write enable input after the active

transition at the CLK input of the distributed RAM

AH, WH

Clock Pulse Width

, T Minimum High or Low pulse width at CLK input

T

1.01

-

ns

WPH WPL

Table 22: CLB Shift Register Switching Characteristics

-4

Symbol

Description

Min

Max

Units

Clock-to-Output Times

T

Time from the active edge at the CLK input to data appearing on the shift

register output

REG

-

4.16

ns

Setup Times

T

Setup time of data at the BX or BY input before the active transition at the

CLK input of the shift register

SRLDS

0.46

-

ns

Hold Times

T

Hold time of the BX or BY data input after the active transition at the CLK

input of the shift register

SRLDH

0.16

1.01

-

ns

Clock Pulse Width

, T Minimum High or Low pulse width at CLK input

T

WPH WPL

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Clock Buffer/Multiplexer Switching Characteristics

Table 23: Clock Distribution Switching Characteristics

Maximum

Description

Symbol

-4 Speed Grade

Units

Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to O-output

delay

T

1.46

ns

GIO

Global clock multiplexer (BUFGMUX) select S-input setup to I0 and I1

inputs. Same as BUFGCE enable CE-input

T

0.63

311

ns

GSI

Frequency of signals distributed on global buffers (all sides)

F

MHz

BUFG

18 x 18 Embedded Multiplier Timing

Table 24: 18 x 18 Embedded Multiplier Timing

-4 Speed Grade

Symbol

Description

Min

Max

Units

Combinatorial Delay

T

Combinatorial multiplier propagation delay from the A and B inputs to

the P outputs, assuming 18-bit inputs and a 36-bit product (AREG,

BREG, and PREG registers unused)

MULT

(1)

-

4.88

ns

Clock-to-Output Times

T

Clock-to-output delay from the active transition of the CLK input to valid

data appearing on the P outputs when using the PREG register

MSCKP_P

-

1.10

ns

(2)

T

Clock-to-output delay from the active transition of the CLK input to valid

data appearing on the P outputs when using either the AREG or BREG

MSCKP_A

MSCKP_B

4.97

(3)

register

Setup Times

T

Data setup time at the A or B input before the active transition at the

CLK when using only the PREG output register (AREG, BREG

registers unused)

MSDCK_P

3.98

-

ns

(2)

T

Data setup time at the A input before the active transition at the CLK

when using the AREG input register

MSDCK_A

MSDCK_B

0.23

0.39

-

ns

(3)

Data setup time at the B input before the active transition at the CLK

(3)

when using the BREG input register

Hold Times

T

Data hold time at the A or B input before the active transition at the CLK

when using only the PREG output register (AREG, BREG registers

unused)

MSCKD_P

-0.97

(2)

T

Data hold time at the A input before the active transition at the CLK

when using the AREG input register

MSCKD_A

MSCKD_B

0.04

0.05

(3)

Data hold time at the B input before the active transition at the CLK

(3)

when using the BREG input register

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Table 24: 18 x 18 Embedded Multiplier Timing (Continued)

-4 Speed Grade

Symbol

Description

Min

Max

Units

Clock Frequency

F

Internal operating frequency for a two-stage 18x18 multiplier using the

AREG and BREG input registers and the PREG output register

MULT

0

240

MHz

(1)

Notes:

1. Combinatorial delay is less and pipelined performance is higher when multiplying input data with less than 18 bits.

2. The PREG register is typically used in both single-stage and two-stage pipelined multiplier implementations.

3. Input registers AREG or BREG are typically used when inferring a two-stage multiplier.

Block RAM Timing

Table 25: Block RAM Timing

-4 Speed Grade

Symbol

Description

Min

Max

Units

Clock-to-Output Times

T

When reading from block RAM, the delay from the active transition

at the CLK input to data appearing at the DOUT output

BCKO

-

2.82

ns

Setup Times

T

Setup time for the ADDR inputs before the active transition at the

CLK input of the block RAM

BACK

BDCK

BECK

BWCK

0.38

0.23

0.77

1.26

-

ns

Setup time for data at the DIN inputs before the active transition at

the CLK input of the block RAM

Setup time for the EN input before the active transition at the CLK

input of the block RAM

Setup time for the WE input before the active transition at the CLK

input of the block RAM

Hold Times

T

Hold time on the ADDR inputs after the active transition at the CLK

input

BCKA

0.14

0.13

-

ns

T

Hold time on the DIN inputs after the active transition at the CLK

input

BCKD

T

Hold time on the EN input after the active transition at the CLK input

Hold time on the WE input after the active transition at the CLK input

0

-

ns

BCKE

BCKW

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Table 25: Block RAM Timing (Continued)

-4 Speed Grade

Symbol

Description

Min

Max

Units

Clock Timing

T

High pulse width of the CLK signal

Low pulse width of the CLK signal

1.59

-

ns

BPWH

BPWL

Clock Frequency

F

Block RAM clock frequency. RAM read output value written back

into RAM, for shift registers and circular buffers. Write-only or

read-only performance is faster.

BRAM

0

230

MHz

Notes:

1. The numbers in this table are based on the operating conditions set forth in Table 6.

Digital Clock Manager Timing

For specification purposes, the DCM consists of three key

components: the Delay-Locked Loop (DLL), the Digital Fre-

quency Synthesizer (DFS), and the Phase Shifter (PS).

Aspects of DLL operation play a role in all DCM applica-

tions. All such applications inevitably use the CLKIN and the

CLKFB inputs connected to either the CLK0 or the CLK2X

feedback, respectively. Thus, specifications in the DLL

tables (Table 26 and Table 27) apply to any application that

only employs the DLL component. When the DFS and/or

the PS components are used together with the DLL, then

the specifications listed in the DFS and PS tables (Table 28

through Table 31) supersede any corresponding ones in the

DLL tables. DLL specifications that do not change with the

addition of DFS or PS functions are presented in Table 26

and Table 27.

Period jitter and cycle-cycle jitter are two of many different

ways of specifying clock jitter. Both specifications describe

statistical variation from a mean value.

Period jitter is the worst-case deviation from the ideal clock

period over a collection of millions of samples. In a histo-

gram of period jitter, the mean value is the clock period.

Cycle-cycle jitter is the worst-case difference in clock period

between adjacent clock cycles in the collection of clock peri-

ods sampled. In a histogram of cycle-cycle jitter, the mean

value is zero.

Spread Spectrum

DCMs accept typical spread spectrum clocks as long as

they meet the input requirements. The DLL will track the fre-

quency changes created by the spread spectrum clock to

drive the global clocks to the FPGA logic. See XAPP469,

Spread-Spectrum Clocking Reception for Displays

for details.

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Delay-Locked Loop

Table 26: Recommended Operating Conditions for the DLL

-4 Speed Grade

Symbol

Description

Min

Max

Units

Input Frequency Ranges

F_CLKIN

CLKIN_FREQ_DLL

Frequency of the CLKIN clock input

5⁽²⁾

240⁽³⁾

MHz

Input Pulse Requirements

CLKIN_PULSE

CLKIN pulse width as a

percentage of the CLKIN

period

F_CLKIN< 150 MHz

F_CLKIN> 150 MHz

40%

45%

60%

55%

-

Input Clock Jitter Tolerance and Delay Path Variation⁽⁴⁾

CLKIN_CYC_JITT_DLL_LF

CLKIN_CYC_JITT_DLL_HF

CLKIN_PER_JITT_DLL

Cycle-to-cycle jitter at the

CLKIN input

F_CLKIN< 150 MHz

F_CLKIN> 150 MHz

-

300

150

1

ps

ns

Period jitter at the CLKIN input

CLKFB_DELAY_VAR_EXT

Allowable variation of off-chip feedback delay from the DCM output to

the CLKFB input

1

Notes:

1. DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.

2. The DFS, when operating independently of the DLL, supports lower FCLKIN frequencies. See Table 28.

3. To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming

clock frequency by two as it enters the DCM. The CLK2X output reproduces the clock frequency provided on the CLKIN input.

4. CLKIN input jitter beyond these limits might cause the DCM to lose lock.

Table 27: Switching Characteristics for the DLL

-4 Speed Grade

Symbol

Description

Min

Max

Units

Output Frequency Ranges

CLKOUT_FREQ_CLK0

CLKOUT_FREQ_CLK90

CLKOUT_FREQ_2X

Frequency for the CLK0 and CLK180 outputs

Frequency for the CLK90 and CLK270 outputs

Frequency for the CLK2X and CLK2X180 outputs

Frequency for the CLKDV output

5

240

200

311

160

MHz

10

CLKOUT_FREQ_DV

0.3125

Output Clock Jitter^(2,3,4)

CLKOUT_PER_JITT_0

CLKOUT_PER_JITT_90

CLKOUT_PER_JITT_180

CLKOUT_PER_JITT_270

CLKOUT_PER_JITT_2X

Period jitter at the CLK0 output

-

100

150

ps

Period jitter at the CLK90 output

Period jitter at the CLK180 output

Period jitter at the CLK270 output

Period jitter at the CLK2X and CLK2X180 outputs

[1% of

CLKIN period

+ 150]

CLKOUT_PER_JITT_DV1

CLKOUT_PER_JITT_DV2

Period jitter at the CLKDV output when performing integer

division

-

150

ps

Period jitter at the CLKDV output when performing

non-integer division

[1% of

CLKIN period

+ 200]

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Table 27: Switching Characteristics for the DLL (Continued)

-4 Speed Grade

Min Max

Symbol

Duty Cycle⁽⁴⁾

Description

Units

CLKOUT_DUTY_CYCLE_DLL Duty cycle variation for the CLK0, CLK90, CLK180,

CLK270, CLK2X, CLK2X180, and CLKDV outputs,

including the BUFGMUX and clock tree duty-cycle

distortion

-

[1% of

CLKIN period

+ 400]

ps

Phase Alignment⁽⁴⁾

CLKIN_CLKFB_PHASE

CLKOUT_PHASE_DLL

Phase offset between the CLKIN and CLKFB inputs

-

200

ps

Phase offset between DLL outputs

CLK0 to CLK2X

(not CLK2X180)

[1% of

CLKIN period

+ 100]

All others

-

[1% of

CLKIN period

+ 200]

ps

Lock Time

LOCK_DLL⁽³⁾

When using the DLL alone: The time 5 MHz < F_CLKIN

<

-

5

ms

from deassertion at the DCM’s Reset

input to the rising transition at its

LOCKED output. When the DCM is

locked, the CLKIN and CLKFB

signals are in phase

15 MHz

F

_CLKIN> 15 MHz

600

μs

Delay Lines

DCM_DELAY_STEP

Finest delay resolution

20

40

ps

Notes:

1. The numbers in this table are based on the operating conditions set forth in Table 6 and Table 26.

2. Indicates the maximum amount of output jitter that the DCM adds to the jitter on the CLKIN input.

3. For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.

4. Some jitter and duty-cycle specifications include 1% of input clock period or 0.01 UI. Example: The data sheet specifies a maximum

jitter of “ [1% of CLKIN period + 150]”. Assume the CLKIN frequency is 100 MHz. The equivalent CLKIN period is 10 ns and 1% of

10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is [100 ps + 150 ps] = 250ps.

Digital Frequency Synthesizer

Table 28: Recommended Operating Conditions for the DFS

-4 Speed Grade

Symbol

Description

Min

Max

Units

(2)

Input Frequency Ranges

333⁽⁴⁾

F_CLKIN

CLKIN_FREQ_FX

Frequency for the CLKIN input

0.200

MHz

(3)

Input Clock Jitter Tolerance

CLKIN_CYC_JITT_FX_LF

CLKIN_CYC_JITT_FX_HF

Cycle-to-cycle jitter at the CLKIN

input, based on CLKFX output

frequency

F

_CLKFX< 150 MHz

-

300

150

ps

F_CLKFX> 150 MHz

CLKIN_PER_JITT_FX

Period jitter at the CLKIN input

-

1

ns

Notes:

1. DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) are used.

2. If both DFS and DLL outputs are used on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in Table 26.

3. CLKIN input jitter beyond these limits may cause the DCM to lose lock.

4. To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming

clock frequency by two as it enters the DCM.

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Table 29: Switching Characteristics for the DFS

-4 Speed Grade

Symbol

Description

Device

All

Min

Max

Units

Output Frequency Ranges

CLKOUT_FREQ_FX

Frequency for the CLKFX and CLKFX180 outputs

5

311

MHz

Output Clock Jitter^(2,3)

CLKOUT_PER_JITT_FX

Period jitter at the CLKFX and CLKFX180

outputs

All

Typ

Max

[1% of

CLKIN <20 MHz

See Note 4

ps

[1% of

CLKIN > 20 MHz

CLKFX CLKFX

period

+ 100]

period

+ 200]

Duty Cycle^(5,6)

CLKOUT_DUTY_CYCLE_FX

Duty cycle precision for the CLKFX and CLKFX180 outputs,

including the BUFGMUX and clock tree duty-cycle distortion

All

-

[1% of

CLKFX

period

+ 400]

ps

Phase Alignment⁽⁶⁾

CLKOUT_PHASE_FX

Phase offset between the DFS CLKFX output and the DLL CLK0

output when both the DFS and DLL are used

All

-

200

ps

CLKOUT_PHASE_FX180

Phase offset between the DFS CLKFX180 output and the DLL

CLK0 output when both the DFS and DLL are used

[1% of

CLKFX

period

+ 300]

Lock Time

LOCK_FX⁽²⁾

The time from deassertion at the DCM’s

Reset input to the rising transition at its

LOCKED output. The DFS asserts LOCKED

when the CLKFX and CLKFX180 signals

are valid. If using both the DLL and the DFS,

use the longer locking time.

5 MHz < F_CLKIN

15 MHz

<

All

-

5

ms

F_CLKIN> 15 MHz

450

μs

Notes:

1. The numbers in this table are based on the operating conditions set forth in Table 6 and Table 28.

2. For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.

3. Maximum output jitter is characterized within a reasonable noise environment (150 ps input period jitter, 40 SSOs and 25% CLB switching). Output

jitter strongly depends on the environment, including the number of SSOs, the output drive strength, CLB utilization, CLB switching activities, switching

frequency, power supply and PCB design. The actual maximum output jitter depends on the system application.

4. Use the Spartan-3A Jitter Calculator (www.xilinx.com/support/documentation/data_sheets/s3a_jitter_calc.zip) to estimate DFS output jitter. Use the

Clocking Wizard to determine jitter for a specific design.

5. The CLKFX and CLKFX180 outputs always have an approximate 50% duty cycle.

6. Some duty-cycle and alignment specifications include 1% of the CLKFX output period or 0.01 UI. Example: The data sheet specifies a maximum jitter

of “ [1% of CLKFX period + 300]”. Assume the CLKFX output frequency is 100 MHz. The equivalent CLKFX period is 10 ns and 1% of 10 ns is 0.1 ns

or 100 ps. According to the data sheet, the maximum jitter is [100 ps + 300 ps] = 400 ps.

Phase Shifter

Table 30: Recommended Operating Conditions for the PS in Variable Phase Mode

-4 Speed Grade

Symbol

Description

Min

Max

Units

Operating Frequency Ranges

PSCLK_FREQ

(F

Frequency for the PSCLK input

1

167

MHz

)

PSCLK

Input Pulse Requirements

PSCLK_PULSE PSCLK pulse width as a percentage of the PSCLK period

40%

60%

-

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Table 31: Switching Characteristics for the PS in Variable Phase Mode

Symbol

Phase Shifting Range

MAX_STEPS⁽²⁾

Description

Units

Maximum allowed number of DCM_DELAY_STEP

steps for a given CLKIN clock period, where T = CLKIN

clock period in ns. If using

CLKIN_DIVIDE_BY_2 = TRUE, double the clock

effective clock period.

CLKIN < 60 MHz

CLKIN > 60 MHz

[INTEGER(10 • steps

(T_CLKIN– 3 ns))]

[INTEGER(15 • steps

(T_CLKIN– 3 ns))]

FINE_SHIFT_RANGE_MIN

Minimum guaranteed delay for variable phase shifting

[MAX_STEPS •

DCM_DELAY_STEP_MIN]

ns

FINE_SHIFT_RANGE_MAX Maximum guaranteed delay for variable phase shifting

[MAX_STEPS •

DCM_DELAY_STEP_MAX]

Notes:

1. The numbers in this table are based on the operating conditions set forth in Table 6 and Table 30.

2. The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM is has no initial fixed phase shifting, i.e., the PHASE_SHIFT

attribute is set to 0.

3. The DCM_DELAY_STEP values are provided at the bottom of Table 27.

Miscellaneous DCM Timing

Table 32: Miscellaneous DCM Timing

Symbol

Description

Min

Max

Units

(1)

DCM_RST_PW_MIN

Minimum duration of a RST pulse width

3

-

CLKIN

cycles

(2)

DCM_RST_PW_MAX

Maximum duration of a RST pulse width

N/A

seconds

minutes

(3)

DCM_CONFIG_LAG_TIME

Maximum duration from V

applied to FPGA

CCINT

configuration successfully completed (DONE pin goes

High) and clocks applied to DCM DLL

Notes:

1. This limit only applies to applications that use the DCM DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV).

The DCM DFS outputs (CLKFX, CLKFX180) are unaffected.

2. This specification is equivalent to the Virtex-4 DCM_RESET specification. This specification does not apply for Spartan-3E FPGAs.

3. This specification is equivalent to the Virtex-4 TCONFIG specification. This specification does not apply for Spartan-3E FPGAs.

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Configuration and JTAG Timing

Table 33: Power-On Timing and the Beginning of Configuration

-4 Speed Grade

Symbol

(2)

Description

Device

Min

Max

5

Units

ms

μs

T_POR

The time from the application of V_CCINT, V_CCAUX, and V_CCOXA3S100E

Bank 2 supply voltage ramps (whichever occurs last) to the

rising transition of the INIT_B pin

XA3S500E

-

XA3S250E

-

5

-

5

XA3S1200E

XA3S1600E

-

5

-

7

T_PROG

The width of the low-going pulse on the PROG_B pin

All

0.5

-

(2)

T_PL

The time from the rising edge of the PROG_B pin to the

rising transition on the INIT_B pin

XA3S100E

XA3S250E

XA3S500E

XA3S1200E

XA3S1600E

All

-

0.5

1

ms

ns

-

2

-

2

T_INIT

Minimum Low pulse width on INIT_B output

250

0.5

-

(3)

T_ICCK

The time from the rising edge of the INIT_B pin to the

generation of the configuration clock signal at the CCLK

output pin

All

4.0

μs

Notes:

1. The numbers in this table are based on the operating conditions set forth in Table 6. This means power must be applied to all V

, V

,

CCINT CCO

and V

lines.

CCAUX

2. Power-on reset and the clearing of configuration memory occurs during this period.

3. This specification applies only to the Master Serial, SPI, BPI-Up, and BPI-Down modes.

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Configuration Clock (CCLK) Characteristics

Table 34: Master Mode CCLK Output Period by ConfigRate Option Setting

ConfigRate

Setting

Temperature

Range

Symbol

Description

Minimum

Maximum

Units

CCLK clock period by

ConfigRate setting

1

I-Grade

Q-Grade

T

(power-on value

and default value)

485

1,250

ns

CCLK1

I-Grade

Q-Grade

T

3

242

121

625

313

157

78.2

39.1

ns

CCLK3

I-Grade

Q-Grade

6

CCLK6

I-Grade

Q-Grade

12

25

50

60.6

30.3

15.1

CCLK12

CCLK25

CCLK50

I-Grade

Q-Grade

I-Grade

Q-Grade

Notes:

1. Set the ConfigRate option value when generating a configuration bitstream. See Bitstream Generator (BitGen) Options in DS312, Module 2.

Table 35: Master Mode CCLK Output Frequency by ConfigRate Option Setting

ConfigRate

Setting

Temperature

Range

Symbol

Description

Minimum

Maximum

Units

Equivalent CCLK clock

frequency by ConfigRate

setting

1

I-Grade

Q-Grade

F

(power-on value

and default value)

0.8

2.1

MHz

CCLK1

I-Grade

Q-Grade

F

3

1.6

3.2

4.2

8.3

MHz

CCLK3

I-Grade

Q-Grade

6

CCLK6

I-Grade

Q-Grade

12

25

50

6.4

16.5

33.0

66.0

CCLK12

CCLK25

CCLK50

I-Grade

Q-Grade

12.8

25.6

I-Grade

Q-Grade

Table 36: Master Mode CCLK Output Minimum Low and High Time

ConfigRate Setting

Symbol

Description

Units

1

3

6

12

25

50

7.3

T

MastermodeCCLKminimum

Low and High time

I-Grade

Q-Grade

MCCL,

MCCH

235

117

58

29.3

14.5

ns

T

Table 37: Slave Mode CCLK Input Low and High Time

Symbol Description

Min

Max

Units

T

SCCL,

SCCH

CCLK Low and High time

5

∞

ns

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Master Serial and Slave Serial Mode Timing

Table 38: Timing for the Master Serial and Slave Serial Configuration Modes

-4 Speed Grade

Slave/

Symbol

Description

Master

Min

Max

Units

Clock-to-Output Times

T

The time from the falling transition on the CCLK pin to data

appearing at the DOUT pin

Both

1.5

10.0

ns

CCO

Setup Times

T

The time from the setup of data at the DIN pin to the active edge of

the CCLK pin

11.0

0

-

ns

DCC

Hold Times

T

The time from the active edge of the CCLK pin to the point when

data is last held at the DIN pin

CCD

Clock Timing

T

F

High pulse width at the CCLK input pin

Master

Slave

Master

Slave

See Table 36

See Table 37

See Table 36

See Table 37

CCH

Low pulse width at the CCLK input pin

CCL

(2)

Frequency of the clock signal at

the CCLK input pin

No bitstream compression

With bitstream compression

0

66

MHz

CCSER

20

Notes:

1. The numbers in this table are based on the operating conditions set forth in Table 6.

2. For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz.

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Slave Parallel Mode Timing

Table 39: Timing for the Slave Parallel Configuration Mode

-4 Speed Grade

Symbol

Description

Min

Max

Units

Clock-to-Output Times

T

The time from the rising transition on the CCLK pin to a signal transition at the

BUSY pin

-

12.0

ns

SMCKBY

Setup Times

T

The time from the setup of data at the D0-D7 pins to the active edge the CCLK

11.0

-

ns

SMDCC

T

Setup time on the CSI_B pin before the active edge of the CCLK pin

Setup time on the RDWR_B pin before active edge of the CCLK pin

10.0

23.0

-

ns

SMCSCC

(2)

SMCCW

Hold Times

T

The time from the active edge of the CCLK pin to the point when data is last

held at the D0-D7 pins

1.0

0

-

ns

SMCCD

SMCCCS

SMWCC

The time from the active edge of the CCLK pin to the point when a logic level

is last held at the CSO_B pin

The time from the active edge of the CCLK pin to the point when a logic level

is last held at the RDWR_B pin

0

Clock Timing

T

F

The High pulse width at the CCLK input pin

5

0

-

ns

CCH

The Low pulse width at the CCLK input pin

-

ns

CCL

(2)

Frequency of the clock

signal at the CCLK input

No bitstream

compression

Not using the BUSY pin

Using the BUSY pin

50

66

20

MHz

CCPAR

With bitstream compression

Notes:

1. The numbers in this table are based on the operating conditions set forth in Table 6.

2. In the Slave Parallel mode, it is necessary to use the BUSY pin when the CCLK frequency exceeds this maximum specification.

3. Some Xilinx documents refer to Parallel modes as “SelectMAP” modes.

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Serial Peripheral Interface Configuration Timing

Table 40: Timing for SPI Configuration Mode

Symbol

Description

Minimum

Maximum

(see Table 34)

-

Units

T

Initial CCLK clock period

CCLK1

CCLKn

MINIT

CCLK clock period after FPGA loads ConfigRate setting

Setup time on VS[2:0] and M[2:0] mode pins before the rising

edge of INIT_B

50

0

ns

T

Hold time on VS[2:0] and M[2:0]mode pins after the rising edge of

INIT_B

-

INITM

T

MOSI output valid after CCLK edge

See Table 38

CCO

DCC

CCD

Setup time on DIN data input before CCLK edge

Hold time on DIN data input after CCLK edge

Table 41: Configuration Timing Requirements for Attached SPI Serial Flash

Symbol

Description

SPI serial Flash PROM chip-select time

SPI serial Flash PROM data input setup time

Requirement

Units

ns

T

T_CCS≤ T_MCCL1– T_CCO

T_DSU≤ T_MCCL1– T_CCO

CCS

DSU

T

ns

T

SPI serial Flash PROM data input hold time

ns

DH

V

T_DH≤ T_MCCH1

T

SPI serial Flash PROM data clock-to-output time

T_V≤ T_MCCLn– T_DCC

f or f

Maximum SPI serial Flash PROM clock frequency (also depends

on specific read command used)

MHz

C

R

1

------------------------------

f_C≥

T_CCLKn(min)

Notes:

1. These requirements are for successful FPGA configuration in SPI mode, where the FPGA provides the CCLK frequency. The post

configuration timing can be different to support the specific needs of the application loaded into the FPGA and the resulting clock source.

2. Subtract additional printed circuit board routing delay as required by the application.

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Byte Peripheral Interface Configuration Timing

Table 42: Timing for BPI Configuration Mode

Symbol

Description

Minimum Maximum

(see Table 34)

Units

T

Initial CCLK clock period

CCLK1

CCLKn

MINIT

T

CCLK clock period after FPGA loads ConfigRate setting

(see Table 34)

Setup time on CSI_B, RDWR_B, and M[2:0] mode pins before the rising

edge of INIT_B

50

0

-

ns

T

Hold time on CSI_B, RDWR_B, and M[2:0] mode pins after the rising

edge of INIT_B

-

INITM

BPI-UP:

(M[2:0]=<0:1:0>)

Minimum period of initial A[23:0] address cycle;

LDC[2:0] and HDC are asserted and valid

5

2

5

2

T

CCLK1

cycles

INITADDR

BPI-DN:

(M[2:0]=<0:1:1>)

T

Address A[23:0] outputs valid after CCLK falling edge

See Table 38

CCO

DCC

CCD

Setup time on D[7:0] data inputs before CCLK rising edge

Hold time on D[7:0] data inputs after CCLK rising edge

Table 43: Configuration Timing Requirements for Attached Parallel NOR Flash

Symbol

Description

Requirement

Units

T

Parallel NOR Flash PROM chip-select

time

CE

T_CE≤ T_INITADDR

T_OE≤ T_INITADDR

T_ACC≤ 0.5T_CCLKn(min)– T_CCO– T_DCC– PCB

ns

(t

)

ELQV

T

Parallel NOR Flash PROM

output-enable time

OE

ns

(t

)

GLQV

T

Parallel NOR Flash PROM read access

time

ACC

(t

AVQV

T

(t

BYTE

For x8/x16 PROMs only: BYTE# to

output valid time

T_BYTE≤ T_INITADDR

ns

(3)

FLQV,

t

)

FHQV

Notes:

1. These requirements are for successful FPGA configuration in BPI mode, where the FPGA provides the CCLK frequency. The post

configuration timing can be different to support the specific needs of the application loaded into the FPGA and the resulting clock source.

2. Subtract additional printed circuit board routing delay as required by the application.

3. The initial BYTE# timing can be extended using an external, appropriately sized pull-down resistor on the FPGA’s LDC2 pin. The resistor

value also depends on whether the FPGA’s HSWAP pin is High or Low.

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IEEE 1149.1/1553 JTAG Test Access Port Timing

Table 44: Timing for the JTAG Test Access Port

-4 Speed Grade

Symbol

Description

Min

Max

Units

Clock-to-Output Times

T

The time from the falling transition on the TCK pin

to data appearing at the TDO pin

1.0

11.0

ns

TCKTDO

Setup Times

T

The time from the setup of data at the TDI pin to

the rising transition at the TCK pin

7.0

-

ns

TDITCK

T

The time from the setup of a logic level at the TMS

pin to the rising transition at the TCK pin

TMSTCK

Hold Times

T

The time from the rising transition at the TCK pin

to the point when data is last held at the TDI pin

0

-

ns

TCKTDI

T

The time from the rising transition at the TCK pin

to the point when a logic level is last held at the

TMS pin

TCKTMS

Clock Timing

T

F

The High pulse width at the TCK pin

The Low pulse width at the TCK pin

Frequency of the TCK signal

5

-

ns

CCH

CCL

TCK

25

MHz

Notes:

1. The numbers in this table are based on the operating conditions set forth in Table 6.

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Revision History

The following table shows the revision history for this document.

Date

Version

1.0

Revision

08/31/07

01/20/09

Initial Xilinx release.

• Updated "Key Feature Differences from Commercial XC Devices."

• Updated T requirement in Table 43.

1.1

ACC

• Updated description of T

and T

in Table 42.

DCC

CCD

• Removed Table 45: MultiBoot Trigger Timing.

09/09/09

2.0

• Added package sizes to Table 2, page 4.

• Removed Genealogy Viewer Link from "Package Marking," page 5.

• Updated data and notes for Table 6, page 8.

• Updated test conditions for R and maximum value for C in Table 7, page 8.

PU

IN

• Updated notes for Table 8, page 9.

• Updated Max V

for LVTTL and LVCMOS33, removed PCIX data, updated V Max for

CCO

IL

LVCMOS18, LVCMOS15, and LVCMOS12, updated V Min for LVCMOS12, and added

IH

note 6 in Table 9, page 11.

• Removed PCIX data, revised note 2, and added note 4 in Table 10, page 12.

• Updated figure description of Figure 5, page 14.

• Added note 4 to Table 13, page 14.

• Removed PC166_3 and PCIX adjustment values from Table 17, page 17.

• Deleted Table 18 (duplicate of Table 17, page 17). Subsequent tables renumbered.

• Removed PCIX data Table 18, page 18.

• Removed PCIX data and removed V

values for DIFF_HSTL_I_18,

DIFF_HSTL_III_18, DIFF_SSTL18_I, and DIFF_SSTL2_I from Table 19, page 19.

REF

• Updated T minimum setup time in Table 20, page 20.

DICK

• Updated notes, references to notes, and revised the maximum clock-to-output times for

Table 24, page 22.

T

MSCKP_P

• Added "Spread Spectrum," page 24.

• Updated note 3 in Table 26, page 25.

• Added note 4 Table 28, page 26.

• Updated notes, references to notes, and CLKOUT_PER_JITT_FX data in Table 29,

page 27.

• Updated MAX_STEPS data in Table 31, page 28.

• Updated ConfigRate Setting for T

to indicate 1 is the default value in Table 34,

CCLK1

page 30.

• Updated ConfigRate Setting for F

to indicate 1 is the default value in Table 35,

CCLK1

page 30.

Notice of Disclaimer

THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND

CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED

WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE

SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.

PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE

PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES

THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO

APPLICABLE LAWS AND REGULATIONS.

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Product Specification

36

R

Automotive Applications Disclaimer

XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING

FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A

VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN

THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III)

USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY

USE OF XILINX PRODUCTS IN SUCH APPLICATIONS.

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Product Specification

37


型号：	XA3S1200E-4TQG144Q
厂家：	XILINX, INC
描述：	Field Programmable Gate Array, 2168 CLBs, 1200000 Gates, 572MHz, CMOS, PQFP144, 22 X 22 MM, LEAD FREE, TQFP-144 时钟栅可编程逻辑
文件：	总37页 (文件大小：723K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

XA3S1200E-4TQG144Q [XILINX]

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