XA3S50-4VQG100Q [XILINX]
Field Programmable Gate Array, 192 CLBs, 50000 Gates, 125MHz, 1728-Cell, PQFP100, LEAD FREE, VQFP-100;型号: | XA3S50-4VQG100Q |
厂家: | XILINX, INC |
描述: | Field Programmable Gate Array, 192 CLBs, 50000 Gates, 125MHz, 1728-Cell, PQFP100, LEAD FREE, VQFP-100 时钟 栅 可编程逻辑 |
文件: | 总8页 (文件大小:204K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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XA Spartan-3 Automotive FPGA Family:
Introduction and Ordering Information
0
0
DS314 (v1.3) June 18, 2009
Product Specification
Summary
The Xilinx® Automotive (XA) Spartan®-3 family of Field-Programmable Gate Arrays meets the needs of high-volume,
cost-sensitive automotive electronic applications. The five-member family offers densities ranging from 50,000 to 1.5 million
system gates, as shown in Table 1.
Introduction
Features
•
AEC-Q100 device qualification and full PPAP
documentation support available in both extended
temperature Q-grade and I-grade
XA devices are available in both extended-temperature
Q-grade (–40°C to +125°C TJ) and I-grade (–40°C to
+100°C TJ) and are qualified to the industry-recognized
AEC-Q100 standard.
•
Guaranteed to meet full electrical specification over the
TJ = –40°C to +125°C temperature range
The XA Spartan-3 family builds on the success of the earlier
XA Spartan-IIE family by increasing the amount of logic
resources, the capacity of internal RAM, the total number of
I/Os, and the overall level of performance as well as by
improving clock management functions. These Spartan-3
enhancements, combined with advanced process
technology, deliver more functionality and bandwidth per
dollar than was previously possible, setting new standards
in the programmable logic industry.
•
•
Revolutionary 90-nanometer process technology
Low cost, high-performance logic solution for
high-volume, automotive applications
♦
Three power rails: for core (1.2V), I/Os (1.2V to
3.3V), and auxiliary purposes (2.5V)
•
SelectIO™ interface signaling
♦
♦
♦
♦
♦
♦
♦
Up to 487 I/O pins
Because of their exceptionally low cost, Spartan-3 FPGAs
are ideally suited to a wide range of advanced automotive
electronics modules and systems ranging from the latest
driver assistance and infotainment systems to instrument
clusters and gateways.
622 Mb/s data transfer rate per I/O
Eighteen single-ended signal standards
Eight differential signal standards including LVDS
Termination by Digitally Controlled Impedance
Signal swing ranging from 1.14V to 3.45V
Double Data Rate (DDR) support
The Spartan-3 family is a flexible alternative to ASICs,
ASSPs, and microcontrollers. FPGAs avoid the high initial
NREs, the lengthy development cycles, and problems with
obsolescence. Also, FPGA programmability permits design
upgrades in the field with no hardware replacement
necessary.
•
Logic resources
♦
♦
Abundant logic cells with shift register capability
Wide multiplexers
Table 1: Summary of Spartan-3 FPGA Attributes
CLB Array
(One CLB = Four Slices)
Maximum
Maximum Differential
System
Gates
Logic
Cells
Distributed BlockRAM
Dedicated
Multipliers
Device
XA3S50
Rows Columns Total CLBs RAM (bits1)
(bits1)
DCMs
User I/O
I/O Pairs
50K
200K
400K
1M
1,728
4,320
16
24
32
48
64
12
20
28
40
52
192
480
12K
30K
72K
4
2
4
4
4
4
124
56
XA3S200
XA3S400
XA3S1000
XA3S1500
Notes:
216K
288K
432K
576K
12
16
24
32
173
76
8,064
896
56K
264
116
17,280
29,952
1,920
3,328
120K
208K
333
149
1.5M
487
221
1. By convention, one Kb is equivalent to 1,024 bits.
© 2004–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. HyperTransport is a licensed trademark of the HyperTransport Technology Consortium in the U.S. and other jurisdictions. All other trademarks are the property of their
respective owners.
DS314 (v1.3) June 18, 2009
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Product Specification
1
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Introduction and Ordering Information
♦
♦
♦
Fast look-ahead carry logic
elements that can be used as flip-flops or latches.
CLBs can be programmed to perform a wide variety of
logical functions as well as to store data.
Dedicated 18 x 18 multipliers
JTAG logic compatible with IEEE 1149.1/1532
•
Input/Output Blocks (IOBs) control the flow of data
between the I/O pins and the internal logic of the
device. Each IOB supports bidirectional data flow plus
3-state operation. Twenty-six different signal standards,
including eight high-performance differential standards,
are available as shown in Table 2. Double Data-Rate
(DDR) registers are included. The Digitally Controlled
Impedance (DCI) feature provides automatic on-chip
terminations, simplifying board designs.
•
•
SelectRAM™ hierarchical memory
♦
♦
Up to 576 Kbits of total block RAM
Up to 208 Kbits of total distributed RAM
Digital Clock Manager (up to four DCMs)
♦
♦
♦
♦
Clock skew elimination
Frequency synthesis
High-resolution phase shifting
Maximum clock frequency 125 MHz
•
•
•
Block RAM provides data storage in the form of 18-Kbit
dual-port blocks.
•
•
Fully supported by Xilinx ISE® software development
system
Multiplier blocks accept two 18-bit binary numbers as
inputs and calculate the product.
♦
Synthesis, mapping, placement and routing
Digital Clock Manager (DCM) blocks provide
self-calibrating, fully digital solutions for distributing,
delaying, multiplying, dividing, and phase shifting clock
signals.
MicroBlaze™ processor, CAN, LIN, MOST, and other
cores
•
•
Pb-free packaging options
These elements are organized as shown in Figure 1. A ring
of IOBs surrounds a regular array of CLBs. The XA3S50
has a single column of block RAM embedded in the array.
Those devices ranging from the XA3S200 to the XA3S1500
have two columns of block RAM. Each column is made up
of several 18 Kbit RAM blocks; each block is associated
with a dedicated multiplier. The DCMs are positioned at the
ends of the block RAM columns.
Xilinx and all of our production partners are qualified to
ISO-TS16949
Please refer to the Spartan-3 complete data sheet (DS099)
for a full product description, AC and DC specifications, and
package pinout descriptions
Architectural Overview
The Spartan-3 family architecture consists of five
fundamental programmable functional elements:
The Spartan-3 family features a rich network of traces and
switches that interconnect all five functional elements,
transmitting signals among them. Each functional element
has an associated switch matrix that permits multiple
connections to the routing.
•
Configurable Logic Blocks (CLBs) contain RAM-based
Look-Up Tables (LUTs) to implement logic and storage
DS314 (v1.3) June 18, 2009
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Product Specification
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Introduction and Ordering Information
DS314-1_01_100808
Notes:
1.
The XA3S50 has only the block RAM column on the far left.
Figure 1: Spartan-3 Family Architecture
Configuration
I/O Capabilities
Spartan-3 FPGAs are programmed by loading configuration
data into robust static memory cells that collectively control
all functional elements and routing resources. Before
powering on the FPGA, configuration data is stored
externally in a PROM or some other nonvolatile medium
either on or off the board. After applying power, the
configuration data is written to the FPGA using any of five
different modes: Master Parallel, Slave Parallel, Master
Serial, Slave Serial and Boundary Scan (JTAG). The Master
and Slave Parallel modes use an 8-bit-wide SelectMAP
port.
The SelectIO feature of Spartan-3 devices supports 18
single-ended standards and eight differential standards as
listed in Table 2. Many standards support the DCI feature,
which uses integrated terminations to eliminate unwanted
signal reflections. Table 3 shows the number of user I/Os as
well as the number of differential I/O pairs available for each
device/package combination.
.
DS314 (v1.3) June 18, 2009
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Product Specification
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Introduction and Ordering Information
DCI
Table 2: Signal Standards Supported by the Spartan-3 Family
Standard
Description
V
CCO (V)
Class
Symbol
Category
Single-Ended
GTL
Option
GTL
Gunning Transceiver Logic
N/A
1.5
1.8
Terminated
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
GTLP
Plus
HSTL
High-Speed Transceiver Logic
I
HSTL_I
HSTL_III
III
HSTL_I_18
HSTL_II_18
HSTL_III_18
LVCMOS12
LVCMOS15
LVCMOS18
LVCMOS25
LVCMOS33
LVTTL
I
II
III
LVCMOS
Low-Voltage CMOS
1.2
1.5
1.8
2.5
3.3
3.3
3.0
1.8
N/A
N/A
Yes
Yes
Yes
Yes
No
N/A
N/A
N/A
LVTTL
PCI
Low-Voltage Transistor-Transistor Logic
Peripheral Component Interconnect
Stub Series Terminated Logic
N/A
PCI33_3
33 MHz
No
SSTL
N/A ( 6.7 mA)
SSTL18_I
SSTL18_II
SSTL2_I
Yes
No
N/A ( 13.4 mA)
2.5
2.5
I
Yes
Yes
II
SSTL2_II
Differential
LDT
(ULVDS)
Lightning Data Transport
(HyperTransport™)
LDT_25
N/A
No
LVDS_25
BLVDS_25
LVDS
Low-Voltage Differential Signaling
Standard
Bus
Yes
No
LVDSEXT_25
Extended Mode
N/A
Yes
No
LVPECL
Low-Voltage Positive Emitter-Coupled
Logic
2.5
LVPECL_25
RSDS_25
RSDS
HSTL
SSTL
Reduced-Swing Differential Signaling
Differential High-Speed Transceiver Logic
Differential Stub Series Terminated Logic
2.5
1.8
2.5
N/A
II
No
Yes
Yes
DIFF_HSTL_II_18
DIFF_SSTL2_II
II
DS314 (v1.3) June 18, 2009
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Product Specification
4
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Introduction and Ordering Information
Table 3: Spartan-3 XA I/O Chart
Available User I/Os and Differential (Diff) I/O Pairs
TQG144 PQG208 FTG256 FGG456
VQG100
FGG676
Device
XA3S50
Grade User
Diff
29
29
-
User
Diff
User
Diff
56
62
62
-
User
Diff
-
User
Diff
-
User
Diff
I,Q
I,Q
I,Q
I,Q
I
63
63
-
-
97
-
-
46
-
124
141
141
-
-
-
-
-
XA3S200
XA3S400
XA3S1000
XA3S1500
Notes:
173
173
173
-
76
76
76
-
-
-
-
-
264
333
333
116
149
149
-
-
-
-
-
-
-
-
-
-
-
-
-
-
487
221
1. All device options listed in a given package column are pin-compatible.
DC Specifications
Table 4: General Recommended Operating Conditions
Symbol
Description
Junction temperature
Min
–40
Nom
Max
Units
I-Grade
25
100
125
°C
TJ
–40
25
°C
Q-Grade
VCCINT
Internal supply voltage
1.140
1.140
2.375
-
1.200
1.260
3.450
2.625
10
V
(1)
VCCO
-
V
Output driver supply voltage
Auxiliary supply voltage
VCCAUX
2.500
V
(2)
ΔVCCAUX
Voltage variance on VCCAUX when using a DCM
-
-
-
-
mV/ms
VIN
Voltage applied to all User I/O
pins and Dual-Purpose pins
relative to GND
V
CCO = 3.3V
CCO < 2.5V
–0.3
–0.3
–0.3
3.75
V
V
V
V
V
CCO+0.3
Voltage applied to all
Dedicated pins relative to
GND
VCCAUX+0.3
Notes:
1. The V
range given here spans the lowest and highest operating voltages of all supported I/O standards. The recommended V
range
CCO
CCO
specific to each of the single-ended I/O standards is given in Table 34 of DS099, and that specific to the differential standards is given in
Table 36 of DS099.
2. Only during DCM operation is it recommended that the rate of change of VCCAUX not exceed 10 mV/ms.
DS314 (v1.3) June 18, 2009
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Product Specification
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Introduction and Ordering Information
Table 5: Quiescent Supply Current Characteristics
I-Grade
Maximum
Q-Grade
Symbol
ICCINTQ
Description
Device
XA3S50
Units
mA
Maximum
Quiescent VCCINT supply current
50
100
XA3S200
XA3S400
XA3S1000
XA3S1500
XA3S50
125
180
315
410
12
200
250
400
-
mA
mA
mA
mA
mA
ICCOQ
Quiescent VCCO supply current
12
XA3S200
XA3S400
XA3S1000
XA3S1500
XA3S50
12
14
14
16
22
12
14
14
-
mA
mA
mA
mA
mA
ICCAUXQ
Quiescent VCCAUX supply current
25
XA3S200
XA3S400
XA3S1000
XA3S1500
33
44
55
85
35
50
60
-
mA
mA
mA
mA
Notes:
1. The numbers in this table are based on the conditions set forth in Table 31 of DS099. Quiescent supply current is measured with all
I/O drivers in a high-impedance state and with all pull-up/pull-down resistors at the I/O pads disabled. Typical values are
characterized using devices with typical processing at ambient room temperature (TA of 25°C at VCCINT = 1.2V, VCCO = 3.3V, and
V
CCAUX = 2.5V). Maximum values are the production test limits measured for each device at the maximum specified junction
temperature and at maximum voltage limits with VCCINT = 1.26V, VCCO = 3.45V, and VCCAUX = 2.625V. The FPGA is programmed
with a “blank” configuration data file (i.e., a design with no functional elements instantiated). For conditions other than those
described above, (e.g., a design including functional elements, the use of DCI standards, etc.), measured quiescent current levels
may be different than the values in the table. Use the XPower Power Estimator for more accurate estimates. See Note 2.
2. There are two recommended ways to estimate the total power consumption (quiescent plus dynamic) for a specific design: a) The
XPower Power Estimator at http://www.xilinx.com/ise/power_tools provides quick, approximate, typical estimates, and does not
require a netlist of the design. b) XPower, part of the Xilinx ISE development software, uses the FPGA netlist as input to provide more
accurate maximum and typical estimates.
3. The maximum numbers in this table also indicate the minimum current each power rail requires in order for the FPGA to power-on
successfully, once all three rails are supplied. If VCCINT is applied before VCCAUX, there may be temporary additional ICCINT current
until VCCAUX is applied. See Surplus ICCINT if VCCINT Applied before VCCAUX, page 51 of DS099.
Ordering Information
Mask Revision Code
R
BGA Ball A1
Fabrication Code
Process Code
R
SPARTAN
Device Type
XA3S1000TM
Date Code
Lot Code
Package
FTG256EGQ0525
D1234567A
4Q
Speed Grade
Temperature Range
DS314-1_02_100808
Figure 2: Spartan-3 BGA Package Marking Example for Part Number XA3S1000-4 FTG256Q
Spartan-3 FPGAs are available in Pb-free packaging options for all device/package combinations. The Pb-free packages
include a special “G” character in the ordering code.
DS314 (v1.3) June 18, 2009
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Product Specification
6
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Introduction and Ordering Information
Pb-Free Packaging
For additional information on Pb-free packaging, see XAPP427: Implementation and Solder Reflow Guidelines for Pb-Free
Packages.
Example: XA3S50 -4 PQ G 208 Q
Device Type
Speed Grade
Package Type
Temperature Range:
Q-Grade = Automotive Extended (TJ = –40°C to +125°C)
I-Grade = Automotive Industrial (TJ = –40°C to +100°C)
Number of Pins
Pb-free
DS314-1_03_100808
Table 6: Package Types and Number of Pins
Device
Speed Grade
Package Type / Number of Pins
Temperature Range (TJ)
I-Grade (–40°C to +100°C)
Q-Grade (–40°C to +125°C)
Standard
Performance
XA3S50
-4
VQG100
100-pin Very Thin Quad Flat Pack (VQFP)
I
XA3S200
XA3S400
TQG144
PQG208
144-pin Thin Quad Flat Pack (TQFP)
208-pin Plastic Quad Flat Pack (PQFP)
Q
256-ball Fine-Pitch Thin Ball Grid Array
(FTBGA)
XA3S1000
XA3S1500
FTG256
FGG456
FGG676
456-ball Fine-Pitch Ball Grid Array (FBGA)
676-ball Fine-Pitch Ball Grid Array (FBGA)
Additional Resources
•
•
•
DS099, Spartan-3 FPGA Family Data Sheet
UG331, Spartan-3 Generation FPGA User Guide
UG332, Spartan-3 Generation Configuration User Guide
Revision History
The following table shows the revision history for this document:
Date
Version
1.0
Description
10/18/04
12/20/04
10/27/06
Initial Xilinx release.
1.1
Multiple text edits throughout.
1.2
Updated IO standards (Table 2), and link to Spartan-3 Data Sheet, added XA3S1500, TQG144, FGG676,
Table 4, and Table 5.
11/28/06
11/12/07
01/25/08
06/18/09
1.2.1
1.2.2
1.2.3
1.3
Changed order of explanations in Table 6 for TQG144 and PQG208.
Changed all values for the Block RAM (bits) column and two values for the XA3S1000 row in Table 1.
Changed XA3S1500 Q-Grade Maximum in Table 5.
Added UG331 and UG332 to "Additional Resources" section.
DS314 (v1.3) June 18, 2009
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Product Specification
7
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Introduction and Ordering Information
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED
WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE
SPECIFICATIONS STATED ON THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
Automotive Applications Disclaimer
XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING
FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A
VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN
THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III)
USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY
USE OF XILINX PRODUCTS IN SUCH APPLICATIONS.
DS314 (v1.3) June 18, 2009
www.xilinx.com
Product Specification
8
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