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XC1701L(3.3V)

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描述：Serial Configuration PROMs

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XC1701L(3.3V) 概述

Serial Configuration PROMs 串行CON组fi guration的PROM

XC1701L(3.3V) 数据手册

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XC1701L (3.3V), XC1701 (5.0V) and

XC17512L (3.3V)

Serial Conﬁguration PROMs

December 10, 1997 (Version 1.1)

Product Specification

Features

Description

•

On-chip address counter, incremented by each rising

edge on the clock input

Simple interface to the FPGA; requires only one user

I/O pin

Cascadable for storing longer or multiple bitstreams

Programmable reset polarity (active High or active Low)

for compatibility with different FPGA solutions

Supports XC4000EX/XL fast conﬁguration mode (15.0

MHz)

Low-power CMOS Floating Gate process

Available in 5 V and 3.3 V versions

Available in compact plastic packages: 8-pin PDIP,

20-pin SOIC, and 20-pin PLCC.

The XC1701L, XC1701 and XC17512L serial conﬁguration

PROMs (SCPs) provide an easy-to-use, cost-effective

method for storing Xilinx FPGA conﬁguration bitstreams.

•

When the FPGA is in master serial mode, it generates a

conﬁguration clock that drives the SCP. A short access time

after the rising clock edge, data appears on the SCP DATA

output pin that is connected to the FPGA DIN pin. The

FPGA generates the appropriate number of clock pulses to

complete the conﬁguration. Once conﬁgured, it disables the

SCP. When the FPGA is in slave mode, the SCP and the

FPGA must both be clocked by an incoming signal.

•

Multiple devices can be concatenated by using the CEO

output to drive the CE input of the following device. The

clock inputs and the DATA outputs of all SCPs in this chain

are interconnected. All devices are compatible and can be

cascaded with other members of the family.

•

Programming support by leading programmer

manufacturers.

Design support using the Xilinx Alliance and

Foundation series software packages.

For device programming, either the Xilinx Alliance or Foun-

dation series development system compiles the FPGA

design ﬁle into a standard Hex format, which is then trans-

ferred to the programmer.

GND

CEO

RESET/

OE or

OE/

RESET

Address Counter

CLK

EPROM

Cell

Output

DATA

Matrix

X3185

Figure 1: Simpliﬁed Block Diagram (does not show programming circuit)

December 10, 1997 (Version 1.1)

5-1

XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Conﬁguration PROMs

Serial PROM Pinouts

Pin Description

8-Pin

PDIP

20-Pin

SOIC

20-Pin

PLCC

Pin Name

DATA

Data output, 3-stated when either CE or OE are inactive.

During programming, the DATA pin is I/O. Note that OE can

be programmed to be either active High or active Low.

DATA

CLK

RESET/OE (OE/RESET)

CLK

GND

CEO

Each rising edge on the CLK input increments the internal

address counter, if both CE and OE are active.

RESET/OE

Capacity

When High, this input holds the address counter reset and

3-states the DATA output. The polarity of this input pin is

programmable as either RESET/OE or OE/RESET. To

avoid confusion, this document describes the pin as

RESET/OE, although the opposite polarity is possible on all

devices. When RESET is active, the address counter is

held at zero, and the DATA output is 3-stated. The polarity

of this input is programmable. The default is active High

RESET, but the preferred option is active Low RESET,

because it can be driven by the FPGA’s INIT pin.

Device

Conﬁguration Bits

1,048,576

XC1701L

XC1701

1,048,576

XC17512L

524,288

Number of Conﬁguration Bits, Including

Header for all Xilinx FPGAs and Compatible

SCP Type

Device

Conﬁguration Bits

283,424

SPROM

XC17512L

XC1701

The polarity of this pin is controlled in the programmer inter-

face. This input pin is easily inverted using the Xilinx HW-

130 Programmer. Third-party programmers have different

methods to invert this pin.

XC4010XL

XC4013XL

XC4020E

XC4020XL

XC4025E

XC4028XL

XC4028EX

XC4036EX

XC4036XL

XC4044XL

XC4052XL

393,623

329,312

521,880

XC17512L

XC1701

422,176

668,184

XC1701L

XC1701

When High, this pin disables the internal address counter,

3-states the DATA output, and forces the device into low-I_CC

standby mode.

668,184

832,528

XC1701

832,528

XC1701L

1,014,928

1,215,368

CEO

XC1701L +

XC17256L

Chip Enable output, to be connected to the CE input of the

next SCP in the daisy chain. This output is Low when the

CE and OE inputs are both active AND the internal address

counter has been incremented beyond its Terminal Count

(TC) value. In other words: when the PROM has been read,

CEO will follow CE as long as OE is active. When OE goes

inactive, CEO stays High until the PROM is reset. Note that

OE can be programmed to be either active High or active

Low.

XC4062XL

XC4085XL

1,433,864

1,924,992

XC1701L +

XC17512L

2 x XC1701L

Programming voltage. No overshoot above the speciﬁed

max voltage is permitted on this pin. For normal read oper-

ation, this pin must be connected to V_CC. Failure to do so

may lead to unpredictable, temperature-dependent opera-

tion and severe problems in circuit debugging. Do not leave

VPP ﬂoating!

and GND

Positive supply and ground pins.

5-2

December 10, 1997 (Version 1.1)

internal address and bit counters which are incremented on

every valid rising edge of CCLK.

Controlling Serial PROMs

Most connections between the FPGA device and the Serial

PROM are simple and self-explanatory.

If the user-programmable, dual-function DIN pin on the

FPGA is used only for conﬁguration, it must still be held at

a deﬁned level during normal operation. The XC3000 and

XC4000 families take care of this automatically with an on-

chip default pull-up resistor.

•

The DATA output(s) of the of the Serial PROM(s) drives

the DIN input of the lead FPGA device.

The master FPGA CCLK output drives the CLK input(s)

of the Serial PROM(s).

The CEO output of a Serial PROM drives the CE input

of the next Serial PROM in a daisy chain (if any).

The RESET/OE input of all Serial PROMs is best driven

by the INIT output of the XC3000 or XC4000 lead

FPGA device. This connection assures that the Serial

PROM address counter is reset before the start of any

(re)conﬁguration, even when a reconﬁguration is

initiated by a V_CCglitch. Other methods – such as

Programming the FPGA With Counters

Unchanged Upon Completion

When multiple FPGA-conﬁgurations for a single FPGA are

stored in a Serial Conﬁguration PROM, the OE pin should

be tied Low. Upon power-up, the internal address counters

are reset and conﬁguration begins with the ﬁrst program

stored in memory. Since the OE pin is held Low, the

address counters are left unchanged after conﬁguration is

complete. Therefore, to reprogram the FPGA with another

program, the D/P line is pulled Low and conﬁguration

begins at the last value of the address counters.

driving RESET/OE from LDC or system reset – assume

that the Serial PROM internal power-on-reset is always

in step with the FPGA’s internal power-on-reset, which

may not be a safe assumption.

•

The CE input of the lead (or only) Serial PROM is driven

by the DONE/PRGM or DONE output of the lead FPGA

device, provided that DONE/PRGM is not permanently

grounded. Otherwise, LDC can be used to drive CE, but

must then be unconditionally High during user

operation. CE can also be permanently tied Low, but

this keeps the DATA output active and causes an

unnecessary supply current of 10 mA maximum.

This method fails if a user applies RESET during the FPGA

conﬁguration process. The FPGA aborts the conﬁguration

and then restarts a new conﬁguration, as intended, but the

Serial PROM does not reset its address counter, since it

never saw a High level on its OE input. The new conﬁgura-

tion, therefore, reads the remaining data in the PROM and

interprets it as preamble, length count etc. Since the FPGA

is the master, it issues the necessary number of CCLK

pulses, up to 16 million (24) and D/P goes High. However,

the FPGA conﬁguration will be completely wrong, with

potential contentions inside the FPGA and on its output

pins. This method must, therefore, never be used when

there is any chance of external reset during conﬁguration.

FPGA Master Serial Mode Summary

The I/O and logic functions of the Logic Cell Array and their

associated interconnections are established by a conﬁgu-

ration program. The program is loaded either automatically

upon power up, or on command, depending on the state of

the three FPGA mode pins. In Master Mode, the FPGA

automatically loads the conﬁguration program from an

external memory. The Serial Conﬁguration PROM has

been designed for compatibility with the Master Serial

Mode.

Cascading Serial Conﬁguration PROMs

For multiple FPGAs conﬁgured as a daisy-chain, or for

future FPGAs requiring larger conﬁguration memories, cas-

caded SCPs provide additional memory. After the last bit

from the ﬁrst SCP is read, the next clock signal to the SCP

asserts its CEO output Low and disables its DATA line. The

second SCP recognizes the Low level on its CE input and

enables its DATA output. See Figure 2.

Upon power-up or reconﬁguration, an FPGA enters the

Master Serial Mode whenever all three of the FPGA mode-

select pins are Low (M0=0, M1=0, M2=0). Data is read from

the Serial Conﬁguration PROM sequentially on a single

data line. Synchronization is provided by the rising edge of

the temporary signal CCLK, which is generated during con-

ﬁguration.

After conﬁguration is complete, the address counters of all

cascaded SCPs are reset if the FPGA RESET pin goes

Low, assuming the SCP reset polarity option has been

inverted.

To reprogram the FPGA with another program, the D/P line

goes Low and conﬁguration begins where the address

counters had stopped. In this case, avoid contention

between DATA and the conﬁgured I/O use of DIN.

Master Serial Mode provides a simple conﬁguration inter-

face. Only a serial data line and two control lines are

required to conﬁgure an FPGA. Data from the Serial Con-

ﬁguration PROM is read sequentially, accessed via the

December 10, 1997 (Version 1.1)

5-3

XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Conﬁguration PROMs

* If Readback is

Activated, a

3.3-kΩ Resistor is

Vcc

Required in

Series With M1

M0 M1 PWRDWN

DOUT

During Configuration

OPTIONAL

the 3.3 kΩ M2 Pull-Down

Resistor Overcomes the

Internal Pull-Up,

Daisy-chained

FPGAs with

Different

HDC

LDC

INIT

but it Allows M2 to

be User I/O.

General-

Purpose

User I/O

Pins

Configurations

•

Other

I/O Pins

OPTIONAL

Slave FPGAs

with Identical

Configurations

FPGA

Vcc

RESET

DATA

CLK

DIN

CCLK

D/P

Cascaded

Serial

Memory

CLK

SCP

CEO

INIT

OE/RESET

(Low Resets the Address Pointer)

CCLK

(OUTPUT)

DIN

DOUT

(OUTPUT)

X8256

Figure 2: Master Serial Mode. The one-time-programmable Serial Conﬁguration PROM supports automatic loading of

conﬁguration programs. Multiple devices can be cascaded to support additional FPGA. An early D/P inhibits the

PROM data output one CCLK cycle before the FPGA I/Os become active.

5-4

December 10, 1997 (Version 1.1)

Standby Mode

Programming

The PROM enters a low-power standby mode whenever

CE is asserted High. The output remains in a high imped-

ance state regardless of the state of the OE input.

The devices can be programmed on programmers supplied

by Xilinx or qualiﬁed third-party vendors. The user must

ensure that the appropriate programming algorithm and the

latest version of the programmer software are used. The

wrong choice can permanently damage the device.

Table 1: Truth Table for XC1700 Control Inputs

Control Inputs

Outputs

Internal Address

RESET

Inactive

Low

DATA

active

3-state

CEO

High

Low

High

I_cc

active

reduced

active

if address < TC: increment

if address > TC: don’t change

Held reset

Active

Inactive

Active

Low

High

Not changing

standby

Held reset

Notes: 1. The XC1700 RESET input has programmable polarity

2. TC = Terminal Count = highest address value. TC+1 = address 0.

IMPORTANT: Always tie the V_PPpin to V_CCin your application. Never leave V_PPﬂoating.

December 10, 1997 (Version 1.1)

5-5

XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Conﬁguration PROMs

XC1701

Absolute Maximum Ratings

Symbol

Description

Supply voltage relative to GND

Units

V_CC

V_PP

V_IN

-0.5 to +7.0

-0.5 to +12.5

-0.5 to V_CC+0.5

-65 to +150

+260

Supply voltage relative to GND

Input voltage relative to GND

V_TS

Voltage applied to 3-state output

Storage temperature (ambient)

T_STG

T_SOL

°C

Maximum soldering temperature (10 s @ 1/16 in.)

Note:

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are

stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under

Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may

affect device reliability.

Operating Conditions

Symbol

Description

Commercial

Industrial

Min

4.75

4.50

Max

5.25

5.50

Units

V_CC

Supply voltage relative to GND 0°C to +70°C junction

Supply voltage relative to GND -40°C to +85°C junction

Supply voltage relative to GND -55°C to +125°C case

Military

DC Characteristics Over Operating Condition

Symbol

V_IH

Description

Min

Max

Units

High-level input voltage

Low-level input voltage

2.0

V_CC

0.8

V_IL

V_OH

V_OL

V_OH

V_OL

I_CCA

I_CCS

I_L

High-level output voltage (I_OH= -4 mA)

Low-level output voltage (I_OL= +4 mA)

High-level output voltage (I_OH= -4 mA)

Low-level output voltage (I_OL= +4 mA)

Supply current, active mode

Commercial

Industrial

3.86

0.32

3.76

0.37

10.0

50.0

10.0

µA

Supply current, standby mode

Input or output leakage current

-10.0

Note: During normal read operation V must be connected to V

5-6

December 10, 1997 (Version 1.1)

XC1701L/XC17512L

Absolute Maximum Ratings

Symbol

Description

Units

V_CC

V_PP

V_IN

Supply voltage relative to GND

-0.5 to +6.0

-0.5 to +12.5

-0.5 to V_CC+0.5

-65 to +150

+260

Input voltage with respect to GND

Voltage applied to 3-state output

V_TS

T_STG

T_SOL

Storage temperature (ambient)

°C

Maximum soldering temperature (10 s @ 1/16 in.)

Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating

Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device

reliability.

Operating Conditions

Symbol

Description

Min

Max

Units

V_CC

Commercial

Supply voltage relative to GND 0°C to +70°C junction

3.0

3.6

DC Characteristics Over Operating Condition

Symbol

V_IH

Description

Min

Max

Units

High-level input voltage

Low-level input voltage

2.0

V_CC

0.8

V_IL

V_OH

V_OL

I_CCA

I_CCS

I_L

High-level output voltage (I_OH= -4 mA)

Low-level output voltage (I_OL= +4 mA)

Supply current, active mode

2.4

0.4

5.0

µA

Supply current, standby mode

50.0

10.0

Input or output leakage current

-10.0

Note: During normal read operation V must be connected to V

December 10, 1997 (Version 1.1)

5-7

XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Conﬁguration PROMs

AC Characteristics Over Operating Condition

HCE

SCE

RESET/OE

HOE

CYC

CLK

CAC

DATA

X2634

XC1701L

XC17512L

XC1701

Min Max

Symbol

Description

Units

Min

Max

T_OE

T_CE

T_CAC

T_OH

T_DF

T_CYC

T_LC

THC

TSCE

T_HCE

T_HOE

OE to Data Delay

CE to Data Delay

CLK to Data Delay

Data Hold From CE, OE, or CLK

CE or OE to Data Float Delay²

Clock Periods

CLK Low Time³

CLK High Time³

CE Setup Time to CLK (to guarantee proper counting)

CE Hold Time to CLK (to guarantee proper counting)

OE Hold Time (guarantees counters are reset)

100

Notes: 1. AC test load = 50 pF

2. Float delays are measured with minimum tester ac load and maximum dc load.

3. Guaranteed by design, not tested.

4. All AC parameters are measured with V = 0.0 V and V = 3.0 V.

5-8

December 10, 1997 (Version 1.1)

AC Characteristics Over Operating Condition (continued)

RESET/OE

CLK

CDF

Last Bit

First Bit

DATA

CEO

OOE

OCK

OCE

X3183

XC1701L

XC17512L

XC1701

Symbol

Description

CLK to Data Float Delay²

CLK to CEO Delay

CE to CEO Delay

Units

Min

Max

Min Max

12 T_CDF

13 T_OCK

14 T_OCE

15 T_OOE

RESET/OE to CEO Delay

Notes: 1. AC test load = 50 pF

2. Float delays are measured with minimum tester ac load and maximum dc load.

3. Guaranteed by design, not tested.

4. All AC parameters are measured with V = 0.0 V and V = 3.0 V.

December 10, 1997 (Version 1.1)

5-9

XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Conﬁguration PROMs

Ordering Information

XC1701L PC20 C

Device Number

Operating Range/Processing

XC1701L

C = Commercial (0° to +70°C)

XC1701

XC17512L

= Industrial (–40° to +85°C)

Package Type

PD8 = 8-Pin Plastic DIP

SO20 = 20-Pin Plastic Small-Outline Package

PC20 = 20-Pin Plastic Leaded Chip Carrier

Marking Information

Due to the small size of the serial PROM package, the complete ordering part number cannot be marked on the package.

The XC preﬁx is deleted and the package code is simpliﬁed. Device marking is as follows.

1701L

Device Number

Operating Range/Processing

XC1701L

XC1701

XC17512L

C = Commercial (0° to +70°C)

Package Type

= Industrial (–40° to +85°C)

= 8-Pin Plastic DIP

= 20-Pin Plastic Small-Outline Package

= 20-Pin Plastic Leaded Chip Carrier

5-10

December 10, 1997 (Version 1.1)

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