XC1701L(3.3V) [XILINX]

Serial Configuration PROMs; 串行CON组fi guration的PROM
XC1701L(3.3V)
型号: XC1701L(3.3V)
厂家: XILINX, INC    XILINX, INC
描述:

Serial Configuration PROMs
串行CON组fi guration的PROM

可编程只读存储器
文件: 总10页 (文件大小:73K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
0
XC1701L (3.3V), XC1701 (5.0V) and  
XC17512L (3.3V)  
Serial Configuration PROMs  
0
5*  
December 10, 1997 (Version 1.1)  
Product Specification  
Features  
Description  
On-chip address counter, incremented by each rising  
edge on the clock input  
Simple interface to the FPGA; requires only one user  
I/O pin  
Cascadable for storing longer or multiple bitstreams  
Programmable reset polarity (active High or active Low)  
for compatibility with different FPGA solutions  
Supports XC4000EX/XL fast configuration mode (15.0  
MHz)  
Low-power CMOS Floating Gate process  
Available in 5 V and 3.3 V versions  
Available in compact plastic packages: 8-pin PDIP,  
20-pin SOIC, and 20-pin PLCC.  
The XC1701L, XC1701 and XC17512L serial configuration  
PROMs (SCPs) provide an easy-to-use, cost-effective  
method for storing Xilinx FPGA configuration bitstreams.  
When the FPGA is in master serial mode, it generates a  
configuration clock that drives the SCP. A short access time  
after the rising clock edge, data appears on the SCP DATA  
output pin that is connected to the FPGA DIN pin. The  
FPGA generates the appropriate number of clock pulses to  
complete the configuration. Once configured, it disables the  
SCP. When the FPGA is in slave mode, the SCP and the  
FPGA must both be clocked by an incoming signal.  
Multiple devices can be concatenated by using the CEO  
output to drive the CE input of the following device. The  
clock inputs and the DATA outputs of all SCPs in this chain  
are interconnected. All devices are compatible and can be  
cascaded with other members of the family.  
Programming support by leading programmer  
manufacturers.  
Design support using the Xilinx Alliance and  
Foundation series software packages.  
For device programming, either the Xilinx Alliance or Foun-  
dation series development system compiles the FPGA  
design file into a standard Hex format, which is then trans-  
ferred to the programmer.  
V
V
PP  
GND  
CC  
CEO  
CE  
RESET/  
OE or  
OE/  
RESET  
Address Counter  
CLK  
TC  
OE  
EPROM  
Cell  
Output  
DATA  
Matrix  
X3185  
Figure 1: Simplified Block Diagram (does not show programming circuit)  
December 10, 1997 (Version 1.1)  
5-1  
XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Configuration PROMs  
Serial PROM Pinouts  
Pin Description  
8-Pin  
PDIP  
20-Pin  
SOIC  
20-Pin  
PLCC  
Pin Name  
DATA  
Data output, 3-stated when either CE or OE are inactive.  
During programming, the DATA pin is I/O. Note that OE can  
be programmed to be either active High or active Low.  
DATA  
CLK  
1
2
3
4
5
6
7
8
1
2
4
3
RESET/OE (OE/RESET)  
8
6
CE  
10  
11  
13  
18  
20  
8
CLK  
GND  
CEO  
10  
14  
17  
20  
Each rising edge on the CLK input increments the internal  
address counter, if both CE and OE are active.  
V
PP  
V
CC  
RESET/OE  
Capacity  
When High, this input holds the address counter reset and  
3-states the DATA output. The polarity of this input pin is  
programmable as either RESET/OE or OE/RESET. To  
avoid confusion, this document describes the pin as  
RESET/OE, although the opposite polarity is possible on all  
devices. When RESET is active, the address counter is  
held at zero, and the DATA output is 3-stated. The polarity  
of this input is programmable. The default is active High  
RESET, but the preferred option is active Low RESET,  
because it can be driven by the FPGA’s INIT pin.  
Device  
Configuration Bits  
1,048,576  
XC1701L  
XC1701  
1,048,576  
XC17512L  
524,288  
Number of Configuration Bits, Including  
Header for all Xilinx FPGAs and Compatible  
SCP Type  
Device  
Configuration Bits  
283,424  
SPROM  
XC17512L  
XC17512L  
XC1701  
The polarity of this pin is controlled in the programmer inter-  
face. This input pin is easily inverted using the Xilinx HW-  
130 Programmer. Third-party programmers have different  
methods to invert this pin.  
XC4010XL  
XC4013XL  
XC4020E  
XC4020XL  
XC4025E  
XC4028XL  
XC4028EX  
XC4036EX  
XC4036XL  
XC4044XL  
XC4052XL  
393,623  
329,312  
521,880  
XC17512L  
XC1701  
422,176  
CE  
668,184  
XC1701L  
XC1701  
When High, this pin disables the internal address counter,  
3-states the DATA output, and forces the device into low-ICC  
standby mode.  
668,184  
832,528  
XC1701  
832,528  
XC1701L  
XC1701L  
1,014,928  
1,215,368  
CEO  
XC1701L +  
XC17256L  
Chip Enable output, to be connected to the CE input of the  
next SCP in the daisy chain. This output is Low when the  
CE and OE inputs are both active AND the internal address  
counter has been incremented beyond its Terminal Count  
(TC) value. In other words: when the PROM has been read,  
CEO will follow CE as long as OE is active. When OE goes  
inactive, CEO stays High until the PROM is reset. Note that  
OE can be programmed to be either active High or active  
Low.  
XC4062XL  
XC4085XL  
1,433,864  
1,924,992  
XC1701L +  
XC17512L  
2 x XC1701L  
V
PP  
Programming voltage. No overshoot above the specified  
max voltage is permitted on this pin. For normal read oper-  
ation, this pin must be connected to VCC. Failure to do so  
may lead to unpredictable, temperature-dependent opera-  
tion and severe problems in circuit debugging. Do not leave  
VPP floating!  
V
and GND  
CC  
Positive supply and ground pins.  
5-2  
December 10, 1997 (Version 1.1)  
internal address and bit counters which are incremented on  
every valid rising edge of CCLK.  
Controlling Serial PROMs  
Most connections between the FPGA device and the Serial  
PROM are simple and self-explanatory.  
If the user-programmable, dual-function DIN pin on the  
FPGA is used only for configuration, it must still be held at  
a defined level during normal operation. The XC3000 and  
XC4000 families take care of this automatically with an on-  
chip default pull-up resistor.  
The DATA output(s) of the of the Serial PROM(s) drives  
the DIN input of the lead FPGA device.  
The master FPGA CCLK output drives the CLK input(s)  
of the Serial PROM(s).  
The CEO output of a Serial PROM drives the CE input  
of the next Serial PROM in a daisy chain (if any).  
The RESET/OE input of all Serial PROMs is best driven  
by the INIT output of the XC3000 or XC4000 lead  
FPGA device. This connection assures that the Serial  
PROM address counter is reset before the start of any  
(re)configuration, even when a reconfiguration is  
initiated by a VCC glitch. Other methods – such as  
Programming the FPGA With Counters  
Unchanged Upon Completion  
When multiple FPGA-configurations for a single FPGA are  
stored in a Serial Configuration PROM, the OE pin should  
be tied Low. Upon power-up, the internal address counters  
are reset and configuration begins with the first program  
stored in memory. Since the OE pin is held Low, the  
address counters are left unchanged after configuration is  
complete. Therefore, to reprogram the FPGA with another  
program, the D/P line is pulled Low and configuration  
begins at the last value of the address counters.  
driving RESET/OE from LDC or system reset – assume  
that the Serial PROM internal power-on-reset is always  
in step with the FPGA’s internal power-on-reset, which  
may not be a safe assumption.  
The CE input of the lead (or only) Serial PROM is driven  
by the DONE/PRGM or DONE output of the lead FPGA  
device, provided that DONE/PRGM is not permanently  
grounded. Otherwise, LDC can be used to drive CE, but  
must then be unconditionally High during user  
operation. CE can also be permanently tied Low, but  
this keeps the DATA output active and causes an  
unnecessary supply current of 10 mA maximum.  
This method fails if a user applies RESET during the FPGA  
configuration process. The FPGA aborts the configuration  
and then restarts a new configuration, as intended, but the  
Serial PROM does not reset its address counter, since it  
never saw a High level on its OE input. The new configura-  
tion, therefore, reads the remaining data in the PROM and  
interprets it as preamble, length count etc. Since the FPGA  
is the master, it issues the necessary number of CCLK  
pulses, up to 16 million (24) and D/P goes High. However,  
the FPGA configuration will be completely wrong, with  
potential contentions inside the FPGA and on its output  
pins. This method must, therefore, never be used when  
there is any chance of external reset during configuration.  
FPGA Master Serial Mode Summary  
The I/O and logic functions of the Logic Cell Array and their  
associated interconnections are established by a configu-  
ration program. The program is loaded either automatically  
upon power up, or on command, depending on the state of  
the three FPGA mode pins. In Master Mode, the FPGA  
automatically loads the configuration program from an  
external memory. The Serial Configuration PROM has  
been designed for compatibility with the Master Serial  
Mode.  
Cascading Serial Configuration PROMs  
For multiple FPGAs configured as a daisy-chain, or for  
future FPGAs requiring larger configuration memories, cas-  
caded SCPs provide additional memory. After the last bit  
from the first SCP is read, the next clock signal to the SCP  
asserts its CEO output Low and disables its DATA line. The  
second SCP recognizes the Low level on its CE input and  
enables its DATA output. See Figure 2.  
Upon power-up or reconfiguration, an FPGA enters the  
Master Serial Mode whenever all three of the FPGA mode-  
select pins are Low (M0=0, M1=0, M2=0). Data is read from  
the Serial Configuration PROM sequentially on a single  
data line. Synchronization is provided by the rising edge of  
the temporary signal CCLK, which is generated during con-  
figuration.  
After configuration is complete, the address counters of all  
cascaded SCPs are reset if the FPGA RESET pin goes  
Low, assuming the SCP reset polarity option has been  
inverted.  
To reprogram the FPGA with another program, the D/P line  
goes Low and configuration begins where the address  
counters had stopped. In this case, avoid contention  
between DATA and the configured I/O use of DIN.  
Master Serial Mode provides a simple configuration inter-  
face. Only a serial data line and two control lines are  
required to configure an FPGA. Data from the Serial Con-  
figuration PROM is read sequentially, accessed via the  
December 10, 1997 (Version 1.1)  
5-3  
XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Configuration PROMs  
* If Readback is  
Activated, a  
3.3-kResistor is  
Vcc  
*
Required in  
Series With M1  
M0 M1 PWRDWN  
DOUT  
During Configuration  
OPTIONAL  
the 3.3 kM2 Pull-Down  
Resistor Overcomes the  
Internal Pull-Up,  
M2  
Daisy-chained  
FPGAs with  
Different  
HDC  
LDC  
INIT  
but it Allows M2 to  
be User I/O.  
General-  
Purpose  
User I/O  
Pins  
Configurations  
Other  
I/O Pins  
OPTIONAL  
Slave FPGAs  
with Identical  
Configurations  
FPGA  
Vcc  
RESET  
RESET  
V
V
PP  
CC  
DATA  
DATA  
CLK  
DIN  
CCLK  
D/P  
Cascaded  
Serial  
Memory  
CLK  
SCP  
CEO  
CE  
CE  
INIT  
OE/RESET  
OE/RESET  
(Low Resets the Address Pointer)  
CCLK  
(OUTPUT)  
DIN  
DOUT  
(OUTPUT)  
X8256  
Figure 2: Master Serial Mode. The one-time-programmable Serial Configuration PROM supports automatic loading of  
configuration programs. Multiple devices can be cascaded to support additional FPGA. An early D/P inhibits the  
PROM data output one CCLK cycle before the FPGA I/Os become active.  
5-4  
December 10, 1997 (Version 1.1)  
 
Standby Mode  
Programming  
The PROM enters a low-power standby mode whenever  
CE is asserted High. The output remains in a high imped-  
ance state regardless of the state of the OE input.  
The devices can be programmed on programmers supplied  
by Xilinx or qualified third-party vendors. The user must  
ensure that the appropriate programming algorithm and the  
latest version of the programmer software are used. The  
wrong choice can permanently damage the device.  
Table 1: Truth Table for XC1700 Control Inputs  
Control Inputs  
Outputs  
Internal Address  
RESET  
Inactive  
CE  
Low  
DATA  
active  
3-state  
3-state  
3-state  
3-state  
CEO  
High  
Low  
High  
High  
High  
Icc  
active  
reduced  
active  
if address < TC: increment  
if address > TC: don’t change  
Held reset  
Active  
Inactive  
Active  
Low  
High  
High  
Not changing  
standby  
standby  
Held reset  
Notes: 1. The XC1700 RESET input has programmable polarity  
2. TC = Terminal Count = highest address value. TC+1 = address 0.  
IMPORTANT: Always tie the VPP pin to VCC in your application. Never leave VPP floating.  
December 10, 1997 (Version 1.1)  
5-5  
XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Configuration PROMs  
XC1701  
Absolute Maximum Ratings  
Symbol  
Description  
Supply voltage relative to GND  
Units  
V
VCC  
VPP  
VIN  
-0.5 to +7.0  
-0.5 to +12.5  
-0.5 to VCC +0.5  
-0.5 to VCC +0.5  
-65 to +150  
+260  
Supply voltage relative to GND  
V
Input voltage relative to GND  
V
VTS  
Voltage applied to 3-state output  
Storage temperature (ambient)  
V
TSTG  
TSOL  
°C  
°C  
Maximum soldering temperature (10 s @ 1/16 in.)  
Note:  
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are  
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under  
Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may  
affect device reliability.  
Operating Conditions  
Symbol  
Description  
Commercial  
Industrial  
Min  
4.75  
4.50  
4.50  
Max  
5.25  
5.50  
5.50  
Units  
VCC  
Supply voltage relative to GND 0°C to +70°C junction  
Supply voltage relative to GND -40°C to +85°C junction  
Supply voltage relative to GND -55°C to +125°C case  
V
V
V
Military  
DC Characteristics Over Operating Condition  
Symbol  
VIH  
Description  
Min  
Max  
Units  
V
High-level input voltage  
Low-level input voltage  
2.0  
0
VCC  
0.8  
VIL  
V
VOH  
VOL  
VOH  
VOL  
ICCA  
ICCS  
IL  
High-level output voltage (IOH = -4 mA)  
Low-level output voltage (IOL = +4 mA)  
High-level output voltage (IOH = -4 mA)  
Low-level output voltage (IOL = +4 mA)  
Supply current, active mode  
Commercial  
Industrial  
3.86  
V
0.32  
V
3.76  
V
0.37  
10.0  
50.0  
10.0  
V
mA  
µA  
µA  
Supply current, standby mode  
Input or output leakage current  
-10.0  
Note: During normal read operation V must be connected to V  
PP  
CC  
5-6  
December 10, 1997 (Version 1.1)  
XC1701L/XC17512L  
Absolute Maximum Ratings  
Symbol  
Description  
Units  
V
VCC  
VPP  
VIN  
Supply voltage relative to GND  
Supply voltage relative to GND  
-0.5 to +6.0  
-0.5 to +12.5  
-0.5 to VCC +0.5  
-0.5 to VCC +0.5  
-65 to +150  
+260  
V
Input voltage with respect to GND  
Voltage applied to 3-state output  
V
VTS  
V
TSTG  
TSOL  
Storage temperature (ambient)  
°C  
°C  
Maximum soldering temperature (10 s @ 1/16 in.)  
Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress  
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating  
Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device  
reliability.  
Operating Conditions  
Symbol  
Description  
Min  
Max  
Units  
VCC  
Commercial  
Supply voltage relative to GND 0°C to +70°C junction  
3.0  
3.6  
V
DC Characteristics Over Operating Condition  
Symbol  
VIH  
Description  
Min  
Max  
Units  
V
High-level input voltage  
Low-level input voltage  
2.0  
0
VCC  
0.8  
VIL  
V
VOH  
VOL  
ICCA  
ICCS  
IL  
High-level output voltage (IOH = -4 mA)  
Low-level output voltage (IOL = +4 mA)  
Supply current, active mode  
2.4  
V
0.4  
5.0  
V
mA  
µA  
µA  
Supply current, standby mode  
50.0  
10.0  
Input or output leakage current  
-10.0  
Note: During normal read operation V must be connected to V  
PP  
CC  
December 10, 1997 (Version 1.1)  
5-7  
XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Configuration PROMs  
AC Characteristics Over Operating Condition  
CE  
9
10  
9
T
T
T
HCE  
SCE  
SCE  
RESET/OE  
T
11  
HOE  
T
8
LC  
7
T
HC  
6
T
CYC  
CLK  
3
4
T
OE  
1
5
T
DF  
T
T
CAC  
OH  
T
2
CE  
DATA  
4
T
OH  
X2634  
XC1701L  
XC17512L  
XC1701  
Min Max  
Symbol  
Description  
Units  
Min  
Max  
30  
1
2
3
4
5
6
7
8
9
TOE  
TCE  
TCAC  
TOH  
TDF  
TCYC  
TLC  
THC  
TSCE  
THCE  
THOE  
OE to Data Delay  
CE to Data Delay  
CLK to Data Delay  
Data Hold From CE, OE, or CLK  
CE or OE to Data Float Delay2  
Clock Periods  
CLK Low Time3  
CLK High Time3  
CE Setup Time to CLK (to guarantee proper counting)  
CE Hold Time to CLK (to guarantee proper counting)  
OE Hold Time (guarantees counters are reset)  
25  
45  
45  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
60  
60  
0
0
50  
50  
67  
20  
20  
20  
0
100  
25  
25  
25  
0
10  
11  
20  
25  
Notes: 1. AC test load = 50 pF  
2. Float delays are measured with minimum tester ac load and maximum dc load.  
3. Guaranteed by design, not tested.  
4. All AC parameters are measured with V = 0.0 V and V = 3.0 V.  
IL  
IH  
5-8  
December 10, 1997 (Version 1.1)  
AC Characteristics Over Operating Condition (continued)  
RESET/OE  
CE  
CLK  
T
12  
CDF  
Last Bit  
First Bit  
DATA  
CEO  
T
13  
T
OOE  
OCK  
15  
T
T
OCE  
14  
14  
OCE  
X3183  
XC1701L  
XC17512L  
XC1701  
Symbol  
Description  
CLK to Data Float Delay2  
CLK to CEO Delay  
CE to CEO Delay  
Units  
Min  
Max  
50  
Min Max  
12 TCDF  
13 TOCK  
14 TOCE  
15 TOOE  
50  
30  
35  
30  
ns  
ns  
ns  
ns  
30  
35  
30  
RESET/OE to CEO Delay  
Notes: 1. AC test load = 50 pF  
2. Float delays are measured with minimum tester ac load and maximum dc load.  
3. Guaranteed by design, not tested.  
4. All AC parameters are measured with V = 0.0 V and V = 3.0 V.  
IL  
IH  
December 10, 1997 (Version 1.1)  
5-9  
XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Configuration PROMs  
Ordering Information  
XC1701L PC20 C  
Device Number  
Operating Range/Processing  
XC1701L  
C = Commercial (0° to +70°C)  
XC1701  
XC17512L  
I
= Industrial (–40° to +85°C)  
Package Type  
PD8 = 8-Pin Plastic DIP  
SO20 = 20-Pin Plastic Small-Outline Package  
PC20 = 20-Pin Plastic Leaded Chip Carrier  
Marking Information  
Due to the small size of the serial PROM package, the complete ordering part number cannot be marked on the package.  
The XC prefix is deleted and the package code is simplified. Device marking is as follows.  
1701L  
P
C
Device Number  
Operating Range/Processing  
XC1701L  
XC1701  
XC17512L  
C = Commercial (0° to +70°C)  
Package Type  
I
= Industrial (–40° to +85°C)  
P
S
J
= 8-Pin Plastic DIP  
= 20-Pin Plastic Small-Outline Package  
= 20-Pin Plastic Leaded Chip Carrier  
5-10  
December 10, 1997 (Version 1.1)  

相关型号:

XC1701L-PD8C

1MX1 CONFIGURATION MEMORY, PDIP8, PLASTIC, DIP-8
ROCHESTER

XC1701L-SO20C

1MX1 CONFIGURATION MEMORY, PDSO20, PLASTIC, SOIC-20
XILINX

XC1701L-SO20C

1MX1 CONFIGURATION MEMORY, PDSO20, PLASTIC, SOIC-20
ROCHESTER

XC1701LPC20C

Configuration PROMs
XILINX

XC1701LPC20I

Configuration PROMs
XILINX

XC1701LPCG20C

Configuration PROMs
XILINX

XC1701LPCG20I

Configuration PROMs
XILINX

XC1701LPD8C

Configuration PROMs
XILINX

XC1701LPD8I

Configuration PROMs
XILINX

XC1701LPDG8C

Configuration PROMs
XILINX

XC1701LPDG8I

Configuration PROMs
XILINX

XC1701LSO20C

Configuration PROMs
XILINX