XC17256EDD8B [XILINX]
Configuration Memory, 256KX1, Serial, CMOS, CDIP8, CERAMIC, DIP-8;
| 型号： | XC17256EDD8B |
| 厂家： | 
XILINX, INC |
| 描述： | Configuration Memory, 256KX1, Serial, CMOS, CDIP8, CERAMIC, DIP-8 CD |
| 文件： | 总11页 (文件大小：655K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
11
QPRO Family of XC1700E
Configuration PROMs
DS670 (v1.0) December 3, 2010
Product Specification
Features
Description
•
Configuration one-time programmable (OTP) read-only
memory designed to store configuration bitstreams of
Xilinx FPGA devices
The XC1700E QPRO™ family of configuration PROMs
provide an easy-to-use, cost-effective method for storing
Xilinx FPGA configuration bitstreams.
•
•
On-chip address counter, incremented by each rising
edge on the clock input
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising clock edge, data appears on the PROM
Simple interface to the FPGA requires only one user
I/O pin
DATA output pin that is connected to the FPGA D pin. The
IN
FPGA generates the appropriate number of clock pulses to
complete the configuration. Once configured, it disables the
PROM. When the FPGA is in Slave Serial mode, the PROM
and the FPGA must both be clocked by an incoming signal.
•
•
Cascadable for storing longer or multiple bitstreams
Programmable reset polarity (active High or active
Low) for compatibility with different FPGA solutions
•
•
•
Low-power CMOS EPROM process
Available in 5V version only
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family.
Programming support by leading programmer
manufacturers.
•
Design support using the Xilinx Alliance and
Foundation series software packages
For device programming, either the Xilinx Alliance™ or the
Foundation™ series development systems compiles the
FPGA design file into a standard HEX format which is then
transferred to most commercial PROM programmers.
X-Ref Target - Figure 1
VCC
VPP
GND
CEO
CE
RESET/OE
or
OE/RESET
Address Counter
CLK
TC
EPROM
Cell
OE
Output
DATA
Matrix
DS670_01_112910
Figure 1: Simplified Block Diagram (Does Not Show Programming Circuit)
© Copyright 2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. All other trademarks are the property of their respective owners.
DS670 (v1.0) December 3, 2010
www.xilinx.com
Product Specification
1
QPRO Family of XC1700E Configuration PROMs
Pin Description
DATA
Data output, 3-stated when either CE or OE are inactive. During programming, the DATA pin is I/O.
Note: OE can be programmed to be either active High or active Low.
CLK
Each rising edge on the CLK input increments the internal address counter, if both CE and OE are active.
RESET/OE
When High, this input holds the address counter reset and 3-states the DATA output. The polarity of this input pin is
programmable as either RESET/OE or OE/RESET. To avoid confusion, this document describes the pin as RESET/OE,
although the opposite polarity is possible on all devices. When RESET is active, the address counter is held at zero, and the
DATA output is put in a high-impedance state. The polarity of this input is programmable. The default is active High RESET,
but the preferred option is active Low RESET, because it can be driven by the FPGA’s INIT pin.
The polarity of this pin is controlled in the programmer interface. This input pin is easily inverted using the Xilinx HW-130
programmer software. Third-party programmers have different methods to invert this pin.
CE
When High, this pin disables the internal address counter, 3-states the DATA output, and forces the device into low-I
standby mode.
CC
CEO
Chip enable output, to be connected to the CE input of the next PROM in the daisy chain. This output is Low when the CE
and OE inputs are both active AND the internal address counter has been incremented beyond its terminal count (TC) value.
In other words: when the PROM has been read, CEO will follow CE as long as OE is active. When OE goes inactive, CEO
stays High until the PROM is reset.
Note: OE can be programmed to be either active High or active Low.
VPP
Programming voltage. No overshoot above the specified maximum voltage is permitted on this pin. For normal read
operation, this pin must be connected to V . Failure to do so can lead to unpredictable, temperature-dependent operation
CC
and severe problems. Do not leave V floating!
PP
VCC and GND
V
is positive supply pin and GND is ground pin.
CC
DS670 (v1.0) December 3, 2010
www.xilinx.com
Product Specification
2
QPRO Family of XC1700E Configuration PROMs
PROM Pinouts
Table 1: PROM Pinouts
Pin Name
Pin Number
DATA
1
2
3
4
5
6
7
8
CLK
RESET/OE (OE/RESET)
CE
GND
CEO
VPP
VCC
Capacity
Table 2: Capacity
Devices
Configuration Bits
XC1765E
65,536
XC17256E
262,144
Number of Configuration Bits, Including Header, for Xilinx FPGAs and Compatible PROMs
Table 3: Number of Configuration Bits, Including Header, for Xilinx FPGAs and Compatible PROMs
Device
Configuration Bits
14,819 to 94,984
95,008 to 247,968
95,008
PROM
XC1765E to XC17256E
XC17256E
XC3000/A series
XC4000 series
XQ4005E
XC17256E
XQ4010E
178,144
XC17256E
XQ4013E
247,968
XC17256E
Controlling PROMs
Connecting the FPGA device with the PROM.
•
•
•
•
The DATA output(s) of the PROM(s) drives the D input of the lead FPGA device.
IN
The Master FPGA CCLK output drives the CLK input(s) of the PROM(s).
The CEO output of a PROM drives the CE input of the next PROM in a daisy chain (if any).
The RESET/OE input of all PROMs is best driven by the INIT output of the lead FPGA device. This connection assures
that the PROM address counter is reset before the start of any reconfiguration, even when a reconfiguration is initiated
by a V glitch. Other methods—such as driving RESET/OE from LDC or system reset—assume the PROM internal
CC
power-on-reset is always in step with the FPGA’s internal power-on-reset. This might not be a safe assumption.
•
•
The PROM CE input can be driven from either the LDC or DONE pins. Using LDC avoids potential contention on the
D
pin.
IN
The CE input of the lead (or only) PROM is driven by the DONE output of the lead FPGA device, provided that DONE
is not permanently grounded. Otherwise, LDC can be used to drive CE, but must then be unconditionally High during
user operation. CE can also be permanently tied Low, but this keeps the DATA output active and causes an
unnecessary supply current of 10 mA maximum.
DS670 (v1.0) December 3, 2010
www.xilinx.com
Product Specification
3
QPRO Family of XC1700E Configuration PROMs
FPGA Master Serial Mode Summary
The I/O and logic functions of the configurable logic block (CLB) and their associated interconnections are established by a
configuration program. The program is loaded either automatically upon power up, or on command, depending on the state
of the three FPGA mode pins. In Master Serial mode, the FPGA automatically loads the configuration program from an
external memory. The Xilinx PROMs have been designed for compatibility with the Master Serial mode.
Upon power-up or reconfiguration, an FPGA enters the Master Serial mode whenever all three of the FPGA mode-select
pins are Low (M0=0, M1=0, M2=0). Data is read from the PROM sequentially on a single data line. Synchronization is
provided by the rising edge of the temporary signal CCLK, which is generated during configuration.
Master Serial Mode provides a simple configuration interface. Only a serial data line and two control lines are required to
configure an FPGA. Data from the PROM is read sequentially, accessed via the internal address and bit counters which are
incremented on every valid rising edge of CCLK.
If the user-programmable, dual-function D pin on the FPGA is used only for configuration, it must still be held at a defined
IN
level during normal operation. Xilinx FPGAs take care of this automatically with an on-chip default pull-up resistor.
Programming the FPGA With Counters Unchanged Upon Completion
When multiple FPGA-configurations for a single FPGA are stored in a PROM, the OE pin should be tied Low. Upon
power-up, the internal address counters are reset and configuration begins with the first program stored in memory. Since
the OE pin is held Low, the address counters are left unchanged after configuration is complete. Therefore, to reprogram the
FPGA with another program, the DONE line is pulled Low and configuration begins at the last value of the address counters.
This method fails if a user applies RESET during the FPGA configuration process. The FPGA aborts the configuration and
then restarts a new configuration, as intended, but the PROM does not reset its address counter, since it never saw a High
level on its OE input. The new configuration, therefore, reads the remaining data in the PROM and interprets it as preamble,
24
length count etc. Since the FPGA is the master, it issues the necessary number of CCLK pulses, up to 16 million (2 ) and
DONE goes High. However, the FPGA configuration will be completely wrong, with potential contentions inside the FPGA
and on its output pins. This method must, therefore, never be used when there is any chance of external reset during
configuration.
Cascading Configuration PROMs
For multiple FPGAs configured as a daisy-chain, or for future FPGAs requiring larger configuration memories, cascaded
PROMs provide additional memory. After the last bit from the first PROM is read, the next clock signal to the PROM asserts
its CEO output Low and disables its DATA line. The second PROM recognizes the Low level on its CE input and enables its
DATA output. See Figure 2.
After configuration is complete, the address counters of all cascaded PROMs are reset if the FPGA RESET pin goes Low,
assuming the PROM reset polarity option has been inverted.
To reprogram the FPGA with another program, the DONE line goes Low and configuration begins where the address
counters had stopped. In this case, avoid contention between DATA and the configured I/O use of D .
IN
DS670 (v1.0) December 3, 2010
www.xilinx.com
Product Specification
4
QPRO Family of XC1700E Configuration PROMs
X-Ref Target - Figure 2
V
CC
D
OUT
OPTIONAL
Daisy-chained
FPGAs with
Different
configurations
OPTIONAL
FPGA
Slave FPGAs
with Identical
Configurations
(1)
MODES
VCC
3.3V
V
V
PP
CC
Cascaded
Serial
Memory
DATA
CLK
DATA
CLK
D
IN
PROM
RESET
RESET
CCLK
DONE
INIT
CE
CEO
CE
OE/RESET
OE/RESET
CCLK
(Output)
D
IN
D
OUT
(Output)
Notes:
1. For mode pin connections, refer to the appropriate FPGA data sheet.
2. The one-time-programmable PROM supports automatic loading of configuration programs.
3. Multiple devices can be cascaded to support additional FPGAs.
4. An early DONE inhibits the PROM data output one CCLK cycle before the FPGA I/Os become active.
ds670_02_120210
Figure 2: Master Serial Mode
DS670 (v1.0) December 3, 2010
www.xilinx.com
Product Specification
5
QPRO Family of XC1700E Configuration PROMs
Standby Mode
The PROM enters a low-power standby mode whenever CE is asserted High. The output remains in a high impedance state
regardless of the state of the OE input.
Programming
The devices can be programmed on programmers supplied by Xilinx or qualified third-party vendors. The user must ensure
that the appropriate programming algorithm and the latest version of the programmer software are used. The wrong choice
can permanently damage the device.
Table 4: Truth Table for XC1700 Control Inputs
Control Inputs
Outputs
CEO
Internal Address
RESET(1)
CE
DATA
ICC
If address TC: increment
Active
High-Z
High
Low
Active
Reduced
Inactive
Low
If address > TC: don’t change(2)
Held reset
Active
Inactive
Active
Low
High
High
High-Z
High-Z(3)
High-Z(3)
High
High
High
Active
Not changing
Standby
Standby
Held reset
Notes:
1. The XC1700 RESET input has programmable polarity
2. TC = Terminal Count = highest address value with valid data.
3. Pull DATA pin to GND or V to meet I
standby current.
CCS
CC
Note: Always tie the VPP pin to VCC in your application. Never leave VPP floating.
DS670 (v1.0) December 3, 2010
www.xilinx.com
Product Specification
6
QPRO Family of XC1700E Configuration PROMs
XC1765E and XC17256E
Absolute Maximum Ratings
Table 5: Absolute Maximum Ratings
Symbol
Description
Range
–0.5 to +7.0
–0.5 to +12.5
–0.5 to VCC + 0.5
–0.5 to VCC + 0.5
–65 to +150
+125
Units
V
VCC
VPP
VIN
Supply voltage relative to GND
Supply voltage relative to GND
Input voltage relative to GND
Voltage applied to High-Z output
Storage temperature (ambient)
V
V
VTS
TSTG
Tj
V
°C
°C
Junction temperature (10s @ 1/16 in.)
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Operating Conditions
Table 6: Operating Conditions
Symbol
Description
Min
Max
Units
(1)
VCC
Supply voltage relative to GND (TC = –55°C to +125°C)
4.50
5.50
V
Notes:
1. During normal read operation VPP must be connected to VCC
DC Characteristics Over Operating Condition
Table 7: DC Characteristics Over Operating Condition
Symbol
VIH
Description
Min
2.0
0
Max
VCC
0.8
–
Units
V
High-level input voltage
Low-level input voltage
VIL
V
VOH
VOL
High-level output voltage (IOH = –4 mA)
Low-level output voltage (IOL = +4 mA)
Supply current, active mode (at maximum frequency)
Supply current, standby mode
3.7
–
V
0.4
10
V
ICCA
–
mA
µA
mA
µA
pF
pF
XC17256E
XC1765E
–
50(1)
1.5(1)
10
ICCS
–
IL
Input or output leakage current
–10
–
CIN
Input capacitance (VIN = GND, f = 1.0 MHz) sample tested
Output capacitance (VIN = GND, f = 1.0 MHz) sample tested
10
COUT
–
10
Notes:
1.
I
standby current is specified for DATA pin that is pulled to V or GND.
CC
CCS
DS670 (v1.0) December 3, 2010
www.xilinx.com
Product Specification
7
QPRO Family of XC1700E Configuration PROMs
AC Characteristics Over Operating Condition
X-Ref Target - Figure 3
CE
T
T
T
HCE
SCE
SCE
RESET/OE
T
HOE
T
LC
T
HC
T
CYC
CLK
T
T
DF
OE
T
T
CAC
OH
T
CE
DATA
T
OH
DS070_03_111010
Figure 3: AC Characteristics Over Operating Condition
(1)(2)
Table 8: AC Characteristics Over Operating Condition
XC1765E
XC17256E
Min Max
25
Symbol
Description
Units
Min
Max
45
60
150
–
TOE
TCE
OE to data delay
CE to data delay
CLK to data delay
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
–
45
50
–
TCAC
TOH
–
Data hold from CE, OE, or CLK(3)
CE or OE to data float delay(3)(4)
Clock periods
0
0
TDF
–
50
–
–
50
–
TCYC
TLC
200
100
100
25
0
80
20
20
20
0
CLK Low time(3)
–
–
THC
CLK High time(3)
–
–
TSCE
THCE
THOE
CE setup time to CLK (to guarantee proper counting)
CE hold time to CLK (to guarantee proper counting)
OE hold time (guarantees counters are reset)
–
–
–
–
100
–
20
–
Notes:
1. AC test load = 50 pF
2. All AC parameters are measured with V = 0.0V and V = 3.0V.
IL
IH
3. Guaranteed by design, not tested.
4. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels.
DS670 (v1.0) December 3, 2010
www.xilinx.com
Product Specification
8
QPRO Family of XC1700E Configuration PROMs
AC Characteristics Over Operating Condition When Cascading
X-Ref Target - Figure 4
RESET/OE
CE
CLK
TCDF
DATA
(First PROM)
Last
Bit
First
Bit
TOCK
TOOE
TOCE
TOCE
CEO
(First PROM)
CE
(Cascaded
PROM)
TCE
TCE
DATA
(Cascaded
PROM)
First
Bit
Last
Bit
n –1
n
n
n +1
DS670_04_120210
Figure 4: AC Characteristics Over Operating Condition When Cascading
(1)(2)
Table 9: AC Characteristics Over Operating Condition When Cascading
XC1765E
XC17256E
Symbol
Description
Units
Min
Max
50
Min
Max
TCDF
TOCK
TOCE
TOOE
CLK to data float delay(3)(4)
CLK to CEO delay(3)
–
–
–
–
–
–
–
–
50
30
35
30
ns
ns
ns
ns
65
CE to CEO delay(3)
45
RESET/OE to CEO delay(3)
40
Notes:
1. AC test load = 50 pF
2. All AC parameters are measured with V = 0.0V and V = 3.0V.
IL
IH
3. Guaranteed by design, not tested.
4. Float delays are measured with 5 pF AC loads. Transition is measured at 200mV from steady state active levels.
DS670 (v1.0) December 3, 2010
www.xilinx.com
Product Specification
9
QPRO Family of XC1700E Configuration PROMs
Ordering Information
X-Ref Target - Figure 5
XC17256E DD8 M
Device Number
XC1765E
XC17256E
Operating Range/Processing
M = Military (TC = –55° to +125°C)
B = Military (TC = –55° to +125°C)
Package Type
DD8 = 8-pin Ceramic DIP
ds670_05_120210
Figure 5: Ordering Information
Valid Ordering Combinations
Table 10: Valid Ordering Combinations
XC17256EDD8M
XC17256EDD8B
XC1765EDD8M
XC1765EDD8B
Marking Information
Due to the small size of the PROM package, the complete ordering part number cannot be marked on the package. The XC
prefix is deleted and the package code is simplified. Devices are marked as shown in Figure 6.
X-Ref Target - Figure 6
17256E
D
M
Device Number
XC1765E
XC17256E
Operating Range/Processing
M = Military (TC = –55° to +125°C)
B = Military (TC = –55° to +125°C)
Package Type
D = 8-pin Ceramic DIP
ds670_06_120310
Figure 6: Marking Information
Revision History
The following table shows the revision history for this document.
Date
Version
Revisions
12/03/10
1.0
Initial Xilinx release.
DS670 (v1.0) December 3, 2010
www.xilinx.com
Product Specification
10
QPRO Family of XC1700E Configuration PROMs
Notice of Disclaimer
THE XILINX HARDWARE DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND CONDITIONS OF
THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES
NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS
STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT
DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH
AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS
OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). USE OF
PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND
REGULATIONS.
CRITICAL APPLICATIONS DISCLAIMER
XILINX PRODUCTS (INCLUDING HARDWARE, SOFTWARE AND/OR IP CORES) ARE NOT DESIGNED OR INTENDED TO BE
FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS IN LIFE-SUPPORT OR
SAFETY DEVICES OR SYSTEMS, CLASS III MEDICAL DEVICES, NUCLEAR FACILITIES, APPLICATIONS RELATED TO THE
DEPLOYMENT OF AIRBAGS, OR ANY OTHER APPLICATIONS THAT COULD LEAD TO DEATH, PERSONAL INJURY OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE (INDIVIDUALLY AND COLLECTIVELY, “CRITICAL APPLICATIONS”). FURTHERMORE,
XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN ANY APPLICATIONS THAT AFFECT CONTROL OF A
VEHICLE OR AIRCRAFT, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF
SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE
OPERATOR. CUSTOMER AGREES, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE XILINX
PRODUCTS, TO THOROUGHLY TEST THE SAME FOR SAFETY PURPOSES. TO THE MAXIMUM EXTENT PERMITTED BY
APPLICABLE LAW, CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN CRITICAL
APPLICATIONS.
DS670 (v1.0) December 3, 2010
www.xilinx.com
Product Specification
11
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