XC17V02V08I [XILINX]
XC17V00 Series Configuration PROM; XC17V00系列配置PROM
| 型号： | XC17V02V08I |
| 厂家： | 
XILINX, INC |
| 描述： | XC17V00 Series Configuration PROM |
| 文件： | 总12页 (文件大小：114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0
R
XC17V00 Series Configuration
PROM
0
8
DS073 (v1.0) July 26, 2000
Advance Product Specification
Features
Description
•
One-time programmable (OTP) read-only memory
designed to store configuration bitstreams of Xilinx
FPGA devices
Xilinx introduces the high-density XC17V00 family of config-
uration PROMs which provide an easy-to-use, cost-effec-
tive method for storing large Xilinx FPGA configuration
bitstreams. Initial devices in the 3.3V family are available in
16 Mb, 8 Mb, 4 Mb, 2 Mb, and 1 Mb densities.
•
Simple interface to the FPGA; configurable to use a
one user I/O pin
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising clock edge, data appears on the PROM
DATA output pin that is connected to the FPGA DIN pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. Once configured, it disables the
PROM. When the FPGA is in Slave Serial mode, the PROM
and the FPGA must both be clocked by an incoming signal.
•
•
Cascadable for storing longer or multiple bitstreams
Programmable reset polarity (active High or active
Low) for compatibility with different FPGA solutions
•
•
•
•
Supports fast configuration
Low-power CMOS Floating Gate process
3.3V supply voltage
Available in compact plastic packages: VQ44, PC44,
PC20, VO8, and SO20
When the FPGA is in SelectMAP mode, an external oscilla-
tor will generate the configuration clock that drives the
PROM and the FPGA. After the rising CCLK edge, data are
available on the PROMs DATA (D0-D7) pins. The data will
be clocked into the FPGA on the following rising edge of the
CCLK. SelectMAP does not utilize a Length Count, so a
free-running oscillator may be used. See Figure 3.
•
•
•
Programming support by leading programmer
manufacturers.
Design support using the Xilinx Alliance and
Foundation series software packages.
Dual configuration modes for the XC17V16 and
XC17V08
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family.
-
-
Serial slow/fast configuration (up to 33 MHz)
Parallel (up to 264 MHz)
•
Guaranteed 20 year life data retention
For device programming, either the Xilinx Alliance or Foun-
dation series development system compiles the FPGA
design file into a standard Hex format, which is then trans-
ferred to most commercial PROM programmers.
© 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS073 (v1.0) July 26, 2000
www.xilinx.com
1
Advance Product Specification
1-800-255-7778
R
XC17V00 Series Configuration PROM
V
V
PP
GND
CC
RESET/
CEO
CE
OE
or
OE/
RESET
Address Counter
CLK
TC
EPROM
Cell
Matrix
OE
Output
DATA
DS073_01_072600
Figure 1: Simplified Block Diagram for XC17V04, XC17V02, and XC17V01 (does not show programming circuit)
V
V
PP
GND
CC
RESET/
OE
or
CEO
CE
OE/
RESET
Address Counter
CLK
TC
BUSY
EPROM
Cell
Matrix
OE
7
8
Output
D0 Data
(Serial or Parallel Mode)
7
D[1:7]
(SelectMAP Interface)
DS073_02_072600
Figure 2: Simplified Block Diagram for XC17V16 and XC17V08 (does not show programming circuit)
2
www.xilinx.com
DS073 (v1.0) July 26, 2000
1-800-255-7778
Advance Product Specification
R
XC17V00 Series Configuration PROM
BUSY (XC17V16 and XC17V08 only)
Pin Description
If BUSY pin is floating, the user must program the BUSY bit
which will cause BUSY pin to go Low internally. When
asserted High, output data are held and when BUSY pin
goes Low, data output will resume.
DATA[0:7]
Data output is in a high-impedance state when either CE or
OE are inactive. During programming, the D0 pin is I/O.
Note that OE can be programmed to be either active High or
active Low.
VPP
Note: XC17V04, XC17V02, and XC17V01 have serial output
only.
Programming voltage. No overshoot above the specified
max voltage is permitted on this pin. For normal read oper-
ation, this pin must be connected to V . Failure to do so
may lead to unpredictable, temperature-dependent opera-
tion and severe problems in circuit debugging. Do not leave
CC
CLK
Each rising edge on the CLK input increments the internal
address counter, if both CE and OE are active.
V
floating!
PP
RESET/OE
VCC and GND
When High, this input holds the address counter reset and
puts the DATA output in a high-impedance state. The polar-
ity of this input pin is programmable as either RESET/OE or
OE/RESET. To avoid confusion, this document describes
the pin as RESET/OE, although the opposite polarity is pos-
sible on all devices. When RESET is active, the address
counter is held at "0", and puts the DATA output in a
high-impedance state. The polarity of this input is program-
mable. The default is active High RESET, but the preferred
option is active Low RESET, because it can be driven by the
FPGAs INIT pin.
Positive supply and ground pins.
PROM Pinouts for XC17V16 and XC17V08
Pin Name
BUSY
44-pin VQFP
44-pin PLCC
24
40
29
42
27
9
30
2
D0
D1
D2
D3
D4
D5
D6
D7
CLK
35
4
The polarity of this pin is controlled in the programmer inter-
face. This input pin is easily inverted using the Xilinx
HW-130 Programmer. Third-party programmers have differ-
ent methods to invert this pin.
33
15
31
20
25
5
25
14
19
43
13
CE
When High, this pin disables the internal address counter,
puts the DATA output in a high-impedance state, and forces
the device into low-I standby mode.
CC
RESET/OE
19
CEO
(OE/RESET)
Chip Enable output, to be connected to the CE input of the
next PROM in the daisy chain. This output is Low when the
CE and OE inputs are both active AND the internal address
counter has been incremented beyond its Terminal Count
(TC) value. In other words: when the PROM has been read,
CEO will follow CE as long as OE is active. When OE goes
inactive, CEO stays High until the PROM is reset. Note that
OE can be programmed to be either active High or active
Low.
CE
15
21
GND
CEO
6, 18, 28, 27, 41 3, 12, 24, 34, 43
21
35
27
41
V
V
PP
CC
8, 16, 17, 26, 36,
38
14, 22, 23, 32,
42, 44
Capacity
Devices
Configuration Bits
XC17V16
XC17V08
16,777,216
8,388,608
DS073 (v1.0) July 26, 2000
Advance Product Specification
www.xilinx.com
1-800-255-7778
3
R
XC17V00 Series Configuration PROM
PROM Pinouts for XC17V04, XC17V02, and
XC17V01
Xilinx FPGAs and Compatible PROMs
Configuration
Device
Bits
PROM
8-pin 20-pin 20-pin 44-pin 44-pin
XCV600E
XCV812E
XCV1000E
XCV1600E
XCV2000E
XCV2600E
XCV3200E
3,961,632
6,519,648
6,587,520
8,308,992
10,159,648
12,922,336
16,283,712
XC17V04
XC17V08
XC17V08
XC17V08
XC17V16
XC17V16
XC17V16
Pin Name VOIC SOIC PLCC VQFP PLCC
DATA
CLK
1
2
3
1
3
8
2
4
6
40
43
13
2
5
RESET/OE
19
(OE/RESET)
CE
4
5
6
7
8
10
11
13
18
20
8
15
18, 41
21
21
24, 3
27
GND
CEO
10
14
17
20
Notes:
1. The suggested PROM is determined by compatibility with the
higher configuration frequency of the Xilinx FPGA CCLK.
V
V
35
41
PP
CC
38
44
Controlling PROMs
Capacity
Connecting the FPGA device with the PROM.
•
The DATA output(s) of the of the PROM(s) drives the
input of the lead FPGA device.
Devices
Configuration Bits
4,194,304
D
IN
XC17V04
XC17V02
XC17V01
•
•
•
The Master FPGA CCLK output drives the CLK input(s)
of the PROM(s).
2,701,312
The CEO output of a PROM drives the CE input of the
next PROM in a daisy chain (if any).
1,679,360
The RESET/OE input of all PROMs is best driven by
the INIT output of the lead FPGA device. This
connection assures that the PROM address counter is
reset before the start of any (re)configuration, even
Xilinx FPGAs and Compatible PROMs
Configuration
Device
XCV50
Bits
PROM
when a reconfiguration is initiated by a V
glitch.
CC
559,200
XC17V01
XC17V01
XC17V01
XC17V01
XC17V02
XC17V02
XC17V04
XC17V08
XC17V08
XC17V01
XC17V01
XC17V01
XC17V02
XC17V02
XC17V04
Other methods—such as driving RESET/OE from LDC
or system reset—assume the PROM internal
power-on-reset is always in step with the FPGA’s
internal power-on-reset. This may not be a safe
assumption.
XCV100
XCV150
XCV200
XCV300
XCV400
XCV600
XCV800
XCV1000
XCV50E
XCV100E
XCV200E
XCV300E
XCV400E
XCV405E
781,216
1,040,096
1,335,840
1,751,808
2,546,048
3,607,968
4,715,616
6,127,744
630,048
•
•
The PROM CE input can be driven from either the LDC
or DONE pins. Using LDC avoids potential contention
on the D pin.
IN
The CE input of the lead (or only) PROM is driven by
the DONE output of the lead FPGA device, provided
that DONE is not permanently grounded. Otherwise,
LDC can be used to drive CE, but must then be
unconditionally High during user operation. CE can
also be permanently tied Low, but this keeps the DATA
output active and causes an unnecessary supply
current of 10 mA maximum.
863,840
1,442,106
1,875,648
2,693,440
3,340,400
•
SelectMAP mode is similar to Slave Serial mode. The
DATA is clocked out of the PROM one byte per CCLK
instead of one bit per CCLK cycle. See FPGA data
sheets for special configuration requirements.
4
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DS073 (v1.0) July 26, 2000
1-800-255-7778
Advance Product Specification
R
XC17V00 Series Configuration PROM
unchanged after configuration is complete. Therefore, to
reprogram the FPGA with another program, the DONE line
is pulled Low and configuration begins at the last value of
the address counters.
FPGA Master Serial Mode Summary
The I/O and logic functions of the Configurable Logic Block
(CLB) and their associated interconnections are estab-
lished by a configuration program. The program is loaded
either automatically upon power up, or on command,
depending on the state of the three FPGA mode pins. In
Master Serial mode, the FPGA automatically loads the con-
figuration program from an external memory. The Xilinx
PROMs have been designed for compatibility with the Mas-
ter Serial mode.
This method fails if a user applies RESET during the FPGA
configuration process. The FPGA aborts the configuration
and then restarts a new configuration, as intended, but the
PROM does not reset its address counter, since it never
saw a High level on its OE input. The new configuration,
therefore, reads the remaining data in the PROM and inter-
prets it as preamble, length count etc. Since the FPGA is
the master, it issues the necessary number of CCLK pulses,
Upon power-up or reconfiguration, an FPGA enters the
Master Serial mode whenever all three of the FPGA
mode-select pins are Low (M0=0, M1=0, M2=0). Data is
read from the PROM sequentially on a single data line. Syn-
chronization is provided by the rising edge of the temporary
signal CCLK, which is generated during configuration.
24
up to 16 million (2 ) and DONE goes High. However, the
FPGA configuration will be completely wrong, with potential
contentions inside the FPGA and on its output pins. This
method must, therefore, never be used when there is any
chance of external reset during configuration.
Master Serial Mode provides a simple configuration inter-
face. Only a serial data line and two control lines are
required to configure an FPGA. Data from the PROM is
read sequentially, accessed via the internal address and bit
counters which are incremented on every valid rising edge
of CCLK.
Cascading Configuration PROMs
For multiple FPGAs configured as a daisy-chain, or for
future FPGAs requiring larger configuration memories, cas-
caded PROMs provide additional memory. After the last bit
from the first PROM is read, the next clock signal to the
PROM asserts its CEO output Low and disables its DATA
line. The second PROM recognizes the Low level on its CE
input and enables its DATA output. See Figure 3.
If the user-programmable, dual-function DIN pin on the
FPGA is used only for configuration, it must still be held at a
defined level during normal operation. The Xilinx FPGA
families take care of this automatically with an on-chip
default pull-up resistor.
After configuration is complete, the address counters of all
cascaded PROMs are reset if the FPGA RESET pin goes
Low, assuming the PROM reset polarity option has been
inverted.
Programming the FPGA With Counters
Unchanged Upon Completion
To reprogram the FPGA with another program, the DONE
line goes Low and configuration begins where the address
counters had stopped. In this case, avoid contention
between DATA and the configured I/O use of DIN.
When multiple FPGA-configurations for a single FPGA are
stored in a PROM, the OE pin should be tied Low. Upon
power-up, the internal address counters are reset and con-
figuration begins with the first program stored in memory.
Since the OE pin is held Low, the address counters are left
DS073 (v1.0) July 26, 2000
Advance Product Specification
www.xilinx.com
1-800-255-7778
5
R
XC17V00 Series Configuration PROM
OPTIONAL
Daisy-chained
FPGAs with
different
DOUT
configurations
FPGA
OPTIONAL
V
CC
Slave FPGAs
with identical
configurations
4.7K
Modes*
Vcco
Vcc
V
CC
**
V
V
BUSY
DATA
CC CCO
DATA
DIN
BUSY
First
PROM
CCLK
Cascaded
PROM
CLK
CE
CLK
CE
CEO
DONE
INIT
OE/RESET
OE/RESET
PROGRAM
(Low Resets the Address Pointer)
*For Mode pin connections, refer to the appropriate FPGA data sheet.
**Virtex, Virtex-E is 300 ohms, all others are 4.7K.
Master Serial Mode
I/O*
I/O*
V
CC
V
CCO
CS
Modes***
WRITE
External Osc
3.3V
4.7K
1K
1K
VIRTEX
Select MAP
V
CC
V
CCO
V
CC
BUSY
XC17Vxx
BUSY
**
CLK
CCLK
8
CEO
D[0:7]
DONE
INIT
D[0:7]
CE
OE/RESET
*CS and WRITE must be pulled down to be used as I/O. One option is shown.
**Virtex, Virtex-E is 300 ohms, all others are 4.7K.
***For Mode pin connections, refer to the appropriate FPGA data sheet.
Virtex Select MAP Mode, XC17V16 and XC17V08 only.
DS073_03_072600
Figure 3: (a) Master Serial Mode (b) Virtex SelectMAP Mode
(dotted lines indicates optional connection)
6
www.xilinx.com
DS073 (v1.0) July 26, 2000
1-800-255-7778
Advance Product Specification
R
XC17V00 Series Configuration PROM
Standby Mode
Programming
The PROM enters a low-power standby mode whenever
CE is asserted High. The output remains in a high imped-
ance state regardless of the state of the OE input.
The devices can be programmed on programmers supplied
by Xilinx or qualified third-party vendors. The user must
ensure that the appropriate programming algorithm and the
latest version of the programmer software are used. The
wrong choice can permanently damage the device.
Table 1: Truth Table for XC17V00 Control Inputs
Control Inputs
Outputs
RESET
CE
Internal Address
DATA
CEO
I
CC
(1)
Inactive
Low
If address < TC : increment
Active
High-Z
High
Low
Active
Reduced
(1)
If address > TC : don’t change
Active
Inactive
Active
Low
High
High
Held reset
Not changing
Held reset
High-Z
High-Z
High-Z
High
High
High
Active
Standby
Standby
Notes:
1. The XC17V00 RESET input has programmable polarity
1. TC = Terminal Count = highest address value. TC + 1 = address 0.
DS073 (v1.0) July 26, 2000
Advance Product Specification
www.xilinx.com
1-800-255-7778
7
R
XC17V00 Series Configuration PROM
Absolute Maximum Ratings
Symbol
Description
Conditions
–0.5 to +7.0
–0.5 to +12.5
Units
V
V
Supply voltage relative to GND
CC
PP
V
Supply voltage relative to GND
V
V
Input voltage relative to GND
–0.5 to V +0.5
V
IN
CC
V
Voltage applied to High-Z output
Storage temperature (ambient)
–0.5 to V +0.5
V
TS
CC
T
–65 to +150
°C
°C
STG
SOL
T
Maximum soldering temperature (10s @ 1/16 in.)
+260
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Operating Conditions (3V Supply)
Symbol
Description
Supply voltage relative to GND (T = 0°C to +70°C)
Min
3.0
3.0
Max
3.6
Units
(1)
V
Commercial
Industrial
V
V
CC
A
Supply voltage relative to GND (T = –40°C to +85°C)
3.6
A
Notes:
1. During normal read operation VPP MUST be connect to V
CC.
DC Characteristics Over Operating Condition
Symbol
Description
Min
Max
Units
V
V
High-level input voltage
Low-level input voltage
2
0
V
CC
IH
V
0.8
-
V
IL
V
High-level output voltage (I = –3 mA)
2.4
-
V
OH
OH
V
Low-level output voltage (I = +3 mA)
0.4
100
V
OL
OL
I
I
I
I
Supply current, standby mode (at maximum frequency)
(XC17V16 and XC17V08 only)
-
mA
CCA
CCS
CCA
CCS
Supply current, standby mode
(XC17V16, XC17V08, XC17V04, XC17V02 only)
-
-
-
350
10
µA
mA
µA
Supply current, standby mode (at maximum frequency)
(XC17V04, XC17V02, and XC17V01 only)
Supply current, standby mode
50
(XC17V01 only)
I
Input or output leakage current
–10
10
10
10
µA
pF
pF
L
C
Input capacitance (V = GND, f = 1.0 MHz)
-
-
IN
IN
C
Output capacitance (V = GND, f = 1.0 MHz)
IN
OUT
8
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1-800-255-7778
DS073 (v1.0) July 26, 2000
Advance Product Specification
R
XC17V00 Series Configuration PROM
AC Characteristics Over Operating Condition for XC17V04, XC17V02, and
XC17V01
CE
T
T
T
HCE
SCE
SCE
RESET/OE
CLK
T
HOE
T
T
HC
LC
T
CYC
T
T
DF
OE
T
T
CAC
OH
T
CE
DATA
T
OH
DS073_04_072600
Symbol
Description
Min
Max
Units
ns
T
T
OE to data delay
CE to data delay
CLK to data delay
-
-
30
45
45
50
-
OE
CE
ns
T
-
ns
CAC
(2,3)
T
CE or OE to data float delay
Data hold from CE, OE, or CLK
Clock periods
-
ns
DF
OH
(3)
T
0
ns
T
67
25
25
25
0
-
ns
CYC
(3)
T
CLK Low time
-
ns
LC
(3)
T
CLK High time
-
ns
HC
T
T
CE setup time to CLK (to guarantee proper counting)
CE hold time to CLK (to guarantee proper counting)
OE hold time (guarantees counters are reset)
-
ns
SCE
HCE
HOE
-
ns
T
25
-
ns
Notes:
1. AC test load = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with V = 0.0V and V = 3.0V.
IL
IH
DS073 (v1.0) July 26, 2000
www.xilinx.com
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Advance Product Specification
1-800-255-7778
R
XC17V00 Series Configuration PROM
AC Characteristics Over Operating Condition for XC17V16 and XC17V08
CE
T
T
T
HCE
SCE
SCE
RESET/OE
CLK
T
HOE
T
T
HC
LC
T
CYC
T
T
DF
OE
T
T
CAC
OH
T
CE
DATA
T
T
SBUSY
OH
T
HBUSY
BUSY
DS073_05_072600
Symbol
Description
Min
Max
Units
ns
T
T
OE to data delay
CE to data delay
CLK to data delay
-
-
15
20
20
35
-
OE
CE
ns
(2)
T
-
ns
CAC
(3,4)
T
CE or OE to data float delay
Data hold from CE, OE, or CLK
Clock periods
-
ns
DF
(4)
T
0
ns
OH
T
67
25
25
25
0
-
ns
CYC
(4)
T
CLK Low time
-
ns
LC
(4)
T
CLK High time
-
ns
HC
T
T
CE setup time to CLK (to guarantee proper counting)
CE hold time to CLK (to guarantee proper counting)
OE hold time (guarantees counters are reset)
BUSY setup time
-
ns
SCE
HCE
HOE
-
ns
T
25
5
-
ns
T
T
-
ns
SBUSY
HBUSY
BUSY hold time
5
-
ns
T
V
reached normal supply voltage range to output valid
CC
100
-
ms
WKU
Notes:
1. AC test load = 50 pF.
2. When BUSY = 0.
3. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
4. Guaranteed by design, not tested.
5. All AC parameters are measured with V = 0.0V and V = 3.0V.
IL
IH
10
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DS073 (v1.0) July 26, 2000
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Advance Product Specification
R
XC17V00 Series Configuration PROM
AC Characteristics Over Operating Condition When Cascading
RESET/OE
CE
CLK
T
CDF
Last Bit
First Bit
DATA
CEO
T
T
OOE
OCK
T
OCE
T
OCE
DS073_06_062800
Symbol
Description
Min
Max
50
Units
ns
(2,3)
T
T
T
CLK to data float delay
-
-
-
-
CDF
OCK
OCE
OOE
(3)
CLK to CEO delay
30
ns
(3)
CE to CEO delay
RESET/OE to CEO delay
35
ns
(3)
T
30
ns
Notes:
1. AC test load = 50 pF
2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady
state active levels.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with V = 0.0V and V = 3.0V.
IL
IH
DS073 (v1.0) July 26, 2000
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Advance Product Specification
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R
XC17V00 Series Configuration PROM
Ordering Information
XC17V16 PC44 C
Device Number
Operating Range/Processing
C = Commercial (T = 0° to +70°C)
XC17V16
XC17V08
XC17V04
XC17V02
XC17V01
Package Type
A
I
= Industrial (T = –40° to +85°C)
A
VQ44 = 44-pin Plastic Quad Flat Package
PC44 = 44-pin Plastic Chip Carrier
V08 = 8-pin Plastic Small Outline Thin Package
PC20 = 20-pin Plastic Leaded Chip Carrier
SO20 = 20-pin Plastic Small Outline Package
Valid Ordering Combinations
XC17V16VQ44C
XC17V16PC44C
XC17V16VQ44I
XC17V16PC44I
XC17V08VQ44C
XC17V08PC44C
XC17V08VQ44I
XC17V08PC44I
XC17V04PC20C
XC17V04PC44C
XC17V04VQ44C
XC17V04PC20I
XC17V04PC44I
XC17V04VQ44I
XC17V02PC20C
XC17V02PC44C
XC17V02VQ44C
XC17V02PC20I
XC17V02PC44I
XC17V02VQ44I
XC17V01PC20C
XC17V01VO8C
XC17V01SO20C
XC17V01PC20I
XC17V01VO8I
XC17V01SO20I
Marking Information
Due to the small size of the commercial serial PROM packages, the complete ordering part number cannot be marked on
the package. The XC prefix is deleted and the package code is simplified. Device marking is as follows:
17V16 PC44 C
Device Number
Operating Range/Processing
C = Commercial (T = 0° to +70°C)
17V16
17V08
17V04
17V02
17V01
Package Type
A
I
= Industrial (T = –40° to +85°C)
A
VQ44 = 44-pin Plastic Quad Flat Package
PC44 = 44-pin Plastic Chip Carrier
V08 = 8-pin Plastic Small Outline Thin Package
PC20 = 20-pin Plastic Leaded Chip Carrier
SO20 = 20-pin Plastic Small Outline Package
Revision History
The following table shows the revision history for this document.
Date
Version
Revision
07/26/00
1.0
Initial Xilinx release.
12
www.xilinx.com
1-800-255-7778
DS073 (v1.0) July 26, 2000
Advance Product Specification
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