XC17V16VQG44C [XILINX]
Configuration Memory, 2MX8, Parallel/serial, CMOS, PQFP44, PLASTIC, QFP-44;型号: | XC17V16VQG44C |
厂家: | XILINX, INC |
描述: | Configuration Memory, 2MX8, Parallel/serial, CMOS, PQFP44, PLASTIC, QFP-44 内存集成电路 |
文件: | 总15页 (文件大小:416K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
0
R
XC17V00 Series Configuration PROMs
0
8
DS073 (v1.12) November 13, 2008
Product Specification
Features
•
One-time programmable (OTP) read-only memory
designed to store configuration bitstreams of
Xilinx FPGA devices
•
•
•
•
Available in compact plastic packages: VQ44, PC44,
PC20, VO8, and SO20
(1)
®
Programming support by leading programmer
manufacturers
•
•
•
Simple interface to the FPGA
®
Cascadable for storing longer or multiple bitstreams
Design support using the ISE Foundation™ and
ISE WebPACK™ software
Programmable reset polarity (active High or active
Low) for compatibility with different FPGA solutions
Dual configuration modes for the XC17V16 and
(1)
XC17V08 devices
•
•
•
Low-power CMOS floating-gate process
3.3V supply voltage
♦
♦
Serial slow/fast configuration (up to 20 Mb/s)
Parallel (up to 160 Mb/s at 20 MHz)
Guaranteed 20 year life data retention
Description
Xilinx introduces the high-density XC17V00 family of
configuration PROMs which provide an easy-to-use, cost-
effective method for storing large Xilinx FPGA configuration
bitstreams. Initial devices in the 3.3V family are available in
16 Mb, 8 Mb, 4 Mb, 2 Mb, and 1 Mb densities. See Figure 1
and Figure 2 for simplified block diagrams of the XC17V00
family.
(SelectMAP) configuration mode interface. When the FPGA
is in Master SelectMAP mode, the FPGA generates the
configuration clock that drives the PROM.
When the FPGA is in Slave SelectMAP mode, an external,
free-running oscillator generates the configuration clock
that drives the PROM and the FPGA. After the rising
configuration clock (CCLK) edge, data is available on the
PROMs DATA (D0-D7) pins. The data is clocked into the
FPGA on the following rising edge of the CCLK (Figure 3).
The XC17V00 PROM can configure a Xilinx FPGA using
the FPGA serial configuration mode interface. When the
FPGA is in Master Serial mode, it generates a configuration
clock that drives the PROM. A short access time after the
rising clock edge, data appears on the PROM DATA output
pin that is connected to the FPGA DIN pin. The FPGA
generates the appropriate number of clock pulses to
complete the configuration. Once configured, it disables the
PROM. When the FPGA is in Slave Serial mode, the PROM
and the FPGA must both be clocked by an incoming signal.
Multiple PROMs can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family.
For device programming, either the Xilinx ISE Foundation or
ISE WebPACK software compiles the FPGA design file into
a standard Hex format, which is then transferred to most
commercial PROM programmers.
(1)
The XC17V08 and XC17V16 PROM can optionally
configure a Xilinx FPGA using the FPGA Parallel
1. Specific part number and package combinations have been discontinued. Refer to XCN07010. Discontinued part number and package combinations
remain in this data sheet for reference.
© Copyright 2000–2008 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. All other trademarks are the property of their respective owners.
DS073 (v1.12) November 13, 2008
www.xilinx.com
Product Specification
1
R
XC17V00 Series Configuration PROMs
X-Ref Target - Figure 1
V
V
PP
GND
CC
RESET/
OE
or
CEO
CE
OE/
RESET
Address Counter
CLK
TC
EPROM
Cell
Matrix
OE
Output
DATA
DS073_01_072600
(1)
Figure 1: Simplified Block Diagram for XC17V04, XC17V02 , and XC17V01
(does not show programming circuit)
X-Ref Target - Figure 2
V
V
PP
GND
CC
RESET/
OE
or
CEO
CE
OE/
RESET
Address Counter
CLK
TC
BUSY
EPROM
Cell
Matrix
OE
7
8
Output
D0 Data
(Serial or Parallel Mode)
7
D[1:7]
(SelectMAP Interface)
DS073_02_031506
(1)
Figure 2: Simplified Block Diagram for XC17V16 and XC17V08
(does not show programming circuit)
DS073 (v1.12) November 13, 2008
www.xilinx.com
Product Specification
2
R
XC17V00 Series Configuration PROMs
CEO
Pin Description
DATA[0:7]
Chip Enable Output is connected to the CE input of the next
PROM in the daisy chain. This output is Low when the CE
and OE inputs are both active AND the internal address
counter has been incremented beyond its Terminal Count
(TC) value. CEO returns to High when OE goes inactive or
CE goes High.
The array data value corresponding to the internal address
counter location is output on enabled DATA[0-7] output
pin(s) when CE is active, OE is active, and the internal
address counter has not incremented beyond its Terminal
Count (TC) value. Otherwise, all data pins are in a high
impedance state when CE is inactive, OE is inactive, or the
internal address counter has incremented beyond its
Terminal Count (TC) value.
BUSY (XC17V16 and XC17V08 Only)
Asserting the BUSY input High prevents rising edges on
CLK from incrementing the internal address counter and
maintains current data on the data pins.
The XC17V01, XC17V02, and XC17V04 have only the
single DATA output pin for connection to the FPGA serial
configuration data input pin.
Note: If the BUSY pin is floating, then the programmable option
to internally tie BUSY to an internal pull-down resistor must be set
during device programming.
The XC17V08 and XC17V16 have the D[0-7] output pins.
During device programming, the XC17V08 and XC17V16
must be programmed for use in either serial output mode or
parallel output mode. For XC17V08 and XC17V16 devices
programmed to serial output mode, only the D0 pin is
VPP
Programming voltage. No overshoot above the specified
maximum voltage is permitted on this pin. For normal read
®
enabled for data output to the Virtex series FPGA serial
operation, this pin must be connected to V . Failure to do
CC
configuration data input pin. In serial mode, the D[1-7]
output pins remain in high impedance state and may be
unconnected. For XC17V08 and XC17V16 devices
programmed to parallel output mode, all D[0-7] output pins
are enabled for byte-wide data output to the FPGA
SelectMAP configuration data input pins.
so may lead to unpredictable, temperature-dependent
operation and severe problems in circuit debugging.
Caution! Do not leave VPP floating!
VCC and GND
The DATA/D0 pin is a bidirectional I/O during device
programming.
Positive supply and ground pins.
PROM Pinouts for XC17V16 and XC17V08
CLK
Pins not listed in Table 1 are “no connect.”
Each rising edge on the CLK input increments the internal
address counter, when CE is active, OE is active, the
internal address counter has not incremented past its
Terminal Count (TC) value, and BUSY is Low.
(1)
Table 1: Pinouts for XC17V16 and XC17V08
Pin Name
BUSY
44-pin VQFP (VQ44) 44-pin PLCC (PC44)
24
40
29
42
27
9
30
2
Note: The BUSY condition applies to only the XC17V08 and
XC17V16.
D0
D1
D2
D3
D4
D5
D6
D7
CLK
35
4
RESET/OE
33
15
31
20
25
5
The polarity of this input pin is programmable as either
RESET/OE or OE/RESET. The polarity is set at the time of
device programming. The device default is active-High
RESET, but compatibility with Xilinx FPGAs requires the
polarity to be programmed with an active-Low RESET.
25
14
19
43
When RESET is active, the address counter is held at “0”,
and puts the DATA output in a high-impedance state.
RESET/OE
(OE/RESET)
13
19
CE
CE
15
6, 18, 28, 37, 41
21
21
3, 12, 24, 34, 43
27
When High, this pin holds the internal address counter in
reset, puts the DATA output in a high-impedance state, and
GND
CEO
forces the device into low-I standby mode.
CC
DS073 (v1.12) November 13, 2008
www.xilinx.com
Product Specification
3
R
XC17V00 Series Configuration PROMs
(1)
Table 1: Pinouts for XC17V16 and XC17V08 (Cont’d)
Pin Name 44-pin VQFP (VQ44) 44-pin PLCC (PC44)
VPP
35
41
VCC
8, 16, 17, 26, 36, 38
14, 22, 23, 32, 42, 44
Notes:
NC
NC
NC
NC
NC
GND
NC
VCC
D4
NC
NC
7
8
9
NC
NC
NC
NC
D1
GND
D3
VCC
D5
BUSY
NC
39
38
37
36
35
34
33
32
31
30
29
1. Specific part number and package combinations have been
discontinued. Refer to XCN07010.
10
11
12
13
14
15
16
17
Capacity
PC44
Top View
Table 2: Device Capacities
Devices
XC17V16
XC17V08(1)
Configuration Bits
16,777,216
8,388,608
Notes:
1. Specific part number and package combinations have been
discontinued. Refer to XCN07010.
Pinout Diagrams for XC17V16 and XC17V08
DS073_13_101502
PROM Pinouts for XC17V04, XC17V02, and
XC17V01
Pins not listed in Table 3 are “no connect.”
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
NC
NC
NC
NC
D1
GND
D3
VCC
D5
BUSY
NC
33
32
31
30
29
28
27
26
25
24
23
Table 3: Pinouts for XC17V04, XC17V02, and XC17V01
8-pin 20-pin 20-pin 44-pin 44-pin
VOIC
SOIC
PLCC
VQFP
PLCC
Pin Name
(V08) (SO20) (PC20) (VQ44) (PC44)
VQ44
Top View
(1)
(1,3)
(1,2)
(2)
(2)
GND
NC
DATA
1
2
1
3
1
3
40
43
2
5
VCC
D4
NC
CLK
9
10
11
RESET/OE
(OE/RESET)
3
8
8
13
19
NC
CE
4
5
6
7
8
10
11
13
18
20
10
11
13
18
20
15
18, 41
21
21
24, 3
27
GND
CEO
VPP
VCC
35
41
38
44
DS073_12_101502
Notes:
1. XC17V01 available in these packages.
2. XC17V02 and XC17V04 available in these packages.
3. Specific part number and package combinations have been
discontinued. Refer to XCN07010.
DS073 (v1.12) November 13, 2008
www.xilinx.com
Product Specification
4
R
XC17V00 Series Configuration PROMs
Capacity
Table 4: Device Capacities
Devices
Configuration Bits
4,194,304
XC17V04
XC17V02(1)
2,097,152
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
7
8
9
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
39
38
37
36
35
34
33
32
31
30
29
XC17V01
1,679,360
Notes:
10
11
12
13
14
15
16
17
1. Specific part number and package combinations have been
discontinued. Refer to XCN07010.
PC44
Top View
(See Note 2)
Pinout Diagrams for XC17V04, XC17V02(1),
and XC17V01
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
33
32
31
30
29
28
27
26
25
24
23
DS073_08_100702
VQ44
Top View
(See Note 2)
DATA(D0)
CLK
VCC
8
7
6
5
1
9
10
11
VPP
CEO
GND
2
VO8
Top View
OE/RESET
CE
3
4
(See Note 1)
DS073_09_110102
DS073_07_100702
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
12
11
DATA(D0)
NC
VCC
NC
VPP
NC
NC
NC
NC
CEO
NC
CLK
NC
NC
NC
SO20
Top
View
(See
Notes 1, 3)
NC
OE/RESET
NC
9
10
CE
GND
DS073_10_082108
DS073 (v1.12) November 13, 2008
www.xilinx.com
Product Specification
5
R
XC17V00 Series Configuration PROMs
Table 5: Xilinx FPGAs and Compatible PROMs (Cont’d)
Configuration
Device
XCV600
XCV800
PROM
Bits
3,607,968
XC17V04
XC17V08(1)
XC17V16
4,715,616
6,127,744
18
17
16
15
VPP
NC
NC
NC
NC
NC
NC
NC
NC
4
5
6
XC17V08(1)
XC17V16
XCV1000
PC20
Top View
7 (See Notes 1, 2, 3)
8
XCV50E
XCV100E
XCV200E
630,048
863,840
XC17V01
XC17V01
XC17V01
14
OE/RESET
1,442,016
XC17V02(1)
XC17V04
XCV300E
1,875,648
DS073_11_062508
XCV400E
XCV405E
XCV600E
2,693,440
3,430,400
3,961,632
XC17V04
XC17V04
XC17V04
Notes:
1. XC1701 is available in these packages.
2. XC1702 and XC1704 are available in these packages.
3. Specific part number and package combinations have been
discontinued. Refer to XCN07010.
XC17V08(1)
XC17V16
XCV812E
XCV1000E
XCV1600E
6,519,648
6,587,520
8,308,992
XC17V08(1)
XC17V16
Xilinx FPGAs and Compatible PROMs
Table 5: Xilinx FPGAs and Compatible PROMs
Configuration
XC17V08(1)
XC17V16
Device
PROM
Bits
XCV2000E
XCV2600E
XCV3200E
XC3S50
10,159,648
12,922,336
16,283,712
439,264
XC17V16
XC17V16
XC17V16
XC17V01
XC17V01
XC2V40
XC2V80
360,096
635,296
XC17V01
XC17V01
XC17V02(1)
XC17V04
XC2V250
1,697,184
XC3S200
1,047,616
XC2V500
2,761,888
4,082,592
XC17V04
XC17V04
XC17V02(1)
XC17V04
XC3S400
XC3S1000
XC3S1500
1,699,136
3,223,488
5,214,784
XC2V1000
XC17V08(1)
XC17V16
XC17V04
XC2V1500
XC2V2000
5,659,296
7,492,000
XC17V08(1)
XC17V16
XC17V08(1)
XC17V16
XC17V08(1)
XC17V16
XC3S2000
7,673,024
XC2V3000
XC2V4000
10,494,368
15,659,936
XC17V16
XC17V16
XC3S4000
XC3S5000
11,316,864
13,271,936
XC17V16
XC17V16
XC17V16+XC17V08(1)
2 of XC17V16
XC2V6000
21,849, 504
Notes:
XC2V8000
XCV50
29,063,072
559,200
2 of XC17V16
XC17V01
XC17V01
XC17V01
XC17V01
1. Specific part number and package combinations have been
discontinued. Refer to XCN07010. For some devices, the
original PROM recommendation is shown along with the
replacement PROM.
XCV100
XCV150
XCV200
781,216
1,040,096
1,335,840
XC17V02(1)
XC17V04
XCV300
XCV400
1,751,808
2,546,048
XC17V04
DS073 (v1.12) November 13, 2008
www.xilinx.com
Product Specification
6
R
XC17V00 Series Configuration PROMs
Controlling PROMs
Cascading Configuration PROMs
Connecting the FPGA device with the PROM.
For multiple FPGAs configured as a daisy-chain, or for
future FPGAs requiring larger configuration memories,
cascaded PROMs provide additional memory. After the last
bit from the first PROM is read, the next clock signal to the
PROM asserts its CEO output Low and disables its DATA
line. The second PROM recognizes the Low level on its CE
input and enables its DATA output. See Figure 3.
•
•
•
•
The DATA output(s) of the PROM(s) drives the
configuration data input(s) of the lead FPGA device.
The Master FPGA CCLK output drives the CLK input(s)
of the PROM(s).
The CEO output of a PROM drives the CE input of the
next PROM in a daisy chain (if any).
After configuration is complete, the address counters of all
cascaded PROMs are reset if the FPGA PROGRAM pin
goes Low, assuming the PROM reset polarity option has
been inverted.
The RESET/OE input of all PROMs is best driven by
the INIT output of the lead FPGA device. This
connection assures that the PROM address counter is
reset before the start of any (re)configuration, even
when a reconfiguration is initiated by a V glitch.
CC
Standby Mode
The PROM enters a low-power standby mode whenever CE
is asserted High. The output remains in a high impedance
state regardless of the state of the OE input.
•
•
The PROM CE input is best connected to the FPGA
DONE pin(s) and a pullup resistor. CE can also be
permanently tied Low, but this keeps the DATA output
active and causes an unnecessary supply current of
15 mA maximum.
SelectMAP mode is similar to Slave Serial mode. The
DATA is clocked out of the PROM one byte per CCLK
instead of one bit per CCLK cycle. See FPGA data
sheets for special configuration requirements.
Programming
The devices can be programmed on programmers supplied
by Xilinx or qualified third-party vendors. The user must
ensure that the appropriate programming algorithm and the
latest version of the programmer software are used. The
wrong choice can permanently damage the device.
FPGA Master Serial Mode Summary
The I/O and logic functions of the Configurable Logic Block
(CLB) and their associated interconnections are established
by a configuration program. The program is loaded either
automatically upon power up, or on command, depending
on the state of the three FPGA mode pins. In Master Serial
mode, the FPGA automatically loads the configuration
program from an external memory. The Xilinx PROMs have
been designed for compatibility with the Master Serial
mode.
Selecting Reset Polarity and
Configuration Modes
The OE/RESET input polarity is programmable on all
XC17V00 PROMs. In addition, the XC17V08 and XC17V16
can accommodate either serial or parallel configuration
mode. The reset polarity and configuration mode are
selectable through the programmer software. For
compatibility with Xilinx FPGAs, the OE/RESET polarity
must be programmed with RESET active-Low.
Upon power-up or reconfiguration, an FPGA enters the
Master Serial mode whenever all three of the FPGA mode-
select pins are Low (M0=0, M1=0, M2=0). Data is read from
the PROM sequentially on a single data line.
Synchronization is provided by the rising edge of the
temporary signal CCLK, which is generated during
configuration.
Master Serial Mode provides a simple configuration
interface. Only one serial data line, two control lines, and
one clock line are required to configure an FPGA. Data from
the PROM is read sequentially, accessed via the internal
address and bit counters which are incremented on every
valid rising edge of CCLK.
If the user-programmable, dual-function DIN pin on the
FPGA is used only for configuration, it must still be held at a
defined level during normal operation. The Xilinx FPGA
families take care of this automatically with an on-chip
default pull-up/down resistor or keeper circuit.
DS073 (v1.12) November 13, 2008
www.xilinx.com
Product Specification
7
R
XC17V00 Series Configuration PROMs
Outputs
Table 6: Truth Table for XC17V00 Control Inputs
Control Inputs
Internal Address
RESET(1)
CE
DATA
CEO
ICC
Inactive
Low
If address < TC(2): increment
Active
High-Z
High
Low
Active
Reduced
If address > TC(2): don’t change
Active
Inactive
Active
Low
High
High
Held reset
Not changing
Held reset
High-Z
High-Z
High-Z
High
High
High
Active
Standby
Standby
Notes:
1. The XC17V00 RESET input has programmable polarity
2. TC = terminal count, highest address value.
DS073 (v1.12) November 13, 2008
www.xilinx.com
Product Specification
8
R
XC17V00 Series Configuration PROMs
X-Ref Target - Figure 3
OPTIONAL
Daisy-chained
FPGAs with
different
DOUT
V
CC
configurations
4.7K
FPGA
OPTIONAL
V
CC
Slave FPGAs
with identical
configurations
4.7K
(1)
Modes
V
CC
V
CC
V
CC
(2)
V
CC
Vpp
V
CC
Vpp
DATA
CLK
CE
DIN
BUSY
BUSY
First
PROM
CCLK
DATA
CEO
DONE
INIT
Cascaded
PROM
CLK
CE
OE/RESET
OE/RESET
PROGRAM
(Low Resets the Address Pointer)
(1) For Mode pin connections, refer to the appropriate FPGA data sheet or user guide.
(2) For specific DONE resistor recommendations, refer to the appropriate FPGA data sheet or user guide.
Master Serial Mode
(1)
I/O
(1)
V
V
V
V
I/O
CC
CC
CC
External
Osc
CS
(4)
(3)
Modes
WRITE
1K
1K
3.3V
4.7K
Vpp
Vpp
BUSY
Second
FPGA
CC
V
CC
(2)
BUSY
BUSY
First
PROM
CLK
CLK
CCLK
PROM
8
PROGRAM
CEO
CEO
D[0:7]
DONE
INIT
D[0:7]
CE
D[0:7]
CE
OE/RESET
OE/RESET
(1) CS and WRITE must be pulled down to be used as I/O. One option is shown.
(2) For specific DONE resistor recommendations, refer to the appropriate FPGA data sheet or user guide.
(3) For Mode pin connections, refer to the appropriate FPGA data sheet or user guide.
(4) External oscillator required for FPGA slave SelectMAP modes.
SelectMAP Mode, XC17V16 and XC17V08(1) only.
DS073_03_102708
Figure 3: (a) Master Serial Mode (b) SelectMAP Mode
(dotted lines indicate optional connection)
Notes:
1. Specific part number and package combinations have been discontinued. Refer to XCN07010.
DS073 (v1.12) November 13, 2008
www.xilinx.com
Product Specification
9
R
XC17V00 Series Configuration PROMs
Absolute Maximum Ratings(1)
Symbol
Description
Conditions
–0.5 to +7.0
–0.5 to +12.5
–0.5 to VCC +0.5
–0.5 to VCC +0.5
–65 to +150
+125
Units
V
VCC
VPP
VIN
Supply voltage relative to GND
Supply voltage relative to GND
Input voltage relative to GND
V
V
VTS
TSTG
TJ
Voltage applied to High-Z output
Storage temperature (ambient)
Junction temperature
V
°C
°C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Operating Conditions (3V Supply)
Symbol
Description
Supply voltage relative to GND (TA = 0°C to +70°C)
Supply voltage relative to GND (TA = –40°C to +85°C)
VCC rise time from 0V to nominal voltage
Min
3.0
3.0
1.0
Max
3.6
3.6
50
Units
V
Commercial
Industrial
(1)
VCC
V
(2)
TVCC
ms
Notes:
1. During normal read operation V must be connected to V
.
CC
PP
2. At power up, the device requires the V power supply to monotonically rise from 0V to nominal voltage within the specified V rise time. If
CC
CC
the power supply cannot meet this requirement, then the device may not power-on-reset properly.
DC Characteristics Over Operating Condition
Symbol
Description
Min
2
Max
VCC
0.8
–
Units
VIH
High-level input voltage
Low-level input voltage
V
V
V
V
VIL
0
VOH
VOL
High-level output voltage (IOH = –3 mA)
Low-level output voltage (IOL = +3 mA)
2.4
–
0.4
Supply current, active mode (at maximum frequency)
(XC17V16 and XC17V08(1) only)
ICCA
ICCA
–
–
100
15
mA
mA
Supply current, active mode (at maximum frequency)
(XC17V04, XC17V02(1), and XC17V01(1) only)
ICCS
IL
Supply current, standby mode
–
–10
–
1
mA
μA
pF
pF
Input or output leakage current
10
15
15
CIN
Input capacitance (VIN = GND, f = 1.0 MHz)
Output capacitance (VIN = GND, f = 1.0 MHz)
COUT
–
Notes:
1. Specific part number and package combinations have been discontinued. Refer to XCN07010.
DS073 (v1.12) November 13, 2008
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Product Specification
10
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XC17V00 Series Configuration PROMs
AC Characteristics over Operating Condition for XC17V04, XC17V02, and
XC17V01
X-Ref Target - Figure 4
TCEH
CE
T
T
T
HCE
SCE
SCE
RESET/OE
T
HOE
T
LC
T
HC
T
CYC
CLK
T
T
DF
OE
T
T
CAC
OH
T
CE
DATA
T
OH
Notes:
1 The XC17V00 RESET/OE input polarity is programmable. The RESET/OE input is shown in the timing diagram with active-high
RESET polarity. Timing specifications are identical for both polarity settings.
2 The diagram shows timing relationships. The diagram is not reflective of actual FPGA signal sequences. See the appropriate
FPGA data sheet or user guide for actual configuration signal sequences.
DS073_04_14102005
Symbol
TOE
Description
Min
–
Max
Units
ns
OE to data delay
CE to data delay
CLK to data delay
30
45
45
50
–
TCE
–
ns
TCAC
TDF
–
ns
CE or OE to data float delay(2,3)
Data hold from CE, OE, or CLK(3)
Clock periods
–
ns
TOH
0
ns
TCYC
TLC
67
25
25
25
0
–
ns
CLK Low time(3)
–
ns
THC
CLK High time(3)
–
ns
TSCE
THCE
THOE
TCEH
CE setup time to CLK (to guarantee proper counting)
CE hold time to CLK (to guarantee proper counting)
OE hold time (guarantees counters are reset)
CE High time (guarantees counters are reset)
–
ns
–
ns
25
20
–
ns
–
ns
Notes:
1. AC test load = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with V = 0.0V and V = 3.0V.
IL
IH
5. If T
6. If T
High, 2 μs, T = 2 μs.
CEH
HOE
CE
High, 2 μs, T = 2 μs.
OE
DS073 (v1.12) November 13, 2008
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Product Specification
11
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XC17V00 Series Configuration PROMs
AC Characteristics over Operating Condition for XC17V16 and XC17V08
X-Ref Target - Figure 5
TCEH
CE
T
T
T
HCE
SCE
SCE
RESET/OE(1)
CLK
T
HOE
T
T
HC
LC
T
CYC
T
T
DF
OE
T
T
OH
CAC
T
CE
DATA
T
T
SBUSY
OH
T
HBUSY
BUSY(2)
Note:
1 The XC17V00 RESET/OE input polarity is programmable. The RESET/OE input is shown in the timing diagram with active-high RESET polarity.
Timing specifications are identical for both polarity settings.
2. If BUSY is inactive (Low) during a rising CLK edge, then new DATA appears at time T
during a rising CLK edge, then there is no corresponding change to DATA.
after the rising CLK edge. If BUSY is active (High)
CAC
DS073_05_031606
Symbol
Description
Min
–
Max
15
20
20
35
–
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TOE
TCE
OE to data delay
CE to data delay
–
TCAC
TDF
CLK to data delay(2)
–
CE or OE to data float delay(3,4)
Data hold from CE, OE, or CLK(4)
Clock periods
–
TOH
0
TCYC
TLC
50
25
25
25
0
–
CLK Low time(4)
–
THC
CLK High time(4)
–
TSCE
THCE
THOE
CE setup time to CLK (to guarantee proper counting)
CE hold time to CLK (to guarantee proper counting)
OE hold time (guarantees counters are reset)
–
–
25
5
–
TSBUSY BUSY setup time
THBUSY BUSY hold time
–
5
–
TCEH
CE High time (guarantees counters are reset)
20
–
Notes:
1. AC test load = 50 pF.
2. When BUSY = 0.
3. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels.
4. Guaranteed by design, not tested.
5. All AC parameters are measured with V = 0.0V and V = 3.0V.
IL
IH
6. If T
7. If T
High, 2 μs, T = 2 μs.
CEH
HOE
CE
High, 2 μs, T = 2 μs.
OE
DS073 (v1.12) November 13, 2008
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Product Specification
12
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XC17V00 Series Configuration PROMs
AC Characteristics over Operating Condition When Cascading
X-Ref Target - Figure 6
RESET/OE
CE
CLK
DATA
CEO
T
CDF
T
T
OCE
Last Bit
First Bit
T
OCK
OOE
Notes:
1 The XC17V00 RESET/OE input polarity is programmable. The RESET/OE input is shown in the timing diagram with active-high
RESET polarity. Timing specifications are identical for both polarity settings.
2 The diagram shows timing of the First Bit and Last Bit for one PROM with respect to signals involved in a cascaded situation.
The diagram does not show timing of data as one PROM transfers control to the next PROM. The shown timing information must
be applied appropriately to each PROM in a cascaded situation to understand the timing of data during the transfer of control
from one PROM to the next.
DS026_07_102005
Symbol
TCDF
Description
Min
–
Max
50
Units
ns
CLK to data float delay(2,3)
CLK to CEO delay(3)
TOCK
–
30
ns
TOCE
CE to CEO delay(3)
–
35
ns
TOOE
RESET/OE to CEO delay(3)
–
30
ns
Notes:
1. AC test load = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with V = 0.0V and V = 3.0V.
IL
IH
Ordering Information
XC17V16 PC44 C
Device Number
Operating Range/Processing
C = Commercial (T = 0° to +70°C)
XC17V16
XC17V04
XC17V01
Package Type
A
I = Industrial (T = –40° to +85°C)
A
VQ44 = 44-pin Plastic Quad Flat Package
PC44 = 44-pin Plastic Chip Carrier
VO8 = 8-pin Plastic Small Outline Thin Package
PC20 = 20-pin Plastic Leaded Chip Carrier
DS073 (v1.12) November 13, 2008
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Product Specification
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XC17V00 Series Configuration PROMs
Valid Ordering Combinations
XC17V16VQ44C
XC17V16PC44C
XC17V16VQ44I
XC17V16PC44I
XC17V04PC20C
XC17V04PC44C
XC17V04VQ44C
XC17V04PC20I
XC17V04PC44I
XC17V04VQ44I
XC17V01VO8C
Marking Information
Due to the small size of the commercial serial PROM packages, the complete ordering part number cannot be marked on
the package. The XC prefix is deleted and the package code is simplified. Device marking is as follows:
XC17V16 PC44 C
Device Number
Operating Range/Processing
XC17V16
XC17V08
XC17V04
XC17V02
C = Commercial (T = 0° to +70°C)
Package Type
A
(1)
I = Industrial (T = –40° to +85°C)
A
VQ44 = 44-pin Plastic Quad Flat Package
PC44 = 44-pin Plastic Chip Carrier
VO8 = 8-pin Plastic Small Outline Thin Package
PC20 = 20-pin Plastic Leaded Chip Carrier
(1)
XC17V01
(1)
SO20 = 20-pin Plastic Small Outline Package
Notes:
1. Specific part number and package combinations have been discontinued. Refer to XCN07010.
DS073 (v1.12) November 13, 2008
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Product Specification
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XC17V00 Series Configuration PROMs
Revision History
The following table shows the revision history for this document.
.
Date
Version
1.0
Revision
07/26/00
10/09/00
11/16/00
Initial Xilinx release.
1.1
Updated 20-pin PLCC Pinouts.
1.2
Updated pinouts for XC17V16 and XC17V08, ICCA DC Characteristic from standby to active mode; CIN
and COUT from 10 pF to 15 pF, added ICCS for XC17V16 and XC17V08 at 500 μA.
02/20/01
04/04/01
10/09/01
1.3
1.4
1.5
Added note to pinouts for “no connect,” updated Figure 3.
Added XC2V products to Compatible PROM table, updated Figure 3, updated text for Virtex-II FPGAs.
Corrected bitstream length for SCV405E, added power-on supply requirements and note for power-on
reset, updated configuration bits for Virtex-II devices, removed CF from Figure 3, and updated FPGA list.
02/27/02
06/14/02
07/29/02
11/05/02
1.6
1.7
1.8
1.9
Added Virtex-II Pro™ FPGAs to the , page 6.
Made additions and changes to Xilinx FPGAs and Compatible PROMs, page 6.
Added Virtex-II Pro FPGAs to , page 6.
Added pinout diagrams, changed , page 6, and added footnotes to AC Characteristics over Operating
Condition for XC17V04, XC17V02, and XC17V01, page 11 and AC Characteristics over Operating
Condition for XC17V16 and XC17V08, page 12.
04/10/03
06/07/07
1.10
1.11
Added Spartan-3 FPGAs to Truth Table for XC17V00 Control Inputs, page 8.
• Figure 2, page 2 updated to show correct three-state control on output data buses.
• Corrected XC3S50 bitstream size in Xilinx FPGAs and Compatible PROMs, page 6.
• Added section Selecting Reset Polarity and Configuration Modes, page 7.
• Removed maximum soldering temperature (TSOL) from "Absolute Maximum Ratings(1)," page 10.
Refer to Xilinx Device Package User Guide for package soldering guidelines.
• Added notes to timing diagram under AC Characteristics over Operating Condition for XC17V04,
XC17V02, and XC17V01, page 11 for clarification.
• Added notes and updated timing diagram AC Characteristics over Operating Condition for XC17V16
and XC17V08, page 12 for clarification.
• Reversed polarity of RESET/OE signal in timing diagram under , page 13 for consistency and added
notes for clarification.
11/13/08
1.12
• Added support for discontinued device and package combinations per XCN07010.
• Added TJ to "Absolute Maximum Ratings(1)," page 10.
• Updated Figure 3.
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED
WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE
SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
DS073 (v1.12) November 13, 2008
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Product Specification
15
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