XC18V04PCG44C [XILINX]
In-System-Programmable Configuration PROMs; 在系统可编程配置PROM
| 型号： | XC18V04PCG44C |
| 厂家： | 
XILINX, INC |
| 描述： | In-System-Programmable Configuration PROMs |
| 文件： | 总24页 (文件大小：316K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
24
R
XC18V00 Series In-System-Programmable
Configuration PROMs
0
DS026 (v5.2) January 11, 2008
Product Specification
Features
•
In-System Programmable 3.3V PROMs for
Configuration of Xilinx FPGAs
•
•
Low-Power Advanced CMOS FLASH Process
Dual Configuration Modes
♦
♦
Endurance of 20,000 Program/Erase Cycles
♦
♦
Serial Slow/Fast Configuration (up to 33 MHz)
Parallel (up to 264 Mb/s at 33 MHz)
Program/Erase Over Full Industrial Voltage and
Temperature Range (–40°C to +85°C)
•
•
•
5V-Tolerant I/O Pins Accept 5V, 3.3V and 2.5V Signals
3.3V or 2.5V Output Capability
•
•
IEEE Std 1149.1 Boundary-Scan (JTAG) Support
JTAG Command Initiation of Standard FPGA
Configuration
Design Support Using the Xilinx ISE™ Foundation™
Software Packages
•
•
Simple Interface to the FPGA
•
•
Available in PC20, SO20, PC44, and VQ44 Packages
Lead-Free (Pb-Free) Packaging
Cascadable for Storing Longer or Multiple Bitstreams
Description
Xilinx introduces the XC18V00 series of in-system
programmable configuration PROMs (Figure 1). Devices in
this 3.3V family include a 4-megabit, a 2-megabit, a
1-megabit, and a 512-kilobit PROM that provide an easy-to-
use, cost-effective method for reprogramming and storing
Xilinx FPGA configuration bitstreams.
When the FPGA is in Master SelectMAP mode, the FPGA
generates a configuration clock that drives the PROM. When
the FPGA is in Slave Parallel or Slave SelectMAP mode, an
external oscillator generates the configuration clock that
drives the PROM and the FPGA. After CE and OE are
enabled, data is available on the PROM’s DATA (D0-D7)
pins. New data is available a short access time after each
rising clock edge. The data is clocked into the FPGA on the
following rising edge of the CCLK. A free-running oscillator
can be used in the Slave Parallel or Slave SelecMAP modes.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after CE and OE are enabled, data is available on the
PROM DATA (D0) pin that is connected to the FPGA DIN
pin. New data is available a short access time after each
rising clock edge. The FPGA generates the appropriate
number of clock pulses to complete the configuration. When
the FPGA is in Slave Serial mode, the PROM and the FPGA
are clocked by an external clock.
Multiple devices can be cascaded by using the CEO output
to drive the CE input of the following device. The clock
inputs and the DATA outputs of all PROMs in this chain are
interconnected. All devices are compatible and can be
cascaded with other members of the family or with the
XC17V00 one-time programmable serial PROM family.
X-Ref Target - Figure 1
CLK CE
OE/RESET
TCK
TMS
TDI
CEO
Data
Control
and
JTAG
Serial
or
Parallel
Interface
Data
D0 DATA
Serial or Parallel Mode
Memory
Address
Interface
7
D[1:7]
Parallel Interface
TDO
CF
DS026_01_040204
Figure 1: XC18V00 Series Block Diagram
© 1999–2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
DS026 (v5.2) January 11, 2008
www.xilinx.com
Product Specification
1
R
XC18V00 Series In-System-Programmable Configuration PROMs
Pinout and Pin Description
Table 1 provides a list of the pin names and descriptions for the 44-pin VQFP and PLCC and the 20-pin SOIC and PLCC
packages.
Table 1: Pin Names and Descriptions
20-pin
SOIC &
PLCC
Pin
Name
Boundary-
Scan Order
44-pin
PLCC
Function
Pin Description
44-pin VQFP
D0
D1
D2
D3
D4
D5
D6
D7
CLK
4
3
DATA OUT D0 is the DATA output pin to provide data for
40
2
1
16
2
configuring an FPGA in serial mode.
OUTPUT
ENABLE
6
5
DATA OUT D0-D7 are the output pins to provide parallel
data for configuring a Xilinx FPGA in Slave
29
42
27
9
35
4
OUTPUT
ENABLE
Parallel/SelectMAP mode.
D1-D7 remain in high-Z state when the PROM
operates in serial mode.
2
1
DATA OUT
D1-D7 can be left unconnected when the
PROM is used in serial mode.
OUTPUT
ENABLE
8
7
DATA OUT
33
15
31
20
25
15
7(1)
14
9
OUTPUT
ENABLE
24
23
DATA OUT
OUTPUT
ENABLE
10
9
DATA OUT
25
14
19
OUTPUT
ENABLE
17
16
DATA OUT
OUTPUT
ENABLE
14
13
DATA OUT
12
OUTPUT
ENABLE
0
DATA IN
Each rising edge on the CLK input increments
the internal address counter if both CE is Low
and OE/RESET is High.
43
13
5
3
8
OE/
RESET
20
19
18
DATA IN
When Low, this input holds the address
counter reset and the DATA output is in a high-
Z state. This is a bidirectional open-drain pin
that is held Low while the PROM is reset.
Polarity is NOT programmable.
19
DATA OUT
OUTPUT
ENABLE
CE
CF
15
DATA IN
When CE is High, the device is put into low-
power standby mode, the address counter is
reset, and the DATA pins are put in a high-Z
state.
15
10
21
16
10
22
21
DATA OUT Allows JTAG CONFIG instruction to initiate
FPGA configuration without powering down
7(1)
OUTPUT
ENABLE
FPGA. This is an open-drain output that is
pulsed Low by the JTAG CONFIG command.
DS026 (v5.2) January 11, 2008
www.xilinx.com
Product Specification
2
R
XC18V00 Series In-System-Programmable Configuration PROMs
Table 1: Pin Names and Descriptions (Cont’d)
20-pin
44-pin
Pin
Name
Boundary-
Scan Order
Function
Pin Description
44-pin VQFP
SOIC &
PLCC
PLCC
CEO
12
11
DATA OUT Chip Enable Output (CEO) is connected to the
CE input of the next PROM in the chain. This
21
27
13
OUTPUT
output is Low when CE is Low and OE/RESET
ENABLE
input is High, AND the internal address counter
has been incremented beyond its Terminal
Count (TC) value. CEO returns to High when
OE/RESET goes Low or CE goes High.
GND
TMS
GND is the ground connection.
6, 18, 28 & 41 3, 12, 24 &
34
11
5
MODE
SELECT
The state of TMS on the rising edge of TCK
determines the state transitions at the Test
Access Port (TAP) controller. TMS has an
internal 50 kΩ resistive pull-up to provide a
logic 1 to the device if the pin is not driven.
5
11
TCK
TDI
CLOCK
DATA IN
This pin is the JTAG test clock. It sequences
the TAP controller and all the JTAG test and
programming electronics.
7
3
13
9
6
4
This pin is the serial input to all JTAG
instruction and data registers. TDI has an
internal 50 kΩ resistive pull-up to provide a
logic 1 to the device if the pin is not driven.
TDO
DATA OUT This pin is the serial output for all JTAG
instruction and data registers. TDO has an
internal 50 kΩ resistive pull-up to provide a
logic 1 to the system if the pin is not driven.
31
37
17
VCCINT
VCCO
Positive 3.3V supply voltage for internal logic. 17, 35 & 38(3)
23, 41 &
44(3)
18 & 20(3)
19
Positive 3.3V or 2.5V supply voltage connected 8, 16, 26 & 36 14, 22, 32 &
to the input buffers(2) and output voltage
drivers.
42
NC
No connects.
1, 2, 4,
1, 6, 7, 8,
11, 12, 20, 22, 10, 17, 18,
23, 24, 30, 32, 26, 28, 29,
33, 34, 37, 39, 30, 36, 38,
44
39, 40, 43
Notes:
1. By default, pin 7 is the D4 pin in the 20-pin packages. However, CF →D4 programming option can be set to override the default and route
the CF function to pin 7 in the Serial mode.
2. For devices with IDCODES 0502x093h, the input buffers are supplied by V
.
CCINT
3. For devices with IDCODES 0503x093h, the following V
pins are no-connects: pin 38 in 44-pin VQFP package, pin 44 in 44-pin PLCC
CCINT
package, and pin 20 in 20-pin SOIC and 20-pin PLCC packages.
DS026 (v5.2) January 11, 2008
www.xilinx.com
Product Specification
3
R
XC18V00 Series In-System-Programmable Configuration PROMs
Pinout Diagrams
DATA(D0)
D2
1
20
19
18
17
16
15
14
13
12
11
VCCINT*
VCCO
VCCINT*
TDO
D1
2
CLK
3
TDI
4
SO20/
SOG20
Top
TMS
5
TCK
6
D3
CF/D4*
OE/RESET
D6
7
D5
View
39
38
37
36
35
34
33
32
31
30
29
NC
NC
TDO
NC
D1
GND
D3
VCCO
D5
NC
NC
NC
NC
TDI
7
8
9
8
CEO
D7
9
CE
10
GND
NC
10
11
12
13
14
15
16
17
TMS
GND
TCK
VCCO
D4
*See pin descriptions.
PC44/PCG44
Top View
DS026_14_102005
CF
NC
4
5
6
7
8
18
17
16
15
14
TDI
TMS
VCCINT*
TDO
D1
PC20/
PCG20
Top View
TCK
*See pin descriptions.
D4/CF*
OE/RESET
D3
DS026_12_20051007
D5
*See pin descriptions.
DS026_15_20051007
NC
NC
TDI
1
2
3
4
5
6
7
8
33
32
31
30
29
28
27
26
25
24
23
NC
NC
TDO
NC
D1
GND
D3
VCCO
D5
NC
NC
NC
TMS
GND
TCK
VCCO
D4
VQ44/VQG44
Top View
9
10
11
CF
NC
*See pin descriptions.
DS026_13_20051007
DS026 (v5.2) January 11, 2008
www.xilinx.com
Product Specification
4
R
XC18V00 Series In-System-Programmable Configuration PROMs
Xilinx FPGAs and Compatible PROMs
Table 2 provides a list of Xilinx FPGAs and compatible PROMs.
Table 2: Xilinx FPGAs and Compatible PROMs (Cont’d)
Table 2: Xilinx FPGAs and Compatible PROMs
Configuration
Configuration
Device
XC18V00 Solution
Device
XC18V00 Solution
Bits
Bits
XCV405E
XCV600E
XCV812E
XCV1000E
XCV1600E
XCV2000E
XCV2600E
XCV3200E
XC2S15
3,430,400
3,961,632
6,519,648
6,587,520
8,308,992
10,159,648
12,922,336
16,283,712
197,696
XC18V04
XC18V04
XC2VP2
XC2VP4
1,305,376
3,006,496
XC18V02
XC18V04
2 of XC18V04
2 of XC18V04
2 of XC18V04
3 of XC18V04
4 of XC18V04
4 of XC18V04
XC18V512
XC18V512
XC18V01
XC18V04 +
XC18V512
XC2VP7
4,485,408
XC2VP20
XC2VP30
XC2VP40
XC2VP50
8,214,560
11,589,920
15,868,192
19,021,344
2 of XC18V04
3 of XC18V04
4 of XC18V04
5 of XC18V04
6 of XC18V04 +
XC18V512
XC2VP70
26,098,976
34,292,768
XC2S30
336,768
8 of XC18V04 +
XC18V512
XC2VP100
XC2S50
559,200
XC2S100
XC2S150
XC2S200
XC2S50E
XC2S100E
XC2S150E
XC2S200E
XC2S300E
XC2S400E
XC2S600E
XC3S50
781,216
XC18V01
XC2V40
XC2V80
470,048
732,576
XC18V512
XC18V01
XC18V02
XC18V04
XC18V04
1,040,096
1,335,840
630,048
XC18V01
XC18V02
XC2V250
XC2V500
XC2V1000
1,726,880
2,767,520
4,089,504
XC18V01
863,840
XC18V01
1,134,496
1,442,016
1,875,648
2,693,440
3,961,632
439,264
XC18V02
XC18V04
+ XC18V02
XC2V1500
5,667,488
XC18V02
XC2V2000
XC2V3000
XC2V4000
7,501,472
10,505,120
15,673,248
2 of XC18V04
3 of XC18V04
4 of XC18V04
XC18V02
XC18V04
XC18V04
5 of XC18V04 +
XC18V02
XC18V512
XC18V01
XC2V6000
21,865,376
XC3S200
XC3S400
XC3S1000
1,047,616
1,699,136
3,223,488
XC2V8000
XCV50
29,081,504
559,200
7 of XC18V04
XC18V01
XC18V01
XC18V01
XC18V02
XC18V02
XC18V04
XC18V04
XC18V02
XC18V04
XCV100
XCV150
XCV200
XCV300
XCV400
XCV600
781,216
XC18V04 +
XC18V01
XC3S1500
5,214,784
1,040,096
1,335,840
1,751,808
2,546,048
3,607,968
XC3S2000
XC3S4000
7,673,024
2 of XC18V04
3 of XC18V04
11,316,864
3 of XC18V04 +
XC18V01
XC3S5000
13,271,936
XC18V04 +
XC18V512
XCV800
4,715,616
6,127,744
Capacity
XC18V04 +
XC18V02
XCV1000
Devices
XC18V04
XC18V02
XC18V01
XC18V512
Configuration Bits
4,194,304
2,097,152
1,048,576
524,288
XCV50E
XCV100E
XCV200E
XCV300E
XCV400E
630,048
863,840
XC18V01
XC18V01
XC18V02
XC18V02
XC18V04
1,442,016
1,875,648
2,693,440
DS026 (v5.2) January 11, 2008
www.xilinx.com
Product Specification
5
R
XC18V00 Series In-System-Programmable Configuration PROMs
system programmable option for future enhancements and
design changes.
In-System Programming
In-System Programmable PROMs can be programmed
individually, or two or more can be chained together and
programmed in-system via the standard 4-pin JTAG
protocol as shown in Figure 2. In-system programming
offers quick and efficient design iterations and eliminates
unnecessary package handling or socketing of devices. The
Xilinx development system provides the programming data
sequence using either Xilinx iMPACT software and a
download cable, a third-party JTAG development system, a
JTAG-compatible board tester, or a simple microprocessor
interface that emulates the JTAG instruction sequence. The
iMPACT software also outputs serial vector format (SVF)
files for use with any tools that accept SVF format and with
automatic test equipment.
Reliability and Endurance
Xilinx in-system programmable products provide a
guaranteed endurance level of 20,000 in-system
program/erase cycles and a minimum data retention of 20
years. Each device meets all functional, performance, and
data retention specifications within this endurance limit. See
the UG116, Xilinx Device Reliability Report, for device
quality, reliability, and process node information.
Design Security
The Xilinx in-system programmable PROM devices
incorporate advanced data security features to fully protect
the programming data against unauthorized reading via
JTAG. Table 3 shows the security setting available.
All outputs are held in a high-Z state or held at clamp levels
during in-system programming.
OE/RESET
The read security bit can be set by the user to prevent the
internal programming pattern from being read or copied via
JTAG. When set, it allows device erase. Erasing the entire
device is the only way to reset the read security bit.
The ISP programming algorithm requires issuance of a
reset that causes OE to go Low.
Table 3: Data Security Options
External Programming
Reset
Set
Xilinx reprogrammable PROMs can also be programmed by
a third-party device programmer, providing the added
flexibility of using pre-programmed devices with an in-
Read Allowed
Program/Erase Allowed
Verify Allowed
Read Inhibited via JTAG
Program/Erase Allowed
Verify Inhibited
X-Ref Target - Figure 2
(a)
(b)
DS026_02_06/1103
Figure 2: In-System Programming Operation (a) Solder Device to PCB and (b) Program Using Download Cable
DS026 (v5.2) January 11, 2008
www.xilinx.com
Product Specification
6
R
XC18V00 Series In-System-Programmable Configuration PROMs
X-Ref Target - Figure 3
IEEE 1149.1 Boundary-Scan (JTAG)
IR[7:5] IR[4]
IR[3]
IR[2] IR[1:0]
01(1)
ISP
000
The XC18V00 family is fully compliant with the IEEE Std.
1149.1 Boundary-Scan, also known as JTAG. A Test
Access Port (TAP) and registers are provided to support all
required Boundary-Scan instructions, as well as many of
the optional instructions specified by IEEE Std. 1149.1. In
addition, the JTAG interface is used to implement in-system
programming (ISP) to facilitate configuration, erasure, and
verification operations on the XC18V00 device.
TDI →
Security
0
→ TDO
Status
Notes:
1. IR[1:0] = 01 is specified by IEEE Std. 1149.1
Figure 3: Instruction Register Values Loaded into IR as
Part of an Instruction Scan Sequence
Boundary-Scan Register
Table 4 lists the required and optional Boundary-Scan
instructions supported in the XC18V00. Refer to the IEEE Std.
1149.1 specification for a complete description of Boundary-
Scan architecture and the required and optional instructions.
The Boundary-Scan register is used to control and observe
the state of the device pins during the EXTEST,
SAMPLE/PRELOAD, and CLAMP instructions. Each output
pin on the XC18V00 has two register stages that contribute
to the Boundary-Scan register, while each input pin only has
one register stage.
Table 4: Boundary-Scan Instructions
Boundary-Scan
Command
Binary
Code [7:0]
Description
For each output pin, the register stage nearest to TDI controls
and observes the output state, and the second stage closest to
TDO controls and observes the high-Z enable state of the pin.
Required Instructions:
BYPASS
11111111 Enables BYPASS
For each input pin, the register stage controls and observes
the input state of the pin.
SAMPLE/
PRELOAD
00000001 Enables Boundary-Scan
SAMPLE/PRELOAD
operation
Identification Registers
EXTEST
00000000 Enables Boundary-Scan
EXTEST operation
The IDCODE is a fixed, vendor-assigned value that is used
to electrically identify the manufacturer and type of the
device being addressed. The IDCODE register is 32 bits
wide. The IDCODE register can be shifted out for
Optional Instructions:
CLAMP
11111010 Enables Boundary-Scan
CLAMP operation
examination by using the IDCODE instruction. The IDCODE
is available to any other system component via JTAG.
HIGHZ
11111100 All outputs in high-Z state
simultaneously
IDCODE
11111110 Enables shifting out
See Table 5 for the XC18V00 IDCODE values.
The IDCODE register has the following binary format:
vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1
where
32-bit IDCODE
USERCODE
11111101 Enables shifting out
32-bit USERCODE
XC18V00 Specific Instructions:
CONFIG
11101110 Initiates FPGA configuration
by pulsing CF pin Low once
v = the die version number
f = the family code (50h for XC18V00 family)
a = the ISP PROM product ID (26h or 36h for the XC18V04)
c = the company code (49h for Xilinx)
Instruction Register
The Instruction Register (IR) for the XC18V00 is eight bits
wide and is connected between TDI and TDO during an
instruction scan sequence. In preparation for an instruction
scan sequence, the instruction register is parallel loaded with
a fixed instruction capture pattern. This pattern is shifted out
onto TDO (LSB first), while an instruction is shifted into the
instruction register from TDI. The detailed composition of the
instruction capture pattern is illustrated in Figure 3.
Note: The LSB of the IDCODE register is always read as logic “1”
as defined by IEEE Std. 1149.1.
Table 5 lists the IDCODE register values for XC18V00 devices.
Table 5: IDCODES Assigned to XC18V00 Devices
ISP-PROM
XC18V01
XC18V02
XC18V04
XC18V512
IDCODE
05024093h or <v>5034093h
05025093h or <v>5035093h
05026093h or <v>5036093h
05023093h or <v>5033093h
The ISP Status field, IR(4), contains logic “1” if the device is
currently in ISP mode; otherwise, it contains logic “0”. The
Security field, IR(3), contains logic “1” if the device has been
programmed with the security option turned on; otherwise, it
contains logic “0”.
Notes:
1. The <v> in the IDCODE field represents the device’s revision
code (in hex), and may vary.
DS026 (v5.2) January 11, 2008
www.xilinx.com
Product Specification
7
R
XC18V00 Series In-System-Programmable Configuration PROMs
The USERCODE instruction gives access to a 32-bit user programmable scratch pad typically used to supply information
about the device’s programmed contents. By using the USERCODE instruction, a user-programmable identification code
can be shifted out for examination. This code is loaded into the USERCODE register during programming of the XC18V00
device. If the device is blank or was not loaded during programming, the USERCODE register contains FFFFFFFFh.
XC18V00 TAP Characteristics
The XC18V00 family performs both in-system programming and IEEE 1149.1 Boundary-Scan (JTAG) testing via a single
four-wire Test Access Port (TAP). This simplifies system designs and allows standard Automatic Test Equipment to perform
both functions. The AC characteristics of the XC18V00 TAP are described as follows.
TAP Timing
Figure 4 shows the timing relationships of the TAP signals. These TAP timing characteristics are identical for both Boundary-
Scan and ISP operations.
X-Ref Target - Figure 4
T
CKMIN1,2
TCK
TMS
T
T
MSS
MSH
T
T
DIH
DIS
TDI
T
DOV
TDO
DS026_04_032702
Figure 4: Test Access Port Timing
TAP AC Parameters
Table 6 shows the timing parameters for the TAP waveforms shown in Figure 4.
Table 6: Test Access Port Timing Parameters
Symbol
TCKMIN1
TCKMIN2
TMSS
Parameter
TCK minimum clock period
Min
100
50
10
25
10
25
–
Max
–
Units
ns
ns
ns
ns
ns
ns
ns
TCK minimum clock period, Bypass mode
TMS setup time
–
–
TMSH
TMS hold time
–
TDIS
TDI setup time
–
TDIH
TDI hold time
–
TDOV
TDO valid delay
25
DS026 (v5.2) January 11, 2008
www.xilinx.com
Product Specification
8
R
XC18V00 Series In-System-Programmable Configuration PROMs
control register is accessible through JTAG, and is set using
the “Parallel mode” setting on the Xilinx iMPACT software.
Serial output is the default configuration mode.
Connecting Configuration PROMs
Connecting the FPGA device with the configuration PROM
(see Figure 5 and Figure 6).
•
The DATA output(s) of the PROM(s) drives the DIN
input of the lead FPGA device.
Master Serial Mode Summary
•
The Master FPGA CCLK output drives the CLK input(s)
of the PROM(s) (in Master Serial and Master
SelectMAP modes only).
The I/O and logic functions of the FPGA’s configurable
logic block (CLB) and their associated interconnections are
established by a configuration program. The program is
loaded either automatically upon power up, or on
command, depending on the state of the three FPGA mode
pins. In Master Serial mode, the FPGA automatically loads
the configuration program from an external memory. Xilinx
PROMs are designed to accommodate the Master Serial
mode.
•
•
The CEO output of a PROM drives the CE input of the
next PROM in a daisy chain (if any).
The OE/RESET pins of all PROMs are connected to
the INIT pins of all FPGA devices. This connection
assures that the PROM address counter is reset before
the start of any (re)configuration, even when a
Upon power-up or reconfiguration, an FPGA enters the
Master Serial mode whenever all three of the FPGA mode-
select pins are Low (M0=0, M1=0, M2=0). Data is read from
the PROM sequentially on a single data line.
Synchronization is provided by the rising edge of the
temporary signal CCLK, which is generated by the FPGA
during configuration.
reconfiguration is initiated by a V
glitch.
CCINT
•
•
The PROM CE input can be driven from the DONE pin.
The CE input of the first (or only) PROM can be driven
by the DONE output of all target FPGA devices,
provided that DONE is not permanently grounded. CE
can also be permanently tied Low, but this keeps the
DATA output active and causes an unnecessary supply
current of 10 mA maximum.
Master Serial mode provides a simple configuration
interface. Only a serial data line, a clock line, and two
control lines are required to configure an FPGA. Data from
the PROM is read sequentially, accessed via the internal
address and bit counters which are incremented on every
valid rising edge of CCLK. If the user-programmable, dual-
function DIN pin on the FPGA is used only for configuration,
it must still be held at a defined level during normal
operation. The Xilinx FPGA families take care of this
automatically with an on-chip pull-up resistor.
Slave Parallel/SelectMap mode is similar to slave serial
mode. The DATA is clocked out of the PROM one byte
per CCLK instead of one bit per CCLK cycle. See FPGA
data sheets for special configuration requirements.
Initiating FPGA Configuration
The XC18V00 devices incorporate a pin named CF that is
controllable through the JTAG CONFIG instruction.
Executing the CONFIG instruction through JTAG pulses the
CF Low once for 300–500 ns, which resets the FPGA and
initiates configuration.
Cascading Configuration PROMs
For multiple FPGAs configured as a serial daisy-chain, or a
single FPGA requiring larger configuration memories in a
serial or SelectMAP configuration mode, cascaded PROMs
provide additional memory (Figure 7 and Figure 8). Multiple
XC18V00 devices can be cascaded by using the CEO
output to drive the CE input of the downstream device. The
clock inputs and the data outputs of all XC18V00 devices in
the chain are interconnected. After the last data from the
first PROM is read, the next clock signal to the PROM
asserts its CEO output Low and drives its DATA line to a
high-Z state. The second PROM recognizes the Low level
on its CE input and enables its DATA output.
The CF pin must be connected to the PROGRAM pin on the
FPGA(s) to use this feature.
The iMPACT software can also issue a JTAG CONFIG
command to initiate FPGA configuration through the “Load
FPGA” setting.
The 20-pin packages do not have a dedicated CF pin. For
20-pin packages, the CF →D4 setting can be used to route
the CF pin function to pin 7 only if the parallel output mode
is not used.
Selecting Configuration Modes
After configuration is complete, address counters of all
cascaded PROMs are reset if the PROM OE/RESET pin
goes Low or CE goes High.
The XC18V00 accommodates serial and parallel methods
of configuration. The configuration modes are selectable
through a user control register in the XC18V00 device. This
DS026 (v5.2) January 11, 2008
www.xilinx.com
Product Specification
9
R
XC18V00 Series In-System-Programmable Configuration PROMs
X-Ref Target - Figure 5
(2)
CCO
V
(1)
V
V
CCO CCINT
(1)
V
V
D0
DIN
MODE PINS
CCINT
(2)
CCO
DIN
CCLK
...OPTIONAL
Slave FPGAs
with identical
configurations
Xilinx FPGA
Master Serial
XC18V00
PROM
DONE
INIT_B (INIT)
PROG_B (PROGRAM)
CLK
CE
CCLK
DONE
...OPTIONAL
Daisy-chained
Slave FPGAs
with different
configurations
CEO
DOUT
DOUT
CCLK
OE/RESET
CF
INIT_B (INIT)
TDI
TMS
TCK
TDO
TDI
PROG_B (PROGRAM)
DONE
TMS
TCK
INIT_B (INIT)
PROG_B (PROGRAM)
TDO
TDI
GND
TMS
TCK
TDO
GND
Notes:
1 For MODE pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet or user guide.
2 For compatible voltages, refer to the appropriate data sheet.
ds026_18_20051007
Figure 5: Master Serial Mode
DS026 (v5.2) January 11, 2008
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Product Specification
10
R
XC18V00 Series In-System-Programmable Configuration PROMs
X-Ref Target - Figure 6
(2)
CCO
V
External
(3)
Oscillator
(1)
8
V
CCO
V
CCINT
(1)
V
D[0:7]
D[0:7]
MODE PINS
RDWR_B
CS_B
CCINT
(2)
V
CCO
Xilinx FPGA
SelectMAP or
Slave-Parallel
XC18V00
PROM
CLK
CE
CCLK
TDI
TMS
TCK
TDO
DONE
CEO
D[0:7]
CCLK
OE/RESET
CF
INIT_B (INIT)
...OPTIONAL
Slave FPGAs
with identical
configurations
PROG_B (PROGRAM)
DONE
TDO
TDI
INIT_B (INIT)
PROG_B (PROGRAM)
TMS
GND
TCK
TDO
GND
Notes:
1 For MODE pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet or user guide.
2 For compatible voltages, refer to the appropriate data sheet.
3 External oscillator required for Virtex/Virtex-E SelectMAP, for Virtex-II/Virtex-II Pro Slave SelectMAP, and for
Spartan-II/Spartan-IIE Slave-Parallel modes.
DS026_19_111207
Figure 6: Master/Slave SelectMAP Mode or Slave Parallel Mode
DS026 (v5.2) January 11, 2008
www.xilinx.com
Product Specification
11
R
XC18V00 Series In-System-Programmable Configuration PROMs
X-Ref Target - Figure 7
(2)
V
V
V
CCO
V
V
CCO
CCO
CCINT
CCINT
(1)
(1)
(1)
V
V
D0
DIN
MODE PINS
DOUT
MODE PINS
V
D0
CCINT
CCINT
(2)
(2)
DIN
V
CCO
CCO
XC18V00
PROM
Xilinx FPGA
Master Serial
Xilinx FPGA
Slave Serial
XC18V00
PROM
First
PROM
(PROM 0)
Cascaded
PROM
(PROM 1)
CLK
CE
CCLK
DONE
CCLK
DONE
CLK
CE
CEO
CEO
OE/RESET
CF
INIT_B (INIT)
INIT_B (INIT)
OE/RESET
CF
TDI
TMS
TCK
TDO
PROG_B (PROGRAM)
PROG_B (PROGRAM)
TDI
TMS
TCK
TDI
TDO
TMS
TCK
TDO
TDI
TDO
TDI
TMS
TCK
TMS
GND
GND
TCK
TDO
GND
GND
Notes:
1 For MODE pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet or user guide.
2 For compatible voltages, refer to the appropriate data sheet.
ds026_16_20051007
Figure 7: Configuring Multiple Devices in Master/Slave Serial Mode
DS026 (v5.2) January 11, 2008
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Product Specification
12
R
XC18V00 Series In-System-Programmable Configuration PROMs
X-Ref Target - Figure 8
(4)
(2)
External
Oscillator
V
CCO
V
V
V
CCINT
V
CCO
CCINT
CCO
(1)
8
8
(3)
D[0:7]
(1)
(3)
(1)
V
V
V
MODE PINS
D[0:7]
MODE PINS
D[0:7](3)
D[0:7](3)
CCINT
(2)
CCINT
(2)
V
CCO
CCO
(3)
(3)
(3)
(3)
RDWR_B
RDWR_B
CS_B
Xilinx FPGA
CS_B
XC18V00
PROM
XC18V00
PROM
Xilinx FPGA
Master
Slave
Serial/SelectMAP
Serial/SelectMAP
First
PROM
(PROM 0)
Cascaded
PROM
(PROM 1)
CCLK
DONE
CCLK
DONE
CLK
CE
CLK
CE
CEO
CEO
INIT_B (INIT)
INIT_B (INIT)
OE/RESET
OE/RESET
TDI
TMS
TCK
TDO
TDI
PROG_B (PROGRAM)
PROG_B (PROGRAM)
CF
CF
TMS
TCK
TDI
TDO
TMS
TCK
GND
TDI
TDO
TDI
TDO
GND
TMS
TCK
TMS
TCK
TDO
GND
GND
Notes:
1
2
3
4
For MODE pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet or user guide.
For compatible voltages, refer to the appropriate data sheet.
Serial modes do not require the D[1:7], RDWR_B, or CS_B pins to be connected.
External oscillator required if CLK is not supplied by an FPGA in Master mode. Refer to the appropriate FPGA data sheet.
DS026_17_111207
Figure 8: Configuring Multiple Devices with Identical Patterns in Master/Slave Serial,
Master/Slave SelectMAP, or Master/Slave Parallel Mode
DS026 (v5.2) January 11, 2008
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Product Specification
13
R
XC18V00 Series In-System-Programmable Configuration PROMs
Reset and Power-On Reset Activation
Standby Mode
At power up, the device requires the V
power supply to
The PROM enters a low-power standby mode whenever CE
is asserted High. The address is reset. The output remains
in a high-Z state regardless of the state of the OE input.
JTAG pins TMS, TDI and TDO can be in a high-Z state or
High. See Table 7.
CCINT
rise monotonically to the nominal operating voltage within
the specified V rise time. If the power supply cannot
CCINT
meet this requirement, then the device might not perform
power-on reset properly. During the power-up sequence,
OE/RESET is held Low by the PROM.
When using the FPGA DONE signal to drive the PROM CE
pin High to reduce standby power after configuration, an
external pull-up resistor should be used. Typically a 330Ω
pull-up resistor is used, but refer to the appropriate FPGA
data sheet for the recommended DONE pin pull-up value. If
the DONE circuit is connected to an LED to indicate FPGA
configuration is complete, and also connected to the PROM
CE pin to enable low-power standby mode, then an external
buffer should be used to drive the LED circuit to ensure valid
transitions on the PROMs CE pin. If low-power standby
mode is not required for the PROM, then the CE pin should
be connected to ground.
Once the required supplies have reached their respective
POR (Power On Reset) thresholds, the OE/RESET release
is delayed (T
minimum) to allow more margin for the
OER
power supplies to stabilize before initiating configuration.
The OE/RESET pin is connected to an external pull-up
resistor and also to the target FPGA's INIT_B pin. For
systems utilizing slow-rising power supplies, an additional
power monitoring circuit can be used to delay the target
configuration until the system power reaches minimum
operating voltages by holding the OE/RESET pin Low.
When OE/RESET is released, the FPGA’s INIT_B pin is
pulled High, allowing the FPGA's configuration sequence to
begin. If the power drops below the power-down threshold
5V Tolerant I/Os
(V
), the PROM resets and OE/RESET is again held
CCPD
The I/Os on each re-programmable PROM are fully 5V tolerant
even through the core power supply is 3.3V. This allows 5V
CMOS signals to connect directly to the PROM inputs without
Low until the after the POR threshold is reached.
OE/RESET polarity is not programmable. These power-up
requirements are shown graphically in Figure 9.
damage. In addition, the 3.3V V
power supply can be
CCINT
For a fully powered Platform Flash PROM, a reset occurs
whenever OE/RESET is asserted (Low) or CE is deasserted
(High). The address counter is reset, CEO is driven High, and
the remaining outputs are placed in a high-Z state.
applied before or after 5V signals are applied to the I/Os. In
mixed 5V/3.3V/2.5V systems, the user pins, the core power
supply (V
), and the output power supply (V
) can have
CCINT
CCO
power applied in any order. This makes the PROM devices
immune to power supply sequencing issues.
X-Ref Target - Figure 9
VCCINT
Recommended Operating Range
Delay or Restart
Configuration
50 ms ramp
200 µs ramp
VCCPOR
VCCPD
A slow-ramping V
supply may still
CCINT
be below the minimum operating
voltage when OE/RESET is released.
In this case, the configuration
sequence must be delayed until both
V
and V
have reached their
CCINT
CCO
TIME (ms)
recommended operating conditions.
TOER
TOER
Power-Up Requirements
TRST
ds026_20_032504
Figure 9: V
CCINT
DS026 (v5.2) January 11, 2008
www.xilinx.com
Product Specification
14
R
XC18V00 Series In-System-Programmable Configuration PROMs
Customer Control Bits
The XC18V00 PROMs have various control bits accessible by the customer. These can be set after the array has been
programmed using “Skip User Array” in Xilinx iMPACT software. The iMPACT software can set these bits to enable the
optional JTAG read security, parallel configuration mode, or CF →D4 pin function. See Table 7.
Table 7: Truth Table for PROM Control Inputs
Control Inputs
OE/RESET
Outputs
CEO
Internal Address
CE
DATA
ICC
High
Low
If address < TC(1): increment
Active
high-Z
High
Low
Active
reduced
If address > TC(1): don’t change
Low
High
Low
Low
High
High
Held reset
Held reset
Held reset
High-Z
High-Z
High-Z
High
High
High
Active
Standby
Standby
Notes:
1. TC = Terminal Count = highest address value. TC + 1 = address 0.
Absolute Maximum Ratings(1,2)
Symbol
VCCINT/VCCO
VIN
Description
Value
Units
Supply voltage relative to GND
–0.5 to +4.0
–0.5 to +5.5
–0.5 to +5.5
–65 to +150
+125
V
V
Input voltage with respect to GND
Voltage applied to high-Z output
Storage temperature (ambient)
Junction temperature
VTS
V
TSTG
° C
° C
TJ
Notes:
1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device
pins can undershoot to –2.0V or overshoot to +7.0V, provided this over- or undershoot lasts less then 10 ns and with the forcing current being
limited to 200 mA.
2. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
Supply Voltage Requirements for Power-On Reset and Power-Down
Symbol
Description
VCCINT rise time from 0V to nominal voltage(2)
POR threshold for the VCCINT supply
Min
0.2
1
Max
50
–
Units
ms
V
TVCC
VCCPOR
TOER
OE/RESET release delay following POR(3)
0
1
ms
ms
TRST
Time required to trigger a device reset when the VCCINT supply drops
below the maximum VCCPD threshold
10
–
VCCPD
Power-down threshold for VCCINT supply
-
1
V
Notes:
1.
V
and V
CCO
supplies can be applied in any order.
CCINT
2. At power up, the device requires the V
power supply to rise monotonically to the nominal operating voltage within the specified T
rise
CCINT
VCC
time. If the power supply cannot meet this requirement, then the device might not perform power-on-reset properly. See Figure 9, page 14.
3. If the V and V supplies do not reach their respective recommended operating conditions before the OE/RESET pin is released,
CCINT
CCO
then the configuration data from the PROM will not be available at the recommended threshold levels. The configuration sequence must be
delayed until both V and V have reached their recommended operating conditions.
CCINT
CCO
4. Typical POR is value is 2.0V.
DS026 (v5.2) January 11, 2008
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Product Specification
15
R
XC18V00 Series In-System-Programmable Configuration PROMs
Recommended Operating Conditions
Symbol
VCCINT
VCCO
Parameter
Min
3.0
3.0
2.3
0
Max
3.6
Units
V
Internal voltage supply
Supply voltage for output drivers for 3.3V operation
Supply voltage for output drivers for 2.5V operation
Low-level input voltage
3.6
V
2.7
V
VIL
VIH
VO
0.8
V
High-level input voltage
2.0
0
5.5
V
Output voltage
VCCO
50
V
TVCC
TA
VCCINT rise time from 0V to nominal voltage(1)
Operating ambient temperature(2)
1
ms
°C
–40
85
Notes:
1. At power up, the device requires the V
power supply to rise monotonically from 0V to nominal voltage within the specified V
rise
CCINT
CCINT
time. If the power supply cannot meet this requirement, then the device might not perform power-on-reset properly. See Figure 9, page 14.
2. Covers the industrial temperature range.
Quality and Reliability Characteristics
Symbol
TDR
Description
Min
20
Max
Units
Years
Cycles
Volts
Data retention
–
–
–
NPE
Program/erase cycles (Endurance)
Electrostatic discharge (ESD)
20,000
2,000
VESD
DC Characteristics Over Operating Conditions
Symbol
Parameter
Test Conditions
IOH = –4 mA
IOH = –500 μA
IOL = 8 mA
Min
Max
–
Units
V
VOH
High-level output voltage for 3.3V outputs
High-level output voltage for 2.5V outputs
Low-level output voltage for 3.3V outputs
Low-level output voltage for 2.5V outputs
Supply current, active mode
2.4
90% VCCO
–
V
VOL
–
–
–
–
–
0.4
0.4
25
10
V
IOL = 500 μA
25 MHz
V
ICC
ICCS
IILJ
mA
mA
μA
Supply current, standby mode
JTAG pins TMS, TDI, and TDO pull-up current (1)
VCCINT = MAX
100
VIN = GND
IIL
IIH
Input leakage current
VCCINT = Max
–10
–10
–
10
10
8
μA
μA
pF
pF
V
IN = GND or VCCINT
Input and output high-Z leakage current
Input capacitance
VCCINT = Max
VIN = GND or VCCINT
CIN
VIN = GND
f = 1.0 MHz
Output capacitance
–
V
OUT = GND
f = 1.0 MHz
14
COUT
Notes:
1. Internal pull-up resistors guarantee valid logic levels at unconnected input pins. These pull-up resistors do not guarantee valid logic levels
when input pins are connected to other circuits.
DS026 (v5.2) January 11, 2008
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Product Specification
16
R
XC18V00 Series In-System-Programmable Configuration PROMs
AC Characteristics Over Operating Conditions for XC18V04 and XC18V02
CE
T
T
SCE
HCE
OE/RESET
CLK
T
HOE
T
T
HC
LC
T
CYC
T
T
DF
OE
T
T
CAC
OH
T
CE
DATA
T
OH
DS026_06_012000
Symbol
TOE
Description
Min
–
Max
Units
ns
OE/RESET to data delay
CE to data delay
10
20
20
-
TCE
–
ns
TCAC
TOH
CLK to data delay
–
ns
Data hold from CE, OE/RESET, or CLK
CE or OE/RESET to data float delay(2)
Clock periods
0
ns
TDF
–
25
–
ns
TCYC
TLC
50
10
10
25
250
250
ns
CLK Low time(3)
–
ns
THC
CLK High time(3)
–
ns
TSCE
THCE
THOE
CE setup time to CLK (guarantees proper counting)(3)
CE High time (guarantees counters are reset)
OE/RESET hold time (guarantees counters are reset)
–
ns
ns
ns
–
–
Notes:
1. AC test load = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with V = 0.0V and V = 3.0V.
IL
IH
5. If T
6. If T
High < 2 μs, T = 2 μs.
HCE
HOE
CE
Low < 2 μs, T = 2 μs.
OE
DS026 (v5.2) January 11, 2008
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Product Specification
17
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XC18V00 Series In-System-Programmable Configuration PROMs
AC Characteristics Over Operating Conditions for XC18V01 and XC18V512
CE
T
T
SCE
HCE
OE/RESET
CLK
T
HOE
T
T
HC
LC
T
CYC
T
T
DF
OE
T
T
CAC
OH
T
CE
DATA
T
OH
DS026_06_012000
Symbol
TOE
Description
Min
–
Max
Units
ns
OE/RESET to data delay
CE to data delay
10
15
15
–
TCE
–
ns
TCAC
TOH
CLK to data delay
–
ns
Data hold from CE, OE/RESET, or CLK
CE or OE/RESET to data float delay(2)
Clock periods
0
ns
TDF
–
25
–
ns
TCYC
TLC
30
10
10
20
250
250
ns
CLK Low time(3)
–
ns
THC
CLK High time(3)
–
ns
TSCE
THCE
THOE
CE setup time to CLK (guarantees proper counting)(3)
CE High time (guarantees counters are reset)
OE/RESET hold time (guarantees counters are reset)
–
ns
ns
ns
–
–
Notes:
1. AC test load = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with V = 0.0V and V = 3.0V.
IL
IH
5. If T
6. If T
High < 2 μs, T = 2 μs.
HCE
HOE
CE
Low < 2 μs, T = 2 μs.
OE
DS026 (v5.2) January 11, 2008
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Product Specification
18
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XC18V00 Series In-System-Programmable Configuration PROMs
AC Characteristics Over Operating Conditions When Cascading for XC18V04 and
XC18V02
OE/RESET
CE
CLK
T
CDF
T
T
OCE
Last Bit
First Bit
DATA
CEO
T
OCK
OOE
DS026_07_020300
Symbol
TCDF
Description
Min
–
Max
25
Units
ns
CLK to data float delay(2,3)
CLK to CEO delay(3)
TOCK
–
20
ns
TOCE
CE to CEO delay(3)
–
20
ns
TOOE
OE/RESET to CEO delay(3)
–
20
ns
Notes:
1. AC test load = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with V = 0.0V and V = 3.0V.
IL
IH
5. For cascade mode:
♦
♦
T
min = T
+ T + FPGA DIN-to-CCLK setup time
CYC
OCK
CE
T
min = T
+ T
CAC
OCK
CE
DS026 (v5.2) January 11, 2008
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Product Specification
19
R
XC18V00 Series In-System-Programmable Configuration PROMs
AC Characteristics Over Operating Conditions When Cascading for XC18V01 and
XC18V512
OE/RESET
CE
CLK
T
CDF
T
T
OCE
Last Bit
First Bit
DATA
CEO
T
OCK
OOE
DS026_07_020300
Symbol
TCDF
Description
Min
–
Max
25
Units
ns
CLK to data float delay(2,3)
CLK to CEO delay(3)
TOCK
–
20
ns
TOCE
CE to CEO delay(3)
–
20
ns
TOOE
OE/RESET to CEO delay(3)
–
20
ns
Notes:
1. AC test load = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with V = 0.0V and V = 3.0V.
IL
IH
5. For cascade mode:
♦
♦
T
min = T
+ T + FPGA DIN-to-CCLK setup time
CYC
OCK
CE
T
min = T
+ T
CAC
OCK
CE
DS026 (v5.2) January 11, 2008
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Product Specification
20
R
XC18V00 Series In-System-Programmable Configuration PROMs
Ordering Information
XC18V04 VQ44 C
Device Number
Operating Range
XC18V04
C = Industrial (T = –40°C to +85°C)
A
Package Type
XC18V02
XC18V01
XC18V512
VQ44 = 44-pin Plastic Quad Flat Package
VQG44 = 44-pin Plastic Quad Flat Package, Pb-free
PC44 = 44-pin Plastic Chip Carrier
PCG44 = 44-pin Plastic Chip Carrier, Pb-free
SO20 = 20-pin Small-Outline Package
SOG20 = 20-pin Small-Outline Package, Pb-free
PC20 = 20-pin Plastic Leaded Chip Carrier
PCG20 = 20-pin Plastic Leaded Chip Carrier, Pb-free
(1)
(1)
(2)
(2)
(2)
(2)
Notes:
1. XC18V04 and XC18V02 only.
2. XC18V01 and XC18V512 only.
Valid Ordering Combinations
XC18V04VQ44C
XC18V04PC44C
XC18V04VQG44C
XC18V04PCG44C
XC18V02VQ44C
XC18V02PC44C
XC18V02VQG44C
XC18V02PCG44C
XC18V01VQ44C
XC18V01PC20C
XC18V01SO20C
XC18V01VQG44C
XC18V01PCG20C
XC18V01SOG20C
XC18V512VQ44C
XC18V512PC20C
XC18V512SO20C
XC18V512VQG44C
XC18V512PCG20C
XC18V512SOG20C
DS026 (v5.2) January 11, 2008
www.xilinx.com
Product Specification
21
R
XC18V00 Series In-System-Programmable Configuration PROMs
Marking Information
44-pin Package
XC18V04 VQ44
Device Number
Operating Range
XC18V04
[no mark] = Industrial (T = –40° C to +85° C)
A
Package Type
VQ44 = 44-pin Plastic Quad Flat Package
XC18V02
XC18V01
XC18V512
VQG44 = 44-pin Plastic Quad Flat Package, Pb-Free
(1)
PC44 = 44-pin Plastic Leaded Chip Carrier
(1)
PCG44 = 44-pin Plastic Leaded Chip Carrier, Pb-Free
Notes:
1. XC18V02 and XC18V04 only.
(1)
20-pin Package
Due to the small size of the serial PROM packages, the complete ordering part number cannot be marked on the
package. The package code is simplified. Device marking is as follows:
XC18V01 S
Device Number
Operating Range
18V01
18V512
[no mark] = Industrial (T = –40° C to +85° C)
A
Package Type
(2)
S = 20-pin Small-Outline Package
SG = 20-pin Small-Outline Package, Pb-free
J = 20-pin Plastic Leaded Chip Carrier
JG = 20-pin Plastic Leaded Chip Carrier, Pb-free
(2)
(2)
(2)
Notes:
1. Refer to XC18V00 PROM product change notices (PCNs) for legacy part markings.
2. XC18V01 and XC18V512 only.
DS026 (v5.2) January 11, 2008
www.xilinx.com
Product Specification
22
R
XC18V00 Series In-System-Programmable Configuration PROMs
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revision
First publication of this early access specification
02/09/99
08/23/99
09/01/99
09/16/99
1.1
Edited text, changed marking, added CF and parallel load
Corrected JTAG order, Security and Endurance data.
1.2
1.3
Corrected SelectMAP diagram, control inputs, reset polarity. Added JTAG and CF description,
256 Kbit and 128 Kbit devices.
01/20/00
02/18/00
04/04/00
06/29/00
2.0
2.1
2.2
2.3
Added Q44 Package, changed XC18xx to XC18Vxx
Updated JTAG configuration, AC and DC characteristics
Removed stand alone resistor on INIT pin in Figure 5. Added Virtex-E and EM parts to FPGA table.
Removed XC18V128 and updated format. Added AC characteristics for XC18V01, XC18V512, and
XC18V256 densities.
11/13/00
2.4
Features: changed 264 MHz to 264 Mb/s at 33 MHz; AC Spec.: TSCE units to ns, THCE CE High time
units to μs. Removed Standby mode statement: “The lower power standby modes available on some
XC18V00 devices are set by the user in the programming software”. Changed 10,000 cycles
endurance to 20,000 cycles.
01/15/01
04/04/01
04/30/01
2.5
2.6
2.7
Updated Figures 5 and 6, added 4.7 resistors. Identification registers: changes ISP PROM product
ID from 06h to 26h.
Updated Figure 8, Virtex SelectMAP mode; added XC2V products to Compatible PROM table;
changed Endurance from 10,000 cycles, 10 years to 20,000, 20 years;
Updated Figure 8: removed Virtex-E in Note 2, fixed SelectMAP mode connections. Under "AC
Characteristics Over Operating Conditions for XC18V04 and XC18V02", changed TSCE from 25 ms
to 25 ns.
06/11/01
09/28/01
2.8
2.9
"AC Characteristics Over Operating Conditions for XC18V01 and XC18V512". Changed Min values
for TSCE from 20 ms to 20 ns and for THCE from 2 ms to 2 μs.
Changed the Boundary-Scan order for the CEO pin in Table 1, updated the configuration bits values
in the table under "Xilinx FPGAs and Compatible PROMs", and added information to the
"Recommended Operating Conditions" table.
11/12/01
12/06/01
02/27/02
03/15/02
03/27/02
06/14/02
07/24/02
09/06/02
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Updated for Spartan-IIE FPGA family.
Changed Figure 5(c).
Updated Table 2 and Figure 8 for the Virtex-II Pro family of devices.
Updated Xilinx software and modified Figure 8 and Figure 5.
Made changes to pages 1-3, 5, 7-11, 13, 14, and 18. Added new Figure 9 and Figure 9.
Made additions and changes to Table 2.
Changed last bullet under Connecting Configuration PROMs, page 9.
Multiple minor changes throughout, plus the addition of Pinout Diagrams, page 4 and the deletion
of Figure 9.
10/31/02
11/18/02
04/17/03
3.8
3.9
Made minor change on Figure 5 (b) and changed orientation of SO20 diagram on page 5.
Added XC2S400E and XC2S600E to Table 2.
3.10
Changes to "Description", "External Programming", and Table 2.
DS026 (v5.2) January 11, 2008
www.xilinx.com
Product Specification
23
R
XC18V00 Series In-System-Programmable Configuration PROMs
06/11/03
4.0
Major revision.
• Added alternate IDCODES to Table 5.
• Discontinued XC18V256 density.
• Eliminated industrial ordering combinations.
• Extended commercial temperature range.
• Added MultiPRO Desktop Tool support.
• Changed THOE and THCE to 250 ns in the tables on <RD Red>page 17 and <RD Red>page 18.
• Made change in capacitance values "DC Characteristics Over Operating Conditions".
• Added Note (3) to Table 1.
• Other minor edits.
12/15/03
04/05/04
4.1
5.0
Added specification (4.7 kΩ) for recommended pull-up resistor on OE/RESET pin to section Reset
and Power-On Reset Activation, page 14.
Added paragraph to section Standby Mode, page 14, concerning use of a pull-up resistor and/or
buffer on the DONE pin.
Major revision.
• Figure 2: Revised configuration bitstream lengths for most Virtex-II FPGAs.
• Replaced previous schematics in Figures 5, 6, 7(a), 7(b), and 7(c) with new Figure 5, Figure 6,
Figure 7, and Figure 8.
• Replaced previous Figure 8 with new Figure 9.
• Replaced previous power-on text section with new Reset and Power-On Reset Activation,
page 14.
• Added specification table Supply Voltage Requirements for Power-On Reset and Power-Down,
page 15.
• Added Footnote (5) to:
♦ Specification table AC Characteristics Over Operating Conditions When Cascading for
XC18V04 and XC18V02, page 19.
♦ Specification table AC Characteristics Over Operating Conditions When Cascading for
XC18V01 and XC18V512, page 20.
• Numerous copyedits and wording changes/clarifications throughout.
07/20/04
03/06/06
5.0.1
5.1
Table 2: Removed reference to XC2VP125 FPGA.
• Added Pb-free packages to Features, page 1, Pinout Diagrams, page 4,"Ordering Information",
Valid Ordering Combinations, page 21and Marking Information, page 22.
• Removed maximum soldering temperature (TSOL) from Absolute Maximum Ratings(1,2)
,
page 15. Refer to Xilinx Device Package User Guide for package soldering guidelines.
• Added information to Table 5 regarding variable JTAG IDCODE revision field.
01/11/08
5.2
• Updated document template.
• Updated URLs.
• Tied RDWR_B and CS_B to GND to ensure valid logic-level Low in FPGA SelectMAP mode in
Figure 6, page 11 and Figure 8, page 13.
• Updated "Marking Information," page 22 for 20-pin packaging.
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED
WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE
SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
DS026 (v5.2) January 11, 2008
www.xilinx.com
Product Specification
24
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