XC18V512PC20C0936 [XILINX]

Configuration Memory, 64KX8, 15ns, Parallel/serial, CMOS, PQCC20, PLASTIC, LCC-20;


型号：	XC18V512PC20C0936
厂家：	XILINX, INC
描述：	Configuration Memory, 64KX8, 15ns, Parallel/serial, CMOS, PQCC20, PLASTIC, LCC-20 内存集成电路
文件：	总30页 (文件大小：607K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

XC18V00 Series In-System

Programmable Configuration

PROMs

DS026 (v3.10) April 17, 2003

Product Specification

•

Dual configuration modes

Features

Serial Slow/Fast configuration (up to 33 MHz)

Parallel (up to 264 Mb/s at 33 MHz)

•

In-system programmable 3.3V PROMs for

configuration of Xilinx FPGAs

Endurance of 20,000 program/erase cycles

•

5V tolerant I/O pins accept 5V, 3.3V and 2.5V signals

3.3V or 2.5V output capability

Program/erase over full commercial/industrial

voltage and temperature range

Available in PC20, SO20, PC44 and VQ44 packages

•

IEEE Std 1149.1 boundary-scan (JTAG) support

Simple interface to the FPGA

Design support using the Xilinx Alliance and

Foundation series software packages.

Cascadable for storing longer or multiple bitstreams

Low-power advanced CMOS FLASH process

•

JTAG command initiation of standard FPGA

configuration

Description

Xilinx introduces the XC18V00 series of in-system program-

mable configuration PROMs (Figure 1). Devices in this 3.3V

family include a 4-megabit, a 2-megabit, a 1-megabit, a

When the FPGA is in Master-SelectMAP mode, the FPGA

generates a configuration clock that drives the PROM.

When the FPGA is in Slave-Parallel or Slave-SelectMAP

Mode, an external oscillator generates the configuration

clock that drives the PROM and the FPGA. After CE and OE

are enabled, data is available on the PROMs DATA (D0-D7)

pins. New data is available a short access time after each

rising clock edge. The data is clocked into the FPGA on the

following rising edge of the CCLK. Neither Slave-Parallel

nor SelectMAP utilize a Length Count, so a free-running

oscillator can be used in the Slave-Parallel or Slave-

SelecMAP modes.

512-Kbit, and

256-Kbit PROM that provide an

easy-to-use, cost-effective method for re-programming and

storing large Xilinx FPGA or CPLD configuration bitstreams.

When the FPGA is in Master Serial mode, it generates a

configuration clock that drives the PROM. A short access

time after CE and OE are enabled, data is available on the

PROM DATA (D0) pin that is connected to the FPGA D

pin. New data is available a short access time after each ris-

ing clock edge. The FPGA generates the appropriate num-

ber of clock pulses to complete the configuration. When the

FPGA is in Slave Serial mode, the PROM and the FPGA are

clocked by an external clock.

Multiple devices can be concatenated by using the CEO

output to drive the CE input of the following device. The

clock inputs and the DATA outputs of all PROMs in this

chain are interconnected. All devices are compatible and

can be cascaded with other members of the family or with

the XC17V00 one-time programmable Serial PROM family.

other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature,

application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may

require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties

or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.

DS026 (v3.10) April 17, 2003

www.xilinx.com

Product Specification

1-800-255-7778

XC18V00 Series In-System Programmable Configuration PROMs

CLK CE

OE/Reset

TCK

Data

Control

CEO

Serial

Parallel

Interface

TMS

TDI

and

JTAG

Interface

Memory

D0 DATA

Serial or Parallel Mode

Data

Address

TDO

D[1:7]

Parallel Interface

DS026_01_090502

Figure 1: XC18V00 Series Block Diagram

Pinout and Pin Description

Pins not listed are "no connects."

Table 1: Pin Names and Descriptions

Boundary

Scan

Order

20-pin

SOIC &

PLCC

Name

44-pin

VQFP

44-pin

PLCC

Function

Pin Description

DATA OUT D0 is the DATA output pin to provide data for

configuring an FPGA in serial mode.

OUTPUT

ENABLE

DATA OUT D0-D7 are the output pins to provide parallel

data for configuring a Xilinx FPGA in

OUTPUT

ENABLE

Slave-Parallel/SelectMap mode.

DATA OUT

OUTPUT

ENABLE

DATA OUT

OUTPUT

ENABLE

(1)

DATA OUT

OUTPUT

ENABLE

DATA OUT

OUTPUT

ENABLE

DATA OUT

OUTPUT

ENABLE

DATA OUT

OUTPUT

ENABLE

www.xilinx.com

DS026 (v3.10) April 17, 2003

1-800-255-7778

Product Specification

XC18V00 Series In-System Programmable Configuration PROMs

Table 1: Pin Names and Descriptions (Continued)

Boundary

20-pin

Name

Scan

Order

44-pin

VQFP

44-pin

PLCC

SOIC &

PLCC

Function

Pin Description

CLK

DATA IN

Each rising edge on the CLK input increments

the internal address counter if both CE is Low

and OE/RESET is High.

OE/

RESET

DATA IN

When Low, this input holds the address

counter reset and the DATA output is in a

high-impedance state. This is a bidirectional

open-drain pin that is held Low while the

PROM is reset. Polarity is NOT

DATA OUT

OUTPUT

ENABLE

programmable.

DATA IN

When CE is High, the device is put into

low-power standby mode, the address

counter is reset, and the DATA pins are put in

a high-impedance state.

(1)

DATA OUT Allows JTAG CONFIG instruction to initiate

FPGA configuration without powering down

OUTPUT

ENABLE

FPGA. This is an open-drain output that is

pulsed Low by the JTAG CONFIG command.

CEO

DATA OUT Chip Enable Output (CEO) is connected to

the CE input of the next PROM in the chain.

OUTPUT

ENABLE

This output is Low when CE is Low and

OE/RESET input is High, AND the internal

address counter has been incremented

beyond its Terminal Count (TC) value. CEO

returns to High when OE/RESET goes Low or

CE goes High.

GND

TMS

GND is the ground connection.

6, 18, 28 & 3, 12, 24

& 34

MODE

SELECT

The state of TMS on the rising edge of TCK

determines the state transitions at the Test

Access Port (TAP) controller. TMS has an

internal 50K ohm resistive pull-up on it to

provide a logic “1” to the device if the pin is not

driven.

TCK

TDI

CLOCK

DATA IN

This pin is the JTAG test clock. It sequences

the TAP controller and all the JTAG test and

programming electronics.

This pin is the serial input to all JTAG

instruction and data registers. TDI has an

internal 50K ohm resistive pull-up on it to

provide a logic “1” to the system if the pin is

not driven.

TDO

DATA OUT This pin is the serial output for all JTAG

instruction and data registers. TDO has an

internal 50K ohm resistive pull-up on it to

provide a logic “1” to the system if the pin is

not driven.

Positive 3.3V supply voltage for internal logic

and input buffers.

17, 35 &

23, 41 &

18 & 20

DS026 (v3.10) April 17, 2003

www.xilinx.com

Product Specification

1-800-255-7778

XC18V00 Series In-System Programmable Configuration PROMs

Table 1: Pin Names and Descriptions (Continued)

Boundary

Scan

Order

20-pin

SOIC &

PLCC

Name

44-pin

VQFP

44-pin

PLCC

Function

Pin Description

Positive 3.3V or 2.5V supply voltage

connected to the output voltage drivers.

8, 16, 26 &

14, 22,

32 & 42

CCO

No connects.

1, 2, 4,

11, 12, 20,

22, 23, 24,

30, 32, 33,

34, 37, 39,

1, 6, 7, 8,

10, 17,

18, 26,

28, 29,

30, 36,

38, 39,

40, 43

Notes:

1. By default, pin 7 is the D4 pin in the 20-pin packages. However, CF --> D4 programming option can be set to override the default and

route the CF function to pin 7 in the Serial mode.

Pinout Diagrams

TDI

TDO

TDI

TDO

TMS

GND

TCK

TMS

GND

TCK

PC44

Top View

VQ44

Top View

GND

CCO

DS026_12_090602

DS026_13_090602

www.xilinx.com

1-800-255-7778

DS026 (v3.10) April 17, 2003

Product Specification

XC18V00 Series In-System Programmable Configuration PROMs

DATA(D0)

VCC

VCCO

VCC

TDO

CEO

GND

CLK

TDI

TMS

TCK

SO20

Top

View

VCC

TDO

TDI

TMS

TCK

PC20

Top View

CF/D4*

OE/RESET

D4/CF*

OE/RESET

*See pin

descriptions.

*See pin descriptions.

DS026_14_111502

DS026_15_111502

Xilinx FPGAs and Compatible PROMs

Table 2 provides a list of Xilinx FPGAs and compatible

PROMs.

Table 2: Xilinx FPGAs and Compatible PROMs

Configuration

Bits

XC18V00

Solution

Device

Table 2: Xilinx FPGAs and Compatible PROMs

XC2V4000

XC2V6000

15,659,936

21,849,504

4 of XC18V04

Configuration

Bits

XC18V00

Solution

Device

XC2VP2

XC2VP4

XC2VP7

5 of XC18V04 +

XC18V02

1,305,440

3,006,560

4,485,472

XC18V02

XC18V04

XC2V8000

XCV50

29,063,072

559,200

7 of XC18V04

XC18V01

XC18V02

XC18V04

XC18V04 +

XC18V512

XCV100

XCV150

XCV200

XCV300

XCV400

XCV600

XCV800

781,216

XC2VP20

XC2VP30

XC2VP40

XC2VP50

XC2VP70

8,214,624

11,364,608

15,563,264

19,021,472

25,604,096

2 of XC18V04

3 of XC18V04

4 of XC18V04

5 of XC18V04

1,040,096

1,335,840

1,751,808

2,546,048

3,607,968

4,715,616

6 of XC18V04 +

XC18V512

XC18V04 +

XC18V512

XC2VP100

XC2VP125

33,645,312

42,782,208

8 of XC18V04 +

XC18V256

XCV1000

6,127,744

XC18V04 +

XC18V02

10 of XC18V04 +

XC18V01

XCV50E

XCV100E

XCV200E

XCV300E

XCV400E

XCV405E

XCV600E

XCV812E

XCV1000E

630,048

863,840

XC18V01

XC2V40

XC2V80

360,096

635,296

XC18V512

XC18V01

XC18V02

XC18V04

1,442,016

1,875,648

2,693,440

3,430,400

3,961,632

6,519,648

6,587,520

XC18V02

XC2V250

XC2V500

XC2V1000

XC2V1500

1,697,184

2,761,888

4,082,592

5,659,296

XC18V02

XC18V04

+ XC18V02

XC18V04

2 of XC18V04

XC2V2000

XC2V3000

7,492,000

2 of XC18V04

3 of XC18V04

10,494,368

DS026 (v3.10) April 17, 2003

Product Specification

www.xilinx.com

1-800-255-7778

XC18V00 Series In-System Programmable Configuration PROMs

Table 2: Xilinx FPGAs and Compatible PROMs

In-System Programming

Configuration

Bits

XC18V00

Solution

In-System Programmable PROMs can be programmed indi-

vidually, or two or more can be daisy-chained together and

programmed in-system via the standard 4-pin JTAG proto-

col as shown in Figure 2. In-system programming offers

quick and efficient design iterations and eliminates unnec-

essary package handling or socketing of devices. The Xilinx

development system provides the programming data

sequence using either Xilinx iMPACT software and a

download cable, a third-party JTAG development system, a

JTAG-compatible board tester, or a simple microprocessor

interface that emulates the JTAG instruction sequence. The

iMPACT software also outputs serial vector format (SVF)

files for use with any tools that accept SVF format and with

automatic test equipment.

Device

XCV1600E

XCV2000E

XCV2600E

XCV3200E

XC2S15

8,308,992

10,159,648

12,922,336

16,283,712

197,696

2 of XC18V04

3 of XC18V04

4 of XC18V04

XC18V256

XC18V512

XC18V01

XC2S30

336,768

XC2S50

559,200

XC2S100

XC2S150

XC2S200

XC2S50E

XC2S100E

XC2S150E

XC2S200E

XC2S300E

XC2S400E

XC2S600E

XC3S50

781,216

XC18V01

1,040,096

1,335,840

630,048

XC18V01

All outputs are held in a high-impedance state or held at

clamp levels during in-system programming.

XC18V02

OE/RESET

XC18V01

The ISP programming algorithm requires issuance of a

reset that causes OE to go Low.

863,840

XC18V01

1,134,496

1,442,016

1,875,648

2,693,440

3,961,632

326,784

XC18V02

External Programming

XC18V02

Xilinx reprogrammable PROMs can also be programmed by

the Xilinx HW-130, Xilinx MultiPRO, or a third-party device

programmer. This provides the added flexibility of using

pre-programmed devices with an in-system programmable

option for future enhancements and design changes.

XC18V02

XC18V04

XC18V512

XC18V01

Reliability and Endurance

XC3S200

XC3S400

XC3S1000

XC3S1500

1,047,616

1,699,136

3,223,488

5,214,784

Xilinx in-system programmable products provide a guaran-

teed endurance level of 20,000 in-system program/erase

cycles and a minimum data retention of 20 years. Each

device meets all functional, performance, and data retention

specifications within this endurance limit.

XC18V02

XC18V04

XC18V04 +

XC18V02

XC3S2000

XC3S4000

XC3S5000

7,673,024

11,316,864

13,271,936

2 of XC18V04

3 of XC18V04

Design Security

The Xilinx in-system programmable PROM devices incorpo-

rate advanced data security features to fully protect the pro-

gramming data against unauthorized reading via JTAG.

Table 3 shows the security setting available.

3 of XC18V04 +

XC18V01

The read security bit can be set by the user to prevent the

internal programming pattern from being read or copied via

JTAG. When set, it allows device erase. Erasing the entire

device is the only way to reset the read security bit.

Capacity

Devices

XC18V04

XC18V02

XC18V01

XC18V512

XC18V256

Configuration Bits

4,194,304

2,097,152

1,048,576

524,288

Table 3: Data Security Options

Default = Reset

Set

Read Allowed

Program/Erase Allowed

Verify Allowed

Read Inhibited via JTAG

Program/Erase Allowed

Verify Inhibited

262,144

www.xilinx.com

1-800-255-7778

DS026 (v3.10) April 17, 2003

Product Specification

XC18V00 Series In-System Programmable Configuration PROMs

Figure 2: In-System Programming Operation (a) Solder Device to PCB and (b) Program Using Download Cable

IEEE 1149.1 Boundary-Scan (JTAG)

The XC18V00 family is fully compliant with the IEEE Std.

1149.1 Boundary-Scan, also known as JTAG. A Test

Table 4: Boundary Scan Instructions

Boundary-Scan

Command

Binary

Code [7:0]

Access Port (TAP) and registers are provided to support all

required boundary scan instructions, as well as many of the

optional instructions specified by IEEE Std. 1149.1. In addi-

tion, the JTAG interface is used to implement in-system pro-

gramming (ISP) to facilitate configuration, erasure, and

verification operations on the XC18V00 device.

Description

Required Instructions

BYPASS

11111111 Enables BYPASS

SAMPLE/

PRELOAD

00000001 Enables boundary-scan

SAMPLE/PRELOAD operation

Table 4 lists the required and optional boundary-scan

instructions supported in the XC18V00. Refer to the IEEE

Std. 1149.1 specification for a complete description of

boundary-scan architecture and the required and optional

instructions.

EXTEST

00000000 Enables boundary-scan

EXTEST operation

Optional Instructions

CLAMP

11111010 Enables boundary-scan

CLAMP operation

Instruction Register

HIGHZ

11111100 all outputs in high-impedance

state simultaneously

The Instruction Register (IR) for the XC18V00 is eight bits

wide and is connected between TDI and TDO during an

instruction scan sequence. In preparation for an instruction

scan sequence, the instruction register is parallel loaded

with a fixed instruction capture pattern. This pattern is

shifted out onto TDO (LSB first), while an instruction is

shifted into the instruction register from TDI. The detailed

composition of the instruction capture pattern is illustrated

in Figure 3.

IDCODE

11111110 Enables shifting out

32-bit IDCODE

USERCODE

11111101 Enables shifting out

32-bit USERCODE

XC18V00 Specific Instructions

CONFIG 11101110 Initiates FPGA configuration

by pulsing CF pin Low

The ISP Status field, IR(4), contains logic “1” if the device is

currently in ISP mode; otherwise, it contains logic “0”. The

Security field, IR(3), contains logic “1” if the device has been

programmed with the security option turned on; otherwise, it

contains logic “0”.

DS026 (v3.10) April 17, 2003

Product Specification

www.xilinx.com

1-800-255-7778

XC18V00 Series In-System Programmable Configuration PROMs

Table 5 lists the IDCODE register values for the XC18V00

devices.

IR[7:5]

IR[4]

IR[3]

IR[2] IR[1:0]

0 1

TDI->

0 0 0

ISP

Status

Security

->TDO

Table 5: IDCODES Assigned to XC18V00 Devices

ISP-PROM

XC18V01

XC18V02

XC18V04

XC18V256

XC18V512

IDCODE

Notes:

1. IR(1:0) = 01 is specified by IEEE Std. 1149.1

05024093h

05025093h

05026093h

05022093h

05023093h

Figure 3: Instruction Register Values Loaded into IR as

Part of an Instruction Scan Sequence

Boundary Scan Register

The boundary-scan register is used to control and observe

the state of the device pins during the EXTEST, SAM-

PLE/PRELOAD, and CLAMP instructions. Each output pin

on the XC18V00 has two register stages that contribute to

the boundary-scan register, while each input pin only has

one register stage.

The USERCODE instruction gives access to a 32-bit user

programmable scratch pad typically used to supply informa-

tion about the device’s programmed contents. By using the

USERCODE instruction, a user-programmable identifica-

tion code can be shifted out for examination. This code is

loaded into the USERCODE register during programming of

the XC18V00 device. If the device is blank or was not

loaded during programming, the USERCODE register con-

tains FFFFFFFFh.

For each output pin, the register stage nearest to TDI con-

trols and observes the output state, and the second stage

closest to TDO controls and observes the High-Z enable

state of the pin.

For each input pin, the register stage controls and observes

the input state of the pin.

XC18V00 TAP Characteristics

Identification Registers

The XC18V00 family performs both in-system programming

and IEEE 1149.1 boundary-scan (JTAG) testing via a single

4-wire Test Access Port (TAP). This simplifies system

designs and allows standard Automatic Test Equipment to

perform both functions. The AC characteristics of the

XC18V00 TAP are described as follows.

The IDCODE is a fixed, vendor-assigned value that is used

to electrically identify the manufacturer and type of the

device being addressed. The IDCODE register is 32 bits

wide. The IDCODE register can be shifted out for examina-

tion by using the IDCODE instruction. The IDCODE is avail-

able to any other system component via JTAG.

The IDCODE register has the following binary format:

vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1

where

TAP Timing

Figure 4 shows the timing relationships of the TAP signals.

These TAP timing characteristics are identical for both

boundary-scan and ISP operations.

v = the die version number

f = the family code (50h for XC18V00 family)

a = the ISP PROM product ID (26h for the XC18V04)

c = the company code (49h for Xilinx)

Note: The LSB of the IDCODE register is always read as

logic “1” as defined by IEEE Std. 1149.1.

www.xilinx.com

1-800-255-7778

DS026 (v3.10) April 17, 2003

Product Specification

XC18V00 Series In-System Programmable Configuration PROMs

CKMIN1,2

TCK

TMS

MSS

MSH

DIS

DIH

TDI

DOV

TDO

DS026_04_032702

Figure 4: Test Access Port Timing

TAP AC Parameters

Table 6 shows the timing parameters for the TAP waveforms shown in Figure 4

Table 6: Test Access Port Timing Parameters

Symbol

Parameter

TCK minimum clock period

Min

100

Max

Units

CKMIN1

CKMIN2

TCK minimum clock period, Bypass Mode

TMS setup time

MSS

TMS hold time

MSH

TDI setup time

DIS

TDI hold time

DIH

TDO valid delay

DOV

Connecting Configuration PROMs

Connecting the FPGA device with the configuration PROM

(see Figure 5 and Figure 6).

•

The PROM CE input can be driven from the DONE pin.

The CE input of the first (or only) PROM can be driven

by the DONE output of all target FPGA devices,

provided that DONE is not permanently grounded. CE

can also be permanently tied Low, but this keeps the

DATA output active and causes an unnecessary supply

current of 10 mA maximum.

•

The DATA output(s) of the PROM(s) drives the D

input of the lead FPGA device.

The Master FPGA CCLK output drives the CLK input(s)

of the PROM(s) (in Master-Serial and

Master-SelectMAP modes only).

Slave-Parallel/SelectMap mode is similar to slave serial

mode. The DATA is clocked out of the PROM one byte

per CCLK instead of one bit per CCLK cycle. See FPGA

data sheets for special configuration requirements.

•

The CEO output of a PROM drives the CE input of the

next PROM in a daisy chain (if any).

The OE/RESET pins of all PROMs are connected to

the INIT pins of all FPGA devices. This connection

assures that the PROM address counter is reset before

the start of any (re)configuration, even when a

Initiating FPGA Configuration

The XC18V00 devices incorporate a pin named CF that is

controllable through the JTAG CONFIG instruction. Execut-

ing the CONFIG instruction through JTAG pulses the CF low

for 300-500 ns, which resets the FPGA and initiates config-

uration.

reconfiguration is initiated by a V glitch.

The CF pin must be connected to the PROGRAM pin on the

FPGA(s) to use this feature.

DS026 (v3.10) April 17, 2003

Product Specification

www.xilinx.com

1-800-255-7778

XC18V00 Series In-System Programmable Configuration PROMs

The iMPACT software can also issue a JTAG CONFIG com-

mand to initiate FPGA configuration through the “Load

FPGA” setting.

provided by the rising edge of the temporary signal CCLK,

which is generated by the FPGA during configuration.

Master Serial Mode provides a simple configuration inter-

face. Only a serial data line, a clock line, and two control

lines are required to configure an FPGA. Data from the

PROM is read sequentially, accessed via the internal

address and bit counters which are incremented on every

valid rising edge of CCLK. If the user-programmable,

The 20-pin packages do not have a dedicated CF pin. For

20-pin packages, the CF --> D4 setting can be used to route

the CF pin function to pin 7 only if the parallel output mode

is not used.

dual-function D pin on the FPGA is used only for configu-

Selecting Configuration Modes

ration, it must still be held at a defined level during normal

operation. The Xilinx FPGA families take care of this auto-

matically with an on-chip pull-up resistor.

The XC18V00 accommodates serial and parallel methods

of configuration. The configuration modes are selectable

through a user control register in the XC18V00 device. This

control register is accessible through JTAG, and is set using

the “Parallel mode” setting on the Xilinx iMPACT software.

Serial output is the default configuration mode.

Cascading Configuration PROMs

For multiple FPGAs configured as a serial daisy-chain, or a

single FPGA requiring larger configuration memories in a

serial or SelectMAP configuration mode, cascaded PROMs

provide additional memory (Figure 5). Multiple XC18V00

devices can be concatenated by using the CEO output to

drive the CE input of the downstream device. The clock

inputs and the data outputs of all XC18V00 devices in the

chain are interconnected. After the last data from the first

PROM is read, the next clock signal to the PROM asserts its

CEO output Low and drives its DATA line to a high-imped-

ance state. The second PROM recognizes the Low level on

its CE input and enables its DATA output. See Figure 7.

Master Serial Mode Summary

The I/O and logic functions of the Configurable Logic Block

(CLB) and their associated interconnections are established

by a configuration program. The program is loaded either

automatically upon power up, or on command, depending

on the state of the three FPGA mode pins. In Master Serial

mode, the FPGA automatically loads the configuration pro-

gram from an external memory. Xilinx PROMs are designed

to accommodate the Master Serial mode.

Upon power-up or reconfiguration, an FPGA enters the Mas-

ter Serial mode whenever all three of the FPGA mode-select

pins are Low (M0=0, M1=0, M2=0). Data is read from the

PROM sequentially on a single data line. Synchronization is

After configuration is complete, address counters of all cas-

caded PROMs are reset if the PROM OE/RESET pin goes

Low or CE goes High.

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1-800-255-7778

DS026 (v3.10) April 17, 2003

Product Specification

XC18V00 Series In-System Programmable Configuration PROMs

Vcco

(See Note 2)

Vcco Vcc

(See Note 2)

Vcco Vcc

(See Note 2)

4.7K

Vcc

DIN

MODE PINS

(See Note 1)

MODE PINS

(See Note 1)

DIN

DOUT

Vcc

Xilinx

FPGA

Xilinx

FPGA

Vcco

XC18V00

Vcco

(See

4.7K

Master

Serial

Slave

Serial

Cascaded

PROM

First

PROM

Note

TDI

CLK

TDI

CLK

CCLK

DONE

CCLK

TDI

TMS

DONE

TCK

CEO

TCK

CEO

TCK

TDO

OE/RESET

INIT

PROGRAM

TDI

TDO

GND

TMS

TCK

TMS

TCK

TDO

Notes:

For Mode pin connections and DONE pin pullup value, refer to appropriate FPGA data sheet.

For compatible voltages, refer to the appropriate FPGA data sheet.

DS026_08_011503

Figure 5: Configuring Multiple Devices in Master/Slave Serial Mode

(2)

Vcco

(2)

Vcco

(2)

Vcco Vcc

Vcc

4.7K

(1)

MODE PINS

**D[0:7]

(3)

(D[0:7]

(3)

D[0:7]

Vcc

D[0:7]

Vcc

Xilinx

Virtex-II

FPGA

Xilinx

Virtex-II

FPGA

Vcco

(2)

Vcco

XC18V00

4.7K

Master

Serial/

SelectMAP

Slave

Serial/

SelectMAP

Cascaded

PROM

First

PROM

(1)

TDI

CLK

TDI

CLK

CCLK

TDI

TMS

DONE

TCK

CEO

TCK

CEO

TCK

TDO

OE/RESET

INIT

PROGRAM

TDI

TDO

GND

TMS

TCK

TMS

TCK

TDO

Notes:

For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet.

For compatible voltges, refer to the appropriate FPGA data sheet.

Master/Slave Serial Mode does not require D[1:7] to be connected.

DS026_09_011503

Figure 6: Configuring Multiple Virtex-II Devices with Identical Patterns in Master/Slave or Serial/SelectMAP Modes

DS026 (v3.10) April 17, 2003

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Product Specification

1-800-255-7778

XC18V00 Series In-System Programmable Configuration PROMs

OPTIONAL

Daisy-chained

FPGAs with

different

DOUT

configurations

FPGA

(2)

Vcco

OPTIONAL

Slave FPGAs

with identical

configurations

(2)

4.7K

(1)

Modes

(2)

Vcco

Vcc

(2)

Vcco

Vcc

Vcco

(2)

Vcco

4.7K

CCO

DATA

CC CCO

DATA

CLK

DIN

First

PROM

Cascaded

PROM

CCLK

CLK

CEO

DONE

INIT

OE/RESET

PROGRAM

Notes:

For Mode pin connections and Done pullup value, refer to the appropriate FPGA data sheet.

For compatible voltages, refer to the appropriate FPGA data sheet.

(a) Master Serial Mode

(1)

I/O

(4)

External

Osc

Vcc

Vcco

Vcc

Vcco

(3)

WRITE

(2)

Modes

Vcco

VIRTEX

(4)

Vcco

(4)

Select MAP

(4)

Vcco

BUSY

4.7K

XC18Vxx

(2)

4.7K

CLK

D[0:7]

CLK

CCLK

D[0:7]

DONE

INIT

PROGRAM

CEO

D[0:7]

OE/RESET

Notes:

CS and WRITE must be either driven Low or pulled down externally. One option is shown.

For Mode pin connections and Done pullup value, refer to the appropriate FPGA data sheet.

External oscillator required for Virtex/Virtex-E SelectMAP or Virtex-II/Virtex-II Pro Slave-SelectMAP modes.

For compatible voltages, refer to the appropriate FPGA data sheet.

(b) Virtex/Virtex-E/Virtex-II/Virtex-II Pro SelectMAP Mode

(1)

I/O

(4)

Vcco

(1)

External

Osc

Vcc

I/O

(3)

(2)

Modes

WRITE

Vcco

Spartan-II,

Spartan-IIE

(4)

Vcco

CCO

(4)

BUSY

3.3K

XC18Vxx

(2)

4.7K

CLK

CCLK

D[0:7]

DONE

INIT

PROGRAM

D[0:7]

OE/RESET

Notes:

CS and WRITE must be pulled down to be used as I/O. One option is shown.

For Mode pin connections and Done pullup value and if Drive Done configuration option is not active, refer to

the appropriate FPGA data sheet.

External oscillator required for Spartan-II/Spartan-IIE Slave-Parallel modes.

4 For compatible voltages, refer to the appropriate FPGA data sheet.

DS026_05_011503

Figure 7: (a) Master Serial Mode (b) Virtex/Virtex-E/Virtex-II Pro SelectMAP Mode (c) Spartan-II/Spartan-IIE

Slave-Parallel Mode (dotted lines indicate optional connection)

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DS026 (v3.10) April 17, 2003

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Product Specification

XC18V00 Series In-System Programmable Configuration PROMs

Reset Activation

Standby Mode

On power up, OE/RESET is held low until the XC18V00 is

active (1 ms). OE/RESET is connected to an external resis-

tor to pull OE/RESET HIGH releasing the FPGA INIT and

allowing configuration to begin. If the power drops below

2.0V, the PROM resets. OE/RESET polarity is not program-

mable. See Figure 8 for power-up requirements.

The PROM enters a low-power standby mode whenever CE

is asserted High. The address is reset. The output remains

in a high-impedance state regardless of the state of the OE

input. JTAG pins TMS, TDI and TDO can be in a

high-impedance state or High.

5V Tolerant I/Os

The I/Os on each re-programmable PROM are fully 5V tol-

erant even through the core power supply is 3.3V. This

allows 5V CMOS signals to connect directly to the PROM

3.6V

Recommended Operating Range

3.0V

inputs without damage. In addition, the 3.3V V

power

Recommended

supply can be applied before or after 5V signals are applied

to the I/Os. In mixed 5V/3.3V/2.5V systems, the user pins,

V_CCRise

Time

the core power supply (V ), and the output power supply

) can have power applied in any order. This makes

CCO

the PROM devices immune to power supply sequencing

issues.

0ms 1ms

50ms

Time (ms)

Customer Control Bits

ds026_10_032702

The XC18V00 PROMs have various control bits accessible

by the customer. These can be set after the array has been

programmed using “Skip User Array” in Xilinx iMPACT soft-

ware. See Table 7.

Figure 8: V Power-Up Requirements

Table 7: Truth Table for PROM Control Inputs

Control Inputs

Outputs

OE/RESET

Internal Address

DATA

CEO

(1)

High

Low

If address < TC : increment

Active

High-Z

High

Low

Active

Reduced

(1)

If address > TC : don’t change

Low

High

Low

High

Held reset

High-Z

High

Active

Standby

Notes:

1. TC = Terminal Count = highest address value. TC + 1 = address 0.

DS026 (v3.10) April 17, 2003

Product Specification

www.xilinx.com

1-800-255-7778

XC18V00 Series In-System Programmable Configuration PROMs

Absolute Maximum Ratings^(1,2)

Symbol

Description

Supply voltage relative to GND

Value

–0.5 to +4.0

–0.5 to +5.5

–65 to +150

+260

Units

Input voltage with respect to GND

Voltage applied to High-Z output

Storage temperature (ambient)

Maximum soldering temperature (10s @ 1/16 in.)

Junction temperature

°C

STG

SOL

+150

Notes:

1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the

device pins can undershoot to –2.0V or overshoot to +7.0V, provided this over- or undershoot lasts less then 10 ns and with the

forcing current being limited to 200 mA.

2. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress

ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions

is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.

Recommended Operating Conditions

Symbol

Parameter

Min

3.0

2.3

Max

3.6

2.7

0.8

5.5

Units

Internal voltage supply (T = 0°C to +70°C)

Commercial

Industrial

CCINT

Internal voltage supply (T = –40°C to +85°C)

Supply voltage for output drivers for 3.3V operation

Supply voltage for output drivers for 2.5V operation

Low-level input voltage

CCO

High-level input voltage

2.0

Output voltage

CCO

(1)

rise time from 0V to nominal voltage

VCC

Notes:

1. At power up, the device requires the V power supply to monotonically rise from 0V to nominal voltage within the specified V rise

time. If the power supply cannot meet this requirement, then the device might not perform power-on-reset properly. See Figure 8.

Quality and Reliability Characteristics

Symbol

Description

Min

Max

Units

Years

Cycles

Volts

Data retention

Program/erase cycles (Endurance)

Electrostatic discharge (ESD)

20,000

2,000

ESD

DC Characteristics Over Operating Conditions

Symbol

Parameter

Test Conditions

Min

Max

Units

High-level output voltage for 3.3V outputs

High-level output voltage for 2.5V outputs

= –4 mA

2.4

= –500 µA

90% V

CCO

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DS026 (v3.10) April 17, 2003

1-800-255-7778

Product Specification

XC18V00 Series In-System Programmable Configuration PROMs

Symbol

Parameter

Test Conditions

Min

Max

0.4

Units

Low-level output voltage for 3.3V outputs

Low-level output voltage for 2.5V outputs

Supply current, active mode

= 8 mA

= 500 µA

25 MHz

µA

Supply current, standby mode

CCS

JTAG pins TMS, TDI, and TDO

MAX

CC =

–100

ILJ

= GND

Input leakage current

= Max

–10

µA

= GND or V

= Max

Input and output High-Z leakage current

Input and output capacitance

= GND or V

and

= GND

f = 1.0 MHz

OUT

DS026 (v3.10) April 17, 2003

Product Specification

www.xilinx.com

1-800-255-7778

XC18V00 Series In-System Programmable Configuration PROMs

AC Characteristics Over Operating Conditions for XC18V04 and XC18V02

SCE

HCE

OE/RESET

CLK

HOE

CYC

CAC

DATA

DS026_06_012000

Symbol

Description

Min

Max

Units

OE/RESET to data delay

CE to data delay

CLK to data delay

CAC

Data hold from CE, OE/RESET, or CLK

(2)

CE or OE/RESET to data float delay

Clock periods

CYC

(3)

CLK Low time

(3)

CLK High time

(3)

CE setup time to CLK (guarantees proper counting)

CE High time (guarantees counters are reset)

SCE

HCE

HOE

OE/RESET hold time (guarantees counters are reset)

Notes:

1. AC test load = 50 pF.

2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.

3. Guaranteed by design, not tested.

4. All AC parameters are measured with V = 0.0V and V = 3.0V.

5. If T

6. If T

High < 2 µs, T = 2 µs.

HCE

Low < 2 µs, T = 2 µs.

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DS026 (v3.10) April 17, 2003

1-800-255-7778

Product Specification

XC18V00 Series In-System Programmable Configuration PROMs

AC Characteristics Over Operating Conditions for XC18V01, XC18V512, and

XC18V256

SCE

HCE

OE/RESET

CLK

HOE

CYC

CAC

DATA

DS026_06_012000

Symbol

Description

Min

Max

Units

OE/RESET to data delay

CE to data delay

CLK to data delay

CAC

Data hold from CE, OE/RESET, or CLK

(2)

CE or OE/RESET to data float delay

Clock periods

CYC

(3)

CLK Low time

(3)

CLK High time

(3)

CE setup time to CLK (guarantees proper counting)

CE High time (guarantees counters are reset)

SCE

HCE

HOE

OE/RESET hold time (guarantees counters are reset)

Notes:

1. AC test load = 50 pF.

2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.

3. Guaranteed by design, not tested.

4. All AC parameters are measured with V = 0.0V and V = 3.0V.

5. If T

6. If T

High < 2 µs, T = 2 µs.

HCE

HOE

High < 2 µs, T = 2 µs.

DS026 (v3.10) April 17, 2003

www.xilinx.com

Product Specification

1-800-255-7778

XC18V00 Series In-System Programmable Configuration PROMs

AC Characteristics Over Operating Conditions When Cascading for XC18V04 and

XC18V02

OE/RESET

CLK

CDF

OCE

Last Bit

First Bit

DATA

CEO

OCK

OOE

DS026_07_020300

Symbol

Description

Min

Max

Units

(2,3)

CLK to data float delay

CDF

OCK

OCE

OOE

(3)

CLK to CEO delay

(3)

CE to CEO delay

(3)

OE/RESET to CEO delay

Notes:

1. AC test load = 50 pF.

2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.

3. Guaranteed by design, not tested.

4. All AC parameters are measured with V = 0.0V and V = 3.0V.

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DS026 (v3.10) April 17, 2003

1-800-255-7778

Product Specification

XC18V00 Series In-System Programmable Configuration PROMs

AC Characteristics Over Operating Conditions When Cascading for XC18V01,

XC18V512, and XC18V256

OE/RESET

CLK

CDF

OCE

Last Bit

First Bit

DATA

CEO

OCK

OOE

DS026_07_020300

Symbol

Description

Min

Max

Units

(2,3)

CLK to data float delay

CDF

OCK

OCE

OOE

(3)

CLK to CEO delay

(3)

CE to CEO delay

(3)

OE/RESET to CEO delay

Notes:

1. AC test load = 50 pF.

2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.

3. Guaranteed by design, not tested.

4. All AC parameters are measured with V = 0.0V and V = 3.0V.

DS026 (v3.10) April 17, 2003

www.xilinx.com

Product Specification

1-800-255-7778

XC18V00 Series In-System Programmable Configuration PROMs

Ordering Information

XC18V04 VQ44 C

Device Number

Operating Range/Processing

XC18V04

XC18V02

XC18V01

XC18V512

XC18V256

C = Commercial (T = 0° to +70°C)

Package Type

= Industrial (T = –40° to +85°C)

VQ44 = 44-pin Plastic Quad Flat Package

PC44 = 44-pin Plastic Chip Carrier

SO20 = 20-pin Small-Outline Package

PC20 = 20-pin Plastic Leaded Chip Carrier

(1)

(2)

Notes:

1. XC18V04 and XC18V02 only.

2. XC18V01, XC18V512, and XC18V256 only.

Valid Ordering Combinations

XC18V04VQ44C

XC18V04PC44C

XC18V02VQ44C

XC18V02PC44C

XC18V01VQ44C

XC18V01PC20C

XC18V01SO20C

XC18V01VQ44I

XC18V01PC20I

XC18V01SO20I

XC18V512VQ44C

XC18V512PC20C

XC18V512SO20C

XC18V512VQ44I

XC18V512PC20I

XC18V512SO20I

XC18V256VQ44C

XC18V256PC20C

XC18V256SO20C

XC18V256VQ44I

XC18V256PC20I

XC18V256SO20I

XC18V04VQ44I

XC18V04PC44I

XC18V02VQ44I

XC18V02PC44I

Marking Information

44-pin Package

XC18V04 VQ44 I

Device Number

Operating Range/Processing

XC18V04

(blank) = Commercial (T = 0° to +70°C)

Package Type

XC18V02

XC18V01

XC18V512

XC18V256

I = Industrial (T = –40° to +85°C)

VQ44 = 44-pin Plastic Quad Flat Package

PC44 = 44-pin Plastic Leaded Chip Carrier

(1)

Notes:

1. XC18V02 and XC18V04 Only.

(1)

20-pin Package

Due to the small size of the commercial serial PROM packages, the complete ordering part number cannot be

marked on the package. The XC prefix is deleted and the package code is simplified. Device marking is as follows:

18V01 S C

Device Number

Operating Range/Processing

18V01

18V512

18V256

C = Commercial (T = 0° to +70°C)

Package Type

= Industrial (T = –40° to +85°C)

S = 20-pin Small-Outline Package

J = 20-pin Plastic Leaded Chip Carrier

Notes:

1. XC18V01, XC18V512, and XC18V256 only.

www.xilinx.com

DS026 (v3.10) April 17, 2003

1-800-255-7778

Product Specification

XC18V00 Series In-System Programmable Configuration PROMs

Revision History

The following table shows the revision history for this document.

Date

2/9/99

8/23/99

9/1/99

9/16/99

Version

1.0

Revision

First publication of this early access specification

Edited text, changed marking, added CF and parallel load

Corrected JTAG order, Security and Endurance data.

1.1

1.2

1.3

Corrected SelectMAP diagram, control inputs, reset polarity. Added JTAG and CF

description, 256 Kbit and 128 Kbit devices.

01/20/00

02/18/00

04/04/00

2.0

2.1

2.2

Added Q44 Package, changed XC18xx to XC18Vxx

Updated JTAG configuration, AC and DC characteristics

Removed stand alone resistor on INIT pin in Figure 5. Added Virtex-E and EM parts to

FPGA table.

06/29/00

11/13/00

2.3

2.4

Removed XC18V128 and updated format. Added AC characteristics for XC18V01,

XC18V512, and XC18V256 densities.

Features: changed 264 MHz to 264 Mb/s at 33 MHz; AC Spec.: T

units to ns, T

HCE

SCE

CE High time units to µs. Removed Standby Mode statement: “The lower power standby

modes available on some XC18V00 devices are set by the user in the programming

software”. Changed 10,000 cycles endurance to 20,000 cycles.

01/15/01

04/04/01

04/30/01

2.5

2.6

2.7

Updated Figures 5 and 6, added 4.7 resistors. Identification registers: changes ISP

PROM product ID from 06h to 26h.

Updated Figure 6, Virtex SelectMAP mode; added XC2V products to Compatible PROM

table; changed Endurance from 10,000 cycles, 10 years to 20,000, 20 years;

Updated Figure 6: removed Virtex-E in Note 2, fixed SelectMAP mode connections.

Under AC Characteristics Over Operating Conditions for XC18V04 and XC18V02,

changed T

from 25 ms to 25 ns.

SCE

06/11/01

09/28/01

2.8

2.9

AC Characteristics Over Operating Conditions for XC18V01, XC18V512, and

XC18V256. Changed Min values for T

to 2 µs.

from 20 ms to 20 ns and for T

from 2 ms

SCE

HCE

Changed the boundary scan order for the CEO pin in Table 1, updated the configuration

bits values in the table under Xilinx FPGAs and Compatible PROMs, and added

information to the Recommended Operating Conditions table.

11/12/01

12/06/01

02/27/02

03/15/02

03/27/02

06/14/02

07/24/02

09/06/02

3.0

3.1

3.2

3.3

3.4

3.5

3.6

3.7

Updated for Spartan-IIE FPGA family.

Changed Figure 7(c).

Updated Table 2 and Figure 6 for the Virtex-II Pro family of devices.

Updated Xilinx software and modified Figure 6 and Figure 7.

Made changes to pages 1-3, 5, 7-11, 13, 14, and 18. Added new Figure 8 and Figure 9.

Made additions and changes to Table 2.

Changed last bullet under Connecting Configuration PROMs, page 9.

Multiple minor changes throughout, plus the addition of Pinout Diagrams, page 4 and

the deletion of Figure 9.

DS026 (v3.10) April 17, 2003

www.xilinx.com

Product Specification

1-800-255-7778

XC18V00 Series In-System Programmable Configuration PROMs

10/31/02

11/18/02

04/17/03

3.8

3.9

Made minor change on Figure 7 (b) and changed orientation of SO20 diagram on page 5.

Added XC2S400E and XC2S600E to Table 2.

3.10

Changes to Description, External Programming, and Table 2.

www.xilinx.com

DS026 (v3.10) April 17, 2003

1-800-255-7778

Product Specification

Discontinue XC18V256 and

I-Grade Ordering Codes for the

XC18V00 Product Family

Product Discontinuation Notice

PDN2003-05 (v1.2) May 5, 2004

Overview

Xilinx is discontinuing the XC18V256^TMdevice and all Industrial Temperature Grade (I-Grade) ordering codes

of the XC18V00 ^TMproduct family.

Product Affected

The following ordering codes are being discontinued:

XC18V256 devices:

XC18V256PC20C

XC18V256SO20C

XC18V256PC20I

XC18V256SO20I

XC18V256VQ44C XC18V256VQ44I

XC18V00 I-grade:

XC18V512PC20I

XC18V512SO20I

XC18V512VQ44I

XC18V01PC20I

XC18V01SO20I

XC18V01VQ44I

XC18V02PC44I

XC18V02VQ44I

XC18V04PC44I

XC18V04VQ44I

Description

Xilinx is streamlining the XC18V00 family by discontinuing ordering codes with minimal customer impact.

The above device/package combinations have declined in customer usage to the point where continued

manufacturing is no longer economical.

Replacement devices are listed in the attached table. The target replacement for the XC18V256 device is the

XC18V512. The target replacements for the XC18V00 I-grade devices are the new XC18V00 C-grade devices.

Note: A separate product change notification (PCN2003-04) has been issued which expands the operating

range/processing of the XC18V00 C-grade devices to meet the operating range/processing of the discontinued

XC18V00 I-grade devices. These target replacements are form, fit, and functionally compatible with the

discontinued devices.

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

PDN2003-05 (v1.2) May 5, 2004

www.xilinx.com

1 of 2

Discontinued

Part Number

Configuration Replacement

Configuration

Bits

Part Number

XC18V256PC20C

XC18V256SO20C

XC18V256VQ44C

XC18V256PC20I

XC18V256SO20I

XC18V256VQ44I

XC18V512PC20I

XC18V512SO20I

XC18V512VQ44I

XC18V01PC20I

XC18V01SO20I

XC18V01VQ44I

XC18V02PC44I

XC18V02VQ44I

XC18V04PC44I

XC18V04VQ44I

262,144 XC18V512PC20C

262,144 XC18V512SO20C

262,144 XC18V512VQ44C

524,288

262,144 XC18V512PC20C0901

262,144 XC18V512SO20C0901

262,144 XC18V512VQ44C0901

524,288 XC18V512PC20C0901

524,288 XC18V512SO20C0901

524,288 XC18V512VQ44C0901

1,048,576 XC18V01PC20C0901

1,048,576 XC18V01SO20C0901

1,048,576 XC18V01VQ44C0901

2,097,152 XC18V02PC44C0901

2,097,152 XC18V02VQ44C0901

4,194,304 XC18V04PC44C0901

4,194,304 XC18V04VQ44C0901

524,288

1,048,576

2,097,152

4,194,304

Key Dates

Final orders are accepted until December 31, 2004

Final deliveries must occur on or before June 30, 2005.

Response

Assistance in planning for the replacement of the above devices is available. Please contact your Xilinx Sales

Representative for more information.

Important Notice: On July 1, 2004, Xilinx Customer Notifications (PCN, PDN, and Quality Alerts) will be

delivered via e-mail alerts sent by the MySupport website (http://www.xilinx.com/support). Register today and

personalize your "MyAlerts" to include Customer Notifications. This change provides many benefits, including

the ability to receive alerts for new and updated information about specific products, as well as alerts for other

publications such as data sheets, errata, application notes, and so forth. For instructions on how to sign up,

refer to Xilinx Answer Record 18683.

Revision History

The following table shows the revision history for this document.

Date

Version

1.0

Revision

6/30/03

10/9/03

5/5/04

Initial release.

Modify page 2 to clarify the replacements for I-grade parts must use SCD0901.

1.1

•

Revise final order date from June 30, 2004, to December 31, 2004.

Revise final delivery date from December 30, 2004, to June 30, 2005.

Reformat document to similar format used by recent customer notifications.

1.2

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

PDN2003-05 (v1.2) May 5, 2004

www.xilinx.com

2 of 2

Discontinue XC18V256 and

I-Grade Ordering Codes for the

XC18V00 Product Family

Product Discontinuation Notice

PDN2003-05 (v1.3) September 1, 2004

Overview

Xilinx is discontinuing the XC18V256^TMdevice and all Industrial Temperature Grade (I-Grade) ordering codes

of the XC18V00 ^TMproduct family.

Product Affected

The following ordering codes are being discontinued:

XC18V256 devices:

XC18V256PC20C

XC18V256SO20C

XC18V256PC20I

XC18V256SO20I

XC18V256VQ44C XC18V256VQ44I

XC18V00 I-grade:

XC18V512PC20I

XC18V512SO20I

XC18V512VQ44I

XC18V01PC20I

XC18V01SO20I

XC18V01VQ44I

XC18V02PC44I

XC18V02VQ44I

XC18V04PC44I

XC18V04VQ44I

Description

Xilinx is streamlining the XC18V00 family by discontinuing ordering codes with minimal customer impact.

The above device/package combinations have declined in customer usage to the point where continued

manufacturing is no longer economical.

Replacement devices are listed in the attached table. The target replacement for the XC18V256 device is the

XC18V512. The target replacements for the XC18V00 I-grade devices are the new XC18V00 C-grade devices.

Note: A separate product change notification (PCN2003-04) has been issued which expands the operating

range/processing of the XC18V00 C-grade devices to meet the operating range/processing of the discontinued

XC18V00 I-grade devices. These target replacements are form, fit, and functionally compatible with the

discontinued devices.

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

PDN2003-05 (v1.3) September 1, 2004

www.xilinx.com

1 of 2

Discontinued

Part Number

Configuration Replacement

Configuration

Bits

Part Number

XC18V256PC20C

XC18V256SO20C

XC18V256VQ44C

XC18V256PC20I

XC18V256SO20I

XC18V256VQ44I

XC18V512PC20I

XC18V512SO20I

XC18V512VQ44I

XC18V01PC20I

XC18V01SO20I

XC18V01VQ44I

XC18V02PC44I

XC18V02VQ44I

XC18V04PC44I

XC18V04VQ44I

262,144 XC18V512PC20C

262,144 XC18V512SO20C

262,144 XC18V512VQ44C

524,288

262,144 XC18V512PC20C0936

262,144 XC18V512SO20C0936

262,144 XC18V512VQ44C0936

524,288 XC18V512PC20C0936

524,288 XC18V512SO20C0936

524,288 XC18V512VQ44C0936

1,048,576 XC18V01PC20C0936

1,048,576 XC18V01SO20C0936

1,048,576 XC18V01VQ44C0936

2,097,152 XC18V02PC44C0936

2,097,152 XC18V02VQ44C0936

4,194,304 XC18V04PC44C0936

4,194,304 XC18V04VQ44C0936

524,288

1,048,576

2,097,152

4,194,304

Key Dates

Final orders are accepted until December 31, 2004.

Final deliveries must occur on or before June 30, 2005.

Response

Assistance in planning for the replacement of the above devices is available. Please contact your Xilinx Sales

Representative for more information.

Important Notice: On July 1, 2004, Xilinx Customer Notifications (PCN, PDN, and Quality Alerts) will be

delivered via e-mail alerts sent by the MySupport website (http://www.xilinx.com/support). Register today and

personalize your "MyAlerts" to include Customer Notifications. This change provides many benefits, including

the ability to receive alerts for new and updated information about specific products, as well as alerts for other

publications such as data sheets, errata, application notes, and so forth. For instructions on how to sign up,

refer to Xilinx Answer Record 18683.

Revision History

The following table shows the revision history for this document.

Date

Version

1.0

Revision

6/30/03

10/9/03

5/5/04

Initial release.

Modify page 2 to clarify the replacements for I-grade parts must use SCD0901.

1.1

•

Revise final order date from June 30, 2004, to December 31, 2004.

Revise final delivery date from December 30, 2004, to June 30, 2005.

Reformat document to similar format used by recent customer notifications.

1.2

Recommended replacements changed to reference SCD0936 instead of SCD0901. This is

related to PCN2004-17.

9/1/04

1.3

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

PDN2003-05 (v1.3) September 1, 2004

www.xilinx.com

2 of 2

February 12, 2004

Key Dates: Qualification samples for product manufactured at STMicroelectronics are

now available. Xilinx is offering 5 sample units free of charge per customer. Use special

ordering code 0901 when placing orders for these sample units. To use ordering code

0901, append "0901" to the end of the standard ordering part number (e.g.,

XC18V04VQ44C0901). The ordering code 0901 will not be marked on the package

topmark.

Customers who need product manufactured at STMicroelectronics beyond the onset of

device cross-shipment (September 10, 2003) should also use ordering code 0901. Only

product manufactured at STMicroelectronics will be used to fulfill SCD0901 orders – this

clarification paragraph was added on July 21, 2003.

Xilinx will begin shipping production devices manufactured at STMicroelectronics starting

September 10, 2003. After this date, customers ordering the standard part number may

receive product manufactured at either UMC or STMicroelectronics.

Customers who need product manufactured at UMC beyond the onset of device cross-

shipment (September 10, 2003) may do so on a short-term basis only by using special

ordering number SCD0799*. To use SCD0799, append “0799” to the end of the standard

part ordering number (e.g., XC18V04VQ44C0799). Only product manufactured at UMC

will be used to fulfill SCD0799 orders. SCD0799 will be available for use starting June

10, 2003 and will be discontinued after December 31, 2003. The ordering code 0799 will

not be marked on the package topmark.

Traceability: The devices manufactured at UMC and STMicroelectronics can be

distinguished both visually and electrically.

Visually: The devices can be distinguished visually by a 3-letter code located on the

second line of the package topmark in between the package/pin code and the datecode.

The second letter in this 3-letter code will be an "R" for product manufactured at

STMicroelectronics. Also, a new traceability code will be added to the top mark for

XC18V00 devices manufactured at STMicroelectronics. See the example below.

Sample topmark for the 44-pin VQFP and PLCC Packages

Example of a UMC package topmark

Example of an STMicro package topmark

XC18V04™

VQ44AEN0233

F1145765A

XC18V04™

VQ44ART0233

STMicroelectronics

traceability code

5PM5A0233

* Reference PCN2003-04A for the latest update on the availability of SCD0799.

Xilinx PCN2003-04 (v1.3) Additional Manufacturer for the XC18V00 Family of ISP Configuration PROMs

Page 2 of 5

Xilinx PCN, PDNs, and Advisories are available at:

http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp?category=Customer+Notifications

February 12, 2004

Sample topmark for the 20-pin SOIC Package

Example of a UMC package topmark

Example of an STMicro package topmark

18V512SC

233342

XC18V512™

SART0233

5BM3A0233

Sample topmark for the 20-pin PLCC Package

Example of a UMC package topmark

Example of an STMicro package topmark

18V512JC

233342

XC18V01™

JART0233

5BM5A0233

Electrically: The devices can be distinguished electrically by the IDCODE:

UMC

IDCODE

STMicroelectronics

IDCODE

Device

XC18V512

XC18V01

XC18V02

XC18V04

05023093h

05024093h

05025093h

05026093h

05033093h

05034093h

05035093h

05036093h

This change will require a software update to your programming algorithms. Please see

the Algorithm Change Notification (ACN2003-01) for further details. Xilinx has informed

and provided the necessary information to our third party programmer partners as well as

our distribution partners to ensure a smooth transition.

Xilinx PCN2003-04 (v1.3) Additional Manufacturer for the XC18V00 Family of ISP Configuration PROMs

Page 3 of 5

Xilinx PCN, PDNs, and Advisories are available at:

http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp?category=Customer+Notifications

February 12, 2004

Qualification Data:

STMicroelectronics Process Qualification Data for 32MBit Flash Memory:

Test Procedure

MIL-STD-883

Procedure

1008

Test Conditions

Hours/Cy

Results

Lots Sample

Fail

Retention Bake

Write/Erase Cycling

Retention Bake

(after W/E Cycling)

Temperature

1000

100,000

168

150°C

250°C

25°C

1008

180

250°C

1010C

1000

240

-40 to 150°C

Cycling

Pressure Pot

JEDEC

22A102

CECC 90,000

121°C, 2 ATM,

RH=100%

85°C, RH=85%,

Vcc=3.6V

Temperature

1000

Humidity, Bias

Xilinx Qualification Data:

Part

Test

Package Sample

Hours/Cy Fails

Status

XC18V04

VQ44

PC44

SO20

PC20

VQ44

PC44

SO20

PC20

VQ44

PC44

SO20

PC20

VQ44

1000

500

1000

500

1000

Pass

HTOL @140°C

XC18V04

Temp Cycle,

Condition C

-65°C to 150°C

HTS, 150°C

XC18V04

Temperature/Humidity

Bias Test - Hast

130°C/85%RH

Temperature/Humidity

1000

Bias Test 85°C /85%RH

Write/Erase Cycling 25°C

ESD - HBM JESD22-A-114

ESD – MM JESD22-A-115-A

Latchup – EIA/JESD78

XC18V04

VQ44

20,000

2000 volts

200 volts

200 mA

Pass

Xilinx PCN2003-04 (v1.3) Additional Manufacturer for the XC18V00 Family of ISP Configuration PROMs

Page 4 of 5

Xilinx PCN, PDNs, and Advisories are available at:

http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp?category=Customer+Notifications

February 12, 2004

Response and Contact: Contact your Xilinx Sales Representative for assistance in

obtaining sample or production devices. Characterization data is available upon request

by emailing the Xilinx Quality Assurance group at pcn@xilinx.com. All other questions

may be direct pcn@xilinx.com, or directly by fax at (408) 369-1718.

Per JEDEC Standard JESD46B, customers should acknowledge receipt of the PCN

within 30 days of delivery of the PCN. Lack of acknowledgement of the PCN within 30

days constitutes acceptance of the change. After acknowledgement, lack of additional

response within the 90-day period constitutes acceptance of the change.

Revision History

Date

Version

1.0

Revision

6/10/03

6/26/03

Initial release.

1.1

Fixed a typographical error in the package topmark: the STMicroelectronics

traceability code should be 5PM5A0233 instead of 5BM5A0233 (change the B to a

P).

7/21/03

2/12/04

1.2

1.3

Modified the Key Dates section to clarify the use of SCD0901.

Modified the Key Dates section to add a footnote which references PCN2003-04A for

the latest information on product availability.

Xilinx PCN2003-04 (v1.3) Additional Manufacturer for the XC18V00 Family of ISP Configuration PROMs

Page 5 of 5

Xilinx PCN, PDNs, and Advisories are available at:

http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp?category=Customer+Notifications

XC18V512PC20C0936 [XILINX]

相关型号：

XC18V512PC20I

XC18V512PC44

XC18V512PC44C

XC18V512PCG20C

XC18V512PCG20C0936

XC18V512SO20

XC18V512SO20C

XC18V512SO20C0901

XC18V512SO20C0936

XC18V512SO20I

XC18V512SOG20C

XC18V512VQ44