XC2C32-4CP56I [XILINX]
Flash PLD, 4.5ns, 32-Cell, CMOS, PBGA56, 6 X 6 MM, 0.50 MM PITCH, CSP-56;
| 型号： | XC2C32-4CP56I |
| 厂家： | 
XILINX, INC |
| 描述： | Flash PLD, 4.5ns, 32-Cell, CMOS, PBGA56, 6 X 6 MM, 0.50 MM PITCH, CSP-56 |
| 文件： | 总12页 (文件大小：76K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0
R
XC2C32 CoolRunner-II CPLD
0
0
DS091 (v1.0) June 4, 2002
Advance Product Specification
Features
Description
•
Optimized for 1.8V systems
The CoolRunner-II 32-macrocell device is designed for both
high performance and low power applications. This lends
power savings to high-end communication equipment and
high speed to battery operated devices. Due to the low
power stand-by and dynamic operation, overall system reli-
ability is improved
-
-
-
-
-
-
-
-
As fast as 3.5 ns pin-to-pin logic delays
As low as 14 µA quiescent current
32 macrocells with up to 800 logic gates
Fast input registers
Slew rate control on individual outputs
LVCMOS 1.8V through 3.3V
1.5V I/O compatible
This device consists of four Function Blocks inter-con-
nected by a low power Advanced Interconnect Matrix (AIM).
The AIM feeds 40 true and complement inputs to each
Function Block. The Function Blocks consist of a 40 by 56
P-term PLA and 16 macrocells which contain numerous
configuration bits that allow for combinational or registered
modes of operation.
LVTTL 3.3V
•
•
Available in multiple package options
-
-
-
44-pin PLCC with 33 user I/O
44-pin VQFP with 33 user I/O
56-ball CP BGA with 33 user I/O
Additionally, these registers can be globally reset or preset
and configured as a D or T flip-flop or as a D latch. There
are also multiple clock signals, both global and local product
term types, configured on a per macrocell basis. Output pin
configurations include slew rate limit, bus hold, pull-up,
open drain and programmable grounds. A Schmitt trigger
input is available on a per input pin basis. In addition to stor-
ing macrocell output states, the macrocell registers may be
configured as "fast input" registers to store signals directly
from input pins.
Advanced system features
-
Fastest in system programming
1.8V ISP using IEEE 1532 (JTAG) interface
·
-
-
-
-
IEEE1149.1 JTAG Boundary Scan Test
Optional Schmitt-trigger input (per pin)
FZP 100% CMOS product term generation
Flexible clocking modes
·
Optional DualEDGE triggered registers
-
Global signal options with macrocell control
·
Multiple global clocks with phase selection per
macrocell
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as
a synchronous clock source. Macrocell registers can be
individually configured to power up to the zero or one state.
A global set/reset control line is also available to asynchro-
nously set or reset selected registers during operation.
Additional local clock, synchronous clock-enable, asyncho-
nous set/reset and output enable signals can be formed
using product terms on a per-macrocell or per-Function
Block basis.
·
·
Multiple global output enables
Global set/reset
-
Efficient control term clocks, output enables and
set/resets for each macrocell and shared across
function blocks
-
-
Advanced design security
Open-drain output option for Wired-OR and LED
drive
-
-
Optional configurable grounds on unused I/Os
Mixed I/O voltages compatible with 1.5V, 1.8V,
2.5V, and 3.3V logic levels
A DualEDGE flip-flop feature is also available on a per mac-
rocell basis. This feature allows high performance synchro-
nous operation based on lower frequency clocking to help
reduce the total power consumption of the device.
-
PLA architecture
·
·
Superior pinout retention
100% product term routability across function
block
The CoolRunner-II 32-macrocell CPLD is I/O compatible
with standard LVTTL and LVCMOS18, LVCMOS25, and
LVCMOS33 (see Table 1). This device is also 1.5V I/O com-
patible with the use of Schmitt-trigger inputs.
-
Hot pluggable
Refer to the CoolRunner™-II family data sheet for architec-
ture description.
© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS091 (v1.0) June 4, 2002
www.xilinx.com
1
Advance Product Specification
1-800-255-7778
R
XC2C32 CoolRunner-II CPLD
EIA/JEDEC standard for 3.3V applications that use an
LVTTL input buffer and Push-Pull output buffer. The
LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications.
CoolRunner-II CPLDs are also 1.5V I/O compatible with the
use of Schmitt-trigger inputs.
Fast Zero Power Design Technology
Xilinx CoolRunner-II CPLDs are fabricated on a 0.18 micron
process technology which is derived from leading edge
FPGA product development. CoolRunner-II CPLDs employ
Fast Zero Power™ (FZP), a design technique that makes
use of CMOS technology in both the fabrication and design
methodology. FZP design technology employs a cascade of
CMOS gates to implement sum of products instead of tradi-
tional sense amplifier methodology. Due to this technology,
Xilinx CoolRunner-II CPLDs achieve both high performance
and low power operation.
Table 1: I/O Standards for XC2C32
I/O Types
Output VCCIO
Input VCCIO
LVTTL
3.3
3.3
2.5
1.8
1.5
3.3
3.3
2.5
1.8
1.5
LVCMOS33
LVCMOS25
LVCMOS18
1.5V I/O
Supported I/O Standards
The CoolRunner-II 32 macrocell features both LVCMOS
and LVTTL I/O implementations. See Table 1 for I/O stan-
dard voltages. The LVTTL I/O standard is a general purpose
20
15
10
5
0
50
100
150
200
250
300
0
Frequency (MHz)
Figure 1: ICC vs Frequency
Table 2: ICC vs Frequency (LVCMOS 1.8V TA = 25°C)(1)
DS091_01_031802
Frequency (MHz)
100 150 175
0
25
50
75
200
225
250
300
Typical -4.5, -6 ICC (mA)
Typical -3.5 ICC (mA)
Notes:
1. 16-bit up/down, resettable binary counter (one counter per function block).
2
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DS091 (v1.0) June 4, 2002
Advance Product Specification
R
XC2C32 CoolRunner-II CPLD
Absolute Maximum Ratings
Symbol
Description
Supply voltage relative to ground
Supply voltage for output drivers
Value
–0.5 to 2.0
–0.5 to 4.0
–0.5 to 4.0
–0.5 to 4.0
–0.5 to 4.0
–0.5 to 4.0
–65 to +150
+260
Units
V
VCC
VCCIO
VJTAG
VAUX
VIN
V
JTAG input voltage limits
V
JTAG input supply voltage
V
Input voltage relative to ground(1)
Voltage applied to 3-state output(1)
Storage Temperature (ambient)
Maximum Soldering temperature (10s @ 1/16in. = 1.5mm)
Junction Temperature
V
VTS
V
TSTG
TSOL
TJ
°C
°C
°C
+150
Notes:
1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easiest to achieve. During transitions,
the device pins may undershoot to –2.0v or overshoot to +4.5V, provided this over or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA.
Recommended Operating Conditions
Symbol
Parameter
Supply voltage for internal logic
and input buffers
Min
1.7
1.7
3.0
2.3
1.7
1.4
1.7
Max
1.9
1.9
3.6
2.7
1.9
1.6
3.6
Units
VCC
Commercial TA = 0°C to +70°C
Industrial TA = –40°C to +85°C
V
V
V
V
V
V
V
VCCIO
Supply voltage for output drivers @ 3.3V operation
Supply voltage for output drivers @ 2.5V operation
Supply voltage for output drivers @ 1.8V operation
Supply voltage for output drivers @ 1.5V operation
JTAG programming pins
VAUX
DC Electrical Characteristics (Over Recommended Operating Conditions)
Symbol
ICCSB
ICCSB
ICC
Parameter
Standby current (-4.5, -6)
Standby current (-3.5)
Test Conditions
VCC = 1.9V, VCCIO = 3.6V
VCC = 1.9V, VCCIO = 3.6V
f = 1 MHz
Min.
Max.
Units
µA
mA
mA
mA
mA
mA
pF
Dynamic current (-4.5, -6)
f = 50 MHz
ICC
Dynamic current (-3.5)
f = 1 MHz
f = 50 MHz
CJTAG
CCLK
CIO
JTAG input capacitance
Global clock input capacitance
I/O capacitance
f = 1 MHz
f = 1 MHz
pF
f = 1 MHz
pF
DS091 (v1.0) June 4, 2002
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3
Advance Product Specification
1-800-255-7778
R
XC2C32 CoolRunner-II CPLD
LVCMOS 3.3V DC Voltage Specifications
Symbol
VCCIO
VIH
Parameter
Input source voltage
Test Conditions
Min.
Max.
Units
V
3.0
3.6
High level input voltage
Low level input voltage
High level output voltage
2
VCCIO + 0.3V
V
VIL
–0.3
0.8
-
V
VOH
IOH = –8 mA, VCCIO = 3V
OH = –0.1 mA, VCCIO = 3V
IOL = 8 mA, VCCIO = 3V
VCCIO – 0.4V
V
I
VCCIO – 0.2V
-
V
VOL
Low level output voltage
-
0.4
0.2
10
10
V
I
OL = 0.1 mA, VCCIO = 3V
-
V
IIL
Input leakage current
I/O High-Z leakage
VIN = 0V or VCCIO to 3.9V
–10
–10
µA
µA
pF
pF
pF
IIH
VIN = 0V or VCCIO to 3.9V
f = 1 MHz
CJTAG
CCLK
CIO
JTAG input capacitance
Global clock input capacitance
I/O capacitance
f = 1 MHz
f = 1 MHz
LVCMOS 2.5V DC Voltage Specifications
Symbol
VCCIO
VIH
Parameter
Input source voltage
Test Conditions
Min.
2.3
Max.
2.7
3.9
0.7
-
Units
V
High level input voltage
Low level input voltage
High level output voltage
1.7
V
VIL
–0.3
V
VOH
IOH = –8 mA, VCCIO = 2.3V
VCCIO – 0.4V
V
IOH = –0.1 mA, VCCIO = 2.3V VCCIO – 0.2V
-
V
VOL
Low level output voltage
IOL = 8 mA, VCCIO = 2.3V
OL = 0.1mA, VCCIO = 2.3V
-
0.4
0.2
10
10
V
I
-
V
IIL
Input leakage current
I/O High-Z leakage
VIN = 0V or VCCIO to 3.9V
VIN = 0V or VCCIO to 3.9V
f = 1 MHz
–10
–10
µA
µA
pF
pF
pF
IIH
CJTAG
CCLK
CIO
JTAG input capacitance
Global clock input capacitance
I/O capacitance
f = 1 MHz
f = 1 MHz
4
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DS091 (v1.0) June 4, 2002
1-800-255-7778
Advance Product Specification
R
XC2C32 CoolRunner-II CPLD
LVCMOS 1.8V DC Voltage Specifications
Symbol
VCCIO
VIH
Parameter
Input source voltage
Test Conditions
Min.
Max.
Units
V
1.7
1.9
High level input voltage
Low level input voltage
High level output voltage
0.7 x VCCIO
3.9
V
VIL
–0.3
0.2 x VCCIO
V
VOH
IOH = –8 mA, VCCIO = 1.7V
OH = –0.1 mA, VCCIO = 1.7V
IOL = 8 mA, VCCIO = 1.7V
VCCIO – 0.45
-
-
V
I
VCCIO – 0.2
V
VOL
Low level output voltage
-
0.45
0.2
10
10
V
I
OL = 0.1 mA, VCCIO = 1.7V
VIN = 0 or VCCIO to 3.9V
VIN = 0 or VCCIO to 3.9V
f = 1 MHz
-
V
IIL
Input leakage current
I/O High-Z leakage
–10
–10
µA
µA
pF
pF
pF
IIH
CJTAG
CCLK
CIO
JTAG input capacitance
Global clock input capacitance
I/O capacitance
f = 1 MHz
f = 1 MHz
(1)
1.5V DC Voltage Specifications
Symbol
VCCIO
VIH
Parameter
Input source voltage
Test Conditions
Min.
Max.
1.6
3.9
0.3
-
Units
V
1.4
High level input voltage
Low level input voltage
High level output voltage
0.7 x VCCIO
V
VIL
–0.3
V
VOH
IOH = –4 mA, VCCIO = 1.4V
VCCIO – 0.45
V
I
OH = –0.1 mA, VCCIO = 1.4V
IOL = 4 mA, VCCIO = 1.4V
VCCIO – 0.2
-
V
VOL
Low level output voltage
-
0.4
0.2
10
10
V
I
OL = 0.1 mA, VCCIO = 1.4V
VIN = 0 or VCCIO to 3.9V
VIN = 0 or VCCIO to 3.9V
f = 1 MHz
-
V
IIL
Input leakage current
I/O High-Z leakage
–10
–10
µA
µA
pF
pF
pF
IIH
CJTAG
CCLK
CIO
JTAG input capacitance
Global clock input capacitance
I/O capacitance
f = 1 MHz
f = 1 MHz
Notes:
1. Hysteresis used on 1.5V inputs.
DS091 (v1.0) June 4, 2002
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5
Advance Product Specification
1-800-255-7778
R
XC2C32 CoolRunner-II CPLD
AC Electrical Characteristics Over Recommended Operating Conditions
-3.5
-4.5
-6
Symbol
TPD1
Parameter
Propagation delay single p-term
Propagation delay OR array
Fast input register p-term clock setup time
Setup time fast (single p-term)
Setup time (OR array)
Min.
Max.
Min.
Max.
Min.
Max. Units
-
-
3.2
3.5
-
-
-
4.1
4.5
-
-
-
5.2
6.0
-
ns
ns
TPD2
TSUF
1.3
1.4
1.7
0
1.6
1.7
2.1
0
2.2
2.3
3.1
0
ns
TSU1
-
-
-
ns
TSU2
-
-
-
ns
THF
Fast input register hold time
P-term hold time
-
-
-
ns
TH
0
-
0
-
0
-
ns
TCO
Clock to output
-
2.8
416
333
303
238
222
-
-
3.7
250
256
233
185
172
-
-
4.7
168
182
159
143
128
-
ns
FTOGGLE
FSYSTEM1
FSYSTEM2
Internal toggle rate
-
-
-
MHz
MHz
MHz
MHz
MHz
ns
(2)
(2)
Maximum system frequency
Maximum system frequency
Maximum external frequency
Maximum external frequency
Fast input register p-term clock setup time
P-term clock setup time (single p-term)
P-term clock setup time (OR array)
Fast input register p-term clock hold time
P-term clock hold
-
-
-
-
-
-
(3)
FEXT1
-
-
-
(3)
FEXT2
-
-
-
TPSUF
TPSU1
TPSU2
TPHF
TPH
1.0
1.1
1.4
0.4
0.3
-
1.2
1.3
1.7
0.6
0.5
-
1.7
1.8
2.6
0.8
0.7
-
-
-
-
ns
-
-
-
ns
-
-
-
ns
-
-
-
ns
TPCO
P-term clock to output
3.1
3.5
3.8
4.5
4.9
5.1
-
4.1
4.5
4.8
5.9
5.9
5.9
-
5.2
5.7
6.0
7.7
7.5
7.0
-
ns
T
T
T
OE/TOD
Global OE to output enable/disable
P-term OE to output enable/disable
-
-
-
ns
POE/TPOD
-
-
-
ns
MOE/TMOD Macrocell driven OE to output enable/disable
-
-
-
ns
TPAO
TAO
P-term set/reset to output valid
Global set/reset to output valid
Register clock enable setup time
Register clock enable hold time
Global clock pulse width High or Low
P-term pulse width High or Low
Configuration time
-
-
-
ns
-
-
-
ns
TSUEC
THEC
1.5
0
1.8
0
2.3
0
ns
-
-
-
ns
TCW
1.2
3.5
-
2.0
4.5
-
3.0
6.0
-
ns
TPCW
TCONFIG
Notes:
-
-
-
ns
µs
1. FTOGGLE (1/2*TCW) is the maximum frequency of a dual edge triggered T flip-flop with output enabled.
2. FSYSTEM1 (1/TCYCLE) is the internal operating frequency for a device fully populated with 16-bit resettable binary counter through one
p-term per macrocell while FSYSTEM2 is through the OR array (one counter per function block).
FEXT1 (1/TSU2+TCO) is the maximum external frequency using one p-term while FEXT2 is through the OR array.
3.
6
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DS091 (v1.0) June 4, 2002
Advance Product Specification
R
XC2C32 CoolRunner-II CPLD
Internal Timing Parameters
-3.5
-4.5
-6
Symbol
Buffer Delays
TIN
Parameter(1)
Min.
Max.
Min.
Max.
Min.
Max.
Units
Input buffer delay
-
-
-
-
-
-
-
1.0
1.3
1.2
1.7
1.2
1.4
2.3
-
-
-
-
-
-
-
1.4
1.8
1.6
2.0
1.7
1.7
2.8
-
-
-
-
-
-
-
1.7
2.4
2.0
2.0
2.2
2.0
3.5
ns
ns
ns
ns
ns
ns
ns
TFIN
Fast data register input delay
Global Clock buffer delay
Global set/reset buffer delay
Global 3-state buffer delay
Output buffer delay
TGCK
TGSR
TGTS
TOUT
TEN
Output buffer enable/disable delay
P-term Delays
TCT
Control term delay
-
-
-
0.5
0.4
0.3
-
-
-
0.6
0.5
0.4
-
-
-
0.8
0.8
0.8
ns
ns
ns
TLOGI1
TLOGI2
Macrocell Delay
Single p-term delay adder
Multiple p-term delay adder
TPDI
Input to output valid
-
1.2
0
0.4
-
1.4
0
0.5
-
1.8
0
0.7
ns
ns
ns
ns
ns
ns
ns
ns
TSUI
Setup before clock
-
-
-
-
-
-
THI
Hold after clock
TECSU
TECHO
TCOI
TAOI
Enable clock setup time
Enable clock hold time
Clock to output valid
Set/reset to output valid
Clock doubler delay
1.2
0
-
1.4
0
-
1.8
0
-
-
-
-
-
0.2
2.0
0
-
0.4
2.2
0
-
0.7
3.0
0
-
-
-
TCDBL
-
-
-
Feedback Delays
TF
Feedback delay
Macrocell to global OE delay
-
-
1.2
1.0
-
-
1.6
1.3
-
-
2.2
2.0
ns
ns
TOEM
I/O Standard Time Adder Delays 1.5V CMOS
TIN15
Standard input adder
Hysteresis input adder
Output adder
-
-
-
-
0.5
2.0
0.5
2.0
-
-
-
-
0.8
3.0
0.8
3.0
-
-
-
-
1.0
4.0
1.0
4.0
ns
ns
ns
ns
THYS15
TOUT15
TSLEW15
Output slew rate adder
I/O Standard Time Adder Delays 1.8V CMOS
TIN18
Standard input adder
Hysteresis input adder
Output adder
-
-
-
-
0
-
-
-
-
0
-
-
-
-
0
ns
ns
ns
ns
THYS18
TOUT18
TSLEW
2.0
0
3.0
0
4.0
0
Output slew rate adder
2.0
3.0
4.0
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Advance Product Specification
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XC2C32 CoolRunner-II CPLD
Internal Timing Parameters (Continued)
-3.5
-4.5
-6
Symbol
Parameter(1)
Min.
Max.
Min.
Max.
Min.
Max.
Units
I/O Standard Time Adder Delays 2.5V CMOS
TIN25
Standard input adder
Hysteresis input adder
Output adder
-
-
-
-
0.5
1.5
1.5
2.0
-
-
-
-
0.8
2.5
2.5
3.0
-
-
-
-
1.0
3.0
3.0
4.0
ns
ns
ns
ns
THYS25
TOUT25
TSLEW25
Output slew rate adder
I/O Standard Time Adder Delays 3.3V CMOS/TTL
TIN33
Standard input adder
Hysteresis input adder
Output adder
-
-
-
-
0.7
1.0
1.0
2.0
-
-
-
-
1.0
2.0
2.0
3.0
-
-
-
-
2.0
3.0
3.0
4.0
ns
ns
ns
ns
THYS33
TOUT33
TSLEW33
Notes:
Output slew rate adder
1. 1.5 ns input pin signal rise/fall.
Switching Characteristics
V
CC
= 1.8V, 25oC
6.0
5.8
5.6
4.4
4.2
4.0
1
2
4
8
12
16
Number of Outputs Switching
DS091_02_031902
8
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Advance Product Specification
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XC2C32 CoolRunner-II CPLD
Pin Descriptions
Function Block
Macro-cell
PC44
44
43
42
40
39
38
37
36
35
34
33
29
28
27
26
25
1
VQ44
38
37
36
34
33
32
31
30
29
28
27
23
22
21
20
19
39
40
41
42
43
44
1
CP56
F1
1
1
2
1
E3
1
3
E1
1(GTS1)
4
D1
C1
A3
1(GTS0)
5
1(GTS3)
6
1(GTS2)
7
A2
1(GSR)
8
B1
1
9
A1
1
10
11
12
13
14
15
16
1
C4
C5
C8
A10
B10
C10
E8
1
1
1
1
1
1
2
G1
F3
2
2
2
2
3
3
H1
G3
J1
2
4
4
2(GCK0)
5
5
2(GCK1)
6
6
K1
2(GCK2)
7
7
K2
2
2
2
2
2
2
2
2
2
8
8
2
K3
9
9
3
H3
K5
10
11
12
13
14
15
16
11
12
14
18
19
20
22
5
6
H5
H8
K8
8
12
13
14
16
H10
G10
F10
Notes:
1. GTS = global output enable, GSR = global set reset,
GCK = global clock x
DS091 (v1.0) June 4, 2002
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9
Advance Product Specification
1-800-255-7778
R
XC2C32 CoolRunner-II CPLD
XC2C32 Global, JTAG, Power/Ground and No Connect Pins
Pin Type
PC44
17
VQ44
11
CP56
K10
TCK
TDI
15
9
J10
TDO
30
24
A6
TMS
16
10
K9
Input Only
24
18
D10
VAUX (JTAG supply voltage)
41
35
D3
Power internal (VCC
)
21
15
G8
Power external I/O (VCCIO
Ground
)
13, 32
10,23,31
-
7,26
4,17,25
-
H6, C6
H4, F8, C7
No connects
K4, K6, K7, H7, E10, A7,
A9, D8, A5, A8, A4, C3
Total user I/O
33
33
33
Ordering Information
Comm. (C)
Ind. (I)
C
Pin/Ball
Spacing (C/Watt) (C/Watt)
θJA
θJC
Part Number
Package Type
Package Dimensions I/O
XC2C32-3PC44C 1.27mm
XC2C32-4PC44C 1.27mm
XC2C32-6PC44C 1.27mm
54.7
54.7
54.7
28.7
28.7
28.7
Plastic Leaded Chip
Carrier
17.5mm x 17.5mm
17.5mm x 17.5mm
17.5mm x 17.5mm
33
33
33
Plastic Leaded Chip
Carrier
C
C
Plastic Leaded Chip
Carrier
XC2C32-3VQ44C
XC2C32-4VQ44C
XC2C32-6VQ44C
XC2C32-3CP56C
XC2C32-4CP56C
XC2C32-6CP56C
XC2C32-4PC44I
0.8mm
0.8mm
0.8mm
0.5mm
0.5mm
0.5mm
1.27mm
47.5
47.5
47.5
65.0
65.0
65.0
54.7
8.2
8.2
Very Thin Quad Flat Pack
Very Thin Quad Flat Pack
Very Thin Quad Flat Pack
Chip Scale Package
12mm x 12mm
12mm x 12mm
12mm x 12mm
6mm x 6mm
33
33
33
33
33
33
33
C
C
C
C
C
C
I
8.2
15.0
15.0
15.0
28.7
Chip Scale Package
6mm x 6mm
Chip Scale Package
6mm x 6mm
Plastic Leaded Chip
Carrier
17.5mm x 17.5mm
XC2C32-6PC44I
1.27mm
54.7
28.7
Plastic Leaded Chip
Carrier
17.5mm x 17.5mm
33
I
XC2C32-4VQ44I
XC2C32-6VQ44I
XC2C32-4CP56I
XC2C32-6CP56I
0.8mm
0.8mm
0.5mm
0.5mm
47.5
47.5
65.0
65.0
8.2
8.2
Very Thin Quad Flat Pack
Very Thin Quad Flat Pack
Chip Scale Package
12mm x 12mm
12mm x 12mm
6mm x 6mm
33
33
33
33
I
I
I
I
15.0
15.0
Chip Scale Package
6mm x 6mm
10
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DS091 (v1.0) June 4, 2002
1-800-255-7778
Advance Product Specification
R
XC2C32 CoolRunner-II CPLD
I/O(1)
I/O(1)
I/O(1)
I/O(3)
I/O
I/O(1)
33
I/O(2)
I/O
I/O
GND
I/O
I/O
I/O(2)
I/O
I/O
GND
I/O
I/O
7
8
9
1
2
3
4
5
6
7
8
39
38
37
36
35
34
33
32
31
30
29
I/O(1)
32
I/O(1)
31
I/O(3)
I/O
10
11
12
13
14
15
16
17
30
PC44
Top View
VQ44
Top View
29
28
27
26
25
24
23
I/O
I/O
I/O
I/O
V
V
V
CCIO
CCIO
V
I/O
CCIO
I/O
CCIO
GND
TDO
I/O
Gnd
TDO
I/O
TDI
TMS
TCK
9
10
11
TDI
TMS
TCK
(1) - Global Output Enable
(2) - Global Clock
(3) - Global Set/Reset
(1) - Global Output Enable
(2) - Global Clock
(3) - Global Set/Reset
Figure 2: PC44 Package
Figure 3: VQ44 Package
I/O(2) I/O(2) I/O
NC
I/O
NC
NC
I/O
TMS TCK
K
J
I/O(2)
I/O
TDI
I/O
I/O GND I/O VCCIO NC
I/O
H
G
F
I/O
I/O
VCC
GND
I/O
I/O
I/O
NC
I
I/O
I/O
CP56
Bottom View
I/O
I/O
E
D
C
B
A
I/O(1)
I/O(1)
I/O(3)
VAUX
NC
NC
I/O
I/O VCCIO GND I/O
I/O
I/O
I/O
I/O I/O(1) I/O(1) NC
NC TDO NC
NC
NC
(1) - Global Output Enable
(2) - Global Clock
(3) - Global Set/Reset
Figure 4: CP56 Package
DS091 (v1.0) June 4, 2002
Advance Product Specification
www.xilinx.com
1-800-255-7778
11
R
XC2C32 CoolRunner-II CPLD
Revision History
The following table shows the revision history for this document.
Date
Version
Revision
06/04/02
1.0
Initial Xilinx release.
12
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DS091 (v1.0) June 4, 2002
1-800-255-7778
Advance Product Specification
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