首页 |元器件品牌

XC2C512-6FGG324C [XILINX]

Flash PLD, 6ns, 512-Cell, CMOS, PBGA324, 23 X 23 MM, 1.20 MM PITCH, LEAD FREE, FBGA-324;
XC2C512-6FGG324C
型号： XC2C512-6FGG324C
厂家： XILINX, INC    XILINX, INC
描述：

Flash PLD, 6ns, 512-Cell, CMOS, PBGA324, 23 X 23 MM, 1.20 MM PITCH, LEAD FREE, FBGA-324

输入元件 可编程逻辑
文件： 总26页 (文件大小：415K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
0
R
XC2C512 CoolRunner-II CPLD  
0
0
DS096 (v2.4) October 1, 2004  
Preliminary Product Specification  
Features  
Description  
•
Optimized for 1.8V systems  
The CoolRunner-II 512-macrocell device is designed for  
both high performance and low power applications. This  
lends power savings to high-end communication equipment  
and high speed to battery operated devices. Due to the low  
power stand-by and dynamic operation, overall system reli-  
ability is improved  
-
-
As fast as 6.0 ns pin-to-pin delays  
As low as 14 µA quiescent current  
•
Industry’s best 0.18 micron CMOS CPLD  
-
-
Optimized architecture for effective logic synthesis  
Multi-voltage I/O operation — 1.5V to 3.3V  
This device consists of thirty two Function Blocks inter-con-  
nected by a low power Advanced Interconnect Matrix (AIM).  
The AIM feeds 40 true and complement inputs to each  
Function Block. The Function Blocks consist of a 40 by 56  
P-term PLA and 16 macrocells which contain numerous  
configuration bits that allow for combinational or registered  
modes of operation.  
•
•
Available in multiple package options  
-
-
-
-
208-pin PQFP with 173 user I/O  
256-ball FT (1.0mm) BGA with 212 user I/O  
324-ball FG (1.2mm) BGA with 270 user I/O  
Pb-free available for all packages  
Advanced system features  
-
Fastest in system programming  
1.8V ISP using IEEE 1532 (JTAG) interface  
Additionally, these registers can be globally reset or preset  
and configured as a D or T flip-flop or as a D latch. There  
are also multiple clock signals, both global and local product  
term types, configured on a per macrocell basis. Output pin  
configurations include slew rate limit, bus hold, pull-up,  
open drain and programmable grounds. A Schmitt-trigger  
input is available on a per input pin basis. In addition to stor-  
ing macrocell output states, the macrocell registers may be  
configured as "direct input" registers to store signals directly  
from input pins.  
·
-
-
-
IEEE1149.1 JTAG Boundary Scan Test  
Optional Schmitt-trigger input (per pin)  
Unsurpassed low power management  
·
DataGATE enable signal control  
-
-
-
Four seperate output banks  
RealDigital 100% CMOS product term generation  
Flexible clocking modes  
·
·
·
Optional DualEDGE triggered registers  
Clock divider (divide by 2,4,6,8,10,12,14,16)  
CoolCLOCK  
Clocking is available on a global or Function Block basis.  
Three global clocks are available for all Function Blocks as  
a synchronous clock source. Macrocell registers can be  
individually configured to power up to the zero or one state.  
A global set/reset control line is also available to asynchro-  
nously set or reset selected registers during operation.  
Additional local clock, synchronous clock-enable, asyncho-  
nous set/reset and output enable signals can be formed  
using product terms on a per-macrocell or per-Function  
Block basis.  
-
Global signal options with macrocell control  
·
Multiple global clocks with phase selection per  
macrocell  
·
·
Multiple global output enables  
Global set/reset  
-
-
Advanced design security  
PLA architecture  
·
·
Superior pinout retention  
100% product term routability across function  
block  
A DualEDGE flip-flop feature is also available on a per mac-  
rocell basis. This feature allows high performance synchro-  
nous operation based on lower frequency clocking to help  
reduce the total power consumption of the device.  
-
-
Open-drain output option for Wired-OR and LED  
drive  
Optional bus-hold, 3-state or weak pullup on  
selected I/O pins  
Circuitry has also been included to divide one externally  
supplied global clock (GCK2) by eight different selections.  
This yields divide by even and odd clock frequencies.  
-
-
Optional configurable grounds on unused I/Os  
Mixed I/O voltages compatible with 1.5V, 1.8V,  
2.5V, and 3.3V logic levels  
The use of the clock divide (division by 2) and DualEDGE  
flip-flop gives the resultant CoolCLOCK feature.  
·
SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility  
-
Hot Pluggable  
DataGATE is a method to selectively disable inputs of the  
CPLD that are not of interest during certain points in time.  
Refer to the CoolRunner™-II family data sheet for architec-  
ture description.  
© 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS096 (v2.4) October 1, 2004  
www.xilinx.com  
1
Preliminary Product Specification  
1-800-255-7778  
R
XC2C512 CoolRunner-II CPLD  
By mapping a signal to the DataGATE function, lower power  
can be achieved due to reduction in signal switching.  
Supported I/O Standards  
The CoolRunner-II 512 macrocell features LVCMOS,  
LVTTL, SSTL, and HSTL I/O implementations. See Table 1  
for I/O standard voltages. The LVTTL I/O standard is a gen-  
eral purpose EIA/JEDEC standard for 3.3V applications that  
use an LVTTL input buffer and Push-Pull output buffer. The  
LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications.  
Both HSTL and SSTL I/O standards make use of a VREF pin  
for JEDEC compliance. CoolRunner-II CPLDs are also 1.5V  
I/O compatible with the use of Schmitt-trigger inputs.  
Another feature that eases voltage translation is output  
banking. Four output banks are available on the  
CoolRunner-II 512 macrocell device that permits easy inter-  
facing to 3.3V, 2.5V, 1.8V, and 1.5V devices.  
The CoolRunner-II 512 macrocell CPLD is I/O compatible  
with various JEDEC I/O standards (see Table 1). This  
device is also 1.5V I/O compatible with the use of  
Schmitt-trigger inputs.  
Table 1: I/O Standards for XC2C512  
RealDigital Design Technology  
Board  
Input Termination  
VCCIO VREF Voltage VTT  
Xilinx CoolRunner-II CPLDs are fabricated on a 0.18 micron  
process technology which is derived from leading edge  
FPGA product development. CoolRunner-II CPLDs employ  
RealDigital, a design technique that makes use of CMOS  
technology in both the fabrication and design methodology.  
RealDigital design technology employs a cascade of CMOS  
gates to implement sum of products instead of traditional  
sense amplifier methodology. Due to this technology, Xilinx  
CoolRunner-II CPLDs achieve both high-performance and  
low power operation.  
Output  
VCCIO  
Input  
I/O Types  
LVTTL  
3.3  
3.3  
2.5  
1.8  
1.5  
1.5  
2.5  
3.3  
3.3  
3.3  
2.5  
1.8  
1.5  
1.5  
2.5  
3.3  
N/A  
N/A  
N/A  
N/A  
N/A  
0.75  
1.25  
1.5  
N/A  
N/A  
N/A  
N/A  
N/A  
0.75  
1.25  
1.5  
LVCMOS33  
LVCMOS25  
LVCMOS18  
1.5V I/O  
HSTL-1  
SSTL2-1  
SSTL3-1  
For information on Vref pins, see XAPP399.  
250  
200  
150  
-7 -10  
100  
50  
0
200  
0
20  
40  
60  
80  
100  
120  
140  
160 180  
Frequency (MHz)  
Figure 1: ICC vs Frequency  
DS096_01_022003  
Table 2: ICC vs Frequency (LVCMOS 1.8V TA = 25°C)(1)  
Frequency (MHz)  
0
20  
40  
60  
80  
100  
125  
150  
200  
Typical -7, -10 ICC (mA)  
Typical -6 ICC (mA)  
Notes:  
0.025  
17.22  
34.37  
52.04  
69.44  
86.85  
108.61 130.37  
1. 16-bit up/down, resettable binary counter (one counter per function block).  
2
www.xilinx.com  
1-800-255-7778  
DS096 (v2.4) October 1, 2004  
Preliminary Product Specification  
R
XC2C512 CoolRunner-II CPLD  
Absolute Maximum Ratings  
Symbol  
Description  
Supply voltage relative to ground  
Supply voltage for output drivers  
Value  
Units  
V
VCC  
–0.5 to 2.0  
–0.5 to 4.0  
-0.5 to 4.0  
-0.5 to 4.0  
–0.5 to 4.0  
–0.5 to 4.0  
–65 to +150  
+150  
VCCIO  
V
(2)  
VJTAG  
VAUX  
JTAG input voltage limits  
V
JTAG input supply voltage  
Input voltage relative to ground(1)  
Voltage applied to 3-state output(1)  
Storage Temperature (ambient)  
Junction Temperature  
V
(1)  
VIN  
V
(1)  
VTS  
V
(3)  
TSTG  
TJ  
°C  
°C  
Notes:  
1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easiest to achieve. During transitions,  
the device pins may undershoot to –2.0v or overshoot to +4.5V, provided this over or undershoot lasts less than 10 ns and with the  
forcing current being limited to 200 mA.  
2. Valid over commercial temperature range.  
3. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb free  
packages, see XAPP427.  
Recommended Operating Conditions  
Symbol  
Parameter  
Min  
1.7  
1.7  
3.0  
2.3  
1.7  
1.4  
1.7  
Max  
1.9  
1.9  
3.6  
2.7  
1.9  
1.6  
3.6  
Units  
VCC  
Supply voltage for internal logic and Commercial TA = 0°C to +70°C  
V
V
V
V
V
V
V
input buffers  
Industrial TA = –40°C to +85°C  
VCCIO  
Supply voltage for output drivers @ 3.3V operation  
Supply voltage for output drivers @ 2.5V operation  
Supply voltage for output drivers @ 1.8V operation  
Supply voltage for output drivers @ 1.5V operation  
JTAG programming  
VAUX  
DC Electrical Characteristics (Over Recommended Operating Conditions)  
Symbol  
ICCSB  
Parameter  
Standby current (-6)  
Test Conditions  
VCC = 1.9V, VCCIO = 3.6V  
VCC = 1.9V, VCCIO = 3.6V  
VCC = 1.9V, VCCIO = 3.6V  
f = 1 MHz  
Typical  
Max.  
Units  
µA  
ICCSB  
Standby current (-7, -10)  
Standby current (-10 industrial)  
Dynamic current (-6)  
50  
200  
250  
µA  
ICCSB  
150  
µA  
(1)  
ICC  
-
-
-
-
-
-
-
mA  
mA  
mA  
mA  
pF  
f = 50 MHz  
(1)  
ICC  
Dynamic current (-7, -10)  
f = 1 MHz  
1
f = 50 MHz  
55  
10  
12  
10  
CJTAG  
CCLK  
CIO  
JTAG input capacitance  
Global clock input capacitance  
I/O capacitance  
f = 1 MHz  
f = 1 MHz  
pF  
f = 1 MHz  
pF  
DS096 (v2.4) October 1, 2004  
www.xilinx.com  
3
Preliminary Product Specification  
1-800-255-7778  
R
XC2C512 CoolRunner-II CPLD  
Symbol  
Parameter  
Test Conditions  
VIN = 0V or VCCIO to 3.9V  
VIN = 0V or VCCIO to 3.9V  
Typical  
–1  
Max.  
Units  
µA  
(2)  
IIL  
Input leakage current  
I/O High-Z leakage  
1
1
(2)  
IIH  
–1  
µA  
Notes:  
1. 16-bit up/down, resettable binary counter (one counter per function block) tested at VCC= VCCIO = 1.9V.  
2. See Quality and Reliability section of the CoolRunner-II family data sheet.  
LVCMOS 3.3V and LVTTL 3.3V DC Voltage Specifications  
Symbol  
VCCIO  
VIH  
Parameter  
Input source voltage  
Test Conditions  
Min.  
Max.  
3.6  
3.9  
0.8  
-
Units  
3.0  
V
V
V
V
V
V
V
High level input voltage  
Low level input voltage  
High level output voltage  
2
VIL  
–0.3  
VOH  
IOH = –8 mA, VCCIO = 3V  
VCCIO – 0.4V  
I
OH = –0.1 mA, VCCIO = 3V  
VCCIO – 0.2V  
-
VOL  
Low level output voltage  
IOL = 8 mA, VCCIO = 3V  
IOL = 0.1 mA, VCCIO = 3V  
-
-
0.4  
0.2  
LVCMOS 2.5V DC Voltage Specifications  
Symbol  
VCCIO  
VIH  
Parameter  
Input source voltage  
Test Conditions  
Min.  
Max.  
2.7  
3.9  
0.7  
-
Units  
2.3  
V
V
V
V
V
V
V
High level input voltage  
Low level input voltage  
High level output voltage  
1.7  
VIL  
–0.3  
VOH  
IOH = –8 mA, VCCIO = 2.3V  
VCCIO – 0.4V  
I
OH = –0.1 mA, VCCIO = 2.3V  
VCCIO – 0.2V  
-
VOL  
Low level output voltage  
IOL = 8 mA, VCCIO = 2.3V  
-
-
0.4  
0.2  
I
OL = 0.1mA, VCCIO = 2.3V  
4
www.xilinx.com  
DS096 (v2.4) October 1, 2004  
1-800-255-7778  
Preliminary Product Specification  
R
XC2C512 CoolRunner-II CPLD  
LVCMOS 1.8V DC Voltage Specifications  
Symbol  
VCCIO  
VIH  
Parameter  
Input source voltage  
Test Conditions  
Min.  
Max.  
Units  
1.7  
1.9  
V
V
V
V
V
V
V
High level input voltage  
Low level input voltage  
High level output voltage  
0.65 x VCCIO  
3.9  
VIL  
–0.3  
0.35 x VCCIO  
VOH  
IOH = –8 mA, VCCIO = 1.7V  
OH = –0.1 mA, VCCIO = 1.7V  
VCCIO – 0.45  
-
-
I
VCCIO – 0.2  
VOL  
Low level output voltage  
IOL = 8 mA, VCCIO = 1.7V  
IOL = 0.1 mA, VCCIO = 1.7V  
-
-
0.45  
0.2  
(1)  
1.5V DC Voltage Specifications  
Symbol  
VCCIO  
VIH  
Parameter  
Input source voltage  
Test Conditions  
Min.  
1.4  
Max.  
Units  
1.6  
V
V
V
V
V
V
V
High level input voltage  
Low level input voltage  
High level output voltage  
0.5 x VCCIO  
0.2 x VCCIO  
VCCIO – 0.45  
VCCIO – 0.2  
-
0.8 x VCCIO  
VIL  
0.5 x VCCIO  
VOH  
IOH = –8 mA, VCCIO = 1.4V  
-
I
OH = –0.1 mA, VCCIO = 1.4V  
-
VOL  
Low level output voltage  
IOL = 8 mA, VCCIO = 1.4V  
IOL = 0.1 mA, VCCIO = 1.4V  
0.4  
0.2  
-
Notes:  
1. Hysteresis used on 1.5V inputs.  
Schmitt Trigger Input DC Voltage Specifications  
Symbol  
VCCIO  
VT+  
Parameter  
Test Conditions  
Min.  
1.4  
Max.  
3.9  
Units  
Input source voltage  
V
V
V
Input hysteresis threshold voltage  
0.5 x VCCIO  
0.2 x VCCIO  
0.8 x VCCIO  
0.5 x VCCIO  
VT-  
SSTL2-1 DC Voltage Specifications  
Symbol  
Parameter  
Test Conditions  
Min.  
2.3  
Typ  
Max.  
Units  
VCCIO  
Input source voltage  
Input reference voltage  
Termination voltage  
2.5  
2.7  
1.35  
V
V
V
V
V
V
V
(1)  
VREF  
1.15  
1.25  
(2)  
VTT  
VREF – 0.04  
VREF + 0.18  
–0.3  
1.25  
VREF + 0.04  
3.9  
VIH  
VIL  
High level input voltage  
Low level input voltage  
High level output voltage  
Low level output voltage  
-
-
-
-
VREF – 0.18  
-
VOH  
VOL  
Notes:  
IOH = –8 mA, VCCIO = 2.3V  
IOL = 8 mA, VCCIO = 2.3V  
VCCIO – 0.62  
-
0.54  
1. VREF should track the variations in VCCIO, also peak to peak AC noise on VREF may not exceed ±2% VREF  
2. VTT of transmitting device must track VREF of receiving devices  
DS096 (v2.4) October 1, 2004  
www.xilinx.com  
5
Preliminary Product Specification  
1-800-255-7778  
R
XC2C512 CoolRunner-II CPLD  
SSTL3-1 DC Voltage Specifications  
Symbol  
Parameter  
Test Conditions  
Min.  
3.0  
Typ  
3.3  
1.5  
1.5  
-
Max.  
3.6  
Units  
VCCIO  
Input source voltage  
Input reference voltage  
Termination voltage  
High level input voltage  
Low level input voltage  
V
V
V
V
V
V
V
(1)  
VREF  
1.3  
1.7  
(2)  
VTT  
VREF – 0.05  
VREF + 0.2  
–0.3  
VREF + 0.05  
VCCIO + 0.3  
VREF – 0.2  
-
VIH  
VIL  
-
VOH  
VOL  
Notes:  
High level output voltage IOH = –8 mA, VCCIO = 3V  
Low level output voltage IOL = 8 mA, VCCIO = 3V  
VCCIO – 1.1  
-
-
-
0.7  
1. VREF should track the variations in VCCIO, also peak to peak AC noise on VREF may not exceed ±2% VREF  
2. VTT of transmitting device must track VREF of receiving devices  
HSTL1 DC Voltage Specifications  
Symbol  
Parameter  
Test Conditions  
Min.  
1.4  
Typ  
Max.  
Units  
VCCIO  
Input source voltage  
Input reference voltage  
Termination voltage  
1.5  
1.6  
V
V
V
V
V
V
V
(1)  
VREF  
0.68  
0.75  
0.90  
(2)  
VTT  
-
VCCIO x 0.5  
-
VIH  
VIL  
High level input voltage  
Low level input voltage  
High level output voltage  
Low level output voltage  
VREF + 0.1  
–0.3  
-
-
-
-
1.9  
VREF – 0.1  
VOH  
VOL  
Notes:  
IOH = –8 mA, VCCIO = 1.7V VCCIO – 0.4  
IOL = 8 mA, VCCIO = 1.7V  
-
-
0.4  
1. VREF should track the variations in VCCIO, also peak-to-peak AC noise on VREF may not exceed ±2% VREF  
2. VTT of transmitting device must track VREF of receiving devices  
6
www.xilinx.com  
DS096 (v2.4) October 1, 2004  
1-800-255-7778  
Preliminary Product Specification  
R
XC2C512 CoolRunner-II CPLD  
AC Electrical Characteristics Over Recommended Operating Conditions  
-6(5)  
Min. Max. Min. Max. Min. Max.  
-7  
-10  
Unit  
s
Symbol  
TPD1  
Parameter  
Propagation delay (single p-term)  
Propagation delay (OR array)  
Direct input register set-up time  
Setup time fast (single p-term)  
Setup time (OR array)  
-
-
5.7  
-
-
7.1  
-
-
9.2  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
TPD2  
TSUD  
TSU1  
TSU2  
TH  
6.0  
7.5  
10.0  
2.4  
2.3  
2.6  
0
-
2.8  
2.6  
3.0  
0
-
3.5  
3.1  
3.9  
0
-
-
-
-
-
-
-
Direct input register hold time  
P-term hold time  
-
-
-
TH  
0
-
4.4  
416  
217  
204  
149  
143  
-
0
-
5.8  
250  
179  
167  
119  
114  
-
0
-
TCO  
Clock to output  
-
-
-
7.8  
(1)  
FTOGGLE  
Internal toggle rate  
-
-
-
166 MHz  
128 MHz  
116 MHz  
(2)  
(2)  
FSYSTEM1  
FSYSTEM2  
Maximum system frequency  
Maximum system frequency  
Maximum external frequency  
Maximum external frequency  
Direct input register p-term clock setup time  
P-term clock setup time (single p-term)  
P-term clock setup time (OR array)  
Direct input register p-term clock hold time  
P-term clock hold  
-
-
-
-
-
-
(3)  
FEXT1  
-
-
-
91  
MHz  
MHz  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
(3)  
FEXT2  
-
-
-
85  
TPSUD  
TPSU1  
TPSU2  
TPHD  
TPH  
1.0  
1.0  
1.4  
0.5  
0.5  
-
1.3  
1.1  
1.5  
0.7  
0.9  
-
2.1  
1.7  
2.5  
0.9  
1.3  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TPCO  
P-term clock to output  
5.6  
5.5  
6.5  
7.1  
7.4  
7.2  
-
7.3  
6.5  
7.5  
8.6  
7.6  
7.5  
-
9.3  
TOE/TOD  
Global OE to output enable/disable  
-
-
-
9.2  
TPOE/TPOD P-term OE to output enable/disable  
MOE/TMOD Macrocell driven OE to output enable/disable  
-
-
-
10.2  
T
-
-
-
12.5  
TPAO  
P-term set/reset to output valid  
Global set/reset to output valid  
Register clock enable setup time  
Register clock enable hold time  
Global clock pulse width High or Low  
P-term pulse width High or Low  
-
-
-
11.6  
TAO  
-
-
-
11.5  
TSUEC  
THEC  
2.4  
0
2.8  
0
3.2  
0
-
-
-
-
TCW  
1.2  
6.0  
-
2.0  
7.5  
7.5  
0.0  
4.0  
-
-
3.0  
10.0  
10.0  
0.0  
6.0  
-
-
TPCW  
TAPRPW  
TDGSU  
TDGH  
TDGR  
TDGW  
TCDRSU  
-
-
-
Asynchronous preset/reset pulse width (High or Low) 6.0  
-
-
-
Set-up before DataGATE latch assertion  
Hold to DataGATE latch assertion  
DataGATE recovery to new data  
0.0  
3.0  
-
-
-
-
-
-
-
7.0  
-
9.3  
-
11.0  
DataGATE low pulse width  
2.5  
1.2  
3.0  
1.7  
5.0  
2.5  
-
-
CDRST setup time before falling edge GCLK2  
-
-
DS096 (v2.4) October 1, 2004  
www.xilinx.com  
7
Preliminary Product Specification  
1-800-255-7778  
R
XC2C512 CoolRunner-II CPLD  
Symbol  
-6(5)  
Min. Max. Min. Max. Min. Max.  
-7  
-10  
Unit  
s
Parameter  
TCDRH  
TCONFIG  
Notes:  
Hold time CDRST after falling edge GCLK2  
Configuration time  
0
-
-
0
-
-
0
-
-
ns  
(4)  
400  
400  
400  
µs  
1. FTOGGLE is the maximum clock frequency to which a T-Flip Flop can reliably toggle (see the CoolRunner-II family data sheet for more  
information).  
2. FSYSTEM1 (1/TCYCLE) is the internal operating frequency for a device fully populated with 16-bit resettable binary counter through one  
p-term per macrocell while FSYSTEM2 is through the OR array .  
3.  
FEXT1(1/TSU1+TCO) is the maximum external frequency using one p-term while FEXT2 is through the OR array  
4. Typical configuration current during TCONFIG is approximately 15mA  
5. The -6 speed grade is Advanced Specification.  
(1)  
Internal Timing Parameters  
-6(1)  
-7  
-10  
Symbol  
Buffer Delays  
TIN  
Parameter(1)  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Units  
Input buffer delay  
-
-
-
-
-
-
-
2.5  
2.8  
1.8  
2.8  
2.0  
2.4  
3.3  
-
-
-
-
-
-
-
3.1  
3.8  
2.4  
3.8  
2.9  
3.0  
3.6  
-
-
-
-
-
-
-
3.8  
5.0  
3.3  
4.6  
3.7  
3.9  
5.5  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
TDIN  
Direct data register input delay  
Global Clock buffer delay  
Global set/reset buffer delay  
Global 3-state buffer delay  
Output buffer delay  
TGCK  
TGSR  
TGTS  
TOUT  
TEN  
Output buffer enable/disable delay  
P-term Delays  
TCT  
Control term delay  
-
-
-
0.6  
0.4  
0.3  
-
-
-
0.8  
0.5  
0.4  
-
-
-
0.9  
0.8  
0.8  
ns  
ns  
ns  
TLOGI1  
TLOGI2  
Macrocell Delay  
Single P-term delay adder  
Multiple P-term delay adder  
TPDI  
Input to output valid  
-
1.2  
0
0.4  
-
1.4  
0
0.5  
-
1.8  
0
0.7  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
TSUI  
Setup before clock  
-
-
-
-
-
-
THI  
Hold after clock  
TECSU  
TECHO  
TCOI  
TAOI  
Enable clock setup time  
Enable clock hold time  
Clock to output valid  
Set/reset to output valid  
Clock doubler delay  
1.2  
0
-
1.3  
0
-
1.8  
0
-
-
-
-
-
0.2  
0.6  
0
-
0.4  
0.7  
0
-
0.7  
3.0  
0
-
-
-
TCDBL  
-
-
-
Feedback Delays  
TF  
Feedback delay  
Macrocell to global OE delay  
-
-
2.8  
1.6  
-
-
3.3  
2.2  
-
-
4.5  
3.0  
ns  
ns  
TOEM  
I/O Standard Time Adder Delays 1.5V I/O  
TIN15  
Standard input adder  
Hysteresis input adder  
-
-
0.5  
2.0  
-
-
0.8  
3.0  
-
-
1.0  
4.0  
ns  
ns  
THYS15  
8
www.xilinx.com  
1-800-255-7778  
DS096 (v2.4) October 1, 2004  
Preliminary Product Specification  
R
XC2C512 CoolRunner-II CPLD  
(1)  
Internal Timing Parameters (Continued)  
-6(1)  
-7  
-10  
Symbol  
TOUT15  
TSLEW15  
I/O Standard Time Adder Delays 1.8V CMOS  
Parameter(1)  
Output adder  
Output slew rate adder  
Min.  
Max.  
0.5  
Min.  
Max.  
0.8  
Min.  
Max.  
1.0  
Units  
ns  
-
-
-
-
-
-
2.0  
3.0  
4.0  
ns  
THYS18  
TOUT18  
TSLEW  
Notes:  
Hysteresis input adder  
Output adder  
-
-
-
1.5  
0
-
-
-
2.0  
0
-
-
-
3.0  
0
ns  
ns  
ns  
Output slew rate adder  
1.5  
2.0  
4.0  
1. The -6 speed grade is Advanced Specification.  
DS096 (v2.4) October 1, 2004  
www.xilinx.com  
9
Preliminary Product Specification  
1-800-255-7778  
R
XC2C512 CoolRunner-II CPLD  
(1)  
Internal Timing Parameters (Continued)  
-6(1)  
-7  
-10  
Symbol  
I/O Standard Time Adder Delays 2.5V CMOS  
Parameter(1)  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Units  
TIN25  
Standard input adder  
Hysteresis input adder  
Output adder  
-
-
-
-
0.5  
1.2  
0.7  
2.0  
-
-
-
-
0.6  
1.5  
0.8  
3.0  
-
-
-
-
1.0  
3.0  
2.0  
4.0  
ns  
ns  
ns  
ns  
THYS25  
TOUT25  
TSLEW25  
Output slew rate adder  
I/O Standard Time Adder Delays 3.3V CMOS/TTL  
TIN33  
Standard input adder  
Hysteresis input adder  
Output adder  
-
-
-
-
0.4  
1.0  
1.0  
2.0  
-
-
-
-
0.5  
1.2  
1.2  
3.0  
-
-
-
-
2.0  
3.0  
3.0  
4.0  
ns  
ns  
ns  
ns  
THYS33  
TOUT33  
TSLEW33  
Output slew rate adder  
I/O Standard Time Adder Delays HSTL, SSTL  
SSTL2-1  
SSTL3-1  
HSTL-1  
Notes:  
Input adder to TIN, TDIN, TGCK  
,
,
,
-
0.3  
-
0.4  
-
1.0  
ns  
T
GSR,TGTS  
Output adder to TOUT  
-
-
0.0  
0.3  
-
-
-0.5  
0.4  
-
-
0.0  
1.0  
ns  
ns  
Input adder to TIN, TDIN, TGCK  
T
GSR,TGTS  
Output adder to TOUT  
-
-
0.0  
0.5  
-
-
-0.50  
0.6  
-
-
0.0  
1.0  
ns  
ns  
Input adder to TIN, TDIN, TGCK  
T
GSR,TGTS  
Output adder to TOUT  
-
0.0  
-
0.0  
-
0.0  
ns  
1. 1.5 ns input pin signal rise/fall.  
10  
www.xilinx.com  
1-800-255-7778  
DS096 (v2.4) October 1, 2004  
Preliminary Product Specification  
R
XC2C512 CoolRunner-II CPLD  
Switching Characteristics  
AC Test Circuit  
V
CC  
V
CC  
= V  
= 1.8V @ 25oC  
CCIO  
7.0  
6.8  
6.6  
6.4  
R
1
Device  
Under Test  
Test Point  
R
C
L
2
Output Type  
LVTTL33  
R
R
C
L
1
2
268Ω  
275Ω  
188Ω  
235Ω  
275Ω  
35 pF  
35 pF  
35pF  
35pF  
35pF  
LVCMOS33  
LVCMOS25  
LVCMOS18  
LVCMOS15  
188Ω  
112.5Ω  
150Ω  
112.5Ω  
150Ω  
6.2  
6.0  
C
includes test fixtures and probe capacitance.  
L
1.5 nsec maximum rise/fall times on inputs.  
2
16  
1
8
4
DS_ACT_08_14_02  
Number of Outputs Switching  
Figure 3: Load Circuit  
DS096_02_022003  
Figure 2: Derating Curve for TPD  
Typical I/O Output Curves  
80  
60  
3.3V  
2.5V  
40  
1.8V  
20  
IOL  
1.5V  
0
0
.5  
1.0  
1.5  
2.0  
2.5  
3.0  
3.5  
VO (Output Volts)  
XC512VoIo_all022003  
Figure 4: Typical Derating Curve for XC2C512  
DS096 (v2.4) October 1, 2004  
www.xilinx.com  
11  
Preliminary Product Specification  
1-800-255-7778  
R
XC2C512 CoolRunner-II CPLD  
11  
Pin Descriptions (Continued)  
Pin Descriptions  
Function  
Block  
Macro-  
cell  
I/O  
Bank  
Function  
Block  
Macro-  
cell  
I/O  
Bank  
PQ208 FT256  
FG324  
PQ208 FT256  
FG324  
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
1
2
205  
-
A2  
-
B3  
C4  
B4  
C5  
B5  
-
2
2
2
2
2
-
1(GTS0)  
1
2
7
D4  
B2  
E3  
C3  
-
C1  
C2  
B1  
B2  
-
2
2
2
2
-
-
1
6
3
203  
1(GTS3)  
3
5
4
-
C5  
A3  
-
1
4
4
5
202  
1
5
-
6
-
1
6
-
-
-
-
7
-
-
-
-
1
7
-
-
-
-
8
-
-
-
-
1
8
-
-
-
-
9
-
-
-
-
1
9
-
-
-
-
10  
11  
12  
13  
14  
15  
16  
1
-
-
-
-
1
10  
11  
12  
13  
14  
15  
16  
1
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
1
-
-
-
-
201  
E7  
A4  
C6  
B5  
C1  
E2  
F2  
E6  
-
A3  
A4  
D6  
A5  
G3  
G2  
G1  
H4  
-
2
2
2
2
2
2
2
2
-
1(GTS2)  
3
D3  
B3  
B4  
C4  
A1  
-
D3  
C3  
A1  
A2  
D2  
D1  
F4  
F3  
-
2
2
2
2
2
2
2
2
-
-
1
2
200  
1
208  
199  
1(GSR)  
206  
-
14  
-
2
-
8
-
2
2
2
3
2
3
D2  
-
4
15  
-
2
4
-
5
2
5
-
-
6
-
-
-
-
2
6
-
-
-
-
7
-
-
-
-
2
7
-
-
-
-
8
-
-
-
-
2
8
-
-
-
-
9
-
-
-
-
2
9
-
-
-
-
10  
11  
12  
13  
14  
15  
16  
-
-
-
-
2
10  
11  
12  
13  
14  
15  
16  
-
-
-
-
-
-
-
-
2
-
-
-
-
-
-
-
-
2
-
-
-
-
-
F3  
D1  
G4  
E1  
H3  
H2  
H1  
J4  
2
2
2
2
2
-
C2  
E5  
B1  
E4  
E2  
E1  
F2  
G4  
2
2
2
2
16  
17  
18  
2(GTS1)  
9
10  
12  
2
2
12  
www.xilinx.com  
1-800-255-7778  
DS096 (v2.4) October 1, 2004  
Preliminary Product Specification  
R
XC2C512 CoolRunner-II CPLD  
Pin Descriptions (Continued)  
Pin Descriptions (Continued)  
Function  
Block  
Macro-  
cell  
I/O  
Bank  
Function  
Block  
Macro-  
cell  
I/O  
Bank  
PQ208 FT256  
FG324  
PQ208 FT256  
FG324  
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
1
2
198  
D6  
A5  
E8  
B6  
C7  
-
C6  
B6  
A6  
D7  
C7  
-
2
2
2
2
2
-
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
1
2
191  
-
E9  
A7  
D8  
B8  
-
B8  
A8  
D9  
C9  
B9  
-
2
2
2
2
2
-
197  
-
3
196  
3
189  
4
195  
4
188  
5
194  
5
187  
6
-
6
-
7
-
-
-
-
7
-
-
-
-
8
-
-
-
-
8
-
-
-
-
9
-
-
-
-
9
-
-
-
-
10  
11  
12  
13  
14  
15  
16  
1
-
-
-
-
10  
11  
12  
13  
14  
15  
16  
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
193  
-
B7  
A7  
D8  
C8  
J3  
J2  
J1  
K4  
-
2
2
2
2
2
2
2
2
-
186  
C8  
A8  
E11  
E10  
H2  
-
A9  
D10  
C10  
B10  
L4  
L3  
L2  
M1  
-
2
2
2
2
2
2
2
2
-
-
A6  
D7  
B7  
G3  
G2  
-
185  
192  
184  
-
19  
20  
21  
-
183  
-
22  
23  
-
2
2
3
3
H4  
-
4
F5  
-
4
5
-
5
-
-
6
-
-
-
-
6
-
-
-
-
7
-
-
-
-
7
-
-
-
-
8
-
-
-
-
8
-
-
-
-
9
-
-
-
-
9
-
-
-
-
10  
11  
12  
13  
14  
15  
16  
-
-
-
-
10  
11  
12  
13  
14  
15  
16  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
K3  
K2  
K1  
L1  
2
2
2
2
-
G1  
H3  
H1  
H5  
M2  
M3  
M4  
N1  
2
2
2
2
-
F1  
-
25  
-
-
-
G5  
-
DS096 (v2.4) October 1, 2004  
Preliminary Product Specification  
www.xilinx.com  
1-800-255-7778  
13  
R
XC2C512 CoolRunner-II CPLD  
Pin Descriptions (Continued)  
Pin Descriptions (Continued)  
Function  
Block  
Macro-  
cell  
I/O  
Bank  
Function  
Block  
Macro-  
cell  
I/O  
Bank  
PQ208 FT256  
FG324  
PQ208 FT256  
FG324  
9
1
2
-
50  
49  
48  
-
-
N3  
-
AA2  
1
1
1
1
-
11  
11  
1
2
45  
-
P1  
M4  
M2  
L3  
-
W2  
W1  
V3  
U4  
-
1
1
1
1
-
9
AB1  
9
3
AA1  
11(GCK0)  
11  
3
44  
43  
-
9
4
-
W4  
4
9
5
-
-
11  
5
9
6
-
-
-
-
11  
6
-
-
-
-
9
7
-
-
-
-
11  
7
-
-
-
-
9
8
-
-
-
-
11  
8
-
-
-
-
9
9
-
-
-
-
-
11  
9
-
-
-
-
9
10  
11  
12  
13  
14  
15  
16  
1
-
-
-
11  
10  
11  
12  
13  
14  
15  
16  
1
-
-
-
-
9
-
-
-
-
11  
-
-
-
-
9
-
-
-
-
11  
-
-
-
-
9
-
R1  
N4  
N2  
M3  
P2  
P4  
P5  
R2  
-
Y3  
Y2  
W3  
Y1  
AB2  
Y4  
AB3  
AA4  
-
1
1
1
1
1
1
1
1
-
11  
41  
40  
39  
38  
60  
61  
62  
63  
64  
-
N1  
L4  
M1  
L5  
R4  
M5  
R5  
R6  
-
V2  
V1  
U3  
U2  
AB5  
Y6  
AA6  
AB6  
W7  
-
1
1
1
1
1
1
1
1
1
-
9
47  
-
11  
9
11  
9(GCK1)  
46  
51  
54  
55  
56  
-
11  
10(CDRST)  
12  
10  
2
12  
2
10(GCK2)  
3
12  
3
10  
10  
4
12  
4
5
12  
5
10  
6
-
-
-
-
12  
6
-
10  
7
-
-
-
-
12  
7
-
-
-
-
10  
8
-
-
-
-
12  
8
-
-
-
-
10  
9
-
-
-
-
12  
9
-
-
-
-
10  
10  
11  
12  
13  
14  
15  
16  
-
-
-
-
12  
10  
11  
12  
13  
14  
15  
16  
-
-
-
-
10  
-
-
-
-
12  
-
-
-
-
10  
-
-
-
-
12  
-
-
-
-
10  
57  
58  
-
T1  
T2  
-
Y5  
AA5  
AB4  
W6  
1
1
1
1
12  
65  
66  
67  
-
N6  
-
Y7  
AA7  
AB7  
W8  
1
1
1
1
10(DGE)  
10  
12  
12  
R3  
-
10  
-
N5  
12  
14  
www.xilinx.com  
1-800-255-7778  
DS096 (v2.4) October 1, 2004  
Preliminary Product Specification  
R
XC2C512 CoolRunner-II CPLD  
Pin Descriptions (Continued)  
Pin Descriptions (Continued)  
Function  
Block  
Macro-  
cell  
I/O  
Bank  
Function  
Block  
Macro-  
cell  
I/O  
Bank  
PQ208 FT256  
FG324  
PQ208 FT256  
FG324  
13  
13  
13  
13  
13  
13  
13  
13  
13  
13  
13  
13  
13  
13  
13  
13  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
1
2
37  
-
-
K4  
L2  
-
U1  
1
1
1
1
-
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
1
2
31  
-
J4  
R1  
1
1
1
1
-
T4  
K1  
P4  
3
36  
35  
-
T3  
3
30  
29  
-
J3  
P3  
4
T2  
4
J2  
P2  
5
-
-
5
-
-
6
-
-
-
-
6
-
-
-
-
7
-
-
-
-
7
-
-
-
-
8
-
-
-
-
-
8
-
-
-
-
9
-
-
-
9
-
-
-
-
10  
11  
12  
13  
14  
15  
16  
1
-
-
-
-
10  
11  
12  
13  
14  
15  
16  
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
K3  
L1  
K5  
K2  
M6  
-
T1  
R4  
R3  
R2  
Y8  
AA8  
AB8  
W9  
Y9  
-
1
1
1
1
1
1
1
1
1
-
28  
27  
-
J5  
P1  
N4  
N3  
N2  
AA10  
AB10  
AB11  
W11  
AA11  
-
1
1
1
1
1
1
1
1
1
-
34  
32  
-
J1  
-
-
-
-
74  
-
N7  
2
-
2
-
3
69  
70  
71  
-
T3  
P6  
T4  
-
3
75  
76  
77  
-
R7  
4
4
M7  
5
5
T6  
-
6
6
7
-
-
-
-
7
-
-
-
-
8
-
-
-
-
8
-
-
-
-
9
-
-
-
-
9
-
-
-
-
10  
11  
12  
13  
14  
15  
16  
-
-
-
-
10  
11  
12  
13  
14  
15  
16  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
72  
-
P7  
-
AA9  
AB9  
W10  
Y10  
1
1
1
1
-
-
Y11  
AB12  
AA12  
Y12  
1
1
1
1
78  
-
-
73  
-
T5  
-
-
-
-
DS096 (v2.4) October 1, 2004  
Preliminary Product Specification  
www.xilinx.com  
1-800-255-7778  
15  
R
XC2C512 CoolRunner-II CPLD  
Pin Descriptions (Continued)  
Pin Descriptions (Continued)  
Function  
Block  
Macro-  
cell  
I/O  
Bank  
Function  
Block  
Macro-  
cell  
I/O  
Bank  
PQ208 FT256  
FG324  
PQ208 FT256  
FG324  
17  
17  
17  
17  
17  
17  
17  
17  
17  
17  
17  
17  
17  
17  
17  
17  
18  
18  
18  
18  
18  
18  
18  
18  
18  
18  
18  
18  
18  
18  
18  
18  
1
2
161  
A16  
A21  
4
4
4
4
4
-
19  
19  
19  
19  
19  
19  
19  
19  
19  
19  
19  
19  
19  
19  
19  
19  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
1
2
170  
D13  
C17  
4
4
4
4
4
-
162  
B13  
B20  
171  
A14  
B17  
3
163  
-
C19  
3
173  
E13  
A17  
4
164  
-
B19  
4
-
A13  
D16  
5
165  
B14  
C18  
5
-
C11  
C16  
6
-
-
-
6
-
-
-
7
-
-
-
-
7
-
-
-
-
8
-
-
-
-
8
-
-
-
-
9
-
-
-
-
9
-
-
-
-
10  
11  
12  
13  
14  
15  
16  
1
-
-
-
-
-
10  
11  
12  
13  
14  
15  
16  
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
166  
C13  
B18  
A19  
D17  
A18  
A22  
B21  
B22  
C20  
-
4
4
4
4
4
4
4
4
-
-
A12  
B11  
D11  
A11  
G12  
D15  
E14  
C16  
-
B16  
A16  
D15  
C15  
D21  
D22  
E20  
F19  
-
4
4
4
4
4
4
4
4
-
167  
A15  
-
168  
C12  
-
169  
B12  
-
160  
B15  
-
2
-
C14  
2
-
3
-
G11  
3
155  
4
159  
B16  
4
154  
5
-
-
5
-
6
-
-
-
-
6
-
-
-
-
7
-
-
-
-
7
-
-
-
-
8
-
-
-
-
8
-
-
-
-
-
9
-
-
-
-
9
-
-
-
10  
11  
12  
13  
14  
15  
16  
-
-
-
-
10  
11  
12  
13  
14  
15  
16  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C21  
D19  
D20  
C22  
4
4
4
4
153  
152  
151  
150  
F14  
D16  
F13  
E15  
E21  
E22  
F20  
F21  
4
4
4
4
-
158  
-
D14  
-
C15  
16  
www.xilinx.com  
1-800-255-7778  
DS096 (v2.4) October 1, 2004  
Preliminary Product Specification  
R
XC2C512 CoolRunner-II CPLD  
Pin Descriptions (Continued)  
Pin Descriptions (Continued)  
Function  
Block  
Macro-  
cell  
I/O  
Bank  
Function  
Block  
Macro-  
cell  
I/O  
Bank  
PQ208 FT256  
FG324  
PQ208 FT256  
FG324  
21  
21  
21  
21  
21  
21  
21  
21  
21  
21  
21  
21  
21  
21  
21  
21  
22  
22  
22  
22  
22  
22  
22  
22  
22  
22  
22  
22  
22  
22  
22  
22  
1
2
-
D10  
B15  
4
4
4
4
4
-
23  
23  
23  
23  
23  
23  
23  
23  
23  
23  
23  
23  
23  
23  
23  
23  
24  
24  
24  
24  
24  
24  
24  
24  
24  
24  
24  
24  
24  
24  
24  
24  
1
2
179  
B9  
A12  
4
4
4
4
4
-
174  
B10  
A15  
180  
-
D12  
3
175  
E12  
D14  
3
-
C9  
B12  
4
-
F12  
B14  
4
182  
-
C12  
5
178  
-
A14  
5
-
C10  
A11  
6
-
-
-
6
-
-
-
7
-
-
-
-
7
-
-
-
-
8
-
-
-
-
8
-
-
-
-
9
-
-
-
-
9
-
-
-
-
-
10  
11  
12  
13  
14  
15  
16  
1
-
-
-
-
-
10  
11  
12  
13  
14  
15  
16  
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
D13  
C13  
B13  
A13  
F22  
G19  
G20  
G21  
-
4
4
4
4
4
4
4
4
-
-
-
A9  
-
B11  
C11  
D11  
A10  
H22  
J19  
J20  
J21  
-
4
4
4
4
4
4
4
4
-
-
-
-
-
-
-
-
149  
148  
147  
146  
-
-
-
D9  
G15  
H13  
G16  
H14  
-
G13  
140  
2
F15  
2
139  
3
G14  
3
138  
4
E16  
4
137  
5
-
5
-
6
-
-
-
-
6
-
-
-
-
7
-
-
-
-
7
-
-
-
-
8
-
-
-
-
8
-
-
-
-
9
-
-
-
-
9
-
-
-
-
10  
11  
12  
13  
14  
15  
16  
-
-
-
-
-
10  
11  
12  
13  
14  
15  
16  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
145  
144  
143  
142  
H12  
F16  
H16  
-
G22  
H19  
H20  
H21  
4
4
4
4
136  
135  
134  
-
H15  
J12  
K12  
J16  
J22  
K19  
K20  
K21  
4
4
4
4
DS096 (v2.4) October 1, 2004  
Preliminary Product Specification  
www.xilinx.com  
1-800-255-7778  
17  
R
XC2C512 CoolRunner-II CPLD  
Pin Descriptions (Continued)  
Pin Descriptions (Continued)  
Function  
Block  
Macro-  
cell  
I/O  
Bank  
Function  
Block  
Macro-  
cell  
I/O  
Bank  
PQ208 FT256  
FG324  
PQ208 FT256  
FG324  
25  
25  
25  
25  
25  
25  
25  
25  
25  
25  
25  
25  
25  
25  
25  
25  
26  
26  
26  
26  
26  
26  
26  
26  
26  
26  
26  
26  
26  
26  
26  
26  
1
2
110  
R16  
W22  
3
3
3
3
-
27  
27  
27  
27  
27  
27  
27  
27  
27  
27  
27  
27  
27  
27  
27  
27  
28  
28  
28  
28  
28  
28  
28  
28  
28  
28  
28  
28  
28  
28  
28  
28  
1
2
118  
L15  
T19  
3
3
3
3
-
111  
N15  
V20  
-
L13  
T20  
3
112  
M15  
V21  
3
119  
M12  
T21  
4
113  
M13  
U19  
4
120  
M16  
T22  
5
-
-
-
5
-
-
-
6
-
-
-
-
6
-
-
-
-
7
-
-
-
-
7
-
-
-
-
8
-
-
-
-
-
8
-
-
-
-
9
-
-
-
-
9
-
-
-
-
10  
11  
12  
13  
14  
15  
16  
1
-
-
-
-
10  
11  
12  
13  
14  
15  
16  
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
114  
115  
116  
117  
109  
108  
107  
106  
-
P16  
N16  
L14  
M14  
N14  
T16  
R15  
P15  
P14  
-
V22  
U20  
U21  
U22  
Y22  
W21  
W20  
Y21  
Y20  
-
3
3
3
3
3
3
3
3
3
-
-
K14  
R19  
R20  
R21  
R22  
W19  
AA20  
Y18  
AA19  
W17  
-
3
3
3
3
3
3
3
3
3
-
-
-
121  
-
-
99  
97  
95  
-
-
T15  
2
2
R12  
3
3
T14  
4
4
N11  
5
5
-
P11  
6
-
6
-
-
7
-
-
-
-
7
-
-
-
-
8
-
-
-
-
8
-
-
-
-
9
-
-
-
-
9
-
-
-
-
10  
11  
12  
13  
14  
15  
16  
-
-
-
-
10  
11  
12  
13  
14  
15  
16  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
103  
102  
101  
100  
P13  
R13  
N13  
R14  
AA22  
AB22  
AA21  
AB21  
3
3
3
3
-
M11  
T13  
N10  
-
Y17  
AA18  
AB18  
AA17  
3
3
3
3
-
-
-
18  
www.xilinx.com  
1-800-255-7778  
DS096 (v2.4) October 1, 2004  
Preliminary Product Specification  
R
XC2C512 CoolRunner-II CPLD  
Pin Descriptions (Continued)  
Pin Descriptions (Continued)  
Function  
Block  
Macro-  
cell  
I/O  
Bank  
Function  
Block  
Macro-  
cell  
I/O  
Bank  
PQ208 FT256  
FG324  
PQ208 FT256  
FG324  
29  
29  
29  
29  
29  
29  
29  
29  
29  
29  
29  
29  
29  
29  
29  
29  
30  
30  
30  
30  
30  
30  
30  
30  
30  
30  
30  
30  
30  
30  
30  
30  
1
2
-
L16  
P19  
3
3
3
3
-
31  
31  
31  
31  
31  
31  
31  
31  
31  
31  
31  
31  
31  
31  
31  
31  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
1
2
126  
K16  
M19  
3
3
3
3
-
-
-
P20  
-
-
M20  
3
122  
-
P21  
3
127  
-
M21  
4
123  
-
P22  
4
128  
J14  
L22  
5
-
-
-
5
-
-
-
6
-
-
-
-
6
-
-
-
-
-
7
-
-
-
-
7
-
-
-
8
-
-
-
-
8
-
-
-
-
9
-
-
-
-
9
-
-
-
-
10  
11  
12  
13  
14  
15  
16  
1
-
-
-
-
-
10  
11  
12  
13  
14  
15  
16  
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
125  
-
-
K15  
L12  
-
N19  
N21  
N22  
M22  
AB17  
W16  
Y16  
AA16  
AB16  
-
3
3
3
3
3
3
3
3
3
-
-
-
L21  
L20  
L19  
K22  
W14  
Y14  
AA14  
AB14  
W13  
-
3
3
3
3
3
3
3
3
3
-
-
J15  
-
-
-
131  
J13  
P9  
N9  
T9  
M8  
T8  
-
-
-
85  
84  
-
2
91  
90  
89  
-
T12  
P10  
T11  
R10  
-
2
3
3
4
4
83  
-
5
5
6
-
6
-
7
-
-
-
-
7
-
-
-
-
8
-
-
-
-
8
-
-
-
-
9
-
-
-
-
9
-
-
-
-
10  
11  
12  
13  
14  
15  
16  
-
-
-
-
10  
11  
12  
13  
14  
15  
16  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
88  
87  
-
M10  
T10  
M9  
R9  
W15  
Y15  
AA15  
AB15  
3
3
3
3
82  
80  
-
P8  
R8  
T7  
N8  
Y13  
AA13  
AB13  
W12  
3
3
3
3
86  
-
Notes:  
1. GTS = global output enable, GSR = global reset/set, GCK =  
global clock, CDRST = clock divide reset, DGE = DataGATE  
enable.  
DS096 (v2.4) October 1, 2004  
Preliminary Product Specification  
www.xilinx.com  
1-800-255-7778  
19  
R
XC2C512 CoolRunner-II CPLD  
XC2C512 JTAG, Power/Ground, No Connect Pins and Total User I/O  
Pin Type  
PQ208  
FT256  
P12  
FG324  
Y19  
TCK  
TDI  
98  
94  
176  
R11  
AB19  
TDO  
TMS  
A10  
C14  
96  
N12  
AB20  
VAUX (JTAG supply voltage)  
11  
F4  
F1  
Power internal (VCC  
)
1, 53, 124  
33,59,79  
P3, K13, D12, D5  
J6, K6, L7, L8  
F7, F8, G6, H6  
J11, K11, L9, L10  
F9, F10, H11  
F6, F11, G7, G8, G9, G10,  
E3, AA3, N20, A20, D4  
M9, N9, P10, P11  
J10,J11, K9, L9  
M14, N14, P12, P13  
J12, J13, K14, L14  
Power Bank 1 I/O (VCCIO1  
Power Bank 2 I/O (VCCIO2  
Power Bank 3 I/O (VCCIO3  
Power Bank 4 I/O (VCCIO4  
Ground  
)
)
)
)
26, 204  
92, 105, 132  
133, 157, 172, 181  
13, 24, 42, 52, 68, 81,  
D5, D18, E4, E19, J9, J14, K10,  
K11, K12, K13, L10, L11, L12,  
93, 104, 129, 130, 141, H7, H8, H9, H10, J7, J8, J9,  
156, 177, 190, 207  
J10, K7, K8, K9, K10, L6, L11 L13, M10, M11, M12, M13, N10,  
N11, N12, N13, P9, P14, V4,  
V19, W5, W18  
No connects  
-
-
-
Total user I/O (includes dual  
function pins)  
173  
212  
270  
Device Part Marking  
R
Device Type  
XC2Cxxx  
This line not  
related to device  
part number  
Package  
Speed  
TQ144  
7C  
Operating Range  
Figure 5: Sample Package with Part Marking  
20  
www.xilinx.com  
DS096 (v2.4) October 1, 2004  
1-800-255-7778  
Preliminary Product Specification  
R
XC2C512 CoolRunner-II CPLD  
Ordering Information  
Commercial  
(C)  
Pin/Ball  
Spacing (C/Watt) (C/Watt)  
θJA  
θJC  
Package Body  
Dimensions  
Industrial  
(I)(1)  
Part Number  
Package Type  
I/O  
XC2C512-6PQ208C(2)  
0.5mm  
0.5mm  
0.5mm  
35.1  
35.1  
35.1  
7.2  
7.2  
7.2  
Plastic Quad Flat  
Pack  
28mm x 28mm 173  
28mm x 28mm 173  
28mm x 28mm 173  
C
C
C
XC2C512-7PQ208C  
XC2C512-10PQ208C  
Plastic Quad Flat  
Pack  
Plastic Quad Flat  
Pack  
XC2C512-6FT256C(2)  
XC2C512-7FT256C  
XC2C512-10FT256C  
XC2C512-6FG324C(2)  
XC2C512-7FG324C  
XC2C512-10FG324C  
1.0mm  
1.0mm  
1.0mm  
1.0mm  
1.0mm  
1.0mm  
32.2  
32.2  
32.2  
39.1  
39.1  
39.1  
35.1  
4.9  
4.9  
4.9  
5.0  
5.0  
5.0  
7.2  
Fine Pitch Thin BGA 17mm x 17mm 212  
Fine Pitch Thin BGA 17mm x 17mm 212  
Fine Pitch Thin BGA 17mm x 17mm 212  
C
C
C
C
C
C
C
Fine Pitch BGA  
Fine Pitch BGA  
Fine Pitch BGA  
23mm x 23mm 270  
23mm x 23mm 270  
23mm x 23mm 270  
28mm x 28mm 173  
XC2C512-6PQG208C(2) 0.5mm  
Plastic Quad Flat  
Pack; Pb-free  
XC2C512-7PQG208C  
XC2C512-10PQG208C  
XC2C512-6FTG256C(2)  
XC2C512-7FTG256C  
XC2C512-10FTG256C  
0.5mm  
0.5mm  
1.0mm  
1.0mm  
1.0mm  
35.1  
35.1  
32.2  
32.2  
32.2  
39.1  
39.1  
39.1  
35.1  
7.2  
7.2  
4.9  
4.9  
4.9  
5.0  
5.0  
5.0  
7.2  
Plastic Quad Flat  
Pack; Pb-free  
28mm x 28mm 173  
28mm x 28mm 173  
C
C
C
C
C
C
C
C
I
Plastic Quad Flat  
Pack; Pb-free  
Fine Pitch Thin BGA; 17mm x 17mm 212  
Pb-free  
Fine Pitch Thin BGA; 17mm x 17mm 212  
Pb-free  
Fine Pitch Thin BGA; 17mm x 17mm 212  
Pb-free  
XC2C512-6FGG324C(2) 1.0mm  
Fine Pitch BGA;  
Pb-free  
23mm x 23mm 270  
23mm x 23mm 270  
23mm x 23mm 270  
28mm x 28mm 173  
XC2C512-7FGG324C  
XC2C512-10FGG324C  
XC2C512-10PQ208I  
1.0mm  
1.0mm  
0.5mm  
Fine Pitch BGA;  
Pb-free  
Fine Pitch BGA;  
Pb-free  
Plastic Quad Flat  
Pack  
XC2C512-10FT256I  
XC2C512-10FG324I  
XC2C512-10PQG208I  
1.0mm  
1.0mm  
0.5mm  
32.2  
39.1  
35.1  
4.9  
5.0  
7.2  
Fine Pitch Thin BGA 17mm x 17mm 212  
I
I
I
Fine Pitch BGA  
23mm x 23mm 270  
28mm x 28mm 173  
Plastic Quad Flat  
Pack; Pb-free  
DS096 (v2.4) October 1, 2004  
Preliminary Product Specification  
www.xilinx.com  
1-800-255-7778  
21  
R
XC2C512 CoolRunner-II CPLD  
Commercial  
(C)  
Pin/Ball  
Spacing (C/Watt) (C/Watt)  
θJA  
θJC  
4.9  
5.0  
Package Body  
Dimensions  
Industrial  
(I)(1)  
Part Number  
Package Type  
I/O  
XC2C512-10FTG256I  
1.0mm  
32.2  
39.1  
Fine Pitch Thin BGA; 17mm x 17mm 212  
Pb-free  
I
XC2C512-10FGG324I  
1.0mm  
Fine Pitch BGA;  
Pb-free  
23mm x 23mm 270  
I
Notes:  
1. C = Commercial (TA = 0°C to +70° C); I = Industrial (TA = –40°C to +85°C).  
2. Inquire with your local sales representative for availability of this part.  
Pb-  
XC2C128 -4 TQ  
G
144  
C
Free Example:  
Standard Example: XC2C128 -4 TQ 144  
C
Device  
Device  
Speed Grade  
Package Type  
Speed Grade  
Package Type  
Number of Pins  
Temperature Range  
-Free  
Pb  
Number of Pins  
Temperature Range  
22  
www.xilinx.com  
1-800-255-7778  
DS096 (v2.4) October 1, 2004  
Preliminary Product Specification  
R
XC2C512 CoolRunner-II CPLD  
VCC  
I/O  
I/O(1)  
I/O  
I/O(1)  
I/O  
I/O(1)  
I/O  
I/O(1)  
I/O  
VAUX  
I/O  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
1
2
3
4
5
6
7
8
9
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
I/O  
I/O  
156  
155  
154  
153  
152  
151  
150  
149  
148  
147  
146  
145  
144  
143  
142  
141  
140  
139  
138  
137  
136  
135  
134  
133  
132  
131  
130  
129  
128  
127  
126  
125  
124  
123  
122  
121  
120  
119  
118  
117  
116  
115  
114  
113  
112  
111  
110  
109  
108  
107  
106  
105  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
I/O  
VCCIO2  
I/O  
VCCIO4  
VCCIO3  
I/O  
GND  
GND  
I/O  
I/O  
I/O  
I/O  
VCC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
PQ208  
Top View  
I/O  
VCCIO1  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
I/O  
I/O(2)  
I/O  
I/O(2)  
I/O  
I/O  
I/O  
I/O  
I/O(4)  
GND  
I/O  
VCCIO3  
(1) - Global Output Enable  
(2) - Global Clock  
(3) - Global Set/Reset  
(4) - Clock Divide Reset  
(5) - DataGATE Enable  
Figure 6: PQ208 Plastic Quad Flat Pack  
DS096 (v2.4) October 1, 2004  
www.xilinx.com  
23  
Preliminary Product Specification  
1-800-255-7778  
R
XC2C512 CoolRunner-II CPLD  
TDO  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
A
B
C
D
E
F
I/O  
I/O(3)  
I/O  
I/O  
I/O(1)  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VCC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VCC  
I/O(1)  
I/O  
I/O(1)  
I/O(1)  
I/O  
I/O  
I/O  
I/O  
I/O  
VCCIO4  
GND  
GND  
GND  
GND  
VCCIO3  
I/O  
I/O  
VCCIO4  
VCCIO2  
VAUX  
I/O  
GND  
GND  
VCCIO2  
GND  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
GND  
GND  
GND  
VCCIO1  
I/O  
GND VCCIO2  
GND VCCIO2  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
G
H
J
VCCIO4  
VCCIO3  
VCCIO3  
GND  
GND  
I/O  
GND  
GND  
VCCIO1  
I/O  
VCCIO1  
VCCIO1  
GND  
GND  
VCC  
I/O  
K
L
VCCIO3  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O(2)  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
TMS  
TCK  
I/O  
I/O  
I/O  
I/O  
TDI  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O(2)  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
M
N
P
R
T
I/O  
I/O  
I/O  
I/O(4)  
I/O  
I/O  
I/O  
I/O  
I/O(2)  
I/O  
VCC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O(5)  
I/O  
I/O  
I/O  
I/O  
FT256 Bottom View  
(1) - Global Output Enable  
(2) - Global Clock  
(3) - Global Set/Reset  
(4) - Clock Divide Reset  
(5) - DataGATE Enable  
Figure 7: FT256 Fine Pitch Thin BGA  
24  
www.xilinx.com  
1-800-255-7778  
DS096 (v2.4) October 1, 2004  
Preliminary Product Specification  
R
XC2C512 CoolRunner-II CPLD  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VCC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O(3)  
I/O  
A
B
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O(1)  
I/O(1)  
I/O  
I/O  
TDO  
C
D
E
VCC  
I/O  
I/O  
GND  
I/O(1)  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
I/O  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
I/O  
I/O  
I/O  
VCC  
I/O  
I/O(1)  
VAUX  
F
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
G
H
J
VCCIO2  
GND VCCIO4  
GND  
GND  
I/O  
I/O  
I/O  
I/O  
VCCIO4  
GND  
VCCIO2  
GND  
I/O  
I/O  
I/O  
I/O  
GND  
GND  
VCCIO2  
VCCIO2  
K
VCCIO4  
GND  
GND  
GND  
GND  
GND  
I/O  
I/O  
I/O  
I/O  
VCCIO4  
VCCIO3  
VCCIO3  
L
GND  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VCC  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
GND  
GND  
GND  
VCCIO1  
VCCIO1  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
M
N
P
I/O  
I/O  
I/O  
I/O  
VCCIO1 VCCIO1  
I/O  
I/O  
I/O  
I/O  
GND VCCIO3  
VCCIO3  
I/O  
R
T
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
U
V
GND  
I/O  
I/O  
I/O  
I/O(2)  
I/O  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
W
Y
I/O  
I/O  
I/O  
I/O  
I/O  
I/O(2)  
I/O  
TCK  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O(5)  
I/O  
VCC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
AA  
AB  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O(2)  
I/O(4)  
TMS  
TDI  
(1) - Global Output Enable  
(2) - Global Clock  
FG324 Bottom View  
(3) - Global Set/Reset  
(4) - Clock Divide Reset  
(5) - DataGATE Enable  
Figure 8: FG324 Fine Pitch BGA  
Additional Information  
CoolRunner-II Datasheets and Application Notes  
Device Packages  
DS096 (v2.4) October 1, 2004  
Preliminary Product Specification  
www.xilinx.com  
1-800-255-7778  
25  
R
XC2C512 CoolRunner-II CPLD  
Revision History  
The following table shows the revision history for this document.  
Date  
Version  
1.0  
Revision  
7/19/02  
3/15/03  
11/25/03  
1/26/04  
8/03/04  
10/01/04  
Initial Xilinx release.  
Added characterization data.  
Fixed two typos.  
2.0  
2.1  
2.2  
Updated Tsol; added links to Datasheets and Application Notes.  
Pb-free documentation  
2.3  
2.4  
Add Asynchronous Preset/Reset Pulse Width specification to AC Electrical Characteristics.  
26  
www.xilinx.com  
DS096 (v2.4) October 1, 2004  
1-800-255-7778  
Preliminary Product Specification  

相关型号：

XC2C512-7FG324C

 暂无描述
XILINX

XC2C512-7FGG324C

 暂无描述
XILINX

XC2C512-7FT256I

 Flash PLD, 7.5ns, 512-Cell, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, PLASTIC, FTBGA-256
XILINX

XC2C512-7FTG256C

 Flash PLD, 7.5ns, 512-Cell, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, LEAD FREE, PLASTIC, FTBGA-256
XILINX

XC2C64

 This lends power savings to High-end Communication equipment and speed to battery operated devices.
XILINX

XC2C64-4CP56C

 This lends power savings to High-end Communication equipment and speed to battery operated devices.
XILINX

XC2C64-4PC44C

 This lends power savings to High-end Communication equipment and speed to battery operated devices.
XILINX

XC2C64-4VQ100C

 This lends power savings to High-end Communication equipment and speed to battery operated devices.
XILINX

XC2C64-4VQ44C

 This lends power savings to High-end Communication equipment and speed to battery operated devices.
XILINX

XC2C64-5CP56C

 This lends power savings to High-end Communication equipment and speed to battery operated devices.
XILINX

XC2C64-5CP56I

 This lends power savings to High-end Communication equipment and speed to battery operated devices.
XILINX

XC2C64-5CPG56C

 Flash PLD, 5ns, 64-Cell, CMOS, PBGA56, 6 X 6 MM, 0.50 MM PITCH, CSP-56
XILINX
©2020 ICPDF网 联系我们和版权申明