XC2S100-5PQ208Q [XILINX]
Field Programmable Gate Array, 600 CLBs, 100000 Gates, 263MHz, 2700-Cell, CMOS, PQFP208, PLASTIC, QFP-208;
| 型号： | XC2S100-5PQ208Q |
| 厂家： | 
XILINX, INC |
| 描述： | Field Programmable Gate Array, 600 CLBs, 100000 Gates, 263MHz, 2700-Cell, CMOS, PQFP208, PLASTIC, QFP-208 栅 |
| 文件： | 总4页 (文件大小：100K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
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Spartan-II 2.5V FPGA
R
Automotive IQ Product Family:
Introduction and Ordering
Product Specification
0
0
DS105-1 (v2.0) August 9, 2013
Introduction
The Spartan™-II 2.5V Field-Programmable Gate Array
(FPGA) Automotive IQ product family gives users high per-
formance, abundant logic resources, and a rich feature set.
The six-member family offers densities ranging from 15,000
to 200,000 system gates, as shown in Table 1.
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System level features
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SelectRAM+™ hierarchical memory:
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·
·
16 bits/LUT distributed RAM
Configurable 4K-bit block RAM
Fast interfaces to external RAM
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Fully PCI compliant
Spartan-II devices deliver more gates, I/Os, and features
per Dollar/Euro than other FPGAs by combining advanced
0.18 μm process technology with a streamlined
Virtex™-based architecture. Features include block RAM
(to 56K bits), distributed RAM (to 75,264 bits), 16 selectable
I/O standards, and four DLLs. Fast, predictable interconnect
means that successive design iterations continue to meet
timing requirements.
Low-power segmented routing architecture
Full readback ability for verification/observability
Dedicated carry logic for high-speed arithmetic
Dedicated multiplier support
Cascade chain for wide-input functions
Abundant registers/latches with enable, set, reset
Four dedicated DLLs for advanced clock control
Four primary low-skew global clock distribution nets
IEEE 1149.1 compatible boundary scan logic
The Spartan-II family is a superior alternative to mask-pro-
grammed ASICs. The FPGA avoids the initial cost, lengthy
development cycles, and inherent risk of conventional
ASICs. Also, FPGA programmability permits design
upgrades in the field with no hardware replacement neces-
sary (impossible with ASICs).
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Versatile I/O and packaging
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Family footprint compatibility in common packages
16 high-performance interface standards
Zero hold time simplifies system timing
Fully supported by powerful Xilinx development system
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Foundation™ ISE Series: Fully integrated software
Alliance Series™: For use with third-party tools
Fully automatic mapping, placement, and routing
Features
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Guaranteed to meet full electrical specifications over
T = –40°C to +125°C
J
•
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Refer to Spartan-II 2.5V FPGA Detailed Functional
Description (DS001-2) for device functional description
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Second generation ASIC replacement technology
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Densities as high as 5,292 logic cells with up to
200,000 system gates
Other than the DC parameters listed, all other DC
specifications are the same as referenced in the
Spartan-II 2.5V FPGA DC and Switching
Characteristics (DS001-3) data sheet
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Streamlined features based on Virtex architecture
Unlimited reprogrammability
•
Refer to Spartan-II 2.5V FPGA Pinout Tables
(DS001-4) for all pin descriptions
Table 1: Spartan-II FPGA Family Members
CLB
Array
(R x C)
Maximum
Total
Total
Logic
Cells
System Gates
(Logic and RAM)
Total
Available
Distributed RAM Block RAM
(1)
Device
XC2S15
XC2S30
XC2S50
XC2S100
XC2S150
XC2S200
CLBs User I/O
Bits
Bits
16K
24K
32K
40K
48K
56K
432
15,000
30,000
8 x 12
12 x 18
16 x 24
20 x 30
24 x 36
28 x 42
96
216
384
600
864
1,176
86
6,144
972
132
176
176
176
284
13,824
24,576
38,400
55,296
75,264
1,728
2,700
3,888
5,292
50,000
100,000
150,000
200,000
Notes:
1. All user I/O counts do not include the four global clock/user input pins. See details in Table 3, page 3.
© 2002–2013 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS105-1 (v2.0) August 9, 2013
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Product Specification
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Spartan-II 2.5V FPGA Automotive IQ Product Family: Introduction and Ordering Information
DC Specifications
Absolute Maximum Ratings
(1)
Symbol
Description
Min
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–65
-
Max
3.0
4.0
3.6
5.5
Units
V
(2)
V
Supply voltage relative to GND
CCINT
(2)
V
Supply voltage relative to GND
V
CCO
V
Input reference voltage
V
REF
(3)
(4)
V
Input voltage relative to GND
5V tolerant I/O
V
IN
(5)
No 5V tolerance
V
V
+ 0.5
V
CCO
(4)
V
Voltage applied to 3-state output
5V tolerant I/O
5.5
+ 0.5
V
TS
(5)
No 5V tolerance
V
CCO
T
Storage temperature (ambient)
Junction temperature
+150
+135
°C
°C
STG
T
J
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
2. Power supplies may turn on in any order.
3.
VIN should not exceed VCCO by more than 3.6V over extended periods of time (e.g., longer than a day).
4. Spartan-II I/Os are 5V Tolerant whenever the LVTTL, LVCMOS2, or PCI33_5 signal standard has been selected. With 5V Tolerant
I/Os selected, the Maximum DC overshoot must be limited to either +5.5V or 10 mA, and undershoot must be limited to either –0.5V
or 10 mA, whichever is easier to achieve. The Maximum AC conditions are as follows: The device pins may undershoot to –2.0V or
overshoot to +7.0V, provided this over/undershoot lasts no more than 11 ns with a forcing current no greater than 100 mA.
5. Without 5V Tolerant I/Os selected, the Maximum DC overshoot must be limited to either VCCO + 0.5V or 10 mA, and undershoot must
be limited to –0.5V or 10 mA, whichever is easier to achieve. The Maximum AC conditions are as follows: The device pins may
undershoot to –2.0V or overshoot to VCCO + 2.0V, provided this over/undershoot lasts no more than 11 ns with a forcing current no
greater than 100 mA.
6. For soldering guidelines, see the packaging Information on the Xilinx website.
Recommended Operating Conditions
Symbol
Description
Junction temperature
Min
–40
Max
125
Units
°C
V
T
J
(1,2)
(2,3)
V
Supply voltage relative to GND
Supply voltage relative to GND
2.5 – 5%
1.4
2.5 + 5%
3.6
CCINT
V
V
CCO
(4)
T
Input signal transition time
-
250
ns
IN
Notes:
1. Functional operation is guaranteed down to a minimum VCCINT of 2.25V (Nominal VCCINT – 10%). For every 50 mV reduction in
VCCINT below 2.375V (nominal VCCINT – 5%), all delay parameters increase by 3%.
2. Supply voltages may be applied in any order desired.
3. Minimum and maximum values for VCCO vary according to the I/O standard selected.
4. Input and output measurement threshold is ~50% of VCCO
.
DC Characteristics Over Operating Conditions
Symbol
Description
supply current
CCINT
Min
Max
60
Units
mA
mA
mA
mA
mA
mA
(1)
I
Quiescent V
XC2S15
XC2S30
XC2S50
XC2S100
XC2S150
XC2S200
-
-
-
-
-
-
CCINTQ
115
125
140
165
200
Notes:
1. With no output current loads, no active input pull-up resistors, all I/O pins 3-stated and floating.
2
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Product Specification
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Spartan-II 2.5V FPGA Automotive IQ Product Family: Introduction and Ordering Information
Spartan-II Product Availability
Table 2 shows the package and speed grades available for
Spartan-II family devices. Table 3 shows the maximum user
I/Os available on the device and the number of user I/Os
available for each device/package combination. The four
global clock pins are usable as additional user I/Os when
not used as a global clock pin. These pins are not included
in user I/O counts.
Table 2: Spartan-II Package and Speed Grade Availability
Pins
100
208
256
456
144
Fine Pitch
BGA
Fine Pitch
BGA
Type
Code
-5
Plastic VQFP
Plastic PQFP
Plastic TQFP
Device
XC2S15
XC2S30
XC2S50
XC2S100
XC2S150
XC2S200
VQ100
PQ208
FG256
FG456
TQ144
Q
-
-
-
-
-
-
Q
Q
Q
Q
-
-5
Q
Q
Q
Q
Q
-5
-
Q
Q
Q
-
-
-5
-
-
-5
-
-
-5
-
Q
-
Notes:
1. Q= Automotive IQ, TJ = –40°C to +125°C.
(1)
Table 3: Spartan-II User I/O Chart
Available User I/O According to Package Type
Maximum
Device
XC2S15
XC2S30
XC2S50
XC2S100
XC2S150
XC2S200
User I/O
VQ100
TQ144
PQ208
-
FG256
FG456
86
60
-
86
92
92
92
-
-
-
132
132
140
140
140
140
-
-
176
-
176
176
176
-
-
176
-
-
-
176
-
284
-
-
284
Notes:
1. All user I/O counts do not include the four global clock/user input pins.
DS105-1 (v2.0) August 9, 2013
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3
Product Specification
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Spartan-II 2.5V FPGA Automotive IQ Product Family: Introduction and Ordering Information
Ordering Information
Example:
XC2S50 -5 PQ 208 Q
Device Type
Temperature Range
Number of Pins
Package Type
Speed Grade
Device Ordering Options
Device
XC2S15
XC2S30
XC2S50
XC2S100
XC2S150
XC2S200
Speed Grade
-5 Standard Performance
Number of Pins / Package Type
VQ100 100-pin Very Thin Plastic QFP
TQ144 144-pin Plastic Thin QFP
PQ208 208-pin Plastic QFP
Temperature Range (TJ)
Q = Automotive IQ –40°C to +125°C
FG256 256-ball Fine Pitch BGA
FG456 456-ball Fine Pitch BGA
Revision History
Version
No.
1.0
1.1
1.2
1.3
1.4
2.0
Date
Description
06/17/2002 Initial Xilinx release.
11/26/2002 Updated Max User I/O in Table 1 and Table 3 for XC2S100 and XC2S150: changed to 176.
02/14/2003 Added references to Spartan-II data sheet, added DC Characteristics Over Operating Conditions table.
05/21/2004 Added VQ100 to Table 2 and Table 3. Added VQ100 to Ordering Information.
10/18/2004 Added "Not to be used in new designs" watermark; moved to "Mature Products"
08/09/2013 This product is obsolete/discontinued per XCN11010.
PN 011311
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DS105-1 (v2.0) August 9, 2013
Product Specification
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