XC2S100E-7TQG144C [XILINX]
Spartan-IIE FPGA; 的Spartan- IIE FPGA
| 型号： | XC2S100E-7TQG144C |
| 厂家： | 
XILINX, INC |
| 描述： | Spartan-IIE FPGA |
| 文件： | 总108页 (文件大小：5063K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Spartan-IIE FPGA Family
Data Sheet
DS077 June 18, 2008
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Product Specification
This document includes all four modules of the Spartan®-IIE FPGA data sheet.
Module 1:
Introduction and Ordering Information
Module 3:
DC and Switching Characteristics
DS077-1 (v2.3) June 18, 2008
DS077-3 (v2.3) June 18, 2008
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Introduction
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DC Specifications
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Absolute Maximum Ratings
Recommended Operating Conditions
DC Characteristics
Power-On Requirements
DC Input and Output Levels
Features
General Overview
Product Availability
User I/O Chart
Ordering Information
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Switching Characteristics
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Pin-to-Pin Parameters
Module 2:
IOB Switching Characteristics
Clock Distribution Characteristics
DLL Timing Parameters
CLB Switching Characteristics
Block RAM Switching Characteristics
TBUF Switching Characteristics
JTAG Switching Characteristics
Configuration Switching Characteristics
Functional Description
DS077-2 (v2.3) June 18, 2008
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Architectural Description
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Spartan-IIE Array
Input/Output Block
Configurable Logic Block
Block RAM
Clock Distribution: Delay-Locked Loop
Boundary Scan
Module 4:
Pinout Tables
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Development System
Configuration
DS077-4 (2.3) June 18, 2008
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Pin Definitions
Pinout Tables
IMPORTANT NOTE: The Spartan-IIE FPGA data sheet is in four modules. Each module has its own Revision History at the
end. Use the PDF "Bookmarks" for easy navigation in this volume.
© 2003-2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
DS077 June 18, 2008
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Product Specification
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2
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DS077 June 18, 2008
Product Specification
Spartan-IIE FPGA Family:
Introduction and Ordering
Information
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DS077-1 (v2.3) June 18, 2008
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Product Specification
·
Fast interfaces to external RAM
Introduction
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Fully 3.3V PCI compliant to 64 bits at 66 MHz and
CardBus compliant
Low-power segmented routing architecture
Dedicated carry logic for high-speed arithmetic
Efficient multiplier support
Cascade chain for wide-input functions
Abundant registers/latches with enable, set, reset
Four dedicated DLLs for advanced clock control
The Spartan®-IIE Field-Programmable Gate Array family
gives users high performance, abundant logic resources,
and a rich feature set, all at an exceptionally low price. The
seven-member family offers densities ranging from 50,000
to 600,000 system gates, as shown in Table 1. System per-
formance is supported beyond 200 MHz.
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Features include block RAM (to 288K bits), distributed RAM
(to 221,184 bits), 19 selectable I/O standards, and four
DLLs (Delay-Locked Loops). Fast, predictable interconnect
means that successive design iterations continue to meet
timing requirements.
·
·
Eliminate clock distribution delay
Multiply, divide, or phase shift
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Four primary low-skew global clock distribution nets
IEEE 1149.1 compatible boundary scan logic
The Spartan-IIE family is a superior alternative to
mask-programmed ASICs. The FPGA avoids the initial cost,
lengthy development cycles, and inherent risk of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary (impossible with ASICs).
•
Versatile I/O and packaging
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-
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Pb-free package options
Low-cost packages available in all densities
Family footprint compatibility in common packages
19 high-performance interface standards
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Up to 205 differential I/O pairs that can be input,
output, or bidirectional
Hot swap I/O (CompactPCI friendly)
LVTTL, LVCMOS, HSTL, SSTL, AGP, CTT, GTL
LVDS and LVPECL differential I/O
Features
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-
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Second generation ASIC replacement technology
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Densities as high as 15,552 logic cells with up to
600,000 system gates
Streamlined features based on Virtex®-E FPGA
architecture
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Core logic powered at 1.8V and I/Os powered at 1.5V,
2.5V, or 3.3V
Fully supported by powerful Xilinx® ISE® development
system
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Unlimited in-system reprogrammability
Very low cost
Cost-effective 0.15 micron technology
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-
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Fully automatic mapping, placement, and routing
Integrated with design entry and verification tools
Extensive IP library including DSP functions and
soft processors
•
System level features
SelectRAM™ hierarchical memory:
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16 bits/LUT distributed RAM
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Configurable 4K-bit true dual-port block RAM
Table 1: Spartan-IIE FPGA Family Members
Typical
System Gate Range
(Logic and RAM)
CLB
Array
(R x C)
Maximum
Available
User I/O(1)
Maximum
Differential
I/O Pairs
Logic
Cells
Total
CLBs
Distributed BlockRAM
Device
RAM Bits
Bits
XC2S50E
XC2S100E
XC2S150E
XC2S200E
XC2S300E
XC2S400E
XC2S600E
1,728
2,700
3,888
5,292
6,912
10,800
15,552
23,000 - 50,000
37,000 - 100,000
52,000 - 150,000
71,000 - 200,000
93,000 - 300,000
145,000 - 400,000
210,000 - 600,000
16 x 24
20 x 30
24 x 36
28 x 42
32 x 48
40 x 60
48 x 72
384
600
182
202
265
289
329
410
514
83
24,576
32K
86
38,400
40K
864
114
120
120
172
205
55,296
48K
1,176
1,536
2,400
3,456
75,264
56K
98,304
64K
153,600
221,184
160K
288K
Notes:
1. User I/O counts include the four global clock/user input pins. See details in Table 2, page 5
© 2003-2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
DS077-1 (v2.3) June 18, 2008
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Product Specification
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Spartan-IIE FPGA Family: Introduction and Ordering Information
Spartan-IIE FPGAs achieve high-performance, low-cost
operation through advanced architecture and semiconduc-
tor technology. Spartan-IIE devices provide system clock
rates beyond 200 MHz. In addition to the conventional ben-
efits of high-volume programmable logic solutions, Spar-
tan-IIE FPGAs also offer on-chip synchronous single-port
and dual-port RAM (block and distributed form), DLL clock
drivers, programmable set and reset on all flip-flops, fast
carry logic, and many other features.
General Overview
The Spartan-IIE family of FPGAs have a regular, flexible,
programmable architecture of Configurable Logic Blocks
(CLBs), surrounded by a perimeter of programmable
Input/Output Blocks (IOBs). There are four Delay-Locked
Loops (DLLs), one at each corner of the die. Two columns
of block RAM lie on opposite sides of the die, between the
CLBs and the IOB columns. The XC2S400E has four col-
umns and the XC2S600E has six columns of block RAM.
These functional elements are interconnected by a powerful
hierarchy of versatile routing channels (see Figure 1).
Spartan-IIE Family Compared to Spartan-II
Family
Spartan-IIE FPGAs are customized by loading configura-
tion data into internal static memory cells. Unlimited repro-
gramming cycles are possible with this approach. Stored
values in these cells determine logic functions and intercon-
nections implemented in the FPGA. Configuration data can
be read from an external serial PROM (master serial mode),
or written into the FPGA in slave serial, slave parallel, or
Boundary Scan modes. Xilinx offers multiple types of
low-cost configuration solutions including the Platform
Flash in-system programmable configuration PROMs.
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•
•
•
Higher density and more I/O
Higher performance
Unique pinouts in cost-effective packages
Differential signaling
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LVDS, Bus LVDS, LVPECL
•
VCCINT = 1.8V
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Lower power
5V tolerance with external resistor
3V tolerance directly
Spartan-IIE FPGAs are typically used in high-volume appli-
cations where the versatility of a fast programmable solution
adds benefits. Spartan-IIE FPGAs are ideal for shortening
product development cycles while offering a cost-effective
solution for high volume production.
•
•
PCI, LVTTL, and LVCMOS2 input buffers powered by
CCO instead of VCCINT
V
Unique larger bitstream
DLL
DLL
CLBs
CLBs
CLBs
CLBs
DLL
DLL
I/O LOGIC
DS077_01_052102
Figure 1: Basic Spartan-IIE Family FPGA Block Diagram
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DS077-1 (v2.3) June 18, 2008
Product Specification
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Spartan-IIE FPGA Family: Introduction and Ordering Information
Spartan-IIE Product Availability
Table 2 shows the maximum user I/Os available on the device and the number of user I/Os available for each
device/package combination.
Table 2: Spartan-IIE FPGA User I/O Chart
Available User I/O According to Package Type
Maximum
User I/O
TQ144
TQG144
PQ208
PQG208
FT256
FTG256
FG456
FGG456
FG676
FGG676
Device
XC2S50E
XC2S100E
XC2S150E
XC2S200E
XC2S300E
XC2S400E
XC2S600E
182
202
265
289
329
410
514
102
146
146
146
146
146
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182
182
182
182
182
182
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-
-
102
202
265
289
329
329
329
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-
-
-
-
-
-
-
-
410
514
-
Notes:
1. User I/O counts include the four global clock/user input pins.
DS077-1 (v2.3) June 18, 2008
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Product Specification
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Spartan-IIE FPGA Family: Introduction and Ordering Information
Ordering Information
Spartan-IIE devices are available in both standard and Pb-free packaging options for all device/package combinations. The
Pb-free packages include a special "G" character in the ordering code.
Standard Packaging
Example: XC2S50E -6 PQ 208 C
Device Type
Speed Grade
Package Type
Temperature Range
Number of Pins
DS077-1_03a_072004
Pb-Free Packaging
Example: XC2S50E -6 PQ G 208 C
Device Type
Temperature Range
Number of Pins
Pb-free
Speed Grade
Package Type
DS077-1_03b_072004
Device Ordering Options
Device
Speed Grade
Package Type / Number of Pins
Temperature Range (TJ)(2)
XC2S50E
XC2S100E
XC2S150E
XC2S200E
XC2S300E
XC2S400E
XC2S600E
-6 Standard Performance
-7 Higher Performance(1)
TQ(G)144 144-pin Plastic Thin QFP
PQ(G)208 208-pin Plastic QFP
C = Commercial
I = Industrial
0°C to +85°C
–40°C to +100°C
FT(G)256 256-ball Fine Pitch BGA
FG(G)456 456-ball Fine Pitch BGA
FG(G)676 676-ball Fine Pitch BGA
Notes:
1. The -7 speed grade is exclusively available in the Commercial temperature range.
2. See www.xilinx.com for information on automotive temperature range devices.
Device Part Marking
Figure 2 is a top marking example for Spartan-IIE FPGAs in
the quad-flat packages. The markings for BGA packages
are nearly identical to those for the quad-flat packages,
except that the marking is rotated with respect to the ball A1
R
R
SPARTAN
Device Type
XC2S50E
PQ208xxx0425
xxxxxxxxx
6C
indicator.
Date Code
Package
The "7C" and "6I" Speed Grade/Temperature Range part
combinations may be dual marked as "7C/6I". Devices
Lot Code (numeric)
Speed
with the dual mark can be used as either -7C or -6I devices.
Operating Range
Devices with a single mark are only guaranteed for the
marked speed grade and temperature range.
Sample package with part marking
for XC2S50E-6PQ208C.
Figure 2: Spartan-IIE QFP Marking Example
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Product Specification
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Spartan-IIE FPGA Family: Introduction and Ordering Information
Revision History
Date
Version No.
Description
06/27/02
11/18/02
1.1
2.0
Updated -7 availability.
Added XC2S400E and XC2S600E. Corrected XC2S150E max I/O count and XC2S50E
differential I/O count and updated availability.
07/09/03
2.1
Noted hot-swap capability. Updated Table 2 to show that all products are available. Clarified
device part marking.
07/28/04
06/18/08
2.2
2.3
Added information on Pb-free packaging options.
Added dual mark information in Device Part Marking. Updated all modules for continuous
page, figure, and table numbering. Updated links. Synchronized all modules to v2.3.
DS077-1 (v2.3) June 18, 2008
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Product Specification
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Spartan-IIE FPGA Family: Introduction and Ordering Information
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DS077-1 (v2.3) June 18, 2008
Product Specification
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Spartan-IIE FPGA Family:
Functional Description
DS077-2 (v2.3) June 18, 2008
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Product Specification
As can be seen in Figure 3, the CLBs form the central logic
structure with easy access to all support and routing struc-
tures. The IOBs are located around all the logic and mem-
ory elements for easy and quick routing of signals on and off
the chip.
Architectural Description
Spartan-IIE FPGA Array
The Spartan®-IIE user-programmable gate array, shown in
Figure 3, is composed of five major configurable elements:
Values stored in static memory cells control all the config-
urable logic elements and interconnect resources. These
values load into the memory cells on power-up, and can
reload if necessary to change the function of the device.
•
IOBs provide the interface between the package pins
and the internal logic
•
CLBs provide the functional elements for constructing
most logic
Each of these elements will be discussed in detail in the fol-
lowing sections.
•
•
Dedicated block RAM memories of 4096 bits each
Clock DLLs for clock-distribution delay compensation
and clock domain control
•
Versatile multi-level interconnect structure
DLL
DLL
CLBs
CLBs
CLBs
CLBs
DLL
DLL
I/O LOGIC
DS077_01_052102
Figure 3: Basic Spartan-IIE Family FPGA Block Diagram
© 2003-2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
DS077-2 (v2.3) June 18, 2008
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Spartan-IIE FPGA Family: Functional Description
T
SR
V
CCO
D
Q
Package
Pin
TFF
CLK
TCE
SR
CK
EC
V
OE
CC
I/O
Programmable
Bias and
ESD Network
Package Pin
SR
O
D
Q
Programmable
Output Buffer
OFF
CK
EC
Internal
Reference
(1)
CC
OCE
V
Programmable
Delay
IQ
I
I/O, V
REF
SR
Package Pin
Programmable
Input Buffer
D
Q
IFF
CK
EC
To Next I/O
ICE
To Other
External V
Inputs
REF
of Bank
Notes:
1. For some I/O standards.
DS077-2_01_051501
Figure 4: Spartan-IIE Input/Output Block (IOB)
Table 3: Standards Supported by I/O (Typical Values)
Input Output Board
Reference Input Source Termination
Voltage Voltage Voltage Voltage
Input/Output Block
The Spartan-IIE FPGA IOB, as seen in Figure 4, features
inputs and outputs that support a wide variety of I/O signal-
ing standards. These high-speed inputs and outputs are
capable of supporting various state of the art memory and
bus interfaces. The default standard is LVTTL. Table 3 lists
several of the standards which are supported along with the
required reference (VREF), output (VCCO) and board termi-
nation (VTT) voltages needed to meet the standard. For
more details on the I/O standards and termination applica-
tion examples, see XAPP179, "Using SelectIO Interfaces in
Spartan-II and Spartan-IIE FPGAs."
I/O Standard
LVTTL (2-24 mA)
LVCMOS2
(VREF
)
(VCCO
)
(VCCO
)
(VTT
N/A
N/A
N/A
N/A
)
N/A
3.3
3.3
N/A
2.5
2.5
LVCMOS18
N/A
1.8
1.8
PCI (3V,
N/A
3.3
3.3
33 MHz/66 MHz)
GTL
0.8
1.0
0.75
0.9
0.9
1.5
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1.5
1.5
1.5
3.3
1.2
1.5
GTL+
The three IOB registers function either as edge-triggered
D-type flip-flops or as level-sensitive latches. Each IOB has
a clock signal (CLK) shared by the three registers and inde-
pendent Clock Enable (CE) signals for each register.
HSTL Class I
HSTL Class III
HSTL Class IV
0.75
1.5
1.5
SSTL3 Class I
and II
1.5
In addition to the CLK and CE control signals, the three reg-
isters share a Set/Reset (SR). For each register, this signal
can be independently configured as a synchronous Set, a
synchronous Reset, an asynchronous Preset, or an asyn-
chronous Clear.
SSTL2 Class I
and II
1.25
N/A
2.5
1.25
CTT
1.5
1.32
N/A
N/A
N/A
N/A
N/A
N/A
3.3
3.3
2.5
3.3
1.5
N/A
N/A
N/A
AGP
A feature not shown in the block diagram, but controlled by
the software, is polarity control. The input and output buffers
and all of the IOB control signals have independent polarity
controls.
LVDS, Bus LVDS
LVPECL
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DS077-2 (v2.3) June 18, 2008
Product Specification
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Spartan-IIE FPGA Family: Functional Description
Optional pull-up and pull-down resistors and an optional
weak-keeper circuit are attached to each user I/O pad. Prior
to configuration all outputs not involved in configuration are
forced into their high-impedance state. The pull-down resis-
tors and the weak-keeper circuits are inactive, but inputs
may optionally be pulled up. The activation of pull-up resis-
tors prior to configuration is controlled on a global basis by
the configuration mode pins. If the pull-up resistors are not
activated, all the pins will float. Consequently, external
pull-up or pull-down resistors must be provided on pins
required to be at a well-defined logic level prior to configura-
tion.
can be used in close proximity to each other. See I/O Bank-
ing.
An optional weak-keeper circuit is connected to each out-
put. When selected, the circuit monitors the voltage on the
pad and weakly drives the pin High or Low to match the
input signal. If the pin is connected to a multiple-source sig-
nal, the weak keeper holds the signal in its last state if all
drivers are disabled. Maintaining a valid logic level in this
way helps eliminate bus chatter.
Because the weak-keeper circuit uses the IOB input buffer
to monitor the input level, an appropriate VREF voltage must
be provided if the signaling standard requires one. The pro-
vision of this voltage must comply with the I/O banking
rules.
All pads are protected against damage from electrostatic
discharge (ESD) and from over-voltage transients. After
configuration, clamping diodes are connected to VCCO for
LVTTL, PCI, HSTL, SSTL, CTT, and AGP standards.
I/O Banking
Some of the I/O standards described above require VCCO
and/or VREF voltages. These voltages are externally sup-
plied and connected to device pins that serve groups of
IOBs, called banks. Consequently, restrictions exist about
which I/O standards can be combined within a given bank.
All Spartan-IIE FPGA IOBs support IEEE 1149.1-compati-
ble boundary scan testing.
Input Path
A buffer in the IOB input path routes the input signal directly
to internal logic and through an optional input flip-flop.
Eight I/O banks result from separating each edge of the
FPGA into two banks (see Figure 5). The pinout tables
show the bank affiliation of each I/O (see Pinout Tables,
page 53). Each bank has multiple VCCO pins which must be
connected to the same voltage. Voltage requirements are
determined by the output standards in use.
An optional delay element at the D-input of this flip-flop elim-
inates pad-to-pad hold time. The delay is matched to the
internal clock-distribution delay of the FPGA, and when
used, assures that the pad-to-pad hold time is zero.
Each input buffer can be configured to conform to any of the
low-voltage signaling standards supported. In some of
these standards the input buffer utilizes a user-supplied
threshold voltage, VREF. The need to supply VREF imposes
constraints on which standards can used in close proximity
to each other. See I/O Banking.
Bank 0
Bank 1
GCLK3 GCLK2
There are optional pull-up and pull-down resistors at each
input for use after configuration.
Spartan-IIE
Device
Output Path
The output path includes a 3-state output buffer that drives
the output signal onto the pad. The output signal can be
routed to the buffer directly from the internal logic or through
an optional IOB output flip-flop.
GCLK1 GCLK0
The 3-state control of the output can also be routed directly
from the internal logic or through a flip-flip that provides syn-
chronous enable and disable.
Bank 5
Bank 4
DS077-2_02_051501
Each output driver can be individually programmed for a
wide range of low-voltage signaling standards. Each output
buffer can source up to 24 mA and sink up to 48 mA. Drive
strength and slew rate controls minimize bus transients. The
default output driver is LVTTL with 12 mA drive strength and
slow slew rate.
Figure 5: Spartan-IIE I/O Banks
In the TQ144 and PQ208 packages, the eight banks have
VCCO connected together. Thus, only one VCCO level is
allowed in these packages, although different VREF values
are allowed in each of the eight banks.
In most signaling standards, the output high voltage
depends on an externally supplied VCCO voltage. The need
to supply VCCO imposes constraints on which standards
Within a bank, standards may be mixed only if they use the
same VCCO. Compatible standards are shown in Table 4.
GTL and GTL+ appear under all voltages because their
open-drain outputs do not depend on VCCO. Note that VCCO
DS077-2 (v2.3) June 18, 2008
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Product Specification
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Spartan-IIE FPGA Family: Functional Description
is required for most output standards and for LVTTL,
LVCMOS, and PCI inputs.
Hot Swap, Hot Insertion, Hot Socketing Support
The I/O pins support hot swap — also called hot insertion
and hot socketing — and are considered CompactPCI
Friendly according to the PCI Bus v2.2 Specification. Con-
sequently, an unpowered Spartan-IIE FPGA can be
plugged directly into a powered system or backplane with-
out affecting or damaging the system or the FPGA. The hot
swap functionality is built into every XC2S150E,
XC2S400E, and XC2S600E device. All other Spartan-IIE
devices built after Product Change Notice PCN2002-05 also
include hot swap functionality.
Table 4: Compatible Standards
VCCO
Compatible Standards
3.3V
PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP,
LVPECL, GTL, GTL+
2.5V
SSTL2 I, SSTL2 II, LVCMOS2, LVDS, Bus
LVDS, GTL, GTL+
1.8V
1.5V
LVCMOS18, GTL, GTL+
To support hot swap, Spartan-IIE devices include the follow-
ing I/O features.
HSTL I, HSTL III, HSTL IV, GTL, GTL+
•
Signals can be applied to Spartan-IIE FPGA I/O pins
before powering the FPGA’s VCCINT or VCCO supply
inputs.
Spartan-IIE FPGA I/O pins are high-impedance (i.e.,
three-stated) before and throughout the power-up and
configuration processes when employing a
configuration mode that does not enable the
preconfiguration weak pull-up resistors (see Table 11,
page 22).
Some input standards require a user-supplied threshold
voltage, VREF. In this case, certain user-I/O pins are auto-
matically configured as inputs for the VREF voltage. About
one in six of the I/O pins in the bank assume this role.
•
VREF pins within a bank are interconnected internally and
consequently only one VREF voltage can be used within
each bank. All VREF pins in the bank, however, must be con-
nected to the external voltage source for correct operation.
In a bank, inputs requiring VREF can be mixed with those
that do not but only one VREF voltage may be used within a
bank. The VCCO and VREF pins for each bank appear in the
device pinout tables.
•
•
There is no current path from the I/O pin back to the
V
CCINT or VCCO voltage supplies.
Spartan-IIE FPGAs are immune to latch-up during hot
swap.
Within a given package, the number of VREF and VCCO pins
can vary depending on the size of device. In larger devices,
more I/O pins convert to VREF pins. Since these are always
a superset of the VREF pins used for smaller devices, it is
possible to design a PCB that permits migration to a larger
device. All VREF pins for the largest device anticipated must
be connected to the VREF voltage, and not used for I/O.
Once connected to the system, each pin adds a small
amount of capacitance (CIN). Likewise, each I/O consumes
a small amount of DC current, equivalent to the input leak-
age specification (IL). There also may be a small amount of
temporary AC current (IHSPO) when the pin input voltage
exceeds VCCO plus 0.4V, which lasts less than 10 ns.
A weak-keeper circuit within each user-I/O pin is enabled
during the last frame of configuration data and has no
noticeable effect on robust system signals driven by an
active driver or a strong pull-up or pull-down resistor.
Undriven or floating system signals may be affected. The
specific effect depends on how the I/O pin is configured.
User-I/O pins configured as outputs or enabled outputs
have a weak pull-up resistor to VCCO during the last config-
uration frame. User-I/O pins configured as inputs or bidirec-
tional I/Os have weak pull-down resistors. The weak-keeper
circuit turns off when the DONE pin goes High, provided
that it is not used in the configured application.
Table 5: I/O Banking
FT256, FG456,
Package
VCCO Banks
VREF Banks
TQ144, PQ208
Interconnected as 1
8 independent
FG676
8 independent
8 independent
See Xilinx® Application Note XAPP179 for more information
on I/O resources.
12
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Product Specification
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Spartan-IIE FPGA Family: Functional Description
The Spartan-IIE FPGA LUT can also provide a 16-bit shift
register that is ideal for capturing high-speed or burst-mode
data. This mode can also be used to store data in applica-
tions such as Digital Signal Processing.
Configurable Logic Block
The basic building block of the Spartan-IIE FPGA CLB is the
logic cell (LC). An LC includes a 4-input function generator,
carry logic, and storage element. The output from the func-
tion generator in each LC drives the CLB output or the
D input of the flip-flop. Each Spartan-IIE FPGA CLB con-
tains four LCs, organized in two similar slices; a single slice
is shown in Figure 6.
Storage Elements
Storage elements in the Spartan-IIE FPGA slice can be
configured either as edge-triggered D-type flip-flops or as
level-sensitive latches. The D inputs can be driven either by
function generators within the slice or directly from slice
inputs, bypassing the function generators.
In addition to the four basic LCs, the Spartan-IIE FPGA CLB
contains logic that combines function generators to provide
functions of five or six inputs.
In addition to Clock and Clock Enable signals, each slice
has synchronous set and reset signals (SR and BY). SR
forces a storage element into the initialization state speci-
fied for it in the configuration. BY forces it into the opposite
state. Alternatively, these signals may be configured to
operate asynchronously.
Look-Up Tables
Spartan-IIE FPGA function generators are implemented as
4-input look-up tables (LUTs). In addition to operating as a
function generator, each LUT can provide a 16 x 1-bit syn-
chronous RAM. Furthermore, the two LUTs within a slice
can be combined to create a 16 x 2-bit or 32 x 1-bit syn-
chronous RAM, or a 16 x 1-bit dual-port synchronous RAM.
All control signals are independently invertible, and are
shared by the two flip-flops within the slice.
DS077-2 (v2.3) June 18, 2008
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Product Specification
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Spartan-IIE FPGA Family: Functional Description
COUT
YB
Y
I4
I3
I2
I1
G4
G3
G2
G1
S
R
Look-Up
Table
YQ
D
Q
Carry
and
Control
Logic
O
CK
EC
F5IN
BY
SR
XB
X
F4
F3
F2
F1
I4
I3
I2
I1
S
R
Look-Up
Table
XQ
D
Q
Carry
and
Control
Logic
O
CK
EC
BX
CIN
CLK
CE
DS001_04_091400
Figure 6: Spartan-IIE CLB Slice (two identical slices in each CLB)
Similarly, the F6 multiplexer combines the outputs of all four
function generators in the CLB by selecting one of the two
F5-multiplexer outputs. This permits the implementation of
any 6-input function, an 8:1 multiplexer, or selected func-
tions of up to 19 inputs.
Additional Logic
The F5 multiplexer in each slice combines the function gen-
erator outputs (Figure 7). This combination provides either
a function generator that can implement any 5-input func-
tion, a 4:1 multiplexer, or selected functions of up to nine
inputs.
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DS077-2 (v2.3) June 18, 2008
Product Specification
R
Spartan-IIE FPGA Family: Functional Description
Block RAM
CLB
Spartan-IIE FPGAs incorporate several large block RAM
memories. These complement the distributed RAM
Look-Up Tables (LUTs) that provide shallow memory struc-
tures implemented in CLBs.
Slice
LUT
LUT
MUXF6
Block RAM memory blocks are organized in columns. Most
Spartan-IIE devices contain two such columns, one along
each vertical edge. The XC2S400E has four block RAM col-
umns and the XC2S600E has six block RAM columns.
These columns extend the full height of the chip. Each
memory block is four CLBs high, and consequently, a
Spartan-IIE device 16 CLBs high will contain four memory
blocks per column, and a total of eight blocks.
MUXF5
Slice
LUT
LUT
Table 6: Spartan-IIE Block RAM Amounts
Spartan-IIE
Device
Total Block RAM
Bits
# of Blocks
XC2S50E
XC2S100E
XC2S150E
XC2S200E
XC2S300E
XC2S400E
XC2S600E
8
32K
40K
MUXF5
10
12
14
16
40
72
48K
DS077-2_05-111501
56K
Figure 7: F5 and F6 Multiplexers
64K
Each CLB has four direct feedthrough paths, one per LC.
These paths provide extra data input lines or additional local
routing that does not consume logic resources.
160K
288K
Arithmetic Logic
Each block RAM cell, as illustrated in Figure 8, is a fully syn-
chronous dual-ported 4096-bit RAM with independent con-
trol signals for each port. The data widths of the two ports
can be configured independently, providing built-in
bus-width conversion.
Dedicated carry logic provides capability for high-speed
arithmetic functions. The Spartan-IIE FPGA CLB supports
two separate carry chains, one per slice. The height of the
carry chains is two bits per CLB.
The arithmetic logic includes an XOR gate that allows a
1-bit full adder to be implemented within an LC. In addition,
a dedicated AND gate improves the efficiency of multiplier
implementations.
RAMB4_S#_S#
WEA
ENA
The dedicated carry path can also be used to cascade func-
tion generators for implementing wide logic functions.
DOA[#:0]
RSTA
CLKA
ADD[#:0]
DIA[#:0]
BUFTs
Each Spartan-IIE FPGA CLB contains two 3-state drivers
(BUFTs) that can drive on-chip busses. The IOBs on the left
and right sides can also drive the on-chip busses. See Ded-
icated Routing, page 17. Each Spartan-IIE FPGA BUFT
has an independent 3-state control pin and an independent
input pin. The 3-state control pin is an active-Low enable
(T). When all BUFTs on a net are disabled, the net is High.
There is no need to instantiate a pull-up unless desired for
simulation purposes. Simultaneously driving BUFTs onto
the same net will not cause contention. If driven both High
and Low, the net will be Low.
WEB
ENB
RSTB
CLKB
ADDRB[#:0]
DIB[#:0]
DOB[#:0]
DS001_05_060100
Figure 8: Dual-Port Block RAM
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15
Product Specification
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Spartan-IIE FPGA Family: Functional Description
Table 7 shows the depth and width aspect ratios for the
block RAM.
To Adjacent
GRM
Table 7: Block RAM Port Aspect Ratios
To
To Adjacent
GRM
Width
Depth
4096
2048
1024
512
ADDR Bus
ADDR<11:0>
ADDR<10:0>
ADDR<9:0>
ADDR<8:0>
ADDR<7:0>
Data Bus
DATA<0>
Adjacent
GRM
GRM
1
2
DATA<1:0>
DATA<3:0>
DATA<7:0>
DATA<15:0>
To Adjacent
GRM
4
Direct
Direct Connection
To Adjacent
CLB
8
CLB
Connection
To Adjacent
CLB
16
256
DS001_06_032300
The Spartan-IIE FPGA block RAM also includes dedicated
routing to provide an efficient interface with both CLBs and
other block RAMs. See Xilinx Application Note XAPP173 for
more information on block RAM.
Figure 9: Spartan-IIE Local Routing
General Purpose Routing
Most Spartan-IIE FPGA signals are routed on the general
purpose routing, and consequently, the majority of intercon-
nect resources are associated with this level of the routing
hierarchy. The general routing resources are located in hor-
izontal and vertical routing channels associated with the
rows and columns of CLBs. The general-purpose routing
resources are listed below.
Programmable Routing
It is the longest delay path that limits the speed of any
design. Consequently, the Spartan-IIE FPGA routing archi-
tecture and its place-and-route software were defined jointly
to minimize long-path delays and yield the best system per-
formance.
•
Adjacent to each CLB is a General Routing Matrix
(GRM). The GRM is the switch matrix through which
horizontal and vertical routing resources connect, and
is also the means by which the CLB gains access to
the general purpose routing.
The joint optimization also reduces design compilation
times because the architecture is software-friendly. Design
cycles are correspondingly reduced due to shorter design
iteration times.
The software automatically uses the best available routing
based on user timing requirements. The details are pro-
vided here for reference.
•
•
24 single-length lines route GRM signals to adjacent
GRMs in each of the four directions.
96 buffered Hex lines route GRM signals to other
GRMs six blocks away in each one of the four
directions. Organized in a staggered pattern, Hex lines
may be driven only at their endpoints. Hex-line signals
can be accessed either at the endpoints or at the
midpoint (three blocks from the source). One third of
the Hex lines are bidirectional, while the remaining
ones are unidirectional.
12 Longlines are buffered, bidirectional wires that
distribute signals across the device quickly and
efficiently. Vertical Longlines span the full height of the
device, and horizontal ones span the full width of the
device.
Local Routing
The local routing resources, as shown in Figure 9, provide
the following three types of connections:
•
Interconnections among the LUTs, flip-flops, and
General Routing Matrix (GRM), described below.
•
Internal CLB feedback paths that provide high-speed
connections to LUTs within the same CLB, chaining
them together with minimal routing delay
•
•
Direct paths that provide high-speed connections
between horizontally adjacent CLBs, eliminating the
delay of the GRM
I/O Routing
Spartan-IIE devices have additional routing resources
around their periphery that form an interface between the
CLB array and the IOBs. This additional routing, called the
VersaRing™ routing, facilitates pin-swapping and pin-lock-
ing, such that logic redesigns can adapt to existing PCB lay-
outs. Time-to-market is reduced, since PCBs and other
system components can be manufactured while the logic
design is still in progress.
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DS077-2 (v2.3) June 18, 2008
Product Specification
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Spartan-IIE FPGA Family: Functional Description
•
•
Horizontal routing resources are provided for on-chip
3-state busses. Four partitionable bus lines are
provided per CLB row, permitting multiple busses
within a row, as shown in Figure 10.
Dedicated Routing
Some classes of signal require dedicated routing resources
to maximize performance. In the Spartan-IIE FPGA archi-
tecture, dedicated routing resources are provided for two
classes of signal.
Two dedicated nets per CLB propagate carry signals
vertically to the adjacent CLB.
3-State
Lines
CLB
CLB
CLB
CLB
DS001_07_090600
Figure 10: BUFT Connections to Dedicated Horizontal Bus Lines
selected either from these pads or from signals in the gen-
eral purpose routing.
Global Routing
Global Routing resources distribute clocks and other sig-
nals with very high fanout throughout the device. Spar-
tan-IIE devices include two tiers of global routing resources
referred to as primary and secondary global routing
resources.
GCLKPAD2
GCLKBUF2
GCLKPAD3
GCLKBUF3
Global
Clock Rows
Global Clock
Column
•
The primary global routing resources are four
dedicated global nets with dedicated input pins that are
designed to distribute high-fanout clock signals with
minimal skew. Each global clock net can drive all CLB,
IOB, and block RAM clock pins. The primary global
nets may only be driven by global buffers. There are
four global buffers, one for each global net.
Global Clock
Spine
•
The secondary global routing resources consist of 24
backbone lines, 12 across the top of the chip and 12
across the bottom. From these lines, up to 12 unique
signals per column can be distributed via the 12
longlines in the column. These secondary resources
are more flexible than the primary resources since they
are not restricted to routing only to clock pins.
GCLKBUF1
GCLKPAD1
GCLKBUF0
GCLKPAD0
DS001_08_060100
Figure 11: Global Clock Distribution Network
Clock Distribution
Delay-Locked Loop (DLL)
The Spartan-IIE family provides high-speed, low-skew clock
distribution through the primary global routing resources
described above. A typical clock distribution net is shown in
Figure 11.
Associated with each global clock input buffer is a fully digi-
tal Delay-Locked Loop (DLL) that can eliminate skew
between the clock input pad and internal clock-input pins
throughout the device. Each DLL can drive two global clock
networks. The DLL monitors the input clock and the distrib-
uted clock, and automatically adjusts a clock delay element
(Figure 12). Additional delay is introduced such that clock
edges reach internal flip-flops exactly one clock period after
they arrive at the input. This closed-loop system effectively
eliminates clock-distribution delay by ensuring that clock
Four global buffers are provided, two at the top center of the
device and two at the bottom center. These drive the four
primary global nets that in turn drive any clock pin.
Four dedicated clock pads are provided, one adjacent to
each of the global buffers. The input to the global buffer is
DS077-2 (v2.3) June 18, 2008
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17
Product Specification
R
Spartan-IIE FPGA Family: Functional Description
edges arrive at internal flip-flops in synchronism with clock
edges arriving at the input.
DLL can delay the completion of the configuration process
until after it has achieved lock. If the DLL uses external feed-
back, apply a reset after startup to ensure consistent lock-
ing to the external signal. See Xilinx Application Note
XAPP174 for more information on DLLs.
Clock
Distribution
Network
CLKOUT
Variable
Delay Line
CLKIN
Boundary Scan
Spartan-IIE devices support all the mandatory bound-
ary-scan instructions specified in the IEEE standard 1149.1.
A Test Access Port (TAP) and registers are provided that
implement the EXTEST, INTEST, SAMPLE/PRELOAD,
BYPASS, IDCODE, and HIGHZ instructions. The TAP also
supports two USERCODE instructions, internal scan
chains, and configuration/readback of the device.
Control
CLKFB
ds077-2_10_070203
Figure 12: Delay-Locked Loop Block Diagram
The TAP uses dedicated package pins that always operate
using LVTTL. For TDO to operate using LVTTL, the VCCO for
Bank 2 must be 3.3V. Otherwise, TDO switches rail-to-rail
between ground and VCCO. The boundary-scan input pins
(TDI, TMS, TCK) do not have a VCCO requirement and oper-
ate with either 2.5V or 3.3V input signaling levels. TDI, TMS,
and TCK hava a default internal weak pull-up resistor, and
TDO has no default resistor. Bitstream options allow setting
any of the four TAP pins to have an internal pull-up,
pull-down, or neither.
In addition to eliminating clock-distribution delay, the DLL
provides advanced control of multiple clock domains. The
DLL provides four quadrature phases of the source clock,
can double the clock, or divide the clock by 1.5, 2, 2.5, 3, 4,
5, 8, or 16. The phase-shifted output have optional
duty-cycle correction (Figure 13).
0
90 180 270
t
0
90 180 270
CLKIN
CLK2X
Boundary-scan operation is independent of individual IOB
configurations, and unaffected by package type. All IOBs,
including unbonded ones, are treated as independent
3-state bidirectional pins in a single scan chain. Retention of
the bidirectional test capability after configuration facilitates
the testing of external interconnections.
CLKDV_DIVIDE=2
CLKDV
Table 8 lists the boundary-scan instructions supported in
Spartan-IIE FPGAs. Internal signals can be captured during
EXTEST by connecting them to unbonded or unused IOBs.
They may also be connected to the unused outputs of IOBs
defined as unidirectional input pins.
DUTY_CYCLE_CORRECTION=FALSE
CLK0
CLK90
CLK180
CLK270
Table 8: Boundary-Scan Instructions
Boundary-Scan
Command
Binary
Code[4:0]
Description
DUTY_CYCLE_CORRECTION=TRUE
EXTEST
00000
00001
Enables boundary-scan
EXTEST operation
CLK0
CLK90
CLK180
CLK270
SAMPLE/
PRELOAD
Enables boundary-scan
SAMPLE/PRELOAD
operation
USER1
USER2
00010
00011
00100
Access user-defined
register 1
x132_07_092599
Access user-defined
register 2
Figure 13: DLL Output Characteristics
CFG_OUT
Access the
configuration bus for
Readback
The DLL also operates as a clock mirror. By driving the out-
put from a DLL off-chip and then back on again, the DLL can
be used to deskew a board level clock among multiple Spar-
tan-IIE devices.
CFG_IN
00101
Access the
configuration bus for
Configuration
In order to guarantee that the system clock is operating cor-
rectly prior to the FPGA starting up after configuration, the
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Product Specification
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Spartan-IIE FPGA Family: Functional Description
Table 8: Boundary-Scan Instructions (Continued)
The public boundary-scan instructions are available prior to
configuration, except for USER1 and USER2. After configu-
ration, the public instructions remain available together with
any USERCODE instructions installed during the configura-
tion. While the SAMPLE/PRELOAD and BYPASS instruc-
tions are available during configuration, it is recommended
that boundary-scan operations not be performed during this
transitional period.
Boundary-Scan
Command
Binary
Code[4:0]
Description
INTEST
USERCODE
IDCODE
00111
01000
01001
01010
Enables boundary-scan
INTEST operation
Enables shifting out
USER code
Enables shifting out of
ID Code
In addition to the test instructions outlined above, the
boundary-scan circuitry can be used to configure the
FPGA, and also to read back the configuration data.
HIGHZ
Disables output pins
while enabling the
Bypass Register
To facilitate internal scan chains, the User Register provides
three outputs (Reset, Update, and Shift) that represent the
corresponding states in the boundary-scan internal state
machine.
JSTART
01100
Clock the start-up
sequence when
StartupClk is TCK
Figure 14 is a diagram of the Spartan-IIE family boundary
scan logic. It includes three bits of Data Register per IOB,
the IEEE 1149.1 Test Access Port controller, and the
Instruction Register with decodes.
BYPASS
11111
Enables BYPASS
RESERVED
All other
codes
Xilinx reserved
instructions
DATA IN
IOB.T
0
1
0
sd
1
D
D
Q
Q
D
Q
LE
IOB IOB IOB IOB IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
sd
1
0
D
Q
LE
1
0
IOB.I
1
sd
D
Q
D
Q
0
LE
1
0
IOB.Q
IOB.T
Bypass
Register
0
1
M
U
X
TDO
1
sd
sd
Instruction Register
D
D
Q
Q
D
Q
Q
TDI
0
LE
1
D
0
LE
1
0
IOB.I
DATAOUT
UPDATE
EXTEST
CLOCK DATA
REGISTER
SHIFT/
CAPTURE
DS001_09_032300
Figure 14: Spartan-IIE Family Boundary Scan Logic
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Product Specification
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Spartan-IIE FPGA Family: Functional Description
Bit Sequence
TDO.T
TDO.O
Bit 0 ( TDO end)
Bit 1
Bit 2
The bit sequence within each IOB is: In, Out, 3-State. The
input-only pins contribute only the In bit to the boundary
scan I/O data register, while the output-only pins contributes
all three bits.
Top-edge IOBs (Right to Left)
Left-edge IOBs (Top to Bottom)
From a cavity-up view of the chip (as shown in the FPGA
Editor), starting in the upper right chip corner, the boundary
scan data-register bits are ordered as shown in Figure 15.
MODE.I
BSDL (Boundary Scan Description Language) files for
Spartan-IIE family devices are available on the Xilinx web
site at:
Bottom-edge IOBs (Left to Right)
http://www.xilinx.com/support/download/sp2ebsdl.htm.
Right-edge IOBs (Bottom to Top)
BSCANT.UPD
Spartan-IIE FPGA boundary scan IDCODE values are
shown in Table 9.
(TDI end)
DS001_10_032300
Figure 15: Boundary Scan Bit Sequence
Table 9: Spartan-IIE IDCODE Values
IDCODE
Device
XC2S50E
Version
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
Family
Array Size
0 0001 0000
0 0001 0100
0 0001 1000
0 0001 1100
0 0010 0000
0 0010 1000
0 0011 0000
Manufacturer
0000 1001 001
0000 1001 001
0000 1001 001
0000 1001 001
0000 1001 001
0000 1001 001
0000 1001 001
Required
0000 101
0000 101
0000 101
0000 101
0000 101
0000 101
0000 101
1
1
1
1
1
1
1
XC2S100E
XC2S150E
XC2S200E
XC2S300E
XC2S400E
XC2S600E
For HDL design entry, the Xilinx FPGA development system
provides interfaces to several synthesis design environ-
ments.
Development System
Spartan-IIE FPGAs are supported by the Xilinx ISE® CAE
tools. The basic methodology for Spartan-IIE FPGA design
consists of three interrelated steps: design entry, imple-
mentation, and verification. Industry-standard tools are
used for design entry and simulation, while Xilinx provides
proprietary architecture-specific tools for implementation.
A standard interface-file specification, Electronic Design
Interchange Format (EDIF), simplifies file transfers into and
out of the development system.
Spartan-IIE FPGAs are supported by a unified library of
standard functions. This library contains over 400 primitives
and macros, ranging from 2-input AND gates to 16-bit accu-
mulators, and includes arithmetic functions, comparators,
counters, data registers, decoders, encoders, I/O functions,
latches, Boolean functions, multiplexers, shift registers, and
barrel shifters.
The Xilinx development system is integrated under the
Xilinx Project Navigator software, providing designers with a
common user interface regardless of their choice of entry
and verification tools. The software simplifies the selection
of implementation options with pull-down menus and on-line
help.
The design environment supports hierarchical design entry,
with high-level designs that comprise major functional
blocks, while lower-level designs define the logic in these
blocks. These hierarchical design elements are automati-
cally combined by the implementation tools. Different
design entry tools can be combined within a hierarchical
Several advanced software features facilitate Spartan-IIE
FPGA design. CORE Generator™ tool functions, for exam-
ple, include macros with relative location constraints to
guide their placement. They help ensure optimal implemen-
tation of common functions.
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DS077-2 (v2.3) June 18, 2008
Product Specification
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Spartan-IIE FPGA Family: Functional Description
design, thus allowing the most convenient entry method to
be used for each portion of the design.
Configuration
Configuration is the process by which the bitstream of a
design, as generated by the Xilinx development software, is
loaded into the internal configuration memory of the FPGA.
Spartan-IIE devices support both serial configuration, using
the master/slave serial and JTAG modes, as well as
byte-wide configuration employing the Slave Parallel mode.
Design Implementation
The place-and-route tools automatically provide the imple-
mentation flow described in this section. The partitioner
takes the EDIF netlist for the design and maps the logic into
the architectural resources of the FPGA (CLBs and IOBs,
for example). The placer then determines the best locations
for these blocks based on their interconnections and the
desired performance. Finally, the router interconnects the
blocks.
Configuration File
Spartan-IIE devices are configured by sequentially loading
frames of data that have been concatenated into a configu-
ration file. Table 10 shows how much nonvolatile storage
space is needed for Spartan-IIE devices.
The algorithms support fully automatic implementation of
most designs. For demanding applications, however, the
user can exercise various degrees of control over the pro-
cess. User partitioning, placement, and routing information
is optionally specified during the design-entry process. The
implementation of highly structured designs can benefit
greatly from basic floorplanning.
It is important to note that, while a PROM is commonly used
to store configuration data before loading them into the
FPGA, it is by no means required. Any of a number of differ-
ent kinds of under populated nonvolatile storage already
available either on or off the board (for example, hard drives,
FLASH cards, and so on) can be used.
The implementation software incorporates timing-driven
placement and routing. Designers specify timing require-
ments along entire paths during design entry. The timing
path analysis routines then recognize these user-specified
requirements and accommodate them.
Table 10: Spartan-IIE Configuration File Size
Device
Configuration File Size (Bits)
630,048
XC2S50E
XC2S100E
XC2S150E
XC2S200E
XC2S300E
XC2S400E
XC2S600E
863,840
Timing requirements are entered in a form directly relating
to the system requirements, such as the targeted clock fre-
quency, or the maximum allowable delay between two reg-
isters. In this way, the overall performance of the system
along entire signal paths is automatically tailored to
user-generated specifications. Specific timing information
for individual nets is unnecessary.
1,134,496
1,442,016
1,875,648
2,693,440
3,961,632
Design Verification
Modes
In addition to conventional software simulation, FPGA users
can use in-circuit debugging techniques. Because Xilinx
devices are infinitely reprogrammable, designs can be veri-
fied in real time without the need for extensive sets of soft-
ware simulation vectors.
Spartan-IIE devices support the following four configuration
modes:
•
•
•
•
Slave Serial mode
Master Serial mode
Slave Parallel mode
Boundary-scan mode
The development system supports both software simulation
and in-circuit debugging techniques. For simulation, the
system extracts the post-layout timing information from the
design database, and back-annotates this information into
the netlist for use by the simulator. Alternatively, the user
can verify timing-critical portions of the design using the
static timing analyzer.
The Configuration mode pins (M2, M1, M0) select among
these configuration modes with the option in each case of
having the IOB pins either pulled up or left floating prior to
the end of configuration. The selection codes are listed in
Table 11.
For in-circuit debugging, Xilinx offers a download cable,
which connects the FPGA in the target system to a PC or
workstation. After downloading the design into the FPGA,
the designer can read back the contents of the flip-flops,
and so observe the internal logic state. Simple modifica-
tions can be downloaded into the system in a matter of min-
utes.
Configuration through the boundary-scan port is always
available, independent of the mode selection. Selecting the
boundary-scan mode simply turns off the other modes. The
three mode pins have internal pull-up resistors, and default
to a logic High if left unconnected.
DS077-2 (v2.3) June 18, 2008
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Product Specification
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Spartan-IIE FPGA Family: Functional Description
Table 11: Configuration Modes
Preconfiguration
CCLK
Configuration Mode
Pull-ups
M0
0
M1
0
M2
0
Direction
Data Width
Serial DOUT
Master Serial mode
No
Out
1
Yes
Yes
Yes
No
0
0
1
Slave Parallel mode
(SelectMAP)
0
1
0
In
8
1
1
No
No
0
1
1
Boundary-Scan mode
Slave Serial mode
Notes:
Yes
No
1
0
0
N/A
In
1
0
1
Yes
No
1
1
0
Yes
1
1
1
1. During power-on and throughout configuration, the I/O drivers will be in a high-impedance state. After configuration, all unused I/Os
(those not assigned signals) will remain in a high-impedance state. Pins used as outputs may pulse High at the end of configuration
(see Answer 10504).
2. If the Mode pins are set for preconfiguration pull-ups, those resistors go into effect once the rising edge of INIT samples the Mode
pins. They will stay in effect until GTS is released during startup, after which the UnusedPin bitstream generator option will determine
whether the unused I/Os have a pull-up, pull-down, or no resistor.
•
•
Loading data frames
Start-up
Signals
There are two kinds of pins that are used to configure
Spartan-IIE devices: Dedicated pins perform only specific
configuration-related functions; the other pins can serve as
general purpose I/Os once user operation has begun.
The memory clearing and start-up phases are the same for
all configuration modes; however, the steps for the loading
of data frames are different. Thus, the details for data frame
loading are described separately in the sections devoted to
each mode.
The dedicated pins comprise the mode pins (M2, M1, M0),
the configuration clock pin (CCLK), the PROGRAM pin, the
DONE pin and the boundary-scan pins (TDI, TDO, TMS,
TCK). Depending on the selected configuration mode,
CCLK may be an output generated by the FPGA, or may be
generated externally, and provided to the FPGA as an input.
Initiating Configuration
There are two different ways to initiate the configuration pro-
cess: applying power to the device or asserting the PRO-
GRAM input.
Note that some configuration pins can act as outputs. For
correct operation, these pins require a VCCO of 3.3V to drive
an LVTTL signal or 2.5V to drive an LVCMOS signal. All the
relevant pins fall in banks 2 or 3. The CS and WRITE pins
for Slave Parallel mode are located in bank 1.
Configuration on power-up occurs automatically unless it is
delayed by the user, as described in a separate section
below. The waveform for configuration on power-up is
shown in Configuration Switching Characteristics, page 48.
Before configuration can begin, VCCO Bank 2 must be
greater than 1.0V. Furthermore, all VCCINT power pins must
be connected to a 1.8V supply. For more information on
delaying configuration, see Clearing Configuration Memory,
page 23.
For a more detailed description than that given below, see
Module 1 and XAPP176, Configuration and Readback of
the Spartan-II and Spartan-IIE FPGA Families.
The Process
The sequence of steps necessary to configure Spartan-IIE
devices are shown in Figure 16. The overall flow can be
divided into three different phases.
Once in user operation, the device can be re-configured
simply by pulling the PROGRAM pin Low. The device
acknowledges the beginning of the configuration process by
driving DONE Low, then enters the memory-clearing phase.
•
•
Initiating configuration
Configuration memory clear
22
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Spartan-IIE FPGA Family: Functional Description
Clearing Configuration Memory
The device indicates that clearing the configuration memory
is in progress by driving INIT Low.
Configuration
at Power-up
Configuration During
User Operation
Delaying Configuration
At this time, the user can delay configuration by holding
either PROGRAM or INIT Low, which causes the device to
remain in the memory clearing phase. Note that the bidirec-
tional INIT line is driving a Low logic level during memory
clearing. Thus, to avoid contention, use an open-drain driver
to keep INIT Low.
VCCO
AND
VCCINT
High?
No
User Pulls
PROGRAM
Low
Yes
With no delay in force, the device indicates that the memory
is completely clear by driving INIT High. The FPGA samples
its mode pins on this Low-to-High transition.
FPGA
Drives INIT
and DONE Low
Loading Configuration Data
Once INIT is High, the user can begin loading configuration
data frames into the device. The details of loading the con-
figuration data are discussed in the sections treating the
configuration modes individually. The sequence of opera-
tions necessary to load configuration data using the serial
modes is shown in Figure 18. Loading data using the Slave
Parallel mode is shown in Figure 21, page 28.
Clear
Configuration
Memory
Delay
Configuration
Yes
User Holding
PROGRAM
Low?
CRC Error Checking
No
After the loading of configuration data, a CRC value embed-
ded in the configuration file is checked against a CRC value
calculated within the FPGA. If the CRC values do not
match, the FPGA drives INIT Low to indicate that an error
has occurred and configuration is aborted. Note that
attempting to load an incorrect bitstream causes configura-
tion to fail and can damage the device.
Delay
Configuration
Yes
User Holding
INIT
Low?
No
FPGA
Samples
Mode Pins
To reconfigure the device, the PROGRAM pin should be
asserted to reset the configuration logic. Recycling power
also resets the FPGA for configuration. See Clearing Con-
figuration Memory.
Load
Configuration
Data Frames
Start-up
The start-up sequence oversees the transition of the FPGA
from the configuration state to full user operation. A match
of CRC values, indicating a successful loading of the config-
uration data, initiates the sequence.
FPGA Drives
INIT Low
Abort Start-up
No
CRC
Correct?
Yes
Start-up Sequence
FPGA Drives DONE High,
Activates I/Os,
Releases GSR net
User Operation
DS001_11_111501
Figure 16: Configuration Flow Diagram
DS077-2 (v2.3) June 18, 2008
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23
R
Spartan-IIE FPGA Family: Functional Description
During start-up, the device performs four operations:
Default Cycles
1. The assertion of DONE. The failure of DONE to go High
may indicate the unsuccessful loading of configuration
data.
Start-up CLK
Phase
2. The release of the Global Three State (GTS). This
activates all the I/Os to which signals are assigned. The
remaining I/Os stay in a high-impedance state with
internal weak pull-up resistors present.
0
1
2
3
4
5
6 7
DONE
GTS
3. The release of the Global Set Reset (GSR). This allows
all flip-flops to change state.
4. The assertion of Global Write Enable (GWE). This
allows all RAMs and flip-flops to change state.
GSR
By default, these operations are synchronized to CCLK.
The entire start-up sequence lasts eight cycles, called
C0-C7, after which the loaded design is fully functional. The
four operations can be selected to switch on any CCLK
GWE
cycle
C1-C6
through
settings
in
the
Xilinx
Sync to DONE
Development Software. The default timing for start-up is
shown in the top half of Figure 17; heavy lines show default
settings.
Start-up CLK
Phase
0
1
2
3
4
5
6 7
The default Start-up sequence is that one CCLK cycle after
DONE goes High, the global 3-state signal (GTS) is
released. This permits device outputs to turn on as neces-
sary.
DONE High
DONE
GTS
One CCLK cycle later, the Global Set/Reset (GSR) and Glo-
bal Write Enable (GWE) signals are released. This permits
the internal storage elements to begin changing state in
response to the logic and the user clock.
GSR
The bottom half of Figure 17 shows another commonly
used version of the start-up timing known as
Sync-to-DONE. This version makes the GTS, GSR, and
GWE events conditional upon the DONE pin going High.
This timing is important for a daisy chain of multiple FPGAs
in serial mode, since it ensures that all FPGAs go through
start-up together, after all their DONE pins have gone High.
GWE
DS001_13_090600
Figure 17: Start-Up Waveforms
Serial Modes
Sync-to-DONE timing is selected by setting the GTS, GSR,
and GWE cycles to a value of DONE in the configuration
options. This causes these signals to transition one clock
cycle after DONE externally transitions High.
There are two serial configuration modes. In Master Serial
mode, the FPGA controls the configuration process by driv-
ing CCLK as an output. In Slave Serial mode, the FPGA
passively receives CCLK as an input from an external agent
(e.g., a microprocessor, CPLD, or second FPGA in master
mode) that is controlling the configuration process. In both
modes, the FPGA is configured by loading one bit per CCLK
cycle. The MSB of each configuration data byte is always
written to the DIN pin first.
The sequence can also be paused at any stage until lock
has been achieved on any or all DLLs.
See Figure 18 for the sequence for loading data into the
Spartan-IIE FPGA serially. This is an expansion of the
"Load Configuration Data Frames" block in Figure 16,
page 23. Note that CS and WRITE are not normally used
during serial configuration. To ensure successful loading of
the FPGA, do not toggle WRITE with CS Low during serial
configuration.
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Spartan-IIE FPGA Family: Functional Description
from a PROM. A Spartan-IIE device in slave serial mode
should be connected as shown for the third device from the
left. Slave Serial mode is selected by a <11x> on the mode
pins (M0, M1, M2). The weak pull-ups on the mode pins
make slave serial the default mode if the pins are left uncon-
nected.
After INIT
Goes High
User Load One
Configuration
Bit on Next
The serial bitstream must be setup at the DIN input pin a
short time before each rising edge of an externally gener-
ated CCLK.
CCLK Rising Edge
Timing for Slave Serial mode is shown in Figure 24,
page 49.
End of
Configuration
Data File?
No
Daisy Chain
Multiple FPGAs in Slave Serial mode can be daisy-chained
for configuration from a single source. After an FPGA is
configured, data for the next device is sent to the DOUT pin.
Data on the DOUT pin changes on the rising edge of CCLK.
Note that DOUT changes on the falling edge of CCLK for
some Xilinx families but mixed daisy chains are allowed.
Configuration must be delayed until INIT pins of all
daisy-chained FPGAs are High. For more information, see
Start-up, page 23.
Yes
To CRC Check
DS001_14_032300
Figure 18: Loading Serial Mode Configuration Data
Slave Serial Mode
The maximum amount of data that can be sent to the DOUT
pin for a serial daisy chain is 220-1 (1,048,575) 32-bit words,
or 33,554,400 bits, which is approximately 8 XC2S600E bit-
streams. The configuration bitstream of downstream
devices is limited to this size.
In Slave Serial mode, the FPGA’s CCLK pin is driven by an
external source, allowing the FPGA to be configured from
other logic devices such as microprocessors or in a
daisy-chain configuration. Figure 19 shows connections for
a Master Serial FPGA configuring a Slave Serial FPGA
3.3V
3.3V
1.8V
3.3V
3.3V
1.8V
3.3 K
M0 M1
M2
VCCO
M0 M1
M2
VCCO
VCCINT
VCCINT
DOUT
DOUT
DIN
CCLK
Spartan-IIE
Spartan-IIE
(Slave)
(Master Serial)
VCC
Xilinx
PROM
CCLK
CLK
DATA
DIN
CE
CEO
PROGRAM
PROGRAM
DONE
RESET/OE
DONE
INIT
INIT
GND
GND
GND
PROGRAM
Notes:
DS077-2_04_061708
1. If the DriveDone configuration option is not active for any of the FPGAs, pull up DONE with a 330Ω resistor.
Figure 19: Master/Slave Serial Configuration Circuit Diagram
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Product Specification
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Spartan-IIE FPGA Family: Functional Description
The FPGA accepts one bit of configuration data on each ris-
ing CCLK edge. After the FPGA has been loaded, the data
for the next device in a daisy-chain is presented on the
DOUT pin after the rising CCLK edge. The timing for Master
Serial mode is shown in Figure 25, page 49.
Master Serial Mode
In Master Serial mode, the CCLK output of the FPGA drives
a Xilinx PROM, which feeds a serial stream of configuration
data to the FPGA’s DIN input. Figure 19 shows a Master
Serial FPGA configuring a Slave Serial FPGA from a
PROM. A Spartan-IIE device in Master Serial mode should
be connected as shown for the device on the left side. Mas-
ter Serial mode is selected by a <00x> on the mode pins
(M0, M1, M2). The PROM RESET pin is driven by INIT, and
the CE input is driven by DONE. For more information on
serial PROMs, see the Xilinx Configuration PROM data
sheets at:
Slave Parallel Mode (SelectMAP)
The Slave Parallel mode, also known as SelectMAP, is the
fastest configuration option. Byte-wide data is written into
the FPGA on the D0-D7 pins. Note that D0 is the MSB of
each byte for configuration. A BUSY flag is provided for con-
trolling the flow of data at a clock frequency above 50 MHz.
www.xilinx.com/support/documentation/configuration_proms_data_sheets.htm
Figure 20, page 27 shows the connections for two
Spartan-IIE devices using the Slave Parallel mode. Slave
Parallel mode is selected by a <011> on the mode pins (M0,
M1, M2).
The interface is identical to the slave serial mode except
that an oscillator internal to the FPGA is used to generate
the configuration clock (CCLK). Any of a number of different
frequencies ranging from 4 to 60 MHz can be set using the
ConfigRate option in the Xilinx development software.
When selecting a CCLK frequency, ensure that the serial
PROM and any daisy-chained FPGAs are fast enough to
support the clock rate. On power-up, while the first 60 bytes
of the configuration data are being loaded, the CCLK fre-
quency is always 2.5 MHz. This frequency is used until the
ConfigRate bits, part of the configuration file, have been
loaded into the FPGA, at which point the frequency
changes to the selected ConfigRate. Unless a different fre-
quency is specified in the design, the default ConfigRate is
4 MHz. The frequency of the CCLK signal created by the
internal oscillator has a variance of +45%, –30% from the
specified value.
The agent controlling configuration is not shown. Typically, a
processor, a microcontroller, or CPLD controls the Slave
Parallel interface. The controlling agent provides byte-wide
configuration data, CCLK, a Chip Select (CS) signal and a
Write signal (WRITE). If BUSY is asserted (High) by the
FPGA, the data must be held until BUSY goes Low.
After configuration, the pins of the Slave Parallel port
(D0-D7) can be used as additional user I/O. Alternatively,
the port may be retained to permit high-speed 8-bit read-
back. Then data can be read by deasserting WRITE. If
retention is selected, prohibit the D0-D7 pins from being
used as user I/O. See Readback, page 28.
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Spartan-IIE FPGA Family: Functional Description
DATA[7:0]
CCLK
WRITE
BUSY
M1 M2
M0
M1 M2
M0
Spartan-IIE
Spartan-IIE
D0:D7
CCLK
WRITE
BUSY
CS
D0:D7
CCLK
WRITE
BUSY
CS(0)
CS(1)
CS
PROGRAM
PROGRAM
DONE
GND
INIT
DONE
GND
INIT
DONE
INIT
PROGRAM
DS077-2_06_110102
Figure 20: Slave Parallel Configuration Circuit Diagram
Multiple Spartan-IIE FPGAs can be configured using the
Slave Parallel mode, and be made to start-up simulta-
neously. To configure multiple devices in this way, wire the
individual CCLK, Data, WRITE, and BUSY pins of all the
devices in parallel. The individual devices are loaded sepa-
rately by asserting the CS pin of each device in turn and
writing the appropriate data. Sync-to-DONE start-up timing
is used to ensure that the start-up sequence does not begin
until all the FPGAs have been loaded. See Start-up,
page 23.
The timing for Slave Parallel mode is shown in Figure 26,
page 50.
For the present example, the user holds WRITE and CS
Low throughout the sequence of write operations. Note that
when CS is asserted on successive CCLKs, WRITE must
remain either asserted or deasserted. Otherwise an abort
will be initiated, as in the next section.
1. Drive data onto D0-D7. Note that to avoid contention,
the data source should not be enabled while CS is Low
and WRITE is High. Similarly, while WRITE is High, no
more than one device’s CS should be asserted.
Write
When using the Slave Parallel Mode, write operations send
packets of byte-wide configuration data into the FPGA.
Figure 21, page 28 shows a flowchart of the write sequence
used to load data into the Spartan-IIE FPGA. This is an
expansion of the "Load Configuration Data Frames" block in
Figure 16, page 23.
2. On the rising edge of CCLK: If BUSY is Low, the data is
accepted on this clock. If BUSY is High (from a previous
write), the data is not accepted. Acceptance will instead
occur on the first clock after BUSY goes Low, and the
data must be held until this happens.
3. Repeat steps 1 and 2 until all the data has been sent.
4. Deassert CS and WRITE.
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Product Specification
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Spartan-IIE FPGA Family: Functional Description
If CCLK is slower than FCCNH, the FPGA will never assert
BUSY. In this case, the above handshake is unnecessary,
and data can simply be entered into the FPGA every CCLK
cycle.
tions. However, to avoid aborting configuration, WRITE
must continue to be asserted while CS is asserted during
CCLK transitions.
Abort
To abort configuration during a write sequence, deassert
WRITE while holding CS Low. The abort operation is initi-
ated at the rising edge of CCLK. The device will remain
BUSY until the aborted operation is complete. After aborting
configuration, data is assumed to be unaligned to word
boundaries and the FPGA requires a new synchronization
word prior to accepting any new packets.
After INIT
Goes High
User Drives
WRITE and CS
Low
Boundary-Scan Configuration Mode
In the boundary-scan mode, no nondedicated pins are
required, configuration being done entirely through the
IEEE 1149.1 Test Access Port (TAP).
Load One
Configuration
Byte on Next
CCLK Rising Edge
Configuration through the TAP uses the special CFG_IN
instruction. This instruction allows data input on TDI to be
converted into data packets for the internal configuration
bus.
The following steps are required to configure the FPGA
through the boundary-scan port.
FPGA
Yes
Driving BUSY
High?
1. Load the CFG_IN instruction into the boundary-scan
instruction register (IR)
No
2. Enter the Shift-DR (SDR) state
3. Shift a standard configuration bitstream into TDI
4. Return to Run-Test-Idle (RTI)
End of
Configuration
Data File?
No
5. Load the JSTART instruction into IR
6. Enter the SDR state
Yes
7. Clock TCK (if selected) through the startup sequence
(the length is programmable)
User Drives
WRITE and CS
High
8. Return to RTI
Configuration and readback via the TAP is always available.
The boundary-scan mode simply locks out the other modes.
The boundary-scan mode is selected by a <10x> on the
mode pins (M0, M1, M2). Note that the PROGRAM pin must
be pulled High prior to reconfiguration. A Low on the PRO-
GRAM pin resets the TAP controller and no boundary scan
operations can be performed. See Xilinx Application Note
XAPP188 for more information on boundary-scan configu-
ration.
To CRC Check
DS001_19_032300
Figure 21: Loading Configuration Data for the Slave
Parallel Mode
Readback
A configuration packet does not have to be written in one
continuous stretch, rather it can be split into many write
sequences. Each sequence would involve assertion of CS.
The configuration data stored in the Spartan-IIE FPGA con-
figuration memory can be read back for verification. Along
with the configuration data it is possible to read back the
contents of all flip-flops/latches, LUT RAMs, and block
RAMs. This capability is used for real-time debugging.
In applications where multiple clock cycles may be required
to access the configuration data before each byte can be
loaded into the Slave Parallel interface, a new byte of data
may not be ready for each consecutive CCLK edge. In such
a case the CS signal may be deasserted until the next byte
is valid on D0-D7. While CS is High, the Slave Parallel inter-
face does not expect any data and ignores all CCLK transi-
For more detailed information see Xilinx Application Note
XAPP176, Configuration and Readback of the Spartan-II
and Spartan-IIE FPGA Families.
28
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Spartan-IIE FPGA Family: Functional Description
Revision History
Version No.
Date
Description
1.0
2.0
11/15/01 Initial Xilinx release.
11/18/02 Added XC2S400E and XC2S600E. Removed Preliminary designation. Clarified details of I/O
standards, boundary scan, and configuration.
2.1
2.3
07/09/03 Added hot swap description (see Hot Swap, Hot Insertion, Hot Socketing Support). Added
Table 9 containing JTAG IDCODE values. Clarified configuration PROM support.
06/18/08 Added note that TDI, TMS, and TCK have a default pull-up resistor. Add note on maximum
daisy-chain limit. Updated Figure 19 since Mode pins can be pulled up to either 2.5V or 3.3V.
Updated all modules for continuous page, figure, and table numbering. Updated links.
Synchronized all modules to v2.3.
DS077-2 (v2.3) June 18, 2008
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Spartan-IIE FPGA Family: Functional Description
30
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Spartan-IIE FPGA Family:
DCand Switching Characteristics
DS077-3 (v2.3) June 18, 2008
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Product Specification
Definition of Terms
In this document, some specifications may be designated as Advance or Preliminary. These designations are based on the
more detailed timing information used by the development system and reported in the output files. These terms are defined
as follows:
Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or families. Values
are subject to change. Use as estimates, not for production.
Preliminary: Based on characterization. Further changes are not expected.
Except for pin-to-pin input and output parameters, the AC parameter delay specifications included in this document are
derived from measuring internal test patterns. All specifications are representative of worst-case supply voltage and junction
temperature conditions. The parameters included are common to popular designs and typical applications. All specifications
are subject to change without notice.
DC Specifications
(1)
Absolute Maximum Ratings
Symbol
VCCINT
VCCO
VREF
VIN
Description
Supply voltage relative to GND
Min
–0.5
–0.5
–0.5
–0.5
–0.5
–65
-
Max
2.0
Units
V
Supply voltage relative to GND
Input reference voltage
4.0
V
4.0
V
Input voltage relative to GND(2,3)
Voltage applied to 3-state output(3)
Storage temperature (ambient)
Junction temperature
4.0
V
VTS
4.0
V
TSTG
TJ
+150
+125
°C
°C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
2. VIN should not exceed VCCO by more than 3.6V over extended periods of time (e.g., longer than a day).
3. Maximum DC overshoot must be limited to either VCCO + 0.5V or 10 mA, and undershoot must be limited to –0.5V or 10 mA,
whichever is easier to achieve. The Maximum AC conditions are as follows: The device pins may undershoot to –2.0V or overshoot
to VCCO + 2.0V, provided this over/undershoot lasts no more than 11 ns with a forcing current no greater than 100 mA.
®
4. For soldering guidelines, see the Packaging Information on the Xilinx website.
© 2003-2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
DS077-3 (v2.3) June 18, 2008
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Product Specification
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Spartan-IIE FPGA Family: DC and Switching Characteristics
Recommended Operating Conditions
Symbol
Description
Min
Max
85
Units
°C
°C
V
TJ
Junction temperature
Commercial
Industrial
0
–40
100
VCCINT
VCCO
TIN
Supply voltage relative to GND(1)
Supply voltage relative to GND(2)
Input signal transition time(3)
Commercial
Industrial
1.8 – 5%
1.8 – 5%
1.2
1.8 + 5%
1.8 + 5%
3.6
V
Commercial
Industrial
V
1.2
3.6
V
-
250
ns
Notes:
1. Functional operation is guaranteed down to a minimum VCCINT of 1.62V (Nominal VCCINT –10%). For every 50 mV reduction in
VCCINT below 1.71V (nominal VCCINT –5%), all delay parameters increase by approximately 3%.
2. Minimum and maximum values for VCCO vary according to the I/O standard selected.
3. Input and output measurement threshold is ~50% of VCCO. See Delay Measurement Methodology, page 41 for specific details.
DC Characteristics Over Operating Conditions
Symbol
Description
Min
Typ
Max
Units
VDRINT
Data retention VCCINT voltage (below which configuration data may
be lost)
1.5
-
-
V
VDRIO
Data retention VCCO voltage (below which configuration data may be
lost)
1.2
-
-
V
ICCINTQ
Quiescent VCCINT supply current(1)
XC2S50E
Commercial
Industrial
-
10
10
10
10
10
10
10
10
12
12
15
15
15
15
-
200
200
200
200
300
300
300
300
300
300
300
300
400
400
2
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
μA
-
XC2S100E Commercial
Industrial
-
-
XC2S150E Commercial
Industrial
-
-
XC2S200E Commercial
Industrial
-
-
XC2S300E Commercial
Industrial
-
-
XC2S400E Commercial
Industrial
-
-
XC2S600E Commercial
Industrial
-
-
ICCOQ
IREF
IL
Quiescent VCCO supply current(1)
VREF current per VREF pin
-
-
-
20
Input or output leakage current per pin
Input capacitance (sample tested)
–10
-
+10
8
μA
pF
CIN
TQ, PQ, FG, FT packages
-
-
-
IRPU
Pad pull-up (when selected) @ VIN = 0V, VCCO = 3.3V
(sample tested)(2)
-
0.25
mA
IRPD
Pad pull-down (when selected) @ VIN = 3.6V (sample tested)(2)
-
-
0.25
mA
Notes:
1. With no output current loads, no active input pull-up resistors, all I/O pins 3-stated and floating.
2. Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors
do not provide valid logic levels when input pins are connected to other circuits.
32
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DS077-3 (v2.3) June 18, 2008
Product Specification
R
Spartan-IIE FPGA Family: DC and Switching Characteristics
Power-On Requirements
Spartan®-IIE FPGAs require that a minimum supply current
ICCPO be provided to the VCCINT lines for a successful
power-on. If more current is available, the FPGA can con-
sume more than ICCPO min., though this cannot adversely
affect reliability.
A maximum limit for ICCPO is not specified. Be careful when
using foldback/crowbar supplies and fuses. It is possible to
control the magnitude of ICCPO by limiting the supply current
available to the FPGA. A current limit below the trip level will
avoid inadvertently activating over-current protection cir-
cuits.
Symbol
Description
Min(1)
300
Typ
Max
Units
mA
ICCPO
Total VCCINT supplycurrent Commercial XC2S50E - XC2S300E After PCN(2)
-
-
-
-
required during power-on
Before
PCN(2)
500
mA
XC2S400E - XC2S600E
500
500
2
-
-
-
-
-
-
mA
mA
A
Industrial
XC2S50E - XC2S300E After PCN(2)
Before
PCN(2)
XC2S400E - XC2S600E
After PCN(2)
700
500
2
-
-
-
mA
μs
TCCPO VCCINT(3,4) ramp time
-
Before PCN(2)
-
50
-
ms
μA
IHSPO
AC current per pin during power-on in
hot-swap applications when
After PCN(2)
-
60
VIN > VCCO + 0.4V; duration < 10ns
Notes:
1. The ICCPO requirement applies for a brief time (commonly only a few milliseconds) when VCCINT ramps from 0 to 1.8V.
2. Devices built after the Product Change Notice PCN 2002-05 (see
http://www.xilinx.com/support/documentation/customer_notices/pcn2002-05.pdf) have improved power-on requirements. Devices
after the PCN have a ‘T’ preceding the date code as referenced in the PCN. Note that the XC2S150E, XC2S400E, and XC2S600E
always have this mark. Devices before the PCN have an ‘S’ preceding the date code. Note that devices before the PCN are
measured with VCCINT and VCCO powering up simultaneously.
3. The ramp time is measured from GND to 1.8V on a fully loaded board.
4. VCCINT must not dip in the negative direction during power on.
5. I/Os are not guaranteed to be disabled until VCCINT is applied.
6. For more information on designing to meet the power-on specifications, refer to the application note XAPP450 "Power-On Current
Requirements for the Spartan-II and Spartan-IIE Families".
DC Input and Output Levels
Values for VIL and VIH are recommended input voltages.
Values for VOL and VOH are guaranteed output voltages
over the recommended operating conditions. Only selected
standards are tested. These are chosen to ensure that all
standards meet their specifications. The selected standards
are tested at minimum VCCO with the respective IOL and IOH
currents shown. Other standards are sample tested.
VIL
VIH
VOL
V, Max
0.4
VOH
V, Min
2.4
IOL
mA
24
12
8
IOH
mA
–24
–12
–8
Input/Output
Standard
V, Min
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
V, Max
0.8
V, Min
2.0
V, Max
3.6
LVTTL(1)
LVCMOS2
LVCMOS18
PCI, 3.3V
GTL
0.7
1.7
2.7
0.4
1.9
35% VCCO
30% VCCO
65% VCCO
50% VCCO
1.95
0.4
VCCO – 0.4
VCCO + 0.5
3.6
10% VCCO
0.4
90% VCCO Note (2) Note (2)
VREF – 0.05 VREF + 0.05
VREF – 0.1 VREF + 0.1
-
-
40
36
-
-
GTL+
3.6
0.6
DS077-3 (v2.3) June 18, 2008
www.xilinx.com
33
Product Specification
R
Spartan-IIE FPGA Family: DC and Switching Characteristics
VIL
VIH
VOL
V, Max
0.4
VOH
IOL
mA
8
IOH
mA
–8
Input/Output
Standard
V, Min
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
V, Max
V, Min
V, Max
3.6
V, Min
HSTL I
HSTL III
HSTL IV
SSTL3 I
SSTL3 II
SSTL2 I
SSTL2 II
CTT
VREF – 0.1
VREF – 0.1
VREF – 0.1
VREF – 0.2
VREF – 0.2
VREF – 0.2
VREF – 0.2
VREF – 0.2
VREF – 0.2
VREF + 0.1
VREF + 0.1
VREF + 0.1
VREF + 0.2
VREF + 0.2
VREF + 0.2
VREF + 0.2
VREF + 0.2
VREF + 0.2
VCCO – 0.4
VCCO – 0.4
VCCO – 0.4
VREF + 0.6
VREF + 0.8
3.6
0.4
24
48
8
–8
3.6
0.4
–8
3.6
VREF – 0.6
VREF – 0.8
–8
3.6
16
7.6
15.2
8
–16
–7.6
–15.2
–8
3.6
VREF – 0.61 VREF + 0.61
3.6
VREF – 0.8
VREF – 0.4
10% VCCO
VREF + 0.8
VREF + 0.4
3.6
AGP
3.6
90% VCCO Note (2) Note (2)
Notes:
1. VOL and VOH for lower drive currents are sample tested.
2. Tested according to the relevant specifications.
LVDS DC Specifications
Symbol
VCCO
VOH
Description
Supply voltage
Conditions
Min
Typ
Max Units
2.375
2.5
2.625
1.6
V
V
Output High voltage for Q and Q
Output Low voltage for Q and Q
RT = 100Ω across Q and Q signals
RT = 100Ω across Q and Q signals
RT = 100Ω across Q and Q signals
1.25 1.425
VOL
0.9
1.075 1.25
350 450
V
VODIFF
Differential output voltage (Q – Q),
Q = High or (Q – Q), Q = High
250
mV
VOCM
VIDIFF
Output common-mode voltage
RT = 100Ω across Q and Q signals
1.125 1.25 1.375
V
Differential input voltage (Q – Q),
Q = High or (Q – Q), Q = High
Common-mode input voltage = 1.25 V 100
350
-
mV
VICM
Input common-mode voltage
Differential input voltage = 350 mV 0.2
1.25
2.2
V
LVPECL DC Specifications
These values are valid at the output of the source termina-
tion pack shown under LVPECL, with a 100Ω differential
load only. The VOH levels are 200 mV below standard
LVPECL levels and are compatible with devices tolerant of
lower common-mode ranges. The following table summa-
rizes the DC output specifications of LVPECL.
DC Parameter
Min
Max
Min
Max
Min
Max
Units
VCCO
3.0
3.3
3.6
V
V
V
V
V
V
VOH
1.8
0.96
1.49
0.86
0.3
2.11
1.27
2.72
2.125
-
1.92
1.06
1.49
0.86
0.3
2.28
1.43
2.72
2.125
-
2.13
1.30
1.49
0.86
0.3
2.41
1.57
2.72
2.125
-
VOL
VIH
VIL
Differential input voltage
34
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DS077-3 (v2.3) June 18, 2008
Product Specification
R
Spartan-IIE FPGA Family: DC and Switching Characteristics
Switching Characteristics
Internal timing parameters are derived from measuring
internal test patterns. Listed below are representative val-
ues. For more specific, more precise, and worst-case guar-
anteed data, use the values reported by the static timing
analyzer (TRACE in the Xilinx Development System) and
back-annotated to the simulation netlist. All timing parame-
ters assume worst-case operating conditions (supply volt-
age and junction temperature). Values apply to all
Spartan-IIE devices unless otherwise noted.
(1)
Global Clock Input to Output Delay for LVTTL, with DLL (Pin-to-Pin)
Speed Grade
All
Min
1.0
-7
-6
Symbol
Description
Max
3.1
Max
3.1
Units
TICKOFDLL
LVTTL global clock input to output delay using
output flip-flop for LVTTL, 12 mA, fast slew rate,
with DLL.
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at 1.4V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values.
For other I/O standards and different loads, see the tables Constants for Calculating TIOOP and Delay Measurement Methodology,
page 41.
3. DLL output jitter is already included in the timing calculation.
4. For data output with different standards, adjust delays with the values shown in IOB Output Delay Adjustments for Different
Standards(1), page 40. For a global clock input with standards other than LVTTL, adjust delays with values from the I/O Standard
Global Clock Input Adjustments, page 42.
(1)
Global Clock Input to Output Delay for LVTTL, without DLL (Pin-to-Pin)
Speed Grade
All
Min
1.5
1.5
1.5
1.5
1.5
1.5
1.6
-7
Max
4.4
4.4
4.5
4.5
4.5
4.6
4.7
-6
Max
4.6
4.6
4.7
4.7
4.7
4.8
4.9
Symbol
Description
Device
Units
ns
TICKOF
LVTTL global clock input to output
delay using output flip-flop for
LVTTL, 12 mA, fast slew rate,
without DLL.
XC2S50E
XC2S100E
XC2S150E
XC2S200E
XC2S300E
XC2S400E
XC2S600E
ns
ns
ns
ns
ns
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at 1.4V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values.
For other I/O standards and different loads, see the tables Constants for Calculating TIOOP and Delay Measurement Methodology,
page 41.
3. For data output with different standards, adjust delays with the values shown in IOB Output Delay Adjustments for Different
Standards(1), page 40. For a global clock input with standards other than LVTTL, adjust delays with values from the I/O Standard
Global Clock Input Adjustments, page 42.
DS077-3 (v2.3) June 18, 2008
www.xilinx.com
35
Product Specification
R
Spartan-IIE FPGA Family: DC and Switching Characteristics
Global Clock Setup and Hold for LVTTL Standard, with DLL (Pin-to-Pin)
Speed Grade
-7
-6
Symbol
Description
Min
Min
Units
TPSDLL / TPHDLL Input setup and hold time relative to global clock input signal
1.6 / 0
1.7 / 0
ns
for LVTTL standard, no delay, IFF,(1) with DLL
Notes:
1. IFF = Input Flip-Flop or Latch
2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
3. DLL output jitter is already included in the timing calculation.
4. For data input with different standards, adjust the setup time delay by the values shown in IOB Input Delay Adjustments for Different
Standards, page 38. For a global clock input with standards other than LVTTL, adjust delays with values from the I/O Standard
Global Clock Input Adjustments, page 42.
5. A zero hold time listing indicates no hold time or a negative hold time.
Global Clock Setup and Hold for LVTTL Standard, without DLL (Pin-to-Pin)
Speed Grade
-7
-6
Symbol
Description
Device
Min
Min
Units
ns
TPSFD / TPHFD
Input setup and hold time relative
to global clock input signal for
LVTTL standard, with delay, IFF,(1)
without DLL
XC2S50E
XC2S100E
XC2S150E
XC2S200E
XC2S300E
XC2S400E
XC2S600E
1.8 / 0
1.8 / 0
1.9 / 0
1.9 / 0
2.0 / 0
2.0 / 0
2.1 / 0
1.8 / 0
1.8 / 0
1.9 / 0
1.9 / 0
2.0 / 0
2.0 / 0
2.1 / 0
ns
ns
ns
ns
ns
ns
Notes:
1. IFF = Input Flip-Flop or Latch
2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
3. For data input with different standards, adjust the setup time delay by the values shown in IOB Input Delay Adjustments for Different
Standards, page 38. For a global clock input with standards other than LVTTL, adjust delays with values from the I/O Standard
Global Clock Input Adjustments, page 42.
36
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DS077-3 (v2.3) June 18, 2008
Product Specification
R
Spartan-IIE FPGA Family: DC and Switching Characteristics
(1)
IOB Input Switching Characteristics
Input delays associated with the pad are specified for LVTTL levels. For other standards, adjust the delays with the values
shown in IOB Input Delay Adjustments for Different Standards, page 38.
Speed Grade
-7
-6
Symbol
Propagation Delays
TIOPI
Description
Device
Min
Max
Min
Max Units
Pad to I output, no delay
Pad to I output, with delay
All
All
All
0.4
0.5
0.7
0.8
1.0
1.5
0.4
0.5
0.7
0.8
1.0
1.6
ns
ns
ns
TIOPID
TIOPLI
Pad to output IQ via transparent latch,
no delay
TIOPLID
Pad to output IQ via transparent latch,
with delay
XC2S50E
XC2S100E
XC2S150E
XC2S200E
XC2S300E
XC2S400E
XC2S600E
1.3
1.3
1.3
1.3
1.3
1.4
1.5
3.0
3.0
3.2
3.2
3.2
3.2
3.5
1.3
1.3
1.3
1.3
1.3
1.4
1.5
3.1
3.1
3.3
3.3
3.3
3.4
3.7
ns
ns
ns
ns
ns
ns
ns
Sequential Delays
TIOCKIQ
Clock CLK to output IQ
All
0.1
0.7
0.1
0.7
ns
Setup/Hold Times with Respect to Clock CLK
TIOPICK / TIOICKP Pad, no delay
All
1.4 / 0
2.9 / 0
2.9 / 0
3.1 / 0
3.1 / 0
3.1 / 0
3.2 / 0
3.5 / 0
0.7 / 0.01
-
-
-
-
-
-
-
-
-
1.5 / 0
2.9 / 0
2.9 / 0
3.1 / 0
3.1 / 0
3.1 / 0
3.2 / 0
3.5 / 0
0.7 / 0.01
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIOPICKD / TIOICKPD Pad, with delay
XC2S50E
XC2S100E
XC2S150E
XC2S200E
XC2S300E
XC2S400E
XC2S600E
All
TIOICECK / TIOCKICE ICE input
Set/Reset Delays
TIOSRCKI
TIOSRIQ
TGSRQ
SR input (IFF, synchronous)
SR input to IQ (asynchronous)
GSR to output IQ
All
All
All
0.9
0.5
3.8
-
1.0
0.5
3.8
-
ns
ns
ns
1.2
8.5
1.4
9.7
Notes:
1. Input timing for LVTTL is measured at 1.4V. For other I/O standards, see the table Delay Measurement Methodology, page 41.
DS077-3 (v2.3) June 18, 2008
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37
Product Specification
R
Spartan-IIE FPGA Family: DC and Switching Characteristics
IOB Input Delay Adjustments for Different Standards
Input delays associated with the pad are specified for LVTTL. For other standards, adjust the delays by the values shown. A
delay adjusted in this way constitutes a worst-case limit.
Speed Grade
Symbol
Description
Standard
-7
-6
Units
Data Input Delay Adjustments
TILVTTL
TILVCMOS2
TILVCMOS18
TILVDS
Standard-specific data input delay LVTTL
adjustments
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVCMOS2
0
0
LVCMOS18
LVDS
0.20
0.15
0.15
0.08
–0.11
0.14
0.14
0.04
0.04
0.04
0.10
0.04
0.20
0.15
0.15
0.08
–0.11
0.14
0.14
0.04
0.04
0.04
0.10
0.04
TILVPECL
TIPCI33_3
TIPCI66_3
TIGTL
LVPECL
PCI, 33 MHz, 3.3V
PCI, 66 MHz, 3.3V
GTL
TIGTLP
GTL+
TIHSTL
HSTL
TISSTL2
TISSTL3
TICTT
SSTL2
SSTL3
CTT
TIAGP
AGP
38
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DS077-3 (v2.3) June 18, 2008
Product Specification
R
Spartan-IIE FPGA Family: DC and Switching Characteristics
IOB Output Switching Characteristics
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays with the values shown in IOB Output Delay Adjustments for Different Standards(1), page 40.
Speed Grade
-7
-6
Symbol
Propagation Delays
TIOOP
Description
Min
Max
Min
Max
Units
O input to pad
1.0
1.2
2.7
3.1
1.0
1.2
2.9
3.4
ns
ns
TIOOLP
O input to pad via transparent latch
3-state Delays
TIOTHZ
T input to pad high impedance(1)
0.7
1.1
0.8
1.2
1.9
1.7
2.9
2.0
3.2
4.6
0.7
1.1
0.8
1.2
1.9
1.9
3.1
2.2
3.4
4.9
ns
ns
ns
ns
ns
TIOTON
T input to valid data on pad
TIOTLPHZ
T input to pad high impedance via transparent latch(1)
T input to valid data on pad via transparent latch
GTS to pad high impedance(1)
TIOTLPON
TGTS
Sequential Delays
TIOCKP
Clock CLK to pad
0.9
0.7
1.1
2.8
2.0
3.2
0.9
0.7
1.1
2.9
2.2
3.4
ns
ns
ns
TIOCKHZ
Clock CLK to pad high impedance (synchronous)(1)
Clock CLK to valid data on pad (synchronous)
TIOCKON
Setup/Hold Times with Respect to Clock CLK
TIOOCK / TIOCKO O input
1.0 / 0
0.7 / 0
0.9 / 0
0.6 / 0
0.6 / 0
0.9 / 0
-
-
-
-
-
-
1.1 / 0
0.7 / 0
1.0 / 0
0.7 / 0
0.8 / 0
1.0 / 0
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
TIOOCECK / TIOCKOCE OCE input
TIOSRCKO / TIOCKOSR SR input (OFF)
TIOTCK / TIOCKT
3-state setup times, T input
TIOTCECK / TIOCKTCE 3-state setup times, TCE input
TIOSRCKT / TIOCKTSR 3-state setup times, SR input (TFF)
Set/Reset Delays
TIOSRP
TIOSRHZ
TIOSRON
TIOGSRQ
SR input to pad (asynchronous)
SR input to pad high impedance (asynchronous)(1)
SR input to valid data on pad (asynchronous)
GSR to pad
1.2
1.0
1.4
3.8
3.3
2.4
3.7
8.5
1.2
1.0
1.4
3.8
3.5
2.7
3.9
9.7
ns
ns
ns
ns
Notes:
1. Three-state turn-off delays should not be adjusted.
DS077-3 (v2.3) June 18, 2008
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39
Product Specification
R
Spartan-IIE FPGA Family: DC and Switching Characteristics
IOB Output Delay Adjustments for Different Standards(1)
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays by the values shown. A delay adjusted in this way constitutes a worst-case limit.
Speed Grade
Symbol
Description
Standard
-7
-6
Units
Output Delay Adjustments (Adj)
TOLVTTL_S2
TOLVTTL_S4
TOLVTTL_S6
TOLVTTL_S8
TOLVTTL_S12
TOLVTTL_S16
TOLVTTL_S24
TOLVTTL_F2
TOLVTTL_F4
TOLVTTL_F6
TOLVTTL_F8
TOLVTTL_F12
TOLVTTL_F16
TOLVTTL_F24
TOLVCMOS2
TOLVCMOS18
TOLVDS
Standard-specific adjustments for LVTTL, Slow, 2 mA
14.7
7.5
14.7
7.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
output delays terminating at pads
4 mA
(based on standard capacitive
6 mA
4.8
4.8
load, CSL
)
8 mA
3.0
3.0
12 mA
16 mA
24 mA
1.9
1.9
1.7
1.7
1.3
1.3
LVTTL, Fast, 2 mA
13.1
5.3
13.1
5.3
4 mA
6 mA
3.1
3.1
8 mA
1.0
1.0
12 mA
16 mA
24 mA
0
0
–0.05
–0.20
0.09
0.7
–0.05
–0.20
0.09
0.7
LVCMOS2
LVCMOS18
LVDS
–1.2
–0.41
2.3
–1.2
–0.41
2.3
TOLVPECL
TOPCI33_3
TOPCI66_3
TOGTL
LVPECL
PCI, 33 MHz, 3.3V
PCI, 66 MHz, 3.3V
GTL
–0.41
0.49
0.8
–0.41
0.49
0.8
TOGTLP
GTL+
TOHSTL_I
HSTL I
–0.51
–0.91
–1.01
–0.51
–0.91
–0.51
–1.01
–0.61
–0.91
–0.51
–0.91
–1.01
–0.51
–0.91
–0.51
–1.01
–0.61
–0.91
TOHSTL_III
TOHSTL_IV
TOSSTL2_I
TOSSLT2_II
TOSSTL3_I
TOSSTL3_II
TOCTT
HSTL III
HSTL IV
SSTL2 I
SSTL2 II
SSTL3 I
SSTL3 II
CTT
TOAGP
AGP
Notes:
1. Output timing is measured at 1.4V with 35 pF external capacitive load for LVTTL. For other I/O standards and different loads, see the
tables Constants for Calculating TIOOP and Delay Measurement Methodology, page 41.
40
www.xilinx.com
DS077-3 (v2.3) June 18, 2008
Product Specification
R
Spartan-IIE FPGA Family: DC and Switching Characteristics
Calculation of T
Capacitance
as a Function of
Constants for Calculating T
IOOP
IOOP
(1)
CSL
FL
TIOOP is the propagation delay from the O Input of the IOB
to the pad. The values for TIOOP are based on the standard
capacitive load (CSL) for each I/O standard as listed in the
table Constants for Calculating TIOOP, below.
Standard
(pF)
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
10
10
0
(ns/pF)
LVTTL Fast Slew Rate, 2 mA drive
LVTTL Fast Slew Rate, 4 mA drive
LVTTL Fast Slew Rate, 6 mA drive
LVTTL Fast Slew Rate, 8 mA drive
0.41
0.20
For other capacitive loads, use the formulas below to calcu-
0.13
late an adjusted propagation delay, TIOOP1
.
0.079
0.044
0.043
0.033
0.41
TIOOP1 = TIOOP + Adj + (CLOAD – CSL) * FL
LVTTL Fast Slew Rate, 12 mA drive
LVTTL Fast Slew Rate, 16 mA drive
LVTTL Fast Slew Rate, 24 mA drive
LVTTL Slow Slew Rate, 2 mA drive
LVTTL Slow Slew Rate, 4 mA drive
LVTTL Slow Slew Rate, 6 mA drive
LVTTL Slow Slew Rate, 8 mA drive
LVTTL Slow Slew Rate, 12 mA drive
LVTTL Slow Slew Rate, 16 mA drive
LVTTL Slow Slew Rate, 24 mA drive
LVCMOS2
Where:
Adj
is selected from IOB Output Delay Adjustments
for Different Standards(1), page 40, according
to the I/O standard used
CLOAD is the capacitive load for the design
FL is the capacitance scaling factor
0.20
0.100
0.086
0.058
0.050
0.048
0.041
0.050
0.050
0.033
0.014
0.017
0.022
0.016
0.014
0.028
0.016
0.029
0.016
0.035
0.037
Delay Measurement Methodology
VREF
Point Typ(2)
Meas.
(1)
(1)
Standard
LVTTL
VL
VH
0
3
1.4
-
LVCMOS2
PCI33_3
PCI66_3
GTL
0
2.5
1.125
-
LVCMOS18
Per PCI Spec
Per PCI Spec
-
PCI 33 MHz 3.3V
-
PCI 66 MHz 3.3V
VREF – 0.2 VREF + 0.2 VREF
VREF – 0.2 VREF + 0.2 VREF
0.80
1.0
0.75
0.90
0.90
1.5
1.25
1.5
GTL
GTL+
GTL+
0
HSTL Class I VREF – 0.5 VREF + 0.5 VREF
HSTL Class III VREF – 0.5 VREF + 0.5 VREF
HSTL Class IV VREF – 0.5 VREF + 0.5 VREF
SSTL3 I and II VREF – 1.0 VREF + 1.0 VREF
SSTL2 I and II VREF – 0.75 VREF + 0.75 VREF
HSTL Class I
20
20
20
30
30
30
30
20
10
HSTL Class III
HSTL Class IV
SSTL2 Class I
SSTL2 Class II
CTT
AGP
VREF – 0.2 VREF + 0.2 VREF
VREF VREF VREF
(0.2xVCCO) (0.2xVCCO
1.2 – 0.125 1.2 + 0.125 1.2
1.6 – 0.3 1.6 + 0.3 1.6
SSTL3 Class I
–
+
Per AGP
Spec
SSTL3 Class II
)
CTT
LVDS
AGP
LVPECL
Notes:
Notes:
1. I/O parameter measurements are made with the capacitance
values shown above. Refer to Application Note XAPP179 for
appropriate terminations.
1. Input waveform switches between VL and VH.
2. Measurements are made at VREF Typ, Maximum, and
Minimum. Worst-case values are reported.
2. I/O standard measurements are reflected in the IBIS model
3. I/O parameter measurements are made with the capacitance
values shown in the following table, Constants for Calculating
TIOOP. Refer to Application Note XAPP179 for appropriate
terminations.
information except where the IBIS format precludes it.
4. I/O standard measurements are reflected in the IBIS model
information except where the IBIS format precludes it.
DS077-3 (v2.3) June 18, 2008
www.xilinx.com
41
Product Specification
R
Spartan-IIE FPGA Family: DC and Switching Characteristics
Clock Distribution Switching Characteristics
TGPIO is specified for LVTTL levels. For other standards, adjust TGPIO with the values shown in I/O Standard Global Clock
Input Adjustments.
Speed Grade
-7
-6
Symbol
Description
Max
Max
Units
GCLK IOB and Buffer
TGPIO
TGIO
Global clock pad to output
0.7
0.7
0.5
ns
ns
Global clock buffer I input to O output
0.45
I/O Standard Global Clock Input Adjustments
Delays associated with a global clock input pad are specified for LVTTL levels. For other standards, adjust the delays by the
values shown. A delay adjusted in this way constitutes a worst-case limit.
Speed Grade
Symbol
Description
Standard
-7
-6
Units
Data Input Delay Adjustments
TGPLVTTL
TGPLVCMOS2
TGPLVCMOS18
TGPLVCDS
TGPLVPECL
TGPPCI33_3
TGPPCI66_3
TGPGTL
Standard-specific global clock
input delay adjustments
LVTTL
LVCMOS2
LVCMOS18
LVDS
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
0
0.2
0.2
0.38
0.38
0.08
–0.11
0.37
0.37
0.27
0.27
0.27
0.33
0.27
0.38
0.38
0.08
–0.11
0.37
0.37
0.27
0.27
0.27
0.33
0.27
LVCPECL
PCI, 33 MHz, 3.3V
PCI, 66 MHz, 3.3V
GTL
TGPGTLP
GTL+
TGPHSTL
HSTL
TGPSSTL2
TGPSSTL3
TGPCTT
SSTL2
SSTL3
CTT
TGPAGP
AGP
Notes:
1. Input timing for GPLVTTL is measured at 1.4V. For other I/O standards, see the table Delay Measurement Methodology, page 41.
42
www.xilinx.com
DS077-3 (v2.3) June 18, 2008
Product Specification
R
Spartan-IIE FPGA Family: DC and Switching Characteristics
DLL Timing Parameters
Because of the difficulty in directly measuring many internal
timing parameters, those parameters are derived from
benchmark timing patterns. The following guidelines reflect
worst-case values across the recommended operating con-
ditions.
Speed Grade
-7
-6
Symbol
FCLKINHF
FCLKINLF
TDLLPW
Description
FCLKIN
-
Min
60
Max
Min
60
Max
Units
MHz
MHz
ns
Input clock frequency (CLKDLLHF)
Input clock frequency (CLKDLL)
Input clock pulse width
320
275
-
25
160
25
135
≥25 MHz
≥50 MHz
≥100 MHz
≥150 MHz
≥200 MHz
≥250 MHz
≥300 MHz
5.0
3.0
2.4
2.0
1.8
1.5
1.3
-
-
-
-
-
-
-
5.0
3.0
2.4
2.0
1.8
1.5
NA
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
DLL Clock Tolerance, Jitter, and Phase Information
All DLL output jitter and phase specifications were deter-
mined through statistical measurement at the package pins
using a clock mirror configuration and matched drivers.
Figure 22, page 44, provides definitions for various parame-
ters in the table below.
CLKDLLHF
CLKDLL
Min Max
Symbol
TIPTOL
TIJITCC
TLOCK
Description
FCLKIN
Min
Max
1.0
150
20
-
Units
ns
Input clock period tolerance
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.0
300
20
Input clock jitter tolerance (cycle-to-cycle)
Time required for DLL to acquire lock(1)
ps
> 60 MHz
50-60 MHz
40-50 MHz
30-40 MHz
25-30 MHz
μs
μs
μs
μs
μs
ps
25
-
50
-
90
-
120
60
TOJITCC
TPHIO
TPHOO
TPHIOM
Output jitter (cycle-to-cycle) for any DLL clock output(2)
Phase offset between CLKIN and CLKO(3)
Phase offset between clock outputs on the DLL(4)
Phase difference between CLKIN and CLKO(5)
60
100
140
160
200
100
140
160
200
ps
ps
ps
TPHOOM Phase difference between clock outputs on the DLL(6)
Notes:
1. Commercial operating conditions. Add 30% for Industrial operating conditions.
2. Output Jitter is cycle-to-cycle jitter measured on the DLL output clock, excluding input clock jitter.
ps
3. Phase Offset between CLKIN and CLKO is the worst-case fixed time difference between rising edges of CLKIN and CLKO,
excluding output jitter and input clock jitter.
4. Phase Offset between Clock Outputs on the DLL is the worst-case fixed time difference between rising edges of any two DLL
outputs, excluding output jitter and input clock jitter.
5. Maximum Phase Difference between CLKIN and CLKO is the sum of output jitter and phase offset between CLKIN and CLKO, or
the greatest difference between CLKIN and CLKO rising edges due to DLL alone (excluding input clock jitter).
6. Maximum Phase Difference between Clock Outputs on the DLL is the sum of output jitter and phase offset between any DLL
clock outputs, or the greatest difference between any two DLL output rising edges due to DLL alone (excluding input clock jitter).
DS077-3 (v2.3) June 18, 2008
www.xilinx.com
43
Product Specification
R
Spartan-IIE FPGA Family: DC and Switching Characteristics
Period Tolerance: the allowed input clock period change in nanoseconds.
1
T
=
CLKIN
F
+ T
_
IPTOL
T
CLKIN
CLKIN
Output Jitter: the difference between an ideal
reference clock edge and the actual design.
Phase Offset and Maximum Phase Difference
Ideal Period
Actual Period
+/- Jitter
+ Maximum
Phase Difference
+ Phase Offset
DS001_52_090800
Figure 22: Period Tolerance and Clock Jitter
44
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DS077-3 (v2.3) June 18, 2008
Product Specification
R
Spartan-IIE FPGA Family: DC and Switching Characteristics
CLB Switching Characteristics
Delays originating at F/G inputs vary slightly according to the input used. The values listed below are worst-case. Precise
values are provided by the timing analyzer.
Speed Grade
-7
-6
Symbol
Description
Min
Max
Min
Max Units
Combinatorial Delays
TILO
TIF5
4-input function: F/G inputs to X/Y outputs
5-input function: F/G inputs to F5 output
5-input function: F/G inputs to X output
6-input function: F/G inputs to Y output via F6 MUX
6-input function: F5IN input to Y output
0.18
0.3
0.3
0.3
0.04
-
0.42
0.8
0.8
0.9
0.2
0.7
0.18
0.3
0.3
0.3
0.04
-
0.47
0.9
ns
ns
ns
ns
ns
ns
TIF5X
0.9
TIF6Y
1.0
TF5INY
TIFNCTL
0.22
0.8
Incremental delay routing through transparent latch to
XQ/YQ outputs
TBYYB
Sequential Delays
TCKO
BY input to YB output
0.18
0.46
0.18
0.51
ns
FF clock CLK to XQ/YQ outputs
Latch clock CLK to XQ/YQ outputs
0.3
0.3
0.9
0.9
0.3
0.3
1.0
1.0
ns
ns
TCKLO
Setup/Hold Times with Respect to Clock CLK
TICK / TCKI 4-input function: F/G inputs
1.0 / 0
1.4 / 0
0.8 / 0
1.5 / 0
0.7 / 0
0.7 / 0
-
-
-
-
-
-
-
1.1 / 0
1.5 / 0
0.8 / 0
1.6 / 0
0.8 / 0
0.7 / 0
0.6 / 0
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
TIF5CK / TCKIF5 5-input function: F/G inputs
TF5INCK / TCKF5IN 6-input function: F5IN input
TIF6CK / TCKIF6 6-input function: F/G inputs via F6 MUX
TDICK / TCKDI
BX/BY inputs
TCECK / TCKCE CE input
TRCK / TCKR
Clock CLK
TCH
SR/BY inputs (synchronous)
0.52 / 0
Pulse width, High
Pulse width, Low
1.3
1.3
-
-
1.4
1.4
-
-
ns
ns
TCL
Set/Reset
TRPW
Pulse width, SR/BY inputs
2.1
0.3
-
2.4
0.3
-
ns
ns
TRQ
Delay from SR/BY inputs to XQ/YQ outputs
(asynchronous)
0.9
1.0
FTOG
Toggle frequency (for export control)
-
400
-
357
MHz
DS077-3 (v2.3) June 18, 2008
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45
Product Specification
R
Spartan-IIE FPGA Family: DC and Switching Characteristics
CLB Arithmetic Switching Characteristics
Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment
listed. Precise values are provided by the timing analyzer.
Speed Grade
-7
-6
Symbol
Description
Min
Max
Min
Max
Units
Combinatorial Delays
TOPX
TOPXB
F operand inputs to X via XOR
F operand input to XB output
F operand input to Y via XOR
F operand input to YB output
F operand input to COUT output
G operand inputs to Y via XOR
G operand input to YB output
G operand input to COUT output
BX initialization input to COUT
CIN input to X output via XOR
CIN input to XB
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.8
0.8
1.4
1.1
0.9
0.8
1.2
0.9
0.51
0.6
0.07
0.7
0.4
0.14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.8
0.9
1.5
1.3
1.0
0.9
1.3
1.0
0.6
0.7
0.1
0.7
0.5
0.15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TOPY
TOPYB
TOPCYF
TOPGY
TOPGYB
TOPCYG
TBXCY
TCINX
TCINXB
TCINY
CIN input to Y via XOR
TCINYB
CIN input to YB
TBYP
CIN input to COUT output
Multiplier Operation
TFANDXB
TFANDYB
TFANDCY
TGANDYB
TGANDCY
F1/2 operand inputs to XB output via AND
F1/2 operand inputs to YB output via AND
F1/2 operand inputs to COUT output via AND
G1/2 operand inputs to YB output via AND
G1/2 operand inputs to COUT output via AND
-
-
-
-
-
0.35
0.7
0.5
0.6
0.3
-
-
-
-
-
0.4
0.8
0.6
0.7
0.4
ns
ns
ns
ns
ns
Setup/Hold Times with Respect to Clock CLK
TCCKX / TCKCX
TCCKY / TCKCY
CIN input to FFX
CIN input to FFY
1.2 / 0
1.2 / 0
-
-
1.3 / 0
1.3 / 0
-
-
ns
ns
46
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DS077-3 (v2.3) June 18, 2008
Product Specification
R
Spartan-IIE FPGA Family: DC and Switching Characteristics
CLB Distributed RAM Switching Characteristics
Speed Grade
-7
-6
Symbol
Description
Min
Max
Min
Max
Units
Sequential Delays
TSHCKO16
TSHCKO32
Clock CLK to X/Y outputs (WE active, 16 x 1 mode)
Clock CLK to X/Y outputs (WE active, 32 x 1 mode)
0.6
0.8
1.5
1.9
0.6
0.8
1.7
2.1
ns
ns
Setup/Hold Times with Respect to Clock CLK
TAS / TAH
TDS / TDH
F/G address inputs
0.42 / 0
0.53 / 0
0.7 / 0
-
-
-
0.5 / 0
0.6 / 0
0.8 / 0
-
-
-
ns
ns
ns
BX/BY data inputs (DIN)
TWS / TWH CE input (WS)
Clock CLK
TWPH
TWPL
TWC
Pulse width, High
2.1
2.1
4.2
-
-
-
2.4
2.4
4.8
-
-
-
ns
ns
ns
Pulse width, Low
Clock period to meet address write cycle time
CLB Shift Register Switching Characteristics
Speed Grade
-7
-6
Symbol
Sequential Delays
TREG
Description
Min
Max
Min
Max
Units
Clock CLK to X/Y outputs
1.2
2.9
1.2
3.2
ns
Setup/Hold Times with Respect to Clock CLK
TSHDICK
TSHCECK
Clock CLK
TSRPH
BX/BY data inputs (DIN)
CE input (WS)
0.53 / 0
0.7 / 0
-
-
0.6 / 0
0.8 / 0
-
-
ns
ns
Pulse width, High
Pulse width, Low
2.1
2.1
-
-
2.4
2.4
-
-
ns
ns
TSRPL
Block RAM Switching Characteristics
Speed Grade
-7
-6
Symbol
Sequential Delays
TBCKO
Description
Clock CLK to DOUT output
Min
Max
Min
Max
Units
0.6
3.1
0.6
3.5
ns
Setup/Hold Times with Respect to Clock CLK
TBACK / TBCKA
TBDCK/ TBCKD
TBECK/ TBCKE
TBRCK/ TBCKR
TBWCK/ TBCKW
Clock CLK
TBPWH
ADDR inputs
DIN inputs
EN inputs
1.0 / 0
1.0 / 0
2.2 / 0
2.1 / 0
2.0 / 0
-
-
-
-
-
1.1 / 0
1.1 / 0
2.5 / 0
2.3 / 0
2.2 / 0
-
-
-
-
-
ns
ns
ns
ns
ns
RST input
WEN input
Pulse width, High
1.4
1.4
2.7
-
-
-
1.5
1.5
3.0
-
-
-
ns
ns
ns
TBPWL
Pulse width, Low
TBCCS
CLKA -> CLKB setup time for different ports
DS077-3 (v2.3) June 18, 2008
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47
Product Specification
R
Spartan-IIE FPGA Family: DC and Switching Characteristics
TBUF Switching Characteristics
Speed Grade
-7
-6
Symbol
TIO
Description
Max
0
Max
0
Units
ns
IN input to OUT output
TOFF
TON
TRI input to OUT output high impedance
TRI input to valid data on OUT output
0.1
0.1
0.11
0.11
ns
ns
JTAG Test Access Port Switching Characteristics
Speed Grade
-7
-6
Symbol
Description
Min
Max
Min
Max
Units
Setup/Hold Times with Respect to TCK
TTAPTCK / TTCKTAP TMS and TDI setup times and hold times
Sequential Delays
4.0 / 2.0
-
4.0 / 2.0
-
ns
TTCKTDO
Output delay from clock TCK to output TDO
TCK clock frequency
-
-
11.0
33
-
-
11.0
33
ns
MHz
FTCK
Configuration Switching Characteristics
(1)
V
T
POR
CC
PROGRAM
INIT
T
PL
T
ICCK
Valid
CCLK Output or Input
M0, M1, M2
(Required)
DS001_12_102301
.
All Devices
Symbol
TPOR
Description
Min
Max
2
Units
ms
Power-on reset
Program latency
-
-
TPL
100
4
μs
TICCK
CCLK output delay (Master serial
mode only)
0.5
μs
TPROGRAM Program pulse width
300
-
ns
Notes:
1. Before configuration can begin, VCCINT and VCCO Bank 2 must reach the recommended operating voltage.
Figure 23: Configuration Timing on Power-Up
48
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DS077-3 (v2.3) June 18, 2008
Product Specification
R
Spartan-IIE FPGA Family: DC and Switching Characteristics
DIN
T
T
T
CCD
CCL
DCC
CCLK
T
CCH
T
CCO
DOUT
(Output)
DS001_16_032300
.
All Devices
Symbol
Description
Min
Max
Units
TDCC
TCCD
/
DIN setup/hold
5 / 0
-
ns
TCCO
TCCH
TCCL
FCC
DOUT
-
5
5
-
12
-
ns
ns
CCLK
High time
Low time
-
ns
Maximum frequency
66
MHz
Figure 24: Slave Serial Mode Timing
CCLK
(Output)
T
CKDS
T
DSCK
Serial Data In
T
CCO
Serial DOUT
(Output)
DS001_17_110101
Units
ns
.
All Devices
Symbol
Description
DIN setup/hold
Min
Max
TDSCK
/
5 / 0
-
TCKDS
TCCO
FCC
CCLK DOUT
Frequency tolerance with respect to
nominal
-
12
ns
-
–30%
+45%
Figure 25: Master Serial Mode Timing
DS077-3 (v2.3) June 18, 2008
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49
Product Specification
R
Spartan-IIE FPGA Family: DC and Switching Characteristics
CCLK
T
CS
T
SMCCCS
SMCSCC
T
WRITE
T
SMWCC
SMCCW
T
SMDCC
T
SMCCD
DATA[7:0]
BUSY
T
SMCKBY
No Write
Write
No Write
Write
DS001_20_061200
All Devices
Symbol
Description
Min
Max
Units
TSMDCC
TSMCCD
TSMCSCC
TSMCCCS
TSMCCW
TSMWCC
TSMCKBY
FCC
/
D0-D7 setup/hold
5 / 1
7 / 1
7 / 1
-
ns
/
CS setup/hold
-
-
ns
ns
/
WRITE setup/hold
CCLK
BUSY propagation delay
Frequency
-
-
-
12
66
50
ns
MHz
MHz
FCCNH
Frequency with no handshake
Figure 26: Slave Parallel (SelectMAP) Mode Write Timing
CCLK
CS
WRITE
DATA[7:0]
BUSY
Abort
DS001_21_032300
Figure 27: Slave Parallel (SelectMAP) Mode Write Abort Waveforms
50
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DS077-3 (v2.3) June 18, 2008
Product Specification
R
Spartan-IIE FPGA Family: DC and Switching Characteristics
Revision History
Version No.
Date
Description
1.0
1.1
2.0
11/15/01 Initial Xilinx release.
06/28/02 Added -7 speed grade and extended DLL specs to Industrial.
11/18/02 Added XC2S400E and XC2S600E. Added minimum specifications. Added reference to
XAPP450 for Power-On Requirements. Removed Preliminary designation.
2.1
2.3
07/09/03 Added ICCINTQ typical values. Reduced ICCPO power-on current requirements. Relaxed
TCCPO power-on ramp requirements. Added IHSPO to describe current in hot-swap
applications. Updated TPSFD / TPHFD description to indicate use of delay element.
06/18/08 Updated I/O measurement thresholds. Updated all modules for continuous page, figure, and
table numbering. Updated links. Synchronized all modules to v2.3.
DS077-3 (v2.3) June 18, 2008
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Product Specification
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Spartan-IIE FPGA Family: DC and Switching Characteristics
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DS077-3 (v2.3) June 18, 2008
Product Specification
R
Spartan-IIE FPGA Family:
Pinout Tables
DS077-4 (2.3) June 18, 2008
0
Product Specification
Introduction
Pin Types
This section describes how the various pins on a
Most pins on a Spartan-IIE FPGA are general-purpose,
user-defined I/O pins. There are, however, different
functional types of pins on Spartan-IIE FPGA packages, as
outlined below.
Spartan®-IIE FPGA connect within the supported
component packages, and provides device-specific thermal
characteristics. Spartan-IIE FPGAs are available in both
standard and Pb-free, RoHS versions of each package, with
the Pb-free version adding a “G” to the middle of the
package code. Except for the thermal characteristics, all
information for the standard package applies equally to the
Pb-free package.
Pin Definitions
Dedicated
Pad Name
Pin
Direction
Description
GCK0, GCK1, GCK2,
GCK3
No
Input
Clock input pins that connect to Global Clock buffers or DLL
inputs. These pins become user inputs when not needed for
clocks.
DLL
No
Input
Input
Clock input pins that connect to DLL input or feedback clocks.
Differential clock input (N input of pair) when paired with adjacent
GCK input. Becomes a user I/O when not needed for clocks.
M0, M1, M2
CCLK
Yes
Yes
Mode pins used to specify the configuration mode.
Input or Output The configuration Clock I/O pin. It is an input for Slave Parallel
and Slave Serial modes, and output in Master Serial mode. After
configuration, it is an input only with Don’t Care logic levels.
PROGRAM
DONE
Yes
Yes
Input
Initiates a configuration sequence when asserted Low.
Bidirectional
Indicates that configuration loading is complete, and that the
start-up sequence is in progress. The output may be open drain.
INIT
No
Bidirectional
(Open-drain)
When Low, indicates that the configuration memory is being
cleared. Goes High to indicate the end of initialization. Goes back
Low to indicate a CRC error. This pin becomes a user I/O after
configuration.
DOUT/BUSY
No
Output
In Slave Parallel mode, BUSY controls the rate at which
configuration data can be loaded. It is not needed below 50 MHz.
This pin becomes a user I/O after configuration unless the Slave
Parallel port is retained.
In serial modes, DOUT provides configuration data to
downstream devices in a daisy-chain. This pin becomes a user
I/O after configuration.
© 2003-2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
DS077-4 (2.3) June 18, 2008
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Product Specification
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Spartan-IIE FPGA Family: Pinout Tables
Pin Definitions (Continued)
Dedicated
Pad Name
Pin
Direction
Description
D0/DIN, D1, D2, D3,
D4, D5, D6, D7
No
Input or Output In Slave Parallel mode, D0-D7 are configuration data input pins.
During readback, D0-D7 are output pins. These pins become
user I/Os after configuration unless the Slave Parallel port is
retained.
In serial modes, DIN is the single data input. This pin becomes a
user I/O after configuration.
WRITE
CS
No
No
Input
Input
In Slave Parallel mode, the active-low Write Enable signal. This
pin becomes a user I/O after configuration unless the Slave
Parallel port is retained.
In Slave Parallel mode, the active-low Chip Select signal. This pin
becomes a user I/O after configuration unless the Slave Parallel
port is retained.
TDI, TDO, TMS, TCK
VCCINT
Yes
Yes
Yes
Mixed
Input
Input
Boundary Scan Test Access Port pins (IEEE 1149.1).
1.8V power supply pins for the internal core logic.
VCCO
Power supply pins for output drivers (1.5V, 1.8V, 2.5V, or 3.3V
subject to banking rules in the Functional Description module.
VREF
No
Input
Input threshold reference voltage pins. Become user I/Os when
an external threshold voltage is not needed (subject to banking
rules in the Functional Description module.
GND
Yes
No
Input
Ground. All must be connected.
IRDY, TRDY
See PCI core
These signals can only be accessed when using Xilinx PCI cores.
documentation If the cores are not used, these pins are available as user I/Os.
L#[P/N]
(e.g., L0P)
No
Bidirectional
Differential I/O with synchronous output. P = positive, N =
negative. The number (#) is used to associate the two pins of a
differential pair. Becomes a general user I/O when not needed for
differential signals.
L#[P/N]_Y
(e.g., L0P_Y)
No
Bidirectional
Differential I/O with asynchronous or synchronous output
(asynchronous output not compatible for all densities in a
package). P = positive, N = negative. The number (#) is used to
associate the two pins of a differential pair. Becomes a general
user I/O when not needed for differential signals.
L#[P/N]_YY
(e.g., L0P_YY)
No
No
Bidirectional
Bidirectional
Differential I/O with asynchronous or synchronous output
(compatible for all densities in a package). P = positive, N =
negative. The number (#) is used to associate the two pins of a
differential pair. Becomes a general user I/O when not needed for
differential signals.
I/O
These pins can be configured to be input and/or output after
configuration is completed. Unused I/Os are disabled with a weak
pull-down resistor. After power-on and before configuration is
completed, these pins are either pulled up or left floating
according to the Mode pin values. See the DC and Switching
Characteristics module for power-on characteristics.
54
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DS077-4 (2.3) June 18, 2008
Product Specification
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Spartan-IIE FPGA Family: Pinout Tables
Spartan-IIE family is not footprint compatible with any other
FPGA family. The following package-specific pinout tables
indicate function, pin, and bank information for all devices
available in that package. The pinouts follow the pad loca-
tions around the die, starting from pin 1 on the QFP pack-
ages.
Spartan-IIE Package Pinouts
The Spartan®-IIE family of FPGAs is available in five popu-
lar, low-cost packages, including plastic quad flat packs and
fine-pitch ball grid arrays. Family members have footprint
compatibility across devices provided in the same package,
with minor exceptions due to the smaller number of I/O in
smaller devices or due to LVDS/LVPECL pin pairing. The
Table 12: Spartan-IIE Family Package Options
(1)
Maximum Lead Pitch
Footprint
Height
(mm)
Mass
(g)
Package
Leads
Type
I/O
102
146
182
329
514
(mm)
Area (mm)
TQ144 / TQG144
PQ208 / PQG208
FT256 / FTG256
FG456 / FGG456
FG676 / FGG676
144
208
256
456
676
Thin Quad Flat Pack (TQFP)
0.5
22 x 22
30.6 x 30.6
17 x 17
1.60
3.70
1.55
2.60
2.60
1.4
5.3
1.0
2.2
3.1
Plastic Quad Flat Pack (PQFP)
Fine-pitch Thin Ball Grid Array (FBGA)
Fine-pitch Ball Grid Array (FBGA)
Fine-pitch Ball Grid Array (FBGA)
0.5
1.0
1.0
23 x 23
1.0
27 x 27
Notes:
1. Package mass is 10%.
Mechanical Drawings
Package Overview
Table 12 shows the five low-cost, space-saving production
package styles for the Spartan-IIE family.
Detailed mechanical drawings for each package type are
available from the Xilinx web site at the specified location in
Table 13.
Each package style is available in an environmentally
friendly lead-free (Pb-free) option. The Pb-free packages
include an extra ‘G’ in the package style name. For
example, the standard “TQ144” package becomes
“TQG144” when ordered as the Pb-free option. Leaded
(non-Pb-free) packages may be available for selected
devices, with the same pin-out and without the "G" in the
ordering code; contact Xilinx® sales for more information.
The mechanical dimensions of the standard and Pb-free
packages are similar, as shown in the mechanical drawings
provided in Table 13.
Material Declaration Data Sheets (MDDS) are also
available on the Xilinx web site for each package.
Table 13: Xilinx Package Documentation
Package
TQ144
Drawing
MDDS
Package Drawing
PK169_TQ144
PK126_TQG144
PK166_PQ208
PK123_PQG208
PK158_FT256
PK115_FTG256
PK154_FG456
PK109_FGG456
PK155_FG676
PK111_FGG676
TQG144
PQ208
Package Drawing
Package Drawing
Package Drawing
Package Drawing
PQG208
FT256
For additional package information, see UG112: Device
Package User Guide.
FTG256
FG456
FGG456
FG676
FGG676
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Product Specification
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Spartan-IIE FPGA Family: Pinout Tables
value similarly reports the difference between the board and
junction temperature. The junction-to-ambient (θJA) value
reports the temperature difference between the ambient
environment and the junction temperature. The θJA value is
reported at different air velocities, measured in linear feet
per minute (LFM). The “Still Air (0 LFM)” column shows the
Package Thermal Characteristics
Table 14 provides the thermal characteristics for the various
Spartan-II FPGA package offerings. This information is also
available using the Thermal Query tool on xilinx.com
(www.xilinx.com/cgi-bin/thermal/thermal.pl).
θ
JA value in a system without a fan. The thermal resistance
drops with increasing air flow.
The junction-to-case thermal resistance (θJC) indicates the
difference between the temperature measured on the
package body (case) and the die junction temperature per
watt of power consumption. The junction-to-board (θJB)
Table 14: Spartan-IIE Package Thermal Characteristics
Junction-to-Ambient (θ
)
JA
at Different Air Flows
Junction-to-Case
(θ
Junction-to-
Still Air
(0 LFM)
Package
Device
)
Board (θ
N/A
N/A
N/A
N/A
N/A
N/A
N/A
17.8
15.1
14.8
11.4
10.1
8.8
)
JB
250 LFM
25.1
24.4
25.9
25.2
25.2
23.9
23.3
21.6
19.5
19.3
16.6
15.6
14.5
19.2
19.0
16.1
15.1
11.7
11.2
11.1
9.9
500 LFM
21.5
20.8
22.9
22.3
22.2
21.2
20.6
20.4
18.2
18.0
15.2
14.2
13.2
18.1
17.9
15.0
13.9
10.5
10.0
9.8
750 LFM
20.1
19.6
21.2
20.7
20.6
19.6
19.1
20.0
17.8
17.6
14.7
13.7
12.6
17.4
17.1
14.3
13.2
10.0
9.5
Units
JC
XC2S50E
5.8
5.3
7.1
6.1
6.0
4.6
4.0
7.3
5.8
5.7
3.9
3.2
2.5
8.4
8.2
6.3
5.6
3.6
2.7
4.1
3.4
32.3
31.4
35.1
34.2
34.1
32.4
31.6
27.4
25.0
24.8
21.9
20.8
19.7
24.3
24.1
21.0
19.9
17.7
17.3
15.6
14.5
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
TQ144
TQG144
XC2S100E
XC2S50E
XC2S100E
XC2S150E
XC2S200E
XC2S300E
XC2S50E
PQ208
PQG208
XC2S100E
XC2S150E
XC2S200E
XC2S300E
XC2S400E
XC2S100E
XC2S150E
XC2S200E
XC2S300E
XC2S400E
XC2S600E
XC2S400E
XC2S600E
FT256
FTG256
14.9
14.6
11.6
10.4
6.5
FG456
FGG456
5.0
7.9
9.2
FG676
FGG676
6.9
8.6
7.9
56
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Product Specification
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Spartan-IIE FPGA Family: Pinout Tables
Asynchronous Output Pad Name Designation
Low Voltage Differential Signals (LVDS
and LVPECL)
The Spartan-IIE family features low-voltage differential sig-
naling (LVDS and LVPECL). Each signal utilizes two pins on
the Spartan-IIE device, known as differential pin pairs. Each
differential pin pair has a Positive (P) and a Negative (N) pin.
These pairs are labeled in the following manner.
Because of differences between densities, the differential
pairs that can be used for asynchronous outputs vary by
device. The pairs that are available in all densities for a
given package have the _YY suffix. These pins should be
used for differential asynchronous outputs if the design may
later move to a different density. All other differential pairs
that can be used for asynchronous outputs have the _Y suf-
fix.
I/O, L#[P/N][-/_Y/_YY]
where
To simplify the following tables, the "Pad Name" column
shows the part of the name that is common across densi-
ties. The "Pad Name" column leaves out the _Y suffix and
the "LVDS Asynchronous Output Option" column indicates
the densities that allow asynchronous outputs for LVDS or
LVPECL on the given pin.
L = LVDS or LVPECL pin
# = Pin pair number
P = Positive
N = Negative
_Y = Asynchronous output allowed (device-dependent)
_YY = Asynchronous output allowed (all devices)
DLL Pins
Pins labeled "I/O (DLL)" can be used as general-purpose
I/O or as inputs to the DLL. Adjacent DLL pins form a differ-
ential pair. They reside in two different banks, so if they are
outputs the VCCO level must be the same for both banks.
Each DLL pin can also be paired with the adjacent GCK
clock pin for a differential clock input. The "I/O (DLL)" pin
always becomes the N terminal when paired with GCK,
even if it is labeled "P" for its pairing with the adjacent DLL
pin.
Available Differential Pairs According to
Package Type
Device
TQ144 PQ208 FT256 FG456 FG676
XC2S50E
XC2S100E
XC2S150E
XC2S200E
XC2S300E
XC2S400E
XC2S600E
28
28
-
50
50
50
50
50
-
83
83
83
83
83
83
-
-
-
86
-
114
120
120
120
120
-
-
VREF Pins
-
Pins labeled "I/O, VREF" can be used as either an I/O or a
VREF pin. If any I/O pin within the bank requires a VREF
input, all the VREF pins in the bank must be connected to
the same voltage. See the I/O banking rules in the Func-
tional Description module for more detail. If no pin in a
given bank requires VREF, then that bank's VREF pins can
be used as general I/O.
-
-
-
172
205
-
-
Synchronous or Asynchronous
I/O pins for differential signals can either be synchronous or
asynchronous, input or output. Differential signaling
requires the pins of each pair to switch simultaneously. If the
output signals driving the pins are from IOB flip-flops, they
are synchronous. If the signals driving the pins are from
internal logic, they are asynchronous, and therefore more
care must be taken that they are simultaneous. Any differ-
ential pairs can be used for synchronous input and output
signals as well as asynchronous input signals.
To simplify the following tables, the "Pad Name" column
shows the part of the name that is common across densi-
ties. When VREF is only available in limited densities, the
"Pad Name" column leaves out the VREF designation and
the "VREF Option" column indicates the densities that pro-
vide VREF on the given pin.
VCCO Banks
In the TQ144 and PQ208 packages, the eight banks have
VCCO connected together. Thus, only one VCCO is
allowed in these packages, although different VREF values
are allowed in each of the eight banks. See I/O Banking.
However, only the differential pairs with the _Y or _YY suffix
can be used for asynchronous output signals.
DS077-4 (2.3) June 18, 2008
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Product Specification
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Spartan-IIE FPGA Family: Pinout Tables
Pinout Tables
The following device-specific pinout tables include all pack-
ages available for each Spartan-IIE device. They follow the
pad locations around the die. In the TQ144 package, all
VCCO pins must be connected to the same voltage.
TQ144 Pinouts (XC2S50E and XC2S100E)
(Continued)
Pad Name
LVDS
Async.
Output
Option
VREF
Option
TQ144 Pinouts (XC2S50E and XC2S100E)
Function
I/O, L22N
Bank
Pin
6
6
6
P27 XC2S50E XC2S100E
Pad Name
LVDS
Async.
Output
Option
I/O
P28
P29
-
-
-
VREF
Option
I/O, VREF
Bank 6
All
Function
GND
Bank
Pin
P1
P2
P3
P4
P5
-
-
-
-
-
-
-
-
-
I/O
6
6
6
-
P30
P31
P32
P33
P34
P35
P36
P37
-
All
All
-
-
-
-
-
-
-
-
-
TMS
I/O
I/O, L21P_YY
I/O, L21N_YY
M1
7
7
7
-
I/O
-
I/O, VREF
Bank 7
All
GND
-
-
M0
-
-
I/O
7
7
7
-
P6
P7
-
-
VCCO
M2
-
-
I/O, L27P
I/O, L27N
GND
XC2S50E XC2S100E
-
-
P8
XC2S50E
-
-
P9
-
I/O, L20N_YY
I/O, L20P_YY
I/O
5
5
5
5
P38
P39
P40
P41
All
All
-
-
-
I/O, L26P_YY
I/O, L26N_YY
7
7
7
P10
P11
All
All
-
-
-
I/O, VREF
Bank 7, L25P
P12 XC2S50E
All
I/O, VREF
Bank 5
-
All
I/O, L25N
I/O
7
7
7
-
P13 XC2S50E
-
-
-
-
-
I/O
5
5
5
-
P42
P43
P44
P45
P46
P47
P48
P49
-
All
All
-
-
P14
P15
P16
P17
-
-
-
-
I/O, L19N_YY
I/O, L19P_YY
GND
XC2S100E
I/O (IRDY)
GND
-
-
VCCO
-
VCCINT
-
-
-
I/O, L18N_YY
I/O, L18P_YY
5
5
5
All
All
-
-
I/O (TRDY)
VCCINT
I/O
6
-
P18
P19
P20
-
-
-
-
-
-
I/O, VREF
Bank 5
All
6
6
6
-
I/O, L24P
P21 XC2S50E
P22 XC2S50E
-
I/O (DLL), L17N
VCCINT
GCK1, I
VCCO
5
-
P50
P51
P52
P53
P54
-
-
-
-
-
-
-
-
-
-
I/O, VREF
Bank 6, L24N
All
5
5
-
I/O, L23P_YY
I/O, L23N_YY
GND
6
6
-
P23
P24
P25
All
All
-
-
-
-
-
GND
I/O, L22P
6
P26 XC2S50E
GCK0, I
4
P55
-
-
58
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Product Specification
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Spartan-IIE FPGA Family: Pinout Tables
TQ144 Pinouts (XC2S50E and XC2S100E)
(Continued)
TQ144 Pinouts (XC2S50E and XC2S100E)
(Continued)
Pad Name
LVDS
Async.
Output
Option
Pad Name
LVDS
Async.
Output
Option
VREF
Option
VREF
Option
Function
Bank
Pin
P56
P57
P58
Function
I/O, VREF
Bank 3, L10N
I/O (D4), L10P
I/O
Bank
Pin
I/O (DLL), L17P
I/O
4
4
4
-
-
-
-
-
3
P85 XC2S50E
All
3
3
-
P86 XC2S50E
-
-
-
-
-
-
I/O, VREF
Bank 4
All
P87
P88
P89
P90
P91
-
-
-
-
-
I/O, L16N_YY
I/O, L16P_YY
VCCINT
4
4
-
P59
P60
P61
P62
P63
P64
P65
P66
All
All
-
-
VCCINT
I/O (TRDY)
VCCO
-
3
-
-
GND
-
-
-
GND
-
I/O, L15N_YY
I/O, L15P_YY
I/O
4
4
4
4
All
All
-
-
XC2S100E
I/O (IRDY)
I/O
2
2
2
2
P92
P93
-
-
-
-
-
I/O, VREF
Bank 4
-
All
I/O (D3), L9N
P94 XC2S50E
P95 XC2S50E
-
I/O, VREF
All
I/O
4
4
4
-
P67
P68
P69
P70
-
-
-
-
-
Bank 2, L9P
I/O, L14N_YY
I/O, L14P_YY
GND
All
All
-
I/O
2
2
2
P96
P97
P98
-
-
-
-
I/O, L8N_YY
All
All
I/O (D2),
L8P_YY
GND
-
P99
-
-
-
DONE
3
-
P71
P72
P73
P74
-
-
-
-
-
-
I/O (D1), L7N
I/O, L7P
I/O
2
2
2
2
P100 XC2S50E
VCCO
P101 XC2S50E XC2S100E
PROGRAM
-
-
P102
P103
-
-
-
I/O (INIT),
L13N_YY
3
All
I/O, VREF
Bank 2
All
I/O (D7),
3
P75
All
-
L13P_YY
I/O
2
2
P104
P105
-
-
-
I/O
3
3
P76
P77
-
-
-
I/O (DIN, D0),
L6N_YY
All
I/O, VREF
Bank 3
All
I/O (DOUT,
BUSY),
L6P_YY
2
P106
All
-
I/O
3
3
3
-
P78
-
-
I/O, L12N
I/O (D6), L12P
GND
P79 XC2S50E XC2S100E
CCLK
VCCO
TDO
GND
TDI
2
-
P107
P108
P109
P110
P111
-
-
-
-
-
-
-
-
-
-
P80 XC2S50E
-
-
-
P81
P82
-
2
-
I/O (D5),
L11N_YY
3
All
-
I/O, L11P_YY
I/O
3
3
P83
P84
All
-
-
-
DS077-4 (2.3) June 18, 2008
www.xilinx.com
59
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
TQ144 Pinouts (XC2S50E and XC2S100E)
(Continued)
TQ144 Pinouts (XC2S50E and XC2S100E)
(Continued)
Pad Name
LVDS
Async.
Output
Option
Pad Name
LVDS
Async.
Output
Option
VREF
Option
VREF
Option
Function
Bank
Pin
Function
Bank
Pin
I/O
0
0
P139
P140
-
-
-
I/O (CS),
L5P_YY
1
1
P112
P113
All
All
-
-
I/O, VREF
Bank 0
All
I/O (WRITE),
L5N_YY
I/O
0
0
-
P141
P142
P143
P144
-
-
-
-
-
-
-
-
I/O
I/O
1
1
P114
P115
-
-
-
TCK
VCCO
I/O, VREF
Bank 1
All
-
I/O
1
1
1
-
P116
P117
P118
P119
P120
P121
P122
P123
-
All
All
-
-
TQ144 Differential Clock Pins
I/O, L4P_YY
I/O, L4N_YY
GND
XC2S100E
P
N
-
-
Clock Bank
Pin
Name
Pin
Name
GCK0
GCK1
GCK2
GCK3
4
5
1
0
P55 GCK0, I
P56
I/O (DLL),
L17P
VCCINT
-
-
-
I/O, L3P_YY
I/O, L3N_YY
1
1
1
All
All
-
-
P52 GCK1, I
P50
I/O (DLL),
L17N
-
P126 GCK2, I P125
P129 GCK3, I P131
I/O (DLL),
L2P
I/O, VREF
Bank 1
All
I/O (DLL),
L2N
I/O
1
1
1
-
P124
P125
P126
P127
P128
-
-
-
-
-
-
-
-
-
-
I/O (DLL), L2P
GCK2, I
GND
VCCO
-
GCK3, I
0
-
P129
P130
P131
P132
-
-
-
-
-
-
VCCINT
I/O (DLL), L2N
0
0
-
I/O, VREF
Bank 0
All
I/O, L1P_YY
I/O, L1N_YY
VCCINT
0
0
-
P133
P134
P135
P136
P137
P138
All
All
-
-
-
-
GND
-
-
-
I/O, L0P_YY
I/O, L0N_YY
0
0
All
All
-
XC2S100E
60
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DS077-4 (2.3) June 18, 2008
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
In the PQ208 package, all VCCO pins must be connected to
the same voltage.
PQ208 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E)
Pad Name
LVDS
Async.
Output
Option
PQ208 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E)
VREF
Option
Pad Name
LVDS
Async.
Output
Option
Function
I/O
Bank
Pin
P22
P23
7
7
-
-
-
VREF
Function
GND
Bank
Pin
P1
P2
P3
P4
Option
I/O,
All
L44P_YY
-
-
-
-
-
-
-
-
-
I/O (IRDY),
L44N_YY
7
P24
All
-
TMS
I/O
7
7
GND
-
-
P25
P26
-
-
-
-
I/O
XC2S200E,
300E
VCCO
I/O
7
7
P5
P6
-
-
I/O (TRDY)
VCCINT
I/O
6
-
P27
P28
P29
P30
-
-
-
-
-
-
-
I/O, VREF
Bank 7,
L49P
XC2S50E,
150E, 200E,
300E
All
6
6
I/O, L49N
7
P7
XC2S50E,
150E, 200E,
300E
-
I/O, L43P
XC2S50E,
300E
I/O, VREF
Bank 6,
L43N
6
P31
XC2S50E,
300E
All
I/O
7
7
7
P8
P9
-
-
-
-
I/O
I/O, L48P
P10
XC2S50E, XC2S100E,
GND
-
P32
P33
-
-
-
300E
150E, 200E,
300E
I/O,
L42P_YY
6
All
I/O, L48N
7
P11
XC2S50E,
300E
-
I/O,
L42N_YY
6
6
6
P34
P35
P36
All
All
All
-
-
-
GND
-
-
P12
P13
P14
P15
-
-
-
-
-
-
I/O,
L41P_YY
VCCO
VCCINT
-
-
I/O,
L41N_YY
I/O,
7
All
L47P_YY
VCCINT
VCCO
-
-
P37
P38
P39
P40
-
-
-
-
-
-
-
I/O,
L47N_YY
7
7
7
P16
P17
P18
All
All
All
-
-
-
-
GND
-
I/O,
L46P_YY
I/O, L40P
6
XC2S50E,
300E
I/O,
L46N_YY
I/O, L40N
6
P41
XC2S50E, XC2S100E,
300E
150E, 200E,
300E
GND
-
P19
P20
-
I/O, VREF
Bank 7,
L45P
7
XC2S50E,
300E
All
I/O
I/O
I/O
6
6
6
P42
P43
P44
-
-
-
-
-
-
I/O, L45N
7
P21
XC2S50E,
300E
-
DS077-4 (2.3) June 18, 2008
www.xilinx.com
61
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
PQ208 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E)
PQ208 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E)
Pad Name
LVDS
Async.
Output
Option
Pad Name
LVDS
Async.
Output
Option
VREF
Option
VREF
Option
Function
Bank
Pin
Function
Bank
Pin
P66
P67
P68
I/O, VREF
Bank 6,
L39P
6
P45 XC2S100E,
150E
All
VCCO
-
-
-
-
-
-
-
VCCINT
I/O, L33N
5
XC2S50E,
100E, 200E,
300E
I/O, L39N
6
6
6
6
P46 XC2S100E,
150E
-
I/O
P47
P48
P49
-
XC2S200E,
300E
I/O, L33P
5
P69
P70
XC2S50E,
100E, 200E,
300E
-
I/O,
All
All
-
L38P_YY
I/O
5
5
-
-
-
I/O,
-
I/O, L32N
P71 XC2S100E,
150E
L38N_YY
M1
-
-
-
-
-
P50
P51
P52
P53
P54
-
-
-
-
-
-
-
-
-
-
GND
-
P72
-
-
GND
M0
I/O, VREF
Bank 5,
L32P
5
P73 XC2S100E,
150E
All
VCCO
M2
I/O
5
5
P74
P75
-
-
-
-
I/O (DLL),
L31N
I/O,
L37N_YY
5
5
5
P55
P56
P57
All
All
-
-
-
VCCINT
GCK1, I
VCCO
GND
-
5
-
P76
P77
P78
P79
-
-
-
-
-
-
-
-
I/O,
L37P_YY
I/O
XC2S200E,
300E
-
I/O
5
5
P58
P59
-
-
GCK0, I
4
4
P80
P81
-
-
-
-
I/O, VREF
Bank 5,
L36N_YY
All
All
I/O (DLL),
L31P
I/O
4
4
P82
P83
-
-
-
I/O,
L36P_YY
5
5
5
5
P60
P61
P62
P63
All
-
-
-
I/O, L30N
XC2S50E,
200E, 300E
I/O, L35N
I/O, L35P
I/O, L34N
XC2S50E,
100E, 300E
I/O, VREF
Bank 4,
L30P
4
P84
XC2S50E,
200E, 300E
All
XC2S50E,
100E, 300E
GND
-
P85
P86
-
-
-
XC2S50E, XC2S100E,
100E, 200E, 150E, 200E,
I/O, L29N
4
XC2S50E,
200E, 300E
300E
300E
I/O, L29P
I/O, L28N
4
4
P87
P88
XC2S50E,
200E, 300E
-
-
I/O, L34P
GND
5
-
P64
P65
XC2S50E,
100E, 200E,
300E
-
XC2S50E,
100E, 200E,
300E
-
-
62
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DS077-4 (2.3) June 18, 2008
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
PQ208 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E)
PQ208 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E)
Pad Name
LVDS
Async.
Output
Option
Pad Name
LVDS
Async.
Output
Option
VREF
Option
VREF
Option
Function
Bank
Pin
Function
Bank
Pin
I/O, L28P
4
P89
XC2S50E,
100E, 200E,
300E
-
I/O, VREF
Bank 3,
L23N
3
P111 XC2S50E,
150E, 200E,
300E
All
VCCINT
VCCO
-
-
P90
P91
P92
P93
-
-
-
-
-
-
-
I/O, L23P
3
P112 XC2S50E,
150E, 200E,
300E
-
GND
-
I/O
3
3
3
P113
P114
-
-
-
-
I/O, L27N
4
XC2S50E,
100E, 200E,
300E
I/O
I/O, L22N
P115 XC2S50E, XC2S100E,
300E
150E, 200E,
300E
I/O, L27P
4
P94
XC2S50E, XC2S100E,
100E, 200E, 150E, 200E,
300E
300E
I/O (D6),
L22P
3
P116 XC2S50E,
300E
-
I/O
I/O
4
4
4
P95
P96
P97
-
-
-
-
-
GND
-
-
P117
P118
P119
P120
-
-
-
-
-
-
VCCO
VCCINT
I/O,
All
L26N_YY
-
-
I/O, VREF
Bank 4,
4
P98
All
All
I/O (D5),
3
All
L21N_YY
L26P_YY
I/O,
L21P_YY
3
3
3
P121
P122
P123
P124
All
All
All
-
-
-
-
I/O
I/O
4
4
P99
-
-
-
P100
XC2S200E,
300E
I/O,
L20N_YY
I/O,
L25N_YY
4
4
-
P101
P102
P103
All
All
-
-
-
-
I/O,
L20P_YY
I/O,
L25P_YY
GND
-
-
I/O, VREF
Bank 3,
L19N
3
P125 XC2S50E,
300E
All
GND
I/O (D4),
L19P
3
P126 XC2S50E,
300E
-
DONE
3
-
P104
P105
P106
P107
-
-
-
-
-
-
VCCO
I/O
3
-
P127
P128
P129
P130
P131
-
-
-
-
-
-
-
-
-
-
PROGRAM
-
-
VCCINT
I/O (TRDY)
VCCO
GND
I/O (INIT),
L24N_YY
3
All
3
-
I/O (D7),
L24P_YY
3
3
3
P108
P109
P110
All
-
-
-
I/O
XC2S200E,
300E
I/O (IRDY),
L18N_YY
2
2
P132
P133
All
All
-
-
I/O
-
-
I/O,
L18P_YY
DS077-4 (2.3) June 18, 2008
www.xilinx.com
63
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
PQ208 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E)
PQ208 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E)
Pad Name
LVDS
Async.
Output
Option
Pad Name
LVDS
Async.
Output
Option
VREF
Option
VREF
Option
Function
I/O
Bank
Pin
Function
Bank
Pin
2
2
P134
-
-
-
VCCO
TDO
GND
TDI
-
2
-
P156
P157
P158
P159
-
-
-
-
-
-
-
-
I/O (D3),
L17N
P135 XC2S50E,
300E
I/O, VREF
Bank 2,
L17P
2
P136 XC2S50E,
300E
All
-
I/O (CS),
L11P_YY
1
1
P160
P161
All
All
-
-
GND
-
P137
P138
-
-
-
I/O,
L16N_YY
2
All
I/O
(WRITE),
L11N_YY
I/O,
L16P_YY
2
2
2
P139
P140
P141
All
All
All
-
-
-
I/O
1
P162
-
XC2S200E,
300E
I/O,
L15N_YY
I/O
1
1
P163
P164
-
-
I/O (D2),
L15P_YY
I/O, VREF
Bank 1,
L10P_YY
All
All
VCCINT
VCCO
GND
-
-
P142
P143
P144
-
-
-
-
-
-
-
I/O,
L10N_YY
1
P165
All
-
-
I/O (D1),
L14N
2
P145 XC2S50E,
300E
I/O
1
1
1
P166
P167
-
-
-
-
I/O
I/O, L14P
2
P146 XC2S50E, XC2S100E,
I/O, L9P
P168 XC2S50E, XC2S100E,
100E, 200E, 150E, 200E,
300E
150E, 200E,
300E
300E
300E
I/O
I/O
I/O
2
2
2
2
P147
P148
P149
-
-
-
-
-
I/O, L9N
1
P169 XC2S50E,
100E, 200E,
300E
-
-
GND
-
-
P170
P171
P172
-
-
-
-
-
-
-
I/O, VREF
Bank 2,
L13N
P150 XC2S100E,
150E
All
VCCO
VCCINT
I/O, L8P
-
I/O, L13P
2
2
2
P151 XC2S100E,
150E
-
1
P173 XC2S50E,
100E, 200E,
300E
I/O
P152
-
XC2S200E,
300E
I/O, L8N
1
P174 XC2S50E,
100E, 200E,
300E
-
I/O (DIN,
D0),
L12N_YY
P153
All
-
-
-
I/O, L7P
I/O, L7N
GND
1
1
-
P175 XC2S50E,
200E, 300E
-
-
-
I/O (DOUT,
BUSY),
L12P_YY
2
2
P154
P155
All
-
P176 XC2S50E,
200E, 300E
CCLK
P177
-
64
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DS077-4 (2.3) June 18, 2008
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
PQ208 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E)
PQ208 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E)
Pad Name
LVDS
Async.
Output
Option
Pad Name
LVDS
Async.
Output
Option
VREF
Option
VREF
Option
Function
Bank
Pin
Function
I/O
Bank
Pin
I/O, VREF
Bank 1, L6P
1
P178 XC2S50E,
200E, 300E
All
-
0
0
P201
P202
-
-
-
I/O,
All
I/O, L6N
1
P179 XC2S50E,
200E, 300E
L0P_YY
I/O, VREF
Bank 0,
L0N_YY
0
P203
All
All
I/O
1
1
P180
P181
-
-
-
-
I/O (DLL),
L5P
I/O
I/O
0
0
P204
P205
-
-
-
GCK2, I
GND
1
-
P182
P183
P184
-
-
-
-
-
-
XC2S200E,
300E
I/O
0
-
P206
P207
P208
-
-
-
-
-
-
VCCO
-
TCK
VCCO
-
GCK3, I
VCCINT
0
-
P185
P186
P187
-
-
-
-
-
-
PQ208 Differential Clock Pins
I/O (DLL),
L5N
0
P
N
Clock Bank
Pin
Name
Pin
Name
I/O, L4P
0
0
P188 XC2S50E,
200E, 300E
-
GCK0
GCK1
GCK2
GCK3
4
5
1
0
P80 GCK0, I
P81
I/O (DLL),
L31P
I/O, VREF
Bank 0, L4N
P189 XC2S50E,
200E, 300E
All
P77 GCK1, I
P75
I/O (DLL),
L31N
GND
-
P190
-
-
-
P182 GCK2, I P181
P185 GCK3, I P187
I/O (DLL),
L5P
I/O, L3P
0
P191 XC2S50E,
200E, 300E
I/O (DLL),
L5N
I/O, L3N
I/O, L2P
0
0
P192 XC2S50E,
200E, 300E
-
-
P193 XC2S50E,
100E, 200E,
300E
I/O, L2N
0
P194 XC2S50E,
100E, 200E,
300E
-
VCCINT
VCCO
GND
-
-
P195
P196
P197
-
-
-
-
-
-
-
-
I/O, L1P
0
P198 XC2S50E,
100E, 200E,
300E
I/O, L1N
I/O
0
0
P199 XC2S50E, XC2S100E,
100E, 200E, 150E, 200E,
300E
300E
P200
-
-
DS077-4 (2.3) June 18, 2008
www.xilinx.com
65
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
FT256 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E, XC2S400E)
(Continued)
FT256 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E,
XC2S400E)
Pad Name
LVDS
Async.
Output
Option
Pad Name
LVDS
Async.
Output
Option
VREF
Option
Function
I/O, L74P
Bank Pin
VREF
Option
Function
TMS
I/O
Bank Pin
7
H4
XC2S100E,
150E, 200E
-
-
B1
D3
C2
-
-
-
-
-
I/O, L74N
7
H3
XC2S100E, XC2S400E
150E, 200E
7
7
I/O, L83P
XC2S100E,
150E
I/O, L73P_YY
7
7
H2
H1
All
All
-
-
I/O (IRDY),
L73N_YY
I/O, L83N
7
C1
XC2S100E, XC2S200E,
150E
300E, 400E
I/O, L82P_YY
I/O, L82N_YY
7
7
7
D2
D1
E3
All
-
-
I/O (TRDY)
I/O, L72P
6
6
J4
J2
-
-
All
XC2S100E, XC2S400E
150E, 200E,
I/O, VREF
Bank 7, L81P
XC2S50E,
150E,200E,
300E, 400E
All
400E
I/O, L72N
I/O, L71P
6
J3
XC2S100E,
150E, 200E,
400E
-
I/O, L81N
7
E4
XC2S50E,
150E,200E,
300E, 400E
-
6
6
J1
XC2S50E,
300E, 400E
-
I/O, L80P
I/O, L80N
I/O, L79P
7
7
7
E2
E1
F4
XC2S200E,
400E
-
-
I/O, VREF
Bank 6, L71N
K1
XC2S50E,
300E, 400E
All
XC2S200E,
400E
I/O, L70P_YY
I/O, L70N_YY
I/O, L69P
6
6
6
K2
K3
L1
All
All
-
-
-
XC2S50E, XC2S100E,
300E, 400E 150E,200E,
300E, 400E
XC2S100E,
150E, 400E
I/O, L79N
7
F3
XC2S50E,
300E, 400E
-
I/O, L69N
6
L2
XC2S100E,
150E, 400E
-
I/O, L78P_YY
I/O, L78N_YY
I/O, L77P
7
7
7
F2
F1
F5
All
All
-
-
-
I/O, L68P_YY
I/O, L68N_YY
I/O, L67P
6
6
6
K4
K5
L3
All
All
-
-
-
XC2S100E,
150E
XC2S50E,
300E, 400E
I/O, L77N
7
G5 XC2S100E,
150E
-
I/O, L67N
6
M2
XC2S50E, XC2S100E,
300E, 400E 150E,200E,
300E, 400E
I/O, L76P_YY
I/O, L76N_YY
7
7
7
G3
G4
G2
All
All
-
-
I/O, L66P
I/O, L66N
6
6
M1 XC2S150E,
200E, 400E
-
I/O, VREF
Bank 7, L75P
XC2S50E,
300E, 400E
All
N1
XC2S150E,
200E, 400E
-
I/O, L75N
7
G1
XC2S50E,
300E, 400E
-
66
www.xilinx.com
DS077-4 (2.3) June 18, 2008
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
FT256 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E, XC2S400E)
(Continued)
FT256 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E, XC2S400E)
(Continued)
Pad Name
LVDS
Async.
Output
Option
Pad Name
LVDS
Async.
Output
Option
VREF
Option
VREF
Option
Function
I/O, L65P
Bank Pin
Function
I/O, L57P
Bank Pin
6
L4
XC2S50E,
150E,200E,
300E, 400E
-
5
5
5
5
5
P6
R6
T6
XC2S50E,
100E, 150E,
300E
-
I/O, VREF
Bank 6, L65N
6
L5
XC2S50E,
150E,200E,
300E, 400E
All
I/O, L56N
I/O, L56P
I/O, L55N
I/O, L55P
XC2S50E, XC2S100E,
100E, 200E, 150E,200E,
300E, 400E 300E, 400E
I/O, L64P_YY
I/O, L64N_YY
I/O, L63P
6
6
6
M3
M4
N2
All
All
-
-
-
XC2S50E,
100E, 200E,
300E, 400E
-
-
-
XC2S100E,
200E, 300E
M6
N7
XC2S50E,
100E, 200E,
300E, 400E
I/O, L63N
6
N3
XC2S100E, XC2S200E,
200E, 300E 300E, 400E
XC2S50E,
100E, 200E,
300E, 400E
I/O, L62P_YY
6
6
-
P1
P2
R1
T2
R3
All
All
-
-
-
-
-
-
I/O, L62N_YY
I/O
5
5
P7
R7
-
-
-
M1
M0
M2
I/O, L54N
XC2S50E,
200E, 300E,
400E
-
-
-
-
I/O, L54P
5
5
5
T7
M7
N8
XC2S50E,
200E, 300E,
400E
-
All
-
I/O, L61N_YY
I/O, L61P_YY
I/O, L60N
5
5
5
P4
R4
T3
All
All
-
-
I/O, VREF
Bank 5, L53N
XC2S50E,
200E, 300E,
400E
XC2S50E, XC2S200E,
100E,200E, 300E, 400E
300E, 400E
I/O, L53P
XC2S50E,
200E, 300E,
400E
I/O, L60P
5
T4
XC2S50E,
100E,200E,
300E, 400E
-
I/O
5
5
P8
R8
-
-
XC2S400E
-
I/O, L59N_YY
I/O, L59P_YY
5
5
5
N5
P5
R5
All
All
All
-
-
I/O (DLL),
L52N
I/O, VREF
Bank 5,
All
GCK1, I
5
T8
-
-
L58N_YY
GCK0, I
4
4
T9
-
-
-
-
I/O, L58P_YY
I/O, L57N
5
5
T5
N6
All
-
-
I/O (DLL),
L52P
R9
XC2S50E,
100E,150E,
300E
I/O, L51N
4
P9
XC2S50E, XC2S400E
150E, 200E,
400E
DS077-4 (2.3) June 18, 2008
www.xilinx.com
67
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
FT256 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E, XC2S400E)
(Continued)
FT256 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E, XC2S400E)
(Continued)
Pad Name
LVDS
Async.
Output
Option
Pad Name
LVDS
Async.
Output
Option
VREF
Option
VREF
Option
Function
I/O, L51P
Bank Pin
Function
I/O, L43N
Bank Pin
4
N9
XC2S50E,
150E,200E,
400E
-
4
R13
XC2S50E, XC2S200E,
150E
300E, 400E
I/O, L43P
4
P13
XC2S50E,
150E
-
I/O, L50N
4
T10
XC2S50E,
200E,300E,
400E
-
I/O, L42N_YY
I/O, L42P_YY
4
4
T14
R14
All
All
-
-
XC2S50E,
200E, 300E,
400E
I/O, VREF
Bank 4, L50P
4
4
R10
P10
All
-
DONE
3
-
T15
R16
P15
-
-
-
-
-
I/O, L49N
I/O, L49P
XC2S50E,
200E,300E,
400E
PROGRAM
I/O (INIT),
L41N_YY
3
All
4
R11
XC2S50E,
200E,300E,
400E
-
I/O (D7),
L41P_YY
3
3
3
3
P16
All
-
-
I/O
4
4
T11
N10
-
-
-
I/O, L40N
I/O, L40P
I/O, L39N
N15 XC2S100E,
150E, 400E
I/O, L48N
XC2S50E,
100E,200E,
300E, 400E
N16 XC2S100E, XC2S200E,
150E, 400E 300E, 400E
I/O, L48P
I/O, L47N
I/O, L47P
I/O, L46N
I/O, L46P
I/O, L45N_YY
4
4
4
4
4
M10 XC2S50E,
100E,200E,
-
-
N14
XC2S50E,
100E, 150E,
200E,
-
300E, 400E
300E(1)
P11
R12
T12
T13
XC2S50E,
100E,200E,
300E, 400E
I/O, L39P
3
M14 XC2S50E,
100E, 150E,
200E,
-
XC2S50E, XC2S100E,
100E,200E, 150E,200E,
300E, 400E 300E, 400E
300E(1)
I/O, VREF
Bank 3, L38N
3
3
M15 XC2S50E,
150E, 200E,
All
-
XC2S50E,
100E,150E,
300E
-
300E, 400E
I/O, L38P
M16 XC2S50E,
150E, 200E,
XC2S50E,
100E,150E,
300E
-
300E, 400E
I/O(2)
3
3
3
M13
L14
L15
-
-
-
-
4
4
N11
M11
All
All
-
I/O(2)
I/O, VREF
Bank 4,
L45P_YY
All
I/O, L36N
XC2S50E, XC2S100E,
300E, 400E 150E,200E,
300E, 400E
I/O, L44N_YY
I/O, L44P_YY
4
4
P12
N12
All
All
-
-
I/O (D6), L36P
3
L16
XC2S50E,
300E, 400E
-
68
www.xilinx.com
DS077-4 (2.3) June 18, 2008
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
FT256 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E, XC2S400E)
(Continued)
FT256 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E, XC2S400E)
(Continued)
Pad Name
LVDS
Async.
Output
Option
Pad Name
LVDS
Async.
Output
Option
VREF
Option
VREF
Option
Function
I/O (D5),
Bank Pin
Function
Bank Pin
3
L13
All
-
I/O, VREF
2
F16
XC2S50E,
All
-
L35N_YY
Bank 2, L28P
300E, 400E
I/O, L35P_YY
I/O, L34N
3
3
K14
All
-
-
I/O, L27N
2
H13
XC2S50E,
100E, 150E,
200E,
K15 XC2S100E,
150E, 400E
300E(1)
I/O, L34P
I/O, L33N
3
3
K16 XC2S100E,
150E, 400E
-
-
I/O, L27P
2
G14 XC2S50E,
100E, 150E,
200E,
-
L12
K12
XC2S50E,
100E,150E,
200E,
300E(2)
I/O, L26N
2
2
F15 XC2S100E,
150E, 400E
-
-
300E(1)
I/O, L33P
3
XC2S50E,
100E,150E,
200E,
-
I/O, L26P
E16 XC2S100E,
150E, 400E
300E(1)
I/O, L25N_YY
2
2
G13
F14
All
All
-
-
I/O, VREF
Bank 3, L32N
3
3
3
K13
J14
XC2S50E,
300E, 400E
All
-
I/O (D2),
L25P_YY
I/O (D4), L32P
I/O, L31N
XC2S50E,
I/O (D1), L24N
I/O, L24P
2
2
E15
D16
XC2S50E,
300E, 400E
-
300E, 400E
J15 XC2S100E,
150E,200E,
400E
-
XC2S50E, XC2S100E,
300E, 400E 150E,200E,
300E, 400E
I/O, L31P
3
J16 XC2S100E, XC2S400E
I/O, L23N
I/O, L23P
I/O, L22N
2
2
2
F13 XC2S150E,
200E, 400E
-
-
-
150E,200E,
400E
E14 XC2S150E,
200E, 400E
I/O (TRDY)
3
2
J13
-
-
D15
XC2S50E,
150E, 200E,
300E, 400E
I/O (IRDY),
L30N_YY
H16
G16
All
All
-
-
I/O, VREF
Bank 2, L22P
2
2
2
2
C16
XC2S50E,
150E, 200E,
300E, 400E
All
-
I/O, L30P_YY
I/O, L29N
2
2
H14 XC2S100E, XC2S400E
150E,200E,
400E
I/O, L21N
I/O, L21P
I/O, L20N
G12 XC2S50E,
100E, 200E,
300E
I/O, L29P
2
2
H15 XC2S100E,
150E,200E,
400E
-
-
F12
XC2S50E,
100E, 200E,
300E
-
I/O (D3), L28N
G15
XC2S50E,
300E, 400E
E13 XC2S100E,
200E, 300E
-
DS077-4 (2.3) June 18, 2008
www.xilinx.com
69
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
FT256 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E, XC2S400E)
(Continued)
FT256 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E, XC2S400E)
(Continued)
Pad Name
LVDS
Async.
Output
Option
Pad Name
LVDS
Async.
Output
Option
VREF
Option
VREF
Option
Function
I/O, L20P
Bank Pin
Function
I/O, L12P
Bank Pin
2
2
2
D14 XC2S100E, XC2S200E,
200E, 300E 300E, 400E
1
E10
XC2S50E,
100E, 200E,
300E, 400E
-
I/O (DIN, D0),
L19N_YY
B16
All
-
I/O, L12N
1
D10
XC2S50E,
100E, 200E,
300E, 400E
-
I/O (DOUT,
BUSY),
C15
All
-
L19P_YY
I/O
1
1
C10
B10
-
-
-
CCLK
TDO
TDI
2
2
-
A15
B14
C13
-
-
-
-
-
-
I/O, L11P
XC2S50E,
200E, 300E,
400E
I/O, L11N
1
1
1
1
1
A10
D9
C9
B9
XC2S50E,
200E, 300E,
400E
-
All
-
I/O (CS),
L18P_YY
1
1
1
A14
A13
B13
All
All
-
-
I/O, VREF
Bank 1, L10P
XC2S50E,
200E, 300E,
400E
I/O (WRITE),
L18N_YY
I/O, L10N
I/O, L9P
I/O, L9N
XC2S50E,
200E, 300E,
400E
I/O, L17P
XC2S50E, XC2S200E,
100E,200E, 300E, 400E
300E, 400E
XC2S50E,
150E, 200E,
400E
-
I/O, L17N
1
C12
XC2S50E,
100E,200E,
300E, 400E
-
A9
XC2S50E, XC2S400E
150E, 200E,
I/O, L16P_YY
I/O, L16N_YY
1
1
1
B12
A12
D12
All
All
All
-
-
400E
I/O, VREF
Bank 1,
L15P_YY
All
I/O (DLL), L8P
GCK2, I
1
1
A8
B8
-
-
-
-
I/O, L15N_YY
I/O, L14P
1
1
E11
D11
All
-
-
GCK3, I
I/O (DLL), L8N
I/O
0
0
0
0
C8
D8
A7
E7
-
-
-
-
XC2S50E,
100E,150E,
300E
-
XC2S400E
-
I/O, L14N
I/O, L13P
I/O, L13N
1
1
1
C11
B11
A11
XC2S50E,
100E,150E,
300E
-
I/O, L7P
XC2S50E,
200E, 300E,
400E
XC2S50E, XC2S100E,
100E,200E, 150E,200E,
300E, 400E 300E, 400E
I/O, VREF
Bank 0, L7N
0
D7
XC2S50E,
200E, 300E,
400E
All
XC2S50E,
100E,200E,
300E, 400E
-
70
www.xilinx.com
DS077-4 (2.3) June 18, 2008
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
FT256 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E, XC2S400E)
(Continued)
FT256 Differential Clock Pins
P
N
Pad Name
LVDS
Async.
Output
Option
Clock Bank
Pin
Name
Pin
Name
GCK0
GCK1
GCK2
GCK3
4
5
1
0
T9
GCK0, I
GCK1, I
GCK2, I
GCK3, I
R9
I/O (DLL),
L52P
VREF
Option
Function
I/O, L6P
Bank Pin
T8
B8
C8
R8
A8
D8
I/O (DLL),
L52N
0
C7
XC2S50E,
200E,300E,
400E
-
I/O (DLL),
L8P
I/O, L6N
0
B7
XC2S50E,
200E,300E,
400E
-
I/O (DLL),
L8N
I/O
0
0
A6
B6
-
-
-
I/O, L5P
XC2S50E,
100E,200E,
300E, 400E
Additional FT256 Package Pins
VCCINT Pins
I/O, L5N
I/O, L4P
I/O, L4N
0
0
0
C6
A5
B5
XC2S50E,
100E,200E,
300E, 400E
-
-
C3
C14
M5
D4
M12
-
D13
N4
-
E5
N13
-
E12
P3
P14
XC2S50E,
100E,200E,
300E, 400E
VCCO Bank 0 Pins
E8
F7
F8
-
-
-
-
-
-
-
-
-
-
XC2S50E, XC2S100E,
100E,200E, 150E,200E,
300E, 400E 300E, 400E
VCCO Bank 1 Pins
E9
F9
F10
H12
K11
M9
I/O, L3P
0
0
D6
E6
XC2S50E,
100E, 300E
-
VCCO Bank 2 Pins
G11
H11
I/O, L3N
XC2S50E,
100E, 300E
-
VCCO Bank 3 Pins
J11
J12
I/O, L2P_YY
0
0
D5
C5
All
All
-
VCCO Bank 4 Pins
I/O, VREF
Bank 0,
All
L9
L10
L2N_YY
I/O, L1P_YY
I/O, L1N_YY
I/O, L0P_YY
I/O, L0N_YY
0
0
0
0
B4
C4
A4
A3
All
All
All
All
-
-
-
XC2S200E,
300E, 400E
I/O
0
-
B3
A2
-
-
-
-
TCK
Notes:
1. Although designated with the _YY suffix in the XC2S50E,
XC2S100E, XC2S150E, XC2S200E, and XC2S300E, these
differential pairs are not asynchronous in the XC2S400E.
2. There is no pair L37.
DS077-4 (2.3) June 18, 2008
www.xilinx.com
71
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
Additional FT256 Package Pins (Continued)
VCCO Bank 5 Pins
L7
L8
M8
K6
H6
-
-
-
-
-
-
VCCO Bank 6 Pins
J5
J6
VCCO Bank 7 Pins
G6
H5
GND Pins
A1
A16
G7
H8
J9
B2
G8
H9
B15
G9
H10
K7
F6
G10
J7
F11
H7
J8
J10
L6
K8
R2
-
K9
K10
T1
L11
-
R15
T16
72
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DS077-4 (2.3) June 18, 2008
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
FG456 Pinouts (XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E, XC2S600E)
Pad Name
LVDS
Async.
Output
Option
Device-Specific Pinouts: XC2S
VREF
Option
Function Bank Pin
100E
TMS
I/O
150E
200E
TMS
I/O
300E
TMS
I/O
400E
TMS
I/O
600E
TMS
I/O
TMS
I/O
-
E4
D3
-
-
-
TMS
7
XC2S150E
I/O,
L113P_Y
I/O
I/O
7
7
C2
C1
-
-
-
-
-
-
-
I/O
I/O
I/O
I/O
I/O
I/O
XC2S150E
I/O,
I/O
L113N_Y
I/O, L#P_Y
I/O, L#N_Y
I/O, L#P_Y
I/O, L#N_Y
7
7
7
7
D2
D1
E2
E3
XC2S150E,
200E, 300E,
400E
-
-
-
I/O,
L112P_Y
I/O,
L119P_Y
I/O,
L119P_Y
I/O,
L119P_Y
I/O, L119P
I/O, L119N
XC2S150E,
200E, 300E,
400E
I/O
I/O,
L112N_Y
I/O,
L119N_Y
I/O,
L119N_Y
I/O,
L119N_Y
XC2S100E, XC2S200E, I/O, L85P_Y I/O, L111P I/O, VREF I/O, VREF
200E, 300E,
600E
I/O, VREF
Bank 7,
L118P
I/O, VREF
Bank 7,
L118P_Y
300E,
400E, 600E
Bank 7,
L118P_Y
Bank 7,
L118P_Y
XC2S100E,
200E, 300E,
600E
-
I/O,
L85N_Y
I/O, L111N
I/O,
L118N_Y
I/O,
L118N_Y
I/O, L118N
I/O,
L118N_Y
I/O
7
7
7
E1
F5
F4
-
-
-
-
-
-
-
-
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O, L#P_Y
XC2S100E,
200E, 300E,
600E
I/O, L84P_Y I/O, L110P
I/O,
L117P_Y
I/O,
L117P_Y
I/O, L117P
I/O,
L117P_Y
I/O, L#N_Y
7
7
7
F3
F2
F1
XC2S100E,
200E, 300E,
600E
-
All
-
I/O,
L84N_Y
I/O, L110N
I/O,
L117N_Y
I/O,
L117N_Y
I/O, L117N
I/O,
L117N_Y
I/O, VREF
Bank 7,
L#P_Y
XC2S150E,
200E, 300E,
400E, 600E
I/O, VREF I/O, VREF I/O, VREF I/O, VREF
Bank 7,
L83P
I/O, VREF
Bank 7,
L116P_Y
I/O, VREF
Bank 7,
L116P_Y
Bank 7,
L109P_Y
Bank 7,
L116P_Y
Bank 7,
L116P_Y
I/O, L#N_Y
XC2S150E,
200E, 300E,
400E, 600E
I/O, L83N
I/O,
L109N_Y
I/O,
L116N_Y
I/O,
L116N_Y
I/O,
L116N_Y
I/O,
L116N_Y
I/O
7
7
G5
G4
-
-
-
-
-
I/O
I/O
I/O
I/O
I/O
I/O, L#P_Y
XC2S150E,
200E, 300E,
400E
I/O,
L108P_Y
I/O,
L115P_Y
I/O,
L115P_Y
I/O,
L115P_Y
I/O, L115P
I/O, L#N_Y
I/O, L#P_Y
I/O, L#N_Y
7
7
7
G3
G2
G1
XC2S150E,
200E, 300E,
400E
-
I/O
I/O,
L108N_Y
I/O,
L115N_Y
I/O,
L115N_Y
I/O,
L115N_Y
I/O, L115N
XC2S100E, XC2S600E I/O, L82P_Y
150E, 300E,
600E
I/O,
L107P_Y
I/O, L114P
I/O, L114N
I/O,
L114P_Y
I/O, L114P I/O, VREF
Bank 7,
L114P_Y
XC2S100E,
150E, 300E,
600E
-
I/O,
L82N_Y
I/O,
L107N_Y
I/O,
L114N_Y
I/O, L114N
I/O,
L114N_Y
DS077-4 (2.3) June 18, 2008
www.xilinx.com
73
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
FG456 Pinouts (XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E, XC2S600E)
Pad Name
LVDS
Async.
Output
Option
Device-Specific Pinouts: XC2S
VREF
Option
Function Bank Pin
100E
150E
200E
300E
400E
600E
I/O
7
7
H5
H3
-
-
-
-
-
I/O
I/O
I/O
I/O, VREF
Bank 7,
L#P_Y
XC2S300E,
400E, 600E
All
I/O, VREF I/O, VREF I/O, VREF I/O, VREF
Bank 7,
L81P
I/O, VREF
Bank 7,
L113P_Y
I/O, VREF
Bank 7,
L113P_Y
Bank 7,
L106P
Bank 7,
L113P
Bank 7,
L113P_Y
I/O, L#N_Y
7
7
7
H4
H2
H1
XC2S300E,
400E, 600E
-
-
-
I/O, L81N
I/O, L106N I/O, L113N
I/O,
L113N_Y
I/O,
L113N_Y
I/O,
L113N_Y
I/O,
L#P_YY
All
All
-
I/O,
L80P_YY
I/O, I/O,
L105P_YY L112P_YY L112P_YY L112P_YY L112P_YY
I/O,
I/O,
I/O,
I/O,
L#N_YY
I/O,
I/O, I/O, I/O, I/O, I/O,
L80N_YY L105N_YY L112N_YY L112N_YY L112N_YY L112N_YY
I/O
7
7
J6
J4
-
-
-
-
-
I/O
I/O
I/O
I/O
I/O, L#P_Y
XC2S150E,
200E, 300E,
400E
I/O,
I/O,
I/O,
L111P_Y
I/O,
L111P_Y
I/O, L111P
L104P_Y
L111P_Y
I/O, L#N_Y
I/O, L#P_Y
I/O, L#N_Y
7
7
7
J5
J3
J2
XC2S100E,
150E, 200E,
300E, 400E
-
-
-
I/O, L79P_Y
I/O,
L104N_Y
I/O,
L111N_Y
I/O,
L111N_Y
I/O,
L111N_Y
I/O, L111N
XC2S100E,
150E, 200E,
300E, 600E
I/O,
L79N_Y
I/O,
L103P_Y
I/O,
L110P_Y
I/O,
L110P_Y
I/O, L110P
I/O, L110N
I/O,
L110P_Y
XC2S150E,
200E, 300E,
600E
-
I/O,
L103N_Y
I/O,
L110N_Y
I/O,
L110N_Y
I/O,
L110N_Y
I/O
7
7
J1
-
-
-
-
-
I/O
I/O
I/O
I/O
I/O, L#P
K5
XC2S100E,
150E, 200E,
300E,
600E(1)
I/O,
L78P_YY
I/O,
I/O,
I/O,
I/O, L109P
I/O,
L109P_Y
L102P_YY L109P_YY L109P_YY
I/O, L#N
7
K6
XC2S100E,
150E, 200E,
300E,
600E(1)
-
I/O,
I/O,
I/O,
I/O,
I/O, L109N
I/O,
L109N_Y
L78N_YY L102N_YY L109N_YY L109N_YY
I/O, VREF
Bank 7,
L#P_Y
7
7
K3
K4
XC2S300E,
400E, 600E
All
-
I/O, VREF I/O, VREF I/O, VREF I/O, VREF
I/O, VREF
Bank 7,
L108P_Y
I/O, VREF
Bank 7,
L108P_Y
Bank 7,
L77P
Bank 7,
L101P
Bank 7,
L108P
Bank 7,
L108P_Y
I/O, L#N_Y
XC2S300E,
400E, 600E
I/O, L77N
I/O, L101N I/O, L108N
I/O,
I/O,
L108N_Y
I/O,
L108N_Y
L108N_Y
I/O
7
7
K2
K1
-
-
-
-
-
-
-
-
I/O
I/O
I/O
I/O, L#P_Y
XC2S300E,
400E
I/O, L107P
I/O,
L107P_Y
I/O,
L107P_Y
I/O, L107P
I/O, L#N_Y
I/O, L#P_Y
7
7
L1
L3
XC2S100E,
150E, 300E,
400E
-
I/O, L76P_Y
I/O,
L100P_Y
I/O, L107N
I/O,
L107N_Y
I/O,
L107N_Y
I/O, L107N
XC2S100E, XC2S400E,
150E, 200E,
300E, 600E
I/O,
L76N_Y
I/O,
L100N_Y
I/O,
L106P_Y
I/O,
L106P_Y
I/O, VREF
Bank 7,
L106P
I/O, VREF
Bank 7,
L106P_Y
600E
I/O, L#N_Y
I/O
7
7
L2
L4
XC2S200E,
300E, 600E
-
-
-
-
I/O
-
I/O,
L106N_Y
I/O,
L106N_Y
I/O, L106N
I/O,
L106N_Y
-
-
I/O
I/O
I/O
74
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DS077-4 (2.3) June 18, 2008
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
FG456 Pinouts (XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E, XC2S600E)
Pad Name
LVDS
Async.
Output
Option
Device-Specific Pinouts: XC2S
VREF
Option
Function Bank Pin
100E
150E
200E
300E
400E
600E
I/O,
7
L5
All
-
I/O,
I/O,
I/O,
I/O,
I/O,
I/O,
L#P_YY
L75P_YY
L99P_YY
L105P_YY L105P_YY L105P_YY L105P_YY
I/O (IRDY),
L#N_YY
7
L6
All
-
I/O (IRDY), I/O (IRDY), I/O (IRDY), I/O (IRDY), I/O (IRDY), I/O (IRDY),
L75N_YY L99N_YY L105N_YY L105N_YY L105N_YY L105N_YY
I/O (TRDY)
I/O
6
6
6
M1
M2
M3
-
-
-
-
-
I/O (TRDY) I/O (TRDY) I/O (TRDY) I/O (TRDY) I/O (TRDY) I/O (TRDY)
-
-
-
-
I/O
I/O
I/O
I/O, L#P_Y
XC2S200E,
300E, 600E
I/O
I/O,
I/O,
I/O, L104P
I/O,
L104P_Y
L104P_Y
L104P_Y
I/O, L#N_Y
I/O, L#P_Y
I/O, L#N_Y
6
6
6
M4
M5
M6
XC2S100E, XC2S400E, I/O, L74P_Y I/O, L98P_Y
I/O,
L104N_Y
I/O,
L104N_Y
I/O, VREF
Bank 6,
L104N
I/O, VREF
Bank 6,
L104N_Y
150E, 200E,
300E, 600E
600E
XC2S100E,
150E, 300E,
400E
-
I/O,
L74N_Y
I/O,
L98N_Y
I/O, L103P
I/O, L103N
I/O,
L103P_Y
I/O,
L103P_Y
I/O, L103P
XC2S300E,
400E
-
-
-
I/O,
L103N_Y
I/O,
L103N_Y
I/O, L103N
I/O
I/O
6
6
6
N1
N2
N3
-
-
-
-
-
-
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O, L73P
I/O, L97P
I/O
I/O, VREF
Bank 6,
L#P
XC2S200E,
400E
All
I/O, VREF I/O, VREF I/O, VREF I/O, VREF
Bank 6,
L73N
I/O, VREF
Bank 6,
L102P_Y
I/O, VREF
Bank 6,
L102P
Bank 6,
L97N
Bank 6,
L102P_Y
Bank 6,
L102P
I/O, L#N
6
6
N4
N5
XC2S100E,
150E, 200E,
400E
-
-
I/O, L72P_Y I/O, L96P_Y
I/O,
L102N_Y
I/O, L102N
I/O,
L102N_Y
I/O, L102N
I/O, L#P_Y
XC2S100E,
150E, 300E,
600E
I/O,
I/O,
I/O, L101P
I/O, L101N
I/O,
L101P_Y
I/O, L101P
I/O,
L101P_Y
L72N_Y
L96N_Y
I/O, L#N_Y
I/O, L#P_Y
6
6
N6
P1
XC2S300E,
600E
-
-
-
-
-
I/O,
L101N_Y
I/O, L101N
I/O, L100P
I/O,
L101N_Y
XC2S150E,
200E, 300E,
600E
I/O, L95P_Y
I/O,
L100P_Y
I/O,
L100P_Y
I/O,
L100P_Y
I/O, L#N_Y
6
P2
XC2S100E,
150E, 200E,
300E, 600E
-
I/O, L71P_Y
I/O,
L95N_Y
I/O,
L100N_Y
I/O,
L100N_Y
I/O, L100N
I/O
I/O,
L100N_Y
I/O
6
6
R1
P3
XC2S100E,
150E
-
-
I/O,
L71N_Y
I/O, L94P_Y
I/O
I/O
I/O
I/O, L#P_Y
XC2S150E,
200E, 300E,
400E, 600E
-
I/O,
L94N_Y
I/O, L99P_Y I/O, L99P_Y I/O,L99P_Y I/O,L99P_Y
I/O, L#N_Y
6
P4
XC2S200E,
300E, 400E,
600E
-
-
-
I/O,
L99N_Y
I/O,
L99N_Y
I/O,
L99N_Y
I/O,
L99N_Y
I/O,
L#P_YY
6
6
P5
P6
All
-
-
I/O,
L70P_YY
I/O,
L93P_YY
I/O,
L98P_YY
I/O,
L98P_YY
I/O,
L98P_YY
I/O,
L98P_YY
I/O,
All
I/O,
I/O,
I/O,
I/O,
I/O,
I/O,
L#N_YY
L70N_YY
L93N_YY
L98N_YY
L98N_YY
L98N_YY
L98N_YY
DS077-4 (2.3) June 18, 2008
www.xilinx.com
75
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
FG456 Pinouts (XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E, XC2S600E)
Pad Name
LVDS
Async.
Output
Option
Device-Specific Pinouts: XC2S
VREF
Option
Function Bank Pin
100E
150E
200E
300E
400E
600E
I/O, L#P_Y
6
R2
XC2S300E,
400E, 600E
-
I/O, L69P
I/O, L92P
I/O, L97P I/O, L97P_Y I/O,L97P_Y I/O,L97P_Y
I/O, VREF
Bank 6,
L#N_Y
6
R3
XC2S300E,
400E, 600E
All
I/O, VREF I/O, VREF I/O, VREF I/O, VREF
I/O, VREF
Bank 6,
L97N_Y
I/O, VREF
Bank 6,
L97N_Y
Bank 6,
L69N
Bank 6,
L92N
Bank 6,
L97N
Bank 6,
L97N_Y
I/O
6
6
6
R4
R5
T2
-
-
-
-
-
-
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O, L#P
XC2S200E, XC2S600E I/O, L68P
400E, 600E
I/O, L91P I/O, L96P_Y I/O, L96P I/O, L96P_Y I/O, VREF
Bank 6,
L96P_Y
I/O, L#N
6
6
6
6
T3
T4
T5
T1
XC2S200E,
400E, 600E
-
-
-
-
I/O, L68N
I/O, L91N
I/O,
L96N_Y
I/O, L96N
I/O,
L96N_Y
I/O,
L96N_Y
I/O, L#P_Y
I/O, L#N_Y
I/O, L#P_Y
XC2S150E,
300E, 400E
-
-
I/O, L90P_Y I/O, L95P I/O, L95P_Y I/O,L95P_Y I/O, L95P
XC2S150E,
300E, 400E
I/O,
L90N_Y
I/O, L95N
I/O,
L95N_Y
I/O,
L95N_Y
I/O, L95N
XC2S150E,
200E, 300E,
400E, 600E
I/O, L67P I/O, L89P_Y I/O, L94P_Y I/O, L94P_Y I/O,L94P_Y I/O,L94P_Y
I/O, VREF
Bank 6,
L#N_Y
6
U1
XC2S150E,
200E, 300E,
400E, 600E
All
I/O, VREF I/O, VREF I/O, VREF I/O, VREF
I/O, VREF
Bank 6,
L94N_Y
I/O, VREF
Bank 6,
L94N_Y
Bank 6,
L67N
Bank 6,
L89N_Y
Bank 6,
L94N_Y
Bank 6,
L94N_Y
I/O
6
6
U2
U3
XC2S100E
-
-
I/O, L66P_Y
I/O
I/O
I/O
I/O
I/O
I/O, L#P_Y
XC2S100E,
150E, 200E,
300E, 400E,
600E
I/O,
L66N_Y
I/O, L88P_Y I/O, L93P_Y I/O, L93P_Y I/O,L93P_Y I/O,L93P_Y
I/O, L#N_Y
6
U4
V1
XC2S150E,
200E, 300E,
400E, 600E
-
-
I/O,
L88N_Y
I/O,
L93N_Y
I/O,
L93N_Y
I/O,
L93N_Y
I/O,
L93N_Y
I/O
6
6
-
-
-
-
-
-
I/O
I/O
I/O
I/O, L#P_Y
W1 XC2S100E,
200E, 300E,
600E
I/O, L65P_Y I/O, L87P I/O, L92P_Y I/O, L92P_Y I/O, L92P I/O,L92P_Y
I/O, L#N_Y
6
V2
XC2S100E, XC2S200E,
I/O,
L65N_Y
I/O, L87N
I/O
I/O, VREF I/O, VREF
I/O, VREF
Bank 6,
L92N
I/O, VREF
Bank 6,
L92N_Y
200E, 300E,
600E
300E,
400E, 600E
Bank 6,
L92N_Y
Bank 6,
L92N_Y
I/O
6
6
W2
V3
-
-
-
I/O
-
I/O
I/O
I/O
I/O
I/O, L#P_Y
XC2S200E,
300E, 400E
I/O, L86P I/O, L91P_Y I/O, L91P_Y I/O,L91P_Y I/O, L91P
I/O, L#N_Y
I/O
6
V4
XC2S200E,
300E, 400E
-
-
-
I/O, L86N
-
I/O,
L91N_Y
I/O,
L91N_Y
I/O,
L91N_Y
I/O, L91N
I/O
6
6
Y1
Y2
-
-
-
-
I/O
I/O
I/O,
All
I/O,
I/O,
I/O,
I/O,
I/O,
I/O,
L#P_YY
L64P_YY
L85P_YY
L90P_YY
L90P_YY
L90P_YY
L90P_YY
I/O,
L#N_YY
6
-
W3
U5
All
-
-
-
I/O,
L64N_YY
I/O,
L85N_YY
I/O,
L90N_YY
I/O,
L90N_YY
I/O,
L90N_YY
I/O,
L90N_YY
M1
M1
M1
M1
M1
M1
M1
76
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DS077-4 (2.3) June 18, 2008
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
FG456 Pinouts (XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E, XC2S600E)
Pad Name
LVDS
Async.
Output
Option
Device-Specific Pinouts: XC2S
VREF
Option
Function Bank Pin
100E
M0
150E
M0
200E
M0
300E
M0
400E
M0
600E
M0
M0
M2
-
-
AA1
AB2
-
-
-
-
M2
M2
M2
M2
M2
M2
I/O, L#N_Y
I/O, L#P_Y
5
5
AA3 XC2S150E,
200E, 300E,
-
-
-
-
-
I/O,
L84N_Y
I/O,
L89N_Y
I/O,
L89N_Y
I/O,
L89N_Y
I/O,
L89N_Y
400E, 600E
AB3 XC2S150E,
200E, 300E,
I/O, L84P_Y I/O, L89P_Y I/O, L89P_Y I/O,L89P_Y I/O,L89P_Y
400E, 600E
I/O
I/O
5
5
AB4
-
-
-
-
-
I/O
I/O
I/O
I/O
I/O
I/O
AA5 XC2S100E,
150E
I/O,
L63N_Y
I/O,
L83N_Y
I/O
I/O, L#N_Y
5
W5 XC2S100E,
150E, 200E,
300E, 400E,
600E
-
I/O, L63P_Y I/O, L83P_Y
I/O,
L88N_Y
I/O,
L88N_Y
I/O,
L88N_Y
I/O,
L88N_Y
I/O, L#P_Y
I/O, L#N_Y
I/O, L#P_Y
5
5
5
Y5
XC2S200E,
300E, 400E,
600E
-
I/O
I/O
I/O, L88P_Y I/O, L88P_Y I/O,L88P_Y I/O,L88P_Y
AB5 XC2S100E, XC2S200E,
200E, 300E, 300E,
400E, 600E 400E, 600E
I/O,
L62N_Y
I/O, L82N
I/O, VREF I/O, VREF
I/O, VREF
Bank 5,
I/O, VREF
Bank 5,
Bank 5,
L87N_Y
Bank 5,
L87N_Y
L87N_Y
L87N_Y
AB6 XC2S100E,
-
I/O, L62P_Y I/O, L82P I/O, L87P_Y I/O, L87P_Y I/O,L87P_Y I/O,L87P_Y
200E, 300E,
400E, 600E
I/O
I/O
5
5
5
Y6
AA6
V6
-
-
-
-
-
-
-
-
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O,
All
I/O,
I/O,
I/O,
I/O,
I/O,
I/O,
L#N_YY
L61N_YY
L81N_YY
L86N_YY
L86N_YY
L86N_YY
L86N_YY
I/O,
L#P_YY
5
5
W6
All
All
-
I/O,
L61P_YY
I/O,
L81P_YY
I/O,
L86P_YY
I/O,
L86P_YY
I/O,
L86P_YY
I/O,
L86P_YY
I/O, VREF
Bank 5,
AB7
All
I/O, VREF I/O, VREF I/O, VREF I/O, VREF
Bank 5,
I/O, VREF
Bank 5,
I/O, VREF
Bank 5,
Bank 5,
Bank 5,
Bank 5,
L#N_YY
L60N_YY
L80N_YY
L85N_YY
L85N_YY
L85N_YY
L85N_YY
I/O,
L#P_YY
5
AA7
All
-
-
I/O,
L60P_YY
I/O,
L80P_YY
I/O,
L85P_YY
I/O,
L85P_YY
I/O,
L85P_YY
I/O,
L85P_YY
I/O
5
5
Y7
V7
-
-
-
-
I/O
I/O
I/O
I/O
I/O
I/O, L#N_Y
XC2S300E,
600E
I/O, L79N
I/O, L84N
I/O,
L84N_Y
I/O, L84N
I/O,
L84N_Y
I/O, L#P_Y
I/O, L#N_Y
5
5
W7 XC2S300E,
600E
-
I/O
I/O, L79P
I/O, L78N
I/O, L84P I/O, L84P_Y I/O, L84P I/O, L84P_Y
AB8 XC2S100E, XC2S600E
300E, 600E
I/O,
L59N_Y
I/O, L83N
I/O,
I/O, L83N
I/O, VREF
Bank 5,
L83N_Y
L83N_Y
I/O, L#P_Y
I/O
5
5
AA8 XC2S100E,
300E, 600E
-
-
I/O, L59P_Y I/O, L78P
I/O, L83P I/O, L83P_Y I/O, L83P I/O,L83P_Y
Y8
-
-
-
-
I/O I/O I/O
DS077-4 (2.3) June 18, 2008
www.xilinx.com
77
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
FG456 Pinouts (XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E, XC2S600E)
Pad Name
LVDS
Async.
Output
Option
Device-Specific Pinouts: XC2S
VREF
Option
Function Bank Pin
100E
150E
200E
300E
400E
600E
I/O, VREF
Bank 5,
L#N_Y
5
5
5
5
V8
XC2S100E,
200E, 300E,
400E, 600E
All
I/O, VREF I/O, VREF I/O, VREF I/O, VREF
I/O, VREF
Bank 5,
L82N_Y
I/O, VREF
Bank 5,
L82N_Y
Bank 5,
L58N_Y
Bank 5,
L77N
Bank 5,
L82N_Y
Bank 5,
L82N_Y
I/O, L#P_Y
I/O, L#N_Y
I/O, L#P_Y
W8 XC2S100E,
200E, 300E,
-
I/O, L58P_Y I/O, L77P I/O, L82P_Y I/O, L82P_Y I/O,L82P_Y I/O,L82P_Y
400E, 600E
AB9 XC2S100E,
200E, 300E,
-
I/O,
I/O, L76N
I/O,
I/O,
I/O,
L81N_Y
I/O,
L81N_Y
L57N_Y
L81N_Y
L81N_Y
400E, 600E
AA9 XC2S100E,
200E, 300E,
-
I/O, L57P_Y I/O, L76P I/O, L81P_Y I/O, L81P_Y I/O,L81P_Y I/O,L81P_Y
400E, 600E
I/O
5
5
AB10
-
-
-
-
-
-
I/O
I/O
I/O
I/O
I/O, L#N_Y
W9 XC2S150E,
300E, 400E,
600E
I/O,
L75N_Y
I/O, L80N
I/O,
L80N_Y
I/O,
L80N_Y
I/O,
L80N_Y
I/O, L#P_Y
I/O, L#N_Y
I/O, L#P_Y
5
5
5
Y9
XC2S100E,
150E, 300E,
400E, 600E
-
-
-
I/O,
L56N_Y
I/O, L75P_Y I/O, L80P I/O, L80P_Y I/O,L80P_Y I/O,L80P_Y
V9
XC2S100E,
150E, 300E,
400E, 600E
I/O, L56P_Y
I/O,
I/O, L79N
I/O,
I/O,
I/O,
L74N_Y
L79N_Y
L79N_Y
L79N_Y
U9
XC2S150E,
300E, 400E,
600E
- I/O, L74P_Y I/O, L79P I/O, L79P_Y I/O,L79P_Y I/O,L79P_Y
I/O
5
5
AA10
-
-
-
-
-
I/O
I/O
I/O
I/O
I/O, L#N_Y
W10 XC2S200E,
300E, 400E,
600E
I/O, L55N
I/O, L73N
I/O,
L78N_Y
I/O,
L78N_Y
I/O,
L78N_Y
I/O,
L78N_Y
I/O, L#P_Y
5
5
5
Y10 XC2S200E,
300E, 400E,
600E
-
All
-
I/O, L55P
I/O, L73P I/O, L78P_Y I/O, L78P_Y I/O,L78P_Y I/O,L78P_Y
I/O, VREF
Bank 5,
L#N_Y
V10 XC2S200E,
300E, 400E,
600E
I/O, VREF I/O, VREF I/O, VREF I/O, VREF
Bank 5,
L54N
I/O, VREF
Bank 5,
L77N_Y
I/O, VREF
Bank 5,
L77N_Y
Bank 5,
L72N
Bank 5,
L77N_Y
Bank 5,
L77N_Y
I/O, L#P_Y
U10 XC2S200E,
300E, 400E,
600E
I/O, L54P
I/O, L72P I/O, L77P_Y I/O, L77P_Y I/O,L77P_Y I/O,L77P_Y
I/O
5
5
5
U11
V11
-
-
-
-
-
-
-
-
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
I/O
I/O, L#N
W11 XC2S200E,
400E
I/O
I/O, L71N
I/O,
L76N_Y
I/O, L76N
I/O,
L76N_Y
I/O, L76N
I/O, L#P
5
Y11 XC2S200E, XC2S400E,
-
I/O, L71P I/O, L76P_Y I/O, L76P
I/O, VREF
Bank 5,
L76P_Y
I/O, VREF
Bank 5,
L76P
400E
600E
I/O
5
5
AA11
AB11
-
-
-
-
-
-
-
I/O
I/O
I/O
I/O (DLL),
L#N
I/O (DLL),
L53N
I/O (DLL),
L70N
I/O (DLL),
L75N
I/O (DLL),
L75N
I/O (DLL),
L75N
I/O (DLL),
L75N
GCK1, I
5
AB12
-
-
GCK1, I
GCK1, I
GCK1, I
GCK1, I
GCK1, I
GCK1, I
78
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DS077-4 (2.3) June 18, 2008
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
FG456 Pinouts (XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E, XC2S600E)
Pad Name
LVDS
Async.
Output
Option
Device-Specific Pinouts: XC2S
VREF
Option
Function Bank Pin
100E
150E
200E
300E
400E
600E
GCK0, I
4
4
AA12
Y12
-
-
-
-
GCK0, I
GCK0, I
GCK0, I
GCK0, I
GCK0, I
GCK0, I
I/O (DLL),
L#P
I/O (DLL),
L53P
I/O (DLL),
L70P
I/O (DLL),
L75P
I/O (DLL),
L75P
I/O (DLL),
L75P
I/O (DLL),
L75P
I/O
4
4
W12
-
-
-
-
-
-
-
I/O
I/O
I/O
I/O, L#N
V12 XC2S150E,
300E, 600E
I/O,
L69N_Y
I/O, L74N
I/O,
L74N_Y
I/O, L74N
I/O,
L74N_Y
I/O, L#P
4
U12 XC2S150E, XC2S400E, I/O, L52N I/O, L69P_Y I/O, L74P I/O, L74P_Y I/O, VREF
I/O, VREF
Bank 4,
L74P_Y
300E, 600E
600E
Bank 4,
L74P
I/O, L#N
I/O, L#P
4
4
AB13 XC2S300E,
600E
-
-
I/O, L52P
-
I/O
-
I/O, L73N
I/O,
L73N_Y
I/O, L73N
I/O,
L73N_Y
AA13 XC2S300E,
600E
I/O, L73P I/O, L73P_Y I/O, L73P I/O, L73P_Y
I/O
4
4
Y13
-
-
-
-
-
-
I/O
I/O
I/O
I/O, L#N
W13 XC2S200E,
300E, 400E,
600E
I/O, L51N
I/O, L68N
I/O,
L72N_Y
I/O,
L72N_Y
I/O,
L72N_Y
I/O,
L72N_Y
I/O, VREF
Bank 4,
L#P
4
V13 XC2S200E,
300E, 400E,
600E
All
I/O, VREF I/O, VREF I/O, VREF I/O, VREF
I/O, VREF
Bank 4,
L72P_Y
I/O, VREF
Bank 4,
L72P_Y
Bank 4,
L51P
Bank 4,
L68P
Bank 4,
L72P_Y
Bank 4,
L72P_Y
I/O
4
4
4
4
4
U13
-
-
-
-
-
-
-
-
-
I/O, L50N
I/O, L67N
I/O
I/O
I/O
I/O
I/O, L#N
I/O, L#P
I/O
AB14
AA14
AB15
I/O, L50P
I/O, L67P
I/O, L71N
I/O, L71P
I/O
I/O, L71N
I/O, L71P
I/O
I/O, L71N
I/O, L71P
I/O
I/O, L71N
I/O, L71P
I/O
-
-
-
-
I/O, L#N
Y14 XC2S100E,
150E, 200E
I/O,
L49N_Y
I/O,
L66N_Y
I/O,
L70N_Y
I/O, L70N
I/O, L70N
I/O, L70N
I/O, L#P
I/O, L#N
I/O, L#P
I/O, L#N
4
4
4
4
W14 XC2S100E,
150E, 200E
-
-
-
-
I/O, L49P_Y I/O, L66P_Y I/O, L70P_Y I/O, L70P
I/O, L70P
I/O, L69N
I/O, L69P
I/O, L70P
I/O, L69N
I/O, L69P
U14 XC2S150E,
200E
-
-
I/O,
L65N_Y
I/O,
L69N_Y
I/O, L69N
V14 XC2S150E,
200E
I/O, L65P_Y I/O, L69P_Y I/O, L69P
AA15 XC2S100E,
200E, 300E,
I/O,
I/O, L64N
I/O,
I/O,
I/O,
L68N_Y
I/O,
L68N_Y
L48N_Y
L68N_Y
L68N_Y
400E, 600E
I/O, L#P
I/O, L#N
4
4
4
Y15 XC2S100E,
200E, 300E,
-
-
I/O, L48P_Y I/O, L64P I/O, L68P_Y I/O, L68P_Y I/O,L68P_Y I/O,L68P_Y
400E, 600E
W15 XC2S100E,
200E, 300E,
I/O,
I/O, L63N
I/O,
I/O,
I/O,
I/O,
L47N_Y
L67N_Y
L67N_Y
L67N_Y
L67N_Y
400E, 600E
I/O, VREF
Bank 4,
L#P
V15 XC2S100E,
200E, 300E,
All
I/O, VREF I/O, VREF I/O, VREF I/O, VREF
I/O, VREF
Bank 4,
L67P_Y
I/O, VREF
Bank 4,
L67P_Y
Bank 4,
L47P_Y
Bank 4,
L63P
Bank 4,
L67P_Y
Bank 4,
L67P_Y
400E, 600E
I/O
I/O
4
4
AB16
AB17
-
-
-
-
-
-
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DS077-4 (2.3) June 18, 2008
www.xilinx.com
79
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
FG456 Pinouts (XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E, XC2S600E)
Pad Name
LVDS
Async.
Output
Option
Device-Specific Pinouts: XC2S
VREF
Option
Function Bank Pin
100E
150E
200E
300E
400E
600E
I/O, L#N
4
AA16 XC2S150E, XC2S600E I/O, L46N
200E, 400E
I/O,
L62N_Y
I/O,
L66N_Y
I/O, L66N
I/O,
L66N_Y
I/O, VREF
Bank 4,
L66N
I/O, L#P
I/O, L#N
I/O, L#P
4
4
4
4
4
Y16 XC2S150E,
200E, 400E
-
-
I/O, L46P I/O, L62P_Y I/O, L66P_Y I/O, L66P I/O, L66P_Y I/O, L66P
W16 XC2S150E,
200E
-
-
I/O,
L61N_Y
I/O,
L65N_Y
I/O, L65N
I/O, L65N
I/O, L65P
I/O, L65N
I/O, L65P
V16 XC2S150E,
200E
-
I/O, L61P_Y I/O, L65P_Y I/O, L65P
I/O,
L#N_YY
AA17
All
-
I/O,
I/O,
I/O,
I/O,
I/O,
I/O,
L45N_YY
L60N_YY
L64N_YY
L64N_YY
L64N_YY
L64N_YY
I/O, VREF
Bank 4,
Y17
All
All
I/O, VREF I/O, VREF I/O, VREF I/O, VREF
I/O, VREF
Bank 4,
I/O, VREF
Bank 4,
Bank 4,
Bank 4,
Bank 4,
Bank 4,
L#P_YY
L45P_YY
L60P_YY
L64P_YY
L64P_YY
L64P_YY
L64P_YY
I/O
4
4
4
AB18 XC2S100E
-
-
-
I/O,
L44N_Y
I/O
I/O
I/O, L63N
I/O, L63P
-
I/O
I/O
I/O
I/O, L#N
I/O, L#P
W17 XC2S100E,
400E, 600E
I/O, L44P_Y I/O, L59N
I/O, L63N
I/O,
L63N_Y
I/O,
L63N_Y
V17 XC2S400E,
600E
-
-
I/O, L59P
I/O, L63P I/O, L63P_Y I/O, L63P_Y
I/O
4
4
AA18
-
-
-
-
I/O
I/O
I/O
I/O, L#N
Y18 XC2S100E,
200E, 300E,
I/O,
L43N_Y
I/O, L58N
I/O,
L62N_Y
I/O,
L62N_Y
I/O,
L62N_Y
I/O,
L62N_Y
400E, 600E
I/O, L#P
4
W18 XC2S100E, XC2S200E, I/O, L43P_Y I/O, L58P
200E, 300E, 300E,
400E, 600E 400E, 600E
I/O, VREF I/O, VREF
I/O, VREF
Bank 4,
L62P_Y
I/O, VREF
Bank 4,
L62P_Y
Bank 4,
L62P_Y
Bank 4,
L62P_Y
I/O
4
4
AB19
-
-
-
I/O
-
I/O
I/O
I/O
I/O
I/O
I/O, L#N
AA19 XC2S150E,
400E
I/O,
L57N_Y
I/O, L61N
I/O, L61N
I/O,
L61N_Y
I/O, L61N
I/O, L#P
I/O
4
Y19 XC2S150E,
400E
-
-
-
I/O, L57P_Y I/O, L61P
I/O, L61P I/O, L61P_Y I/O, L61P
4
4
AB21
AB20
-
-
-
-
-
I/O
I/O
I/O
I/O,
All
I/O,
I/O,
I/O,
I/O,
I/O,
I/O,
L#N_YY
L42N_YY
L56N_YY
L60N_YY
L60N_YY
L60N_YY
L60N_YY
I/O,
4
AA20
All
-
I/O,
I/O,
I/O,
I/O,
I/O,
I/O,
L#P_YY
L42P_YY
L56P_YY
L60P_YY
L60P_YY
L60P_YY
L60P_YY
DONE
3
-
W20
Y21
W21
-
-
-
-
-
DONE
DONE
DONE
DONE
DONE
DONE
PROGRAM
PROGRAM PROGRAM PROGRAM PROGRAM PROGRAM PROGRAM
I/O (INIT),
L#N_YY
3
All
I/O (INIT),
L41N_YY
I/O (INIT),
L55N_YY
I/O (INIT),
L59N_YY
I/O (INIT),
L59N_YY
I/O (INIT),
L59N_YY
I/O (INIT),
L59N_YY
I/O (D7),
L#P_YY
3
Y22
All
-
I/O (D7),
L41P_YY
I/O (D7),
L55P_YY
I/O (D7),
L59P_YY
I/O (D7),
L59P_YY
I/O (D7),
L59P_YY
I/O (D7),
L59P_YY
I/O
I/O
3
3
W22
V21
-
-
-
-
-
-
-
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
80
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DS077-4 (2.3) June 18, 2008
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
FG456 Pinouts (XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E, XC2S600E)
Pad Name
LVDS
Async.
Output
Option
Device-Specific Pinouts: XC2S
VREF
Option
Function Bank Pin
100E
150E
200E
300E
400E
600E
I/O, L#N
I/O, L#P
I/O, L#N
I/O, L#P
3
3
3
3
V19 XC2S150E,
200E, 300E,
400E
-
-
I/O,
L54N_Y
I/O,
L58N_Y
I/O,
L58N_Y
I/O,
L58N_Y
I/O, L58N
V20 XC2S150E,
200E, 300E,
400E
-
I/O
I/O, L54P_Y I/O, L58P_Y I/O, L58P_Y I/O,L58P_Y I/O, L58P
V22 XC2S100E, XC2S200E,
I/O,
L40N_Y
I/O, L53N
I/O, VREF I/O, VREF
Bank 3,
L57N_Y
I/O, VREF
Bank 3,
L57N
I/O, VREF
Bank 3,
L57N_Y
200E, 300E,
600E
300E,
400E, 600E
Bank 3,
L57N_Y
U22 XC2S100E,
200E, 300E,
600E
-
I/O, L40P_Y I/O, L53P I/O, L57P_Y I/O, L57P_Y I/O, L57P I/O,L57P_Y
I/O
3
3
3
U21
U20
-
-
-
-
-
-
-
-
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O, L#N
U18 XC2S100E,
200E, 300E,
600E
I/O,
L39N_Y
I/O, L52N
I/O,
L56N_Y
I/O,
L56N_Y
I/O, L56N
I/O,
L56N_Y
I/O, L#P
3
3
3
U19 XC2S100E,
200E, 300E,
600E
-
All
-
I/O, L39P_Y I/O, L52P I/O, L56P_Y I/O, L56P_Y I/O, L56P I/O,L56P_Y
I/O, VREF
Bank 3,
L#N
T21 XC2S150E,
200E, 300E,
I/O, VREF I/O, VREF I/O, VREF I/O, VREF
I/O, VREF
Bank 3,
L55N_Y
I/O, VREF
Bank 3,
L55N_Y
Bank 3,
L38N
Bank 3,
L51N_Y
Bank 3,
L55N_Y
Bank 3,
L55N_Y
400E, 600E
I/O, L#P
T22 XC2S150E,
200E, 300E,
I/O, L38P I/O, L51P_Y I/O, L55P_Y I/O, L55P_Y I/O,L55P_Y I/O,L55P_Y
400E, 600E
I/O
3
3
T20
-
-
-
-
-
I/O
I/O
I/O
I/O
I/O
I/O, L#N
T18 XC2S150E,
200E, 300E,
400E
I/O,
L50N_Y
I/O,
L54N_Y
I/O,
L54N_Y
I/O,
L54N_Y
I/O, L54N
I/O, L#P
I/O, L#N
I/O, L#P
I/O
3
3
3
T19 XC2S150E,
200E, 300E,
400E
-
I/O
I/O, L50P_Y I/O, L54P_Y I/O, L54P_Y I/O,L54P_Y I/O, L54P
R21 XC2S100E, XC2S600E
I/O,
L37N_Y
I/O,
L49N_Y
I/O, L53N
I/O,
L53N_Y
I/O, L53N
I/O, VREF
Bank 3,
150E, 300E,
600E
L53N_Y
R22 XC2S100E,
150E, 300E,
600E
-
I/O, L37P_Y I/O, L49P_Y I/O, L53P I/O, L53P_Y I/O, L53P I/O,L53P_Y
3
3
R20
-
-
-
-
-
I/O
I/O
I/O
I/O, VREF
Bank 3,
L#N
R18 XC2S300E,
400E, 600E
All
I/O, VREF I/O, VREF I/O, VREF I/O, VREF
Bank 3,
L36N
I/O, VREF
Bank 3,
L52N_Y
I/O, VREF
Bank 3,
L52N_Y
Bank 3,
L48N
Bank 3,
L52N
Bank 3,
L52N_Y
I/O (D6),
L#P
3
3
3
R19 XC2S300E,
400E, 600E
-
-
-
I/O (D6),
L36P
I/O (D6),
L48P
I/O (D6),
L52P
I/O (D6),
L52P_Y
I/O (D6),
L52P_Y
I/O (D6),
L52P_Y
I/O (D5),
L#N_YY
P22
All
I/O (D5),
L35N_YY
I/O (D5),
L47N_YY
I/O (D5),
L51N_YY
I/O (D5),
L51N_YY
I/O (D5)
L51N_YY
I/O (D5),
L51N_YY
I/O,
P21
All
I/O,
I/O,
I/O,
I/O,
I/O,
I/O,
L#P_YY
L35P_YY
L47P_YY
L51P_YY
L51P_YY
L51P_YY
L51P_YY
DS077-4 (2.3) June 18, 2008
www.xilinx.com
81
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
FG456 Pinouts (XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E, XC2S600E)
Pad Name
LVDS
Async.
Output
Option
Device-Specific Pinouts: XC2S
VREF
Option
Function Bank Pin
100E
150E
200E
300E
400E
600E
I/O
I/O
3
3
P20
-
-
-
-
-
-
I/O
I/O
I/O
I/O, L#N
P18 XC2S150E,
200E, 300E,
400E
I/O,
L46N_Y
I/O,
L50N_Y
I/O,
L50N_Y
I/O,
I/O, L50N
L50N_Y
I/O, L#P
I/O, L#N
I/O, L#P
3
3
3
P19 XC2S100E,
150E, 200E,
-
-
-
I/O,
L34N_Y
I/O, L46P_Y I/O, L50P_Y I/O, L50P_Y I/O,L50P_Y I/O, L50P
300E, 400E
N22 XC2S100E,
150E, 200E,
I/O, L34P_Y
I/O,
I/O,
I/O,
I/O, L49N
I/O,
L45N_Y
L49N_Y
L49N_Y
L49N_Y
300E, 600E
N21 XC2S150E,
200E, 300E,
600E
-
-
I/O, L45P_Y I/O, L49P_Y I/O, L49P_Y I/O, L49P I/O,L49P_Y
I/O
3
3
P17
-
-
-
-
I/O
I/O
I/O
I/O
I/O, L#N
N19 XC2S100E,
150E, 200E,
300E,
I/O,
L33N_YY
I/O,
I/O,
I/O,
I/O, L48N
I/O,
L44N_YY
L48N_YY
L48N_YY
L48N_Y
600E(1)
I/O, L#P
3
N20 XC2S100E,
150E, 200E,
300E,
-
I/O,
L33P_YY
I/O,
L44P_YY
I/O,
L48P_YY
I/O,
L48P_YY
I/O, L48P I/O, L48P_Y
600E(1)
I/O, VREF
Bank 3,
L#N
3
3
N18 XC2S300E,
400E, 600E
All
-
I/O, VREF I/O, VREF I/O, VREF I/O, VREF
I/O, VREF
Bank 3,
L47N_Y
I/O, VREF
Bank 3,
L47N_Y
Bank 3,
L32N
Bank 3,
L43N
Bank 3,
L47N
Bank 3,
L47N_Y
I/O (D4),
L#P
N17 XC2S300E,
400E, 600E
I/O (D4),
L32P
I/O (D4),
L43P
I/O (D4),
L47P
I/O (D4),
L47P_Y
I/O (D4),
L47P_Y
I/O (D4),
L47P_Y
I/O
3
3
M22
-
-
-
-
-
-
-
-
I/O
I/O
I/O
I/O, L#N
M20 XC2S300E,
400E
I/O, L46N
I/O,
L46N_Y
I/O,
L46N_Y
I/O, L46N
I/O, L#P
I/O, L#N
I/O, L#P
3
3
3
M21 XC2S100E,
150E, 300E,
400E
-
I/O,
L31N_Y
I/O,
L42N_Y
I/O, L46P I/O, L46P_Y I/O,L46P_Y I/O, L46P
M18 XC2S100E, XC2S400E, I/O, L31P_Y I/O, L42P_Y
I/O,
L45N_Y
I/O,
L45N_Y
I/O, VREF
Bank 3,
L45N
I/O, VREF
Bank 3,
L45N_Y
150E, 200E,
300E, 600E
600E
M19 XC2S200E,
300E, 600E
-
-
-
I/O
-
I/O, L45P_Y I/O, L45P_Y I/O, L45P I/O, L45P_Y
I/O
3
3
M17
L22
-
-
-
-
-
I/O I/O I/O
I/O (TRDY)
I/O (TRDY) I/O (TRDY) I/O (TRDY) I/O (TRDY) I/O (TRDY) I/O (TRDY)
I/O (IRDY),
L#N_YY
2
2
L21
L20
L19
All
All
-
-
-
I/O (IRDY), I/O (IRDY), I/O (IRDY), I/O (IRDY), I/O (IRDY), I/O (IRDY),
L30N_YY
L41N_YY
L44N_YY
L44N_YY
L44N_YY
L44N_YY
I/O,
L#P_YY
I/O,
I/O,
I/O,
I/O,
I/O,
I/O,
L30P_YY
L41P_YY
L44P_YY
L44P_YY
L44P_YY
L44P_YY
I/O
2
2
-
-
-
-
-
-
I/O
I/O
I/O
I/O, L#N
L18 XC2S200E,
300E, 600E
I/O
I/O,
I/O,
I/O, L43N
I/O,
L43N_Y
L43N_Y
L43N_Y
82
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DS077-4 (2.3) June 18, 2008
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
FG456 Pinouts (XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E, XC2S600E)
Pad Name
LVDS
Async.
Output
Option
Device-Specific Pinouts: XC2S
VREF
Option
Function Bank Pin
100E
150E
200E
300E
400E
600E
I/O, L#P
I/O, L#N
I/O, L#P
2
2
2
L17 XC2S100E, XC2S400E,
I/O,
L29N_Y
I/O,
L40N_Y
I/O, L43P_Y I/O, L43P_Y I/O, VREF
I/O, VREF
Bank 2,
L43P_Y
150E, 200E,
300E, 600E
600E
Bank 2,
L43P
K22 XC2S100E,
150E, 300E,
400E
-
I/O, L29P_Y I/O, L40P_Y I/O, L42N
I/O,
I/O,
I/O, L42N
L42N_Y
L42N_Y
K21 XC2S300E,
400E
-
-
-
-
I/O, L42P I/O, L42P_Y I/O, L42P_Y I/O, L42P
I/O
2
2
K20
K19
-
-
-
-
-
-
I/O
I/O
I/O
I/O (D3)
I/O (D3)
I/O (D3),
L39N
I/O (D3)
I/O (D3)
I/O (D3)
I/O (D3)
I/O, VREF
Bank 2,
L#N
2
2
K18 XC2S100E,
200E, 400E
All
-
I/O, VREF I/O, VREF I/O, VREF I/O, VREF
I/O, VREF
Bank 2,
L41N_Y
I/O, VREF
Bank 2,
L41N
Bank 2,
L28N_Y
Bank 2,
L39P
Bank 2,
L41N_Y
Bank 2,
L41N
I/O, L#P
K17
XC2S100,
150E, 200E,
400E
I/O, L28P_Y
I/O,
I/O, L41P_Y I/O, L41P I/O, L41P_Y I/O, L41P
L38N_Y
I/O, L#N
I/O, L#P
I/O, L#N
2
2
2
J22 XC2S150E,
300E, 600E
-
-
-
I/O
I/O, L38P_Y I/O, L40N
I/O,
L40N_Y
I/O, L40N
I/O,
L40N_Y
J21 XC2S300E,
600E
-
-
-
I/O, L40P I/O, L40P_Y I/O, L40P I/O,L40P_Y
J20 XC2S150E,
200E, 300E,
600E
I/O,
I/O,
I/O,
L39N_Y
I/O, L39N
I/O,
L39N_Y
L37N_Y
L39N_Y
I/O, L#P
2
J19 XC2S100E,
150E, 200E,
-
I/O,
L27N_Y
I/O, L37P_Y I/O, L39P_Y I/O, L39P_Y I/O, L39P I/O,L39P_Y
300E, 600E
I/O
2
2
H22 XC2S100E,
150E
-
-
I/O, L27P_Y
-
I/O,
L36N_Y
I/O
I/O
I/O
I/O
I/O, L#N
J18 XC2S150E,
200E, 300E,
I/O, L36P_Y
I/O,
L38N_Y
I/O,
L38N_Y
I/O,
L38N_Y
I/O,
L38N_Y
400E, 600E
I/O, L#P
I/O, L#N
2
2
2
J17 XC2S200E,
300E, 400E,
600E
-
-
-
-
- I/O, L38P_Y I/O, L38P_Y I/O,L38P_Y I/O,L38P_Y
H21 XC2S150E,
200E, 300E,
I/O
I/O,
I/O,
I/O,
I/O,
I/O,
L35N_Y
L37N_Y
L37N_Y
L37N_Y
L37N_Y
400E, 600E
I/O (D2),
L#P
H20 XC2S150E,
200E, 300E,
I/O (D2)
I/O (D2),
L35P_Y
I/O (D2),
L37P_Y
I/O (D2),
L37P_Y
I/O (D2),
L37P_Y
I/O (D2),
L37P_Y
400E, 600E
I/O (D1),
L#N
2
2
H19 XC2S300E,
400E, 600E
-
I/O (D1),
L26N
I/O (D1),
L34N
I/O (D1),
L36N
I/O (D1),
L36N_Y
I/O (D1),
L36N_Y
I/O (D1),
L36N_Y
I/O, VREF
Bank 2,
L#P
H18 XC2S300E,
400E, 600E
All
I/O, VREF I/O, VREF I/O, VREF I/O, VREF
Bank 2,
L26P
I/O, VREF
Bank 2,
L36P_Y
I/O, VREF
Bank 2,
L36P_Y
Bank 2,
L34P
Bank 2,
L36P
Bank 2,
L36P_Y
I/O
I/O
2
2
G22
F22
-
-
-
-
-
-
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DS077-4 (2.3) June 18, 2008
www.xilinx.com
83
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
FG456 Pinouts (XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E, XC2S600E)
Pad Name
LVDS
Async.
Output
Option
Device-Specific Pinouts: XC2S
VREF
Option
Function Bank Pin
100E
150E
200E
300E
400E
600E
I/O, L#N
2
G21 XC2S200E, XC2S600E I/O, L25N
400E, 600E
I/O, L33N
I/O,
L35N_Y
I/O, L35N
I/O,
L35N_Y
I/O, VREF
Bank 2,
L35N_Y
I/O, L#P
I/O, L#N
I/O, L#P
I/O, L#N
2
2
2
2
G20 XC2S200E,
400E, 600E
-
-
-
-
I/O, L25P
I/O, L33P I/O, L35P_Y I/O, L35P I/O, L35P_Y I/O, L35P_Y
G19 XC2S150E,
300E
-
I/O,
L32N_Y
I/O, L34N
I/O,
L34N_Y
I/O, L34N
I/O, L34N
I/O, L34P
G18 XC2S150E,
300E
-
I/O, L32P_Y I/O, L34P I/O, L34P_Y I/O, L34P
E22 XC2S150E,
200E, 300E,
I/O, L24N
I/O,
I/O,
I/O,
I/O,
I/O,
L31N_Y
L33N_Y
L33N_Y
L33N_Y
L33N_Y
400E, 600E
I/O, VREF
Bank 2,
L#P
2
F21 XC2S150E,
200E, 300E,
All
I/O, VREF I/O, VREF I/O, VREF I/O, VREF
I/O, VREF
Bank 2,
L33P_Y
I/O, VREF
Bank 2,
L33P_Y
Bank 2,
L24P
Bank 2,
L31P_Y
Bank 2,
L33P_Y
Bank 2,
L33P_Y
400E, 600E
I/O
2
2
E21 XC2S100E
-
-
I/O,
L23N_Y
I/O
I/O
I/O
I/O
I/O
I/O, L#N
F20 XC2S100E,
150E, 200E,
300E, 400E,
600E
I/O, L23P_Y
I/O,
L30N_Y
I/O,
L32N_Y
I/O,
L32N_Y
I/O,
L32N_Y
I/O,
L32N_Y
I/O, L#P
2
F19 XC2S150E,
200E, 300E,
-
-
-
I/O, L30P_Y I/O, L32P_Y I/O, L32P_Y I/O, L32P_Y I/O, L32P_Y
400E, 600E
I/O
2
2
F18
-
-
-
-
-
I/O
I/O
I/O
I/O, L#N
D22 XC2S100E,
200E, 300E,
600E
I/O,
L22N_Y
I/O, L29N
I/O,
I/O,
I/O, L31N
I/O,
L31N_Y
L31N_Y
L31N_Y
I/O, L#P
2
D21 XC2S100E, XC2S200E, I/O, L22P_Y I/O, L29P
I/O, VREF I/O, VREF
I/O, VREF
Bank 2,
L31P
I/O, VREF
Bank 2,
L31P_Y
200E, 300E,
600E
300E,
400E, 600E
Bank 2,
L31P_Y
Bank 2,
L31P_Y
I/O, L#N
I/O, L#P
I/O
2
2
E20 XC2S200E,
300E, 400E
-
I/O
I/O, L28N
I/O,
L30N_Y
I/O,
L30N_Y
I/O,
L30N_Y
I/O, L30N
E19 XC2S200E,
300E, 400E
-
-
I/O, L28P I/O, L30P_Y I/O, L30P_Y I/O,L30P_Y I/O, L30P
2
2
D20
C22
-
-
-
-
-
-
I/O
I/O
I/O
I/O (DIN,
D0),
All
I/O (DIN,
D0),
I/O (DIN,
D0),
I/O (DIN,
D0),
I/O (DIN,
D0),
I/O (DIN,
D0),
I/O (DIN,
D0),
L#N_YY
L21N_YY
L27N_YY
L29N_YY
L29N_YY
L29N_YY
L29N_YY
I/O (DOUT,
BUSY),
2
C21
All
-
I/O (DOUT, I/O (DOUT, I/O (DOUT, I/O (DOUT, I/O (DOUT, I/O (DOUT,
BUSY),
BUSY),
BUSY),
BUSY),
BUSY),
BUSY),
L#P_YY
L21P_YY
L27P_YY
L29P_YY
L29P_YY
L29P_YY
L29P_YY
CCLK
TDO
TDI
2
2
-
B22
A21
C19
-
-
-
-
-
-
CCLK
TDO
TDI
CCLK
TDO
TDI
CCLK
TDO
TDI
CCLK
TDO
TDI
CCLK
TDO
TDI
CCLK
TDO
TDI
I/O (CS),
L#P_YY
1
B20
All
-
I/O (CS),
L20P_YY
I/O (CS),
L26P_YY
I/O (CS),
L28P_YY
I/O (CS),
L28P_YY
I/O (CS),
L28P_YY
I/O (CS),
L28P_YY
84
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DS077-4 (2.3) June 18, 2008
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
FG456 Pinouts (XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E, XC2S600E)
Pad Name
LVDS
Async.
Output
Option
Device-Specific Pinouts: XC2S
VREF
Option
Function Bank Pin
100E
150E
200E
300E
400E
600E
I/O
1
A20
All
-
I/O
I/O
I/O
I/O
I/O
I/O
(WRITE),
L#N_YY
(WRITE),
L20N_YY
(WRITE),
L26N_YY
(WRITE),
L28N_YY
(WRITE),
L28N_YY
(WRITE),
L28N_YY
(WRITE),
L28N_YY
I/O
1
1
1
D18
C18
-
-
-
-
-
-
-
-
-
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O, L#P
B19 XC2S200E,
300E, 400E,
600E
I/O, L25P I/O, L27P_Y I/O, L27P_Y I/O,L27P_Y I/O,L27P_Y
I/O, L#N
I/O, L#P
I/O, L#N
1
1
1
A19 XC2S200E,
300E, 400E,
600E
-
I/O
I/O, L25N
I/O,
L27N_Y
I/O,
L27N_Y
I/O,
L27N_Y
I/O,
L27N_Y
B18 XC2S100E, XC2S200E, I/O, L19P_Y I/O, L24P
200E, 300E, 300E,
400E, 600E 400E, 600E
I/O, VREF I/O, VREF
Bank 1,
L26P_Y
I/O, VREF
Bank 1,
L26P_Y
I/O, VREF
Bank 1,
L26P_Y
Bank 1,
L26P_Y
A18 XC2S100E,
-
I/O,
I/O, L24N
I/O,
I/O,
I/O,
I/O,
200E, 300E,
400E, 600E
L19N_Y
L26N_Y
L26N_Y
L26N_Y
L26N_Y
I/O
I/O
1
1
1
D17
C17
B17
-
-
-
-
-
-
-
-
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O,
All
I/O,
I/O,
I/O,
I/O,
I/O,
I/O,
L#P_YY
L18P_YY
L23P_YY
L25P_YY
L25P_YY
L25P_YY
L25P_YY
I/O,
L#N_YY
1
1
A17
E16
All
All
-
I/O,
L18N_YY
I/O,
L23N_YY
I/O,
L25N_YY
I/O,
L25N_YY
I/O,
L25N_YY
I/O,
L25N_YY
I/O, VREF
Bank 1,
All
I/O, VREF I/O, VREF I/O, VREF I/O, VREF
Bank 1,
I/O, VREF
Bank 1,
I/O, VREF
Bank 1,
Bank 1,
Bank 1,
Bank 1,
L#P_YY
L17P_YY
L22P_YY
L24P_YY
L24P_YY
L24P_YY
L24P_YY
I/O,
L#N_YY
1
E17
E15
All
-
-
I/O,
L17N_YY
I/O,
L22N_YY
I/O,
L24N_YY
I/O,
L24N_YY
I/O,
L24N_YY
I/O,
L24N_YY
I/O
1
1
-
-
-
-
I/O
I/O
I/O
I/O
I/O
I/O, L#P
D16 XC2S300E,
600E
I/O, L21P
I/O, L23P I/O, L23P_Y I/O, L23P I/O,L23P_Y
I/O, L#N
I/O, L#P
1
1
C16 XC2S300E,
600E
-
I/O
I/O, L21N
I/O, L23N
I/O,
L23N_Y
I/O, L23N
I/O,
L23N_Y
B16 XC2S100E, XC2S600E I/O, L16P_Y I/O, L20P
300E, 600E
I/O, L22P I/O, L22P_Y I/O, L22P
I/O, VREF
Bank 1,
L22P_Y
I/O, L#N
I/O
1
A16 XC2S100E,
300E, 600E
-
I/O,
L16N_Y
I/O, L20N
-
I/O, L22N
-
I/O,
L22N_Y
I/O, L22N
I/O
I/O,
L22N_Y
1
1
F14
-
-
-
I/O
I/O
I/O, VREF
Bank 1,
L#P
D15 XC2S100E,
200E, 300E,
All
I/O, VREF I/O, VREF I/O, VREF I/O, VREF
Bank 1,
L15P_Y
I/O, VREF
Bank 1,
L21P_Y
I/O, VREF
Bank 1,
L21P_Y
Bank 1,
L19P
Bank 1,
L21P_Y
Bank 1,
L21P_Y
400E, 600E
I/O, L#N
1
1
C15 XC2S100E,
200E, 300E,
-
-
I/O,
L15N_Y
I/O, L19N
I/O,
L21N_Y
I/O,
L21N_Y
I/O,
L21N_Y
I/O,
L21N_Y
400E, 600E
I/O, L#P
B15 XC2S100E,
200E, 300E,
I/O, L14P_Y I/O, L18P I/O, L20P_Y I/O, L20P_Y I/O,L20P_Y I/O,L20P_Y
400E, 600E
DS077-4 (2.3) June 18, 2008
www.xilinx.com
85
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
FG456 Pinouts (XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E, XC2S600E)
Pad Name
LVDS
Async.
Output
Option
Device-Specific Pinouts: XC2S
VREF
Option
Function Bank Pin
100E
150E
200E
300E
400E
600E
I/O, L#N
1
A15 XC2S100E,
200E, 300E,
-
I/O,
L14N_Y
I/O, L18N
I/O,
L20N_Y
I/O,
L20N_Y
I/O,
L20N_Y
I/O,
L20N_Y
400E, 600E
I/O
1
1
E14
-
-
-
-
-
-
I/O
I/O
I/O
I/O
I/O, L#P
D14 XC2S150E,
300E, 400E,
600E
I/O, L17P_Y I/O, L19P I/O, L19P_Y I/O,L19P_Y I/O,L19P_Y
I/O, L#N
I/O, L#P
I/O, L#N
1
1
1
C14 XC2S100E,
150E, 300E,
-
-
-
I/O, L13P_Y
I/O,
L17N_Y
I/O, L19N
I/O,
L19N_Y
I/O,
L19N_Y
I/O,
L19N_Y
400E, 600E
B14 XC2S100E,
150E, 300E,
I/O,
L13N_Y
I/O, L16P_Y I/O, L18P I/O, L18P_Y I/O,L18P_Y I/O,L18P_Y
400E, 600E
A14 XC2S150E,
300E, 400E,
600E
-
I/O,
L16N_Y
I/O, L18N
I/O,
L18N_Y
I/O,
L18N_Y
I/O,
L18N_Y
I/O
1
1
E13
-
-
-
-
-
I/O
I/O
I/O
I/O
I/O, L#P
D13 XC2S200E,
300E, 400E,
600E
I/O, L12P
I/O, L15P I/O, L17P_Y I/O, L17P_Y I/O,L17P_Y I/O,L17P_Y
I/O, L#N
1
1
1
C13 XC2S200E,
300E, 400E,
600E
-
All
-
I/O, L12N
I/O, L15N
I/O,
L17N_Y
I/O,
L17N_Y
I/O,
L17N_Y
I/O,
L17N_Y
I/O, VREF
Bank 1,
L#P
B13 XC2S200E,
300E, 400E,
600E
I/O, VREF I/O, VREF I/O, VREF I/O, VREF
Bank 1,
L11P
I/O, VREF
Bank 1,
L16P_Y
I/O, VREF
Bank 1,
L16P_Y
Bank 1,
L14P
Bank 1,
L16P_Y
Bank 1,
L16P_Y
I/O, L#N
A13 XC2S200E,
300E, 400E,
600E
I/O, L11N
I/O, L14N
I/O,
L16N_Y
I/O,
L16N_Y
I/O,
L16N_Y
I/O,
L16N_Y
I/O
1
1
F13
-
-
-
-
-
-
-
-
I/O
I/O
I/O
I/O, L#P
C12 XC2S300E,
600E
I/O, L15P I/O, L15P_Y I/O, L15P I/O,L15P_Y
I/O, L#N
I/O, L#P
1
1
B12 XC2S300E,
600E
-
I/O, L10P
I/O
I/O, L15N
I/O,
L15N_Y
I/O, L15N
I/O,
L15N_Y
D12 XC2S150E, XC2S400E, I/O, L10N I/O, L13P_Y I/O, L14P I/O, L14P_Y I/O, VREF
I/O, VREF
Bank 1,
L14P_Y
300E, 600E
600E
Bank 1,
L14P
I/O, L#N
I/O
1
E12 XC2S150E,
300E, 600E
-
-
-
I/O,
L13N_Y
I/O, L14N
-
I/O,
L14N_Y
I/O, L14N
I/O,
L14N_Y
1
1
F12
A12
-
-
-
-
-
I/O
I/O
I/O
I/O (DLL),
L#P
I/O (DLL),
L9P
I/O (DLL),
L12P
I/O (DLL),
L13P
I/O (DLL),
L13P
I/O (DLL),
L13P
I/O (DLL),
L13P
GCK2, I
1
A11
-
-
GCK2, I
GCK2, I
GCK2, I
GCK2, I
GCK2, I
GCK2, I
GCK3, I
0
0
C11
B11
-
-
-
-
GCK3, I
GCK3, I
GCK3, I
GCK3, I
GCK3, I
GCK3, I
I/O (DLL),
L#N
I/O (DLL),
L9N
I/O (DLL),
L12N
I/O (DLL),
L13N
I/O (DLL),
L13N
I/O (DLL),
L13N
I/O (DLL),
L13N
I/O
0
D11
-
-
-
-
-
I/O
I/O
I/O
86
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DS077-4 (2.3) June 18, 2008
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
FG456 Pinouts (XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E, XC2S600E)
Pad Name
LVDS
Async.
Output
Option
Device-Specific Pinouts: XC2S
VREF
Option
Function Bank Pin
100E
150E
200E
300E
400E
600E
I/O
0
0
0
F11
-
XC2S400E,
600E
-
-
I/O
I/O
I/O, VREF
Bank 0
I/O, VREF
Bank 0
I/O, L#P
I/O, L#N
A10 XC2S300E,
600E
-
I/O
-
I/O, L11P
I/O, L11N
-
I/O, L12P I/O, L12P_Y I/O, L12P I/O,L12P_Y
B10 XC2S300E,
600E
-
I/O, L12N
-
I/O,
L12N_Y
I/O, L12N
I/O
I/O,
L12N_Y
I/O
0
0
E11
-
-
-
-
I/O
I/O
I/O, L#P
C10 XC2S200E,
300E, 400E,
600E
I/O, L8P
I/O, L10P I/O, L11P_Y I/O, L11P_Y I/O,L11P_Y I/O,L11P_Y
I/O, VREF
Bank 0,
L#N
0
D10 XC2S200E,
300E, 400E,
600E
All
I/O, VREF I/O, VREF I/O, VREF I/O, VREF
I/O, VREF
Bank 0,
L11N_Y
I/O, VREF
Bank 0,
L11N_Y
Bank 0,
L8N
Bank 0,
L10N
Bank 0,
L11N_Y
Bank 0,
L11N_Y
I/O
0
0
0
0
0
F10
A9
-
-
-
-
-
-
-
-
-
I/O, L7P
I/O
I/O
-
I/O
I/O
I/O
I/O
I/O, L#P
I/O, L#N
I/O
I/O, L7N
I/O, L10P
I/O, L10N
I/O
I/O, L10P
I/O, L10N
I/O
I/O, L10P
I/O, L10N
I/O
I/O, L10P
I/O, L10N
I/O
B9
-
-
E10
C9
-
I/O, L#P
XC2S100E,
150E, 200E
I/O, L6P_Y I/O, L9P_Y I/O, L9P_Y
I/O, L9P
I/O, L9P
I/O, L9P
I/O, L#N
I/O, L#P
I/O, L#N
I/O, L#P
0
0
0
0
D9
F9
E9
A8
XC2S100E,
150E, 200E
-
-
-
-
I/O, L6N_Y I/O, L9N_Y I/O, L9N_Y
I/O, L9N
I/O, L8P
I/O, L8N
I/O, L9N
I/O, L8P
I/O, L8N
I/O, L9N
I/O, L8P
I/O, L8N
XC2S150E,
200E
-
I/O, L8P_Y I/O, L8P_Y
I/O, L8N_Y I/O, L8N_Y
XC2S150E,
200E
-
XC2S100E,
200E, 300E,
400E, 600E
I/O, L5P_Y
I/O, L7P
I/O, L7N
I/O, L6P
I/O, L7P_Y I/O, L7P_Y I/O, L7P_Y I/O, L7P_Y
I/O, L7N_Y I/O, L7N_Y I/O, L7N_Y I/O, L7N_Y
I/O, L6P_Y I/O, L6P_Y I/O, L6P_Y I/O, L6P_Y
I/O, L#N
I/O, L#P
0
0
0
B8
C8
D8
XC2S100E,
200E, 300E,
400E, 600E
-
-
I/O, L5N_Y
I/O, L4P_Y
XC2S100E,
200E, 300E,
400E, 600E
I/O, VREF
Bank 0,
L#N
XC2S100E,
200E, 300E,
400E, 600E
All
I/O, VREF I/O, VREF I/O, VREF I/O, VREF
I/O, VREF
Bank 0,
L6N_Y
I/O, VREF
Bank 0,
L6N_Y
Bank 0,
L4N_Y
Bank 0,
L6N
Bank 0,
L6N_Y
Bank 0,
L6N_Y
I/O
0
0
0
A7
B7
C7
-
-
-
-
-
-
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O, L#P
XC2S150E, XC2S600E
200E
I/O, L3P
I/O, L5P_Y I/O, L5P_Y
I/O, L5N_Y I/O, L5N_Y
I/O, L4P_Y I/O, L4P_Y
I/O, L4N_Y I/O, L4N_Y
I/O, L5P
I/O, L5P
I/O, VREF
Bank0,L5P
I/O, L#N
I/O, L#P
I/O, L#N
0
0
0
D7
E8
E7
XC2S150E,
200E
-
-
-
I/O, L3N
I/O, L5N
I/O, L4P
I/O, L4N
I/O, L5N
I/O, L4P
I/O, L4N
I/O, L5N
I/O, L4P
I/O, L4N
XC2S150E,
200E
-
-
XC2S150E,
200E
DS077-4 (2.3) June 18, 2008
www.xilinx.com
87
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
FG456 Pinouts (XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E, XC2S600E)
Pad Name
LVDS
Async.
Output
Option
Device-Specific Pinouts: XC2S
VREF
Option
Function Bank Pin
100E
150E
200E
300E
400E
600E
I/O,
0
A6
All
-
I/O,
I/O,
I/O,
I/O,
I/O,
I/O,
L#P_YY
L2P_YY
L3P_YY
L3P_YY
L3P_YY
L3P_YY
L3P_YY
I/O, VREF
Bank 0,
L#N_YY
0
B6
All
All
I/O, VREF I/O, VREF I/O, VREF I/O, VREF
I/O, VREF
Bank 0,
L3N_YY
I/O, VREF
Bank 0,
L3N_YY
Bank 0,
L2N_YY
Bank 0,
L3N_YY
Bank 0,
L3N_YY
Bank 0,
L3N_YY
I/O
0
0
0
0
0
C6
A5
B5
D6
B4
XC2S100E
-
-
-
-
-
I/O, L1P_Y
I/O
I/O, L2P
I/O, L2N
-
I/O
I/O, L2P
I/O, L2N
-
I/O
I/O
I/O
I/O, L#P
I/O, L#N
I/O
XC2S100E
I/O, L1N_Y
I/O, L2P
I/O, L2N
I/O
I/O, L2P
I/O, L2N
I/O
I/O, L2P
I/O, L2N
I/O
-
-
-
-
I/O, L#P
XC2S100E,
200E, 300E,
400E, 600E
I/O, L0P_Y
I/O, L1P
I/O, L1P_Y I/O, L1P_Y I/O, L1P_Y I/O, L1P_Y
I/O, L#N
0
C5
XC2S100E, XC2S200E, I/O, L0N_Y
200E, 300E, 300E,
400E, 600E 400E, 600E
I/O, L1N
I/O, VREF I/O, VREF
I/O, VREF
Bank 0,
L1N_Y
I/O, VREF
Bank 0,
L1N_Y
Bank 0,
L1N_Y
Bank 0,
L1N_Y
I/O
0
0
A4
A3
-
-
-
I/O
-
I/O
I/O
I/O
I/O
I/O
I/O, L#P
XC2S150E,
400E, 600E
I/O, L0P_Y
I/O, L0P
I/O, L0P
I/O, L0P_Y I/O, L0P_Y
I/O, L#N
0
B3
XC2S150E,
400E, 600E
-
-
I/O, L0N_Y
I/O, L0N
I/O, L0N
I/O, L0N_Y I/O, L0N_Y
I/O
0
0
-
C4
D5
E6
-
-
-
-
-
-
-
-
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TCK
TCK
TCK
TCK
TCK
TCK
TCK
Notes:
1. Although designated with the _YY suffix in the XC2S100E, XC2S150E, XC2S200E, and XC2S300E, these differential pairs are not
asynchronous in the XC2S400E.
FG456 Differential Clock Pins
P
N
Clock
GCK0
GCK1
GCK2
GCK3
Bank
Pin
AA12
AB12
A11
Name
Pin
Y12
Name
4
5
1
0
GCK0, I
GCK1, I
GCK2, I
GCK3, I
I/O (DLL), L#P
I/O (DLL), L#N
I/O (DLL), L#P
I/O (DLL), L#N
AB11
A12
C11
B11
Additional FG456 Package Pins
VCCINT Pins
D4(1)
G16
U6
D19(1)
H7
E5
H16
V5
E18
F6
F17
T7
W19(1)
G7
T8
-
G8
T15
-
G15
R7
R16
W4(1)
T16
-
U17
V18
VCCO Bank 0 Pins
F7
F8
G9
G10
-
-
-
-
-
88
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DS077-4 (2.3) June 18, 2008
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
Additional FG456 Package Pins (Continued)
VCCO Bank 1 Pins
F15
F16
H17
P16
T14
T10
P7
G13
J16
R17
U15
U7
G14
K16
T17
U16
U8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VCCO Bank 2 Pins
G17
VCCO Bank 3 Pins
N16
VCCO Bank 4 Pins
T13
VCCO Bank 5 Pins
T9
VCCO Bank 6 Pins
N7
R6
T6
VCCO Bank 7 Pins
G6
GND Pins
A1
H6
J7
K7
A2(2)
J9
A22
J10
B1(2)
J11
B2
J12
B21
J13
L9
C3
J14
C20
K9
G11
K10
L12
M13
P9
G12
K11
K12
L14
M16
P11
AA2
K13
L16
K14
M7
L7
L10
L11
M12
N14
Y20
-
L13
M9
M10
N12
T11
AB1
M11
N13
T12
AB22
M14
N9
N10
P13
AA21
N11
P14
AA22(2)
P10
Y4(2)
P12
AA4(2)
Y3
-
Not Connected Pins
A2(2) B1(2)
Notes:
D4(1)
D19(1)
W4(1)
W19(1)
Y4(2)
AA4(2)
AA22(2)
1. VCCINT connections in XC2S400E and XC2S600E. No Connects (no internal connection) in XC2S100E, XC2S150E, XC2S200E,
and XC2S300E.
2. GND connections in XC2S400E and XC2S600E. No Connects (no internal connection) in XC2S100E, XC2S150E, XC2S200E, and
XC2S300E
FG676 Pinouts (XC2S400E, XC2S600E)
Pad Name
Device-Specific Pinouts
LVDS Async.
VREF
Function
Bank
Pin
B1
D3
C2
C1
D2
D1
E2
E1
Output Option
Option
XC2S400E
XC2S600E
TMS
TMS
I/O
-
-
-
-
-
-
-
-
-
-
TMS
7
7
7
7
7
7
7
-
I/O
I/O
I/O, L204P
-
-
I/O, L204P
I/O, L204N
I/O, L203P_Y
I/O, L203N_Y
I/O, L202P_YY
I/O, L202N_YY
I/O, L204N
-
-
I/O, L203P
XC2S600E
XC2S600E
All
-
I/O, L203N
I/O
I/O, L202P_YY
I/O, L202N_YY
I/O, L202P_YY
I/O, L202N_YY
All
DS077-4 (2.3) June 18, 2008
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89
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
FG676 Pinouts (XC2S400E, XC2S600E) (Continued)
Pad Name
Device-Specific Pinouts
LVDS Async.
VREF
Function
I/O, L201P
Bank
Pin
E4
F5
Output Option
Option
XC2S400E
XC2S600E
I/O, L201P
I/O, L201N
7
7
7
XC2S400E
XC2S400E
XC2S600E
-
-
I/O, L201P_Y
I/O, L201N_Y
I/O, L201N
I/O, VREF Bank 7,
L200P
F4
All
I/O, VREF Bank 7,
L200P
I/O, VREF Bank 7,
L200P_Y
I/O, L200N
I/O, L199P
I/O, L199N
I/O, L198P
I/O, L198N
I/O, L197P
I/O, L197N
7
7
7
7
7
7
7
7
F3
F2
XC2S600E
XC2S600E
XC2S600E
XC2S400E
XC2S400E
XC2S600E
XC2S600E
All
-
-
I/O, L200N
-
I/O, L200N_Y
I/O, L199P_Y
I/O, L199N_Y
I/O, L198P
F1
-
I/O
G6
G5
G4
G3
G2
-
I/O, L198P_Y
I/O, L198N_Y
I/O, L197P
I/O, L197N
-
I/O, L198N
-
I/O, L197P_Y
I/O, L197N_Y
-
I/O, VREF Bank 7,
L196P_YY
All
I/O, VREF Bank 7,
L196P_YY
I/O, VREF Bank 7,
L196P_YY
I/O, L196N_YY
I/O
7
7
7
7
7
7
7
7
G1
H7
H6
H5
J8
All
-
I/O, L196N_YY
I/O
I/O, L196N_YY
I/O
-
-
I/O, L195P_YY
I/O, L195N_YY
I/O
All
All
-
I/O, L195P_YY
I/O, L195N_YY
-
I/O, L195P_YY
I/O, L195N_YY
I/O
-
-
-
I/O, L194P
I/O, L194N
I/O, L193P
H2
H1
J7
XC2S400E
XC2S400E
XC2S600E
-
I/O, L194P_Y
I/O, L194N_Y
I/O
I/O, L194P
I/O, L194N
-
XC2S600E
I/O, VREF Bank 7,
L193P_Y
I/O, L193N
I/O
7
7
7
7
7
7
J6
J5
J4
J3
K5
J2
XC2S600E
-
-
-
I/O, L193N_Y
I/O
-
I/O
I/O, L192P_YY
I/O, L192N_YY
I/O
All
All
-
-
I/O, L192P_YY
I/O, L192N_YY
I/O
I/O, L192P_YY
I/O, L192N_YY
I/O
-
-
I/O, VREF Bank 7,
L191P_YY
All
All
I/O, VREF Bank 7,
L191P_YY
I/O, VREF Bank 7,
L191P_YY
I/O, L191N_YY
I/O, L190P_YY
I/O, L190N_YY
I/O
7
7
7
7
7
7
7
J1
K8
K7
K4
K3
K2
K1
All
All
All
-
-
-
-
-
-
-
-
I/O, L191N_YY
I/O, L190P_YY
I/O, L190N_YY
-
I/O, L191N_YY
I/O, L190P_YY
I/O, L190N_YY
I/O
I/O, L189P_YY
I/O, L189N_YY
I/O
All
All
-
I/O, L189P_YY
I/O, L189N_YY
-
I/O, L189P_YY
I/O, L189N_YY
I/O
90
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Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
Device-Specific Pinouts
FG676 Pinouts (XC2S400E, XC2S600E) (Continued)
Pad Name
LVDS Async.
VREF
Function
I/O, L188P
Bank
Pin
L8
Output Option
Option
XC2S400E
I/O, L188P_Y
I/O, L188N_Y
I/O, L187P
I/O, L187N
-
XC2S600E
I/O, L188P
I/O, L188N
I/O, L187P_Y
I/O, L187N_Y
I/O
7
7
7
7
7
7
7
7
7
7
7
XC2S400E
XC2S400E
XC2S600E
XC2S600E
-
-
-
I/O, L188N
I/O, L187P
I/O, L187N
I/O
L7
L6
-
L5
-
L3
-
I/O, L186P
I/O, L186N
I/O
L2
XC2S600E
XC2S600E
-
-
I/O, L186P
I/O, L186N
-
I/O, L186P_Y
I/O, L186N_Y
I/O
L1
-
M9
M8
M7
M6
-
I/O, L185P
I/O, L185N
XC2S600E
XC2S600E
All
-
I/O, L185P
I/O, L185N
I/O, L185P_Y
I/O, L185N_Y
-
I/O, VREF Bank 7,
L184P_YY
All
I/O, VREF Bank 7,
L184P_YY
I/O, VREF Bank 7,
L184P_YY
I/O, L184N_YY
I/O
7
7
7
7
7
7
7
7
M5
M4
M2
M1
N9
N8
N7
N6
All
-
-
I/O, L184N_YY
-
I/O, L184N_YY
I/O
-
I/O, L183P_YY
I/O, L183N_YY
I/O
All
All
-
I/O, L183P_YY
I/O, L183N_YY
-
I/O, L183P_YY
I/O, L183N_YY
I/O
-
-
-
I/O, L182P
I/O, L182N
XC2S400E
XC2S400E
XC2S600E
-
I/O, L182P_Y
I/O, L182N_Y
I/O, L182P
I/O, L182N
-
I/O, VREF Bank 7,
L181P
All
I/O, VREF Bank 7,
L181P
I/O, VREF Bank 7,
L181P_Y
I/O, L181N
7
7
7
7
7
7
7
N5
N4
N3
N2
N1
P1
P2
XC2S600E
-
-
-
-
-
-
-
I/O, L181N
I/O, L181N_Y
I/O
I/O
-
-
I/O, L180P_YY
I/O, L180N_YY
I/O
All
All
-
I/O, L180P_YY
I/O, L180N_YY
-
I/O, L180P_YY
I/O, L180N_YY
I/O
I/O, L179P_YY
I/O (IRDY), L179N_YY
All
All
I/O, L179P_YY
I/O, L179P_YY
I/O (IRDY), L179N_YY
I/O (IRDY),
L179N_YY
I/O (TRDY), L178P
I/O, L178N
I/O, L177P
I/O, L177N
I/O
6
6
6
6
6
6
P3
P4
P5
P6
P7
P8
XC2S600E
XC2S600E
XC2S600E
XC2S600E
-
-
-
-
-
-
-
I/O (TRDY)
I/O (TRDY), L178P_Y
I/O, L178N_Y
I/O, L177P_Y
I/O, L177N_Y
I/O
-
-
I/O
I/O
I/O, L176P
XC2S600E
I/O, L176P
I/O, L176P_Y
DS077-4 (2.3) June 18, 2008
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91
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
FG676 Pinouts (XC2S400E, XC2S600E) (Continued)
Pad Name
Device-Specific Pinouts
LVDS Async.
VREF
Function
Bank
Pin
Output Option
Option
XC2S400E
XC2S600E
I/O, VREF Bank 6,
L176N
6
P9
XC2S600E
All
I/O, VREF Bank 6,
L176N
I/O, VREF Bank 6,
L176N_Y
I/O, L175P
I/O, L175N
I/O
6
6
6
6
6
6
6
6
R1
R2
R4
R5
R6
R7
R8
R9
XC2S400E
-
-
I/O, L175P_Y
I/O, L175N_Y
-
I/O, L175P
I/O, L175N
I/O
XC2S400E
-
-
I/O, L174P_YY
I/O, L174N_YY
I/O
All
All
-
-
I/O, L174P_YY
I/O, L174N_YY
-
I/O, L174P_YY
I/O, L174N_YY
I/O
-
-
I/O, L173P_YY
All
All
-
I/O, L173P_YY
I/O, L173P_YY
I/O, VREF Bank 6,
L173N_YY
All
I/O, VREF Bank 6,
L173N_YY
I/O, VREF Bank 6,
L173N_YY
I/O, L172P
I/O, L172N
I/O
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
T1
T2
T3
T5
T6
U1
T7
T8
U2
U3
U7
U4
U5
U8
V1
V2
V3
V4
XC2S600E
-
-
I/O, L172P
I/O, L172P_Y
I/O, L172N_Y
I/O
XC2S600E
I/O, L172N
-
-
-
I/O, L171P
I/O, L171N
I/O
XC2S600E
-
I/O, L171P
I/O, L171P_Y
I/O, L171N_Y
I/O
XC2S600E
-
I/O, L171N
-
-
-
I/O, L170P
I/O, L170N
I/O, L169P
I/O, L169N
I/O
XC2S600E
-
I/O, L170P
I/O, L170P_Y
I/O, L170N_Y
I/O, L169P
I/O, L169N
I/O
XC2S600E
-
I/O, L170N
XC2S400E
-
I/O, L169P_Y
XC2S400E
-
I/O, L169N_Y
-
-
-
I/O, L168P
I/O, L168N
I/O
XC2S600E
-
-
I/O, L168P_Y
I/O, L168N_Y
I/O
XC2S600E
-
I/O
I/O
-
-
I/O, L167P_YY
I/O, L167N_YY
I/O
All
All
-
-
I/O, L167P_YY
I/O, L167N_YY
I/O
I/O, L167P_YY
I/O, L167N_YY
I/O
-
-
I/O, VREF Bank 6,
L166P_YY
All
All
I/O, VREF Bank 6,
L166P_YY
I/O, VREF Bank 6,
L166P_YY
I/O, L166N_YY
I/O, L165P_YY
I/O, L165N_YY
I/O
6
6
6
6
6
V5
V6
V7
V8
W1
All
-
-
-
-
-
I/O, L166N_YY
I/O, L165P_YY
I/O, L165N_YY
-
I/O, L166N_YY
I/O, L165P_YY
I/O, L165N_YY
I/O
All
All
-
I/O, L164P
XC2S600E
I/O, L164P
I/O, L164P_Y
92
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Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
Device-Specific Pinouts
FG676 Pinouts (XC2S400E, XC2S600E) (Continued)
Pad Name
LVDS Async.
VREF
Function
I/O, L164N
Bank
Pin
Output Option
Option
XC2S400E
XC2S600E
6
W2
XC2S600E
XC2S600E
I/O, L164N
I/O, VREF Bank 6,
L164N_Y
I/O, L163P
I/O, L163N
I/O
6
6
6
6
6
6
6
6
W5
W6
W7
Y1
Y2
Y3
Y4
Y5
XC2S400E
-
-
I/O, L163P_Y
I/O, L163N_Y
I/O
I/O, L163P
I/O, L163N
I/O
XC2S400E
-
-
I/O, L162P_YY
I/O, L162N_YY
I/O
All
All
-
-
I/O, L162P_YY
I/O, L162N_YY
-
I/O, L162P_YY
I/O, L162N_YY
I/O
-
-
I/O, L161P_YY
All
All
-
I/O, L161P_YY
I/O, L161P_YY
I/O, VREF Bank 6,
L161N_YY
All
I/O, VREF Bank 6,
L161N_YY
I/O, VREF Bank 6,
L161N_YY
I/O
6
6
6
6
6
6
6
6
Y6
-
-
-
I/O
I/O
I/O, L160P_YY
I/O, L160N_YY
I/O, L159P
I/O, L159N
I/O
AA1
AA2
AA3
AA4
Y7
All
I/O, L160P_YY
I/O, L160N_YY
I/O, L159P
I/O, L159N
-
I/O, L160P_YY
I/O, L160N_YY
I/O, L159P_Y
I/O, L159N_Y
I/O
All
-
XC2S600E
XC2S600E
-
-
-
-
I/O, L158P
AA5
AB5
XC2S600E
XC2S600E
-
I/O, L158P
I/O, L158P_Y
I/O, VREF Bank 6,
L158N
All
I/O, VREF Bank 6,
L158N
I/O, VREF Bank 6,
L158N_Y
I/O, L157P
I/O, L157N
I/O, L156P
I/O, L156N
I/O, L155P_YY
I/O, L155N_YY
I/O, L154P
I/O, L154N
I/O, L153P_YY
I/O, L153N_YY
M1
6
6
6
6
6
6
6
6
6
6
-
AB1
AB2
AC1
AC2
AC3
AB4
AD1
AD2
AE1
AF2
AE3
AF3
AD4
XC2S400E
-
-
-
-
-
-
-
-
-
-
-
-
-
I/O, L157P_Y
I/O, L157P
I/O, L157N
I/O, L156P_Y
I/O, L156N_Y
I/O, L155P_YY
I/O, L155N_YY
I/O, L154P
I/O, L154N
I/O, L153P_YY
I/O, L153N_YY
M1
XC2S400E
I/O, L157N_Y
XC2S600E
-
XC2S600E
I/O
All
All
-
I/O, L155P_YY
I/O, L155N_YY
-
-
-
All
All
-
I/O, L153P_YY
I/O, L153N_YY
M1
M0
M2
M0
-
-
M0
M2
-
-
M2
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Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
FG676 Pinouts (XC2S400E, XC2S600E) (Continued)
Pad Name
Device-Specific Pinouts
XC2S400E XC2S600E
LVDS Async.
Output Option
VREF
Option
Function
Bank
Pin
I/O
5
5
5
5
5
5
5
5
5
5
AC5
AE4
AF4
AE5
AF5
AA6
AB6
AC6
AD6
AE6
-
-
-
I/O
I/O
I/O, L152N
I/O, L152P
-
I/O
I/O, L152N
I/O, L152P
I/O, L151N
I/O, L151P
I/O, L150N
I/O, L150P
I/O, L149N_YY
I/O, L149P_YY
-
-
-
I/O, L151N
I/O, L151P
-
-
-
-
XC2S400E
XC2S400E
All
-
I/O
I/O, L150N
I/O, L150P
-
I/O, L150N_Y
I/O, L150P_Y
I/O, L149N_YY
I/O, L149P_YY
-
I/O, L149N_YY
I/O, L149P_YY
-
All
-
I/O, VREF Bank 5,
L148N_YY
All
All
I/O, VREF Bank 5,
L148N_YY
I/O, VREF Bank 5,
L148N_YY
I/O, L148P_YY
I/O, L147N
5
5
5
5
5
5
5
5
AF6
AA7
AB7
AC7
AD7
AE7
AF7
Y8
All
-
-
I/O, L148P_YY
-
I/O, L148P_YY
I/O, L147N_Y
I/O, L147P_Y
I/O, L146N_YY
I/O, L146P_YY
I/O, L145N_YY
I/O, L145P_YY
XC2S600E
I/O, L147P
XC2S600E
-
I/O
I/O, L146N_YY
I/O, L146P_YY
I/O, L145N_YY
I/O, L145P_YY
All
All
All
All
All
-
I/O, L146N_YY
I/O, L146P_YY
I/O, L145N_YY
I/O, L145P_YY
-
-
-
I/O, VREF Bank 5,
L144N_YY
All
I/O, VREF Bank 5,
L144N_YY
I/O, VREF Bank 5,
L144N_YY
I/O, L144P_YY
I/O, L143N_YY
I/O, L143P_YY
I/O
5
5
5
5
5
5
5
AA8
AE8
AF8
AB8
W9
All
-
I/O, L144P_YY
I/O, L143N_YY
I/O, L143P_YY
I/O
I/O, L144P_YY
I/O, L143N_YY
I/O, L143P_YY
I/O
All
All
-
-
-
-
I/O, L142N
I/O, L142P
I/O, L141N
XC2S600E
XC2S600E
XC2S600E
-
I/O, L142N
I/O, L142P
-
I/O, L142N_Y
I/O, L142P_Y
Y9
-
AA9
XC2S600E
I/O, VREF Bank 5,
L141N_Y
I/O, L141P
5
5
5
5
5
5
AB9
AC9
AD9
AE9
AF9
W10
XC2S600E
-
-
I/O
I/O, L141P_Y
I/O, L140N_YY
I/O, L140P_YY
I/O, L139N_YY
I/O, L139P_YY
I/O, L140N_YY
I/O, L140P_YY
I/O, L139N_YY
I/O, L139P_YY
All
All
All
All
All
I/O, L140N_YY
I/O, L140P_YY
I/O, L139N_YY
I/O, L139P_YY
-
-
-
I/O, VREF Bank 5,
L138N_YY
All
I/O, VREF Bank 5,
L138N_YY
I/O, VREF Bank 5,
L138N_YY
94
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DS077-4 (2.3) June 18, 2008
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
Device-Specific Pinouts
FG676 Pinouts (XC2S400E, XC2S600E) (Continued)
Pad Name
LVDS Async.
VREF
Function
I/O, L138P_YY
I/O, L137N_YY
I/O, L137P_YY
I/O
Bank
5
Pin
Output Option
Option
XC2S400E
I/O, L138P_YY
I/O, L137N_YY
I/O, L137P_YY
-
XC2S600E
I/O, L138P_YY
I/O, L137N_YY
I/O, L137P_YY
I/O
Y10
All
-
-
5
AB10
AC10
AD10
AE10
AF10
AD11
W11
Y11
All
5
All
-
5
-
-
I/O, L136N
I/O, L136P
I/O
5
XC2S600E
-
I/O, L136N
I/O, L136P
-
I/O, L136N_Y
I/O, L136P_Y
I/O
5
XC2S600E
-
5
-
-
I/O, L135N_YY
I/O, L135P_YY
I/O, L134N_YY
I/O, L134P_YY
I/O
5
All
All
All
All
-
-
I/O, L135N_YY
I/O, L135P_YY
I/O, L134N_YY
I/O, L134P_YY
-
I/O, L135N_YY
I/O, L135P_YY
I/O, L134N_YY
I/O, L134P_YY
I/O
5
-
5
AA11
AB11
V12
-
5
-
5
-
I/O, L133N
I/O, L133P
I/O
5
AE11
AF11
W12
Y12
-
-
I/O, L133N
I/O, L133P
-
I/O, L133N
I/O, L133P
I/O
5
-
-
5
-
-
I/O, L132N_YY
I/O, L132P_YY
5
All
All
All
-
I/O, L132N_YY
I/O, L132P_YY
I/O, L132N_YY
I/O, L132P_YY
5
AA12
AB12
-
I/O, VREF Bank 5,
L131N_YY
5
All
I/O, VREF Bank 5,
L131N_YY
I/O, VREF Bank 5,
L131N_YY
I/O, L131P_YY
I/O
5
5
5
5
5
5
5
5
AC12
V13
All
-
-
I/O, L131P_YY
-
I/O, L131P_YY
I/O
-
I/O, L130N_YY
I/O, L130P_YY
I/O
AE12
AF12
W13
Y13
All
All
-
I/O, L130N_YY
I/O, L130P_YY
-
I/O, L130N_YY
I/O, L130P_YY
I/O
-
-
-
I/O, L129N
I/O, L129P
XC2S600E
XC2S600E
XC2S600E
-
I/O, L129N
I/O, L129P
I/O, L129N_Y
I/O, L129P_Y
AA13
AB13
-
I/O, VREF Bank 5,
L128N
All
I/O, VREF Bank 5,
L128N
I/O, VREF Bank 5,
L128N_Y
I/O, L128P
I/O
5
5
5
5
5
5
AC13
AD13
V14
XC2S600E
-
-
-
-
-
-
I/O, L128P
I/O, L128P_Y
I/O
-
-
-
-
-
-
I/O, L127N
I/O, L127P
I/O (DLL), L126N
GCK1, I
I/O
-
I/O, L127N
I/O, L127P
I/O (DLL), L126N
GCK1, I
W14
AE13
AF13
I/O (DLL), L126N
GCK1, I
DS077-4 (2.3) June 18, 2008
www.xilinx.com
95
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
FG676 Pinouts (XC2S400E, XC2S600E) (Continued)
Pad Name
Device-Specific Pinouts
LVDS Async.
VREF
Function
Bank
Pin
Output Option
Option
XC2S400E
XC2S600E
GCK0, I
4
4
4
4
4
4
4
4
AF14
AE14
AD14
AC14
AB14
AC15
AA14
Y14
-
-
-
GCK0, I
I/O (DLL), L126P
-
GCK0, I
I/O (DLL), L126P
I/O
I/O (DLL), L126P
I/O
-
-
-
I/O, L125N
I/O, L125P
I/O
-
-
I/O, L125N
I/O, L125P
-
I/O, L125N
I/O, L125P
I/O
-
-
-
-
I/O, L124N
XC2S600E
XC2S600E
-
I/O, L124N
I/O, L124N_Y
I/O, VREF Bank 4,
L124P
All
I/O, VREF Bank 4,
L124P
I/O, VREF Bank 4,
L124P_Y
I/O, L123N
I/O, L123P
I/O
4
4
4
4
4
4
4
4
AF15
AE15
AB15
AA15
Y15
XC2S600E
-
-
I/O, L123N
I/O, L123P
-
I/O, L123N_Y
I/O, L123P_Y
I/O
XC2S600E
-
-
I/O, L122N_YY
I/O, L122P_YY
I/O
All
All
-
-
I/O, L122N_YY
I/O, L122P_YY
-
I/O, L122N_YY
I/O, L122P_YY
I/O
-
AF16
W15
V15
-
I/O, L121N_YY
All
All
-
I/O, L121N_YY
I/O, L121N_YY
I/O, VREF Bank 4,
L121P_YY
All
I/O, VREF Bank 4,
L121P_YY
I/O, VREF Bank 4,
L121P_YY
I/O, L120N_YY
I/O, L120P_YY
I/O
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
AE16
AD16
AB16
AA16
Y16
All
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I/O, L120N_YY
I/O, L120P_YY
-
I/O, L120N_YY
I/O, L120P_YY
I/O
All
-
I/O, L119N
I/O, L119P
I/O
-
I/O, L119N
I/O, L119P
-
I/O, L119N
I/O, L119P
I/O
-
W16
-
I/O, L118N_YY
I/O, L118P_YY
I/O, L117N_YY
I/O, L117P_YY
I/O
AF17
AE17
AD17
AC17
AB17
Y17
All
I/O, L118N_YY
I/O, L118P_YY
I/O, L117N_YY
I/O, L117P_YY
-
I/O, L118N_YY
I/O, L118P_YY
I/O, L117N_YY
I/O, L117P_YY
I/O
All
All
All
-
I/O, L116N
I/O, L116P
I/O
XC2S600E
I/O, L116N
I/O, L116P
-
I/O, L116N_Y
I/O, L116P_Y
I/O
W17
XC2S600E
AF18
AE18
AD18
-
I/O, L115N_YY
I/O, L115P_YY
All
All
I/O, L115N_YY
I/O, L115P_YY
I/O, L115N_YY
I/O, L115P_YY
96
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DS077-4 (2.3) June 18, 2008
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
Device-Specific Pinouts
FG676 Pinouts (XC2S400E, XC2S600E) (Continued)
Pad Name
LVDS Async.
VREF
Function
Bank
Pin
Output Option
Option
XC2S400E
XC2S600E
I/O
4
4
AC18
AB18
-
-
-
I/O
I/O
I/O, VREF Bank 4,
L114N
All
I/O, VREF Bank 4,
L114N
I/O, VREF Bank 4,
L114N
I/O, L114P
I/O, L113N
I/O, L113P
I/O
4
4
4
4
4
4
AA18
Y18
-
-
I/O, L114P
I/O, L114P
I/O, L113N
I/O, L113P
I/O
-
-
I/O, L113N
W18
-
-
I/O, L113P
AB19
AF19
AE19
-
-
I/O
I/O
-
I/O, L112N
I/O, L112P
XC2S600E
XC2S600E
-
I/O, L112N_Y
XC2S600E
I/O, VREF Bank 4,
L112P_Y
I/O, L111N
I/O, L111P
I/O
4
4
4
4
4
4
4
4
AA19
Y19
XC2S600E
-
-
I/O, L111N
I/O, L111P
-
I/O, L111N_Y
I/O, L111P_Y
I/O
XC2S600E
AF20
AE20
AD20
AC20
AB20
AA20
-
-
I/O, L110N
I/O, L110P
I/O
XC2S600E
-
I/O, L110N
I/O, L110P
I/O
I/O, L110N_Y
I/O, L110P_Y
I/O
XC2S600E
-
-
-
I/O, L109N_YY
All
All
-
I/O, L109N_YY
I/O, L109N_YY
I/O, VREF Bank 4,
L109P_YY
All
I/O, VREF Bank 4,
L109P_YY
I/O, VREF Bank 4,
L109P_YY
I/O
4
4
4
4
4
4
4
4
Y20
-
-
-
-
I/O
I/O, L108N
I/O, L108P
I/O, L107N
I/O, L107P
-
I/O
I/O, L108N
I/O, L108P
I/O, L107N
I/O, L107P
I/O
AF21
AE21
AD21
AC21
AC22
AF22
AE22
I/O, L108N
I/O, L108P
I/O, L107N
I/O, L107P
I/O
-
-
-
-
-
-
-
-
I/O, L106N_YY
All
All
-
I/O, L106N_YY
I/O, L106N_YY
I/O, VREF Bank 4,
L106P_YY
All
I/O, VREF Bank 4,
L106P_YY
I/O, VREF Bank 4,
L106P_YY
I/O, L105N_YY
I/O, L105P_YY
I/O, L104N_YY
I/O, L104P_YY
I/O, L103N
4
4
4
4
4
4
4
4
AB21
AA21
AF23
AE23
AD23
AE24
AF24
AF25
All
-
-
-
-
-
-
-
-
I/O, L105N_YY
I/O, L105P_YY
I/O, L104N_YY
I/O, L104P_YY
I/O
I/O, L105N_YY
I/O, L105P_YY
I/O, L104N_YY
I/O, L104P_YY
I/O, L103N_Y
I/O, L103P_Y
I/O, L102N_YY
I/O, L102P_YY
All
All
All
XC2S600E
XC2S600E
All
I/O, L103P
-
I/O, L102N_YY
I/O, L102P_YY
I/O, L102N_YY
I/O, L102P_YY
All
DS077-4 (2.3) June 18, 2008
www.xilinx.com
97
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
FG676 Pinouts (XC2S400E, XC2S600E) (Continued)
Pad Name
Device-Specific Pinouts
LVDS Async.
VREF
Function
Bank
Pin
Output Option
Option
XC2S400E
XC2S600E
DONE
3
-
AE26
AC24
AD25
AD26
AC25
AC26
AB22
AB23
AB25
AB26
AA23
AA24
AA25
-
-
-
DONE
DONE
PROGRAM
I/O (INIT), L101N_YY
I/O (D7), L101P_YY
I/O, L100N
-
PROGRAM
PROGRAM
3
3
3
3
3
3
3
3
3
3
3
All
-
I/O (INIT), L101N_YY I/O (INIT), L101N_YY
All
-
I/O (D7), L101P_YY
I/O (D7), L101P_YY
I/O, L100N
-
-
-
I/O, L100P
-
-
-
I/O, L100P
I/O, L99N
XC2S600E
-
-
I/O, L99N_Y
I/O, L99P_Y
I/O, L98N_YY
I/O, L98P_YY
I/O, L97N
I/O, L99P
XC2S600E
-
I/O
I/O, L98N_YY
I/O, L98P_YY
I/O, L97N
All
-
I/O, L98N_YY
I/O, L98P_YY
I/O, L97N_Y
I/O, L97P_Y
All
-
-
-
I/O, L97P
-
-
I/O, L97P
I/O, VREF Bank 3,
L96N
XC2S600E
All
I/O, VREF Bank 3,
L96N
I/O, VREF Bank 3,
L96N_Y
I/O, L96P
I/O, L95N
I/O, L95P
I/O, L94N
I/O, L94P
I/O, L93N
I/O, L93P
3
3
3
3
3
3
3
3
AA26
AA22
Y22
XC2S600E
XC2S600E
XC2S600E
XC2S400E
XC2S400E
XC2S600E
XC2S600E
All
-
-
I/O, L96P
-
I/O, L96P_Y
I/O, L95N_Y
I/O, L95P_Y
I/O, L94N
-
I/O
Y23
-
I/O, L94N_Y
I/O, L94P_Y
I/O, L93N
I/O, L93P
Y24
-
I/O, L94P
Y25
-
I/O, L93N_Y
I/O, L93P_Y
Y26
-
I/O, VREF Bank 3,
L92N_YY
W21
All
I/O, VREF Bank 3,
L92N_YY
I/O, VREF Bank 3,
L92N_YY
I/O, L92P_YY
I/O
3
3
3
3
3
3
3
3
W22
Y21
W25
W26
W20
V19
V20
V21
All
-
I/O, L92P_YY
I/O, L92P_YY
I/O
-
-
-
I/O, L91N_YY
I/O, L91P_YY
I/O
All
All
-
I/O, L91N_YY
I/O, L91P_YY
I/O
I/O, L91N_YY
I/O, L91P_YY
I/O
-
-
-
I/O, L90N
I/O, L90P
I/O, L89N
XC2S400E
XC2S400E
XC2S600E
-
I/O, L90N_Y
I/O, L90P_Y
-
I/O, L90N
I/O, L90P
-
XC2S600E
I/O, VREF Bank 3,
L89N_Y
I/O, L89P
I/O
3
3
3
V22
V23
V24
XC2S600E
-
-
-
I/O
I/O
I/O, L89P_Y
I/O
-
I/O, L88N_YY
All
I/O, L88N_YY
I/O, L88N_YY
98
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DS077-4 (2.3) June 18, 2008
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
Device-Specific Pinouts
FG676 Pinouts (XC2S400E, XC2S600E) (Continued)
Pad Name
LVDS Async.
VREF
Function
I/O, L88P_YY
Bank
Pin
V25
V26
U19
Output Option
Option
XC2S400E
I/O, L88P_YY
I/O
XC2S600E
I/O, L88P_YY
I/O
3
3
3
All
-
-
-
I/O
I/O, VREF Bank 3,
L87N_YY
All
All
I/O, VREF Bank 3,
L87N_YY
I/O, VREF Bank 3,
L87N_YY
I/O (D6), L87P_YY
I/O (D5), L86N_YY
I/O, L86P_YY
I/O
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
U20
U22
U23
U24
U25
U26
R18
T19
T20
T21
T22
T24
T25
T26
R19
R20
R21
R22
All
All
-
-
I/O (D6), L87P_YY
I/O (D6), L87P_YY
I/O (D5), L86N_YY
I/O, L86P_YY
I/O
I/O (D5), L86N_YY
All
-
I/O, L86P_YY
-
-
-
-
I/O, L85N
I/O, L85P
I/O
XC2S600E
XC2S600E
-
-
I/O, L85N_Y
I/O, L85P_Y
I/O
-
I/O
-
I/O
I/O, L84N
I/O, L84P
I/O, L83N
I/O, L83P
I/O
XC2S400E
XC2S400E
XC2S600E
XC2S600E
-
-
I/O, L84N_Y
I/O, L84P_Y
I/O, L83N
I/O, L83P
-
I/O, L84N
-
I/O, L84P
-
I/O, L83N_Y
I/O, L83P_Y
I/O
-
-
I/O, L82N
I/O, L82P
I/O
XC2S600E
XC2S600E
-
-
I/O, L82N
I/O, L82P
-
I/O, L82N_Y
I/O, L82P_Y
I/O
-
-
I/O, L81N
I/O, L81P
XC2S600E
XC2S600E
All
-
I/O, L81N
I/O, L81P
I/O, L81N_Y
I/O, L81P_Y
-
I/O, VREF Bank 3,
L80N_YY
All
I/O, VREF Bank 3,
L80N_YY
I/O, VREF Bank 3,
L80N_YY
I/O (D4), L80P_YY
I/O
3
3
3
3
3
3
3
3
R23
P18
R25
R26
P19
P20
P21
P22
All
-
-
I/O (D4), L80P_YY
-
I/O (D4), L80P_YY
I/O
-
I/O, L79N_YY
I/O, L79P_YY
I/O
All
All
-
I/O, L79N_YY
I/O, L79P_YY
-
I/O, L79N_YY
I/O, L79P_YY
I/O
-
-
-
I/O, L78N
I/O, L78P
XC2S400E
XC2S400E
XC2S600E
-
I/O, L78N_Y
I/O, L78P_Y
I/O, L78N
I/O, L78P
-
I/O, VREF Bank 3,
L77N
All
I/O, VREF Bank 3,
L77N
I/O, VREF Bank 3,
L77N_Y
I/O, L77P
I/O
3
3
3
3
P23
P24
P25
P26
XC2S600E
-
-
-
-
I/O, L77P
-
I/O, L77P_Y
I/O
-
I/O, L76N_YY
I/O, L76P_YY
All
All
I/O, L76N_YY
I/O, L76P_YY
I/O, L76N_YY
I/O, L76P_YY
DS077-4 (2.3) June 18, 2008
www.xilinx.com
99
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
FG676 Pinouts (XC2S400E, XC2S600E) (Continued)
Pad Name
Device-Specific Pinouts
XC2S400E XC2S600E
I/O
I/O (TRDY)
LVDS Async.
Output Option
VREF
Option
Function
Bank
Pin
N18
N24
I/O
3
3
-
-
-
-
-
I/O (TRDY)
I/O (TRDY)
I/O (IRDY), L75N_YY
I/O, L75P_YY
I/O
2
2
2
2
2
2
2
2
N26
N25
N19
N23
N22
M23
N21
N20
All
-
-
I/O (IRDY), L75N_YY I/O (IRDY), L75N_YY
All
I/O, L75P_YY
I/O, L75P_YY
I/O
-
-
-
I/O, L74N
I/O, L74P
I/O
XC2S600E
XC2S600E
-
-
-
I/O
I/O, L74N_Y
I/O, L74P_Y
I/O
-
-
I/O
I/O, L73N
XC2S600E
XC2S600E
-
I/O, L73N
I/O, L73N_Y
I/O, VREF Bank 2,
L73P
All
I/O, VREF Bank 2,
L73P
I/O, VREF Bank 2,
L73P_Y
I/O, L72N
I/O, L72P
I/O
2
2
2
2
2
2
2
2
M26
M25
M22
M21
M20
L26
XC2S400E
-
-
I/O, L72N_Y
I/O, L72P_Y
-
I/O, L72N
I/O, L72P
XC2S400E
-
-
I/O
I/O, L71N_YY
I/O, L71P_YY
I/O
All
All
-
-
I/O, L71N_YY
I/O, L71P_YY
-
I/O, L71N_YY
I/O, L71P_YY
I/O
-
-
I/O (D3), L70N_YY
M19
M18
All
All
-
I/O (D3), L70N_YY
I/O (D3), L70N_YY
I/O, VREF Bank 2,
L70P_YY
All
I/O, VREF Bank 2,
L70P_YY
I/O, VREF Bank 2,
L70P_YY
I/O, L69N
I/O, L69P
I/O
2
2
2
2
2
2
2
2
2
2
2
2
2
2
L25
L24
L22
L21
L20
L19
K26
K25
K24
K23
K22
K20
K19
J26
XC2S600E
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I/O, L69N
I/O, L69N_Y
I/O, L69P_Y
I/O
XC2S600E
I/O, L69P
-
-
I/O, L68N
I/O, L68P
I/O
XC2S600E
I/O, L68N
I/O, L68N_Y
I/O, L68P_Y
I/O
XC2S600E
I/O, L68P
-
-
I/O, L67N
I/O, L67P
I/O, L66N
I/O, L66P
I/O
XC2S600E
I/O, L67N
I/O, L67N_Y
I/O, L67P_Y
I/O, L66N
I/O, L66P
I/O
XC2S600E
I/O, L67P
-
-
-
I/O
-
-
I/O, L65N
I/O, L65P
I/O
XC2S600E
XC2S600E
-
I/O
I/O
I/O
I/O, L65N_Y
I/O, L65P_Y
I/O
100
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DS077-4 (2.3) June 18, 2008
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
Device-Specific Pinouts
FG676 Pinouts (XC2S400E, XC2S600E) (Continued)
Pad Name
LVDS Async.
VREF
Function
I/O, L64N_YY
Bank
Pin
J25
J24
J23
J22
Output Option
Option
XC2S400E
I/O, L64N_YY
I/O (D2), L64P_YY
I/O (D1)
XC2S600E
I/O, L64N_YY
I/O (D2), L64P_YY
I/O (D1)
2
2
2
2
All
All
-
-
-
I/O (D2), L64P_YY
I/O (D1)
-
I/O, VREF Bank 2,
L63N_YY
All
All
I/O, VREF Bank 2,
L63N_YY
I/O, VREF Bank 2,
L63N_YY
I/O, L63P_YY
I/O, L62N_YY
I/O, L62P_YY
I/O
2
2
2
2
2
2
J21
J20
J19
H22
H26
H25
All
-
I/O, L63P_YY
I/O, L63P_YY
I/O, L62N_YY
I/O, L62P_YY
I/O
All
-
I/O, L62N_YY
All
-
-
I/O, L62P_YY
-
I/O
I/O
-
I/O, L61N
XC2S600E
XC2S600E
-
I/O, L61N_Y
I/O, L61P
XC2S600E
I/O, VREF Bank 2,
L61P_Y
I/O, L60N
I/O, L60P
I/O
2
2
2
2
2
2
2
2
H21
H20
G26
G25
G24
G23
G22
G21
XC2S400E
-
-
I/O, L60N_Y
I/O, L60P_Y
-
I/O, L60N
I/O, L60P
I/O
XC2S400E
-
-
I/O, L59N_YY
I/O, L59P_YY
I/O
All
All
-
-
I/O, L59N_YY
I/O, L59P_YY
I/O
I/O, L59N_YY
I/O, L59P_YY
I/O
-
-
I/O, L58N_YY
All
All
-
I/O, L58N_YY
I/O, L58N_YY
I/O, VREF Bank 2,
L58P_YY
All
I/O, VREF Bank 2,
L58P_YY
I/O, VREF Bank 2,
L58P_YY
I/O
2
2
2
2
2
2
2
2
G20
F26
F25
F24
F23
F22
E26
E25
-
-
-
I/O
I/O
I/O, L57N_YY
I/O, L57P_YY
I/O, L56N
I/O, L56P
I/O
All
I/O, L57N_YY
I/O, L57P_YY
I/O, L56N
I/O, L56P
-
I/O, L57N_YY
I/O, L57P_YY
I/O, L56N_Y
I/O, L56P_Y
I/O
All
-
XC2S600E
XC2S600E
-
-
-
-
I/O, L55N
XC2S600E
XC2S600E
-
I/O, L55N
I/O, L55N_Y
I/O, VREF Bank 2,
L55P
All
I/O, VREF Bank 2,
L55P
I/O, VREF Bank 2,
L55P_Y
I/O, L54N
2
2
2
2
2
2
E23
E22
F21
E21
D26
D25
XC2S400E
XC2S400E
All
-
-
-
-
-
-
I/O, L54N_Y
I/O, L54P_Y
I/O, L53N_YY
I/O, L53P_YY
I/O
I/O, L54N
I/O, L54P
I/O, L54P
I/O, L53N_YY
I/O, L53P_YY
I/O, L52N
I/O, L53N_YY
I/O, L53P_YY
I/O, L52N_Y
I/O, L52P_Y
All
XC2S600E
XC2S600E
I/O, L52P
-
DS077-4 (2.3) June 18, 2008
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101
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
FG676 Pinouts (XC2S400E, XC2S600E) (Continued)
Pad Name
Device-Specific Pinouts
XC2S400E XC2S600E
LVDS Async.
Output Option
VREF
Option
Function
I/O, L51N
Bank
Pin
D24
C25
C26
2
2
2
-
-
-
-
-
-
-
I/O, L51N
I/O, L51P
I/O, L51P
I/O (DIN, D0),
L50N_YY
All
I/O (DIN, D0),
L50N_YY
I/O (DIN, D0),
L50N_YY
I/O (DOUT, BUSY),
L50P_YY
2
B26
All
-
I/O (DOUT, BUSY),
L50P_YY
I/O (DOUT, BUSY),
L50P_YY
CCLK
TDO
TDI
2
2
-
A25
C23
D22
-
-
-
-
-
-
CCLK
TDO
TDI
CCLK
TDO
TDI
I/O (CS), L49P_YY
1
1
B24
A24
All
All
-
-
I/O (CS), L49P_YY
I/O (CS), L49P_YY
I/O (WRITE), L49N_YY
I/O (WRITE),
L49N_YY
I/O (WRITE),
L49N_YY
I/O, L48P
1
1
1
1
1
1
1
B23
A23
B22
A22
D21
C21
B21
-
-
-
I/O
I/O, L48P
I/O, L48N
I/O, L48N
-
XC2S400E
XC2S400E
All
-
I/O, L47P
-
I/O, L47P_Y
I/O, L47N_Y
I/O, L46P_YY
I/O, L46N_YY
I/O, L47P
I/O, L47N
-
I/O, L47N
I/O, L46P_YY
I/O, L46N_YY
-
I/O, L46P_YY
I/O, L46N_YY
All
-
I/O, VREF Bank 1,
L45P_YY
All
All
I/O, VREF Bank 1,
L45P_YY
I/O, VREF Bank 1,
L45P_YY
I/O, L45N_YY
I/O, L44P
1
1
1
1
1
1
1
1
A21
F20
E20
D20
C20
B20
A20
G19
All
-
-
I/O, L45N_YY
-
I/O, L45N_YY
I/O, L44P_Y
I/O, L44N_Y
I/O, L43P_YY
I/O, L43N_YY
I/O, L42P_YY
I/O, L42N_YY
XC2S600E
I/O, L44N
XC2S600E
-
I/O
I/O, L43P_YY
I/O, L43N_YY
I/O, L42P_YY
I/O, L42N_YY
All
All
All
All
All
-
I/O, L43P_YY
I/O, L43N_YY
I/O, L42P_YY
I/O, L42N_YY
-
-
-
I/O, VREF Bank 1,
L41P_YY
All
I/O, VREF Bank 1,
L41P_YY
I/O, VREF Bank 1,
L41P_YY
I/O, L41N_YY
I/O
1
1
1
1
1
1
F19
E19
B19
A19
H18
G18
All
-
-
-
-
-
-
I/O, L41N_YY
-
I/O, L41N_YY
I/O
-
I/O, L40P_YY
I/O, L40N_YY
I/O
All
I/O, L40P_YY
I/O, L40N_YY
I/O
I/O, L40P_YY
I/O, L40N_YY
I/O
All
-
I/O, L39P
XC2S600E
I/O, L39P
I/O, L39P_Y
102
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DS077-4 (2.3) June 18, 2008
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
Device-Specific Pinouts
FG676 Pinouts (XC2S400E, XC2S600E) (Continued)
Pad Name
LVDS Async.
VREF
Function
I/O, L39N
Bank
Pin
F18
D18
Output Option
Option
XC2S400E
I/O, L39N
-
XC2S600E
1
1
XC2S600E
XC2S600E
-
I/O, L39N_Y
I/O, L38P
XC2S600E
I/O, VREF Bank 1,
L38P_Y
I/O, L38N
1
1
1
1
1
1
C18
B18
A18
H17
G17
E18
XC2S600E
-
-
I/O
I/O, L38N_Y
I/O, L37P_YY
I/O, L37N_YY
I/O, L36P_YY
I/O, L36N_YY
I/O, L37P_YY
I/O, L37N_YY
I/O, L36P_YY
I/O, L36N_YY
All
All
All
All
All
I/O, L37P_YY
I/O, L37N_YY
I/O, L36P_YY
I/O, L36N_YY
-
-
-
I/O, VREF Bank 1,
L35P_YY
All
I/O, VREF Bank 1,
L35P_YY
I/O, VREF Bank 1,
L35P_YY
I/O, L35N_YY
I/O, L34P_YY
I/O, L34N_YY
I/O
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
E17
D17
C17
H16
B17
A17
G16
F16
E16
C16
B16
A16
J15
All
-
-
I/O, L35N_YY
I/O, L34P_YY
I/O, L34N_YY
-
I/O, L35N_YY
I/O, L34P_YY
I/O, L34N_YY
I/O
All
All
-
-
-
I/O, L33P
I/O, L33N
I/O
XC2S600E
-
I/O, L33P
I/O, L33N
-
I/O, L33P_Y
I/O, L33N_Y
I/O
XC2S600E
-
-
-
I/O, L32P_YY
I/O, L32N_YY
I/O, L31P_YY
I/O, L31N_YY
I/O
All
All
All
All
-
-
I/O, L32P_YY
I/O, L32N_YY
I/O, L31P_YY
I/O, L31N_YY
-
I/O, L32P_YY
I/O, L32N_YY
I/O, L31P_YY
I/O, L31N_YY
I/O
-
-
-
-
I/O, L30P
I/O, L30N
I/O
-
-
I/O, L30P
I/O, L30N
-
I/O, L30P
H15
G15
F15
E15
B15
-
-
I/O, L30N
-
-
I/O
I/O, L29P_YY
I/O, L29N_YY
All
All
All
-
I/O, L29P_YY
I/O, L29N_YY
I/O, L29P_YY
I/O, L29N_YY
-
I/O, VREF Bank 1,
L28P_YY
All
I/O, VREF Bank 1,
L28P_YY
I/O, VREF Bank 1,
L28P_YY
I/O, L28N_YY
I/O
1
1
1
1
1
1
1
A15
D15
J14
All
-
-
-
-
-
-
-
I/O, L28N_YY
-
I/O, L28N_YY
I/O
-
I/O, L27P_YY
I/O, L27N_YY
I/O
All
I/O, L27P_YY
I/O, L27N_YY
-
I/O, L27P_YY
I/O, L27N_YY
I/O
H14
G14
F14
E14
All
-
I/O, L26P
I/O, L26N
XC2S600E
XC2S600E
I/O, L26P
I/O, L26N
I/O, L26P_Y
I/O, L26N_Y
DS077-4 (2.3) June 18, 2008
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103
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
FG676 Pinouts (XC2S400E, XC2S600E) (Continued)
Pad Name
Device-Specific Pinouts
LVDS Async.
VREF
Function
Bank
Pin
Output Option
Option
XC2S400E
XC2S600E
I/O, VREF Bank 1,
L25P
1
D14
XC2S600E
All
I/O, VREF Bank 1,
L25P
I/O, VREF Bank 1,
L25P_Y
I/O, L25N
I/O
1
1
1
1
1
1
1
C14
J13
XC2S600E
-
-
-
-
-
-
-
I/O, L25N
-
I/O, L25N_Y
I/O
-
-
-
-
-
-
I/O, L24P
I/O, L24N
I/O
C13
D13
H13
B14
A14
I/O, L24P
I/O, L24N
-
I/O, L24P
I/O, L24N
I/O
I/O (DLL), L23P
GCK2, I
I/O (DLL), L23P
GCK2, I
I/O (DLL), L23P
GCK2, I
GCK3, I
0
0
0
0
0
0
0
A13
B13
E13
F13
G13
A12
B12
-
-
-
GCK3, I
I/O (DLL), L23N
-
GCK3, I
I/O (DLL), L23N
I/O
I/O (DLL), L23N
I/O
-
-
-
I/O, L22P_YY
I/O, L22N_YY
I/O, L21P
All
-
I/O, L22P_YY
I/O, L22N_YY
-
I/O, L22P_YY
I/O, L22N_YY
I/O, L21P_Y
All
-
XC2S600E
XC2S600E
-
I/O, VREF Bank 0,
L21N
All
I/O, VREF Bank 0
I/O, VREF Bank 0,
L21N_Y
I/O, L20P
I/O, L20N
I/O
0
0
0
0
0
0
0
0
D12
E12
F12
G12
H12
J12
XC2S600E
-
-
I/O, L20P
I/O, L20N
-
I/O, L20P_Y
I/O, L20N_Y
I/O
XC2S600E
-
-
I/O, L19P_YY
I/O, L19N_YY
I/O
All
All
-
-
I/O, L19P_YY
I/O, L19N_YY
-
I/O, L19P_YY
I/O, L19N_YY
I/O
-
-
I/O, L18P_YY
A11
B11
All
All
-
I/O, L18P_YY
I/O, L18P_YY
I/O, VREF Bank 0,
L18N_YY
All
I/O, VREF Bank 0,
L18N_YY
I/O, VREF Bank 0,
L18N_YY
I/O, L17P_YY
I/O, L17N_YY
I/O
0
0
0
0
0
0
0
0
0
E11
F11
C11
G11
H11
C10
A10
B10
D10
All
All
-
-
-
-
-
-
-
-
-
-
I/O, L17P_YY
I/O, L17N_YY
-
I/O, L17P_YY
I/O, L17N_YY
I/O
I/O, L16P
-
I/O, L16P
I/O, L16N
-
I/O, L16P
I/O, L16N
I/O
-
I/O, L16N
I/O
-
I/O, L15P_YY
I/O, L15N_YY
I/O, L14P_YY
All
All
All
I/O, L15P_YY
I/O, L15N_YY
I/O, L14P_YY
I/O, L15P_YY
I/O, L15N_YY
I/O, L14P_YY
104
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DS077-4 (2.3) June 18, 2008
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
Device-Specific Pinouts
FG676 Pinouts (XC2S400E, XC2S600E) (Continued)
Pad Name
LVDS Async.
VREF
Function
I/O, L14N_YY
Bank
Pin
E10
G10
A9
Output Option
Option
XC2S400E
I/O, L14N_YY
-
XC2S600E
I/O, L14N_YY
I/O
0
0
0
0
0
0
0
0
0
All
-
-
I/O
-
I/O, L13P
I/O, L13N
I/O
XC2S600E
-
I/O, L13P
I/O, L13N
-
I/O, L13P_Y
I/O, L13N_Y
I/O
B9
XC2S600E
-
H10
C9
-
All
All
-
-
I/O, L12P_YY
I/O, L12N_YY
I/O
-
I/O, L12P_YY
I/O, L12N_YY
I/O
I/O, L12P_YY
I/O, L12N_YY
I/O
D9
-
E9
-
I/O, VREF Bank 0,
L11P
F9
-
All
I/O, VREF Bank 0,
L11P
I/O, VREF Bank 0,
L11P
I/O, L11N
I/O, L10P
I/O, L10N
I/O
0
0
0
0
0
0
G9
A8
B8
H9
E8
F8
-
-
I/O, L11N
I/O, L10P
I/O, L10N
I/O
I/O, L11N
I/O, L10P
I/O, L10N
I/O
-
-
-
-
-
-
I/O, L9P
I/O, L9N
XC2S600E
XC2S600E
-
I/O
I/O, L9P_Y
XC2S600E
-
I/O, VREF Bank 0,
L9N_Y
I/O, L8P
I/O, L8N
I/O
0
0
0
0
0
0
0
0
A7
B7
G8
C7
D7
E7
F7
G7
XC2S600E
-
-
I/O, L8P
I/O, L8N
I/O
I/O, L8P_Y
I/O, L8N_Y
I/O
XC2S600E
-
-
I/O, L7P_YY
I/O, L7N_YY
I/O
All
All
-
-
I/O, L7P_YY
I/O, L7N_YY
-
I/O, L7P_YY
I/O, L7N_YY
I/O
-
-
I/O, L6P_YY
All
All
-
I/O, L6P_YY
I/O, L6P_YY
I/O, VREF Bank 0,
L6N_YY
All
I/O, VREF Bank 0,
L6N_YY
I/O, VREF Bank 0,
L6N_YY
I/O
0
0
0
0
0
0
0
0
A6
B6
C6
D6
E6
F6
A5
B5
-
-
-
-
I/O
I/O, L5P
I/O, L5N
I/O, L4P
I/O, L4N
-
I/O
I/O, L5P
I/O, L5N
I/O, L4P
I/O, L4N
I/O
I/O, L5P
I/O, L5N
I/O, L4P
I/O, L4N
I/O
-
-
-
-
-
-
-
-
I/O, L3P_YY
All
All
-
I/O, L3P_YY
I/O, L3P_YY
I/O, VREF Bank 0,
L3N_YY
All
I/O, VREF Bank 0,
L3N_YY
I/O, VREF Bank 0,
L3N_YY
I/O, L2P_YY
0
D5
All
-
I/O, L2P_YY
I/O, L2P_YY
DS077-4 (2.3) June 18, 2008
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105
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
FG676 Pinouts (XC2S400E, XC2S600E) (Continued)
Pad Name
Device-Specific Pinouts
LVDS Async.
VREF
Function
I/O, L2N_YY
Bank
Pin
E5
B4
C4
A3
B3
A4
A2
Output Option
Option
XC2S400E
XC2S600E
I/O, L2N_YY
I/O, L1P_YY
I/O, L1N_YY
I/O, L0P_Y
I/O, L0N_Y
I/O
0
0
0
0
0
0
-
All
-
-
-
-
-
-
-
I/O, L2N_YY
I/O, L1P_YY
I/O, L1N_YY
I/O, L0P
I/O, L0N
I/O
All
I/O, L1P_YY
All
I/O, L1N_YY
XC2S600E
I/O
-
XC2S600E
-
-
I/O
TCK
TCK
TCK
FG676 Differential Clock Pins
P Input
N Input
Clock
GCK0
GCK1
GCK2
GCK3
Bank
Pin
AF14
AF13
A14
Name
Pin
AE14
AE13
B14
Name
4
5
1
0
GCK0, I
GCK1, I
GCK2, I
GCK3, I
I/O (DLL), L126P
I/O (DLL), L126N
I/O (DLL), L23P
I/O (DLL), L23N
A13
B13
Additional FG676 Package Pins
VCCINT Pins
H8
H19
L10
U17
J9
L17
V9
J18
T10
V18
K10
K11
U10
W19
K16
U11
-
K17
T17
W8
U16
VCCO Bank 0 Pins
C5
C8
D11
D16
K18
T18
V16
V10
T4
J10
J11
J17
K12
K14
K13
K15
VCCO Bank 1 Pins
C19
C22
H24
R17
U15
U13
R10
K9
J16
VCCO Bank 2 Pins
E24
L18
L23
M17
W24
AD19
AD5
W3
N17
AB24
AD22
AD8
AB3
E3
VCCO Bank 3 Pins
P17
T23
U18
AC16
AC11
U9
VCCO Bank 4 Pins
U14
V17
VCCO Bank 5 Pins
U12
V11
VCCO Bank 6 Pins
P10
T9
L9
VCCO Bank 7 Pins
H3
L4
M10
N10
106
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DS077-4 (2.3) June 18, 2008
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
Additional FG676 Package Pins (Continued)
GND Pins
A1
C24
H4
A26
D4
B2
D8
B25
D19
K21
M3
C3
D23
L11
C12
F10
C15
F17
L13
M13
N13
P14
R14
T14
AA10
AD12
-
H23
L15
K6
L12
L14
L16
M16
N16
R3
M11
N11
P12
R12
T12
W4
M12
N12
P13
R13
T13
M14
N14
P15
R15
T15
AA17
AD15
M15
N15
P16
R16
T16
AC4
AD24
M24
P11
R11
T11
R24
U6
U21
AC19
AE25
W23
AD3
AF26
AC8
AE2
AC23
AF1
Not Connected Pins (XC2S400E Only)
A12
C11
E7
A16
C25
E13
F22
H13
K1
A23
D2
B3
D15
F2
C1
D18
F6
C2
D24
F8
C10
D25
F12
G26
J12
L19
N4
E19
G10
H16
K4
F20
H10
J13
L22
N9
G14
H25
K22
M9
G15
J6
G16
J8
K24
M22
P4
L3
L26
N18
P24
U4
M4
N1
N19
R4
N23
R7
P5
P18
T24
V12
Y3
P19
U1
R19
U25
W14
AA22
AC22
AD13
AF18
T3
U7
U24
W13
AA9
AC15
AD11
AF16
V8
V13
Y7
V21
Y21
AB22
AD2
AE24
W12
AA7
AC1
AD10
AF4
W16
AB15
AC25
AD14
AF20
AB16
AC26
AE5
-
AB17
AD1
AE19
DS077-4 (2.3) June 18, 2008
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107
Product Specification
R
Spartan-IIE FPGA Family: Pinout Tables
Revision History
Version
No.
1.0
1.1
2.0
Date
Description
11/15/01 Initial Xilinx release.
12/20/01 Corrected differential pin pair designations.
11/18/02 Added XC2S400E and XC2S600E and FG676. Removed L37 designation from FT256 pinouts.
Minor corrections and clarifications to pinout definitions. Removed Preliminary designation.
2.1
2.3
02/14/03 Added differential pairs table on page 57, fixed 3 P/N designation typos introduced in v2.0.
Clarified that XC2S50E has two VREF pins per bank.
06/18/08 Added Package Overview section. Updated all modules for continuous page, figure, and table
numbering. Updated links. Synchronized all modules to v2.3.
108
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DS077-4 (2.3) June 18, 2008
Product Specification
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