XC2S50E-7PQ208C [XILINX]
Spartan-IIE 1.8V FPGA Family; 的Spartan- IIE 1.8V FPGA系列
| 型号： | XC2S50E-7PQ208C |
| 厂家： | 
XILINX, INC |
| 描述： | Spartan-IIE 1.8V FPGA Family |
| 文件： | 总4页 (文件大小：113K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Spartan-IIE 1.8V FPGA Family:
Introduction and Ordering
Information
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0
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DS077-1 (v1.0) November 15, 2001
Preliminary Product Specification
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System level features
Introduction
-
SelectRAM+™ hierarchical memory:
The Spartan™-IIE 1.8V Field-Programmable Gate Array
family gives users high performance, abundant logic
resources, and a rich feature set, all at an exceptionally low
price. The five-member family offers densities ranging from
50,000 to 300,000 system gates, as shown in Table 1. Sys-
tem performance is supported beyond 200 MHz.
·
·
·
16 bits/LUT distributed RAM
Configurable 4K-bit true dual-port block RAM
Fast interfaces to external RAM
-
Fully 3.3V PCI compliant to 64 bits at 66 MHz and
CardBus compliant
-
-
-
-
-
-
-
-
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Low-power segmented routing architecture
Full readback ability for verification/observability
Dedicated carry logic for high-speed arithmetic
Efficient multiplier support
Cascade chain for wide-input functions
Abundant registers/latches with enable, set, reset
Four dedicated DLLs for advanced clock control
Four primary low-skew global clock distribution nets
IEEE 1149.1 compatible boundary scan logic
Spartan-IIE devices deliver more gates, I/Os, and features
per dollar than other FPGAs by combining advanced pro-
cess technology with a streamlined architecture based on
the proven Virtex™-E platform. Features include block RAM
(to 64K bits), distributed RAM (to 98,304 bits), 19 selectable
I/O standards, and four DLLs (Delay-Locked Loops). Fast,
predictable interconnect means that successive design iter-
ations continue to meet timing requirements.
The Spartan-IIE family is a superior alternative to
mask-programmed ASICs. The FPGA avoids the initial cost,
lengthy development cycles, and inherent risk of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary (impossible with ASICs).
•
Versatile I/O and packaging
-
-
-
Low cost packages available in all densities
Family footprint compatibility in common packages
19 high-performance interface standards, including
LVDS and LVPECL
-
Up to 120 differential I/O pairs that can be input,
output, or bidirectional
Features
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Zero hold time simplifies system timing
•
Second generation ASIC replacement technology
•
Fully supported by powerful Xilinx ISE development
system
-
-
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Densities as high as 6,912 logic cells with up to
300,000 system gates
Fully automatic mapping, placement, and routing
Integrated with design entry and verification tools
-
Streamlined features based on Virtex-E
architecture
-
-
Unlimited in-system reprogrammability
Very low cost
Table 1: Spartan-IIE FPGA Family Members
Typical
CLB
Maximum
Maximum
Logic System Gate Range
Array
Total
Available Differential Distributed
Block
Device
Cells
1,728
2,700
3,888
5,292
6,912
(Logic and RAM)
23,000 - 50,000
37,000 - 100,000
52,000 - 150,000
71,000 - 200,000
93,000 - 300,000
(R x C) CLBs
User I/O
182
I/O Pairs
84
RAM Bits
24,576
38,400
55,296
75,264
98,304
RAM Bits
XC2S50E
XC2S100E
XC2S150E
XC2S200E
XC2S300E
16 x 24
20 x 30
24 x 36
384
600
864
32K
40K
48K
56K
64K
202
86
263
114
28 x 42 1,176
32 x 48 1,536
289
120
329
120
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS077-1 (v1.0) November 15, 2001
www.xilinx.com
1
Preliminary Product Specification
1-800-255-7778
R
Spartan-IIE 1.8V FPGA Family: Introduction and Ordering Information
Spartan-IIE FPGAs achieve high-performance, low-cost
operation through advanced architecture and semiconduc-
tor technology. Spartan-IIE devices provide system clock
rates beyond 200 MHz. Spartan-IIE FPGAs offer the most
cost-effective solution while maintaining leading edge per-
formance. In addition to the conventional benefits of
high-volume programmable logic solutions, Spartan-IIE
FPGAs also offer on-chip synchronous single-port and
dual-port RAM (block and distributed form), DLL clock driv-
ers, programmable set and reset on all flip-flops, fast carry
logic, and many other features.
General Overview
The Spartan-IIE family of FPGAs have a regular, flexible,
programmable architecture of Configurable Logic Blocks
(CLBs), surrounded by a perimeter of programmable
Input/Output Blocks (IOBs). There are four Delay-Locked
Loops (DLLs), one at each corner of the die. Two columns
of block RAM lie on opposite sides of the die, between the
CLBs and the IOB columns. These functional elements are
interconnected by a powerful hierarchy of versatile routing
channels (see Figure 1).
Spartan-IIE FPGAs are customized by loading configura-
tion data into internal static memory cells. Unlimited repro-
gramming cycles are possible with this approach. Stored
values in these cells determine logic functions and intercon-
nections implemented in the FPGA. Configuration data can
be read from an external serial PROM (master serial mode),
or written into the FPGA in slave serial, slave parallel, or
Boundary Scan modes. The Xilinx XC17S00A PROM family
is recommended for serial configuration of Spartan-IIE
FPGAs. The XC18V00 reprogrammable PROM family is
recommended for parallel or serial configuration.
Spartan-IIE Family Compared to Spartan-II
Family
•
•
•
•
Higher density and more I/O
Higher performance
Unique pinouts in cost-effective packages
Differential signaling
-
LVDS, Bus LVDS, LVPECL
= 1.8V
•
V
CCINT
-
-
-
Lower power
5V tolerance with 100Ω external resistor
3V tolerance directly
Spartan-IIE FPGAs are typically used in high-volume appli-
cations where the versatility of a fast programmable solution
adds benefits. Spartan-IIE FPGAs are ideal for shortening
product development cycles while offering a cost-effective
solution for high volume production.
•
•
PCI, LVTTL, and LVCMOS2 input buffers powered by
instead of V
V
CCO
CCINT
Unique larger bitstream
DLL
DLL
DLL
DLL
I/O LOGIC
DS077_01_102201
Figure 1: Basic Spartan-IIE Family FPGA Block Diagram
2
www.xilinx.com
DS077-1 (v1.0) November 15, 2001
1-800-255-7778
Preliminary Product Specification
R
Spartan-IIE 1.8V FPGA Family: Introduction and Ordering Information
Spartan-IIE Product Availability
Table 2 shows the package and speed grades available for
Spartan-IIE family devices. Table 3 shows the maximum
user I/Os available on the device and the number of user
I/Os available for each device/package combination.
Table 2: Spartan-IIE Package and Speed Grade Availability
Pins
Type
Code
-6
144
208
Plastic PQFP
PQ208
C, I
256
456
Plastic TQFP
Fine Pitch BGA
Fine Pitch BGA
Device
TQ144
FT256
C, I
(C)
FG456
-
XC2S50E
C, I
-7
(C)
(C)
-
XC2S100E
XC2S150E
XC2S200E
XC2S300E
-6
C, I
C, I
C, I
(C)
C, I
(C)
(C, I)
(C)
C, I
(C)
C, I
(C)
-7
(C)
(C)
-6
-
-
-
-
-
-
(C, I)
(C)
(C, I)
(C)
-7
-6
C, I
C, I
(C)
-7
(C)
-6
C, I
C, I
(C)
-7
(C)
Notes:
1. C = Commercial, T = 0° to +85°C; I = Industrial, TJ = –40°C to +100°C
J
2. Parentheses indicate product not yet released. Contact sales for availability.
Table 3: Spartan-IIE User I/O Chart
Available User I/O According to Package Type
Maximum
User I/O
Device
TQ144
PQ208
146
FT256
182
FG456
XC2S50E
XC2S100E
XC2S150E
XC2S200E
XC2S300E
182
202
263
289
329
102
-
102
146
182
202
263
289
329
-
-
-
146
182
146
182
146
182
DS077-1 (v1.0) November 15, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
3
R
Spartan-IIE 1.8V FPGA Family: Introduction and Ordering Information
Ordering Information
Example:
XC2S50E -6 PQ 208 C
Device Type
Temperature Range
Number of Pins
Package Type
Speed Grade
Device Ordering Options
Device
Speed Grade
Package Type / Number of Pins
TQ144 144-pin Plastic Thin QFP
PQ208 208-pin Plastic QFP
Temperature Range (T )
J
XC2S50E
XC2S100E
XC2S150E
XC2S200E
XC2S300E
-6 Standard Performance
-7 Higher Performance
C = Commercial
I = Industrial
0°C to +85°C
–40°C to +100°C
FT256 256-ball Fine Pitch BGA
FG456 456-ball Fine Pitch BGA
Revision History
Version No.
Date
11/15/01 Initial Xilinx release.
Description
1.0
The Spartan-IIE Family Data Sheet
DS077-1, Spartan-IIE 1.8V FPGA Family: Introduction and Ordering Information (Module 1)
DS077-2, Spartan-IIE 1.8V FPGA Family: Functional Description (Module 2)
DS077-3, Spartan-IIE 1.8V FPGA Family: DC and Switching Characteristics (Module 3)
DS077-4, Spartan-IIE 1.8V FPGA Family: Pinout Tables (Module 4)
4
www.xilinx.com
DS077-1 (v1.0) November 15, 2001
1-800-255-7778
Preliminary Product Specification
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