XC2V2000-6BGG957C [XILINX]
Field Programmable Gate Array, 2688 CLBs, 2000000 Gates, 820MHz, CMOS, PBGA957, FLIP CHIP, BGA-957;
| 型号： | XC2V2000-6BGG957C |
| 厂家： | 
XILINX, INC |
| 描述： | Field Programmable Gate Array, 2688 CLBs, 2000000 Gates, 820MHz, CMOS, PBGA957, FLIP CHIP, BGA-957 栅 |
| 文件： | 总309页 (文件大小：2266K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0
R
Virtex-II 1.5V
Field-Programmable Gate Arrays
0
0
DS031-1 (v1.9) September 26, 2002
Advance Product Specification
Summary of VirtexTM-II Features
•
Industry First Platform FPGA Solution
-
-
Programmable sink current (2 mA to 24 mA) per I/O
Digitally Controlled Impedance (DCI) I/O: on-chip
termination resistors for single-ended I/O standards
•
IP-Immersion Architecture
-
-
-
Densities from 40K to 8M system gates
-
-
-
-
PCI-X compatible (133 MHz and 66 MHz) at 3.3V
PCI compliant (66 MHz and 33 MHz) at 3.3V
CardBus compliant (33 MHz) at 3.3V
Differential Signaling
420 MHz internal clock speed (Advance Data)
840+ Mb/s I/O (Advance Data)
•
•
SelectRAM™ Memory Hierarchy
-
3 Mb of dual-port RAM in 18 Kbit block SelectRAM
resources
·
840 Mb/s Low-Voltage Differential Signaling I/O
(LVDS) with current mode drivers
-
Up to 1.5 Mb of distributed SelectRAM resources
·
·
Bus LVDS I/O
Lightning Data Transport (LDT) I/O with current
driver buffers
High-Performance Interfaces to External Memory
-
DRAM interfaces
·
Low-Voltage Positive Emitter-Coupled Logic
(LVPECL) I/O
Built-in DDR input and output registers
·
·
·
SDR / DDR SDRAM
Network FCRAM
Reduced Latency DRAM
·
-
Proprietary high-performance SelectLink
Technology
-
-
SRAM interfaces
·
·
SDR / DDR SRAM
QDR™ SRAM
·
·
·
High-bandwidth data path
Double Data Rate (DDR) link
Web-based HDL generation methodology
CAM interfaces
•
•
Arithmetic Functions
•
•
Supported by Xilinx Foundation™ and Alliance
Series™ Development Systems
-
-
Dedicated 18-bit x 18-bit multiplier blocks
Fast look-ahead carry logic chains
-
-
-
Integrated VHDL and Verilog design flows
Compilation of 10M system gates designs
Internet Team Design (ITD) tool
Flexible Logic Resources
-
Up to 93,184 internal registers / latches with Clock
Enable
SRAM-Based In-System Configuration
-
Up to 93,184 look-up tables (LUTs) or cascadable
16-bit shift registers
-
-
Fast SelectMAP configuration
Triple Data Encryption Standard (DES) security
option (Bitstream Encryption)
-
-
Wide multiplexers and wide-input function support
Horizontal cascade chain and sum-of-products
support
-
-
-
-
IEEE 1532 support
Partial reconfiguration
Unlimited reprogrammability
Readback capability
-
Internal 3-state bussing
•
High-Performance Clock Management Circuitry
-
Up to 12 DCM (Digital Clock Manager) modules
•
•
0.15 µm 8-Layer Metal Process with 0.12 µm
High-Speed Transistors
·
·
·
Precise clock de-skew
Flexible frequency synthesis
High-resolution phase shifting
1.5V (V
) Core Power Supply, Dedicated 3.3V
CCINT
-
16 global clock multiplexer buffers
V
Auxiliary and V
I/O Power Supplies
CCO
CCAUX
•
•
Active Interconnect Technology
•
•
IEEE 1149.1 Compatible Boundary-Scan Logic
Support
-
-
Fourth generation segmented routing structure
Predictable, fast routing delay, independent of fanout
Flip-Chip and Wire-Bond Ball Grid Array (BGA)
Packages in Three Standard Fine Pitches (0.80 mm,
1.00 mm, and 1.27 mm)
SelectI/O™-Ultra Technology
-
-
Up to 1,108 user I/Os
•
100% Factory Tested
19 single-ended and six differential standards
© 2001-2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS031-1 (v1.9) September 26, 2002
Advance Product Specification
www.xilinx.com
1-800-255-7778
Module 1 of 4
1
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Virtex-II 1.5V Field-Programmable Gate Arrays
Table 1: Virtex-II Field-Programmable Gate Array Family Members
CLB
(1 CLB = 4 slices = Max 128 bits)
SelectRAM Blocks
Maximum
System
Gates Row x Col. Slices
Array
Distributed
RAM Kbits
Multiplier 18 Kbit Max RAM
Max I/O
DCMs Pads
(1)
Device
XC2V40
Blocks
4
Blocks
4
(Kbits)
72
40K
80K
250K
500K
1M
8 x 8
16 x 8
256
8
16
4
4
88
120
XC2V80
512
8
8
144
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
Notes:
24 x 16
32 x 24
40 x 32
48 x 40
56 x 48
64 x 56
80 x 72
96 x 88
112 x 104
1,536
3,072
5,120
7,680
10,752
14,336
23,040
33,792
46,592
48
24
24
432
8
200
96
32
32
576
8
264
160
240
336
448
720
1,056
1,456
40
40
720
8
432
1.5M
2M
48
48
864
8
528
56
56
1,008
1,728
2,160
2,592
3,024
8
624
3M
96
96
12
12
12
12
720
4M
120
144
168
120
144
168
912
6M
1,104
1,108
8M
1. See details in Table 2, “Maximum Number of User I/O Pads”.
General Description
The Virtex-II family is a platform FPGA developed for high
performance from low-density to high-density designs that
are based on IP cores and customized modules. The family
delivers complete solutions for telecommunication, wire-
less, networking, video, and DSP applications, including
PCI, LVDS, and DDR interfaces.
Table 2 shows the maximum number of user I/Os available.
The Virtex-II device/package combination table (Table 6 at
the end of this section) details the maximum number of I/Os
for each device and package using wire-bond or flip-chip
technology.
Table 2: Maximum Number of User I/O Pads
The leading-edge 0.15 µm / 0.12 µm CMOS 8-layer metal
process and the Virtex-II architecture are optimized for high
speed with low power consumption. Combining a wide vari-
ety of flexible features and a large range of densities up to
10 million system gates, the Virtex-II family enhances pro-
grammable logic design capabilities and is a powerful alter-
native to mask-programmed gates arrays. As shown in
Table 1, the Virtex-II family comprises 11 members, ranging
from 40K to 8M system gates.
Device
XC2V40
Wire-Bond
Flip-Chip
88
120
200
264
328
392
-
-
-
XC2V80
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
-
-
432
528
624
720
912
1,104
1,108
Packaging
Offerings include ball grid array (BGA) packages with
0.80 mm, 1.00 mm, and 1.27 mm pitches. In addition to tra-
ditional wire-bond interconnects, flip-chip interconnect is
used in some of the BGA offerings. The use of flip-chip
interconnect offers more I/Os than is possible in wire-bond
versions of the similar packages. Flip-chip construction
offers the combination of high pin count with high thermal
capacity.
516
-
-
-
Module 1 of 4
2
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DS031-1 (v1.9) September 26, 2002
Advance Product Specification
R
Virtex-II 1.5V Field-Programmable Gate Arrays
Architecture
Virtex-II Array Overview
Virtex-II devices are user-programmable gate arrays with
various configurable elements. The Virtex-II architecture is
optimized for high-density and high-performance logic
designs. As shown in Figure 1, the programmable device is
comprised of input/output blocks (IOBs) and internal
configurable logic blocks (CLBs).
Programmable I/O blocks provide the interface between
package pins and the internal configurable logic. Most
popular and leading-edge I/O standards are supported by
the programmable IOBs.
DCM
DCM
IOB
Global Clock Mux
Configurable Logic
Programmable I/Os
CLB
Block SelectRAM
Multiplier
DS031_28_100900
Figure 1: Virtex-II Architecture Overview
The internal configurable logic includes four major elements
organized in a regular array.
cells. These values are loaded in the memory cells during
configuration and can be reloaded to change the functions
of the programmable elements.
•
Configurable Logic Blocks (CLBs) provide functional
elements for combinatorial and synchronous logic,
including basic storage elements. BUFTs (3-state
buffers) associated with each CLB element drive
dedicated segmentable horizontal routing resources.
Virtex-II Features
This section briefly describes Virtex-II features.
Input/Output Blocks (IOBs)
•
•
•
Block SelectRAM memory modules provide large
18 Kbit storage elements of dual-port RAM.
IOBs are programmable and can be categorized as follows:
•
Input block with an optional single-data-rate or
double-data-rate (DDR) register
Multiplier blocks are 18-bit x 18-bit dedicated
multipliers.
DCM (Digital Clock Manager) blocks provide
self-calibrating, fully digital solutions for clock
distribution delay compensation, clock multiplication
and division, coarse- and fine-grained clock phase
shifting.
•
Output block with an optional single-data-rate or DDR
register, and an optional 3-state buffer, to be driven
directly or through a single or DDR register
•
Bidirectional block (any combination of input and output
configurations)
A new generation of programmable routing resources called
Active Interconnect Technology interconnects all of these
elements. The general routing matrix (GRM) is an array of
routing switches. Each programmable element is tied to a
switch matrix, allowing multiple connections to the general
routing matrix. The overall programmable interconnection is
hierarchical and designed to support high-speed designs.
These registers are either edge-triggered D-type flip-flops
or level-sensitive latches.
IOBs support the following single-ended I/O standards:
•
•
•
•
LVTTL, LVCMOS (3.3V, 2.5V, 1.8V, and 1.5V)
PCI-X compatible (133 MHz and 66 MHz) at 3.3V
PCI compliant (66 MHz and 33 MHz) at 3.3V
CardBus compliant (33 MHz) at 3.3V
All programmable elements, including the routing
resources, are controlled by values stored in static memory
DS031-1 (v1.9) September 26, 2002
Advance Product Specification
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Virtex-II 1.5V Field-Programmable Gate Arrays
•
•
•
•
GTL and GTLP
A multiplier block is associated with each SelectRAM mem-
ory block. The multiplier block is a dedicated 18 x 18-bit
multiplier and is optimized for operations based on the block
SelectRAM content on one port. The 18 x 18 multiplier can
be used independently of the block SelectRAM resource.
Read/multiply/accumulate operations and DSP filter struc-
tures are extremely efficient.
HSTL (Class I, II, III, and IV)
SSTL (3.3V and 2.5V, Class I and II)
AGP-2X
The digitally controlled impedance (DCI) I/O feature auto-
matically provides on-chip termination for each I/O element.
Both the SelectRAM memory and the multiplier resource
are connected to four switch matrices to access the general
routing resources.
The IOB elements also support the following differential sig-
naling I/O standards:
•
•
•
•
•
LVDS
Global Clocking
BLVDS (Bus LVDS)
ULVDS
The DCM and global clock multiplexer buffers provide a
complete solution for designing high-speed clocking
schemes.
LDT
LVPECL
Up to 12 DCM blocks are available. To generate de-skewed
internal or external clocks, each DCM can be used to elimi-
nate clock distribution delay. The DCM also provides 90-,
180-, and 270-degree phase-shifted versions of its output
clocks. Fine-grained phase shifting offers high-resolution
phase adjustments in increments of 1/256 of the clock
period. Very flexible frequency synthesis provides a clock
output frequency equal to any M/D ratio of the input clock
frequency, where M and D are two integers. For the exact
timing parameters, see Virtex™-II Electrical Characteris-
tics.
Two adjacent pads are used for each differential pair. Two or
four IOB blocks connect to one switch matrix to access the
routing resources.
Configurable Logic Blocks (CLBs)
CLB resources include four slices and two 3-state buffers.
Each slice is equivalent and contains:
•
•
•
•
•
•
•
Two function generators (F & G)
Two storage elements
Arithmetic logic gates
Virtex-II devices have 16 global clock MUX buffers, with up
to eight clock nets per quadrant. Each global clock MUX
buffer can select one of the two clock inputs and switch
glitch-free from one clock to the other. Each DCM block is
able to drive up to four of the 16 global clock MUX buffers.
Large multiplexers
Wide function capability
Fast carry look-ahead chain
Horizontal cascade chain (OR gate)
The function generators F & G are configurable as 4-input
look-up tables (LUTs), as 16-bit shift registers, or as 16-bit
distributed SelectRAM memory.
Routing Resources
The IOB, CLB, block SelectRAM, multiplier, and DCM ele-
ments all use the same interconnect scheme and the same
access to the global routing matrix. Timing models are
shared, greatly improving the predictability of the perfor-
mance of high-speed designs.
In addition, the two storage elements are either edge-trig-
gered D-type flip-flops or level-sensitive latches.
Each CLB has internal fast interconnect and connects to a
switch matrix to access general routing resources.
There are a total of 16 global clock lines, with eight available
per quadrant. In addition, 24 vertical and horizontal long
lines per row or column as well as massive secondary and
local routing resources provide fast interconnect. Virtex-II
buffered interconnects are relatively unaffected by net
fanout and the interconnect layout is designed to minimize
crosstalk.
Block SelectRAM Memory
The block SelectRAM memory resources are 18 Kb of
dual-port RAM, programmable from 16K x 1 bit to 512 x 36
bits, in various depth and width configurations. Each port is
totally synchronous and independent, offering three
"read-during-write" modes. Block SelectRAM memory is
cascadable to implement large embedded storage blocks.
Supported memory configurations for dual-port and sin-
gle-port modes are shown in Table 3.
Horizontal and vertical routing resources for each row or
column include:
•
•
•
•
24 long lines
120 hex lines
Table 3: Dual-Port And Single-Port Configurations
40 double lines
16K x 1 bit
8K x 2 bits
4K x 4 bits
2K x 9 bits
1K x 18 bits
512 x 36 bits
16 direct connect lines (total in all four directions)
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DS031-1 (v1.9) September 26, 2002
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Advance Product Specification
R
Virtex-II 1.5V Field-Programmable Gate Arrays
Boundary Scan
Readback and Integrated Logic Analyzer
Boundary scan instructions and associated data registers
support a standard methodology for accessing and config-
uring Virtex-II devices that complies with IEEE standards
1149.1 — 1993 and 1532. A system mode and a test mode
are implemented. In system mode, a Virtex-II device per-
forms its intended mission even while executing non-test
boundary-scan instructions. In test mode, boundary-scan
test instructions control the I/O pins for testing purposes.
The Virtex-II Test Access Port (TAP) supports BYPASS,
PRELOAD, SAMPLE, IDCODE, and USERCODE non-test
instructions. The EXTEST, INTEST, and HIGHZ test instruc-
tions are also supported.
Configuration data stored in Virtex-II configuration memory
can be read back for verification. Along with the configura-
tion data, the contents of all flip-flops/latches, distributed
SelectRAM, and block SelectRAM memory resources can
be read back. This capability is useful for real-time debug-
ging.
The Integrated Logic Analyzer (ILA) core and software pro-
vides a complete solution for accessing and verifying
Virtex-II devices.
Virtex-II Device/Package Combinations
and Maximum I/O
Wire-bond and flip-chip packages are available. Table 4 and
Table 5 show the maximum possible number of user I/Os in
wire-bond and flip-chip packages, respectively. Table 6
shows the number of available user I/Os for all device/pack-
age combinations.
Configuration
Virtex-II devices are configured by loading data into internal
configuration memory, using the following five modes:
•
•
•
•
•
Slave-serial mode
Master-serial mode
•
CS denotes wire-bond chip-scale ball grid array (BGA)
(0.80 mm pitch).
Slave SelectMAP mode
Master SelectMAP mode
Boundary-Scan mode (IEEE 1532)
•
•
•
•
FG denotes wire-bond fine-pitch BGA (1.00 mm pitch).
FF denotes flip-chip fine-pitch BGA (1.00 mm pitch).
BG denotes standard BGA (1.27 mm pitch).
A Data Encryption Standard (DES) decryptor is available
on-chip to secure the bitstreams. One or two triple-DES key
sets can be used to optionally encrypt the configuration
information.
BF denotes flip-chip BGA (1.27 mm pitch).
The number of I/Os per package include all user I/Os except
the 15 control pins (CCLK, DONE, M0, M1, M2, PROG_B,
PWRDWN_B, TCK, TDI, TDO, TMS, HSWAP_EN, DXN,
DXP, and RSVD) and VBATT.
Table 4: Wire-Bond Packages Information
Package
Pitch (mm)
CS144
0.80
FG256
1.00
FG456
1.00
FG676
1.00
BG575
1.27
BG728
1.27
Size (mm)
I/Os
12 x 12
92
17 x 17
172
23 x 23
324
27 x 27
484
31 x 31
408
35 x 35
516
Table 5: Flip-Chip Packages Information
Package FF896
Pitch (mm) 1.00
FF1152
1.00
FF1517
1.00
BF957
1.27
40 x 40
684
Size (mm)
I/Os
31 x 31
624
35 x 35
824
40 x 40
1,108
DS031-1 (v1.9) September 26, 2002
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Virtex-II 1.5V Field-Programmable Gate Arrays
Table 6: Virtex-II Device/Package Combinations and Maximum Number of Available I/Os (Advance Information)
Available I/Os
XC2V
40
XC2V
80
XC2V
250
XC2V
500
XC2V
1000
XC2V
1500
XC2V
2000
XC2V
3000
XC2V
4000
XC2V
6000
XC2V
8000
Package
CS144
FG256
FG456
FG676
FF896
88
88
-
92
92
-
-
-
-
-
-
-
-
120
172
172
172
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
200
264
324
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
392
456
624
-
484
-
-
-
-
-
-
432
528
-
824
1,104
-
-
FF1152
FF1517
BG575
BG728
BF957
Notes:
-
-
-
720
-
824
912
-
824
-
-
-
-
1,108
-
328
392
408
-
-
-
-
-
-
-
-
-
-
516
684
-
-
-
624
684
684
1. All devices in a particular package are pinout (footprint) compatible. In addition, the FG456 and FG676 packages are compatible, as
are the FF896 and FF1152 packages.
Virtex-II Ordering Information
Example: XC2V1000-5FG456C
Device Type
Temperature Range
C = Commercial (Tj = 0˚C to +85˚C)
I = Industrial (Tj = –40˚C to +100˚C)
Speed Grade
(-4, -5, -6)
Number of Pins
Package Type
DS031_35_033001
Figure 2: Virtex-II Ordering Information
Module 1 of 4
6
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DS031-1 (v1.9) September 26, 2002
Advance Product Specification
R
Virtex-II 1.5V Field-Programmable Gate Arrays
Revision History
This section records the change history for this module of the data sheet.
Date
Version
1.0
Revision
11/07/00
12/06/00
01/15/01
Early access draft.
Initial release.
1.1
1.2
Added values to the tables in the Virtex-II Performance Characteristics and Virtex-II
Switching Characteristics sections.
01/25/01
04/02/01
07/30/01
10/02/01
07/16/02
09/26/02
1.3
1.5
1.6
1.7
1.8
1.9
The data sheet was divided into four modules (per the current style standard).
Skipped v1.4 to sync up modules. Reverted to traditional double-column format.
TM
Made minor changes to items listed under Summary of Virtex -II Features.
Minor edits.
Updated Virtex-II Device/Package Combinations shown in Table 6.
Updated Table 2 and Table 6 to reflect supported Virtex-II Device/Package Combinations.
Virtex-II Data Sheet
The Virtex-II Data Sheet contains the following modules:
•
DS031-1, Virtex-II 1.5V FPGAs: Introduction and
Ordering Information (Module 1)
•
•
DS031-3, Virtex-II 1.5V FPGAs: DC and Switching
Characteristics (Module 3)
DS031-4, Virtex-II 1.5V FPGAs: Pinout Tables
(Module 4)
•
DS031-2, Virtex-II 1.5V FPGAs: Functional Description
(Module 2)
DS031-1 (v1.9) September 26, 2002
Advance Product Specification
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7
0
R
Virtex-II 1.5V
Field-Programmable Gate Arrays
0
0
DS031-2 (v2.1) September 26, 2002
Advance Product Specification
Detailed Description
Input/Output Blocks (IOBs)
Table 1: Supported Single-Ended I/O Standards
Virtex-II I/O blocks (IOBs) are provided in groups of two or
four on the perimeter of each device. Each IOB can be used
as input and/or output for single-ended I/Os. Two IOBs can
be used as a differential pair. A differential pair is always
connected to the same switch matrix, as shown in Figure 1.
Board
Termination
I/O
Standard
Output
Input
Input
V
V
V
Voltage (V
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1.2
)
CCO
CCO
REF
TT
LVTTL
3.3
3.3
3.3
3.3
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0.8
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
PCI33_3
PCI66_3
PCI-X
IOB blocks are designed for high performances I/Os, sup-
porting 19 single-ended standards, as well as differential
signaling with LVDS, LDT, Bus LVDS, and LVPECL.
2.5
2.5
1.8
1.8
1.5
1.5
3.3
3.3
IOB
PAD4
3.3
3.3
Differential Pair
IOB
3.3
3.3
PAD3
Switch
GTL
Note 1
Note 1
1.5
Note 1
Note 1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Matrix
IOB
GTLP
1.0
1.5
PAD2
Differential Pair
HSTL_I
0.75
0.75
0.9
0.75
0.75
1.5
IOB
PAD1
HSTL_II
HSTL_III
HSTL_IV
HSTL_I
1.5
DS031_30_101600
1.5
Figure 1: Virtex-II Input/Output Tile
1.5
0.9
1.5
1.8
0.9
0.9
Note: Differential I/Os must use the same clock.
HSTL_II
HSTL_III
HSTL_IV
SSTL2_I
SSTL2_II
SSTL3_I
SSTL3_II
AGP-2X/AGP
Notes:
1.8
0.9
0.9
Supported I/O Standards
1.8
1.1
1.8
Virtex-II IOB blocks feature SelectI/O-Ultra inputs and out-
puts that support a wide variety of I/O signaling standards.
1.8
1.1
1.8
In addition to the internal supply voltage (V
= 1.5V),
CCINT
2.5
1.25
1.25
1.5
1.25
1.25
1.5
output driver supply voltage (V
) is dependent on the I/O
CCO
standard (see Table 1). An auxiliary supply voltage
(V = 3.3 V) is required, regardless of the I/O stan-
2.5
CCAUX
3.3
dard used. For exact supply voltage absolute maximum rat-
ings, see DC Input and Output Levels.
3.3
1.5
1.5
3.3
1.32
N/A
1.
V
of GTL or GTLP should not be lower than the
CCO
termination voltage or the voltage seen at the I/O pad.
© 2001-2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
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Virtex-II 1.5V Field-Programmable Gate Arrays
Table 2: Supported Differential Signal I/O Standards
Table 3: Supported DCI I/O Standards
Output
Input
Input
Output
I/O
Standard
Output
Input
Input
Termination
Type
I/O Standard
LVPECL_33
LDT_25
V
V
V
V
V
V
V
CCO
CCO
REF
OD
CCO
CCO
REF
(1)
LVDCI_33
3.3
3.3
2.5
2.5
1.8
1.8
1.5
1.5
1.2
1.5
1.5
1.5
1.5
1.5
1.8
1.8
1.8
1.8
2.5
2.5
3.3
3.3
3.3
3.3
2.5
2.5
1.8
1.8
1.5
1.5
1.2
1.5
1.5
1.5
1.5
1.5
N/A
N/A
N/A
N/A
2.5
2.5
3.3
3.3
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0.8
Series
Series
Series
Series
Series
Series
Series
Series
Single
Single
Split
3.3
2.5
3.3
2.5
3.3
2.5
2.5
2.5
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
490 mV to 1.22V
0.430 - 0.670
0.250 - 0.400
0.250 - 0.400
0.330 - 0.700
0.330 - 0.700
0.250 - 0.450
0.430 - 0.670
(1)
(1)
(1)
(1)
LVDCI_DV2_33
(1)
LVDCI_25
LVDS_33
LVDCI_DV2_25
LVDS_25
(1)
LVDCI_18
LVDSEXT_33
LVDSEXT_25
BLVDS_25
ULVDS_25
LVDCI_DV2_18
(1)
LVDCI_15
LVDCI_DV2_15
GTL_DCI
GTLP_DCI
1.0
All of the user IOBs have fixed-clamp diodes to V
and to
HSTL_I_DCI
HSTL_II_DCI
HSTL_III_DCI
HSTL_IV_DCI
HSTL_I_DCI
HSTL_II_DCI
HSTL_III_DCI
HSTL_IV_DCI
0.75
0.75
0.9
CCO
ground. As outputs, these IOBs are not compatible or compli-
ant with 5V I/O standards. As inputs, these IOBs are not nor-
mally 5V tolerant, but can be used with 5V I/O standards when
external current-limiting resistors are used. For more details,
see the “5V Tolerant I/Os“ Tech Topic at www.xilinx.com.
Split
Single
Single
Split
0.9
0.9
Table 3 lists supported I/O standards with Digitally Con-
trolled Impedance. See Digitally Controlled Impedance
(DCI), page 9.
0.9
Split
1.1
Single
Single
Split
1.1
(2)
SSTL2_I_DCI
SSTL2_II_DCI
1.25
1.25
1.5
(2)
(2)
Split
SSTL3_I_DCI
SSTL3_II_DCI
Notes:
Split
(2)
1.5
Split
1. LVDCI_XX and LVDCI_DV2_XX are LVCMOS controlled
impedance buffers, matching the reference resistors or half
of the reference resistors.
2. These are SSTL compatible.
Logic Resources
IOB blocks include six storage elements, as shown in
Figure 2.
Each storage element can be configured either as an
edge-triggered D-type flip-flop or as a level-sensitive latch.
On the input, output, and 3-state path, one or two DDR reg-
isters can be used.
Double data rate is directly accomplished by the two regis-
ters on each path, clocked by the rising edges (or falling
edges) from two different clock nets. The two clock signals
are generated by the DCM and must be 180 degrees out of
phase, as shown in Figure 3. There are two input, output,
and 3-state data signals, each being alternately clocked out.
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Virtex-II 1.5V Field-Programmable Gate Arrays
The DDR mechanism shown in Figure 3 can be used to mir-
ror a copy of the clock on the output. This is useful for prop-
agating a clock along the data that has an identical delay. It
is also useful for multiple clock generation, where there is a
unique clock driver for every clock load. Virtex-II devices
can produce many copies of a clock with very little skew.
IOB
Input
DDR mux
Reg
OCK1
Reg
ICK1
Each group of two registers has a clock enable signal (ICE
for the input registers, OCE for the output registers, and
TCE for the 3-state registers). The clock enable signals are
active High by default. If left unconnected, the clock enable
for that storage element defaults to the active state.
Reg
3-State
OCK2
Reg
ICK2
Each IOB block has common synchronous or asynchronous
set and reset (SR and REV signals).
DDR mux
Reg
OCK1
SR forces the storage element into the state specified by the
SRHIGH or SRLOW attribute. SRHIGH forces a logic “1”.
SRLOW forces a logic “0”. When SR is used, a second input
(REV) forces the storage element into the opposite state. The
reset condition predominates over the set condition. The ini-
tial state after configuration or global initialization state is
defined by a separate INIT0 and INIT1 attribute. By default,
the SRLOW attribute forces INIT0, and the SRHIGH attribute
forces INIT1.
PAD
Reg
Output
OCK2
DS031_29_100900
Figure 2: Virtex-II IOB Block
DCM
180° 0°
FDDR
FDDR
D1
Q1
D1
Q1
CLOCK
CLK1
CLK1
Q
Q
DDR MUX
DDR MUX
D2
D2
Q2
CLK2
Q2
CLK2
(50/50 duty cycle clock)
DS031_26_100900
Figure 3: Double Data Rate Registers
For each storage element, the SRHIGH, SRLOW, INIT0,
and INIT1 attributes are independent. Synchronous or
asynchronous set / reset is consistent in an IOB block.
latches) (see Figure 4) can be configured as follows:
•
•
•
•
•
No set or reset
Synchronous set
All the control signals have independent polarity. Any
inverter placed on a control input is automatically absorbed.
Synchronous reset
Synchronous set and reset
Asynchronous set (preset)
Each register or latch (independent of all other registers or
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•
•
Asynchronous reset (clear)
The synchronous reset overrides a set, and an asynchro-
nous clear overrides a preset.
Asynchronous set and reset (preset and clear)
(O/T) 1
Attribute
INIT1
INIT0
FF
SRHIGH
SRLOW
LATCH
Q1
D1
(O/T) CE
CE
(O/T) CLK1
CK1
SR REV
SR
Shared
by all
registers
FF1
(OQ or TQ)
DDR MUX
FF2
REV
FF
LATCH
D2
Q2
CE
Attribute
INIT1
INIT0
SRHIGH
SRLOW
(O/T) CLK2
(O/T) 2
CK2
SR REV
Reset Type
SYNC
ASYNC
DS031_25_110300
Figure 4: Register / Latch Configuration in an IOB Block
pull-up and pull-down resistors are in the range 10 - 60 KΩ,
which is the specification for V when operating at 3.3V
(from 3.0 to 3.6V only). The clamp diode is always present,
even when power is not.
Input/Output Individual Options
CCO
Each device pad has optional pull-up, pull-down, and
weak-keeper in LVTTL and LVCMOS SelectI/O-Ultra config-
urations, as illustrated in Figure 5. Values of the optional
V
CCO
Clamp
Diode
OBUF
Weak
Keeper
V
CCO
Program Current
10-60KΩ
PAD
V
CCO
10-60KΩ
V
= 3.3V
= 1.5V
Program
Delay
CCAUX
V
CCINT
IBUF
DS031_23_011601
Figure 5: LVTTL, LVCMOS or PCI SelectI/O-Ultra Standards
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Virtex-II 1.5V Field-Programmable Gate Arrays
The optional weak-keeper circuit is connected to each out-
put. When selected, the circuit monitors the voltage on the
pad and weakly drives the pin High or Low. If the pin is con-
nected to a multiple-source signal, the weak-keeper holds
the signal in its last state if all drivers are disabled. Maintain-
ing a valid logic level in this way eliminates bus chatter;
pull-up or pull-down override the weak-keeper circuit.
LVTTL sinks and sources current up to 24 mA. The current
is programmable for LVTTL and LVCMOS SelectI/O-Ultra
standards (see Table 4). Drive-strength and slew-rate con-
trols for each output driver, minimize bus transients. For
LVDCI and LVDCI_DV2 standards, drive strength and
slew-rate controls are not available.
Table 4: LVTTL and LVCMOS Programmable Currents (Sink and Source)
SelectI/O-Ultra
LVTTL
Programmable Current (Worst-Case Guaranteed Minimum)
2 mA
2 mA
2 mA
2 mA
2 mA
4 mA
4 mA
4 mA
4 mA
4 mA
6 mA
6 mA
6 mA
6 mA
6 mA
8 mA
8 mA
8 mA
8 mA
8 mA
12 mA
12 mA
12 mA
12 mA
12 mA
16 mA
16 mA
16 mA
16 mA
16 mA
24 mA
24 mA
24 mA
n/a
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
n/a
Figure 6 shows the SSTL2, SSTL3, and HSTL configura-
tions. HSTL can sink current up to 48 mA. (HSTL IV)
All Virtex-II IOBs support IEEE 1149.1 compatible boundary
scan testing.
Input Path
V
CCO
The Virtex-II IOB input path routes input signals directly to
internal logic and / or through an optional input flip-flop or
latch, or through the DDR input registers. An optional delay
element at the D-input of the storage element eliminates
pad-to-pad hold time. The delay is matched to the internal
clock-distribution delay of the Virtex-II device, and when
used, assures that the pad-to-pad hold time is zero.
Clamp
Diode
OBUF
Each input buffer can be configured to conform to any of the
low-voltage signaling standards supported. In some of
these standards the input buffer utilizes a user-supplied
PAD
threshold voltage, V . The need to supply V
imposes
REF
REF
constraints on which standards can be used in the same
bank. See I/O banking description.
V
V
= 3.3V
CCAUX
= 1.5V
CCINT
Output Path
V
REF
The output path includes a 3-state output buffer that drives
the output signal onto the pad. The output and / or the
3-state signal can be routed to the buffer directly from the
internal logic or through an output / 3-state flip-flop or latch,
or through the DDR output / 3-state registers.
DS031_24_100900
Figure 6: SSTL or HSTL SelectI/O-Ultra Standards
All pads are protected against damage from electrostatic
discharge (ESD) and from over-voltage transients. Virtex-II
uses two memory cells to control the configuration of an I/O
as an input. This is to reduce the probability of an I/O con-
figured as an input from flipping to an output when sub-
jected to a single event upset (SEU) in space applications.
Each output driver can be individually programmed for a
wide range of low-voltage signaling standards. In most sig-
naling standards, the output High voltage depends on an
externally supplied V
voltage. The need to supply V
CCO
CCO
imposes constraints on which standards can be used in the
same bank. See I/O banking description.
Prior to configuration, all outputs not involved in configura-
tion are forced into their high-impedance state. The
pull-down resistors and the weak-keeper circuits are inac-
tive. The dedicated pin HSWAP_EN controls the pull-up
resistors prior to configuration. By default, HSWAP_EN is
set high, which disables the pull-up resistors on user I/O
pins. When HSWAP_EN is set low, the pull-up resistors are
activated on user I/O pins.
I/O Banking
Some of the I/O standards described above require V
CCO
and V
voltages. These voltages are externally supplied
REF
and connected to device pins that serve groups of IOB
blocks, called banks. Consequently, restrictions exist about
which I/O standards can be combined within a given bank.
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Eight I/O banks result from dividing each edge of the FPGA
into two banks, as shown in Figure 7 and Figure 8. Each
V
pins within a bank are interconnected internally, and
REF
consequently only one V
voltage can be used within
REF
bank has multiple V
pins, all of which must be con-
each bank. However, for correct operation, all V
pins in
CCO
REF
nected to the same voltage. This voltage is determined by
the output standards in use.
the bank must be connected to the external reference volt-
age source.
Table 5: Compatible Output Standards
V
Compatible Standards
Bank 0
Bank 1
CCO
3.3V PCI, LVTTL, SSTL3 (I & II), AGP-2X, LVDS_33,
LVDSEXT_33, LVCMOS33, LVDCI_33,
LVDCI_DV2_33, SSTL3_DCI (I & II), LVPECL,
GTL, GTLP
2.5V SSTL2 (I & II), LVCMOS25, GTL, GTLP,
LVDS_25, LVDSEXT_25, LVDCI_25,
LVDCI_DV2_25, SSTL2_DCI (I & II), LDT,
ULVDS, BLVDS
Bank 5
Bank 4
1.8V HSTL (I, II, III, & IV), LVCMOS18, GTL, GTLP,
ug002_c2_014_112900
LVDCI_18, LVDCI_DV2_18, HSTL_DCI (I,II, III &
IV)
Figure 7: Virtex-II I/O Banks: Top View for Wire-Bond
Packages (CS, FG, & BG)
1.5V HSTL (I, II, III, & IV), LVCMOS15, GTL, GTLP,
LVDCI_15, LVDCI_DV2_15, GTLP_DCI,
HSTL_DCI (I,II, III & IV)
Within a bank, output standards can be mixed only if they
use the same V
dards. GTL and GTLP appear under all voltages because
their open-drain outputs do not depend on V
. Table 5 lists compatible output stan-
CCO
1.2V GTL_DCI
.
CCO
The V
and the V
pins for each bank appear in the
REF
CCO
Some input standards require a user-supplied threshold
voltage, V . In this case, certain user-I/O pins are auto-
device pinout tables. Within a given package, the number of
and V pins can vary depending on the size of
REF
V
REF
CCO
matically configured as inputs for the V
imately one in six of the I/O pins in the bank assume this
role. Table 6 lists compatible input standards.
voltage. Approx-
REF
device. In larger devices, more I/O pins convert to V
pins. Since these are always a superset of the V
used for smaller devices, it is possible to design a PCB that
permits migration to a larger device if necessary.
REF
pins
REF
All V
pins for the largest device anticipated must be con-
REF
nected to the V
devices, some V
voltage and not used for I/O. In smaller
REF
Bank 1
Bank 0
pins used in larger devices do not con-
CCO
nect within the package. These unconnected pins can be
left unconnected externally, or, if necessary, they can be
connected to the V
larger device.
voltage to permit migration to a
CCO
Bank 4
Bank 5
ds031_66_112900
Figure 8: Virtex-II I/O Banks: Top View for Flip-Chip
Packages (FF & BF)
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Table 6: Compatible Input Standards
V
CCO
3.3V
2.5V
1.8V
1.5V
1.2V
V
REF
No V
LVTTL, LVDCI_33,
LVDCI_DV2_33,
LVCMOS33,
PCI33_3, PCI66_3,
PCI-X, LVDS_33,
LVDSEXT_33,
LVPECL_33,
LVCMOS25,
LVDCI_25,
LVDCI_DV2_25,
LVDS_33,
LVDSEXT_33,
LVDS_25,
LVCMOS18,
LVDCI_18,
LVDCI_DV2_18,
LVDS_33, LVDS_25, LDT, ULVDS_25
LDT, ULVDS_25
LVCMOS15,
LVDCI_15,
LVDCI_DV2_15,
-
REF
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
LVDS_25,
LVDSEXT_25, LDT,
BLVDS,
(2)
ULVDS_25
1.5V
LVTTL, LVDCI_33,
LVDCI_DV2_33,
LVCMOS33,
PCI33_3, PCI66_3,
PCI-X, LVDS_33,
LVDSEXT_33,
LVCMOS25,
LVDCI_25,
LVDCI_DV2_25,
LVDS_33,
LVDSEXT_33,
LVDS_25,
LVCMOS18,
LVDCI_18,
LVDCI_DV2_18,
LVDS_33, LVDS_25, LDT, ULVDS_25
LDT, ULVDS_25
LVCMOS15,
LVDCI_15,
LVDCI_DV2_15,
-
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
LVDSEXT_25, LDT,
BLVDS, ULVDS_25,
SSTL3_I_DCI,
SSTL3_II_DCI
SSTL3_I, SSTL3_II
SSTL3_I, SSTL3_II
-
-
-
-
1.32V
LVTTL, LVDCI_33,
LVDCI_DV2_33,
LVCMOS33,
PCI33_3, PCI66_3,
PCI-X, LVDS_33,
LVDSEXT_33,
LVCMOS25,
LVDCI_25,
LVDCI_DV2_25,
LVDS_33,
LVDSEXT_33,
LVDS_25,
LVCMOS18,
LVDCI_18,
LVDCI_DV2_18,
LVDS_33, LVDS_25, LDT, ULVDS_25
LDT, ULVDS_25
LVCMOS15,
LVDCI_15,
LVDCI_DV2_15,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
AGP-2X/AGP
-
-
-
-
-
1.25V
LVTTL, LVDCI_33,
LVDCI_DV2_33,
LVCMOS33,
PCI33_3, PCI66_3,
PCI-X, LVDS_33,
LVDSEXT_33,
LVCMOS25,
LVDCI_25,
LVDCI_DV2_25,
LVDS_33,
LVDSEXT_33,
LVDS_25,
LVCMOS18,
LVDCI_18,
LVDCI_DV2_18,
LVDS_33, LVDS_25, LDT, ULVDS_25
LDT, ULVDS_25
LVCMOS15,
LVDCI_15,
LVDCI_DV2_15,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
LVDSEXT_25, LDT,
BLVDS, ULVDS_25,
SSTL2_I_DCI,
SSTL2_II_DCI
SSTL2_I, SSTL2_II
SSTL2_I, SSTL2_II
-
-
-
DS031-2 (v2.1) September 26, 2002
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Virtex-II 1.5V Field-Programmable Gate Arrays
Table 6: Compatible Input Standards (Continued)
V
CCO
3.3V
2.5V
1.8V
1.5V
1.2V
V
REF
1.0V
LVTTL, LVDCI_33,
LVDCI_DV2_33,
LVCMOS33,
PCI33_3, PCI66_3,
PCI-X, LVDS_33,
LVDSEXT_33,
LVCMOS25,
LVDCI_25,
LVDCI_DV2_25,
LVDS_33,
LVDSEXT_33,
LVDS_25,
LVCMOS18,
LVDCI_18,
LVDCI_DV2_18,
LVDS_33, LVDS_25, GTLP_DCI, LDT,
LDT, ULVDS_25 ULVDS_25
LVCMOS15,
LVDCI_15,
LVDCI_DV2_15,
-
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
GTLP
GTLP
GTLP
GTLP
-
-
0.9V
LVTTL, LVDCI_33,
LVDCI_DV2_33,
LVCMOS33,
PCI33_3, PCI66_3,
PCI-X, LVDS_33,
LVDSEXT_33,
LVCMOS25,
LVDCI_25,
LVDCI_DV2_25,
LVDS_33,
LVDSEXT_33,
LVDS_25,
LVCMOS18,
LVDCI_18,
LVDCI_DV2_18,
LVCMOS15,
LVDCI_15,
LVDCI_DV2_15,
LVDS_33, LVDS_25, LDT, ULVDS_25,
LDT, ULVDS_25,
HSTL_III_DCI,
HSTL_IV_DCI
HSTL_III_DCI,
HSTL_IV_DCI
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
HSTL_III, HSTL_IV
HSTL_III, HSTL_IV
HSTL_III, HSTL_IV
HSTL_III, HSTL_IV
-
0.8V
LVTTL, LVDCI_33,
LVDCI_DV2_33,
LVCMOS33,
PCI33_3, PCI66_3,
PCI-X, LVDS_33,
LVDSEXT_33,
LVCMOS25,
LVDCI_25,
LVDCI_DV2_25,
LVDS_33,
LVDSEXT_33,
LVDS_25,
LVCMOS18,
LVDCI_18,
LVDCI_DV2_18,
LVDS_33, LVDS_25, LDT, ULVDS_25
LDT, ULVDS_25
LVCMOS15,
LVDCI_15,
LVDCI_DV2_15,
GTL_DCI
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
GTL
GTL
GTL
GTL
GTL
-
0.75V
LVTTL, LVDCI_33,
LVDCI_DV2_33,
LVCMOS33,
PCI33_3, PCI66_3,
PCI-X, LVDS_33,
LVDSEXT_33,
LVCMOS25,
LVDCI_25,
LVDCI_DV2_25,
LVDS_33,
LVDSEXT_33,
LVDS_25,
LVCMOS18,
LVDCI_18,
LVDCI_DV2_18,
LVCMOS15,
LVDCI_15,
LVDCI_DV2_15,
LVDS_33, LVDS_25, LDT, ULVDS_25,
LDT, ULVDS_25,
HSTL_III_DCI,
HSTL_IV_DCI
HSTL_I_DCI,
HSTL_II_DCI
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
HSTL_I, HSTL_II
HSTL_I, HSTL_II
HSTL_I, HSTL_II
HSTL_I, HSTL_II
-
Notes:
1. Inputs that are V
controlled are completely independent of those that are V
controlled. Therefore, V controlled inputs can
REF
CCO
REF
CCO
also be placed in banks with inputs and outputs of different voltages that are V
controlled.
2. All non-DCI differential inputs are V
controlled. This makes them (Inputs Only) very flexible in terms of banking rules.
CCAUX
3. Care must be taken to ensure that the input DC levels are within V
+ 0.5V, because all user I/Os have clamp diodes connected
CCO
to V
.
CCO
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Virtex-II 1.5V Field-Programmable Gate Arrays
Controlled Impedance Drivers (Series
Termination)
DCI can be used to provide a buffer with a controlled output
impedance. It is desirable for this output impedance to
match the transmission line impedance (Z). Virtex-II input
buffers also support LVDCI and LVDCI_DV2 I/O standards.
Digitally Controlled Impedance (DCI)
Today’s chip output signals with fast edge rates require ter-
mination to prevent reflections and maintain signal integrity.
High pin count packages (especially ball grid arrays) can
not accommodate external termination resistors.
Virtex-II DCI provides controlled impedance drivers and
on-chip termination for single-ended I/Os. This eliminates
the need for external resistors, and improves signal integrity.
The DCI feature can be used on any IOB by selecting one of
the DCI I/O standards.
IOB
Z
Z
When applied to inputs, DCI provides input parallel termina-
tion. When applied to outputs, DCI provides controlled
impedance drivers (series termination) or output parallel
termination.
Virtex-II DCI
V
= 3.3 V, 2.5 V, 1.8 V or 1.5 V
CCO
DS031_51_110600
Figure 10: Internal Series Termination
DCI operates independently on each I/O bank. When a DCI
I/O standard is used in a particular I/O bank, external refer-
ence resistors must be connected to two dual-function pins
on the bank. These resistors, voltage reference of N transis-
tor (VRN) and the voltage reference of P transistor (VRP)
are shown in Figure 9.
Table 7: SelectI/O-Ultra Controlled Impedance Buffers
V
DCI
DCI Half Impedance
LVDCI_DV2_33
LVDCI_DV2_25
LVDCI_DV2_18
LVDCI_DV2_15
CCO
3.3 V
2.5 V
1.8 V
1.5 V
LVDCI_33
LVDCI_25
LVDCI_18
LVDCI_15
1 Bank
DCI
DCI
Controlled Impedance Drivers (Parallel
Termination)
DCI also provides on-chip termination for SSTL3, SSTL2,
HSTL (Class I, II, III, or IV), and GTL/GTLP receivers or
transmitters on bidirectional lines.
DCI
DCI
V
CCO
Table 8 lists the on-chip parallel terminations available in Vir-
tex-II devices. V
that there is a V
GTLP_DCI, due to the on-chip termination resistor.
must be set according to Table 3. Note
CCO
R
(1%)
(1%)
REF
requirement for GTL_DCI and
CCO
VRN
VRP
Table 8: SelectI/O-Ultra Buffers With On-Chip Parallel
Termination
R
REF
External
On-Chip
GND
I/O Standard
SSTL3 Class I
SSTL3 Class II
SSTL2 Class I
SSTL2 Class II
HSTL Class I
HSTL Class II
HSTL Class III
HSTL Class IV
GTL
Termination
Termination
DS031_50_101200
(1)
Figure 9: DCI in a Virtex-II Bank
SSTL3_I
SSTL3_II
SSTL2_I
SSTL2_II
HSTL_I
HSTL_II
HSTL_III
HSTL_IV
GTL
SSTL3_I_DCI
SSTL3_II_DCI
SSTL2_I_DCI
SSTL2_II_DCI
(1)
(1)
(1)
When used with a terminated I/O standard, the value of
resistors are specified by the standard (typically 50 Ω).
When used with a controlled impedance driver, the resistors
set the output impedance of the driver within the specified
range (25 Ω to 100 Ω). For all series and parallel termina-
tions listed in Table 7 and Table 8, the reference resistors
must have the same value for any given bank. One percent
resistors are recommended.
HSTL_I_DCI
HSTL_II_DCI
HSTL_III_DCI
HSTL_IV_DCI
GTL_DCI
The DCI system adjusts the I/O impedance to match the two
external reference resistors, or half of the reference resis-
tors, and compensates for impedance changes due to volt-
age and/or temperature fluctuations. The adjustment is
done by turning parallel transistors in the IOB on or off.
GTLP
GTLP
GTLP_DCI
Notes:
1. SSTL Compatible
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Virtex-II 1.5V Field-Programmable Gate Arrays
Figure 11 provides examples illustrating the use of the HSTL_I_DCI, HSTL_II_DCI, HSTL_III_DCI, and HSTL_IV_DCI I/O
standards. For a complete list, see the Virtex-II User Guide.
HSTL_I
HSTL_II
HSTL_III
HSTL_IV
V
/2
V
/2
V
/2
V
V
V
CCO
CCO
CCO
CCO
CCO
R
CCO
R
R
R
R
R
Conventional
Z
Z
Z
0
Z
0
0
0
V
V
/2
CCO
V
/2
CCO
CCO
V
V
V
DCI Transmit
Conventional
Receive
CCO
CCO
CCO
R
2R
R
R
R
R
Z
Z
0
0
Z
Z
0
0
2R
Virtex-II DCI
Virtex-II DCI
Virtex-II DCI
Virtex-II DCI
V
/2
V
V
CCO
CCO
2R
CCO
2R
V
V
V
Conventional
Transmit
DCI Receive
CCO
R
CCO
CCO
R
R
R
Z
Z
0
0
Z
Z
0
0
2R
2R
Virtex-II DCI
Virtex-II DCI
Virtex-II DCI
Virtex-II DCI
V
V
V
CCO
CCO
2R
CCO
V
V
CCO
V
CCO
R
CCO
R
2R
2R
DCI Transmit
DCI Receive
R
Z
Z
0
0
Z
Z
0
0
2R
2R
2R
Virtex-II DCI
Virtex-II DCI
Virtex-II DCI
Virtex-II DCI
Virtex-II DCI
Virtex-II DCI Virtex-II DCI
Virtex-II DCI
V
V
V
V
CCO
CCO
CCO
CCO
R
2R
R
2R
Z
Z
0
0
Bidirectional
N/A
N/A
2R
2R
Virtex-II DCI
Virtex-II DCI
Virtex-II DCI
Virtex-II DCI
Reference
Resistor
VRN = VRP = R = Z
VRN = VRP = R = Z
VRN = VRP = R = Z
VRN = VRP = R = Z
0
0
0
0
Recommended
50 Ω
50 Ω
50 Ω
50 Ω
Z
0
DS031_65a_100201
Figure 11: HSTL DCI Usage Examples
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Virtex-II 1.5V Field-Programmable Gate Arrays
Figure 12 provides examples illustrating the use of the SSTL2_I_DCI, SSTL2_II_DCI, SSTL3_I_DCI, and SSTL3_II_DCI I/O
standards. For a complete list, see the Virtex-II User Guide.
SSTL2_I
SSTL2_II
SSTL3_I
SSTL3_II
V
/2
V
/2
CCO
CCO
V
/2
V
/2
V
/2
V
/2
CCO
CCO
CCO
CCO
R
R
R
R
R
R
Conventional
Z
0
Z
0
Z
Z
0
0
R/2
R/2
R/2
R/2
V
/2
CCO
V
V
/2
CCO
V
V
/2
CCO
CCO
CCO
V
/2
CCO
DCI Transmit
Conventional
Receive
25Ω
25Ω
R
2R
R
R
2R
2R
25Ω
25Ω
R
Z
Z
0
0
Z
0
Z
0
2R
Virtex-II DCI
Virtex-II DCI
Virtex-II DCI
Virtex-II DCI
V
V
V
V
V
V
CCO/2
CCO
2R
CCO/2
CCO
2R
CCO
2R
CCO
2R
Conventional
Transmit
DCI Receive
R
R
Z
Z
Z
Z
0
0
0
0
R/2
R/2
R/2
R/2
2R
2R
2R
2R
Virtex-II DCI
Virtex-II DCI
Virtex-II DCI
Virtex-II DCI
V
V
V
V
V
CCO
V
CCO
CCO
CCO
CCO
CCO
25Ω
2R
25Ω
2R
2R
25Ω
2R
2R
25Ω
2R
DCI Transmit
DCI Receive
Z
0
Z
Z
Z
0
0
0
2R
2R
2R
2R
2R
2R
Virtex-II DCI
Virtex-II DCI
Virtex-II DCI
Virtex-II DCI
Virtex-II DCI
Virtex-II DCI
Virtex-II DCI
Virtex-II DCI
V
V
V
V
CCO
CCO
CCO
CCO
25Ω
25Ω
2R
2R
2R
2R
Z
Z
0
0
Bidirectional
N/A
N/A
2R
2R
2R
2R
25Ω
Virtex-II DCI
25Ω
Virtex-II DCI
Virtex-II DCI
Virtex-II DCI
Reference
Resistor
VRN = VRP = R = Z
VRN = VRP = R = Z
VRN = VRP = R = Z
VRN = VRP = R = Z
0
0
0
0
Recommended
50 Ω
50 Ω
50 Ω
50 Ω
Z
0
DS031_65b_100201
Figure 12: SSTL DCI Usage Examples
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Virtex-II 1.5V Field-Programmable Gate Arrays
Figure 13 provides examples illustrating the use of the LVDS_DCI and LVDSEXT_DCI I/O standards. For a complete list,
see the Virtex-II User Guide.
LVDS_DCI and LVDSEXT_DCI Receiver
Z
0
2R
Conventional
Z
0
Virtex-II
LVDS
V
CCO
2R
2R
Z
0
Conventional
Transmit
DCI Receive
V
CCO
2R
2R
Z
0
Virtex-II
LVDS DCI
Reference
Resistor
VRN = VRP = R = Z
0
Recommended
50 Ω
Z
0
DS031_65c_082102
Figure 13: LVDS DCI Usage Examples
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Virtex-II 1.5V Field-Programmable Gate Arrays
Configurable Logic Blocks (CLBs)
The Virtex-II configurable logic blocks (CLB) are organized
in an array and are used to build combinatorial and synchro-
nous logic designs. Each CLB element is tied to a switch
matrix to access the general routing matrix, as shown in
Figure 14. A CLB element comprises 4 similar slices, with
fast local feedback within the CLB. The four slices are split
in two columns of two slices with two independent carry
logic chains and one common shift chain.
Configurations
Look-Up Table
Virtex-II function generators are implemented as 4-input
look-up tables (LUTs). Four independent inputs are pro-
vided to each of the two function generators in a slice (F and
G). These function generators are each capable of imple-
menting any arbitrarily defined boolean function of four
inputs. The propagation delay is therefore independent of
the function implemented. Signals from the function gener-
ators can exit the slice (X or Y output), can input the XOR
dedicated gate (see arithmetic logic), or input the carry-logic
multiplexer (see fast look-ahead carry logic), or feed the D
input of the storage element, or go to the MUXF5 (not
shown in Figure 16).
COUT
TBUF X0Y1
TBUF X0Y0
Slice
X1Y1
Slice
X1Y0
COUT
Switch
Matrix
In addition to the basic LUTs, the Virtex-II slice contains
logic (MUXF5 and MUXFX multiplexers) that combines
function generators to provide any function of five, six,
seven, or eight inputs. The MUXFX are either MUXF6,
MUXF7 or MUXF8 according to the slice considered in the
CLB. Selected functions up to nine inputs (MUXF5 multi-
plexer) can be implemented in one slice. The MUXFX can
also be a MUXF6, MUXF7, or MUXF8 multiplexers to map
any functions of six, seven, or eight inputs and selected
wide logic functions.
SHIFT
CIN
Slice
X0Y1
Fast
Slice
X0Y0
Connects
to neighbors
DS031_32_101600
CIN
Figure 14: Virtex-II CLB Element
Slice Description
Register/Latch
Each slice includes two 4-input function generators, carry
logic, arithmetic logic gates, wide function multiplexers and
two storage elements. As shown in Figure 15, each 4-input
function generator is programmable as a 4-input LUT, 16
bits of distributed SelectRAM memory, or a 16-bit vari-
able-tap shift register element.
The storage elements in a Virtex-II slice can be configured
either as edge-triggered D-type flip-flops or as level-sensi-
tive latches. The D input can be directly driven by the X or Y
output via the DX or DY input, or by the slice inputs bypass-
ing the function generators via the BX or BY input. The clock
enable signal (CE) is active High by default. If left uncon-
nected, the clock enable for that storage element defaults to
the active state.
The output from the function generator in each slice drives
both the slice output and the D input of the storage element.
Figure 16 shows a more detailed view of a single slice.
In addition to clock (CK) and clock enable (CE) signals,
each slice has set and reset signals (SR and BY slice
inputs). SR forces the storage element into the state speci-
fied by the attribute SRHIGH or SRLOW. SRHIGH forces a
logic “1” when SR is asserted. SRLOW forces a logic “0”.
When SR is used, a second input (BY) forces the storage
element into the opposite state. The reset condition is pre-
dominant over the set condition. (See Figure 17.)
ORCY
RAM16
MUXFx
SRL16
Register
CY
LUT
G
The initial state after configuration or global initial state is
defined by a separate INIT0 and INIT1 attribute. By default,
setting the SRLOW attribute sets INIT0, and setting the
SRHIGH attribute sets INIT1.
RAM16
MUXF5
CY
SRL16
Register
For each slice, set and reset can be set to be synchronous
or asynchronous. Virtex-II devices also have the ability to
set INIT0 and INIT1 independent of SRHIGH and SRLOW.
LUT
F
Arithmetic Logic
The control signals clock (CLK), clock enable (CE) and
set/reset (SR) are common to both storage elements in one
slice. All of the control signals have independent polarity. Any
inverter placed on a control input is automatically absorbed.
DS031_31_100900
Figure 15: Virtex-II Slice Configuration
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Virtex-II 1.5V Field-Programmable Gate Arrays
COUT
SHIFTIN
ORCY
SOPIN
SOPOUT
YB
0
Dual-Port
Shift-Reg
YBMUX
MUXCY
1
A4
A3
G4
G3
1
0
LUT
RAM
ROM
A2
A1
G2
G1
D
GYMUX
WG4
WG3
WG2
WG1
WG4
WG3
WG2
WG1
Y
G
DY
MC15
DI
XORG
FF
LATCH
WS
ALTDIG
DYMUX
CE
D
Q
G2
PROD
G1
Q
Y
MULTAND
CE
CLK CK
CYOG
BY
1
0
SR REV
BY
SLICEWE[2:0]
WSG
SR
SHIFTOUT
WE[2:0]
WE
DIG
CLK
MUXCY
1
0
WSF
CE
CLK
SR
Shared between
x & y Registers
CIN
DS031_01_080601
Figure 16: Virtex-II Slice (Top Half)
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Virtex-II 1.5V Field-Programmable Gate Arrays
Distributed SelectRAM memory modules are synchronous
(write) resources. The combinatorial read access time is
extremely fast, while the synchronous write simplifies
high-speed designs. A synchronous read can be imple-
mented with a storage element in the same slice. The dis-
tributed SelectRAM memory and the storage element share
the same clock input. A Write Enable (WE) input is active
High, and is driven by the SR input.
FFY
FF
LATCH
DY
YQ
Attribute
D
Q
CE
CK
INIT1
INIT0
SRHIGH
SRLOW
SR REV
Table 9 shows the number of LUTs (2 per slice) occupied by
each distributed SelectRAM configuration.
BY
FFX
Table 9: Distributed SelectRAM Configurations
FF
LATCH
RAM
Number of LUTs
DX
D
XQ
Q
16 x 1S
16 x 1D
32 x 1S
32 x 1D
64 x 1S
64 x 1D
128 x 1S
1
2
2
4
4
8
8
Attribute
CE
CE
CK
SR REV
INIT1
INIT0
SRHIGH
SRLOW
CLK
SR
BX
Reset Type
SYNC
ASYNC
DS031_22_110600
Figure 17: Register / Latch Configuration in a Slice
Notes:
1. S = single-port configuration; D = dual-port configuration
The set and reset functionality of a register or a latch can be
configured as follows:
For single-port configurations, distributed SelectRAM mem-
ory has one address port for synchronous writes and asyn-
chronous reads.
•
•
•
•
•
•
•
No set or reset
Synchronous set
Synchronous reset
For dual-port configurations, distributed SelectRAM mem-
ory has one port for synchronous writes and asynchronous
reads and another port for asynchronous reads. The func-
tion generator (LUT) has separated read address inputs
(A1, A2, A3, A4) and write address inputs (WG1/WF1,
WG2/WF2, WG3/WF3, WG4/WF4).
Synchronous set and reset
Asynchronous set (preset)
Asynchronous reset (clear)
Asynchronous set and reset (preset and clear)
The synchronous reset has precedence over a set, and an
asynchronous clear has precedence over a preset.
In single-port mode, read and write addresses share the
same address bus. In dual-port mode, one function genera-
tor (R/W port) is connected with shared read and write
addresses. The second function generator has the A inputs
(read) connected to the second read-only port address and
the W inputs (write) shared with the first read/write port
address.
Distributed SelectRAM Memory
Each function generator (LUT) can implement a 16 x 1-bit
synchronous RAM resource called a distributed SelectRAM
element. The SelectRAM elements are configurable within
a CLB to implement the following:
•
•
•
•
•
•
•
Single-Port 16 x 8 bit RAM
Single-Port 32 x 4 bit RAM
Single-Port 64 x 2 bit RAM
Single-Port 128 x 1 bit RAM
Dual-Port 16 x 4 bit RAM
Dual-Port 32 x 2 bit RAM
Dual-Port 64 x 1 bit RAM
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Virtex-II 1.5V Field-Programmable Gate Arrays
Figure 18, Figure 19, and Figure 20 illustrate various exam-
ple configurations.
RAM 16x1D
RAM 16x1S
dual_port
RAM
G[4:1]
4
4
DPRA[3:0]
A[3:0]
DPO
D
RAM
4
WG[4:1]
WS
Output
D
A[3:0]
D
A[4:1]
DI
4
WG[4:1]
Registered
Output
(BY)
D
Q
D
WS
DI
(BY)
WSG
(optional)
WSG
WE
CK
(SR)
WE
CK
WE
WCLK
dual_port
RAM
DS031_02_100900
4
A[3:0]
G[4:1]
SPO
D
Figure 18: Distributed SelectRAM (RAM16x1S)
WG[4:1]
WS
DI
RAM 32x1S
(BX)
WSG
A[4]
(SR)
RAM
WE
WCLK
WE
CK
4
D
A[3:0]
G[4:1]
WG[4:1]
WS DI
DS031_04_110100
(BY)
(SR)
D
Figure 20: Dual-Port Distributed SelectRAM
WSG
WE0
WE
(RAM16x1D)
Output
WE
WCLK
CK
Similar to the RAM configuration, each function generator
(LUT) can implement a 16 x 1-bit ROM. Five configurations
Registered
Output
D Q
F5MUX
WSF
are
available:
ROM16x1,
ROM32x1,
ROM64x1,
WS
RAM
DI
ROM128x1, and ROM256x1. The ROM elements are cas-
cadable to implement wider or/and deeper ROM. ROM con-
tents are loaded at configuration. Table 10 shows the
number of LUTs occupied by each configuration.
(optional)
D
4
F[4:1]
WF[4:1]
Table 10: ROM Configuration
DS031_03_110100
ROM
16 x 1
32 x 1
64 x 1
128 x 1
256 x 1
Number of LUTs
Figure 19: Single-Port Distributed SelectRAM
1
(RAM32x1S)
2
4
8 (1 CLB)
16 (2 CLBs)
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Virtex-II 1.5V Field-Programmable Gate Arrays
Shift Registers
Each function generator can also be configured as a 16-bit
shift register. The write operation is synchronous with a
clock input (CLK) and an optional clock enable, as shown in
Figure 21. A dynamic read access is performed through the
4-bit address bus, A[3:0]. The configurable 16-bit shift regis-
ter cannot be set or reset. The read is asynchronous, how-
ever the storage element or flip-flop is available to
implement a synchronous read. The storage element
should always be used with a constant address. For exam-
ple, when building an 8-bit shift register and configuring the
addresses to point to the 7th bit, the 8th bit can be the
flip-flop. The overall system performance is improved by
using the superior clock-to-out of the flip-flops.
1 Shift Chain
in CLB
DI
SRLC16
MC15
D
IN
FF
DI
SRLC16
D
FF
MC15
SLICE S3
SHIFTOUT
SHIFTIN
D
DI
FF
SRLC16
SRLC16
SHIFTIN
MC15
SHIFT-REG
4
DI
Output
D
D
FF
A[3:0]
D(BY)
A[4:1]
SRLC16
MC15
Registered
Output
MC15
D
Q
SLICE S2
DI
WS
SHIFTOUT
(optional)
WSG
CE (SR)
CLK
WE
CK
SHIFTIN
DI
SRLC16
MC15
D
FF
FF
SHIFTOUT
DS031_05_110600
Figure 21: Shift Register Configurations
DI
SRLC16
D
An additional dedicated connection between shift registers
allows connecting the last bit of one shift register to the first
bit of the next, without using the ordinary LUT output. (See
Figure 22.) Longer shift registers can be built with dynamic
access to any bit in the chain. The shift register chaining
and the MUXF5, MUXF6, and MUXF7 multiplexers allow up
to a 128-bit shift register with addressable access to be
implemented in one CLB.
MC15
SLICE S1
SHIFTOUT
FF
SHIFTIN
D
SRLC16
MC15
DI
DI
SRLC16
MC15
D
FF
SLICE S0
CLB
OUT
CASCADABLE OUT
DS031_06_110200
Figure 22: Cascadable Shift Register
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Virtex-II 1.5V Field-Programmable Gate Arrays
Multiplexers
Each Virtex-II slice has one MUXF5 multiplexer and one
MUXFX multiplexer. The MUXFX multiplexer implements
the MUXF6, MUXF7, or MUXF8, as shown in Figure 23.
Each CLB element has two MUXF6 multiplexers, one
MUXF7 multiplexer and one MUXF8 multiplexer. Examples
of multiplexers are shown in the Virtex-II User Guide. Any
LUT can implement a 2:1 multiplexer.
Virtex-II function generators and associated multiplexers
can implement the following:
•
•
•
•
4:1 multiplexer in one slice
8:1 multiplexer in two slices
16:1 multiplexer in one CLB element (4 slices)
32:1 multiplexer in two CLB elements (8 slices)
MUXF8 combines
the two MUXF7 outputs
(Two CLBs)
G
F
Slice S3
MUXF6 combines the two MUXF5
outputs from slices S2 and S3
G
F
Slice S2
MUXF7 combines the two MUXF6
outputs from slices S0 and S2
G
Slice S1
F
MUXF6 combines the two MUXF5
outputs from slices S0 and S1
G
F
Slice S0
CLB
DS031_08_100201
Figure 23: MUXF5 and MUXFX multiplexers
Fast Lookahead Carry Logic
be used to cascade function generators for implementing
wide logic functions.
Dedicated carry logic provides fast arithmetic addition and
subtraction. The Virtex-II CLB has two separate carry
chains, as shown in the Figure 24.
Arithmetic Logic
The arithmetic logic includes an XOR gate that allows a
2-bit full adder to be implemented within a slice. In addition,
a dedicated AND (MULT_AND) gate (shown in Figure 16)
improves the efficiency of multiplier implementation.
The height of the carry chains is two bits per slice. The carry
chain in the Virtex-II device is running upward. The dedi-
cated carry path and carry multiplexer (MUXCY) can also
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Virtex-II 1.5V Field-Programmable Gate Arrays
COUT
COUT
to S0 of the next CLB
to CIN of S2 of the next CLB
MUXCY
O
O
I
I
FF
FF
LUT
LUT
(First Carry Chain)
SLICE S3
MUXCY
CIN
COUT
MUXCY
O
O
I
I
FF
FF
LUT
LUT
SLICE S2
MUXCY
MUXCY
FF
O
O
I
I
LUT
LUT
SLICE S1
MUXCY
FF
CIN
COUT
(Second Carry Chain)
MUXCY
FF
O
O
I
I
LUT
LUT
SLICE S0
MUXCY
FF
CIN
CIN
CLB
DS031_07_110200
Figure 24: Fast Carry Logic Path
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Virtex-II 1.5V Field-Programmable Gate Arrays
Sum of Products
Each Virtex-II slice has a dedicated OR gate named ORCY,
ORing together outputs from the slices carryout and the ORCY
from an adjacent slice. The ORCY gate with the dedicated
Sum of Products (SOP) chain are designed for implementing
large, flexible SOP chains. One input of each ORCY is con-
nected through the fast SOP chain to the output of the previous
ORCY in the same slice row. The second input is connected to
the output of the top MUXCY in the same slice, as shown in
Figure 25.
LUTs and MUXCYs can implement large AND gates or
other combinatorial logic functions. Figure 26 illustrates
LUT and MUXCY resources configured as a 16-input AND
gate.
ORCY
ORCY
ORCY
ORCY
SOP
4
4
4
4
4
4
4
4
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
MUXCY
MUXCY
MUXCY
MUXCY
Slice 1
Slice 3
Slice 1
Slice 3
MUXCY
MUXCY
MUXCY
MUXCY
4
4
4
4
4
4
4
4
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
MUXCY
MUXCY
MUXCY
MUXCY
Slice 0
Slice 2
Slice 0
Slice 2
MUXCY
V
MUXCY
V
MUXCY
V
MUXCY
V
CC
CC
CC
CC
CLB
CLB
ds031_64_110300
Figure 25: Horizontal Cascade Chain
OUT
4
4
MUXCY
0
1
LUT
“0”
Slice
MUXCY
0
1
LUT
“0”
16
AND
OUT
4
4
MUXCY
0
1
LUT
LUT
“0”
Slice
MUXCY
0
1
V
CC
DS031_41_110600
Figure 26: Wide-Input AND Gate (16 Inputs)
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Virtex-II 1.5V Field-Programmable Gate Arrays
Locations / Organization
3-State Buffers
Four horizontal routing resources per CLB are provided for
on-chip 3-state busses. Each 3-state buffer has access
alternately to two horizontal lines, which can be partitioned
as shown in Figure 28. The switch matrices corresponding
to SelectRAM memory and multiplier or I/O blocks are
skipped.
Introduction
Each Virtex-II CLB contains two 3-state drivers (TBUFs)
that can drive on-chip busses. Each 3-state buffer has its
own 3-state control pin and its own input pin.
Each of the four slices have access to the two 3-state buff-
ers through the switch matrix, as shown in Figure 27.
TBUFs in neighboring CLBs can access slice outputs by
direct connects. The outputs of the 3-state buffers drive hor-
izontal routing resources used to implement 3-state busses.
Number of 3-State Buffers
Table 11 shows the number of 3-state buffers available in
each Virtex-II device. The number of 3-state buffers is twice
the number of CLB elements.
Table 11: Virtex-II 3-State Buffers
TBUF
3-State Buffers
per Row
Total Number
of 3-State Buffers
Device
XC2V40
TBUF
Slice
S3
16
16
128
256
Switch
Matrix
Slice
S2
XC2V80
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
32
768
Slice
S1
48
1,536
2,560
3,840
5,376
7,168
11,520
16,896
23,296
Slice
S0
64
80
DS031_37_060700
Figure 27: Virtex-II 3-State Buffers
96
112
144
176
208
The 3-state buffer logic is implemented using AND-OR logic
rather than 3-state drivers, so that timing is more predict-
able and less load dependant especially with larger devices.
3 - state lines
Programmable
connection
Switch
matrix
CLB-II
Switch
matrix
CLB-II
DS031_09_032700
Figure 28: 3-State Buffer Connection to Horizontal Lines
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Virtex-II 1.5V Field-Programmable Gate Arrays
CLB/Slice Configurations
Table 12 summarizes the logic resources in one CLB. All of the CLBs are identical and each CLB or slice can be
implemented in one of the configurations listed. Table 13 shows the available resources in all CLBs.
Table 12: Logic Resources in One CLB
Arithmetic &
MULT_ANDs Carry-Chains Chains
SOP
Distributed
SelectRAM
Shift
Registers TBUF
Slices
LUTs
Flip-Flops
4
8
8
8
2
2
128 bits
128 bits
2
Table 13: Virtex-II Logic Resources Available in All CLBs
CLB Array: Number Number
Max Distributed
SelectRAM or Shift
Register (bits)
Number
of
Flip-Flops Carry-Chains
Number
Number
of SOP
Chains
Row x
of
of
of
(1)
(1)
Device
Column
Slices
LUTs
XC2V40
8 x 8
16 x 8
256
512
8,192
16,384
512
16
16
16
XC2V80
512
1,024
1,024
32
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
24 x 16
32 x 24
40 x 32
48 x 40
56 x 48
64 x 56
80 x 72
96 x 88
112 x 104
1,536
3,072
5,120
7,680
10,752
14,336
23,040
33,792
46,592
3,072
49,152
3,072
32
48
6,144
98,304
6,144
48
64
10,240
15,360
21,504
28,672
46,080
67,584
93,184
163,840
245,760
344,064
458,752
737,280
1,081,344
1,490,944
10,240
15,360
21,504
28,672
46,080
67,584
93,184
64
80
80
96
96
112
128
160
192
224
112
144
176
208
Notes:
1. The carry-chains and SOP chains can be split or cascaded.
18 Kbit Block SelectRAM Resources
Introduction
Virtex-II devices incorporate large amounts of 18 Kbit block
SelectRAM. These complement the distributed SelectRAM
resources that provide shallow RAM structures imple-
mented in CLBs. Each Virtex-II block SelectRAM is an 18
Kbit true dual-port RAM with two independently clocked and
independently controlled synchronous ports that access a
common storage area. Both ports are functionally identical.
CLK, EN, WE, and SSR polarities are defined through con-
figuration.
need only) be valid during the set-up time window prior to a
rising (or falling, a configuration option) clock edge. Data
outputs change as a result of the same clock edge.
Configuration
The Virtex-II block SelectRAM supports various configura-
tions, including single- and dual-port RAM and various
data/address aspect ratios. Supported memory configura-
tions for single- and dual-port modes are shown in Table 14.
Each port has the following types of inputs: Clock and Clock
Enable, Write Enable, Set/Reset, and Address, as well as
separate Data/parity data inputs (for write) and Data/parity
data outputs (for read).
Table 14: Dual- and Single-Port Configurations
16K x 1 bit
8K x 2 bits
4K x 4 bits
2K x 9 bits
1K x 18 bits
512 x 36 bits
Operation is synchronous; the block SelectRAM behaves
like a register. Control, address and data inputs must (and
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Virtex-II 1.5V Field-Programmable Gate Arrays
Single-Port Configuration
Dual-Port Configuration
As a single-port RAM, the block SelectRAM has access to
the 18 Kbit memory locations in any of the 2K x 9-bit,
1K x 18-bit, or 512 x 36-bit configurations and to 16 Kbit
memory locations in any of the 16K x 1-bit, 8K x 2-bit, or
4K x 4-bit configurations. The advantage of the 9-bit, 18-bit
and 36-bit widths is the ability to store a parity bit for each
eight bits. Parity bits must be generated or checked exter-
nally in user logic. In such cases, the width is viewed as 8 +
1, 16 + 2, or 32 + 4. These extra parity bits are stored and
behave exactly as the other bits, including the timing param-
eters. Video applications can use the 9-bit ratio of Virtex-II
block SelectRAM memory to advantage.
As a dual-port RAM, each port of block SelectRAM has
access to a common 18 Kbit memory resource. These are
fully synchronous ports with independent control signals for
each port. The data widths of the two ports can be config-
ured independently, providing built-in bus-width conversion.
Table 15 illustrates the different configurations available on
ports A & B.
Each block SelectRAM cell is a fully synchronous memory
as illustrated in Figure 29. Input data bus and output data
bus widths are identical.
18 Kbit Block SelectRAM
DI
DIP
ADDR
WE
EN
SSR
CLK
DO
DOP
DS031_10_071602
Figure 29: 18 Kbit Block SelectRAM Memory in
Single-Port Mode
Table 15: Dual-Port Mode Configurations
Port A
Port B
Port A
Port B
Port A
Port B
Port A
Port B
Port A
Port B
Port A
Port B
16K x 1
16K x 1
8K x 2
16K x 1
8K x 2
16K x 1
4K x 4
16K x 1
2K x 9
16K x 1
1K x 18
8K x 2
16K x 1
512 x 36
8K x 2
8K x 2
8K x 2
8K x 2
4K x 4
2K x 9
1K x 18
4K x 4
512 x 36
4K x 4
4K x 4
4K x 4
4K x 4
2K x 9
1K x 18
2K x 9
512 x 36
2K x 9
2K x 9
2K x 9
1K x 18
1K x 18
512 x 36
512 x 36
1K x 18
1K x 18
512 x 36
512 x 36
If both ports are configured in either 2K x 9-bit, 1K x 18-bit,
or 512 x 36-bit configurations, the 18 Kbit block is accessi-
ble from port A or B. If both ports are configured in either
16K x 1-bit, 8K x 2-bit. or 4K x 4-bit configurations, the
16 K-bit block is accessible from Port A or Port B. All other
configurations result in one port having access to an 18 Kbit
memory block and the other port having access to a 16 K-bit
subset of the memory block equal to 16 Kbits.
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Virtex-II 1.5V Field-Programmable Gate Arrays
Each block SelectRAM cell is a fully synchronous memory,
as illustrated in Figure 30. The two ports have independent
inputs and outputs and are independently clocked.
Table 16: 18 Kbit Block SelectRAM Port Aspect Ratio
Width
Depth
16,384
8,192
4,096
2,048
1,024
512
Address Bus
ADDR[13:0]
ADDR[12:0]
ADDR[11:0]
ADDR[10:0]
ADDR[9:0]
Data Bus
DATA[0]
Parity Bus
N/A
1
2
18 Kbit Block SelectRAM
DATA[1:0]
DATA[3:0]
DATA[7:0]
DATA[15:0]
DATA[31:0]
N/A
DIA
4
N/A
DIPA
ADDRA
9
Parity[0]
Parity[1:0]
Parity[3:0]
WEA
ENA
18
36
ADDR[8:0]
SSRA
CLKA
DOA
DOPA
Read/Write Operations
DIB
The Virtex-II block SelectRAM read operation is fully syn-
chronous. An address is presented, and the read operation
is enabled by control signals WEA and WEB in addition to
ENA or ENB. Then, depending on clock polarity, a rising or
falling clock edge causes the stored data to be loaded into
output registers.
DIPB
ADDRB
WEB
ENB
SSRB
CLKB
DOB
DOPB
The write operation is also fully synchronous. Data and
address are presented, and the write operation is enabled
by control signals WEA or WEB in addition to ENA or ENB.
Then, again depending on the clock input mode, a rising or
falling clock edge causes the data to be loaded into the
memory cell addressed.
DS031_11_071602
Figure 30: 18 Kbit Block SelectRAM in Dual-Port Mode
Port Aspect Ratios
Table 16 shows the depth and the width aspect ratios for the
18 Kbit block SelectRAM. Virtex-II block SelectRAM also
includes dedicated routing resources to provide an efficient
interface with CLBs, block SelectRAM, and multipliers.
A write operation performs a simultaneous read operation.
Three different options are available, selected by configura-
tion:
1. “WRITE_FIRST”
The “WRITE_FIRST” option is a transparent mode. The
same clock edge that writes the data input (DI) into the
memory also transfers DI into the output registers DO
as shown in Figure 31.
Internal
Memory
DO
Data_in
DI
Data_out = Data_in
CLK
WE
Data_in
Address
New
aa
RAM Contents
Data_out
Old
New
New
DS031_14_102000
Figure 31: WRITE_FIRST Mode
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2. “READ_FIRST”
The “READ_FIRST” option is a read-before-write mode.
The same clock edge that writes data input (DI) into the memory also transfers the prior content of the memory cell
addressed into the data output registers DO, as shown in Figure 32.
Internal
Memory
DO
Data_in
Prior stored data
DI
CLK
WE
Data_in
New
Address
aa
RAM Contents
Data_out
Old
New
Old
DS031_13_102000
Figure 32: READ_FIRST Mode
3. “NO_CHANGE”
The “NO_CHANGE” option maintains the content of the output registers, regardless of the write operation. The clock edge
during the write mode has no effect on the content of the data output register DO. When the port is configured as
“NO_CHANGE”, only a read operation loads a new value in the output register DO, as shown in Figure 33.
Internal
Memory
DO
Data_in
No change during write
DI
CLK
WE
Data_in
Address
New
aa
RAM Contents
Data_out
Old
New
Last Read Cycle Content (no change)
DS031_12_102000
Figure 33: NO_CHANGE Mode
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Virtex-II 1.5V Field-Programmable Gate Arrays
number of CLBs in a column divided by four. Column loca-
tions are shown in Table 18.
Control Pins and Attributes
Virtex-II SelectRAM memory has two independent ports
with the control signals described in Table 17. All control
inputs including the clock have an optional inversion.
Table 18: SelectRAM Memory Floor Plan
SelectRAM Blocks
Table 17: Control Functions
Device
Columns
Per Column
Total
4
Control Signal
Function
XC2V40
2
2
4
4
4
4
4
6
6
6
6
2
CLK
EN
Read and Write Clock
XC2V80
4
8
Enable affects Read, Write, Set, Reset
Write Enable
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
6
24
WE
SSR
8
32
Set DO register to SRVAL (attribute)
10
12
14
16
20
24
28
40
Initial memory content is determined by the INIT_xx
attributes. Separate attributes determine the output register
value after device configuration (INIT) and SSR is asserted
(SRVAL). Both attributes (INIT_B and SRVAL) are available
for each port when a block SelectRAM resource is config-
ured as dual-port RAM.
48
56
96
120
144
168
Locations
Virtex-II SelectRAM memory blocks are located in either
four or six columns. The number of blocks per column
depends of the device array size and is equivalent to the
SelectRAM Blocks
SelectRAM Blocks
SelectRAM Blocks
ds031_38_101000
Figure 34: Block SelectRAM (2-column, 4-column, and 6-column)
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Virtex-II 1.5V Field-Programmable Gate Arrays
Total Amount of SelectRAM Memory
Table 19 shows the amount of block SelectRAM memory
available for each Virtex-II device. The 18 Kbit SelectRAM
blocks are cascadable to implement deeper or wider single- or
dual-port memory resources.
Switch
Matrix
Table 19: Virtex-II SelectRAM Memory Available
Switch
Matrix
Total SelectRAM Memory
18-Kbit block
SelectRAM
Device
Blocks
4
in Kbits
72
in Bits
73,728
Switch
Matrix
XC2V40
XC2V80
8
144
147,456
442,368
589,824
737,280
884,736
1,032,192
1,769,472
2,211,840
2,654,208
3,096,576
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
24
432
Switch
Matrix
32
576
40
720
DS031_33_101000
48
864
Figure 35: SelectRAM and Multiplier Blocks
56
1,008
1,728
2,160
2,592
3,024
Association With Block SelectRAM Memory
96
The interconnect is designed to allow SelectRAM memory
and multiplier blocks to be used at the same time, but some
interconnect is shared between the SelectRAM and the
multiplier. Thus, SelectRAM memory can be used only up to
18 bits wide when the multiplier is used, because the multi-
plier shares inputs with the upper data bits of the
SelectRAM memory.
120
144
168
18-Bit x 18-Bit Multipliers
This sharing of the interconnect is optimized for an
18-bit-wide block SelectRAM resource feeding the multi-
plier. The use of SelectRAM memory and the multiplier with
an accumulator in LUTs allows for implementation of a digi-
tal signal processor (DSP) multiplier-accumulator (MAC)
function, which is commonly used in finite and infinite
impulse response (FIR and IIR) digital filters.
Introduction
A Virtex-II multiplier block is an 18-bit by 18-bit 2’s comple-
ment signed multiplier. Virtex-II devices incorporate many
embedded multiplier blocks. These multipliers can be asso-
ciated with an 18 Kbit block SelectRAM resource or can be
used independently. They are optimized for high-speed
operations and have a lower power consumption compared
to an 18-bit x 18-bit multiplier in slices.
Configuration
The multiplier block is an 18-bit by 18-bit signed multiplier
(2's complement). Both A and B are 18-bit-wide inputs, and
the output is 36 bits. Figure 36 shows a multiplier block.
Each SelectRAM memory and multiplier block is tied to four
switch matrices, as shown in Figure 35.
Multiplier Block
A[17:0]
MULT 18 x 18
P[35:0]
B[17:0]
DS031_40_100400
Figure 36: Multiplier Block
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Locations / Organization
Table 20: Multiplier Floor Plan
Multiplier organization is identical to the 18 Kbit SelectRAM
organization, because each multiplier is associated with an
18 Kbit block SelectRAM resource.
Multipliers
Per Column
Device
Columns
Total
4
XC2V40
2
2
4
4
4
4
4
6
6
6
6
2
In addition to the built-in multiplier blocks, the CLB elements
have dedicated logic to implement efficient multipliers in
logic. (Refer to Configurable Logic Blocks (CLBs)).
XC2V80
4
8
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
6
24
8
32
10
12
14
16
20
24
28
40
48
56
96
120
144
168
Multiplier Blocks
Multiplier Blocks
Multiplier Blocks
DS031_39_101000
Figure 37: Multipliers (2-column, 4-column, and 6-column)
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Virtex-II 1.5V Field-Programmable Gate Arrays
Global Clock Multiplexer Buffers
Virtex-II devices have 16 clock input pins that can also be
used as regular user I/Os. Eight clock pads are on the top
edge of the device, in the middle of the array, and eight are
on the bottom edge, as illustrated in Figure 38.
can also be driven by local interconnects. The DCM has
clock output(s) that can be connected to global clock buffer
inputs, as shown in Figure 39.
Global clock buffers are used to distribute the clock to some
or all synchronous logic elements (such as registers in
CLBs and IOBs, and SelectRAM blocks.
The global clock multiplexer buffer represents the input to
dedicated low-skew clock tree distribution in Virtex-II
devices. Like the clock pads, eight global clock multiplexer
buffers are on the top edge of the device and eight are on
the bottom edge.
Eight global clocks can be used in each quadrant of the
Virtex-II device. Designers should consider the clock distri-
bution detail of the device prior to pin-locking and floorplan-
ning (see the Virtex-II User Guide).
Clock
Pad
Clock
Pad
8 clock pads
I
CLKIN
Clock
Buffer
Virtex-II
DCM
Device
CLKOUT
I
0
8 clock pads
Clock Distribution
Clock
Buffer
DS031_42_101000
0
Figure 38: Virtex-II Clock Pads
Clock Distribution
DS031_43_101000
Each global clock buffer can either be driven by the clock
pad to distribute a clock directly to the device, or driven by
the Digital Clock Manager (DCM), discussed in Digital
Clock Manager (DCM), page 31. Each global clock buffer
Figure 39: Virtex-II Clock Distribution Configurations
Figure 40 shows clock distribution in Virtex-II devices.
8 BUFGMUX
NE
NW
8
8
8 BUFGMUX
8
NW
SW
NE
SE
8 max
16 Clocks
16 Clocks
8
SE
8 BUFGMUX
SW
8 BUFGMUX
DS031_45_120200
Figure 40: Virtex-II Clock Distribution
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In each quadrant, up to eight clocks are organized in clock
rows. A clock row supports up to 16 CLB rows (eight up and
eight down). For the largest devices a new clock row is
added, as necessary.
BUFGMUX
BUFGMUX can switch between two unrelated, even asyn-
chronous clocks. Basically, a Low on S selects the I0 input,
a High on S selects the I1 input. Switching from one clock to
the other is done in such a way that the output High and Low
time is never shorter than the shortest High or Low time of
either input clock. As long as the presently selected clock is
High, any level change of S has no effect .
To reduce power consumption, any unused clock branches
remain static.
Global clocks are driven by dedicated clock buffers (BUFG),
which can also be used to gate the clock (BUFGCE) or to mul-
tiplex between two independent clock inputs (BUFGMUX).
BUFGMUX
The most common configuration option of this element is as
a buffer. A BUFG function in this (global buffer) mode, is
shown in Figure 41.
I0
O
I1
BUFG
I
O
S
DS031_63_112900
DS031_61_101200
Figure 43: Virtex-II BUFGMUX Function
Figure 41: Virtex-II BUFG Function
If the presently selected clock is Low while S changes, or if
it goes Low after S has changed, the output is kept Low until
the other ("to-be-selected") clock has made a transition
from High to Low. At that instant, the new clock starts driv-
ing the output.
The Virtex-II global clock buffer BUFG can also be config-
ured as a clock enable/disable circuit (Figure 42), as well as
a two-input clock multiplexer (Figure 43). A functional
description of these two options is provided below. Each of
them can be used in either of two modes, selected by con-
figuration: rising clock edge or falling clock edge.
The two clock inputs can be asynchronous with regard to
each other, and the S input can change at any time, except
for a short setup time prior to the rising edge of the presently
selected clock; that is, prior to the rising edge of the
BUFGMUX output O. Violating this setup time requirement
can result in an undefined runt pulse output.
This section describes the rising clock edge option. For the
opposite option, falling clock edge, just change all "rising"
references to "falling" and all "High" references to "Low",
except for the description of the CE or S levels. The rising
clock edge option uses the BUFGCE and BUFGMUX prim-
itives. The falling clock edge option uses the BUFGCE_1
and BUFGMUX_1 primitives.
All Virtex-II devices have 16 global clock multiplexer buffers.
Figure 44 shows a switchover from CLK0 to CLK1.
BUFGCE
Wait for Low
If the CE input is active (High) prior to the incoming rising
clock edge, this Low-to-High-to-Low clock pulse passes
through the clock buffer. Any level change of CE during the
incoming clock High time has no effect.
S
CLK0
Switch
CLK1
BUFGCE
OUT
I
O
CE
DS031_62_101200
DS031_46_112900
Figure 42: Virtex-II BUFGCE Function
Figure 44: Clock Multiplexer Waveform Diagram
If the CE input is inactive (Low) prior to the incoming rising
clock edge, the following clock pulse does not pass through
the clock buffer, and the output stays Low. Any level change
of CE during the incoming clock High time has no effect. CE
must not change during a short setup window just prior to
the rising clock edge on the BUFGCE input I. Violating this
setup time requirement can result in an undefined runt
pulse output.
•
•
•
The current clock is CLK0.
S is activated High.
If CLK0 is currently High, the multiplexer waits for CLK0
to go Low.
•
•
•
Once CLK0 is Low, the multiplexer output stays Low
until CLK1 transitions High to Low.
When CLK1 transitions from High to Low, the output
switches to CLK1.
No glitches or short pulses can appear on the output.
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Virtex-II 1.5V Field-Programmable Gate Arrays
Digital Clock Manager (DCM)
The Virtex-II DCM offers a wide range of powerful clock
management features.
Table 21: DCM Status Pins
Status Pin
Function
•
Clock De-skew: The DCM generates new system
clocks (either internally or externally to the FPGA),
which are phase-aligned to the input clock, thus
eliminating clock distribution delays.
0
1
2
3
4
5
6
7
Phase Shift Overflow
CLKIN Stopped
CLKFX Stopped
•
•
Frequency Synthesis: The DCM generates a wide
range of output clock frequencies, performing very
flexible clock multiplication and division.
N/A
N/A
N/A
N/A
N/A
Phase Shifting: The DCM provides both coarse phase
shifting and fine-grained phase shifting with dynamic
phase shift control.
The DCM utilizes fully digital delay lines allowing robust
high-precision control of clock phase and frequency. It also
utilizes fully digital feedback systems, operating dynamically
to compensate for temperature and voltage variations dur-
ing operation.
Clock De-Skew
The DCM de-skews the output clocks relative to the input
clock by automatically adjusting a digital delay line. Addi-
tional delay is introduced so that clock edges arrive at inter-
nal registers and block RAMs simultaneously with the clock
edges arriving at the input clock pad. Alternatively, external
clocks, which are also de-skewed relative to the input clock,
can be generated for board-level routing. All DCM output
clocks are phase-aligned to CLK0 and, therefore, are also
phase-aligned to the input clock.
Up to four of the nine DCM clock outputs can drive inputs to
global clock buffers or global clock multiplexer buffers simul-
taneously (see Figure 45). All DCM clock outputs can simul-
taneously drive general routing resources, including routes
to output buffers.
DCM
To achieve clock de-skew, the CLKFB input must be con-
nected, and its source must be either CLK0 or CLK2X. Note
that CLKFB must always be connected, unless only the
CLKFX or CLKFX180 outputs are used and de-skew is not
required.
CLK0
CLKIN
CLK90
CLKFB
CLK180
CLK270
RST
CLK2X
Frequency Synthesis
CLK2X180
DSSEN
The DCM provides flexible methods for generating new
clock frequencies. Each method has a different operating
frequency range and different AC characteristics. The
CLK2X and CLK2X180 outputs double the clock frequency.
The CLKDV output creates divided output clocks with divi-
sion options of 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5,
8, 9, 10, 11, 12, 13, 14, 15, and 16.
CLKDV
PSINCDEC
PSEN
PSCLK
CLKFX
CLKFX180
LOCKED
STATUS[7:0]
PSDONE
clock signal
The CLKFX and CLKFX180 outputs can be used to pro-
duce clocks at the following frequency:
control signal
DS031_67_112900
Figure 45: Digital Clock Manager
FREQ
= (M/D) * FREQ
CLKIN
CLKFX
where M and D are two integers. Specifications for M and D
are provided under DCM Timing Parameters. By default,
M=4 and D=1, which results in a clock output frequency four
times faster than the clock input frequency (CLKIN).
The DCM can be configured to delay the completion of the
Virtex-II configuration process until after the DCM has
achieved lock. This guarantees that the chip does not begin
operating until after the system clocks generated by the
DCM have stabilized.
CLK2X180 is phase shifted 180 degrees relative to CLK2X.
CLKFX180 is phase shifted 180 degrees relative to CLKFX.
All frequency synthesis outputs automatically have 50/50
duty cycles (with the exception of the CLKDV output when
performing a non-integer divide in high-frequency mode).
The DCM has the following general control signals:
•
•
RST input pin: resets the entire DCM
LOCKED output pin: asserted High when all enabled
DCM circuits have locked.
Note that CLK2X and CLK2X180 are not available in
high-frequency mode.
•
STATUS output pins (active High): shown in Table 21.
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Phase Shifting
The DCM provides additional control over clock skew
through either coarse or fine-grained phase shifting. The
CLK0, CLK90, CLK180, and CLK270 outputs are each
phase shifted by ¼ of the input clock period relative to each
other, providing coarse phase control. Note that CLK90 and
CLK270 are not available in high-frequency mode.
shifting. For more information on DCM features, see the
Virtex-II User Guide.
Table 22 lists fine-phase shifting control pins, when used in
variable mode.
Table 22: Fine-Phase Shifting Control Pins
Fine-phase adjustment affects all nine DCM output clocks.
When activated, the phase shift between the rising edges of
CLKIN and CLKFB is a specified fraction of the input clock
period.
Control Pin
PSINCDEC
PSEN
Direction
Function
in
in
Increment or decrement
Enable ± phase shift
Clock for phase shift
Active when completed
In variable mode, the PHASE_SHIFT value can also be
dynamically incremented or decremented as determined by
PSINCDEC synchronously to PSCLK, when the PSEN
input is active. Figure 46 illustrates the effects of fine-phase
PSCLK
in
PSDONE
out
CLKIN
CLKOUT_PHASE_SHIFT
= NONE
CLKFB
CLKIN
CLKFB
CLKOUT_PHASE_SHIFT
= FIXED
(PS/256) x PERIOD
(PS negative)
(PS/256) x PERIOD
(PS positive)
CLKIN
CLKIN
CLKIN
CLKFB
CLKOUT_PHASE_SHIFT
= VARIABLE
(PS/256) x PERIOD
(PS negative)
(PS/256) x PERIOD
CLKIN
CLKIN
(PS positive)
DS031_48_101201
Figure 46: Fine-Phase Shifting Effects
Two separate components of the phase shift range must be
understood:
The reason for the difference between fixed and variable
modes is as follows. For variable mode to allow symmetric,
dynamic sweeps from -255/256 to +255/256, the DCM sets
the "zero phase skew" point as the middle of the delay line,
thus dividing the total delay line range in half. In fixed mode,
since the PHASE_SHIFT value never changes after configu-
ration, the entire delay line is available for insertion into
either the CLKIN or CLKFB path (to create either positive or
negative skew).
•
•
PHASE_SHIFT attribute range
FINE_SHIFT_RANGE DCM timing parameter range
The PHASE_SHIFT attribute is the numerator in the following
equation:
Phase Shift (ns) = (PHASE_SHIFT/256) * PERIOD
CLKIN
The full range of this attribute is always -255 to +255, but its
practical range varies with CLKIN frequency, as constrained
by the FINE_SHIFT_RANGE component, which represents
the total delay achievable by the phase shift delay line. Total
delay is a function of the number of delay taps used in the
circuit. Across process, voltage, and temperature, this abso-
lute range is guaranteed to be as specified under DCM Tim-
ing Parameters.
Taking both of these components into consideration, the fol-
lowing are some usage examples:
•
•
•
If PERIOD
= 2 * FINE_SHIFT_RANGE, then
CLKIN
PHASE_SHIFT in fixed mode is limited to ± 128, and in
variable mode it is limited to ± 64.
If PERIOD
= FINE_SHIFT_RANGE, then
CLKIN
PHASE_SHIFT in fixed mode is limited to ± 255, and in
variable mode it is limited to ± 128.
Absolute range (fixed mode) = ± FINE_SHIFT_RANGE
Absolute range (variable mode) = ± FINE_SHIFT_RANGE/2
If PERIOD
≤ 0.5 * FINE_SHIFT_RANGE, then
CLKIN
PHASE_SHIFT is limited to ± 255 in either mode.
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Virtex-II 1.5V Field-Programmable Gate Arrays
Operating Modes
The frequency ranges of DCM input and output clocks
depend on the operating mode specified, either
low-frequency mode or high-frequency mode, according to
Table 23. (For actual values, see Virtex-II Switching Char-
acteristics). The CLK2X, CLK2X180, CLK90, and CLK270
outputs are not available in high-frequency mode.
High or low-frequency mode is selected by an attribute.
Table 23: DCM Frequency Ranges
Low-Frequency Mode
High-Frequency Mode
Output Clock
CLK0, CLK180
CLKIN Input
CLK Output
CLKIN Input
CLK Output
CLKIN_FREQ_DLL_LF CLKOUT_FREQ_1X_LF CLKIN_FREQ_DLL_HF CLKOUT_FREQ_1X_HF
CLK90, CLK270
CLK2X, CLK2X180
CLKDV
CLKIN_FREQ_DLL_LF CLKOUT_FREQ_1X_LF
CLKIN_FREQ_DLL_LF CLKOUT_FREQ_2X_LF
NA
NA
NA
NA
CLKIN_FREQ_DLL_LF CLKOUT_FREQ_DV_LF CLKIN_FREQ_DLL_HF CLKOUT_FREQ_DV_HF
CLKFX, CLKFX180
CLKIN_FREQ_FX_LF
CLKOUT_FREQ_FX_LF CLKIN_FREQ_FX_HF
CLKOUT_FREQ_FX_HF
Locations/Organization
Virtex-II DCMs are placed on the top and bottom of each
block RAM and multiplier column. The number of DCMs
depends on the device size, as shown in Table 24.
Table 24: DCM Organization
Device
XC2V40
Columns
DCMs
2
2
4
4
4
4
4
6
6
6
6
4
4
XC2V80
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
8
8
8
8
8
12
12
12
12
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Virtex-II 1.5V Field-Programmable Gate Arrays
Active Interconnect Technology
Local and global Virtex-II routing resources are optimized for speed and timing predictability, as well as to facilitate IP cores
implementation. Virtex-II Active Interconnect Technology is a fully buffered programmable routing matrix. All routing
resources are segmented to offer the advantages of a hierarchical solution. Virtex-II logic features like CLBs, IOBs, block
RAM, multipliers, and DCMs are all connected to an identical switch matrix for access to global routing resources, as shown
in Figure 47.
Switch
Matrix
Switch
CLB
Matrix
Switch
Matrix
Switch
Matrix
18Kb
MULT
IOB
BRAM
18 x 18
Switch
Matrix
Switch
Matrix
DCM
Switch
Matrix
DS031_55_101000
Figure 47: Active Interconnect Technology
Each Virtex-II device can be represented as an array of switch matrixes with logic blocks attached, as illustrated in
Figure 48.
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
IOB
IOB
IOB
IOB
IOB
IOB
CLB
CLB
CLB
CLB
IOB
CLB
CLB
CLB
CLB
DCM
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
DS031_34_110300
Figure 48: Routing Resources
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Place-and-route software takes advantage of this regular
array to deliver optimum system performance and fast com-
pile times. The segmented routing resources are essential
to guarantee IP cores portability and to efficiently handle an
incremental design flow that is based on modular imple-
mentations. Total design time is reduced due to fewer and
shorter design iterations.
Hierarchical Routing Resources
Most Virtex-II signals are routed using the global routing
resources, which are located in horizontal and vertical rout-
ing channels between each switch matrix.
As shown in Figure 49, Virtex-II has fully buffered program-
mable interconnections, with a number of resources
counted between any two adjacent switch matrix rows or
columns. Fanout has minimal impact on the performance of
each net.
24 Horizontal Long Lines
24 Vertical Long Lines
120 Horizontal Hex Lines
120 Vertical Hex Lines
40 Horizontal Double Lines
40 Vertical Double Lines
16 Direct Connections
(total in all four directions)
8 Fast Connects
DS031_60_110200
Figure 49: Hierarchical Routing Resources
•
•
The long lines are bidirectional wires that distribute
signals across the device. Vertical and horizontal long
lines span the full height and width of the device.
•
The fast connect lines are the internal CLB local
interconnections from LUT outputs to LUT inputs.
Dedicated Routing
The hex lines route signals to every third or sixth block
away in all four directions. Organized in a staggered
pattern, hex lines can only be driven from one end.
Hex-line signals can be accessed either at the endpoints
or at the midpoint (three blocks from the source).
In addition to the global and local routing resources, dedi-
cated signals are available.
•
There are eight global clock nets per quadrant (see
Global Clock Multiplexer Buffers).
•
•
The double lines route signals to every first or second
block away in all four directions. Organized in a
staggered pattern, double lines can be driven only at
their endpoints. Double-line signals can be accessed
either at the endpoints or at the midpoint (one block
from the source).
•
Horizontal routing resources are provided for on-chip
3-state busses. Four partitionable bus lines are
provided per CLB row, permitting multiple busses
within a row. (See 3-State Buffers.)
•
Two dedicated carry-chain resources per slice column
(two per CLB column) propagate carry-chain MUXCY
output signals vertically to the adjacent slice. (See
CLB/Slice Configurations.)
The direct connect lines route signals to neighboring
blocks: vertically, horizontally, and diagonally.
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Virtex-II 1.5V Field-Programmable Gate Arrays
•
•
One dedicated SOP chain per slice row (two per CLB
row) propagate ORCY output logic signals horizontally
to the adjacent slice. (See Sum of Products.)
Design Entry
All Xilinx ISE development systems support the mainstream
EDA design entry capabilities, ranging from schematic
design to advanced HDL design methodologies. Given the
high densities of the Virtex-II family, designs are created
most efficiently using HDLs. To further improve their time to
market, many Xilinx customers employ incremental, modu-
lar, and Intellectual Property (IP) design techniques. When
properly used, these techniques further accelerate the logic
design process.
One dedicated shift-chain per CLB connects the output
of LUTs in shift-register mode to the input of the next
LUT in shift-register mode (vertically) inside the CLB.
(See Shift Registers, page 17.)
Creating a Design
Creating Virtex-II designs is easy with Xilinx Integrated Syn-
thesis Environment (ISE) development systems, which sup-
port advanced design capabilities, including ProActive
Timing Closure, integrated logic analysis, and the fastest
place and route runtimes in the industry. ISE solutions
enable designers to get the performance they need, quickly
and easily.
To enable designers to leverage existing investments in
EDA tools, and to ensure high performance design flows,
Xilinx jointly develops tools with leading EDA vendors,
including:
®
•
•
•
•
•
•
•
Aldec
®
Cadence
As a result of the ongoing cooperative development efforts
between Xilinx and EDA Alliance partners, designers can
take advantage of the benefits provided by EDA technolo-
gies in the programmable logic design process. Xilinx devel-
opment systems are available in a number of easy to use
configurations, collectively known as the ISE Series.
®
Exemplar
Mentor Graphics
®
®
Model Technology
®
Synopsys
®
Synplicity
ISE Alliance
Complete information on Alliance Series partners and their
associated design flows is available at www.xilinx.com on
the Xilinx Alliance Series web page.
The ISE Alliance solution is designed to plug and play within
an existing design environment. Built using industry standard
data formats and netlists, these stable, flexible products
enable Alliance EDA partners to deliver their best design
automation capabilities to Xilinx customers, along with the
time to market benefits of ProActive Timing Closure.
The ISE Foundation product offers schematic entry and
HDL design capabilities as part of an integrated design
solution - enabling one-stop shopping. These capabilities
are powerful, easy to use, and they support the full portfolio
of Xilinx programmable logic devices. HDL design capabil-
ities include a color-coded HDL editor with integrated lan-
guage templates, state diagram entry, and Core generation
capabilities.
ISE Foundation
The ISE Foundation solution delivers the benefits of true
HDL-based design in a seamlessly integrated design envi-
ronment. An intuitive project navigator, as well as powerful
HDL design and two HDL synthesis tools, ensure that
high-quality results are achieved quickly and easily. The ISE
Foundation product includes:
Synthesis
The ISE Alliance product is engineered to support
advanced design flows with the industry’s best synthesis
tools. Advanced design methodologies include:
•
•
State Diagram entry using Xilinx StateCAD
•
•
•
•
Physical Synthesis
Incremental synthesis
RTL floorplanning
Automatic HDL Testbench generation using Xilinx
HDLBencher
•
HDL Simulation using ModelSim XE
Direct physical mapping
Design Flow
The ISE Foundation product seamlessly integrates synthesis
capabilities purchased directly from Exemplar, Synopsys, and
Synplicity. In addition, it includes the capabilities of Xilinx
Synthesis Technology.
Virtex-II design flow proceeds as follows:
•
•
•
•
Design Entry
Synthesis
A benefit of having two seamlessly integrated synthesis
engines within an ISE design flow is the ability to apply alter-
native sets of optimization techniques on designs, helping to
ensure that designers can meet even the toughest timing
requirements.
Implementation
Verification
Most programmable logic designers iterate through these
steps several times in the process of completing a design.
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Virtex-II 1.5V Field-Programmable Gate Arrays
capability only available in the Xilinx design flow is “Modular
Design”, part of the Xilinx suite of team design tools, which
enables autonomous design, implementation, and verifica-
tion of design modules.
Design Implementation
The ISE Series development systems include Xilinx tim-
ing-driven implementation tools, frequently called “place
and route” or “fitting” software. This robust suite of tools
enables the creation of an intuitive, flexible, tightly inte-
grated design flow that efficiently bridges “logical” and
“physical” design domains. This simplifies the task of defin-
ing a design, including its behavior, timing requirements,
and optional layout (or floorplanning), as well as simplifying
the task of analyzing reports generated during the imple-
mentation process.
Incremental Synthesis
Xilinx unique hierarchical floorplanning capabilities enable
designers to create a programmable logic design by isolating
design changes within one hierarchical “logic block”, and
perform synthesis, verification and implementation pro-
cesses on that specific logic block. By preserving the logic in
unchanged portions of a design, Xilinx incremental design
makes the high-density design process more efficient.
The Virtex-II implementation process is comprised of Syn-
thesis, translation, mapping, place and route, and configu-
ration file generation. While the tools can be run individually,
many designers choose to run the entire implementation
process with the click of a button. To assist those who prefer
to script their design flows, Xilinx provides Xflow, an auto-
mated single command line process.
Xilinx hierarchical floorplanning capabilities can be speci-
fied using the high-level floorplanner or a preferred RTL
floorplanner (see the Xilinx web site for a list of supported
EDA partners). When used in conjunction with one of the
EDA partners’ floorplanners, higher performance results
can be achieved, as many synthesis tools use this more
predictable detailed physical implementation information to
establish more aggressive and accurate timing estimates
when performing their logic optimizations.
Design Verification
In addition to conventional design verification using static
timing analysis or simulation techniques, Xilinx offers pow-
erful in-circuit debugging techniques using ChipScope ILA
(Integrated Logic Analysis). The reconfigurable nature of
Xilinx FPGAs means that designs can be verified in real
time without the need for extensive sets of software simula-
tion vectors.
Modular Design
Xilinx innovative modular design capabilities take the incre-
mental design process one step further by enabling the
designer to delegate responsibility for completing the
design, synthesis, verification, and implementation of a hier-
archical “logic block” to an arbitrary number of designers -
assigning a specific region within the target FPGA for exclu-
sive use by each of the team members.
For simulation, the system extracts post-layout timing infor-
mation from the design database, and back-annotates this
information into the netlist for use by the simulator. The back
annotation features a variety of patented Xilinx techniques,
resulting in the industry’s most powerful simulation flows.
Alternatively, timing-critical portions of a design can be ver-
ified using the Xilinx static timing analyzer or a third party
static timing analysis tool like Synopsys Prime Time™, by
exporting timing data in the STAMP data format.
This team design capability enables an autonomous
approach to design modules, changing the hand-off point to
the lead designer or integrator from “my module works in
simulation” to “my module works in the FPGA”. This unique
design methodology also leverages the Xilinx hierarchical
floorplanning capabilities and enables the Xilinx (or EDA
partner) floorplanner to manage the efficient implementa-
tion of very high-density FPGAs.
For in-circuit debugging, ChipScope ILA enables designers
to analyze the real-time behavior of a device while operating
at full system speeds. Logic analysis commands and cap-
tured data are transferred between the ChipScope software
and ILA cores within the Virtex-II FPGA, using industry
standard JTAG protocols. These JTAG transactions are
driven over an optional download cable (MultiLINX or
JTAG), connecting the Virtex device in the target system to
a PC or workstation.
Configuration
Virtex-II devices are configured by loading application spe-
cific configuration data into the internal configuration mem-
ory. Configuration is carried out using a subset of the device
pins, some of which are dedicated, while others can be
re-used as general purpose inputs and outputs once config-
uration is complete.
ChipScope ILA was designed to look and feel like a logic
analyzer, making it easy to begin debugging a design imme-
diately. Modifications to the desired logic analysis can be
downloaded directly into the system in a matter of minutes.
Depending on the system design, several configuration
modes are supported, selectable via mode pins. The mode
pins M2, M1 and M0 are dedicated pins. An additional pin,
HSWAP_EN is used in conjunction with the mode pins to
select whether user I/O pins have pull-ups during configura-
tion. By default, HSWAP_EN is tied High (internal pull-up)
which shuts off the pull-ups on the user I/O pins during con-
figuration. When HSWAP_EN is tied Low, user I/Os have
Other Unique Features of Virtex-II Design Flow
Xilinx design flows feature a number of unique capabilities.
Among these are efficient incremental HDL design flows; a
robust capability that is enabled by Xilinx exclusive hierar-
chical floorplanning capabilities. Another powerful design
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pull-ups during configuration. Other dedicated pins are
CCLK (the configuration clock pin), DONE, PROG_B, and
the boundary-scan pins: TDI, TDO, TMS, and TCK.
Depending on the configuration mode chosen, CCLK can
be an output generated by the FPGA, or an input accepting
an externally generated clock. The configuration pins and
loaded, the data for the next device in a daisy-chain is pre-
sented on the DOUT pin after the rising CCLK edge.
The interface is identical to slave serial except that an inter-
nal oscillator is used to generate the configuration clock
(CCLK). A wide range of frequencies can be selected for
CCLK which always starts at a slow default frequency. Con-
figuration bits then switch CCLK to a higher frequency for
the remainder of the configuration.
boundary scan pins are independent of the V
. The aux-
CCO
iliary power supply (V
) of 3.3V is used for these pins.
CCAUX
All configuration pins are LVTTL 12 mA. (See Virtex-II DC
Characteristics.)
Slave SelectMAP Mode
The SelectMAP mode is the fastest configuration option.
Byte-wide data is written into the Virtex-II FPGA device with
a BUSY flag controlling the flow of data. An external data
source provides a byte stream, CCLK, an active Low Chip
Select (CS_B) signal and a Write signal (RDWR_B). If
BUSY is asserted (High) by the FPGA, the data must be
held until BUSY goes Low. Data can also be read using the
SelectMAP mode. If RDWR_B is asserted, configuration
data is read out of the FPGA as part of a readback opera-
tion.
A persist option is available which can be used to force the
configuration pins to retain their configuration function even
after device configuration is complete. If the persist option is
not selected then the configuration pins with the exception
of CCLK, PROG_B, and DONE can be used as user I/O in
normal operation. The persist option does not apply to the
boundary-scan related pins. The persist feature is valuable
in applications which employ partial reconfiguration or
reconfiguration on the fly.
Configuration Modes
After configuration, the pins of the SelectMAP port can be
used as additional user I/O. Alternatively, the port can be
retained to permit high-speed 8-bit readback using the per-
sist option.
Virtex-II supports the following five configuration modes:
•
•
•
•
•
Slave-serial mode
Master-serial mode
Multiple Virtex-II FPGAs can be configured using the
SelectMAP mode, and be made to start-up simultaneously.
To configure multiple devices in this way, wire the individual
CCLK, Data, RDWR_B, and BUSY pins of all the devices in
parallel. The individual devices are loaded separately by
deasserting the CS_B pin of each device in turn and writing
the appropriate data.
Slave SelectMAP mode
Master SelectMAP mode
Boundary-Scan mode (IEEE 1532/IEEE 1149)
A detailed description of configuration modes is provided in
the Virtex-II User Guide.
Slave-Serial Mode
Master SelectMAP Mode
In slave-serial mode, the FPGA receives configuration data
in bit-serial form from a serial PROM or other serial source
of configuration data. The CCLK pin on the FPGA is an
input in this mode. The serial bitstream must be setup at the
DIN input pin a short time before each rising edge of the
externally generated CCLK.
This mode is a master version of the SelectMAP mode. The
device is configured byte-wide on a CCLK supplied by the
Virtex-II FPGA device. Timing is similar to the Slave Serial-
MAP mode except that CCLK is supplied by the Virtex-II
FPGA.
Boundary-Scan (JTAG, IEEE 1532) Mode
Multiple FPGAs can be daisy-chained for configuration from
a single source. After a particular FPGA has been config-
ured, the data for the next device is routed internally to the
DOUT pin. The data on the DOUT pin changes on the rising
edge of CCLK.
In boundary-scan mode, dedicated pins are used for config-
uring the Virtex-II device. The configuration is done entirely
through the IEEE 1149.1 Test Access Port (TAP). Virtex-II
device configuration using Boundary scan is compliant with
IEEE 1149.1-1993 standard and the new IEEE 1532 stan-
dard for In-System Configurable (ISC) devices. The IEEE
1532 standard is backward compliant with the IEEE
1149.1-1993 TAP and state machine. The IEEE Standard
1532 for In-System Configurable (ISC) devices is intended
to be programmed, reprogrammed, or tested on the board
via a physical and logical protocol.
Slave-serial mode is selected by applying <111> to the
mode pins (M2, M1, M0). A weak pull-up on the mode pins
makes slave serial the default mode if the pins are left
unconnected.
Master-Serial Mode
In master-serial mode, the CCLK pin is an output pin. It is
the Virtex-II FPGA device that drives the configuration clock
on the CCLK pin to a Xilinx Serial PROM which in turn feeds
bit-serial data to the DIN input. The FPGA accepts this data
on each rising CCLK edge. After the FPGA has been
Configuration through the boundary-scan port is always
available, independent of the mode selection. Selecting the
boundary-scan mode simply turns off the other modes.
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Virtex-II 1.5V Field-Programmable Gate Arrays
Table 25: Virtex-II Configuration Mode Pin Settings
(1)
(2)
Configuration Mode
Master Serial
M2
0
M1
0
M0
0
CCLK Direction
Data Width
Serial D
OUT
Out
In
1
1
8
8
1
Yes
Yes
No
No
No
Slave Serial
1
1
1
Master SelectMAP
Slave SelectMAP
Boundary Scan
Notes:
0
1
1
Out
In
1
1
0
1
0
1
N/A
1. The HSWAP_EN pin controls the pullups. Setting M2, M1, and M0 selects the configuration mode, while the HSWAP_EN pin
controls whether or not the pullups are used.
2. Daisy chaining is possible only in modes where Serial D
support daisy chaining of downstream devices.
is used. For example, in SelectMAP modes, the first device does NOT
OUT
Table 26 lists the total number of bits required to configure
each device.
being cleared. Extending the time that the pin is Low causes
the configuration sequencer to wait. Thus, configuration is
delayed by preventing entry into the phase where data is
loaded.
Table 26: Virtex-II Bitstream Lengths
Device
# of Configuration Bits
360,096
The configuration process can also be initiated by asserting
the PROG_B pin. The end of the memory-clearing phase is
signaled by the INIT_B pin going High, and the completion
of the entire process is signaled by the DONE pin going
High. The Global Set/Reset (GSR) signal is pulsed after the
last frame of configuration data is written but before the
start-up sequence. The GSR signal resets all flip-flops on
the device.
XC2V40
XC2V80
635,296
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
1,697,184
2,761,888
4,082,592
The default start-up sequence is that one CCLK cycle after
DONE goes High, the global 3-state signal (GTS) is
released. This permits device outputs to turn on as neces-
sary. One CCLK cycle later, the Global Write Enable (GWE)
signal is released. This permits the internal storage ele-
ments to begin changing state in response to the logic and
the user clock.
5,659,296
7,492,000
10,494,368
15,659,936
21,849,504
29,063,072
The relative timing of these events can be changed via con-
figuration options in software. In addition, the GTS and
GWE events can be made dependent on the DONE pins of
multiple devices all going High, forcing the devices to start
synchronously. The sequence can also be paused at any
stage, until lock has been achieved on any or all DCMs, as
well as the DCI.
Configuration Sequence
The configuration of Virtex-II devices is a three-phase pro-
cess after Power On Reset or POR. POR occurs when
V
and V
is greater than 1.2V, V
is greater than 2.5V,
CCINT
CCAUX
Readback
(bank 4) is greater than 1.5V. Once the POR volt-
CCO
In this mode, configuration data from the Virtex-II FPGA
device can be read back. Readback is supported only in the
SelectMAP (master and slave) and Boundary Scan mode.
ages have been reached, the three-phase process begins.
First, the configuration memory is cleared. Next, con-
figuration data is loaded into the memory, and finally, the
logic is activated by a start-up process.
Along with the configuration data, it is possible to read back
the contents of all registers, distributed SelectRAM, and
block RAM resources. This capability is used for real-time
debugging. For more detailed configuration information, see
the Virtex-II User Guide.
Configuration is automatically initiated on power-up unless
it is delayed by the user. The INIT_B pin can be held Low
using an open-drain driver. An open-drain is required since
INIT_B is a bidirectional open-drain pin that is held Low by a
Virtex-II FPGA device while the configuration memory is
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Virtex-II 1.5V Field-Programmable Gate Arrays
Bitstream Encryption
Partial Reconfiguration
Virtex-II devices have an on-chip decryptor using one or two
sets of three keys for triple-key Data Encryption Standard
(DES) operation. Xilinx software tools offer an optional
encryption of the configuration data (bitstream) with a tri-
ple-key DES determined by the designer.
Partial reconfiguration of Virtex-II devices can be accom-
plished in either Slave SelectMAP mode or Boundary-Scan
mode. Instead of resetting the chip and doing a full configu-
ration, new data is loaded into a specified area of the chip,
while the rest of the chip remains in operation. Data is
loaded on a column basis, with the smallest load unit being
a configuration “frame” of the bitstream (device size depen-
dent).
The keys are stored in the FPGA by JTAG instruction and
retained by a battery connected to the V
pin, when the
BATT
device is not powered. Virtex-II devices can be configured
with the corresponding encrypted bitstream, using any of
the configuration modes described previously.
Partial reconfiguration is useful for applications that require
different designs to be loaded into the same area of a chip,
or that require the ability to change portions of a design
without having to reset or reconfigure the entire chip.
A detailed description of how to use bitstream encryption is
provided in the Virtex-II User Guide. Your local FAE can also
provide specific information on this feature.
Revision History
This section records the change history for this module of the data sheet.
Date
Version
1.0
Revision
11/07/00
12/06/00
01/15/01
Early access draft.
Initial release.
1.1
1.2
Added values to the tables in the Virtex-II Performance Characteristics and Virtex-II
Switching Characteristics sections.
01/25/01
04/02/01
1.3
1.5
The data sheet was divided into four modules (per the current style standard). A note was
added to Table 1.
•
Under Input/Output Individual Options, the range of values for optional pull-up and
pull-down resistors was changed to 10 - 60 KΩ from 50 - 100 KΩ.
•
•
•
Skipped v1.4 to sync up modules. Reverted to traditional double-column format.
Added Table 6.
07/30/01
1.6
Changed definition of multiply and divide integer ranges under Digital Clock Manager
(DCM).
•
•
Made numerous minor edits throughout this module.
Updated descriptions under Digitally Controlled Impedance (DCI), Global Clock
Multiplexer Buffers, Digital Clock Manager (DCM), and Creating a Design.
10/02/01
1.7
•
•
•
Made clarifying edits under Digital Clock Manager (DCM).
Changed bitstream lengths for each device in Table 26.
Updated compatible input standards listed in Table 6.
10/12/01
11/29/01
07/16/02
09/26/02
1.8
1.9
2.0
2.1
•
•
Changed number of resources available to the XC2V40 device in Table 13.
Clarified Power On Reset information under Configuration Sequence.
Virtex-II Data Sheet
The Virtex-II Data Sheet contains the following modules:
•
DS031-1, Virtex-II 1.5V FPGAs: Introduction and
Ordering Information (Module 1)
•
•
DS031-3, Virtex-II 1.5V FPGAs: DC and Switching
Characteristics (Module 3)
•
DS031-2, Virtex-II 1.5V FPGAs: Functional Description
(Module 2)
DS031-4, Virtex-II 1.5V FPGAs: Pinout Tables
(Module 4)
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Field-Programmable Gate Arrays
0
0
DS031-3 (v2.3) September 26, 2002
Advance Product Specification
Virtex™-II Electrical Characteristics
Virtex-II devices are provided in –4, –5, and –6 speed
grades, with –6 having the highest performance.
mercial device). However, only selected speed grades
and/or devices might be available in the industrial range.
Virtex-II DC and AC characteristics are specified for both
commercial and industrial grades. Except the operating tem-
perature range or unless otherwise noted, all the DC and AC
electrical parameters are the same for a particular speed
grade (that is, the timing characteristics of a –4 speed grade
industrial device are the same as for a –4 speed grade com-
All supply voltage and junction temperature specifications
are representative of worst-case conditions. The parame-
ters included are common to popular designs and typical
applications. Contact Xilinx for design considerations
requiring more detailed information.
All specifications are subject to change without notice.
Virtex-II DC Characteristics
Table 1: Absolute Maximum Ratings
Symbol
Description
Internal supply voltage relative to GND
Units
V
–0.5 to 1.65
–0.5 to 4.0
–0.5 to 4.0
–0.5 to 4.0
V
V
CCINT
V
Auxiliary supply voltage relative to GND
Output drivers supply voltage relative to GND
Key memory battery backup supply
Input reference voltage
CCAUX
V
V
CCO
V
V
BATT
V
–0.5 to V
+ 0.5
V
REF
CCO
CCO
V
Input voltage relative to GND (user and dedicated I/Os)
Voltage applied to 3-state output (user and dedicated I/Os)
Storage temperature (ambient)
–0.5 to V
+ 0.5
V
IN
V
–0.5 to 4.0
–65 to +150
+220
V
TS
T
°C
°C
°C
STG
SOL
T
Maximum soldering temp.
T
Operating junction temperature
+125
J
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
© 2001-2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS031-3 (v2.3) September 26, 2002
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Virtex-II 1.5V Field-Programmable Gate Arrays
Table 2: Recommended Operating Conditions
Symbol
Description
Min
1.425
1.425
3.135
3.135
1.2
Max
1.575
1.575
3.465
3.465
3.6
Units
Internal supply voltage relative to GND, T = 0 °C to +85°C
Commercial
Industrial
V
V
V
V
V
V
V
V
J
V
CCINT
Internal supply voltage relative to GND, T = –40°C to +100°C
J
Auxiliary supply voltage relative to GND, T = 0 °C to +85°C
Commercial
Industrial
J
V
CCAUX
Auxiliary supply voltage relative to GND, T = –40°C to +100°C
J
Supply voltage relative to GND, T = 0 °C to +85°C
Commercial
Industrial
J
V
CCO
Supply voltage relative to GND, T = –40°C to +100°C
1.2
3.6
J
Battery voltage relative to GND, T = 0 °C to +85°C
Commercial
Industrial
1.0
3.6
J
V
BATT
Battery voltage relative to GND, T = –40°C to +100°C
1.0
3.6
J
Notes:
1. If battery is not used, do not connect V
.
BATT
2. Recommended maximum voltage droop for V
is 10 mV/ms.
CCAUX
3. The thresholds for Power On Reset are V
> 1.2V, V
> 2.5V, and V (Bank 4) > 1.5 V.
CCINT
CCAUX
CCO
4. For power bypassing guidelines, see XAPP623 at www.xilinx.com.
Table 3: DC Characteristics Over Recommended Operating Conditions
Symbol Description
voltage
Device
All
Min
Max Units
V
Data retention V
Data retention V
1.2
2.5
V
V
DRINT
CCINT
V
I
voltage
All
DRI
CCAUX
V
current per bank
REF
All
–10
–10
+10
+10
10
µA
µA
pF
µA
µA
nA
REF
I
Input leakage current
Input capacitance
All
L
C
All
IN
I
Pad pull-up (when selected) @ V = 0 V, V = 3.3 V (sample tested)
CCO
All
All
All
Note 1 250
Note 1 250
100
RPU
RPD
IN
I
Pad pull-down (when selected) @ V = 3.6 V (sample tested)
IN
I
Battery supply current
BATT
Notes:
1. Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors
do not guarantee valid logic levels when input pins are connected to other circuits.
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Virtex-II 1.5V Field-Programmable Gate Arrays
Table 4: Quiescent Supply Current
Symbol
Description
supply current
Device
Min
Typical
Max
Units
XC2V40
XC2V80
50
50
65
TBD
125
150
200
250
350
400
500
650
800
TBD
Quiescent V
Quiescent V
Quiescent V
CCINT
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
80
100
125
150
200
225
250
TBD
I
mA
CCINTQ
(1,2)
XC2V40
XC2V80
1
1
1
1
1
2
2
2
2
TBD
2
2
2
2
4
4
4
4
supply current
CCO
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
mA
I
CCOQ
2
TBD
4
TBD
(1,2)
XC2V40
XC2V80
10
10
TBD
25
supply current
CCAUX
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
10
10
10
15
15
20
20
25
25
25
25
50
50
75
75
100
TBD
mA
I
CCAUXQ
TBD
Notes:
1. With no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating.
2. If DCI or differential signaling is used, more accurate values can be obtained by using the Power Estimator or XPOWER™.
3. Data are retained even if V drops to 0 V.
CCO
4. Values specified for quiescent supply current parameters are Commercial Grade. For Industrial Grade values, multiply Commercial
Grade values by 1.25.
If any V
bank powers up before V
, then each bank
Power-On Power Supply Requirements
CCO
CCAUX
draws up to 300 mA, worst case, until the V
powers
CCAUX
Xilinx FPGAs require a certain amount of supply current
during power-on to insure proper device operation. The
actual current consumed depends on the power-on ramp
rate of the power supply.
(1)
on . This does not harm the device. If the current is limited
to the minimum value above, or larger, the device powers on
properly after all three supplies have passed through their
power on reset threshold voltages.
The V
, V
, and V
power supplies shall each
CCO
CCINT CCAUX
Once initialized and configured, use the power calculator to
estimate current drain on these supplies.
ramp on no faster than 200 µs and no slower than 50 ms.
Ramp on is defined as: 0 V to minimum supply voltages.
DC
Notes:
Table 5 shows the minimum current required by Virtex-II
devices for proper power on and configuration.
1. The 300 mA is transient current (peak); it eventually
disappears even if V
does not power up.
CCAUX
Power supplies can be turned on in any sequence.
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Virtex-II 1.5V Field-Programmable Gate Arrays
Table 5: Minimum Power On Current Required for Virtex-II Devices
Device (mA)
XC2V40, XC2V80,
XC2V250, XC2V500 XC2V1000 XC2V1500 XC2V2000
XC2V3000 XC2V4000
XC2V6000 XC2V8000
I
I
I
200
100
50
250
100
50
350
100
100
400
100
100
500
100
100
650
100
100
800
100
100
TBD
TBD
TBD
CCINTMIN
CCAUXMIN
CCOMIN
Notes:
1. Values specified for power on current parameters are Commercial Grade. For Industrial Grade values, multiply Commercial Grade
values by 1.25.
2.
I
values listed here apply to the entire device (all banks).
CCOMIN
General Power Supply Requirements
Proper decoupling of all FPGA power supplies is sessential.
Consult Xilinx Application Note 623 for detailed information
on power distribution system design.
tion are provided in Xilinx Answer Record 13756, available
at www.support.xilinx.com.
V
V
can share a power plane with 3.3V V
does not have excessive noise. Using simultaneously
, but only if
CCO
CCAUX
V
V
powers critical resources in the FPGA. Thus,
is especially susceptible to power supply noise.
CCAUX
CCAUX
CCO
switching output (SSO) limits are essential for keeping
power supply noise to a minimum. (More information on
SSO is available in Xilinx Answer Record 11713.)
Changes in V
voltage outside of 200 mV peak to peak
CCAUX
should take place at a rate no faster than 10 mV per milli-
second. Techniques to help reduce jitter and period distor-
DC Input and Output Levels
Values for V and V are recommended input voltages.
sen to ensure that all standards meet their specifications.
IL
IH
Values for I
and I
are guaranteed over the recom-
The selected standards are tested at minimum V
with
OL
OH
CCO
mended operating conditions at the V
and V
test
the respective V
and V
voltage levels shown. Other
OL
OH
OL
OH
points. Only selected standards are tested. These are cho-
standards are sample tested.
Table 6: DC Input and Output Levels
V
V
V
V
I
I
OH
Input/Output
Standard
IL
IH
OL
OH
OL
V, Min
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
V, Max
V, Min
2.0
V, Max
3.6
V, Max
0.4
V, Min
mA
24
mA
– 24
– 24
– 24
– 16
– 16
Note 2
Note 2
Note 2
n/a
(1)
LVTTL
0.8
0.8
0.7
2.4
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
PCI33_3
PCI66_3
PCI–X
2.0
3.6
0.4
V
V
– 0.4
24
CCO
CCO
1.7
2.7
0.4
– 0.4
– 0.4
– 0.4
24
35% V
35% V
30% V
30% V
65% V
1.95
1.7
0.4
V
V
16
CCO
CCO
CCO
CCO
CCO
CCO
CCO
CCO
CCO
CCO
65% V
50% V
50% V
0.4
16
V
V
+ 0.5
10% V
10% V
90% V
90% V
Note 2
Note 2
Note 2
36
CCO
CCO
CCO
CCO
CCO
CCO
+ 0.5
Note 2
Note 2
+ 0.1
Note 2
Note 2
Note 2
GTLP
V
– 0.1
– 0.05
– 0.1
– 0.1
– 0.1
– 0.1
– 0.2
V
V
V
V
V
V
V
V
+ 0.5
0.6
0.4
0.4
0.4
0.4
0.4
n/a
n/a
REF
REF
CCO
CCO
CCO
CCO
CCO
CCO
CCO
GTL
V
V
+ 0.05
+ 0.1
+ 0.1
+ 0.1
+ 0.1
+ 0.2
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
40
n/a
REF
REF
HSTL I
V
V
V
V
V
V
– 0.4
8
– 8
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
CCO
CCO
CCO
CCO
HSTL II
V
V
– 0.4
– 0.4
– 0.4
+ 0.6
16
– 16
– 8
HSTL III
HSTL IV
SSTL3 I
V
V
V
V
V
V
24
48
– 8
V
– 0.6
V
8
– 8
REF
REF
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Virtex-II 1.5V Field-Programmable Gate Arrays
Table 6: DC Input and Output Levels (Continued)
V
V
V
V
I
I
OH
Input/Output
Standard
SSTL3 II
SSTL2 I
IL
IH
OL
OH
OL
V, Min
– 0.5
– 0.5
– 0.5
– 0.5
V, Max
V, Min
V, Max
V, Max
– 0.8
V, Min
V + 0.8
REF
mA
16
mA
– 16
V
V
V
V
– 0.2
– 0.2
– 0.2
– 0.2
V
V
V
V
+ 0.2
V
V
V
V
+ 0.5
V
REF
REF
REF
REF
REF
REF
REF
REF
CCO
CCO
CCO
CCO
REF
+ 0.2
+ 0.2
+ 0.2
+ 0.5
+ 0.5
+ 0.5
V
V
– 0.65
– 0.80
V
+ 0.65
+ 0.80
7.6
– 7.6
– 15.2
Note 2
REF
REF
REF
REF
SSTL2 II
AGP
V
15.2
Note 2
10% V
90% V
CCO
CCO
Notes:
1.
V
and V for lower drive currents are sample tested. The DONE pin is always LVTTL 12 mA.
OH
OL
2. Tested according to the relevant specifications.
3. LVTTL and LVCMOS inputs have approximately 100 mV of hysteresis.
LDT Differential Signal DC Specifications (LDT_25)
Table 7: LDT DC Specifications
DC Parameter
Symbol
Conditions
Min
500
–15
560
–15
200
–15
500
–15
Typ
Max
Units
mV
mV
mV
mV
mV
mV
mV
mV
Differential Output Voltage
V
R = 100 Ω across Q and Q signals
600
700
15
OD
T
Change in V Magnitude
∆ V
OD
OD
Output Common Mode Voltage
V
R = 100 Ω across Q and Q signals
600
600
600
640
15
OCM
T
Change in V Magnitude
∆ V
OS
OCM
Input Differential Voltage
V
1000
15
ID
Change in V Magnitude
∆ V
ID
ID
Input Common Mode Voltage
V
700
15
ICM
Change in V
Magnitude
∆ V
ICM
ICM
LVDS DC Specifications (LVDS_33 & LVDS_25)
Table 8: LVDS DC Specifications
DC Parameter
Supply Voltage
Symbol
Conditions
Min
Typ
Max
Units
V
3.3 or 2.5
V
V
V
CCO
Output High Voltage for Q and Q
Output Low Voltage for Q and Q
V
R = 100 Ω across Q and Q signals
1.575
OH
T
V
R = 100 Ω across Q and Q signals
0.925
250
OL
T
Differential Output Voltage (Q – Q),
Q = High (Q – Q), Q = High
V
R = 100 Ω across Q and Q signals
350
1.2
400
1.375
N/A
mV
V
ODIFF
T
Output Common-Mode Voltage
V
R = 100 Ω across Q and Q signals
1.125
100
OCM
IDIFF
T
Differential Input Voltage (Q – Q),
Q = High (Q – Q), Q = High
V
Common-mode input voltage = 1.25 V
Differential input voltage = 350 mV
350
1.25
mV
V
Input Common-Mode Voltage
V
0.2
V
– 0.5
CCO
ICM
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Extended LVDS DC Specifications (LVDSEXT_33 & LVDSEXT_25)
Table 9: Extended LVDS DC Specifications
DC Parameter
Supply Voltage
Symbol
Conditions
Min
Typ
Max
Units
V
3.3 or 2.5
V
V
V
CCO
Output High voltage for Q and Q
Output Low voltage for Q and Q
V
R = 100 Ω across Q and Q signals
1.785
OH
T
V
R = 100 Ω across Q and Q signals
0.705
440
OL
T
Differential output voltage (Q – Q),
Q = High (Q – Q), Q = High
V
R = 100 Ω across Q and Q signals
820
1.375
N/A
mV
V
ODIFF
T
Output common-mode voltage
V
R = 100 Ω across Q and Q signals
1.125
100
1.200
350
OCM
IDIFF
T
Differential input voltage (Q – Q),
Q = High (Q – Q), Q = High
V
Common-mode input voltage = 1.25 V
Differential input voltage = 350 mV
mV
V
Input common-mode voltage
V
0.2
1.25
V
– 0.5
CCO
ICM
LVPECL DC Specifications
These values are valid when driving a 100 Ω differential
load only, i.e., a 100 Ω resistor between the two receiver
levels and are compatible with devices tolerant of lower
common-mode ranges. Table 10 summarizes the DC output
specifications of LVPECL.
pins. The V
levels are 200 mV below standard LVPECL
OH
Table 10: LVPECL DC Specifications
DC Parameter
Min
Max
Min
Max
Min
Max
Units
V
3.0
3.3
3.6
V
V
V
V
V
V
CCO
V
1.8
0.96
1.49
0.86
0.3
2.11
1.27
2.72
2.125
–
1.92
1.06
1.49
0.86
0.3
2.28
1.43
2.72
2.125
–
2.13
1.30
1.49
0.86
0.3
2.41
1.57
2.72
2.125
–
OH
V
OL
V
IH
V
IL
Differential Input Voltage
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Virtex-II 1.5V Field-Programmable Gate Arrays
Virtex-II Performance Characteristics
This section provides the performance characteristics of
some common functions and designs implemented in
Virtex-II devices. The numbers reported here are worst-case
values; they have all been fully characterized. Note that
these values are subject to the same guidelines as Virtex-II
Switching Characteristics, page 9 (speed files).
Table 11 provides pin-to-pin values (in nanoseconds)
including IOB delays; that is, delay through the device from
input pin to output pin. In the case of multiple inputs and out-
puts, the worst delay is reported.
Table 11: Pin-to-Pin Performance
Description
Basic Functions
Device Used & Speed Grade Pin-to-Pin (with I/O delays) Units
XC2V1000 –5
XC2V1000 –5
XC2V1000 –5
XC2V1000 –5
XC2V1000 –5
XC2V1000 –5
XC2V1000 –5
XC2V1000 –5
6.3
7.7
9.3
5.7
6.5
6.7
8.7
5.0
ns
ns
ns
ns
ns
ns
ns
ns
16-bit Address Decoder
32-bit Address Decoder
64-bit Address Decoder
4:1 MUX
8:1 MUX
16:1 MUX
32:1 MUX
Combinatorial (pad to LUT to pad)
Memory
Block RAM
1.6
9.5
ns
ns
Pad to setup
Clock to Pad
Distributed RAM
Pad to setup
XC2V1000 –5
XC2V1000 –5
2.7
ns
ns
Clock to Pad
5.1 (no clk skew)
Table 12 shows internal (register-to-register) performance. Values are reported in MHz.
Table 12: Register-to-Register Performance
Device Used & Speed
Grade
Register-to-Register
Performance
Description
Basic Functions
Units
XC2V1000 –5
XC2V1000 –5
XC2V1000 –5
XC2V1000 –5
XC2V1000 –5
XC2V1000 –5
XC2V1000 –5
XC2V1000 –5
398
291
274
563
454
414
323
613
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
16-bit Address Decoder
32-bit Address Decoder
64-bit Address Decoder
4:1 MUX
8:1 MUX
16:1 MUX
32:1 MUX
Register to LUT to Register
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Virtex-II 1.5V Field-Programmable Gate Arrays
Table 12: Register-to-Register Performance (Continued)
Device Used & Speed
Register-to-Register
Performance
Description
Grade
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
XC2V1000 –5
XC2V1000 –5
XC2V1000 –5
XC2V1000 –5
XC2V1000 –5
XC2V1000 –5
XC2V1000 –5
292
239
114
114
110
88
8-bit Adder
16-bit Adder
64-bit Adder
64-bit Counter
64-bit Accumulator
Multiplier 18x18 (with Block RAM inputs)
Multiplier 18x18 (with Register inputs)
Memory
105
Block RAM
278
277
270
253
257
259
250
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Single-Port 4096 x 4 bits
Single-Port 2048 x 9 bits
Single-Port 1024 x 18 bits
Single-Port 512 x 36 bits
Dual-Port A:4096 x 4 bits & B:1024 x 18 bits
Dual-Port A:1024 x 18 bits & B:1024 x 18 bits
Dual-Port A:2048 x 9 bits & B: 512 x 36 bits
Distributed RAM
XC2V1000 –5
XC2V1000 –5
XC2V1000 –5
XC2V1000 –5
XC2V1000 –5
XC2V1000 –5
387
335
266
409
311
294
MHz
MHz
MHz
MHz
MHz
MHz
Single-Port 32 x 8-bit
Single-Port 64 x 8-bit
Single-Port 128 x 8-bit
Dual-Port 16 x 8
Dual-Port 32 x 8
Dual-Port 64 x 8
Shift Registers
N/A
N/A
MHz
MHz
128-bit SRL
256-bit SRL
FIFOs (Async. in Block RAM)
1024 x 18-bit Read
279
172
MHz
MHz
1024 x 18-bit Write
FIFOs (Sync. in SRL)
128 x 8-bit
N/A
N/A
MHz
MHz
128 x 16-bit
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Virtex-II 1.5V Field-Programmable Gate Arrays
Virtex-II Switching Characteristics
Switching characteristics in this document are specified on
a per-speed-grade basis and can be designated as
Advance, Preliminary, or Production. Note that Virtex-II
Performance Characteristics, page 7 are subject to these
guidelines, as well. Each designation is defined as follows:
completely on the status of the fabrication process for each
device. Table 13 correlates the current status of each Virtex-II
device with a corresponding speed grade designation.
The values reported in this version of the switching charac-
teristics are extracted from speeds file version 1.111.
Advance: These speed files are based on simulations only
and are typically available soon after device design specifi-
cations are frozen. Although speed grades with this desig-
nation are considered relatively stable and conservative,
some under-reporting might still occur.
Table 13: Virtex-II Device Speed Grade Designations
Speed Grade Designations
Device
XC2V40
Advance
Preliminary Production
–6, –5, –4
Preliminary: These speed files are based on complete ES
(engineering sample) silicon characterization. Devices and
speed grades with this designation are intended to give a
better indication of the expected performance of production
silicon. The probability of under-reporting delays is greatly
reduced as compared to Advance data.
Production: These speed files are released once enough
production silicon of a particular device family member has
been characterized to provide full correlation between
speed files and devices over numerous production lots.
There is no under-reporting of delays, and customers
receive formal notification of any subsequent changes. Typ-
ically, the slowest speed grades transition to Production
before faster speed grades.
XC2V80
–6
–6
–5, –4
–5, –4
–5, –4
–5, –4
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
–6
–6
–6, –5, –4
–6
–5, –4
–5, –4
–5, –4
–5, –4
–6
–6
–6
–5, –4
All specifications are always representative of worst-case
supply voltage and junction temperature conditions.
Since individual family members are produced at different
times, the migration from one category to another depends
Testing of Switching Characteristics
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the Xilinx static timing analyzer
and back-annotate to the simulation net list. Unless other-
wise noted, values apply to all Virtex-II devices.
IOB Input Switching Characteristics
Input delays associated with the pad are specified for
LVTTL levels. For other standards, adjust the delays with
the values shown in IOB Input Switching Characteristics
Standard Adjustments, page 11.
Table 14: IOB Input Switching Characteristics
Speed Grade
Description
Propagation Delays
Symbol
Device
– 6
– 5
– 4
Units
T
All
0.69
1.92
1.92
1.92
1.92
1.92
1.92
1.92
1.97
1.97
2.10
TBD
0.76
2.11
2.11
2.11
2.11
2.11
2.11
2.11
2.16
2.16
2.31
TBD
0.88
2.43
2.43
2.43
2.43
2.43
2.43
2.43
2.49
2.49
2.66
TBD
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
Pad to I output, no delay
Pad to I output, with delay
IOPI
XC2V40
T
IOPID
XC2V80
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
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Table 14: IOB Input Switching Characteristics (Continued)
Speed Grade
– 5
Description
Symbol
Device
– 6
– 4
Units
Propagation Delays
Pad to output IQ via transparent
latch, no delay
T
All
0.83
0.91
1.05
ns, Max
IOPLI
XC2V40
XC2V80
3.23
3.23
3.23
3.23
3.23
3.23
3.23
3.32
3.32
3.60
TBD
0.61
3.55
3.55
3.55
3.55
3.55
3.55
3.55
3.65
3.65
3.95
TBD
0.67
4.09
4.09
4.09
4.09
4.09
4.09
4.09
4.20
4.20
4.55
TBD
0.77
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
Pad to output IQ via transparent
latch, with delay
T
IOPLID
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
All
T
Clock CLK to output IQ
IOCKIQ
Setup and Hold Times With Respect to Clock at IOB Input
Register
Pad, no delay
T
/T
All
0.84/–0.36
3.24/–2.04
3.24/–2.04
3.24/–2.04
3.24/–2.04
3.24/–2.04
3.24/–2.04
3.24/–2.04
3.33/–2.10
3.33/–2.10
3.61/–2.29
TBD
0.92/–0.39
3.57/–2.24
3.57/–2.24
3.57/–2.24
3.57/–2.24
3.57/–2.24
3.57/–2.24
3.57/–2.24
3.67/–2.31
3.67/–2.31
3.97/–2.52
TBD
1.06/–0.45
4.10/–2.58
4.10/–2.58
4.10/–2.58
4.10/–2.58
4.10/–2.58
4.10/–2.58
4.10/–2.58
4.22/–2.66
4.22/–2.66
4.56/–2.90
TBD
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
IOPICK IOICKP
XC2V40
XC2V80
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
All
Pad, with delay
T
/T
IOPICKD IOICKPD
T
/T
0.19/ 0.03
0.27
0.21/ 0.04
0.30
0.24/ 0.04
0.34
ICE input
IOICECK IOCKICE
T
All
SR input (IFF, synchronous)
Set/Reset Delays
SR input to IQ (asynchronous)
GSR to output IQ
Notes:
IOSRCKI
T
All
All
1.11
7.39
1.22
7.99
1.40
9.19
ns, Max
ns, Max
IOSRIQ
T
GSRQ
1. Input timing for LVTTL is measured at 1.4 V. For other I/O standards, see Table 18.
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IOB Input Switching Characteristics Standard Adjustments
Table 15: IOB Input Switching Characteristics Standard Adjustments
Speed Grade
– 5
Description
Symbol
Standard
– 6
– 4
Units
Data Input Delay Adjustments
0.00
0.00
0.11
0.42
0.98
0.60
0.60
0.60
0.00
0.00
0.00
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.35
0.35
0.35
0.00
0.11
0.42
0.00
0.00
0.11
0.43
1.00
0.60
0.60
0.60
0.00
0.00
0.00
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.35
0.35
0.35
0.00
0.11
0.43
0.00
0.00
0.12
0.49
1.15
0.69
0.69
0.69
0.00
0.00
0.00
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.40
0.40
0.40
0.00
0.12
0.49
Standard-specific data input delay
adjustments
T
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVDS_25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ILVTTL
T
T
T
T
ILVCMOS33
ILVCMOS25
ILVCMOS18
ILVCMOS15
T
ILVDS_25
T
LVDS_33
ILVDS_33
T
LVPECL
ILVPECL_33
T
T
PCI, 33 MHz, 3.3 V
PCI, 66 MHz, 3.3 V
PCI–X, 133 MHz, 3.3 V
GTL
IPCI33_3
IPCI66_3
T
IPCIX
T
IGTL
T
GTLP
IGTLP
T
HSTL I
IHSTL_I
IHSTL_II
IHSTL_III
IHSTL_IV
T
HSTL II
T
HSTL III
T
HSTL IV
T
HSTL I_18
HSTL II_18
HSTL III_18
HSTL IV_18
SSTL2 I
IHSTL_I_18
IHSTL_II_18
IHSTL_III_18
IHSTL_IV_18
T
T
T
T
ISSTL2_I
ISSTL2_II
T
SSTL2 II
T
SSTL3 I
ISSTL3_I
ISSTL3_II
T
SSTL3 II
T
AGP
IAGP
T
T
T
LVDCI_33
LVDCI_25
LVDCI_18
ILVDCI_33
ILVDCI_25
ILVDCI_18
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Virtex-II 1.5V Field-Programmable Gate Arrays
Table 15: IOB Input Switching Characteristics Standard Adjustments (Continued)
Speed Grade
– 5
Description
Symbol
Standard
LVDCI_15
– 6
– 4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.98
0.00
0.11
0.42
0.98
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.35
0.35
0.48
0.48
1.00
0.00
0.11
0.43
1.00
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.35
0.35
0.49
0.49
1.14
0.00
0.12
0.49
1.14
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.40
0.40
0.56
0.56
T
ILVDCI_15
T
T
T
T
LVDCI_DV2_33
LVDCI_DV2_25
LVDCI_DV2_18
LVDCI_DV2_15
GTL_DCI
ILVDCI_DV2_33
ILVDCI_DV2_25
ILVDCI_DV2_18
ILVDCI_DV2_15
T
IGTL_DCI
T
GTLP_DCI
IGTLP_DCI
T
HSTL_I_DCI
HSTL_II_DCI
HSTL_III_DCI
HSTL_IV_DCI
HSTL_I_DCI_18
HSTL_II_DCI_18
HSTL_III_DCI_18
HSTL_IV_DCI_18
SSTL2_I_DCI
SSTL2_II_DCI
SSTL3_I_DCI
SSTL3_II_DCI
LDT_25
IHSTL_I_DCI
IHSTL_II_DCI
IHSTL_III_DCI
IHSTL_IV_DCI
T
T
T
T
IHSTL_I_DCI_18
IHSTL_II_DCI_18
IHSTL_III_DCI_18
IHSTL_IV_DCI_18
T
T
T
T
ISSTL2_I_DCI
T
ISSTL2_II_DCI
T
ISSTL3_I_DCI
ISSTL3_II_DCI
T
T
ILDT_25
T
ULVDS_25
IULVDS_25
Notes:
1. Input timing for LVTTL is measured at 1.4 V. For other I/O standards, see Table 18.
Module 3 of 4
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Virtex-II 1.5V Field-Programmable Gate Arrays
IOB Output Switching Characteristics
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays with the values shown in IOB Output Switching Characteristics Standard Adjustments, page 14.
Table 16: IOB Output Switching Characteristics
Speed Grade
Description
Propagation Delays
Symbol
– 6
– 5
– 4
Units
O input to Pad
T
2.52
2.81
2.63
2.95
3.03
3.40
ns, Max
ns, Max
IOOP
O input to Pad via transparent latch
3-State Delays
T
IOOLP
(1)
0.51
2.47
0.56
2.57
0.64
2.96
T input to Pad high-impedance
T
ns, Max
ns, Max
IOTHZ
IOTON
T input to valid data on Pad
T
T input to Pad high-impedance via transparent
latch
T
0.80
0.88
1.01
ns, Max
IOTLPHZ
IOTLPON
(1)
T input to valid data on Pad via transparent latch
T
2.76
6.69
2.89
7.22
3.33
8.30
ns, Max
ns, Max
(1)
GTS to Pad high impedance
T
GTS
Sequential Delays
2.84
0.95
2.90
2.99
1.04
3.06
3.44
1.20
3.51
Clock CLK to Pad
T
ns, Max
ns, Max
ns, Max
IOCKP
Clock CLK to Pad high-impedance
T
IOCKHZ
IOCKON
(1)
(synchronous)
Clock CLK to valid data on Pad (synchronous)
Setup and Hold Times Before/After Clock CLK
O input
T
0.31/–0.08
0.19/–0.06
0.27/–0.05
0.28/–0.06
0.19/–0.06
0.27/–0.05
0.34/–0.09
0.21/–0.07
0.30/–0.06
0.31/–0.07
0.21/–0.07
0.30/–0.06
0.39/–0.11
0.24/–0.08
0.34/–0.07
0.35/–0.08
0.24/–0.08
0.34/–0.07
T
/T
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
IOOCK IOCKO
OCE input
T
T
/T
IOOCECK IOCKOCE
SR input (OFF)
/T
IOSRCKO IOCKOSR
3–State Setup Times, T input
3–State Setup Times, TCE input
3–State Setup Times, SR input (TFF)
Set/Reset Delays
T
/T
IOTCK IOCKT
T
T
/T
IOTCECK IOCKTCE
/T
IOSRCKT IOCKTSR
3.50
1.52
3.71
1.67
4.26
1.92
SR input to Pad (asynchronous)
SR input to Pad high-impedance
T
ns, Max
ns, Max
IOSRP
T
IOSRHZ
(1)
(asynchronous)
3.47
5.44
3.68
5.98
4.23
6.88
SR input to valid data on Pad (asynchronous)
GSR to Pad
T
T
ns, Max
ns, Max
IOSRON
IOGSRQ
Notes:
1. The 3-state turn-off delays should not be adjusted.
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Virtex-II 1.5V Field-Programmable Gate Arrays
IOB Output Switching Characteristics Standard Adjustments
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays by the values shown.
Table 17: IOB Output Switching Characteristics Standard Adjustments
Speed Grade
Description
Symbol
Standard
– 6
– 5
– 4
Units
Output Delay Adjustments
Standard-specific adjustments for output
delays terminating at pads (based on
standard capacitive load, Csl)
T
LVTTL, Slow, 2 mA
4 mA
15.28
8.61
15.73
8.87
18.09
10.20
7.03
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
OLVTTL_S2
T
OLVTTL_S4
T
6 mA
5.94
6.11
OLVTTL_S6
T
8 mA
3.68
3.79
4.35
OLVTTL_S8
OLVTTL_S12
OLVTTL_S16
OLVTTL_S24
T
T
T
12 mA
2.61
2.69
3.09
16 mA
1.65
1.70
1.96
24 mA
1.08
1.11
1.28
T
LVTTL, Fast, 2 mA
4 mA
12.16
5.09
12.52
5.25
14.40
6.03
OLVTTL_F2
OLVTTL_F4
OLVTTL_F6
OLVTTL_F8
T
T
T
6 mA
3.26
3.35
3.85
8 mA
0.53
0.54
0.62
T
T
T
12 mA
0.00
0.00
0.00
OLVTTL_F12
OLVTTL_F16
OLVTTL_F24
16 mA
–0.43
–0.60
–1.27
–1.07
–1.15
–1.14
–1.21
0.67
–0.45
–0.62
–1.31
–1.11
–1.19
–1.18
–1.25
0.69
–0.51
–0.71
–1.51
–1.27
–1.37
–1.35
–1.44
0.79
24 mA
T
LVDS
OLVDS_25
OLVDS_33
T
LVDS
T
T
LVDS
OLVDSEXT_25
OLVDSEXT_33
LVDS
T
LDT
OLDT_25
T
BLVDS
OBLVDS_25
OULVDS_25
T
ULVDS
–1.21
0.14
–1.25
0.15
–1.44
0.17
T
LVPECL
PCI, 33 MHz, 3.3 V
PCI, 66 MHz, 3.3 V
PCI–X, 133 MHz, 3.3 V
GTL
OLVPECL_33
T
T
–0.22
–0.85
–0.84
–1.31
–1.05
–0.65
–1.04
–1.06
–1.28
–0.83
–1.07
–1.05
–1.26
–0.22
–0.88
–0.87
–1.35
–1.09
–0.67
–1.07
–1.09
–1.32
–0.85
–1.10
–1.08
–1.29
–0.26
–1.01
–1.00
–1.55
–1.25
–0.77
–1.24
–1.26
–1.51
–0.98
–1.27
–1.24
–1.49
OPCI33_3
OPCI66_3
T
OPCIX
T
OGTL
T
GTLP
OGTLP
T
HSTL I
OHSTL_I
T
HSTL II
OHSTL_II
OHSTL_III
T
HSTL III
HSTL IV
HSTL I_18
HSTL II_18
HSTL III_18
HSTL IV_18
T
OHSTL_IV
T
OHSTL_I_18
T
OHSTL_II_18
OHSTL_III_18
T
T
OHSTL_IV_18
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Table 17: IOB Output Switching Characteristics Standard Adjustments (Continued)
Speed Grade
– 5
Description
Symbol
Standard
– 6
– 4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
T
SSTL2 I
–0.73
–1.10
–0.65
–1.01
–1.07
13.63
6.45
–0.75
–1.13
–0.67
–1.04
–1.10
14.04
6.64
–0.87
–1.30
–0.78
–1.20
–1.27
16.14
7.63
OSSTL2_I
OSSTL2_II
T
SSTL2 II
T
SSTL3 I
OSSTL3_I
OSSTL3_II
T
SSTL3 II
T
AGP
OAGP
OLVCMOS33_S2
T
LVCMOS33, Slow, 2 mA
T
4 mA
OLVCMOS33_S4
T
6 mA
4.56
4.70
5.40
OLVCMOS33_S6
T
8 mA
2.62
2.70
3.11
OLVCMOS33_S8
OLVCMOS33_S12
OLVCMOS33_S16
OLVCMOS33_S24
T
T
T
12 mA
1.87
1.93
2.21
16 mA
1.15
1.18
1.36
24 mA
0.91
0.94
1.08
T
LVCMOS33, Fast, 2 mA
11.63
4.64
11.97
4.78
13.77
5.49
OLVCMOS33_F2
OLVCMOS33_F4
OLVCMOS33_F6
OLVCMOS33_F8
T
4 mA
T
T
6 mA
2.14
2.20
2.53
8 mA
0.48
0.50
0.57
T
T
T
12 mA
0.04
0.05
0.05
OLVCMOS33_F12
OLVCMOS33_F16
OLVCMOS33_F24
16 mA
–0.48
–0.58
12.68
6.57
–0.49
–0.60
13.05
6.76
–0.57
–0.69
15.01
7.78
24 mA
T
LVCMOS25, Slow, 2 mA
OLVCMOS25_S2
T
4 mA
OLVCMOS25_S4
T
6 mA
5.83
6.00
6.90
OLVCMOS25_S6
T
8 mA
4.84
4.98
5.73
OLVCMOS25_S8
OLVCMOS25_S12
OLVCMOS25_S16
OLVCMOS25_S24
T
T
T
12 mA
3.03
3.12
3.59
16 mA
2.33
2.40
2.76
24 mA
1.83
1.89
2.17
T
LVCMOS25, Fast, 2 mA
9.05
9.32
10.72
4.09
OLVCMOS25_F2
OLVCMOS25_F4
OLVCMOS25_F6
OLVCMOS25_F8
T
4 mA
3.45
3.55
T
T
6 mA
1.11
1.14
1.31
8 mA
0.49
0.51
0.58
T
T
T
12 mA
–0.11
–0.37
–0.61
20.74
12.35
8.76
–0.11
–0.38
–0.63
21.36
12.72
9.02
–0.13
–0.44
–0.72
24.57
14.63
10.37
9.29
OLVCMOS25_F12
OLVCMOS25_F16
OLVCMOS25_F24
16 mA
24 mA
T
LVCMOS18, Slow, 2 mA
OLVCMOS18_S2
T
4 mA
OLVCMOS18_S4
T
6 mA
8 mA
OLVCMOS18_S6
T
7.84
8.08
OLVCMOS18_S8
OLVCMOS18_S12
OLVCMOS18_S16
T
T
12 mA
5.85
6.03
6.93
16 mA
5.46
5.62
6.46
T
LVCMOS18, Fast, 2 mA
9.63
9.92
11.40
OLVCMOS18_F2
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Virtex-II 1.5V Field-Programmable Gate Arrays
Table 17: IOB Output Switching Characteristics Standard Adjustments (Continued)
Speed Grade
– 5
Description
Symbol
Standard
4 mA
– 6
– 4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
T
T
T
4.29
4.41
5.08
OLVCMOS18_F4
OLVCMOS18_F6
OLVCMOS18_F8
6 mA
1.61
1.66
1.91
8 mA
1.03
1.06
1.22
T
T
12 mA
0.26
0.27
0.31
OLVCMOS18_F12
OLVCMOS18_F16
16 mA
0.11
0.11
0.12
T
LVCMOS15, Slow, 2 mA
4 mA
23.54
14.89
13.58
10.62
9.58
24.25
15.34
13.99
10.94
9.86
27.88
17.64
16.08
12.58
11.34
10.24
10.81
5.74
OLVCMOS15_S2
T
OLVCMOS15_S4
T
6 mA
OLVCMOS15_S6
T
8 mA
OLVCMOS15_S8
OLVCMOS15_S12
OLVCMOS15_S16
T
T
12 mA
16 mA
8.65
8.91
T
LVCMOS15, Fast, 2 mA
4 mA
9.13
9.40
OLVCMOS15_F2
OLVCMOS15_F4
OLVCMOS15_F6
OLVCMOS15_F8
T
4.84
4.99
T
T
6 mA
2.20
2.27
2.61
8 mA
1.16
1.20
1.38
T
T
12 mA
0.75
0.78
0.89
OLVCMOS15_F12
OLVCMOS15_F16
16 mA
0.61
0.63
0.72
T
T
T
T
LVDCI_33
1.91
1.97
2.26
OLVDCI_33
OLVDCI_25
OLVDCI_18
OLVDCI_15
LVDCI_25
1.36
1.40
1.61
LVDCI_18
1.29
1.33
1.53
LVDCI_15
0.96
0.99
1.14
T
LVDCI_DV2_33
LVDCI_DV2_25
LVDCI_DV2_18
LVDCI_DV2_15
GTL_DCI
1.91
1.97
2.27
OLVDCI_DV2_33
T
1.36
1.40
1.61
OLVDCI_DV2_25
T
1.03
1.06
1.22
OLVDCI_DV2_18
T
0.94
0.96
1.11
OLVDCI_DV2_15
T
–1.38
–1.00
–0.65
–0.72
–1.09
–1.35
–0.84
–0.94
–1.05
–1.28
–0.84
–1.02
–0.85
–0.74
–1.42
–1.03
–0.67
–0.74
–1.12
–1.39
–0.86
–0.97
–1.08
–1.32
–0.86
–1.05
–0.88
–0.76
–1.63
–1.18
–0.77
–0.85
–1.29
–1.59
–0.99
–1.12
–1.24
–1.52
–0.99
–1.20
–1.01
–0.88
OGTL_DCI
T
GTLP_DCI
HSTL_I_DCI
HSTL_II_DCI
HSTL_III_DCI
HSTL_IV_DCI
HSTL_I_DCI_18
HSTL_II_DCI_18
HSTL_III_DCI_18
HSTL_IV_DCI_18
SSTL2_I_DCI
SSTL2_II_DCI
SSTL3_I_DCI
SSTL3_II_DCI
OGTLP_DCI
T
OHSTL_I_DCI
OHSTL_II_DCI
OHSTL_III_DCI
T
T
T
OHSTL_IV_DCI
T
OHSTL_I_DCI_18
OHSTL_II_DCI_18
OHSTL_III_DCI_18
T
T
T
OHSTL_IV_DCI_18
T
OSSTL2_I_DCI
OSSTL2_II_DCI
T
T
OSSTL3_I_DCI
OSSTL3_II_DCI
T
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Virtex-II 1.5V Field-Programmable Gate Arrays
Table 18: Delay Measurement Methodology
(1)
(1)
(2)
Standard
V
V
Meas. Point
V (Typ)
REF
L
H
LVTTL
0
3
1.4
1.65
1.25
0.9
–
–
–
–
–
–
–
–
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
PCI33_3
0
0
0
0
3.3
2.5
1.8
1.5
0.75
Per PCI Specification
Per PCI Specification
Per PCI–X Specification
PCI66_3
PCIX33_3
GTL
V
V
V
V
V
V
V
– 0.2
– 0.2
– 0.5
– 0.5
– 0.5
– 0.5
– 1.0
– 0.75
V
V
V
V
V
V
V
+ 0.2
+ 0.2
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 1.0
+ 0.75
V
V
V
V
V
V
V
V
V
0.80
1.0
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
GTLP
HSTL Class I
HSTL Class II
HSTL Class III
HSTL Class IV
SSTL3 I & II
SSTL2 I & II
AGP
0.75
0.75
0.90
0.90
1.5
V
V
1.25
REF
REF
V
– (0.2xV
)
V
+ (0.2xV )
CCO
Per AGP Spec
REF
CCO
REF
LVDS_25
1.2
1.2
1.2
1.2
0.6
0.6
1.6
1.2 – 0.125
1.2 – 0.125
1.2 – 0.125
1.2 – 0.125
0.6 – 0.125
0.6 – 0.125
1.6 –0.3
1.2 + 0.125
1.2 + 0.125
1.2 + 0.125
1.2 + 0.125
0.6 + 0.125
0.6 + 0.125
1.6 + 0.3
LVDS_33
LVDSEXT_25
LVDSEXT_33
ULVDS_25
LDT_25
LVPECL
Notes:
1. Input waveform switches between V and V .
L
H
2. Measurements are made at V
(Typ), Maximum, and Minimum. Worst-case values are reported.
REF
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Virtex-II 1.5V Field-Programmable Gate Arrays
Table 19: Standard Capacitive Loads
Standard
Csl (pF)
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
10
10
10
0
LVTTL Fast Slew Rate, 2mA drive
LVTTL Fast Slew Rate, 4mA drive
LVTTL Fast Slew Rate, 6mA drive
LVTTL Fast Slew Rate, 8mA drive
LVTTL Fast Slew Rate, 12mA drive
LVTTL Fast Slew Rate, 16mA drive
LVTTL Fast Slew Rate, 24mA drive
LVTTL Slow Slew Rate, 2mA drive
LVTTL Slow Slew Rate, 4mA drive
LVTTL Slow Slew Rate, 6mA drive
LVTTL Slow Slew Rate, 8mA drive
LVTTL Slow Slew Rate, 12mA drive
LVTTL Slow Slew Rate, 16mA drive
LVTTL Slow Slew Rate, 24mA drive
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
PCI 33MHZ 3.3 V
PCI 66 MHz 3.3 V
PCI–X 133 MHz 3.3 V
GTL
GTLP
0
HSTL Class I
10
10
10
10
10
10
10
10
10
HSTL Class II
HSTL Class III
HSTL Class IV
SSTL2 Class I
SSTL2 Class II
SSTL3 Class I
SSTL3 Class II
AGP
Notes:
1. I/O parameter measurements are made with the capacitance values shown above.
2. I/O standard measurements are reflected in the IBIS model information except where the IBIS format precludes it.
3. Use of IBIS models results in a more accurate prediction of the propagation delay:
a. Model the output in an IBIS simulation into the standard capacitive load.
b. Record the relative time to the V or V transition of interest.
OH
OL
c. Remove the capacitance, and model the actual PCB traces (transmission lines) and actual loads from the appropriate IBIS
models for driven devices.
d. Record the results from the new simulation.
e. Compare with the capacitance simulation. The increase or decrease in delay from the capacitive load delay simulation should
be added or subtracted from the value above to predict the actual delay.
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Virtex-II 1.5V Field-Programmable Gate Arrays
Clock Distribution Switching Characteristics
Table 20: Clock Distribution Switching Characteristics
Speed Grade
Description
Symbol
– 6
– 5
– 4
Units
Global Clock Buffer I input to O output
T
0.47
0.52
0.59
ns, Max
GIO
CLB Switching Characteristics
Delays originating at F/G inputs vary slightly according to the input used (see Figure 16). The values listed below are
worst-case. Precise values are provided by the timing analyzer.
Table 21: CLB Switching Characteristics
Speed Grade
Description
Combinatorial Delays
Symbol
– 6
– 5
– 4
Units
0.35
0.57
0.76
0.36
0.26
0.26
0.35
0.39
0.63
0.83
0.39
0.28
0.28
0.38
0.44
0.72
0.95
0.45
0.32
0.32
0.44
4-input function: F/G inputs to X/Y outputs
5-input function: F/G inputs to F5 output
5-input function: F/G inputs to X output
FXINA or FXINB inputs to Y output via MUXFX
FXINA input to FX output via MUXFX
FXINB input to FX output via MUXFX
SOPIN input to SOPOUT output via ORCY
T
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ILO
T
IF5
T
T
IF5X
IFXY
T
T
INAFX
INBFX
T
SOPSOP
Incremental delay routing through transparent latch
to XQ/YQ outputs
0.41
0.45
0.51
T
ns, Max
IFNCTL
Sequential Delays
0.45
0.54
0.50
0.59
0.57
0.68
FF Clock CLK to XQ/YQ outputs
Latch Clock CLK to XQ/YQ outputs
Setup and Hold Times Before/After Clock CLK
BX/BY inputs
T
ns, Max
ns, Max
CKO
T
CKLO
0.30/–0.07
0.30/–0.07
0.30/–0.07
0.19/–0.06
0.21/–0.02
0.33/–0.08
0.33/–0.08
0.33/–0.08
0.21/–0.07
0.23/–0.03
0.37/–0.09
0.37/–0.09
0.37/–0.09
0.24/–0.08
0.26/–0.03
T
/T
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
DICK CKDI
DY inputs
T
/T
DYCK CKDY
DX inputs
T
T
T
/T
DXCK CKDX
CE input
/T
CECK CKCE
SR/BY inputs (synchronous)
Clock CLK
T
SRCK/ SCKR
0.61
0.61
0.67
0.67
0.77
0.77
Minimum Pulse Width, High
Minimum Pulse Width, Low
Set/Reset
T
ns, Min
ns, Min
CH
T
CL
0.61
1.06
820
0.67
1.17
750
0.77
1.34
650
Minimum Pulse Width, SR/BY inputs
T
ns, Min
ns, Max
MHz
RPW
Delay from SR/BY inputs to XQ/YQ outputs
(asynchronous)
T
RQ
Toggle Frequency (MHz) (for export control)
F
TOG
DS031-3 (v2.3) September 26, 2002
Advance Product Specification
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Module 3 of 4
19
R
Virtex-II 1.5V Field-Programmable Gate Arrays
CLB Distributed RAM Switching Characteristics
Table 22: CLB Distributed RAM Switching Characteristics
Speed Grade
– 5
Description
Symbol
– 6
– 4
Units
Sequential Delays
1.63
1.97
1.77
1.79
2.17
1.94
2.05
2.49
2.23
Clock CLK to X/Y outputs (WE active) in 16 x 1 mode
Clock CLK to X/Y outputs (WE active) in 32 x 1 mode
Clock CLK to F5 output
T
T
T
ns, Max
ns, Max
ns, Max
SHCKO16
SHCKO32
SHCKOF5
Setup and Hold Times Before/After Clock CLK
BX/BY data inputs (DIN)
0.53/–0.09
0.40/ 0.00
0.42/–0.01
0.58/–0.10
0.44/ 0.00
0.46/–0.01
0.67/–0.11
0.50/ 0.00
0.53/–0.01
T
/T
ns, Min
ns, Min
ns, Min
DS DH
F/G address inputs
T
/T
AS AH
SR input (WS)
T
/T
WES WEH
Clock CLK
Minimum Pulse Width, High
T
0.57
0.57
1.14
0.63
0.63
1.25
0.72
0.72
1.44
ns, Min
ns, Min
ns, Min
WPH
Minimum Pulse Width, Low
T
WPL
Minimum clock period to meet address write cycle time
T
WC
CLB Shift Register Switching Characteristics
Table 23: CLB Shift Register Switching Characteristics
Speed Grade
– 5
Description
Sequential Delays
Symbol
– 6
– 4
Units
2.31
2.65
2.23
2.18
1.92
2.45
2.54
2.92
2.46
2.40
2.11
2.69
2.92
3.35
2.82
2.75
2.43
3.09
Clock CLK to X/Y outputs
T
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
REG
Clock CLK to X/Y outputs
T
REG32
REGXB
REGYB
Clock CLK to XB output via MC15 LUT output
Clock CLK to YB output via MC15 LUT output
Clock CLK to Shiftout
T
T
T
CKSH
Clock CLK to F5 output
T
REGF5
Setup and Hold Times Before/After Clock CLK
BX/BY data inputs (DIN)
0.53/–0.07
0.19/–0.06
0.58/–0.08
0.21/–0.07
0.67/–0.09
0.24/–0.08
T
/T
ns, Min
ns, Min
SRLDS SRLDH
SR input (WS)
T
/T
WSS WSH
Clock CLK
Minimum Pulse Width, High
Minimum Pulse Width, Low
T
0.57
0.57
0.63
0.63
0.72
0.72
ns, Min
ns, Min
SRPH
T
SRPL
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Advance Product Specification
R
Virtex-II 1.5V Field-Programmable Gate Arrays
Multiplier Switching Characteristics
Table 24: Multiplier Switching Characteristics
Speed Grade
Description
Propagation Delay to Output Pin
Input to Pin 35
Input to Pin 34
Input to Pin 33
Input to Pin 32
Input to Pin 31
Input to Pin 30
Input to Pin 29
Input to Pin 28
Input to Pin 27
Input to Pin 26
Input to Pin 25
Input to Pin 24
Input to Pin 23
Input to Pin 22
Input to Pin 21
Input to Pin 20
Input to Pin 19
Input to Pin 18
Input to Pin 17
Input to Pin 16
Input to Pin 15
Input to Pin 14
Input to Pin 13
Input to Pin 12
Input to Pin 11
Input to Pin 10
Input to Pin 9
Symbol
– 6
– 5
– 4
Units
4.66
4.57
4.47
4.37
4.28
4.18
4.08
3.99
3.89
3.79
3.69
3.60
3.50
3.40
3.31
3.21
3.11
3.02
2.92
2.82
2.72
2.63
2.53
2.43
2.34
2.24
2.14
2.05
1.95
1.85
1.75
1.66
1.56
1.46
1.37
1.27
8.50
8.33
8.16
7.99
7.82
7.65
7.48
7.31
7.14
6.97
6.80
6.63
6.46
6.29
6.12
5.95
5.78
5.61
5.44
5.27
5.10
4.93
4.76
4.59
4.42
4.25
4.08
3.91
3.74
3.57
3.40
3.23
3.06
2.89
2.72
2.55
10.36
10.15
9.95
9.74
9.53
9.33
9.12
8.91
8.70
8.50
8.29
8.08
7.88
7.67
7.46
7.26
7.05
6.84
6.63
6.43
6.22
6.01
5.81
5.60
5.39
5.19
4.98
4.77
4.56
4.36
4.15
3.94
3.74
3.53
3.32
3.12
T
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
MULT_P35
MULT_P34
MULT_P33
MULT_P32
MULT_P31
MULT_P30
MULT_P29
MULT_P28
MULT_P27
MULT_P26
MULT_P25
MULT_P24
MULT_P23
MULT_P22
MULT_P21
MULT_P20
MULT_P19
MULT_P18
MULT_P17
MULT_P16
MULT_P15
MULT_P14
MULT_P13
MULT_P12
MULT_P11
MULT_P10
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
MULT_P9
MULT_P8
MULT_P7
MULT_P6
MULT_P5
MULT_P4
MULT_P3
MULT_P2
MULT_P1
MULT_P0
Input to Pin 8
T
Input to Pin 7
T
T
T
T
T
T
T
T
Input to Pin 6
Input to Pin 5
Input to Pin 4
Input to Pin 3
Input to Pin 2
Input to Pin 1
Input to Pin 0
DS031-3 (v2.3) September 26, 2002
Advance Product Specification
www.xilinx.com
1-800-255-7778
Module 3 of 4
21
R
Virtex-II 1.5V Field-Programmable Gate Arrays
Table 25: Pipelined Multiplier Switching Characteristics
Speed Grade
– 5
Description
Setup and Hold Times Before/After Clock
Data Inputs
Symbol
– 6
– 4
Units
T
/T
3.00/0.00
0.72/0.00
0.72/0.00
3.45/0.00
0.80/0.00
0.80/0.00
3.89/0.00
0.86/0.00
0.86/0.00
ns, Max
ns, Max
ns, Max
MULIDCK MULCKID
Clock Enable
T
/T
MULIDCK_CE MULCKID_CE
Reset
T
/T
MULIDCK_RST MULCKID_RST
Clock to Output Pin
Clock to Pin 35
Clock to Pin 34
Clock to Pin 33
Clock to Pin 32
Clock to Pin 31
Clock to Pin 30
Clock to Pin 29
Clock to Pin 28
Clock to Pin 27
Clock to Pin 26
Clock to Pin 25
Clock to Pin 24
Clock to Pin 23
Clock to Pin 22
Clock to Pin 21
Clock to Pin 20
Clock to Pin 19
Clock to Pin 18
Clock to Pin 17
Clock to Pin 16
Clock to Pin 15
Clock to Pin 14
Clock to Pin 13
Clock to Pin 12
Clock to Pin 11
Clock to Pin 10
Clock to Pin 9
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
2.76
2.66
2.56
2.47
2.37
2.27
2.17
2.08
1.98
1.88
1.79
1.69
1.59
1.50
1.40
1.30
1.20
1.11
1.01
0.91
0.91
0.91
0.91
0.91
0.91
0.91
0.91
0.91
0.91
0.91
0.91
0.91
0.91
0.91
0.91
0.91
6.91
6.75
6.59
6.43
6.27
6.11
5.95
5.79
5.63
5.47
5.31
5.15
4.99
4.83
4.67
4.51
4.35
4.19
4.03
3.87
3.71
3.55
3.39
3.23
3.07
2.91
2.75
2.59
2.43
2.27
2.11
1.95
1.79
1.63
1.47
1.31
8.12
7.93
7.74
7.56
7.37
7.19
7.00
6.81
6.63
6.44
6.26
6.07
5.88
5.70
5.51
5.33
5.14
4.95
4.77
4.58
4.40
4.21
4.02
3.84
3.65
3.47
3.28
3.09
2.91
2.72
2.54
2.35
2.16
1.98
1.79
1.61
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
MULTCK_P35
MULTCK_P34
MULTCK_P33
MULTCK_P32
MULTCK_P31
MULTCK_P30
MULTCK_P29
MULTCK_P28
MULTCK_P27
MULTCK_P26
MULTCK_P25
MULTCK_P24
MULTCK_P23
MULTCK_P22
MULTCK_P21
MULTCK_P20
MULTCK_P19
MULTCK_P18
MULTCK_P17
MULTCK_P16
MULTCK_P15
MULTCK_P14
MULTCK_P13
MULTCK_P12
MULTCK_P11
MULTCK_P10
T
MULTCK_P9
MULTCK_P8
MULTCK_P7
MULTCK_P6
MULTCK_P5
MULTCK_P4
MULTCK_P3
MULTCK_P2
MULTCK_P1
MULTCK_P0
Clock to Pin 8
T
Clock to Pin 7
T
T
T
T
T
T
T
T
Clock to Pin 6
Clock to Pin 5
Clock to Pin 4
Clock to Pin 3
Clock to Pin 2
Clock to Pin 1
Clock to Pin 0
Module 3 of 4
22
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DS031-3 (v2.3) September 26, 2002
Advance Product Specification
R
Virtex-II 1.5V Field-Programmable Gate Arrays
Enhanced Multiplier Switching Characteristics
Table 26 and Table 27 provide timing information for enhanced Virtex-II multiplier blocks, available in stepping revisions of
Virtex-II devices. For more information on stepping revisions, availability, and ordering instructions, see your local sales
representative.
Table 26: Enhanced Multiplier Switching Characteristics
Speed Grade
Description
Propagation Delay to Output Pin
Symbol
– 6
– 5
– 4
Units
Input to Pin 35
Input to Pin 34
Input to Pin 33
Input to Pin 32
Input to Pin 31
Input to Pin 30
Input to Pin 29
Input to Pin 28
Input to Pin 27
Input to Pin 26
Input to Pin 25
Input to Pin 24
Input to Pin 23
Input to Pin 22
Input to Pin 21
Input to Pin 20
Input to Pin 19
Input to Pin 18
Input to Pin 17
Input to Pin 16
Input to Pin 15
Input to Pin 14
Input to Pin 13
Input to Pin 12
Input to Pin 11
Input to Pin 10
Input to Pin 9
Input to Pin 8
Input to Pin 7
Input to Pin 6
Input to Pin 5
Input to Pin 4
Input to Pin 3
Input to Pin 2
Input to Pin 1
Input to Pin 0
T
4.66
4.57
4.47
4.37
4.28
4.18
4.08
3.99
3.89
3.79
3.69
3.60
3.50
3.40
3.31
3.21
3.11
3.02
2.92
2.82
2.72
2.63
2.53
2.43
2.34
2.24
2.14
2.05
1.95
1.85
1.75
1.66
1.56
1.46
1.37
1.27
5.14
5.03
4.93
4.82
4.71
4.61
4.50
4.39
4.28
4.18
4.07
3.96
3.86
3.75
3.64
3.54
3.43
3.32
3.21
3.11
3.00
2.89
2.79
2.68
2.57
2.47
2.36
2.25
2.14
2.04
1.93
1.82
1.72
1.61
1.50
1.40
5.91
5.79
5.66
5.54
5.42
5.29
5.17
5.05
4.92
4.80
4.68
4.56
4.43
4.31
4.19
4.06
3.94
3.82
3.69
3.57
3.45
3.33
3.20
3.08
2.96
2.83
2.71
2.59
2.46
2.34
2.22
2.10
1.97
1.85
1.73
1.60
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
MULT_P35
MULT_P34
MULT_P33
MULT_P32
MULT_P31
MULT_P30
MULT_P29
MULT_P28
MULT_P27
MULT_P26
MULT_P25
MULT_P24
MULT_P23
MULT_P22
MULT_P21
MULT_P20
MULT_P19
MULT_P18
MULT_P17
MULT_P16
MULT_P15
MULT_P14
MULT_P13
MULT_P12
MULT_P11
MULT_P10
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
MULT_P9
MULT_P8
MULT_P7
MULT_P6
MULT_P5
MULT_P4
MULT_P3
MULT_P2
MULT_P1
MULT_P0
T
T
T
T
T
T
T
T
T
DS031-3 (v2.3) September 26, 2002
Advance Product Specification
www.xilinx.com
1-800-255-7778
Module 3 of 4
23
R
Virtex-II 1.5V Field-Programmable Gate Arrays
Table 27: Enhanced Pipelined Multiplier Switching Characteristics
Speed Grade
– 5
Description
Setup and Hold Times Before/After Clock
Data Inputs
Symbol
– 6
– 4
Units
T
/T
3.00/0.00
0.72/0.00
0.72/0.00
3.45/0.00
0.80/0.00
0.80/0.00
3.89/0.00
0.86/0.00
0.86/0.00
ns, Max
ns, Max
ns, Max
MULIDCK MULCKID
Clock Enable
T
/T
MULIDCK_CE MULCKID_CE
Reset
T
/T
MULIDCK_RST MULCKID_RST
Clock to Output Pin
Clock to Pin 35
Clock to Pin 34
Clock to Pin 33
Clock to Pin 32
Clock to Pin 31
Clock to Pin 30
Clock to Pin 29
Clock to Pin 28
Clock to Pin 27
Clock to Pin 26
Clock to Pin 25
Clock to Pin 24
Clock to Pin 23
Clock to Pin 22
Clock to Pin 21
Clock to Pin 20
Clock to Pin 19
Clock to Pin 18
Clock to Pin 17
Clock to Pin 16
Clock to Pin 15
Clock to Pin 14
Clock to Pin 13
Clock to Pin 12
Clock to Pin 11
Clock to Pin 10
Clock to Pin 9
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
2.95
2.85
2.76
2.66
2.56
2.47
2.37
2.27
2.17
2.08
1.98
1.88
1.79
1.69
1.59
1.50
1.40
1.30
1.20
1.11
1.01
0.91
0.91
0.91
0.91
0.91
0.91
0.91
0.91
0.91
0.91
0.91
0.91
0.91
0.91
0.91
3.25
3.14
3.04
2.93
2.82
2.72
2.61
2.50
2.40
2.29
2.18
2.07
1.97
1.86
1.75
1.65
1.54
1.43
1.33
1.22
1.11
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
3.74
3.61
3.49
3.37
3.25
3.12
3.00
2.88
2.75
2.63
2.51
2.38
2.26
2.14
2.02
1.89
1.77
1.65
1.52
1.40
1.28
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
MULTCK_P35
MULTCK_P34
MULTCK_P33
MULTCK_P32
MULTCK_P31
MULTCK_P30
MULTCK_P29
MULTCK_P28
MULTCK_P27
MULTCK_P26
MULTCK_P25
MULTCK_P24
MULTCK_P23
MULTCK_P22
MULTCK_P21
MULTCK_P20
MULTCK_P19
MULTCK_P18
MULTCK_P17
MULTCK_P16
MULTCK_P15
MULTCK_P14
MULTCK_P13
MULTCK_P12
MULTCK_P11
MULTCK_P10
T
MULTCK_P9
MULTCK_P8
MULTCK_P7
MULTCK_P6
MULTCK_P5
MULTCK_P4
MULTCK_P3
MULTCK_P2
MULTCK_P1
MULTCK_P0
Clock to Pin 8
T
Clock to Pin 7
T
T
T
T
T
T
T
T
Clock to Pin 6
Clock to Pin 5
Clock to Pin 4
Clock to Pin 3
Clock to Pin 2
Clock to Pin 1
Clock to Pin 0
Module 3 of 4
24
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DS031-3 (v2.3) September 26, 2002
Advance Product Specification
R
Virtex-II 1.5V Field-Programmable Gate Arrays
Block SelectRAM Switching Characteristics
Table 28: Block SelectRAM Switching Characteristics
Speed Grade
Description
Sequential Delays
Symbol
– 6
– 5
– 4
Units
2.10
2.31
2.65
Clock CLK to DOUT output
Setup and Hold Times Before Clock CLK
ADDR inputs
T
ns, Max
BCKO
T
/T
0.29/ 0.00
0.29/ 0.00
0.95/–0.46
1.31/–0.71
0.57/–0.19
0.32/ 0.00
0.32/ 0.00
1.04/–0.50
1.44/–0.78
0.63/–0.21
0.36/ 0.00
0.36/ 0.00
1.20/–0.58
1.65/–0.90
0.72/–0.25
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
BACK BCKA
DIN inputs
T
T
T
/T
BDCK BCKD
EN input
/T
BECK BCKE
RST input
/T
BRCK BCKR
WEN input
T
/T
BWCK BCKW
Clock CLK
Minimum Pulse Width, High
Minimum Pulse Width, Low
T
1.17
1.17
1.29
1.29
1.48
1.48
ns, Min
ns, Min
BPWH
T
BPWL
TBUF Switching Characteristics
Table 29: TBUF Switching Characteristics
Speed Grade
Description
Combinatorial Delays
Symbol
– 6
– 5
– 4
Units
0.45
0.44
0.44
0.50
0.48
0.48
0.58
0.55
0.55
IN input to OUT output
T
ns, Max
ns, Max
ns, Max
IO
TRI input to OUT output high-impedance
TRI input to valid data on OUT output
T
OFF
T
ON
JTAG Test Access Port Switching Characteristics
Table 30: JTAG Test Access Port Switching Characteristics
Description
TMS and TDI Setup times before TCK
TMS and TDI Hold times after TCK
Output delay from clock TCK to output TDO
Maximum TCK clock frequency
Symbol
Units
T
5.5
0.0
ns, Min
ns, Min
TAPTK
T
TCKTAP
TCKTDO
T
10.0
33
ns, Max
MHz, Max
F
TCK
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Virtex-II 1.5V Field-Programmable Gate Arrays
Virtex-II Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted.
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, With DCM
Table 31: Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, With DCM
Speed Grade
Description
Symbol
Device
– 6
– 5
– 4
Units
LVTTL Global Clock Input to Output delay
using Output flip-flop, 12 mA, Fast Slew
Rate, with DCM.
For data output with different standards,
adjust the delays with the values shown in
IOB Output Switching Characteristics
Standard Adjustments, page 14.
XC2V40
XC2V80
2.19
2.19
2.19
2.19
2.19
2.19
2.19
2.28
2.28
2.73
TBD
2.40
2.40
2.40
2.40
2.40
2.40
2.40
2.50
2.50
3.00
TBD
2.76
2.76
2.76
2.76
2.76
2.76
2.76
2.88
2.88
3.45
TBD
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Global Clock and OFF with DCM
T
ICKOFDCM
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured with a 35 pF external capacitive load. The only time it is not 50% of V threshold is with LVCMOS. For
CC
other I/O standards and different loads, see Table 18.
3. DCM output jitter is included in the measurement.
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Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, Without DCM
Table 32: Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, Without DCM
Speed Grade
Description
Symbol
Device
– 6
– 5
– 4
Units
LVTTL Global Clock Input to Output Delay using
Output flip-flop, 12 mA, Fast Slew Rate, without
DCM.
For data output with different standards, adjust
the delays with the values shown in IOB Output
Switching Characteristics Standard
Adjustments, page 14.
XC2V40
XC2V80
4.28
4.28
4.50
4.50
5.10
5.10
5.20
5.23
5.55
6.00
TBD
4.70
4.70
5.00
5.00
5.40
5.40
5.55
5.76
6.11
6.50
TBD
4.98
4.98
5.75
5.75
5.90
5.90
6.38
6.62
7.02
7.22
TBD
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Global Clock and OFF without DCM
T
ICKOF
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at 50% V threshold with 35 pF external capacitive load. For other I/O standards and different loads, see
CC
Table 18.
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Virtex-II 1.5V Field-Programmable Gate Arrays
Virtex-II Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted.
Global Clock Setup and Hold for LVTTL Standard, With DCM
Table 33: Global Clock Setup and Hold for LVTTL Standard, With DCM
Speed Grade
Description
Symbol
Device
– 6
– 5
– 4
Units
Input Setup and Hold Time
Relative to Global Clock Input
Signal for LVTTL Standard.
For data input with different
standards, adjust the setup time
delay by the values shown in IOB
Input Switching
Characteristics Standard
Adjustments, page 11.
No Delay
XC2V40
XC2V80
1.60/–0.90
1.60/–0.90
1.60/–0.90
1.60/–0.90
1.60/–0.90
1.60/–0.90
1.70/–0.90
1.70/–0.90
1.70/–0.90
1.70/–0.90
TBD
1.60/–0.90
1.60/–0.90
1.60/–0.90
1.60/–0.90
1.60/–0.90
1.60/–0.90
1.70/–0.90
1.70/–0.90
1.70/–0.90
1.70/–0.90
TBD
1.84/–0.76
1.84/–0.76
1.84/–0.76
1.84/–0.76
1.84/–0.76
1.84/–0.76
1.96/–0.76
1.96/–0.76
1.96/–0.76
1.96/–0.76
TBD
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
T
/T
PSDCM PHDCM
Global Clock and IFF with DCM
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
Notes:
1. IFF = Input Flip-Flop or Latch
2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
3. DCM output jitter is included in the measurement.
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Virtex-II 1.5V Field-Programmable Gate Arrays
Global Clock Setup and Hold for LVTTL Standard, Without DCM
,
Table 34: Global Clock Setup and Hold for LVTTL Standard, Without DCM
Speed Grade
– 5
Description
Symbol
Device
– 6
– 4
Units
Input Setup and Hold Time
Relative to Global Clock Input
(2)
Signal for LVTTL Standard.
For data input with different
standards, adjust the setup time
delay by the values shown in IOB
InputSwitching Characteristics
Standard Adjustments,
page 11.
XC2V40
XC2V80
1.92/ 0.00
2.10/ 0.00
1.92/ 0.00
1.92/ 0.00
1.92/ 0.00
1.92/ 0.00
1.92/ 0.00
1.92/ 0.00
2.00/ 0.00
1.92/ 0.50
TBD
1.92/ 0.00
2.10/ 0.00
1.92/ 0.00
1.92/ 0.00
1.92/ 0.00
1.92/ 0.00
1.92/ 0.00
1.92/ 0.00
2.00/ 0.00
1.92/ 0.50
TBD
2.21/ 0.00
2.21/ 0.00
2.21/ 0.00
2.21/ 0.00
2.21/ 0.00
2.21/ 0.00
2.21/ 0.00
2.21/ 0.00
2.30/ 0.00
2.21/ 0.50
TBD
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Full Delay
T
/T
PSFD PHFD
(1)
Global Clock and IFF without
DCM
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
Notes:
1. IFF = Input Flip-Flop or Latch
2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
3. These values are parametrically measured.
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Virtex-II 1.5V Field-Programmable Gate Arrays
DCM Timing Parameters
All devices are 100% functionally tested. Because of the dif-
ficulty in directly measuring many internal timing parame-
ters, those parameters are derived from benchmark timing
patterns. The following guidelines reflect worst-case values
across the recommended operating conditions. All output
jitter and phase specifications are determined through sta-
tistical measurement at the package pins.
Operating Frequency Ranges
e
Table 35: Operating Frequency Ranges
Speed Grade
– 6
– 4
Description
Symbol
Constraints
– 5
Units
Output Clocks (Low Frequency Mode)
CLK0, CLK90, CLK180, CLK270
CLK2X, CLK2X180
CLKOUT_FREQ_1X_LF_Min
CLKOUT_FREQ_1X_LF_Max
CLKOUT_FREQ_2X_LF_Min
CLKOUT_FREQ_2X_LF_Max
CLKOUT_FREQ_DV_LF_Min
CLKOUT_FREQ_DV_LF_Max
CLKOUT_FREQ_FX_LF_Min
CLKOUT_FREQ_FX_LF_Max
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
24.00
230.00
48.00
450.00
1.50
24.00
210.00
48.00
420.00
1.50
24.00
180.00
48.00
360.00
1.50
CLKDV
150.00
24.00
260.00
140.00
24.00
240.00
120.00
24.00
210.00
CLKFX, CLKFX180
Input Clocks (Low Frequency Mode)
(1), (3)
CLKIN (using DLL outputs)
CLKIN_FREQ_DLL_LF_Min
CLKIN_FREQ_DLL_LF_Max
CLKIN_FREQ_FX_LF_Min
CLKIN_FREQ_FX_LF_Max
PSCLK_FREQ_LF_Min
MHz
MHz
MHz
MHz
MHz
MHz
24.00
230.00
1.00
24.00
210.00
1.00
24.00
180.00
1.00
(2), (3)
CLKIN (using CLKFX outputs)
260.00
0.01
240.00
0.01
210.00
0.01
PSCLK
PSCLK_FREQ_LF_Max
450.00
420.00
360.00
Output Clocks (High Frequency Mode)
CLK0, CLK180
CLKOUT_FREQ_1X_HF_Min
MHz
MHz
MHz
MHz
MHz
MHz
48.00
450.00
3.00
48.00
420.00
3.00
48.00
360.00
3.00
CLKOUT_FREQ_1X_HF_Max
CLKOUT_FREQ_DV_HF_Min
CLKOUT_FREQ_DV_HF_Max
CLKOUT_FREQ_FX_HF_Min
CLKOUT_FREQ_FX_HF_Max
CLKDV
300.00
210.00
350.00
280.00
210.00
320.00
240.00
210.00
270.00
CLKFX, CLKFX180
Input Clocks (High Frequency Mode)
(1), (3)
CLKIN (using DLL outputs)
CLKIN_FREQ_DLL_HF_Min
CLKIN_FREQ_DLL_HF_Max
CLKIN_FRQ_FX_HF_Min
CLKIN_FRQ_FX_HF_Max
PSCLK_FREQ_HF_Min
MHz
MHz
MHz
MHz
MHz
MHz
48.00
450.00
50.00
350.00
0.01
48.00
420.00
50.00
320.00
0.01
48.00
360.00
50.00
270.00
0.01
(2), (3)
CLKIN (using CLKFX outputs)
PSCLK
PSCLK_FREQ_HF_Max
450.00
420.00
360.00
Notes:
1. “DLL outputs” is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. If both DLL and CLKFX outputs are used, follow the more restrictive specification.
3. If the CLKIN_DIVIDE_BY_2 attribute of the DCM is used, then double these values.
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Input Clock Tolerances
Table 36: Input Clock Tolerances
Speed Grade
– 6
– 5
– 4
Constraints
FCLKIN
Description
Symbol
Min
Max
Min
Max
Min
Max
Units
Input Clock Low/high Pulse Width
PSCLK
PSCLK_PULSE
< 1MHz
25.00
25.00
10.00
5.00
3.00
2.40
2.00
1.80
1.50
1.30
1.15
1.05
25.00
25.00
10.00
5.00
3.00
2.40
2.00
1.80
1.50
1.30
1.15
1.05
25.00
25.00
10.00
5.00
3.00
2.40
2.00
1.80
1.50
1.30
1.15
1.05
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1 – 10 MHz
10 – 25 MHz
25 – 50 MHz
50 – 100 MHz
100 – 150 MHz
150 – 200 MHz
200 – 250 MHz
250 – 300 MHz
300 – 350 MHz
350 – 400 MHz
> 400 MHz
PSCLK_PULSE and
CLKIN_PULSE
PSCLK and CLKIN(2)
Input Clock Cycle-Cycle Jitter (Low Frequency Mode)
CLKIN (using DLL outputs)(1)
CLKIN_CYC_JITT_DLL_LF
CLKIN_CYC_JITT_FX_LF
±300
±300
±300
±300
±300
±300
ps
ps
CLKIN (using CLKFX outputs)(2)
Input Clock Cycle-Cycle Jitter (High Frequency Mode)
CLKIN (using DLL outputs)(1)
CLKIN_CYC_JITT_DLL_HF
CLKIN_CYC_JITT_FX_HF
±150
±150
±150
±150
±150
±150
ps
ps
CLKIN (using CLKFX outputs)(2)
Input Clock Period Jitter (Low Frequency Mode)
CLKIN (using DLL outputs)(1)
CLKIN_PER_JITT_DLL_LF
CLKIN_PER_JITT_FX_LF
±1
±1
±1
±1
±1
±1
ns
ns
CLKIN (using CLKFX outputs)(2)
Input Clock Period Jitter (High Frequency Mode)
CLKIN (using DLL outputs)(1)
CLKIN_PER_JITT_DLL_HF
CLKIN_PER_JITT_FX_HF
±1
±1
±1
±1
±1
±1
ns
ns
CLKIN (using CLKFX outputs)(2)
Feedback Clock Path Delay Variation
CLKFB off-chip feedback
CLKFB_DELAY_VAR_EXT
±1
±1
±1
ns
Notes:
1. “”DLL outputs” is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. If both DLL and CLKFX outputs are used, follow the more restrictive specification.
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Output Clock Jitter
Table 37: Output Clock Jitter
Speed Grade
– 5
– 6
– 4
Description
Clock Synthesis Period Jitter
CLK0
Symbol
Constraints
Units
CLKOUT_PER_JITT_0
CLKOUT_PER_JITT_90
CLKOUT_PER_JITT_180
CLKOUT_PER_JITT_270
CLKOUT_PER_JITT_2X
CLKOUT_PER_JITT_DV1
CLKOUT_PER_JITT_DV2
CLKOUT_PER_JITT_FX
ps
±100
±150
±150
±150
±200
±150
±300
±100
±150
±150
±150
±200
±150
±300
±100
±150
±150
±150
±200
±150
±300
CLK90
ps
ps
ps
ps
ps
ps
ps
CLK180
CLK270
CLK2X, CLK2X180
CLKDV (integer division)
CLKDV (non-integer division)
CLKFX, CLKFX180
Note 1 Note 1 Note 1
Notes:
1. Values for this parameter are available at www.xilinx.com.
Output Clock Phase Alignment
Table 38: Output Clock Phase Alignment
Speed Grade
– 6
– 4
Description
Symbol
Constraints
– 5
Units
Phase Offset Between CLKIN and CLKFB
CLKIN/CLKFB
CLKIN_CLKFB_PHASE
ps
ps
±50
±140
±50
±140
±50
Phase Offset Between Any DCM Outputs
All CLK* outputs
CLKOUT_PHASE
±140
Duty Cycle Precision
(1)
DLL outputs
CLKOUT_DUTY_CYCLE_DLL
CLKOUT_DUTY_CYCLE_FX
ps
ps
±150
±100
±150
±100
±150
±100
CLKFX outputs
Notes:
1. “”DLL outputs” is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. Specification also applies to PSCLK.
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Miscellaneous Timing Parameters
Table 39: Miscellaneous Timing Parameters
Constraints
Description
Symbol
F
Speed Grade
– 5
Units
CLKIN
– 6
– 4
Time Required to Achieve LOCK
(1)
Using DLL outputs
LOCK_DLL
µs
µs
µs
µs
µs
ms
ms
20.0
25.0
50.0
90.0
120.0
10.0
10.0
20.0
25.0
50.0
90.0
120.0
10.0
10.0
20.0
25.0
50.0
90.0
120.0
10.0
10.0
LOCK_DLL_60
> 60MHz
LOCK_DLL_50_60
LOCK_DLL_40_50
LOCK_DLL_30_40
LOCK_DLL_24_30
LOCK_FX_MIN
50 - 60 MHz
40 - 50 MHz
30 - 40 MHz
24 - 30 MHz
Using CLKFX outputs
LOCK_FX_MAX
Additional lock time with
fine-phase shifting
50.0
50.0
50.0
µs
LOCK_DLL_FINE_SHIFT
Fine-Phase Shifting
Absolute shifting range
Delay Lines
ns
10.0
10.0
10.0
FINE_SHIFT_RANGE
Tap delay resolution
ps
ps
DCM_TAP_MIN
DCM_TAP_MAX
30.0
60.0
30.0
60.0
30.0
60.0
Notes:
1. “”DLL outputs” is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. Specification also applies to PSCLK.
Frequency Synthesis
Table 40: Frequency Synthesis
Attribute
Min
2
Max
32
CLKFX_MULTIPLY
CLKFX_DIVIDE
1
32
Parameter Cross Reference
Table 41: Parameter Cross Reference
Libraries Guide
Data Sheet
DLL_CLKOUT_{MIN|MAX}_LF
DFS_CLKOUT_{MIN|MAX}_LF
DLL_CLKIN_{MIN|MAX}_LF
DFS_CLKIN_{MIN|MAX}_LF
DLL_CLKOUT_{MIN|MAX}_HF
DFS_CLKOUT_{MIN|MAX}_HF
DLL_CLKIN_{MIN|MAX}_HF
DFS_CLKIN_{MIN|MAX}_HF
CLKOUT_FREQ_{1X|2X|DV}_LF
CLKOUT_FREQ_FX_LF
CLKIN_FREQ_DLL_LF
CLKIN_FREQ_FX_LF
CLKOUT_FREQ_{1X|DV}_HF
CLKOUT_FREQ_FX_HF
CLKIN_FREQ_DLL_HF
CLKIN_FREQ_FX_HF
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Virtex-II 1.5V Field-Programmable Gate Arrays
Source-Synchronous Switching Characteristics
The parameters in this section provide the necessary values for calculating timing budgets for Virtex-II source-synchronous
transmitter and receiver data-valid windows.
Table 42: Duty Cycle Distortion and Clock-Tree Skew
Speed Grade
Description
Symbol
Device
All
– 6
140
50
– 5
140
50
– 4
140
50
Units
ps
(1)
Duty Cycle Distortion
T
DCD_CLK0
T
All
ps
DCD_CLK180
(2)
Clock Tree Skew
XC2V40
XC2V80
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
50
ps
T
CKSKEW
50
ps
50
ps
50
ps
80
ps
80
ps
100
100
TBD
500
TBD
ps
ps
ps
ps
TBD
TBD
ps
Notes:
1. These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For
cases where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused
by asymmetrical rise/fall times.
T
T
applies to cases where local (IOB) inversion is used to provide the negative-edge clock to the DDR element in the I/O.
DCD_CLK0
applies to cases where the CLK180 output of the DCM is used to provide the negative-edge clock to the DDR element
DCD_CLK180
in the I/O.
2. This value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew
exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor
and Timing Analyzer tools to evaluate clock skew specific to your application.
Table 43: Package Skew
Description
Symbol
Device/Package
XC2V1000 / FF896
XC2V3000 / FF1152
XC2V3000 / BF957
XC2V4000 / FF1152
XC2V4000 / FF1517
XC2V4000 / BF957
XC2V6000 / FF1152
XC2V6000 / FF1517
XC2V6000 / BF957
Value
130
115
130
130
200
140
90
Units
ps
(1)
Package Skew
T
PKGSKEW
ps
ps
ps
ps
ps
ps
105
105
ps
ps
Notes:
1. These values represent the worst-case skew between any two balls of the package: shortest flight time to longest flight time from Pad
to Ball (7.1ps per mm).
2. Package trace length information is available for these device/package combinations. This information can be used to deskew the
package.
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Speed Grade
Table 44: Sample Window
Description
Symbol
Device
XC2V40
– 6
– 5
500
500
500
500
500
500
500
500
500
500
TBD
– 4
Units
ps
(1)
Sampling Error at Receiver Pins
T
SAMP
XC2V80
ps
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
ps
ps
ps
ps
ps
ps
ps
ps
TBD
TBD
ps
Notes:
1. This parameter indicates the total sampling error of Virtex-II DDR input registers across voltage, temperature, and process. The
characterization methodology uses the DCM to capture the DDR input registers’ edges of operation. These measurements include:
- CLK0 and CLK180 DCM jitter
- Worst-case Duty-Cycle Distortion - T
- DCM accuracy (phase offset)
- DCM phase shift resolution.
DCD_CLK180
These measurements do not include package or clock tree skew.
Table 45: Pin-to-Pin Setup/Hold: Source-Synchronous Configuration
Speed Grade
– 5
Description
Symbol
Device
– 6
– 4
Units
Data Input Set-Up and Hold Times Relative to a Forwarded
Clock Input Pin, Using DCM and Global Clock Buffer.
For situations where clock and data inputs conform to
different standards, adjust the setup and hold values
accordingly using the values shown in IOB Input Switching
Characteristics Standard Adjustments, page 11.
No Delay
XC2V40
XC2V80
TBD
TBD
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
T
XXX
Global Clock and IFF with DCM
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
TBD
TBD
0.2/0.5
TBD
TBD
0.2/0.5
TBD
0.2/0.6
TBD
TBD
TBD
Notes:
1. IFF = Input Flip-Flop
2. The timing values were measured using the fine-phase adjustment feature of the DCM.
3. The worst-case duty-cycle distortion and DCM jitter on CLK0 and CLK180 is included in these measurements.
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Virtex-II 1.5V Field-Programmable Gate Arrays
Source Synchronous Timing Budgets
This section describes how to use the parameters provided in the Source-Synchronous Switching Characteristics
section to develop system-specific timing budgets. The following analysis provides information necessary for determining
Virtex-II contributions to an overall system timing analysis; no assumptions are made about the effects of Inter-Symbol
Interference or PCB skew.
Virtex-II Transmitter Data-Valid Window (TX)
is the minimum aggregate valid data period for a
Virtex-II Receiver Data-Valid Window (RX)
T
R is the required minimum aggregate valid data period for
X
X
source-synchronous data bus at the pins of the device and
is calculated as follows:
a source-synchronous data bus at the pins of the device
and is calculated as follows:
(1)
(2)
(1)
(2)
(3)
T = Data Period - [Jitter + Duty Cycle Distortion
+
R = [TSAMP + TCKSKEW + TPKGSKEW
]
X
X
(3)
(4)
TCKSKEW + TPKGSKEW
]
Notes:
Notes:
1. This parameter indicates the total sampling error of Virtex-II
DDR input registers across voltage, temperature, and
process. The characterization methodology uses the DCM to
capture the DDR input registers’ edges of operation. These
measurements include:
1. Jitter values and accumulation methodology to be provided in
a future release of this document. The absolute period jitter
values found in the DCM Timing Parameters section of the
particular DCM output clock used to clock the IOB FF can be
used for a best case analysis.
2. This value depends on the clocking methodology used. See
Note1 for Table 42.
3. This value represents the worst-case clock-tree skew
observable between sequential I/O elements. Significantly
less clock-tree skew exists for I/O registers that are close to
each other and fed by the same or adjacent clock-tree
branches. Use the Xilinx FPGA_Editor and Timing Analyzer
tools to evaluate clock skew specific to your application.
4. These values represent the worst-case skew between any two
balls of the package: shortest flight time to longest flight time
from Pad to Ball.
-
-
-
-
CLK0 and CLK180 DCM jitter in a quiet system
Worst-case duty-cycle distortion
DCM accuracy (phase offset)
DCM phase shift resolution.
These measurements do not include package or clock tree
skew.
2. This value represents the worst-case clock-tree skew
observable between sequential I/O elements. Significantly
less clock-tree skew exists for I/O registers that are close to
each other and fed by the same or adjacent clock-tree
branches. Use the Xilinx FPGA_Editor and Timing Analyzer
tools to evaluate clock skew specific to your application.
3. These values represent the worst-case skew between any two
balls of the package: shortest flight time to longest flight time
from Pad to Ball.
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Virtex-II 1.5V Field-Programmable Gate Arrays
Revision History
This section records the change history for this module of the data sheet.
Date
Version
1.0
Revision
11/07/00
12/06/00
01/15/01
Early access draft.
Initial release.
1.1
1.2
Added values to the tables in the Virtex-II Performance Characteristics and Virtex-II
Switching Characteristics sections.
•
The data sheet was divided into four modules (per the current style standard).
01/25/01
1.3
1.5
•
Updated values in the Virtex-II Performance Characteristics and Virtex-II Switching
Characteristics tables.
•
•
Table 18, “Delay Measurement Methodology,” on page 17
Updated values in the Virtex-II Performance Characteristics and Virtex-II Switching
Characteristics tables.
04/23/01
•
Added T
symbol to Table 23.
REG32
•
•
Skipped v1.4 to sync with other modules. Reverted to traditional double-column format.
Updated values in the Virtex-II Performance Characteristics and Virtex-II Switching
Characteristics tables.
07/30/01
10/02/01
1.6
1.7
•
Added values to the Virtex-II Pin-to-Pin Output Parameter Guidelines and Virtex-II
Pin-to-Pin Input Parameter Guidelines tables.
•
•
Added Frequency Synthesis table.
Updated values in the Virtex-II Performance Characteristics and Virtex-II Switching
Characteristics tables.
•
Updated the speed grade designations used in data sheets, and added Table 13, which
shows the current speed grade designation for each device.
•
•
Corrected the speed grade designation for the XC2V1000 device in Table 13.
10/05/01
10/12/01
1.8
1.9
Updated values in the Virtex-II Performance Characteristics and Virtex-II Switching
Characteristics tables.
•
•
Updated values in Table 3, Table 4, Table 5, Virtex-II Performance Characteristics,
and Virtex-II Switching Characteristics tables.
Updated values in Virtex-II Performance Characteristics and Virtex-II Switching
Characteristics tables, based on values extracted from speeds file version 1.96.
11/28/01
01/03/02
2.0
2.1
•
•
•
Changed the speed grade designation for the XC2V6000 device in Table 13.
Updated values in Table 4, "Quiescent Supply Current."
07/16/02
09/26/02
2.2
2.3
Updated values in Virtex-II Performance Characteristics and Virtex-II Switching
Characteristics tables, based on values extracted from speeds file version 1.111.
•
•
Added Enhanced Multiplier Switching Characteristics section.
Added footnote to Table 34, "Global Clock Setup and Hold for LVTTL Standard,
Without DCM."
•
•
•
Added Source-Synchronous Switching Characteristics section.
Removed mention of MIL-M-38510/605 specification.
Added footnotes to Table 2 and Table 6.
Virtex-II Data Sheet
The Virtex-II Data Sheet contains the following modules:
•
DS031-1, Virtex-II 1.5V FPGAs: Introduction and
Ordering Information (Module 1)
•
•
DS031-3, Virtex-II 1.5V FPGAs: DC and Switching
Characteristics (Module 3)
•
DS031-2, Virtex-II 1.5V FPGAs: Functional Description
(Module 2)
DS031-4, Virtex-II 1.5V FPGAs: Pinout Tables
(Module 4)
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0
Virtex-II 1.5V
R
Field-Programmable Gate Arrays
Pinout Information
0
0
DS031-4 (v1.8) October 7, 2002
Advance Product Specification
This document provides Virtex™-II Device/Package Combinations and Maximum I/Os Available and Virtex-II Pin
Definitions, followed by pinout tables for the following packages:
•
•
•
•
•
CS144 Chip-Scale BGA Package
FG256 Fine-Pitch BGA Package
FG456 Fine-Pitch BGA Package
FG676 Fine-Pitch BGA Package
BG575 Standard BGA Package
•
•
•
•
•
BG728 Standard BGA Package
FF896 Flip-Chip Fine-Pitch BGA Package
FF1152 Flip-Chip Fine-Pitch BGA Package
FF1517 Flip-Chip Fine-Pitch BGA Package
BF957 Flip-Chip BGA Package
•
CS denotes wire-bond chip-scale ball grid array (BGA)
(0.80 mm pitch).
Virtex™-II Device/Package
Combinations and Maximum I/Os
Available
Wire-bond and flip-chip packages are available. Table 1 and
Table 2 show the maximum number of user I/Os possible in
wire-bond and flip-chip packages, respectively.
•
•
•
•
FG denotes wire-bond fine-pitch BGA (1.00 mm pitch).
FF denotes flip-chip fine-pitch BGA (1.00 mm pitch).
BG denotes standard BGA (1.27 mm pitch).
BF denotes flip-chip BGA (1.27 mm pitch).
The number of I/Os per package include all user I/Os except
the 15 control pins (CCLK, DONE, M0, M1, M2, PROG_B,
PWRDWN_B, TCK, TDI, TDO, TMS, HSWAP_EN, DXN,
DXP, AND RSVD).
Table 3 shows the number of user I/Os available for all
device/package combinations.
Table 1: Wire-Bond Packages Information
Package
Pitch (mm)
CS144
0.80
FG256
1.00
FG456
1.00
FG676
1.00
BG575
1.27
BG728
1.27
Size (mm)
I/Os
12 x 12
92
17 x 17
172
23 x 23
324
27 x 27
484
31 x 31
408
35 x 35
516
Table 2: Flip-Chip Packages Information
Package
Pitch (mm)
FF896
1.00
FF1152
FF1517
BF957
1.00
35 x 35
824
1.00
40 x 40
1,108
1.27
40 x 40
684
Size (mm)
I/Os
31 x 31
624
© 2001-2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 3: Virtex-II Device/Package Combinations and Maximum Number of Available I/Os
Available I/Os
XC2V
40
XC2V
80
XC2V
250
XC2V
500
XC2V
1000
XC2V
1500
XC2V
2000
XC2V
3000
XC2V
4000
XC2V
6000
XC2V
8000
Package
CS144
FG256
FG456
FG676
FF896
88
88
-
92
92
-
-
-
-
-
-
-
-
120
172
172
172
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
200
264
324
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
392
456
624
-
484
-
-
-
-
-
-
432
528
-
824
1,104
-
-
FF1152
FF1517
BG575
BG728
BF957
-
-
-
720
-
824
912
-
824
-
-
-
-
1,108
-
328
392
408
-
-
-
-
-
-
-
-
-
-
516
684
-
-
-
624
684
684
All of the devices supported in a particular package are
pinout compatible and are listed in the same table (one
table per package). In addition, the FG456 and FG676
packages are compatible, as are the FF896 and FF1152
packages. Pins that are not available for the smallest
devices are listed in right-hand columns.
Virtex-II Pin Definitions
This section describes the pinouts for Virtex-II devices in the
following packages:
•
•
•
CS144: wire-bond chip-scale ball grid array (BGA) of
0.80 mm pitch
FG256, FG456, and FG676: wire-bond fine-pitch BGA
of 1.00 mm pitch
Each device is split into eight I/O banks to allow for flexibility
in the choice of I/O standards (see the Virtex-II Data Sheet).
Global pins, including JTAG, configuration, and
power/ground pins, are listed at the end of each table.
Table 4 provides definitions for all pin types.
FF896, FF1152, FF1517: flip-chip fine-pitch BGA of
1.00 mm pitch
•
•
BG575 and BG728: wire-bond BGA of 1.27 mm pitch
BF957: flip-chip BGA of 1.27 mm pitch
The FG256 pinouts (Table 6) is included as an example. All
Virtex-II pinout tables are available on the distribution
CD-ROM, or on the web (at http://www.xilinx.com).
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Pin Definitions
Table 4 provides a description of each pin type listed in Virtex-II pinout tables.
Table 4: Virtex-II Pin Definitions
Pin Name
User I/O Pins
IO_LXXY_#
Direction
Description
Input/Output All user I/O pins are capable of differential signalling and can implement LVDS, ULVDS,
BLVDS, LVPECL, or LDT pairs. Each user I/O is labeled “IO_LXXY_#”, where:
IO indicates a user I/O pin.
LXXY indicates a differential pair, with XX a unique pair in the bank and Y = P/N for
the positive and negative sides of the differential pair.
# indicates the bank number (0 through 7)
Dual-Function Pins
IO_LXXY_#/ZZZ
The dual-function pins are labelled “IO_LXXY_#/ZZZ”, where ZZZ can be one of the
following pins:
Per Bank - VRP, VRN, or VREF
Globally - GCLKX(S/P), BUSY/DOUT, INIT_B, DIN/D0 – D7, RDWR_B, or CS_B
With /ZZZ:
DIN / D0, D1, D2, Input/Output In SelectMAP mode, D0 through D7 are configuration data pins. These pins become
D3, D4, D5, D6,
D7
user I/Os after configuration, unless the SelectMAP port is retained.
In bit-serial modes, DIN (D0) is the single-data input. This pin becomes a user I/O after
configuration.
CS_B
Input
In SelectMAP mode, this is the active-low Chip Select signal. The pin becomes a user
I/O after configuration, unless the SelectMAP port is retained.
RDWR_B
BUSY/DOUT
Input
In SelectMAP mode, this is the active-low Write Enable signal. The pin becomes a user
I/O after configuration, unless the SelectMAP port is retained.
Output
In SelectMAP mode, BUSY controls the rate at which configuration data is loaded. The
pin becomes a user I/O after configuration, unless the SelectMAP port is retained.
In bit-serial modes, DOUT provides preamble and configuration data to downstream
devices in a daisy-chain. The pin becomes a user I/O after configuration.
INIT_B
Bidirectional When Low, this pin indicates that the configuration memory is being cleared. When held
(open-drain) Low, the start of configuration is delayed. During configuration, a Low on this output
indicates that a configuration data error has occurred. The pin becomes a user I/O after
configuration.
GCLKx (S/P)
Input
These are clock input pins that connect to Global Clock Buffers. These pins become
regular user I/Os when not needed for clocks.
VRP
Input
Input
Input
Input
Input
This pin is for the DCI voltage reference resistor of P transistor (per bank).
This pin is for the DCI voltage reference resistor of N transistor (per bank).
This is the alternative pin for the DCI voltage reference resistor of P transistor.
This is the alternative pin for the DCI voltage reference resistor of N transistor.
VRN
ALT_VRP
ALT_VRN
V
These are input threshold voltage pins. They become user I/Os when an external
threshold voltage is not needed (per bank).
REF
Dedicated Pins(1)
CCLK
Input/Output Configuration clock. Output in Master mode or Input in Slave mode.
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 4: Virtex-II Pin Definitions (Continued)
Pin Name
PROG_B
Direction
Input
Description
Active Low asynchronous reset to configuration logic. This pin has a permanent weak
pull-up resistor.
DONE
Input/Output DONE is a bidirectional signal with an optional internal pull-up resistor. As an output,
this pin indicates completion of the configuration process. As an input, a Low level on
DONE can be configured to delay the start-up sequence.
M2, M1, M0
HSWAP_EN
TCK
Input
Input
Input
Input
Output
Input
Input
Configuration mode selection.
Enable I/O pullups during configuration.
Boundary Scan Clock.
TDI
Boundary Scan Data Input.
Boundary Scan Data Output.
Boundary Scan Mode Select.
Power down pin.
TDO
TMS
PWRDWN_B
Other Pins
DXN, DXP
N/A
Temperature-sensing diode pins (Anode: DXP, Cathode: DXN).
Decryptor key memory backup supply. (Do not connect if battery is not used.)
Reserved pin - do not connect.
V
Input
N/A
BATT
RSVD
V
V
V
Input
Input
Input
Input
Power-supply pins for the output drivers (per bank).
Power-supply pins for auxiliary circuits.
CCO
CCAUX
CCINT
Power-supply pins for the internal core logic.
Ground.
GND
Notes:
1. All dedicated pins (JTAG and configuration) are powered by V
(independent of the bank V
voltage).
CCO
CCAUX
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
CS144 Chip-Scale BGA Package
As shown in Table 5, XC2V40, XC2V80, and XC2V250 Virtex-II devices are available in the CS144 package. Pins in the
XC2V40, XC2V80, and XC2V250 devices are the same except for pin differences in the XC2V40 device, shown in the No
Connect column. Following this table are the CS144 Chip-Scale BGA Package Specifications (0.80mm pitch).
Table 5: CS144 — XC2V40, XC2V80, and XC2V250
Bank
Pin Description
IO_L01N_0
Pin Number
No Connect in the XC2V40
0
0
0
0
0
0
0
0
0
0
0
0
B3
A3
C4
B4
A4
D5
A5
D6
C6
B6
A6
D7
IO_L01P_0
IO_L02N_0
IO_L02P_0
IO_L03N_0/VRP_0
IO_L03P_0/VRN_0
IO_L94N_0/VREF_0
IO_L94P_0
IO_L95N_0/GCLK7P
IO_L95P_0/GCLK6S
IO_L96N_0/GCLK5P
IO_L96P_0/GCLK4S
1
1
1
1
1
1
1
1
1
1
1
1
IO_L96N_1/GCLK3P
IO_L96P_1/GCLK2S
IO_L95N_1/GCLK1P
IO_L95P_1/GCLK0S
IO_L94N_1
A7
B7
A8
B8
C8
IO_L94P_1/VREF_1
IO_L03N_1/VRP_1
IO_L03P_1/VRN_1
IO_L02N_1
D8
C9
D9
A10
B10
C10
D10
IO_L02P_1
IO_L01N_1
IO_L01P_1
2
2
2
2
2
2
2
2
2
2
IO_L01N_2
IO_L01P_2
C13
D11
D12
D13
E10
E11
E13
F11
F12
G10
IO_L02N_2/VRP_2
IO_L02P_2/VRN_2
IO_L03N_2
IO_L03P_2/VREF_2
IO_L93N_2
NC
NC
IO_L93P_2/VREF_2
IO_L94N_2
IO_L94P_2
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Table 5: CS144 — XC2V40, XC2V80, and XC2V250
Bank
Pin Description
IO_L96N_2
Pin Number
G11
No Connect in the XC2V40
2
2
IO_L96P_2
G13
3
3
3
3
3
3
3
3
3
3
IO_L96N_3
IO_L96P_3
G12
H12
H11
J13
IO_L94N_3
IO_L94P_3
IO_L03N_3/VREF_3
IO_L03P_3
J10
K13
K12
K11
K10
L13
IO_L02N_3/VRP_3
IO_L02P_3/VRN_3
IO_L01N_3
IO_L01P_3
4
4
4
4
4
4
4
4
4
4
4
4
IO_L01N_4/DOUT
IO_L01P_4/INIT_B
IO_L02N_4/D0
M11
N11
L10
M10
N10
K9
IO_L02P_4/D1
IO_L03N_4/D2/ALT_VRP_4
IO_L03P_4/D3/ALT_VRN_4
IO_L94N_4/VREF_4
IO_L94P_4
N9
K8
IO_L95N_4/GCLK3S
IO_L95P_4/GCLK2P
IO_L96N_4/GCLK1S
IO_L96P_4/GCLK0P
L8
M8
N8
K7
5
5
5
5
5
5
5
5
5
5
5
5
IO_L96N_5/GCLK7S
IO_L96P_5/GCLK6P
IO_L95N_5/GCLK5S
IO_L95P_5/GCLK4P
IO_L94N_5
N7
M7
N6
M6
L6
IO_L94P_5/VREF_5
IO_L03N_5/D4/ALT_VRP_5
IO_L03P_5/D5/ALT_VRN_5
IO_L02N_5/D6
K6
L5
K5
N4
M4
L4
IO_L02P_5/D7
IO_L01N_5/RDWR_B
IO_L01P_5/CS_B
K4
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 5: CS144 — XC2V40, XC2V80, and XC2V250
Bank
Pin Description
IO_L01P_6
Pin Number
No Connect in the XC2V40
6
6
6
6
6
6
6
6
6
6
L3
L2
L1
K3
K2
K1
J2
IO_L01N_6
IO_L02P_6/VRN_6
IO_L02N_6/VRP_6
IO_L03P_6
IO_L03N_6/VREF_6
IO_L94P_6
IO_L94N_6
H4
H3
H1
IO_L96P_6
IO_L96N_6
7
7
7
7
7
7
7
7
7
7
7
7
IO_L96P_7
IO_L96N_7
G4
G3
G1
F1
F2
F4
E2
E3
E4
D1
D2
D3
IO_L94P_7
IO_L94N_7
IO_L93P_7/VREF_7
IO_L93N_7
NC
NC
IO_L03P_7/VREF_7
IO_L03N_7
IO_L02P_7/VRN_7
IO_L02N_7/VRP_7
IO_L01P_7
IO_L01N_7
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
VCCO_0
VCCO_0
VCCO_1
VCCO_1
VCCO_2
VCCO_2
VCCO_3
VCCO_3
VCCO_4
VCCO_4
VCCO_5
VCCO_5
VCCO_6
VCCO_6
VCCO_7
VCCO_7
B5
C3
A11
A9
F10
C12
L12
J12
M9
L11
N3
N5
J3
M1
D4
F3
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 5: CS144 — XC2V40, XC2V80, and XC2V250
Bank
Pin Description
Pin Number
No Connect in the XC2V40
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
CCLK
PROG_B
DONE
M0
M13
B1
N12
N2
M1
M2
M2
M3
TCK
B12
C1
TDI
TDO
C11
A13
M12
A1
TMS
PWRDWN_B
HSWAP_EN
RSVD
RSVD
VBATT
RSVD
A2
B2
A12
B11
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
GND
C2
N1
N13
B13
H2
L7
H13
C7
E1
GND
G2
J1
GND
GND
J4
GND
M5
L9
GND
GND
J11
H10
F13
E12
B9
GND
GND
GND
GND
GND
C5
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
CS144 Chip-Scale BGA Package Specifications (0.80mm pitch)
Figure 1: CS144 Chip-Scale BGA Package Specifications
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
FG256 Fine-Pitch BGA Package
As shown in Table 6, XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000 Virtex-II devices are available in the FG256
fine-pitch BGA package. The pins in the XC2V250, XC2V500, and XC2V1000 devices are same. The No Connect columns
show pin differences for the XC2V40 and XC2V80 devices. Following this table are the FG256 Fine-Pitch BGA Package
Specifications (1.00mm pitch).
Table 6: FG256 BGA — XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000
Bank
0
Pin Description
IO_L01N_0
Pin Number
C4
No Connect in XC2V40 No Connect in XC2V80
0
IO_L01P_0
B4
0
IO_L02N_0
D5
0
IO_L02P_0
C5
0
IO_L03N_0/VRP_0
IO_L03P_0/VRN_0
IO_L04N_0/VREF_0
IO_L04P_0
B5
0
A5
0
D6
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
0
C6
0
IO_L05N_0
B6
0
IO_L05P_0
A6
0
IO_L92N_0
E6
0
IO_L92P_0
E7
0
IO_L93N_0
D7
0
IO_L93P_0
C7
0
IO_L94N_0/VREF_0
IO_L94P_0
B7
0
A7
0
IO_L95N_0/GCLK7P
IO_L95P_0/GCLK6S
IO_L96N_0/GCLK5P
IO_L96P_0/GCLK4S
D8
0
C8
0
B8
0
A8
1
1
1
1
1
1
1
1
1
IO_L96N_1/GCLK3P
IO_L96P_1/GCLK2S
IO_L95N_1/GCLK1P
IO_L95P_1/GCLK0S
IO_L94N_1
A9
B9
C9
D9
A10
B10
C10
D10
E10
IO_L94P_1/VREF_1
IO_L93N_1
NC
NC
NC
NC
NC
NC
IO_L93P_1
IO_L92N_1
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 6: FG256 BGA — XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000
Bank
Pin Description
IO_L92P_1
Pin Number
E11
No Connect in XC2V40 No Connect in XC2V80
1
1
1
1
1
1
1
1
1
1
1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IO_L05N_1
A11
IO_L05P_1
B11
IO_L04N_1
C11
IO_L04P_1/VREF_1
IO_L03N_1/VRP_1
IO_L03P_1/VRN_1
IO_L02N_1
D11
A12
B12
C12
IO_L02P_1
D12
IO_L01N_1
B13
IO_L01P_1
C13
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO_L01N_2
IO_L01P_2
C16
D16
D14
D15
E13
E14
E15
E16
F13
F14
F15
F16
F12
G12
G13
G14
G15
G16
H13
H14
H15
H16
IO_L02N_2/VRP_2
IO_L02P_2/VRN_2
IO_L03N_2
IO_L03P_2/VREF_2
IO_L04N_2
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IO_L04P_2
IO_L06N_2
IO_L06P_2
IO_L43N_2
NC
NC
NC
NC
IO_L43P_2
IO_L45N_2
IO_L45P_2/VREF_2
IO_L91N_2
IO_L91P_2
IO_L93N_2
IO_L93P_2/VREF_2
IO_L94N_2
IO_L94P_2
IO_L96N_2
IO_L96P_2
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 6: FG256 BGA — XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000
Bank
Pin Description
Pin Number
No Connect in XC2V40 No Connect in XC2V80
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO_L96N_3
IO_L96P_3
J16
J15
J14
J13
K16
K15
K14
K13
K12
L12
L16
L15
L14
L13
M16
M15
M14
M13
N15
N14
N16
P16
IO_L94N_3
IO_L94P_3
IO_L93N_3/VREF_3
IO_L93P_3
NC
NC
NC
NC
IO_L91N_3
IO_L91P_3
IO_L45N_3/VREF_3
IO_L45P_3
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IO_L43N_3
IO_L43P_3
IO_L06N_3
IO_L06P_3
IO_L04N_3
IO_L04P_3
IO_L03N_3/VREF_3
IO_L03P_3
IO_L02N_3/VRP_3
IO_L02P_3/VRN_3
IO_L01N_3
IO_L01P_3
4
4
4
4
4
4
4
4
4
4
IO_L01N_4/DOUT
IO_L01P_4/INIT_B
IO_L02N_4/D0
T14
T13
P13
R13
N12
P12
R12
T12
N11
P11
IO_L02P_4/D1
IO_L03N_4/D2/ALT_VRP_4
IO_L03P_4/D3/ALT_VRN_4
IO_L04N_4/VREF_4
IO_L04P_4
NC
NC
NC
NC
NC
NC
NC
NC
IO_L05N_4/VRP_4
IO_L05P_4/VRN_4
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 6: FG256 BGA — XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000
Bank
Pin Description
IO_L91N_4/VREF_4
IO_L91P_4
Pin Number
R11
T11
No Connect in XC2V40 No Connect in XC2V80
4
4
4
4
4
4
4
4
4
4
4
4
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IO_L92N_4
M11
M10
N10
P10
R10
T10
IO_L92P_4
IO_L93N_4
IO_L93P_4
IO_L94N_4/VREF_4
IO_L94P_4
IO_L95N_4/GCLK3S
IO_L95P_4/GCLK2P
IO_L96N_4/GCLK1S
IO_L96P_4/GCLK0P
N9
P9
R9
T9
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
IO_L96N_5/GCLK7S
IO_L96P_5/GCLK6P
IO_L95N_5/GCLK5S
IO_L95P_5/GCLK4P
IO_L94N_5
T8
R8
P8
N8
T7
R7
P7
N7
M7
M6
T6
R6
P6
N6
T5
R5
P5
N5
R4
P4
T4
IO_L94P_5/VREF_5
IO_L93N_5
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IO_L93P_5
IO_L92N_5
IO_L92P_5
IO_L91N_5
IO_L91P_5/VREF_5
IO_L05N_5/VRP_5
IO_L05P_5/VRN_5
IO_L04N_5
IO_L04P_5/VREF_5
IO_L03N_5/D4/ALT_VRP_5
IO_L03P_5/D5/ALT_VRN_5
IO_L02N_5/D6
IO_L02P_5/D7
IO_L01N_5/RDWR_B
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 6: FG256 BGA — XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000
Bank
Pin Description
Pin Number
No Connect in XC2V40 No Connect in XC2V80
5
IO_L01P_5/CS_B
T3
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
IO_L01P_6
IO_L01N_6
P1
N1
N3
N2
M4
M3
M2
M1
L4
L3
L2
L1
L5
K5
K4
K3
K2
K1
J4
IO_L02P_6/VRN_6
IO_L02N_6/VRP_6
IO_L03P_6
IO_L03N_6/VREF_6
IO_L04P_6
NC
NC
NC
NC
IO_L04N_6
IO_L06P_6
IO_L06N_6
IO_L43P_6
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IO_L43N_6
IO_L45P_6
IO_L45N_6/VREF_6
IO_L91P_6
IO_L91N_6
IO_L93P_6
IO_L93N_6/VREF_6
IO_L94P_6
IO_L94N_6
J3
IO_L96P_6
J2
IO_L96N_6
J1
7
7
7
7
7
7
7
7
7
IO_L96P_7
IO_L96N_7
H1
H2
H3
H4
G1
G2
G3
G4
G5
IO_L94P_7
IO_L94N_7
IO_L93P_7/VREF_7
IO_L93N_7
NC
NC
NC
NC
NC
IO_L91P_7
IO_L91N_7
IO_L45P_7/VREF_7
NC
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 6: FG256 BGA — XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000
Bank
Pin Description
IO_L45N_7
Pin Number
No Connect in XC2V40 No Connect in XC2V80
7
7
7
7
7
7
7
7
7
7
7
7
7
F5
F1
F2
F3
F4
E1
E2
E3
E4
D2
D3
D1
C1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IO_L43P_7
IO_L43N_7
IO_L06P_7
IO_L06N_7
IO_L04P_7
IO_L04N_7
IO_L03P_7/VREF_7
IO_L03N_7
IO_L02P_7/VRN_7
IO_L02N_7/VRP_7
IO_L01P_7
IO_L01N_7
0
0
0
1
1
1
2
2
2
3
3
3
4
4
4
5
5
5
6
6
VCCO_0
VCCO_0
VCCO_0
VCCO_1
VCCO_1
VCCO_1
VCCO_2
VCCO_2
VCCO_2
VCCO_3
VCCO_3
VCCO_3
VCCO_4
VCCO_4
VCCO_4
VCCO_5
VCCO_5
VCCO_5
VCCO_6
VCCO_6
F8
F7
E8
F10
F9
E9
H12
H11
G11
K11
J12
J11
M9
L10
L9
M8
L8
L7
K6
J6
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 6: FG256 BGA — XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000
Bank
Pin Description
VCCO_6
Pin Number
No Connect in XC2V40 No Connect in XC2V80
6
7
7
7
J5
H6
H5
G6
VCCO_7
VCCO_7
VCCO_7
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
CCLK
PROG_B
DONE
M0
P15
A2
R14
T2
M1
P2
M2
R3
HSWAP_EN
TCK
B3
A15
C2
TDI
TDO
C15
B14
T15
A4
TMS
PWRDWN_B
RSVD
RSVD
VBATT
RSVD
A3
A14
A13
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
R16
R1
B16
B1
N13
N4
M12
M5
E12
E5
D13
D4
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 6: FG256 BGA — XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000
Bank
Pin Description
Pin Number
No Connect in XC2V40 No Connect in XC2V80
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
T16
T1
R15
R2
P14
P3
L11
L6
K10
K9
K8
K7
J10
J9
J8
J7
H10
H9
H8
H7
G10
G9
G8
G7
F11
F6
C14
C3
B15
B2
A16
A1
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
FG256 Fine-Pitch BGA Package Specifications (1.00mm pitch)
Figure 2: FG256 Fine-Pitch BGA Package Specifications
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
FG456 Fine-Pitch BGA Package
As shown in Table 7, XC2V250, XC2V500, and XC2V1000 Virtex-II devices are available in the FG456 fine-pitch BGA
package. Pins in the XC2V250, XC2V500, and XC2V1000 devices are the same, except for the pin differences in the
XC2V250 and XC2V500 devices shown in the No Connect columns. Following this table are the FG456 Fine-Pitch BGA
Package Specifications (1.00mm pitch).
Table 7: FG456 BGA — XC2V250, XC2V500, and XC2V1000
Bank
0
Pin Description
IO_L01N_0
Pin Number
B4
No Connect in XC2V250
No Connect in XC2V500
0
IO_L01P_0
A4
0
IO_L02N_0
C4
0
IO_L02P_0
C5
0
IO_L03N_0/VRP_0
IO_L03P_0/VRN_0
IO_L04N_0/VREF_0
IO_L04P_0
B5
0
A5
0
D6
0
C6
0
IO_L05N_0
B6
0
IO_L05P_0
A6
0
IO_L06N_0
E7
0
IO_L06P_0
E8
0
IO_L21N_0
D7
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
0
IO_L21P_0/VREF_0
IO_L22N_0
C7
0
B7
0
IO_L22P_0
A7
0
IO_L24N_0
D8
0
IO_L24P_0
C8
0
IO_L49N_0
B8
0
IO_L49P_0
A8
0
IO_L51N_0
E9
0
IO_L51P_0/VREF_0
IO_L52N_0
F9
0
D9
0
IO_L52P_0
C9
0
IO_L54N_0
B9
0
IO_L54P_0
A9
0
IO_L91N_0/VREF_0
IO_L91P_0
E10
F10
D10
C10
0
0
IO_L92N_0
0
IO_L92P_0
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 7: FG456 BGA — XC2V250, XC2V500, and XC2V1000
Bank
Pin Description
IO_L93N_0
Pin Number
B10
No Connect in XC2V250
No Connect in XC2V500
0
0
0
0
0
0
0
0
IO_L93P_0
A10
IO_L94N_0/VREF_0
IO_L94P_0
E11
F11
IO_L95N_0/GCLK7P
IO_L95P_0/GCLK6S
IO_L96N_0/GCLK5P
IO_L96P_0/GCLK4S
D11
C11
B11
A11
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IO_L96N_1/GCLK3P
IO_L96P_1/GCLK2S
IO_L95N_1/GCLK1P
IO_L95P_1/GCLK0S
IO_L94N_1
F12
F13
E12
D12
C12
B12
A13
B13
C13
D13
E13
E14
A14
B14
C14
D14
A15
B15
C15
D15
F14
E15
A16
B16
C16
IO_L94P_1/VREF_1
IO_L93N_1
IO_L93P_1
IO_L92N_1
IO_L92P_1
IO_L91N_1
IO_L91P_1/VREF_1
IO_L54N_1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IO_L54P_1
IO_L52N_1
IO_L52P_1
IO_L51N_1/VREF_1
IO_L51P_1
IO_L49N_1
IO_L49P_1
IO_L24N_1
NC
NC
NC
NC
NC
IO_L24P_1
IO_L22N_1
IO_L22P_1
IO_L21N_1/VREF_1
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 7: FG456 BGA — XC2V250, XC2V500, and XC2V1000
Bank
Pin Description
IO_L21P_1
Pin Number
D16
No Connect in XC2V250
No Connect in XC2V500
1
1
1
1
1
1
1
1
1
1
1
1
1
NC
NC
IO_L06N_1
E16
IO_L06P_1
E17
IO_L05N_1
A17
IO_L05P_1
B17
IO_L04N_1
C17
IO_L04P_1/VREF_1
IO_L03N_1/VRP_1
IO_L03P_1/VRN_1
IO_L02N_1
D17
A18
B18
C18
IO_L02P_1
D18
IO_L01N_1
A19
IO_L01P_1
B19
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO_L01N_2
IO_L01P_2
C21
C22
E18
F18
D21
D22
E19
E20
E21
E22
F19
F20
F21
F22
G18
H18
G19
G20
G21
G22
IO_L02N_2/VRP_2
IO_L02P_2/VRN_2
IO_L03N_2
IO_L03P_2/VREF_2
IO_L04N_2
IO_L04P_2
IO_L06N_2
IO_L06P_2
IO_L19N_2
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IO_L19P_2
IO_L21N_2
IO_L21P_2/VREF_2
IO_L22N_2
IO_L22P_2
IO_L24N_2
IO_L24P_2
IO_L43N_2
IO_L43P_2
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 7: FG456 BGA — XC2V250, XC2V500, and XC2V1000
Bank
2
Pin Description
IO_L45N_2
Pin Number
H19
H20
H21
H22
J17
No Connect in XC2V250
No Connect in XC2V500
2
IO_L45P_2/VREF_2
IO_L46N_2
2
2
IO_L46P_2
2
IO_L48N_2
2
IO_L48P_2
J18
2
IO_L49N_2
J19
NC
NC
NC
NC
NC
NC
NC
NC
2
IO_L49P_2
J20
2
IO_L51N_2
J21
2
IO_L51P_2/VREF_2
IO_L52N_2
J22
2
K17
K18
K19
K20
K21
K22
L17
2
IO_L52P_2
2
IO_L54N_2
2
IO_L54P_2
2
IO_L91N_2
2
IO_L91P_2
2
IO_L93N_2
2
IO_L93P_2/VREF_2
IO_L94N_2
L18
2
L19
2
IO_L94P_2
L20
2
IO_L96N_2
L21
2
IO_L96P_2
L22
3
3
3
3
3
3
3
3
3
3
3
IO_L96N_3
IO_L96P_3
M21
M20
M19
M18
M17
N17
N22
N21
N20
N19
N18
IO_L94N_3
IO_L94P_3
IO_L93N_3/VREF_3
IO_L93P_3
IO_L91N_3
IO_L91P_3
IO_L54N_3
NC
NC
NC
IO_L54P_3
IO_L52N_3
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 7: FG456 BGA — XC2V250, XC2V500, and XC2V1000
Bank
3
Pin Description
IO_L52P_3
Pin Number
P18
P22
P21
P20
P19
R22
R21
R20
R19
R18
P17
T22
No Connect in XC2V250
No Connect in XC2V500
NC
NC
NC
NC
NC
3
IO_L51N_3/VREF_3
IO_L51P_3
3
3
IO_L49N_3
3
IO_L49P_3
3
IO_L48N_3
3
IO_L48P_3
3
IO_L46N_3
3
IO_L46P_3
3
IO_L45N_3/VREF_3
IO_L45P_3
3
3
IO_L43N_3
3
IO_L43P_3
T21
3
IO_L24N_3
T20
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
3
IO_L24P_3
T19
3
IO_L22N_3
U22
U21
U20
U19
T18
3
IO_L22P_3
3
IO_L21N_3/VREF_3
IO_L21P_3
3
3
IO_L19N_3
3
IO_L19P_3
U18
V22
V21
V20
V19
W22
W21
Y22
Y21
W20
AA20
3
IO_L06N_3
3
IO_L06P_3
3
IO_L04N_3
3
IO_L04P_3
3
IO_L03N_3/VREF_3
IO_L03P_3
3
3
IO_L02N_3/VRP_3
IO_L02P_3/VRN_3
IO_L01N_3
3
3
3
IO_L01P_3
4
4
IO_L01N_4/DOUT
IO_L01P_4/INIT_B
AB19
AA19
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 7: FG456 BGA — XC2V250, XC2V500, and XC2V1000
Bank
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Pin Description
IO_L02N_4/D0
IO_L02P_4/D1
IO_L03N_4/D2/ALT_VRP_4
IO_L03P_4/D3/ALT_VRN_4
IO_L04N_4/VREF_4
IO_L04P_4
Pin Number
V18
No Connect in XC2V250
No Connect in XC2V500
V17
W18
Y18
AA18
AB18
W17
Y17
IO_L05N_4/VRP_4
IO_L05P_4/VRN_4
IO_L06N_4
AA17
AB17
V16
IO_L06P_4
IO_L19N_4
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IO_L19P_4
V15
IO_L21N_4
W16
Y16
IO_L21P_4/VREF_4
IO_L22N_4
AA16
AB16
W15
Y15
IO_L22P_4
IO_L24N_4
IO_L24P_4
IO_L49N_4
AA15
AB15
U14
IO_L49P_4
IO_L51N_4
IO_L51P_4/VREF_4
IO_L52N_4
V14
W14
Y14
IO_L52P_4
IO_L54N_4
AA14
AB14
U13
IO_L54P_4
IO_L91N_4/VREF_4
IO_L91P_4
V13
IO_L92N_4
W13
Y13
IO_L92P_4
IO_L93N_4
AA13
AB13
U12
IO_L93P_4
IO_L94N_4/VREF_4
IO_L94P_4
V12
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 7: FG456 BGA — XC2V250, XC2V500, and XC2V1000
Bank
Pin Description
Pin Number
W12
No Connect in XC2V250
No Connect in XC2V500
4
4
4
4
IO_L95N_4/GCLK3S
IO_L95P_4/GCLK2P
IO_L96N_4/GCLK1S
IO_L96P_4/GCLK0P
Y12
AA12
AB12
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
IO_L96N_5/GCLK7S
IO_L96P_5/GCLK6P
IO_L95N_5/GCLK5S
IO_L95P_5/GCLK4P
IO_L94N_5
AA11
Y11
W11
V11
U11
U10
AB10
AA10
Y10
W10
V10
V9
IO_L94P_5/VREF_5
IO_L93N_5
IO_L93P_5
IO_L92N_5
IO_L92P_5
IO_L91N_5
IO_L91P_5/VREF_5
IO_L54N_5
AB9
AA9
Y9
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IO_L54P_5
IO_L52N_5
IO_L52P_5
W9
IO_L51N_5/VREF_5
IO_L51P_5
AB8
AA8
Y8
IO_L49N_5
IO_L49P_5
W8
IO_L24N_5
U9
NC
NC
NC
NC
NC
NC
NC
NC
IO_L24P_5
V8
IO_L22N_5
AB7
AA7
Y7
IO_L22P_5
IO_L21N_5/VREF_5
IO_L21P_5
W7
IO_L19N_5
AB6
AA6
Y6
IO_L19P_5
IO_L06N_5
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Advance Product Specification
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R
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 7: FG456 BGA — XC2V250, XC2V500, and XC2V1000
Bank
Pin Description
IO_L06P_5
Pin Number
W6
No Connect in XC2V250
No Connect in XC2V500
5
5
5
5
5
5
5
5
5
5
5
IO_L05N_5/VRP_5
IO_L05P_5/VRN_5
IO_L04N_5
V7
V6
AB5
AA5
Y5
IO_L04P_5/VREF_5
IO_L03N_5/D4/ALT_VRP_5
IO_L03P_5/D5/ALT_VRN_5
IO_L02N_5/D6
W5
AB4
AA4
Y4
IO_L02P_5/D7
IO_L01N_5/RDWR_B
IO_L01P_5/CS_B
AA3
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
IO_L01P_6
IO_L01N_6
V5
U5
Y2
Y1
V4
V3
W2
W1
U4
U3
V2
V1
U2
U1
T5
R5
T4
T3
T2
T1
R4
R3
IO_L02P_6/VRN_6
IO_L02N_6/VRP_6
IO_L03P_6
IO_L03N_6/VREF_6
IO_L04P_6
IO_L04N_6
IO_L06P_6
IO_L06N_6
IO_L19P_6
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IO_L19N_6
IO_L21P_6
IO_L21N_6/VREF_6
IO_L22P_6
IO_L22N_6
IO_L24P_6
IO_L24N_6
IO_L43P_6
IO_L43N_6
IO_L45P_6
IO_L45N_6/VREF_6
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R
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 7: FG456 BGA — XC2V250, XC2V500, and XC2V1000
Bank
6
Pin Description
IO_L46P_6
Pin Number
R2
No Connect in XC2V250
No Connect in XC2V500
6
IO_L46N_6
IO_L48P_6
R1
6
P6
6
IO_L48N_6
P5
6
IO_L49P_6
P4
NC
NC
NC
NC
NC
NC
NC
NC
6
IO_L49N_6
IO_L51P_6
P3
6
P2
6
IO_L51N_6/VREF_6
IO_L52P_6
P1
6
N6
6
IO_L52N_6
IO_L54P_6
N5
6
N4
6
IO_L54N_6
IO_L91P_6
N3
6
N2
6
IO_L91N_6
IO_L93P_6
N1
6
M6
M5
M4
M3
M2
M1
6
IO_L93N_6/VREF_6
IO_L94P_6
6
6
IO_L94N_6
6
IO_L96P_6
6
IO_L96N_6
7
7
7
7
7
7
7
7
7
7
7
7
7
IO_L96P_7
IO_L96N_7
L2
L3
L4
L5
K1
K2
K3
K4
L6
K6
K5
J5
J1
IO_L94P_7
IO_L94N_7
IO_L93P_7/VREF_7
IO_L93N_7
IO_L91P_7
IO_L91N_7
IO_L54P_7
NC
NC
NC
NC
NC
IO_L54N_7
IO_L52P_7
IO_L52N_7
IO_L51P_7/VREF_7
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Advance Product Specification
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Module 4 of 4
27
R
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 7: FG456 BGA — XC2V250, XC2V500, and XC2V1000
Bank
7
Pin Description
IO_L51N_7
Pin Number
J2
No Connect in XC2V250
No Connect in XC2V500
NC
NC
NC
7
IO_L49P_7
J3
7
IO_L49N_7
J4
7
IO_L48P_7
H1
H2
H3
H4
J6
7
IO_L48N_7
7
IO_L46P_7
7
IO_L46N_7
7
IO_L45P_7/VREF_7
IO_L45N_7
7
H5
G1
G2
G3
G4
F1
7
IO_L43P_7
7
IO_L43N_7
7
IO_L24P_7
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
7
IO_L24N_7
7
IO_L22P_7
7
IO_L22N_7
F2
7
IO_L21P_7/VREF_7
IO_L21N_7
F3
7
F4
7
IO_L19P_7
G5
F5
7
IO_L19N_7
7
IO_L06P_7
E1
7
IO_L06N_7
E2
7
IO_L04P_7
E3
7
IO_L04N_7
E4
7
IO_L03P_7/VREF_7
IO_L03N_7
D1
D2
C1
C2
E5
7
7
IO_L02P_7/VRN_7
IO_L02N_7/VRP_7
IO_L01P_7
7
7
7
IO_L01N_7
E6
0
0
0
0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
G11
G10
G9
F8
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Advance Product Specification
R
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 7: FG456 BGA — XC2V250, XC2V500, and XC2V1000
Bank
0
1
1
1
1
1
2
2
2
2
2
3
3
3
3
3
4
4
4
4
4
5
5
5
5
5
6
6
6
6
6
7
7
7
Pin Description
VCCO_0
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_7
VCCO_7
VCCO_7
Pin Number
F7
No Connect in XC2V250
No Connect in XC2V500
G14
G13
G12
F16
F15
L16
K16
J16
H17
G17
T17
R17
P16
N16
M16
U16
U15
T14
T13
T12
U8
U7
T11
T10
T9
T6
R6
P7
N7
M7
L7
K7
J7
DS031-4 (v1.8) October 7, 2002
Advance Product Specification
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Module 4 of 4
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R
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 7: FG456 BGA — XC2V250, XC2V500, and XC2V1000
Bank
Pin Description
VCCO_7
Pin Number
No Connect in XC2V250
No Connect in XC2V500
7
7
H6
G6
VCCO_7
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
CCLK
PROG_B
DONE
M0
Y19
A2
AB20
AB2
W3
M1
M2
AB3
B3
HSWAP_EN
TCK
C19
D3
TDI
TDO
D20
B20
AB21
D5
TMS
PWRDWN_B
DXN
DXP
A3
VBATT
RSVD
A21
A20
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
AB11
AA22
AA1
M22
L1
B22
B1
A12
U17
U6
T16
T15
T8
T7
Module 4 of 4
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DS031-4 (v1.8) October 7, 2002
Advance Product Specification
R
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 7: FG456 BGA — XC2V250, XC2V500, and XC2V1000
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
GND
Pin Number
R16
R7
No Connect in XC2V250
No Connect in XC2V500
H16
H7
G16
G15
G8
G7
F17
F6
AB22
AB1
AA21
AA2
Y20
Y3
GND
GND
GND
GND
GND
GND
W19
W4
GND
GND
P14
P13
P12
P11
P10
P9
GND
GND
GND
GND
GND
GND
N14
N13
N12
N11
N10
N9
GND
GND
GND
GND
GND
GND
M14
M13
M12
M11
GND
GND
GND
DS031-4 (v1.8) October 7, 2002
Advance Product Specification
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Module 4 of 4
31
R
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 7: FG456 BGA — XC2V250, XC2V500, and XC2V1000
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin Number
M10
M9
No Connect in XC2V250
No Connect in XC2V500
L14
L13
L12
L11
L10
L9
K14
K13
K12
K11
K10
K9
J14
J13
J12
J11
J10
J9
D19
D4
C20
C3
B21
B2
A22
A1
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
FG456 Fine-Pitch BGA Package Specifications (1.00mm pitch)
Figure 3: FG456 Fine-Pitch BGA Package Specifications
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
FG676 Fine-Pitch BGA Package
As shown in Table 8, XC2V1500, XC2V2000, and XC2V3000 Virtex-II devices are available in the FG676 fine-pitch BGA
package. Pins in the XC2V1500, XC2V2000, and XC2V3000 devices are the same, except for the pin differences in the
XC2V1500 and XC2V2000 devices shown in the No Connect columns. Following this table are the FG676 Fine-Pitch BGA
Package Specifications (1.00mm pitch).
Table 8: FG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank
0
Pin Description
IO_L01N_0
Pin Number No Connect in XC2V1500 No Connect in XC2V2000
D6
C6
B1
A2
D7
C7
B3
A3
G6
G7
E6
E7
B4
A4
B5
A5
B6
A6
A7
A8
0
IO_L01P_0
0
IO_L02N_0
0
IO_L02P_0
0
IO_L03N_0/VRP_0
IO_L03P_0/VRN_0
IO_L04N_0/VREF_0
IO_L04P_0
0
0
0
0
IO_L05N_0
0
IO_L05P_0
0
IO_L06N_0
0
IO_L06P_0
0
IO_L19N_0
0
IO_L19P_0
0
IO_L21N_0
0
IO_L21P_0/VREF_0
IO_L22N_0
0
0
IO_L22P_0
0
IO_L24N_0
0
IO_L24P_0
0
IO_L25N_0
E8
D8
G8
F8
C8
B8
D9
E9
F9
G9
B9
A9
C9
NC
NC
NC
NC
NC
NC
NC
NC
0
IO_L25P_0
0
IO_L27N_0
0
IO_L27P_0/VREF_0
IO_L49N_0
0
0
IO_L49P_0
0
IO_L51N_0
0
IO_L51P_0/VREF_0
IO_L52N_0
0
0
IO_L52P_0
0
IO_L54N_0
0
IO_L54P_0
0
IO_L67N_0
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 8: FG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank
0
Pin Description
IO_L67P_0
Pin Number No Connect in XC2V1500 No Connect in XC2V2000
C10
F10
G10
E10
D10
A10
A11
0
IO_L69N_0
0
IO_L69P_0/VREF_0
IO_L70N_0
0
0
IO_L70P_0
0
IO_L72N_0
0
IO_L72P_0
0
IO_L73N_0
F11
E11
G11
H11
D11
C11
B11
B12
G12
H12
F12
E12
D12
C12
G13
H13
F13
E13
D13
C13
NC
NC
NC
NC
NC
NC
NC
NC
0
IO_L73P_0
0
IO_L75N_0
0
IO_L75P_0/VREF_0
IO_L76N_0
0
0
IO_L76P_0
0
IO_L78N_0
0
IO_L78P_0
0
IO_L91N_0/VREF_0
IO_L91P_0
0
0
IO_L92N_0
0
IO_L92P_0
0
IO_L93N_0
0
IO_L93P_0
0
IO_L94N_0/VREF_0
IO_L94P_0
0
0
IO_L95N_0/GCLK7P
IO_L95P_0/GCLK6S
IO_L96N_0/GCLK5P
IO_L96P_0/GCLK4S
0
0
0
1
1
1
1
1
1
1
1
1
IO_L96N_1/GCLK3P
IO_L96P_1/GCLK2S
IO_L95N_1/GCLK1P
IO_L95P_1/GCLK0S
IO_L94N_1
H14
H15
G14
F14
E14
D14
A12
A13
A14
IO_L94P_1/VREF_1
IO_L93N_1
IO_L93P_1
IO_L92N_1
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 8: FG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Description
IO_L92P_1
Pin Number No Connect in XC2V1500 No Connect in XC2V2000
A15
B15
C15
IO_L91N_1
IO_L91P_1/VREF_1
IO_L78N_1
D15
E15
F15
G15
G16
F16
A16
A17
B16
C16
D16
E16
C17
D17
H16
G17
E17
F17
A18
A19
E18
D18
B18
C18
F19
F18
G18
G19
B19
C19
D19
E19
A20
A21
NC
NC
NC
NC
NC
NC
NC
NC
IO_L78P_1
IO_L76N_1
IO_L76P_1
IO_L75N_1/VREF_1
IO_L75P_1
IO_L73N_1
IO_L73P_1
IO_L72N_1
IO_L72P_1
IO_L70N_1
IO_L70P_1
IO_L69N_1/VREF_1
IO_L69P_1
IO_L67N_1
IO_L67P_1
IO_L54N_1
IO_L54P_1
IO_L52N_1
IO_L52P_1
IO_L51N_1/VREF_1
IO_L51P_1
IO_L49N_1
IO_L49P_1
IO_L27N_1/VREF_1
IO_L27P_1
NC
NC
NC
NC
NC
NC
NC
NC
IO_L25N_1
IO_L25P_1
IO_L24N_1
IO_L24P_1
IO_L22N_1
IO_L22P_1
IO_L21N_1/VREF_1
IO_L21P_1
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 8: FG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank
Pin Description
IO_L19N_1
Pin Number No Connect in XC2V1500 No Connect in XC2V2000
1
1
1
1
1
1
1
1
1
1
1
1
1
1
E20
F20
B21
B22
A22
A23
C21
D21
C20
D20
A24
A25
B23
B24
IO_L19P_1
IO_L06N_1
IO_L06P_1
IO_L05N_1
IO_L05P_1
IO_L04N_1
IO_L04P_1/VREF_1
IO_L03N_1/VRP_1
IO_L03P_1/VRN_1
IO_L02N_1
IO_L02P_1
IO_L01N_1
IO_L01P_1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO_L01N_2
IO_L01P_2
B26
C26
G20
H20
C25
D25
E23
E24
G21
G22
D26
E26
F23
F24
E25
F25
H22
H21
IO_L02N_2/VRP_2
IO_L02P_2/VRN_2
IO_L03N_2
IO_L03P_2/VREF_2
IO_L04N_2
IO_L04P_2
IO_L06N_2
IO_L06P_2
IO_L19N_2
IO_L19P_2
IO_L21N_2
IO_L21P_2/VREF_2
IO_L22N_2
IO_L22P_2
IO_L24N_2
IO_L24P_2
IO_L25N_2
G23
G24
F26
G26
NC
NC
NC
NC
IO_L25P_2
IO_L43N_2
IO_L43P_2
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 8: FG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Pin Description
IO_L45N_2
Pin Number No Connect in XC2V1500 No Connect in XC2V2000
H23
H24
J21
J20
H25
H26
J22
J23
K21
K22
K20
L20
J24
J25
K23
K24
J26
K26
L22
L21
L25
L26
IO_L45P_2/VREF_2
IO_L46N_2
IO_L46P_2
IO_L48N_2
IO_L48P_2
IO_L49N_2
IO_L49P_2
IO_L51N_2
IO_L51P_2/VREF_2
IO_L52N_2
IO_L52P_2
IO_L54N_2
IO_L54P_2
IO_L67N_2
IO_L67P_2
IO_L69N_2
IO_L69P_2/VREF_2
IO_L70N_2
IO_L70P_2
IO_L72N_2
IO_L72P_2
IO_L73N_2
L19
M19
L23
NC
NC
NC
NC
NC
NC
NC
NC
IO_L73P_2
IO_L75N_2
IO_L75P_2/VREF_2
IO_L76N_2
L24
M22
M21
M23
M24
M25
M26
M20
N20
N22
N21
N24
IO_L76P_2
IO_L78N_2
IO_L78P_2
IO_L91N_2
IO_L91P_2
IO_L93N_2
IO_L93P_2/VREF_2
IO_L94N_2
IO_L94P_2
IO_L96N_2
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 8: FG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank
Pin Description
Pin Number No Connect in XC2V1500 No Connect in XC2V2000
2
IO_L96P_2
N23
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO_L96N_3
IO_L96P_3
N26
P26
P23
P22
P19
N19
P21
P20
IO_L94N_3
IO_L94P_3
IO_L93N_3/VREF_3
IO_L93P_3
IO_L91N_3
IO_L91P_3
IO_L78N_3
IO_L78P_3
R26
R25
R20
R19
R24
R23
R22
R21
T26
T25
T20
T19
T24
T23
T22
T21
U26
V26
U24
U23
U22
U21
V25
V24
V23
V22
W26
NC
NC
NC
NC
NC
NC
NC
NC
IO_L76N_3
IO_L76P_3
IO_L75N_3/VREF_3
IO_L75P_3
IO_L73N_3
IO_L73P_3
IO_L72N_3
IO_L72P_3
IO_L70N_3
IO_L70P_3
IO_L69N_3/VREF_3
IO_L69P_3
IO_L67N_3
IO_L67P_3
IO_L54N_3
IO_L54P_3
IO_L52N_3
IO_L52P_3
IO_L51N_3/VREF_3
IO_L51P_3
IO_L49N_3
IO_L49P_3
IO_L48N_3
IO_L48P_3
IO_L46N_3
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 8: FG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank
3
Pin Description
IO_L46P_3
Pin Number No Connect in XC2V1500 No Connect in XC2V2000
Y26
U20
V20
W25
W24
3
IO_L45N_3/VREF_3
IO_L45P_3
3
3
IO_L43N_3
3
IO_L43P_3
3
IO_L25N_3
V21
W21
NC
NC
NC
NC
3
IO_L25P_3
3
IO_L24N_3
AA26
AA25
Y24
3
IO_L24P_3
3
IO_L22N_3
3
IO_L22P_3
Y23
3
IO_L21N_3/VREF_3
IO_L21P_3
W22
3
W23
3
IO_L19N_3
AB26
AB25
AC26
AC25
AD26
AD25
AA24
AA23
AB24
AB23
Y22
3
IO_L19P_3
3
IO_L06N_3
3
IO_L06P_3
3
IO_L04N_3
3
IO_L04P_3
3
IO_L03N_3/VREF_3
IO_L03P_3
3
3
IO_L02N_3/VRP_3
IO_L02P_3/VRN_3
IO_L01N_3
3
3
3
IO_L01P_3
AA22
4
4
4
4
4
4
4
4
4
4
4
IO_L01N_4/DOUT
IO_L01P_4/INIT_B
IO_L02N_4/D0
AD21
AC21
Y20
IO_L02P_4/D1
Y19
IO_L03N_4/D2/ALT_VRP_4
IO_L03P_4/D3/ALT_VRN_4
IO_L04N_4/VREF_4
IO_L04P_4
AA20
AB20
AC22
AE21
AE26
AF25
W20
IO_L05N_4/VRP_4
IO_L05P_4/VRN_4
IO_L06N_4
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 8: FG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Pin Description
IO_L06P_4
Pin Number No Connect in XC2V1500 No Connect in XC2V2000
Y21
IO_L19N_4
AE24
AF24
AE23
AF23
AE22
AF22
AF21
AF20
IO_L19P_4
IO_L21N_4
IO_L21P_4/VREF_4
IO_L22N_4
IO_L22P_4
IO_L24N_4
IO_L24P_4
IO_L25N_4
AA19
AB19
AD20
AC20
AC19
AD19
AE19
AF19
AA18
AB18
Y18
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IO_L25P_4
IO_L27N_4
IO_L27P_4/VREF_4
IO_L28N_4
IO_L28P_4
IO_L49N_4
IO_L49P_4
IO_L51N_4
IO_L51P_4/VREF_4
IO_L52N_4
IO_L52P_4
Y17
IO_L54N_4
AC18
AD18
AE18
AF18
AA17
AB17
AC17
AD17
AF17
AF16
AB16
AC16
AA16
Y16
IO_L54P_4
IO_L67N_4
IO_L67P_4
IO_L69N_4
IO_L69P_4/VREF_4
IO_L70N_4
IO_L70P_4
IO_L72N_4
IO_L72P_4
IO_L73N_4
NC
NC
NC
NC
NC
NC
IO_L73P_4
IO_L75N_4
IO_L75P_4/VREF_4
IO_L76N_4
AD16
AE16
IO_L76P_4
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 8: FG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank
Pin Description
IO_L78N_4
Pin Number No Connect in XC2V1500 No Connect in XC2V2000
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Y15
AA15
W15
NC
NC
IO_L78P_4
IO_L91N_4/VREF_4
IO_L91P_4
W16
IO_L92N_4
AB15
AC15
AD15
AE15
W14
IO_L92P_4
IO_L93N_4
IO_L93P_4
IO_L94N_4/VREF_4
IO_L94P_4
Y14
IO_L95N_4/GCLK3S
IO_L95P_4/GCLK2P
IO_L96N_4/GCLK1S
IO_L96P_4/GCLK0P
AA14
AB14
AC14
AD14
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
IO_L96N_5/GCLK7S
IO_L96P_5/GCLK6P
IO_L95N_5/GCLK5S
IO_L95P_5/GCLK4P
IO_L94N_5
AC13
AB13
AA13
Y13
W13
IO_L94P_5/VREF_5
IO_L93N_5
W12
AF15
AF14
AF13
AF12
AE12
AD12
AC12
AB12
AA12
Y12
IO_L93P_5
IO_L92N_5
IO_L92P_5
IO_L91N_5
IO_L91P_5/VREF_5
IO_L78N_5
NC
NC
NC
NC
NC
NC
NC
NC
IO_L78P_5
IO_L76N_5
IO_L76P_5
IO_L75N_5/VREF_5
IO_L75P_5
AF11
AF10
AE11
AD11
AC11
AB11
IO_L73N_5
IO_L73P_5
IO_L72N_5
IO_L72P_5
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 8: FG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
Pin Description
IO_L70N_5
Pin Number No Connect in XC2V1500 No Connect in XC2V2000
W11
Y10
IO_L70P_5
IO_L69N_5/VREF_5
IO_L69P_5
Y11
AA11
AF9
IO_L67N_5
IO_L67P_5
AF8
IO_L54N_5
AE9
IO_L54P_5
AD9
AB10
AA10
AD10
AC10
AE8
IO_L52N_5
IO_L52P_5
IO_L51N_5/VREF_5
IO_L51P_5
IO_L49N_5
IO_L49P_5
AF7
IO_L28N_5
AD8
AC8
AB9
AC9
AA9
Y9
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IO_L28P_5
IO_L27N_5/VREF_5
IO_L27P_5
IO_L25N_5
IO_L25P_5
IO_L24N_5
AF6
AE6
AB8
AA8
AC7
AD7
AF5
AE5
AF4
AE4
AF3
AE3
Y8
IO_L24P_5
IO_L22N_5
IO_L22P_5
IO_L21N_5/VREF_5
IO_L21P_5
IO_L19N_5
IO_L19P_5
IO_L06N_5
IO_L06P_5
IO_L05N_5/VRP_5
IO_L05P_5/VRN_5
IO_L04N_5
IO_L04P_5/VREF_5
IO_L03N_5/D4/ALT_VRP_5
IO_L03P_5/D5/ALT_VRN_5
IO_L02N_5/D6
Y7
AB7
AA7
AD6
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 8: FG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank
Pin Description
IO_L02P_5/D7
Pin Number No Connect in XC2V1500 No Connect in XC2V2000
5
5
5
AC6
AB6
AC5
IO_L01N_5/RDWR_B
IO_L01P_5/CS_B
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
IO_L01P_6
IO_L01N_6
AF2
AE1
AB4
AB3
AD2
AD1
AC2
AC1
AB2
AB1
AA4
AA3
Y6
IO_L02P_6/VRN_6
IO_L02N_6/VRP_6
IO_L03P_6
IO_L03N_6/VREF_6
IO_L04P_6
IO_L04N_6
IO_L06P_6
IO_L06N_6
IO_L19P_6
IO_L19N_6
IO_L21P_6
IO_L21N_6/VREF_6
IO_L22P_6
Y5
W6
IO_L22N_6
W7
IO_L24P_6
AA2
AA1
IO_L24N_6
IO_L25P_6
Y4
Y3
W5
W4
W2
W3
Y1
W1
V6
V7
V5
V4
V3
V2
V1
NC
NC
NC
NC
IO_L25N_6
IO_L43P_6
IO_L43N_6
IO_L45P_6
IO_L45N_6/VREF_6
IO_L46P_6
IO_L46N_6
IO_L48P_6
IO_L48N_6
IO_L49P_6
IO_L49N_6
IO_L51P_6
IO_L51N_6/VREF_6
IO_L52P_6
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Table 8: FG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank
6
Pin Description
IO_L52N_6
Pin Number No Connect in XC2V1500 No Connect in XC2V2000
U1
U7
T7
U4
U3
U6
U5
T5
T6
T8
R8
6
IO_L54P_6
6
IO_L54N_6
6
IO_L67P_6
6
IO_L67N_6
6
IO_L69P_6
6
IO_L69N_6/VREF_6
IO_L70P_6
6
6
IO_L70N_6
6
IO_L72P_6
6
IO_L72N_6
6
IO_L73P_6
T2
T1
T4
T3
R6
R5
R4
R3
R2
R1
R7
P7
P6
P5
P4
P3
NC
NC
NC
NC
NC
NC
NC
NC
6
IO_L73N_6
6
IO_L75P_6
6
IO_L75N_6/VREF_6
IO_L76P_6
6
6
IO_L76N_6
6
IO_L78P_6
6
IO_L78N_6
6
IO_L91P_6
6
IO_L91N_6
6
IO_L93P_6
6
IO_L93N_6/VREF_6
IO_L94P_6
6
6
IO_L94N_6
6
IO_L96P_6
6
IO_L96N_6
7
7
7
7
7
7
7
7
7
IO_L96P_7
IO_L96N_7
P1
N1
N4
N5
N6
N7
P8
N8
M1
IO_L94P_7
IO_L94N_7
IO_L93P_7/VREF_7
IO_L93N_7
IO_L91P_7
IO_L91N_7
IO_L78P_7
NC
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 8: FG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
Pin Description
IO_L78N_7
IO_L76P_7
Pin Number No Connect in XC2V1500 No Connect in XC2V2000
M2
M5
M6
M3
M4
M7
M8
L1
L2
L5
L6
L3
L4
K1
J1
NC
NC
NC
NC
NC
NC
NC
IO_L76N_7
IO_L75P_7/VREF_7
IO_L75N_7
IO_L73P_7
IO_L73N_7
IO_L72P_7
IO_L72N_7
IO_L70P_7
IO_L70N_7
IO_L69P_7/VREF_7
IO_L69N_7
IO_L67P_7
IO_L67N_7
IO_L54P_7
K3
K4
K5
K6
L8
L7
J2
IO_L54N_7
IO_L52P_7
IO_L52N_7
IO_L51P_7/VREF_7
IO_L51N_7
IO_L49P_7
IO_L49N_7
IO_L48P_7
H1
J3
IO_L48N_7
IO_L46P_7
J4
J5
IO_L46N_7
IO_L45P_7/VREF_7
IO_L45N_7
IO_L43P_7
J6
H5
H4
K7
J7
IO_L43N_7
IO_L25P_7
H2
H3
G1
F1
G3
G4
NC
NC
NC
NC
IO_L25N_7
IO_L24P_7
IO_L24N_7
IO_L22P_7
IO_L22N_7
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Table 8: FG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank
Pin Description
IO_L21P_7/VREF_7
IO_L21N_7
Pin Number No Connect in XC2V1500 No Connect in XC2V2000
7
7
7
7
7
7
7
7
7
7
7
7
7
7
F3
F2
H6
H7
E1
E2
D1
D2
C1
C2
E3
E4
G5
F4
IO_L19P_7
IO_L19N_7
IO_L06P_7
IO_L06N_7
IO_L04P_7
IO_L04N_7
IO_L03P_7/VREF_7
IO_L03N_7
IO_L02P_7/VRN_7
IO_L02N_7/VRP_7
IO_L01P_7
IO_L01N_7
0
0
0
0
0
0
0
1
1
1
1
1
1
1
2
2
2
2
2
2
2
3
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_3
J13
J12
J11
H10
H9
B10
B7
B17
J16
J15
J14
H18
H17
B20
N18
M18
L18
K25
K19
J19
G25
Y25
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 8: FG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank
3
3
3
3
3
3
4
4
4
4
4
4
4
5
5
5
5
5
5
5
6
6
6
6
6
6
6
7
7
7
7
7
7
7
Pin Description
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
Pin Number No Connect in XC2V1500 No Connect in XC2V2000
V19
U25
U19
T18
R18
P18
AE20
AE17
W18
W17
V16
V15
V14
AE10
AE7
W10
W9
V13
V12
V11
Y2
V8
U8
U2
T9
R9
P9
N9
M9
L9
K8
K2
J8
G2
NA
NA
CCLK
AB21
C4
PROG_B
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 8: FG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
DONE
M0
Pin Number No Connect in XC2V1500 No Connect in XC2V2000
AD22
AD4
AA5
AD5
D5
M1
M2
HSWAP_EN
TCK
E21
F5
TDI
TDO
F22
D22
AD23
F7
TMS
PWRDWN_B
DXN
DXP
C5
VBATT
RSVD
C23
C22
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
AD13
AC24
AC3
P24
N3
D24
D3
C14
W19
W8
V18
V17
V10
V9
U18
U9
K18
K9
J18
J17
J10
J9
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 8: FG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
VCCINT
VCCINT
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin Number No Connect in XC2V1500 No Connect in XC2V2000
H19
H8
AF26
AF1
AE25
AE14
AE13
AE2
AD24
AD3
AC23
AC4
AB22
AB5
AA21
AA6
U17
U16
U15
U14
U13
U12
U11
U10
T17
T16
T15
T14
T13
T12
T11
T10
R17
R16
R15
R14
R13
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 8: FG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin Number No Connect in XC2V1500 No Connect in XC2V2000
R12
R11
R10
P25
P17
P16
P15
P14
P13
P12
P11
P10
P2
N25
N17
N16
N15
N14
N13
N12
N11
N10
N2
M17
M16
M15
M14
M13
M12
M11
M10
L17
L16
L15
L14
L13
L12
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 8: FG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin Number No Connect in XC2V1500 No Connect in XC2V2000
L11
L10
K17
K16
K15
K14
K13
K12
K11
K10
F21
F6
E22
E5
D23
D4
C24
C3
B25
B14
B13
B2
A26
A1
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
FG676 Fine-Pitch BGA Package Specifications (1.00mm pitch)
Figure 4: FG676 Fine-Pitch BGA Package Specifications
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
BG575 Standard BGA Package
As shown in Table 9, XC2V1000, XC2V1500, and XC2V2000 Virtex-II devices are available in the BG575 BGA package.
Pins in the XC2V1000, XC2V1500, and XC2V2000 devices are the same, except for the pin differences in the XC2V1000
and XC2V1500 devices shown in the No Connect columns. Following this table are the BG575 Standard BGA Package
Specifications (1.27mm pitch).
Table 9: BG575 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
0
Pin Description
IO_L01N_0
Pin Number No Connect in XC2V1000 No Connect in XC2V1500
A3
A4
D5
C5
E6
D6
F7
0
IO_L01P_0
0
IO_L02N_0
0
IO_L02P_0
0
IO_L03N_0/VRP_0
IO_L03P_0/VRN_0
IO_L04N_0/VREF_0
IO_L04P_0
0
0
0
E7
G8
H9
A5
A6
B5
B6
D7
C7
F8
0
IO_L05N_0
0
IO_L05P_0
0
IO_L06N_0
0
IO_L06P_0
0
IO_L19N_0
0
IO_L19P_0
0
IO_L21N_0
0
IO_L21P_0/VREF_0
IO_L22N_0
0
0
IO_L22P_0
E8
G9
F9
0
IO_L24N_0
0
IO_L24P_0
0
IO_L49N_0
G10
H10
B7
B8
D8
C8
E9
D9
0
IO_L49P_0
0
IO_L51N_0
0
IO_L51P_0/VREF_0
IO_L52N_0
0
0
IO_L52P_0
0
IO_L54N_0
0
IO_L54P_0
0
IO_L67N_0
A8
A9
C9
NC
NC
NC
0
IO_L67P_0
0
IO_L69N_0
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 9: BG575 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
0
Pin Description
IO_L69P_0/VREF_0
IO_L70N_0
Pin Number No Connect in XC2V1000 No Connect in XC2V1500
B9
NC
NC
NC
NC
NC
NC
NC
0
F10
E10
A10
A11
C10
B10
D11
C11
G11
E11
C12
B12
E12
D12
G12
F12
H11
H12
0
IO_L70P_0
0
IO_L72N_0
0
IO_L72P_0
0
IO_L73N_0
NC
NC
0
IO_L73P_0
0
IO_L91N_0/VREF_0
IO_L91P_0
0
0
IO_L92N_0
0
IO_L92P_0
0
IO_L93N_0
0
IO_L93P_0
0
IO_L94N_0/VREF_0
IO_L94P_0
0
0
IO_L95N_0/GCLK7P
IO_L95P_0/GCLK6S
IO_L96N_0/GCLK5P
IO_L96P_0/GCLK4S
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IO_L96N_1/GCLK3P
IO_L96P_1/GCLK2S
IO_L95N_1/GCLK1P
IO_L95P_1/GCLK0S
IO_L94N_1
A13
A14
B13
C13
D13
E13
F13
G13
H13
H14
C14
D14
E14
G14
A15
A16
IO_L94P_1/VREF_1
IO_L93N_1
IO_L93P_1
IO_L92N_1
IO_L92P_1
IO_L91N_1
IO_L91P_1/VREF_1
IO_L73N_1
NC
NC
NC
NC
NC
NC
IO_L73P_1
IO_L72N_1
IO_L72P_1
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 9: BG575 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Description
IO_L70N_1
Pin Number No Connect in XC2V1000 No Connect in XC2V1500
B15
C15
E15
F15
G15
H15
B16
C16
D16
E16
F16
G16
A17
A19
B17
B18
C17
D17
F17
E17
A20
A21
B19
B20
C18
D18
C20
D20
D19
E19
E18
F18
H16
G17
NC
NC
NC
NC
NC
NC
IO_L70P_1
IO_L69N_1/VREF_1
IO_L69P_1
IO_L67N_1
IO_L67P_1
IO_L54N_1
IO_L54P_1
IO_L52N_1
IO_L52P_1
IO_L51N_1/VREF_1
IO_L51P_1
IO_L49N_1
IO_L49P_1
IO_L24N_1
IO_L24P_1
IO_L22N_1
IO_L22P_1
IO_L21N_1/VREF_1
IO_L21P_1
IO_L19N_1
IO_L19P_1
IO_L06N_1
IO_L06P_1
IO_L05N_1
IO_L05P_1
IO_L04N_1
IO_L04P_1/VREF_1
IO_L03N_1/VRP_1
IO_L03P_1/VRN_1
IO_L02N_1
IO_L02P_1
IO_L01N_1
IO_L01P_1
2
IO_L01N_2
D22
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 9: BG575 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Pin Description
IO_L01P_2
Pin Number No Connect in XC2V1000 No Connect in XC2V1500
D23
E21
E22
F21
F20
G20
G19
H18
J17
D24
E23
E24
F24
F23
G23
G21
G22
H19
H20
J18
J19
K17
K18
H23
H24
H21
H22
J24
K24
J22
J23
J20
J21
IO_L02N_2/VRP_2
IO_L02P_2/VRN_2
IO_L03N_2
IO_L03P_2/VREF_2
IO_L04N_2
IO_L04P_2
IO_L06N_2
IO_L06P_2
IO_L19N_2
IO_L19P_2
IO_L21N_2
IO_L21P_2/VREF_2
IO_L22N_2
IO_L22P_2
IO_L24N_2
IO_L24P_2
IO_L43N_2
IO_L43P_2
IO_L45N_2
IO_L45P_2/VREF_2
IO_L46N_2
IO_L46P_2
IO_L48N_2
IO_L48P_2
IO_L49N_2
IO_L49P_2
IO_L51N_2
IO_L51P_2/VREF_2
IO_L52N_2
IO_L52P_2
IO_L54N_2
IO_L54P_2
IO_L67N_2
K19
K20
L17
NC
NC
NC
IO_L67P_2
IO_L69N_2
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 9: BG575 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
Pin Description
IO_L69P_2/VREF_2
IO_L70N_2
Pin Number No Connect in XC2V1000 No Connect in XC2V1500
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
L18
K23
L24
NC
NC
NC
NC
NC
NC
NC
IO_L70P_2
IO_L72N_2
K22
L22
IO_L72P_2
IO_L73N_2
L21
NC
NC
IO_L73P_2
L20
IO_L91N_2
M23
N24
M21
M22
M19
M20
M17
M18
IO_L91P_2
IO_L93N_2
IO_L93P_2/VREF_2
IO_L94N_2
IO_L94P_2
IO_L96N_2
IO_L96P_2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO_L96N_3
IO_L96P_3
N23
N22
N20
N21
N19
N18
N17
P17
P24
R24
R23
R22
P22
P21
P20
P18
T24
U24
T23
T22
IO_L94N_3
IO_L94P_3
IO_L93N_3/VREF_3
IO_L93P_3
IO_L91N_3
IO_L91P_3
IO_L73N_3
IO_L73P_3
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IO_L72N_3
IO_L72P_3
IO_L70N_3
IO_L70P_3
IO_L69N_3/VREF_3
IO_L69P_3
IO_L67N_3
IO_L67P_3
IO_L54N_3
IO_L54P_3
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 9: BG575 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
3
Pin Description
IO_L52N_3
Pin Number No Connect in XC2V1000 No Connect in XC2V1500
T21
T20
3
IO_L52P_3
3
IO_L51N_3/VREF_3
IO_L51P_3
R20
R19
W24
W23
U23
V23
U22
U21
V22
V21
U19
U20
T19
3
3
IO_L49N_3
3
IO_L49P_3
3
IO_L48N_3
3
IO_L48P_3
3
IO_L46N_3
3
IO_L46P_3
3
IO_L45N_3/VREF_3
IO_L45P_3
3
3
IO_L43N_3
3
IO_L43P_3
3
IO_L24N_3
3
IO_L24P_3
T18
3
IO_L22N_3
R18
R17
Y24
Y23
AA24
AB24
AA23
AA22
Y22
Y21
W21
W20
V20
V19
U18
T17
3
IO_L22P_3
3
IO_L21N_3/VREF_3
IO_L21P_3
3
3
IO_L19N_3
3
IO_L19P_3
3
IO_L06N_3
3
IO_L06P_3
3
IO_L04N_3
3
IO_L04P_3
3
IO_L03N_3/VREF_3
IO_L03P_3
3
3
IO_L02N_3/VRP_3
IO_L02P_3/VRN_3
IO_L01N_3
3
3
3
IO_L01P_3
4
4
4
IO_L01N_4/DOUT
IO_L01P_4/INIT_B
IO_L02N_4/D0
AD22
AD21
AA20
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 9: BG575 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Pin Description
IO_L02P_4/D1
IO_L03N_4/D2/ALT_VRP_4
IO_L03P_4/D3/ALT_VRN_4
IO_L04N_4/VREF_4
IO_L04P_4
Pin Number No Connect in XC2V1000 No Connect in XC2V1500
AB20
Y19
AA19
W18
Y18
IO_L05N_4/VRP_4
IO_L05P_4/VRN_4
IO_L06N_4
U16
V17
AD20
AD19
AC20
AC19
AA18
AB18
AC18
AC17
AA17
AB17
Y17
IO_L06P_4
IO_L19N_4
IO_L19P_4
IO_L21N_4
IO_L21P_4/VREF_4
IO_L22N_4
IO_L22P_4
IO_L24N_4
IO_L24P_4
IO_L49N_4
IO_L49P_4
W17
IO_L51N_4
V16
IO_L51P_4/VREF_4
IO_L52N_4
W16
AD17
AD16
AB16
AC16
IO_L52P_4
IO_L54N_4
IO_L54P_4
IO_L67N_4
Y16
AA16
W15
Y15
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IO_L67P_4
IO_L69N_4
IO_L69P_4/VREF_4
IO_L70N_4
U15
IO_L70P_4
V15
IO_L72N_4
AD15
AD14
AB15
AC15
AA14
IO_L72P_4
IO_L73N_4
NC
NC
IO_L73P_4
IO_L91N_4/VREF_4
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 9: BG575 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
Pin Description
IO_L91P_4
Pin Number No Connect in XC2V1000 No Connect in XC2V1500
4
4
4
4
4
4
4
4
4
4
4
AB14
V14
IO_L92N_4
IO_L92P_4
Y14
IO_L93N_4
AB13
AC13
Y13
IO_L93P_4
IO_L94N_4/VREF_4
IO_L94P_4
AA13
V13
IO_L95N_4/GCLK3S
IO_L95P_4/GCLK2P
IO_L96N_4/GCLK1S
IO_L96P_4/GCLK0P
W13
U14
U13
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
IO_L96N_5/GCLK7S
IO_L96P_5/GCLK6P
IO_L95N_5/GCLK5S
IO_L95P_5/GCLK4P
IO_L94N_5
AD12
AD11
AC12
AB12
AA12
Y12
IO_L94P_5/VREF_5
IO_L93N_5
W12
V12
IO_L93P_5
IO_L92N_5
U12
IO_L92P_5
U11
IO_L91N_5
AB11
AA11
IO_L91P_5/VREF_5
IO_L73N_5
Y11
V11
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IO_L73P_5
IO_L72N_5
AD10
AD9
AC10
AB10
Y10
IO_L72P_5
IO_L70N_5
IO_L70P_5
IO_L69N_5/VREF_5
IO_L69P_5
W10
V10
IO_L67N_5
IO_L67P_5
U10
IO_L54N_5
AC9
AB9
IO_L54P_5
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 9: BG575 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
5
Pin Description
IO_L52N_5
Pin Number No Connect in XC2V1000 No Connect in XC2V1500
AA9
Y9
5
IO_L52P_5
5
IO_L51N_5/VREF_5
IO_L51P_5
W9
5
V9
5
IO_L49N_5
AD8
AD6
AC8
AC7
AB8
AA8
W8
5
IO_L49P_5
5
IO_L24N_5
5
IO_L24P_5
5
IO_L22N_5
5
IO_L22P_5
5
IO_L21N_5/VREF_5
IO_L21P_5
5
Y8
5
IO_L19N_5
AD5
AD4
AC6
AC5
AB7
AA7
AB5
AA5
AA6
Y6
5
IO_L19P_5
5
IO_L06N_5
5
IO_L06P_5
5
IO_L05N_5/VRP_5
IO_L05P_5/VRN_5
IO_L04N_5
5
5
5
IO_L04P_5/VREF_5
IO_L03N_5/D4/ALT_VRP_5
IO_L03P_5/D5/ALT_VRN_5
IO_L02N_5/D6
IO_L02P_5/D7
IO_L01N_5/RDWR_B
IO_L01P_5/CS_B
5
5
5
Y7
5
W7
5
V8
5
U9
6
6
6
6
6
6
6
6
6
IO_L01P_6
IO_L01N_6
AB2
AB1
AA3
AA2
Y4
IO_L02P_6/VRN_6
IO_L02N_6/VRP_6
IO_L03P_6
IO_L03N_6/VREF_6
IO_L04P_6
Y3
W4
W5
V5
IO_L04N_6
IO_L06P_6
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R
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 9: BG575 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
Pin Description
IO_L06N_6
IO_L19P_6
Pin Number No Connect in XC2V1000 No Connect in XC2V1500
V6
U7
T8
IO_L19N_6
IO_L21P_6
AA1
Y2
Y1
W1
W2
V2
V4
V3
U6
U5
T7
IO_L21N_6/VREF_6
IO_L22P_6
IO_L22N_6
IO_L24P_6
IO_L24N_6
IO_L43P_6
IO_L43N_6
IO_L45P_6
IO_L45N_6/VREF_6
IO_L46P_6
IO_L46N_6
IO_L48P_6
T6
R8
R7
U2
U1
U4
U3
T1
IO_L48N_6
IO_L49P_6
IO_L49N_6
IO_L51P_6
IO_L51N_6/VREF_6
IO_L52P_6
IO_L52N_6
IO_L54P_6
R1
T3
IO_L54N_6
IO_L67P_6
T2
T5
T4
R6
R5
P8
P7
R2
P1
R3
P3
P5
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IO_L67N_6
IO_L69P_6
IO_L69N_6/VREF_6
IO_L70P_6
IO_L70N_6
IO_L72P_6
IO_L72N_6
IO_L73P_6
NC
NC
IO_L73N_6
IO_L91P_6
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 9: BG575 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
Pin Description
IO_L91N_6
Pin Number No Connect in XC2V1000 No Connect in XC2V1500
6
6
6
6
6
6
6
P4
N4
N3
N6
N5
N8
N7
IO_L93P_6
IO_L93N_6/VREF_6
IO_L94P_6
IO_L94N_6
IO_L96P_6
IO_L96N_6
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
IO_L96P_7
IO_L96N_7
IO_L94P_7
N2
M1
M2
M3
M4
M5
M6
M7
IO_L94N_7
IO_L93P_7/VREF_7
IO_L93N_7
IO_L91P_7
IO_L91N_7
IO_L73P_7
M8
L8
L1
K1
K2
K3
L3
L4
L5
L7
J1
H1
J2
J3
J4
J5
K5
K6
F1
F2
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IO_L73N_7
IO_L72P_7
IO_L72N_7
IO_L70P_7
IO_L70N_7
IO_L69P_7/VREF_7
IO_L69N_7
IO_L67P_7
IO_L67N_7
IO_L54P_7
IO_L54N_7
IO_L52P_7
IO_L52N_7
IO_L51P_7/VREF_7
IO_L51N_7
IO_L49P_7
IO_L49N_7
IO_L48P_7
IO_L48N_7
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 9: BG575 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
7
Pin Description
IO_L46P_7
Pin Number No Connect in XC2V1000 No Connect in XC2V1500
H2
G2
H3
H4
G3
G4
H5
H6
J6
7
IO_L46N_7
7
IO_L45P_7/VREF_7
IO_L45N_7
7
7
IO_L43P_7
7
IO_L43N_7
7
IO_L24P_7
7
IO_L24N_7
7
IO_L22P_7
7
IO_L22N_7
J7
7
IO_L21P_7/VREF_7
IO_L21N_7
K7
K8
E1
E2
D2
D3
E3
E4
F4
F5
G5
G6
H7
J8
7
7
IO_L19P_7
7
IO_L19N_7
7
IO_L06P_7
7
IO_L06N_7
7
IO_L04P_7
7
IO_L04N_7
7
IO_L03P_7/VREF_7
IO_L03N_7
7
7
IO_L02P_7/VRN_7
IO_L02N_7/VRP_7
IO_L01P_7
7
7
7
IO_L01N_7
0
0
0
0
0
0
1
1
1
1
1
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
J12
J11
J10
F11
C6
B11
J15
J14
J13
F14
C19
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R
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 9: BG575 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
1
2
2
2
2
2
2
3
3
3
3
3
3
4
4
4
4
4
4
5
5
5
5
5
5
6
6
6
6
6
6
7
7
7
7
7
Pin Description
VCCO_1
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
Pin Number No Connect in XC2V1000 No Connect in XC2V1500
B14
M16
L23
L19
L16
K16
F22
W22
R16
P23
P19
P16
N16
AC14
AB19
W14
T15
T14
T13
AC11
AB6
W11
T12
T11
T10
W3
R9
P9
P6
P2
N9
M9
L9
L6
L2
K9
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 9: BG575 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
Pin Description
Pin Number No Connect in XC2V1000 No Connect in XC2V1500
7
VCCO_7
F3
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
CCLK
PROG_B
DONE
M0
AB23
C1
AB21
AC4
AB4
AD3
C2
M1
M2
HSWAP_EN
TCK
C23
D1
TDI
TDO
C24
C21
AC21
B4
TMS
PWRDWN_B
DXN
DXP
C4
VBATT
RSVD
B21
A22
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
AD13
AC22
AC3
N1
M24
B22
B3
A12
U17
U8
T16
T9
R15
R14
R13
R12
R11
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Advance Product Specification
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R
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 9: BG575 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
GND
Pin Number No Connect in XC2V1000 No Connect in XC2V1500
R10
P15
P10
N15
N10
M15
M10
L15
L10
K15
K14
K13
K12
K11
K10
J16
J9
H17
H8
AD24
AD23
AD18
AD7
AD2
AD1
AC24
AC23
AC2
AC1
AB22
AB3
AA21
AA15
AA10
AA4
Y20
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 9: BG575 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin Number No Connect in XC2V1000 No Connect in XC2V1500
Y5
W19
W6
V24
V18
V7
V1
R21
R4
P14
P13
P12
P11
N14
N13
N12
N11
M14
M13
M12
M11
L14
L13
L12
L11
K21
K4
G24
G18
G7
G1
F19
F6
E20
E5
D21
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 9: BG575 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
Pin Number No Connect in XC2V1000 No Connect in XC2V1500
D15
D10
D4
GND
GND
GND
C22
C3
GND
GND
B24
B23
B2
GND
GND
GND
B1
GND
A24
A23
A18
A7
GND
GND
GND
GND
A2
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BG575 Standard BGA Package Specifications (1.27mm pitch)
Figure 5: BG575 Standard BGA Package Specifications
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
BG728 Standard BGA Package
As shown in Table 10, XC2V3000 Virtex-II devices are available in the BG728 BGA package. Following this table are the
BG728 Standard BGA Package Specifications (1.27mm pitch).
Table 10: BG728 BGA — XC2V3000
Bank
0
Pin Description
IO_L01N_0
Pin Number
B3
0
IO_L01P_0
A3
0
IO_L02N_0
B4
0
IO_L02P_0
A4
0
IO_L03N_0/VRP_0
IO_L03P_0/VRN_0
IO_L04N_0/VREF_0
IO_L04P_0
C5
0
C6
0
B5
0
A5
0
IO_L05N_0
E6
0
IO_L05P_0
D6
0
IO_L06N_0
B6
0
IO_L06P_0
A6
0
IO_L19N_0
E7
0
IO_L19P_0
D8
0
IO_L21N_0
F8
0
IO_L21P_0/VREF_0
IO_L22N_0
E8
0
C7
0
IO_L22P_0
C8
0
IO_L24N_0
B7
0
IO_L24P_0
A7
0
IO_L25N_0
H9
0
IO_L25P_0
J9
0
IO_L27N_0
F9
0
IO_L27P_0/VREF_0
IO_L28N_0
G9
E9
0
0
IO_L28P_0
D9
0
IO_L30N_0
C9
0
IO_L30P_0
B9
0
IO_L49N_0
A8
0
IO_L49P_0
A9
0
IO_L51N_0
G10
H10
F10
0
IO_L51P_0/VREF_0
IO_L52N_0
0
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 10: BG728 BGA — XC2V3000
Bank
0
Pin Description
IO_L52P_0
Pin Number
E10
D10
C10
B10
A10
G11
H11
F11
F12
0
IO_L54N_0
0
IO_L54P_0
0
IO_L67N_0
0
IO_L67P_0
0
IO_L69N_0
0
IO_L69P_0/VREF_0
IO_L70N_0
0
0
IO_L70P_0
0
IO_L72N_0
D11
C11
B11
A11
H12
J12
0
IO_L72P_0
0
IO_L73N_0
0
IO_L73P_0
0
IO_L75N_0
0
IO_L75P_0/VREF_0
IO_L76N_0
0
E12
D12
B12
A12
J13
0
IO_L76P_0
0
IO_L78N_0
0
IO_L78P_0
0
IO_L91N_0/VREF_0
IO_L91P_0
0
H13
G13
F13
0
IO_L92N_0
0
IO_L92P_0
0
IO_L93N_0
E13
D13
B13
A13
C13
C14
F14
0
IO_L93P_0
0
IO_L94N_0/VREF_0
IO_L94P_0
0
0
IO_L95N_0/GCLK7P
IO_L95P_0/GCLK6S
IO_L96N_0/GCLK5P
IO_L96P_0/GCLK4S
0
0
0
E14
1
1
1
1
IO_L96N_1/GCLK3P
IO_L96P_1/GCLK2S
IO_L95N_1/GCLK1P
IO_L95P_1/GCLK0S
G14
H14
A15
B15
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 10: BG728 BGA — XC2V3000
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Description
IO_L94N_1
Pin Number
C15
D15
E15
F15
G15
H15
J15
IO_L94P_1/VREF_1
IO_L93N_1
IO_L93P_1
IO_L92N_1
IO_L92P_1
IO_L91N_1
IO_L91P_1/VREF_1
IO_L78N_1
J16
A16
B16
D16
E16
F16
F17
H16
H17
A17
B17
C17
D17
G18
G17
A18
B18
C18
D18
E18
F18
H19
H18
A19
A20
B19
C19
D19
E19
IO_L78P_1
IO_L76N_1
IO_L76P_1
IO_L75N_1/VREF_1
IO_L75P_1
IO_L73N_1
IO_L73P_1
IO_L72N_1
IO_L72P_1
IO_L70N_1
IO_L70P_1
IO_L69N_1/VREF_1
IO_L69P_1
IO_L67N_1
IO_L67P_1
IO_L54N_1
IO_L54P_1
IO_L52N_1
IO_L52P_1
IO_L51N_1/VREF_1
IO_L51P_1
IO_L49N_1
IO_L49P_1
IO_L30N_1
IO_L30P_1
IO_L28N_1
IO_L28P_1
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Table 10: BG728 BGA — XC2V3000
Bank
1
Pin Description
IO_L27N_1/VREF_1
IO_L27P_1
Pin Number
F19
1
G19
J19
1
IO_L25N_1
1
IO_L25P_1
J20
1
IO_L24N_1
C20
C21
D20
E21
E20
F20
1
IO_L24P_1
1
IO_L22N_1
1
IO_L22P_1
1
IO_L21N_1/VREF_1
IO_L21P_1
1
1
IO_L19N_1
A21
B21
A22
B22
C22
C23
D22
E22
A23
B23
A24
B24
A25
B25
1
IO_L19P_1
1
IO_L06N_1
1
IO_L06P_1
1
IO_L05N_1
1
IO_L05P_1
1
IO_L04N_1
1
IO_L04P_1/VREF_1
IO_L03N_1/VRP_1
IO_L03P_1/VRN_1
IO_L02N_1
1
1
1
1
IO_L02P_1
1
IO_L01N_1
1
IO_L01P_1
2
2
2
2
2
2
2
2
2
2
2
IO_L01N_2
IO_L01P_2
C27
D27
D25
D26
E24
E25
E26
E27
F23
F24
F25
IO_L02N_2/VRP_2
IO_L02P_2/VRN_2
IO_L03N_2
IO_L03P_2/VREF_2
IO_L04N_2
IO_L04P_2
IO_L06N_2
IO_L06P_2
IO_L19N_2
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Table 10: BG728 BGA — XC2V3000
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Pin Description
IO_L19P_2
Pin Number
F26
F27
G27
G23
H23
G25
G26
H21
J21
IO_L21N_2
IO_L21P_2/VREF_2
IO_L22N_2
IO_L22P_2
IO_L24N_2
IO_L24P_2
IO_L25N_2
IO_L25P_2
IO_L27N_2
H22
J22
IO_L27P_2/VREF_2
IO_L28N_2
H24
H25
H27
J27
IO_L28P_2
IO_L30N_2
IO_L30P_2
IO_L43N_2
J23
IO_L43P_2
J24
IO_L45N_2
J25
IO_L45P_2/VREF_2
IO_L46N_2
J26
K20
K21
K22
K23
K24
K25
K26
K27
L20
IO_L46P_2
IO_L48N_2
IO_L48P_2
IO_L49N_2
IO_L49P_2
IO_L51N_2
IO_L51P_2/VREF_2
IO_L52N_2
IO_L52P_2
M20
L21
IO_L54N_2
IO_L54P_2
L22
IO_L67N_2
L24
IO_L67P_2
L25
IO_L69N_2
L26
IO_L69P_2/VREF_2
IO_L70N_2
L27
M19
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Table 10: BG728 BGA — XC2V3000
Bank
2
Pin Description
IO_L70P_2
Pin Number
N19
2
IO_L72N_2
M22
M23
M24
N24
2
IO_L72P_2
2
IO_L73N_2
2
IO_L73P_2
2
IO_L75N_2
M26
M27
N20
2
IO_L75P_2/VREF_2
IO_L76N_2
2
2
IO_L76P_2
N21
2
IO_L78N_2
N22
2
IO_L78P_2
N23
2
IO_L91N_2
N25
2
IO_L91P_2
P25
2
IO_L93N_2
N26
2
IO_L93P_2/VREF_2
IO_L94N_2
N27
2
P20
2
IO_L94P_2
P21
2
IO_L96N_2
P22
2
IO_L96P_2
P23
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO_L96N_3
IO_L96P_3
R27
R26
R25
R24
R23
T23
R22
R21
R20
R19
T27
T26
T24
U24
T22
U22
IO_L94N_3
IO_L94P_3
IO_L93N_3/VREF_3
IO_L93P_3
IO_L91N_3
IO_L91P_3
IO_L78N_3
IO_L78P_3
IO_L76N_3
IO_L76P_3
IO_L75N_3/VREF_3
IO_L75P_3
IO_L73N_3
IO_L73P_3
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 10: BG728 BGA — XC2V3000
Bank
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Description
IO_L72N_3
Pin Number
T20
IO_L72P_3
T19
IO_L70N_3
U27
IO_L70P_3
U26
IO_L69N_3/VREF_3
IO_L69P_3
U25
V25
IO_L67N_3
U21
IO_L67P_3
U20
IO_L54N_3
V27
IO_L54P_3
V26
IO_L52N_3
V24
IO_L52P_3
V23
IO_L51N_3/VREF_3
IO_L51P_3
V22
W22
V21
IO_L49N_3
IO_L49P_3
V20
IO_L48N_3
W27
Y27
IO_L48P_3
IO_L46N_3
W26
W25
W24
W23
W21
W20
W19
Y19
IO_L46P_3
IO_L45N_3/VREF_3
IO_L45P_3
IO_L43N_3
IO_L43P_3
IO_L28N_3
IO_L28P_3
IO_L27N_3/VREF_3
IO_L27P_3
Y25
Y24
IO_L25N_3
Y23
IO_L25P_3
AA23
Y22
IO_L24N_3
IO_L24P_3
Y21
IO_L22N_3
AA27
AB27
AA26
AA25
IO_L22P_3
IO_L21N_3/VREF_3
IO_L21P_3
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Table 10: BG728 BGA — XC2V3000
Bank
Pin Description
IO_L19N_3
Pin Number
AB26
3
3
3
3
3
3
3
3
3
3
3
3
IO_L19P_3
AB25
IO_L06N_3
AB24
IO_L06P_3
AB23
IO_L04N_3
AC27
AC26
AC25
AC24
AD27
AE27
IO_L04P_3
IO_L03N_3/VREF_3
IO_L03P_3
IO_L02N_3/VRP_3
IO_L02P_3/VRN_3
IO_L01N_3
AD26
AD25
IO_L01P_3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
IO_L01N_4/DOUT
IO_L01P_4/INIT_B
IO_L02N_4/D0
IO_L02P_4/D1
IO_L03N_4/D2/ALT_VRP_4
IO_L03P_4/D3/ALT_VRN_4
IO_L04N_4/VREF_4
IO_L04P_4
AF25
AG25
AF24
AG24
AD23
AE23
AF23
AG23
AD22
AE22
AF22
AG22
AC21
AB21
AE21
AE20
AF21
AG21
AB20
AA20
AC20
AD20
AG20
IO_L05N_4/VRP_4
IO_L05P_4/VRN_4
IO_L06N_4
IO_L06P_4
IO_L19N_4
IO_L19P_4
IO_L21N_4
IO_L21P_4/VREF_4
IO_L22N_4
IO_L22P_4
IO_L24N_4
IO_L24P_4
IO_L25N_4
IO_L25P_4
IO_L27N_4
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 10: BG728 BGA — XC2V3000
Bank
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Pin Description
IO_L27P_4/VREF_4
IO_L28N_4
Pin Number
AG19
AB19
AA19
AC19
AD19
AE19
AF19
AA18
Y18
IO_L28P_4
IO_L30N_4
IO_L30P_4
IO_L49N_4
IO_L49P_4
IO_L51N_4
IO_L51P_4/VREF_4
IO_L52N_4
AB18
AC18
AD18
AE18
AF18
AG18
AA17
Y17
IO_L52P_4
IO_L54N_4
IO_L54P_4
IO_L67N_4
IO_L67P_4
IO_L69N_4
IO_L69P_4/VREF_4
IO_L70N_4
AB17
AB16
AD17
AE17
AF17
AG17
Y16
IO_L70P_4
IO_L72N_4
IO_L72P_4
IO_L73N_4
IO_L73P_4
IO_L75N_4
IO_L75P_4/VREF_4
IO_L76N_4
W16
AC16
AD16
AF16
AG16
W15
IO_L76P_4
IO_L78N_4
IO_L78P_4
IO_L91N_4/VREF_4
IO_L91P_4
Y15
IO_L92N_4
AB15
AA15
AC15
AD15
AE15
IO_L92P_4
IO_L93N_4
IO_L93P_4
IO_L94N_4/VREF_4
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Table 10: BG728 BGA — XC2V3000
Bank
Pin Description
IO_L94P_4
Pin Number
AE14
4
4
4
4
4
IO_L95N_4/GCLK3S
IO_L95P_4/GCLK2P
IO_L96N_4/GCLK1S
IO_L96P_4/GCLK0P
AF15
AG15
Y14
AA14
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
IO_L96N_5/GCLK7S
IO_L96P_5/GCLK6P
IO_L95N_5/GCLK5S
IO_L95P_5/GCLK4P
IO_L94N_5
AC14
AB14
AG13
AF13
AE13
AD13
AC13
AB13
AA13
Y13
IO_L94P_5/VREF_5
IO_L93N_5
IO_L93P_5
IO_L92N_5
IO_L92P_5
IO_L91N_5
W13
IO_L91P_5/VREF_5
IO_L78N_5
W12
AG12
AF12
AD12
AC12
AB12
AB11
Y12
IO_L78P_5
IO_L76N_5
IO_L76P_5
IO_L75N_5/VREF_5
IO_L75P_5
IO_L73N_5
IO_L73P_5
Y11
IO_L72N_5
AG11
AF11
AE11
AD11
AA10
AA11
AG10
AF10
AE10
AD10
IO_L72P_5
IO_L70N_5
IO_L70P_5
IO_L69N_5/VREF_5
IO_L69P_5
IO_L67N_5
IO_L67P_5
IO_L54N_5
IO_L54P_5
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 10: BG728 BGA — XC2V3000
Bank
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
Pin Description
IO_L52N_5
Pin Number
AC10
AB10
Y9
IO_L52P_5
IO_L51N_5/VREF_5
IO_L51P_5
Y10
IO_L49N_5
AG9
AG8
AF9
IO_L49P_5
IO_L30N_5
IO_L30P_5
AE9
AD9
AC9
AB9
AA9
AE8
AE7
AD8
AC8
AB8
AA8
AG7
AF7
IO_L28N_5
IO_L28P_5
IO_L27N_5/VREF_5
IO_L27P_5
IO_L25N_5
IO_L25P_5
IO_L24N_5
IO_L24P_5
IO_L22N_5
IO_L22P_5
IO_L21N_5/VREF_5
IO_L21P_5
IO_L19N_5
AC7
AB7
AG6
AF6
IO_L19P_5
IO_L06N_5
IO_L06P_5
IO_L05N_5/VRP_5
IO_L05P_5/VRN_5
IO_L04N_5
AE6
AD6
AG5
AF5
IO_L04P_5/VREF_5
IO_L03N_5/D4/ALT_VRP_5
IO_L03P_5/D5/ALT_VRN_5
IO_L02N_5/D6
IO_L02P_5/D7
IO_L01N_5/RDWR_B
IO_L01P_5/CS_B
AE5
AD5
AG4
AF4
AG3
AF3
6
IO_L01P_6
AE1
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Table 10: BG728 BGA — XC2V3000
Bank
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
Pin Description
IO_L01N_6
Pin Number
AD1
AD3
AD2
AC4
AC3
AC2
AC1
AB5
AB4
AB3
AB2
AB1
AA1
AA5
AA6
AA3
AA2
Y5
IO_L02P_6/VRN_6
IO_L02N_6/VRP_6
IO_L03P_6
IO_L03N_6/VREF_6
IO_L04P_6
IO_L04N_6
IO_L06P_6
IO_L06N_6
IO_L19P_6
IO_L19N_6
IO_L21P_6
IO_L21N_6/VREF_6
IO_L22P_6
IO_L22N_6
IO_L24P_6
IO_L24N_6
IO_L25P_6
IO_L25N_6
Y6
IO_L27P_6
Y4
IO_L27N_6/VREF_6
IO_L28P_6
Y3
Y1
IO_L28N_6
W1
IO_L43P_6
W8
IO_L43N_6
W9
IO_L45P_6
W6
IO_L45N_6/VREF_6
IO_L46P_6
W7
W5
IO_L46N_6
W4
IO_L48P_6
W3
IO_L48N_6
W2
IO_L49P_6
V7
IO_L49N_6
V8
IO_L51P_6
V5
IO_L51N_6/VREF_6
IO_L52P_6
V6
V4
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 10: BG728 BGA — XC2V3000
Bank
6
Pin Description
IO_L52N_6
Pin Number
V3
6
IO_L54P_6
V2
6
IO_L54N_6
V1
6
IO_L67P_6
U8
T8
6
IO_L67N_6
6
IO_L69P_6
U6
U7
U4
U3
U2
U1
T9
6
IO_L69N_6/VREF_6
IO_L70P_6
6
6
IO_L70N_6
IO_L72P_6
6
6
IO_L72N_6
IO_L73P_6
6
6
IO_L73N_6
IO_L75P_6
R9
T5
6
6
IO_L75N_6/VREF_6
IO_L76P_6
T6
6
T4
6
IO_L76N_6
IO_L78P_6
R4
T2
6
6
IO_L78N_6
T1
6
IO_L91P_6
R7
R8
R5
R6
R3
P3
6
IO_L91N_6
IO_L93P_6
6
6
IO_L93N_6/VREF_6
IO_L94P_6
6
6
IO_L94N_6
IO_L96P_6
6
R2
R1
6
IO_L96N_6
7
7
7
7
7
7
7
7
IO_L96P_7
IO_L96N_7
P5
P6
P7
P8
N1
N2
N3
N4
IO_L94P_7
IO_L94N_7
IO_L93P_7/VREF_7
IO_L93N_7
IO_L91P_7
IO_L91N_7
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Table 10: BG728 BGA — XC2V3000
Bank
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
Pin Description
IO_L78P_7
Pin Number
N6
N7
N9
N8
N5
M6
M1
M2
M4
M5
M8
M9
L1
IO_L78N_7
IO_L76P_7
IO_L76N_7
IO_L75P_7/VREF_7
IO_L75N_7
IO_L73P_7
IO_L73N_7
IO_L72P_7
IO_L72N_7
IO_L70P_7
IO_L70N_7
IO_L69P_7/VREF_7
IO_L69N_7
IO_L67P_7
L2
L3
IO_L67N_7
IO_L54P_7
L4
K1
K2
K4
K5
L6
IO_L54N_7
IO_L52P_7
IO_L52N_7
IO_L51P_7/VREF_7
IO_L51N_7
IO_L49P_7
L7
K6
K7
L8
IO_L49N_7
IO_L48P_7
IO_L48N_7
IO_L46P_7
K8
J1
IO_L46N_7
IO_L45P_7/VREF_7
IO_L45N_7
IO_L43P_7
H1
J2
J3
K3
J4
IO_L43N_7
IO_L30P_7
H3
H4
J5
IO_L30N_7
IO_L28P_7
IO_L28N_7
J6
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 10: BG728 BGA — XC2V3000
Bank
7
Pin Description
IO_L27P_7/VREF_7
IO_L27N_7
Pin Number
H5
7
H6
7
IO_L25P_7
J7
7
IO_L25N_7
J8
7
IO_L24P_7
G1
F1
7
IO_L24N_7
7
IO_L22P_7
G2
G3
F2
7
IO_L22N_7
7
IO_L21P_7/VREF_7
IO_L21N_7
7
F3
7
IO_L19P_7
G5
G6
F4
7
IO_L19N_7
7
IO_L06P_7
7
IO_L06N_7
F5
7
IO_L04P_7
E1
7
IO_L04N_7
E2
7
IO_L03P_7/VREF_7
IO_L03N_7
D1
7
C1
7
IO_L02P_7/VRN_7
IO_L02N_7/VRP_7
IO_L01P_7
E3
7
E4
7
D2
7
IO_L01N_7
D3
0
0
0
0
0
0
0
0
1
1
1
1
1
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
K13
K12
K11
J11
J10
G12
D7
C12
K17
K16
K15
J18
J17
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 10: BG728 BGA — XC2V3000
Bank
1
1
1
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
6
Pin Description
VCCO_1
VCCO_1
VCCO_1
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_6
Pin Number
G16
D21
C16
N18
M25
M21
M18
L19
L18
K19
G24
AA24
V19
U19
U18
T25
T21
T18
R18
AE16
AD21
AA16
W18
W17
V17
V16
V15
AE12
AD7
AA12
W11
W10
V13
V12
V11
AA4
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 10: BG728 BGA — XC2V3000
Bank
Pin Description
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
Pin Number
V9
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
U10
U9
T10
T7
T3
R10
M10
M7
M3
L10
L9
K9
G4
N10
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
CCLK
PROG_B
DONE
M0
AA22
C4
AC22
AC6
Y7
M1
M2
AE4
D5
HSWAP_EN
TCK
G20
H7
TDI
TDO
G22
F21
AE24
G8
TMS
PWRDWN_B
DXN
DXP
F7
VBATT
RSVD
D23
C24
NA
NA
NA
VCCAUX
VCCAUX
VCCAUX
AF14
AE26
AE2
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 10: BG728 BGA — XC2V3000
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
Pin Number
P26
P2
C26
C2
B14
V18
V14
V10
U17
U16
U15
U14
U13
U12
U11
T17
T11
R17
R11
P18
P17
P11
P10
N17
N11
M17
M11
L17
L16
L15
L14
L13
L12
L11
K18
K14
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 10: BG728 BGA — XC2V3000
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
VCCINT
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin Number
K10
AG27
AG26
AG14
AG2
AG1
AF27
AF26
AF20
AF8
AF2
AF1
AE25
AE3
AD24
AD14
AD4
AC23
AC17
AC11
AC5
AB22
AB6
AA21
AA7
Y26
Y20
Y8
Y2
W14
U23
U5
T16
T15
T14
T13
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 10: BG728 BGA — XC2V3000
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin Number
T12
R16
R15
R14
R13
R12
P27
P24
P19
P16
P15
P14
P13
P12
P9
P4
P1
N16
N15
N14
N13
N12
M16
M15
M14
M13
M12
L23
L5
J14
H26
H20
H8
H2
G21
G7
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 10: BG728 BGA — XC2V3000
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
Pin Number
F22
F6
GND
GND
E23
E17
E11
E5
GND
GND
GND
GND
D24
D14
D4
GND
GND
GND
C25
C3
GND
GND
B27
B26
B20
B8
GND
GND
GND
GND
B2
GND
B1
GND
A27
A26
A14
A2
GND
GND
GND
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
BG728 Standard BGA Package Specifications (1.27mm pitch)
Figure 6: BG728 Standard BGA Package Specifications
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
FF896 Flip-Chip Fine-Pitch BGA Package
As shown in Table 11, XC2V1000, XC2V1500, and XC2V2000 Virtex-II devices are available in the FF896 flip-chip fine-pitch
BGA package. Pins in the XC2V1000, XC2V1500, and XC2V2000 devices are the same, except for the pin differences in the
XC2V1000 and XC2V1500 devices shown in the No Connect columns. Following this table are the FF896 Flip-Chip
Fine-Pitch BGA Package Specifications (1.00mm pitch).
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
0
Pin Description
IO_L01N_0
Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
B27
A27
F24
E24
C26
C25
A26
A25
F23
F22
C24
D25
A24
B25
G22
G21
D24
D23
B23
B24
H21
H20
E22
E23
A22
B22
F21
F20
C23
C22
B20
B21
0
IO_L01P_0
0
IO_L02N_0
0
IO_L02P_0
0
IO_L03N_0/VRP_0
IO_L03P_0/VRN_0
IO_L04N_0/VREF_0
IO_L04P_0
0
0
0
0
IO_L05N_0
0
IO_L05P_0
0
IO_L06N_0
0
IO_L06P_0
0
IO_L19N_0
0
IO_L19P_0
0
IO_L20N_0
0
IO_L20P_0
0
IO_L21N_0
0
IO_L21P_0/VREF_0
IO_L22N_0
0
0
IO_L22P_0
0
IO_L23N_0
0
IO_L23P_0
0
IO_L24N_0
0
IO_L24P_0
0
IO_L49N_0
0
IO_L49P_0
0
IO_L50N_0
0
IO_L50P_0
0
IO_L51N_0
0
IO_L51P_0/VREF_0
IO_L52N_0
0
0
IO_L52P_0
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pin Description
IO_L53N_0
Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
G20
G19
D21
D22
IO_L53P_0
IO_L54N_0
IO_L54P_0
IO_L67N_0
E20
E21
H19
H18
D20
D19
A20
A21
F19
F18
C19
C20
B18
B19
G18
H17
E18
D18
A18
A19
J17
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IO_L67P_0
IO_L68N_0
IO_L68P_0
IO_L69N_0
IO_L69P_0/VREF_0
IO_L70N_0
IO_L70P_0
IO_L71N_0
IO_L71P_0
IO_L72N_0
IO_L72P_0
IO_L73N_0
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IO_L73P_0
IO_L74N_0
IO_L74P_0
IO_L75N_0
IO_L75P_0/VREF_0
IO_L76N_0
IO_L76P_0
IO_L77N_0
IO_L77P_0
J16
IO_L78N_0
E16
E17
B17
B16
F17
F16
D16
D17
A17
A16
H16
IO_L78P_0
IO_L91N_0/VREF_0
IO_L91P_0
IO_L92N_0
IO_L92P_0
IO_L93N_0
IO_L93P_0
IO_L94N_0/VREF_0
IO_L94P_0
IO_L95N_0/GCLK7P
DS031-4 (v1.8) October 7, 2002
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
Pin Description
Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
0
0
0
IO_L95P_0/GCLK6S
IO_L96N_0/GCLK5P
IO_L96P_0/GCLK4S
G16
C17
C16
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IO_L96N_1/GCLK3P
IO_L96P_1/GCLK2S
IO_L95N_1/GCLK1P
IO_L95P_1/GCLK0S
IO_L94N_1
C15
C14
F15
F14
B15
B14
D14
D15
G15
H15
A14
A13
IO_L94P_1/VREF_1
IO_L93N_1
IO_L93P_1
IO_L92N_1
IO_L92P_1
IO_L91N_1
IO_L91P_1/VREF_1
IO_L78N_1
E14
E15
J15
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IO_L78P_1
IO_L77N_1
IO_L77P_1
J14
IO_L76N_1
B12
B13
D13
E13
H14
H13
A11
A12
C11
C12
F13
F12
B10
B11
D12
D11
G13
IO_L76P_1
IO_L75N_1/VREF_1
IO_L75P_1
IO_L74N_1
IO_L74P_1
IO_L73N_1
IO_L73P_1
IO_L72N_1
IO_L72P_1
IO_L71N_1
IO_L71P_1
IO_L70N_1
IO_L70P_1
IO_L69N_1/VREF_1
IO_L69P_1
IO_L68N_1
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Description
IO_L68P_1
Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
G12
A9
NC
NC
NC
IO_L67N_1
IO_L67P_1
A10
E10
E11
H12
H11
D9
IO_L54N_1
IO_L54P_1
IO_L53N_1
IO_L53P_1
IO_L52N_1
IO_L52P_1
D10
C9
IO_L51N_1/VREF_1
IO_L51P_1
C8
IO_L50N_1
F11
F10
B8
IO_L50P_1
IO_L49N_1
IO_L49P_1
B9
IO_L24N_1
E8
IO_L24P_1
E9
IO_L23N_1
G11
H10
B7
IO_L23P_1
IO_L22N_1
IO_L22P_1
A7
IO_L21N_1/VREF_1
IO_L21P_1
D8
E7
IO_L20N_1
G10
G9
A5
IO_L20P_1
IO_L19N_1
IO_L19P_1
A6
IO_L06N_1
C6
IO_L06P_1
C7
IO_L05N_1
F9
IO_L05P_1
G8
B6
IO_L04N_1
IO_L04P_1/VREF_1
IO_L03N_1/VRP_1
IO_L03P_1/VRN_1
IO_L02N_1
C5
D7
D6
F8
IO_L02P_1
F7
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
Pin Description
IO_L01N_1
Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
1
1
B4
A4
IO_L01P_1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO_L01N_2
IO_L01P_2
C1
B1
H9
H8
D3
E3
D2
C2
G7
H7
F4
E4
E1
D1
G6
H6
F5
G5
G2
F2
J8
IO_L02N_2/VRP_2
IO_L02P_2/VRN_2
IO_L03N_2
IO_L03P_2/VREF_2
IO_L04N_2
IO_L04P_2
IO_L05N_2
IO_L05P_2
IO_L06N_2
IO_L06P_2
IO_L19N_2
IO_L19P_2
IO_L20N_2
IO_L20P_2
IO_L21N_2
IO_L21P_2/VREF_2
IO_L22N_2
IO_L22P_2
IO_L23N_2
IO_L23P_2
J7
IO_L24N_2
G3
F3
G1
F1
K8
L8
IO_L24P_2
IO_L43N_2
IO_L43P_2
IO_L44N_2
IO_L44P_2
IO_L45N_2
G4
H4
J2
IO_L45P_2/VREF_2
IO_L46N_2
IO_L46P_2
H2
J6
IO_L47N_2
IO_L47P_2
K6
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Pin Description
IO_L48N_2
IO_L48P_2
IO_L49N_2
IO_L49P_2
IO_L50N_2
IO_L50P_2
IO_L51N_2
IO_L51P_2/VREF_2
IO_L52N_2
IO_L52P_2
IO_L53N_2
IO_L53P_2
IO_L54N_2
IO_L54P_2
IO_L67N_2
IO_L67P_2
IO_L68N_2
IO_L68P_2
IO_L69N_2
IO_L69P_2/VREF_2
IO_L70N_2
IO_L70P_2
IO_L71N_2
IO_L71P_2
IO_L72N_2
IO_L72P_2
IO_L73N_2
IO_L73P_2
IO_L74N_2
IO_L74P_2
IO_L75N_2
IO_L75P_2/VREF_2
IO_L76N_2
IO_L76P_2
IO_L77N_2
IO_L77P_2
IO_L78N_2
Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
J5
H5
J3
H3
K7
L7
J4
K4
K1
J1
L6
M6
L5
K5
L2
K2
M8
N8
L4
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
M4
M1
L1
M7
N7
M3
L3
N2
M2
N6
P6
N5
N4
P1
N1
P9
R9
R5
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DS031-4 (v1.8) October 7, 2002
Advance Product Specification
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
Pin Description
IO_L78P_2
Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
2
2
2
2
2
2
2
2
2
2
2
2
2
P5
R2
P2
P8
R8
P4
R4
R1
T2
R7
R6
R3
P3
NC
NC
IO_L91N_2
IO_L91P_2
IO_L92N_2
IO_L92P_2
IO_L93N_2
IO_L93P_2/VREF_2
IO_L94N_2
IO_L94P_2
IO_L95N_2
IO_L95P_2
IO_L96N_2
IO_L96P_2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO_L96N_3
IO_L96P_3
IO_L95N_3
IO_L95P_3
IO_L94N_3
IO_L94P_3
IO_L93N_3/VREF_3
IO_L93P_3
IO_L92N_3
IO_L92P_3
IO_L91N_3
IO_L91P_3
IO_L78N_3
IO_L78P_3
IO_L77N_3
IO_L77P_3
IO_L76N_3
IO_L76P_3
IO_L75N_3/VREF_3
IO_L75P_3
IO_L74N_3
IO_L74P_3
IO_L73N_3
T7
T6
U1
V1
T3
U3
T8
U8
U2
V2
T4
U4
U9
T9
W1
Y1
T5
U5
U6
V6
W2
Y2
V4
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
Bank
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Description
IO_L73P_3
IO_L72N_3
IO_L72P_3
IO_L71N_3
IO_L71P_3
IO_L70N_3
IO_L70P_3
IO_L69N_3/VREF_3
IO_L69P_3
IO_L68N_3
IO_L68P_3
IO_L67N_3
IO_L67P_3
IO_L54N_3
IO_L54P_3
IO_L53N_3
IO_L53P_3
IO_L52N_3
IO_L52P_3
IO_L51N_3/VREF_3
IO_L51P_3
IO_L50N_3
IO_L50P_3
IO_L49N_3
IO_L49P_3
IO_L48N_3
IO_L48P_3
IO_L47N_3
IO_L47P_3
IO_L46N_3
IO_L46P_3
IO_L45N_3/VREF_3
IO_L45P_3
IO_L44N_3
IO_L44P_3
IO_L43N_3
IO_L43P_3
W4
W7
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
V7
V5
W6
W3
Y3
V8
W8
AA1
AB1
Y4
AA4
AA6
Y6
AA2
AB2
Y5
AA5
Y8
AA8
AC2
AD2
Y7
AA7
AC6
AB6
AD1
AE1
AB3
AC3
AB7
AC7
AB4
AC4
AB5
AC5
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Advance Product Specification
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
3
Pin Description
IO_L24N_3
Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
AC8
AB8
AE2
AF3
AD3
AE3
AD6
AD7
AF1
AG1
AD4
AE4
AD8
AE7
AG2
AH2
AD5
AE5
AC9
AD9
AH1
AJ1
3
IO_L24P_3
3
IO_L23N_3
3
IO_L23P_3
3
IO_L22N_3
3
IO_L22P_3
3
IO_L21N_3/VREF_3
IO_L21P_3
3
3
IO_L20N_3
3
IO_L20P_3
3
IO_L19N_3
3
IO_L19P_3
3
IO_L06N_3
3
IO_L06P_3
3
IO_L05N_3
3
IO_L05P_3
3
IO_L04N_3
3
IO_L04P_3
3
IO_L03N_3/VREF_3
IO_L03P_3
3
3
IO_L02N_3/VRP_3
IO_L02P_3/VRN_3
IO_L01N_3
3
3
AF4
AG3
3
IO_L01P_3
4
4
4
4
4
4
4
4
4
4
4
4
IO_L01N_4/DOUT
IO_L01P_4/INIT_B
IO_L02N_4/D0
AK2
AJ3
AE8
AF9
AH5
AH6
AJ4
IO_L02P_4/D1
IO_L03N_4/D2/ALT_VRP_4
IO_L03P_4/D3/ALT_VRN_4
IO_L04N_4/VREF_4
IO_L04P_4
AK4
AC10
AC11
AH7
AG6
IO_L05N_4/VRP_4
IO_L05P_4/VRN_4
IO_L06N_4
IO_L06P_4
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Advance Product Specification
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Pin Description
IO_L19N_4
IO_L19P_4
IO_L20N_4
IO_L20P_4
IO_L21N_4
IO_L21P_4/VREF_4
IO_L22N_4
IO_L22P_4
IO_L23N_4
IO_L23P_4
IO_L24N_4
IO_L24P_4
IO_L49N_4
IO_L49P_4
IO_L50N_4
IO_L50P_4
IO_L51N_4
IO_L51P_4/VREF_4
IO_L52N_4
IO_L52P_4
IO_L53N_4
IO_L53P_4
IO_L54N_4
IO_L54P_4
IO_L67N_4
IO_L67P_4
IO_L68N_4
IO_L68P_4
IO_L69N_4
IO_L69P_4/VREF_4
IO_L70N_4
IO_L70P_4
IO_L71N_4
IO_L71P_4
IO_L72N_4
IO_L72P_4
IO_L73N_4
Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
AK6
AK5
AE9
AE10
AF7
AF8
AK7
AJ6
AD10
AD11
AG8
AG7
AJ8
AJ7
AE11
AE12
AG9
AG10
AK9
AJ9
AH8
AH9
AF11
AF10
AJ11
AJ10
AC12
AC13
AG11
AG12
AK11
AK10
AD12
AD13
AH12
AH11
AJ13
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DS031-4 (v1.8) October 7, 2002
Advance Product Specification
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103
R
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
4
Pin Description
IO_L73P_4
Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
AJ12
AE13
AE14
AF13
AG13
AK13
AK12
AB14
AB15
AF15
AF14
AJ14
AJ15
AC14
AC15
AG15
AG14
AK14
AK15
AD15
AE15
AH14
AH15
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
4
IO_L74N_4
4
IO_L74P_4
4
IO_L75N_4
4
IO_L75P_4/VREF_4
IO_L76N_4
4
4
IO_L76P_4
4
IO_L77N_4
4
IO_L77P_4
4
IO_L78N_4
4
IO_L78P_4
4
IO_L91N_4/VREF_4
IO_L91P_4
4
4
IO_L92N_4
4
IO_L92P_4
4
IO_L93N_4
4
IO_L93P_4
4
IO_L94N_4/VREF_4
IO_L94P_4
4
4
IO_L95N_4/GCLK3S
IO_L95P_4/GCLK2P
IO_L96N_4/GCLK1S
IO_L96P_4/GCLK0P
4
4
4
5
5
5
5
5
5
5
5
5
5
5
5
5
IO_L96N_5/GCLK7S
IO_L96P_5/GCLK6P
IO_L95N_5/GCLK5S
IO_L95P_5/GCLK4P
IO_L94N_5
AH16
AH17
AE16
AD16
AJ16
AJ17
AG17
AG16
AC16
AC17
AK17
AK18
AF17
IO_L94P_5/VREF_5
IO_L93N_5
IO_L93P_5
IO_L92N_5
IO_L92P_5
IO_L91N_5
IO_L91P_5/VREF_5
IO_L78N_5
NC
NC
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Advance Product Specification
R
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
Bank
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
Pin Description
IO_L78P_5
IO_L77N_5
IO_L77P_5
IO_L76N_5
IO_L76P_5
IO_L75N_5/VREF_5
IO_L75P_5
IO_L74N_5
IO_L74P_5
IO_L73N_5
IO_L73P_5
IO_L72N_5
IO_L72P_5
IO_L71N_5
IO_L71P_5
IO_L70N_5
IO_L70P_5
IO_L69N_5/VREF_5
IO_L69P_5
IO_L68N_5
IO_L68P_5
IO_L67N_5
IO_L67P_5
IO_L54N_5
IO_L54P_5
IO_L53N_5
IO_L53P_5
IO_L52N_5
IO_L52P_5
IO_L51N_5/VREF_5
IO_L51P_5
IO_L50N_5
IO_L50P_5
IO_L49N_5
IO_L49P_5
IO_L24N_5
IO_L24P_5
AF16
AB16
AB17
AJ19
AJ18
AG18
AF18
AE17
AE18
AK20
AK19
AH20
AH19
AD18
AD19
AJ21
AJ20
AG19
AG20
AC18
AC19
AK22
AK21
AF21
AF20
AH22
AH23
AG22
AG21
AF22
AF23
AE19
AE20
AJ23
AJ22
AF24
AG23
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DS031-4 (v1.8) October 7, 2002
Advance Product Specification
www.xilinx.com
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Module 4 of 4
105
R
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
5
Pin Description
IO_L23N_5
Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
AD20
AD21
AK25
AK24
AH24
AH25
AE21
AD22
AJ25
AJ24
AG25
AG24
AC20
AC21
AK26
AK27
AH26
AJ27
AE22
AE23
AJ28
AK29
5
IO_L23P_5
5
IO_L22N_5
5
IO_L22P_5
5
IO_L21N_5/VREF_5
IO_L21P_5
5
5
IO_L20N_5
5
IO_L20P_5
5
IO_L19N_5
5
IO_L19P_5
5
IO_L06N_5
5
IO_L06P_5
5
IO_L05N_5/VRP_5
IO_L05P_5/VRN_5
IO_L04N_5
5
5
5
IO_L04P_5/VREF_5
IO_L03N_5/D4/ALT_VRP_5
IO_L03P_5/D5/ALT_VRN_5
IO_L02N_5/D6
IO_L02P_5/D7
IO_L01N_5/RDWR_B
IO_L01P_5/CS_B
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
IO_L01P_6
IO_L01N_6
AC22
AB23
AG28
AF28
AJ30
AH30
AD23
AC23
AF27
AE27
AG29
AH29
AE24
AD24
IO_L02P_6/VRN_6
IO_L02N_6/VRP_6
IO_L03P_6
IO_L03N_6/VREF_6
IO_L04P_6
IO_L04N_6
IO_L05P_6
IO_L05N_6
IO_L06P_6
IO_L06N_6
IO_L19P_6
IO_L19N_6
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
Pin Description
IO_L20P_6
IO_L20N_6
IO_L21P_6
IO_L21N_6/VREF_6
IO_L22P_6
IO_L22N_6
IO_L23P_6
IO_L23N_6
IO_L24P_6
IO_L24N_6
IO_L43P_6
IO_L43N_6
IO_L44P_6
IO_L44N_6
IO_L45P_6
IO_L45N_6/VREF_6
IO_L46P_6
IO_L46N_6
IO_L47P_6
IO_L47N_6
IO_L48P_6
IO_L48N_6
IO_L49P_6
IO_L49N_6
IO_L50P_6
IO_L50N_6
IO_L51P_6
IO_L51N_6/VREF_6
IO_L52P_6
IO_L52N_6
IO_L53P_6
IO_L53N_6
IO_L54P_6
IO_L54N_6
IO_L67P_6
IO_L67N_6
IO_L68P_6
Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
AE26
AD26
AG30
AF30
AD25
AC25
AE28
AD28
AD29
AE29
AC24
AB24
AD27
AC27
AC26
AB26
AA23
Y23
AC28
AB28
AD30
AE30
AB25
AA25
AA24
Y24
AC29
AB30
Y25
W25
AB27
AA27
AA29
AB29
W23
V23
NC
NC
NC
AA26
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
6
Pin Description
IO_L68N_6
IO_L69P_6
IO_L69N_6/VREF_6
IO_L70P_6
IO_L70N_6
IO_L71P_6
IO_L71N_6
IO_L72P_6
IO_L72N_6
IO_L73P_6
IO_L73N_6
IO_L74P_6
IO_L74N_6
IO_L75P_6
IO_L75N_6/VREF_6
IO_L76P_6
IO_L76N_6
IO_L77P_6
IO_L77N_6
IO_L78P_6
IO_L78N_6
IO_L91P_6
IO_L91N_6
IO_L92P_6
IO_L92N_6
IO_L93P_6
IO_L93N_6/VREF_6
IO_L94P_6
IO_L94N_6
IO_L95P_6
IO_L95N_6
IO_L96P_6
IO_L96N_6
Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
Y26
AA30
Y30
W24
V24
Y27
W27
W28
Y28
V25
U25
V26
V27
Y29
W29
U22
T22
U26
T26
V30
W30
U23
T23
U27
T27
V29
U29
T24
T25
U28
T28
T30
U30
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
6
6
6
6
6
6
6
6
6
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
7
7
7
IO_L96P_7
IO_L96N_7
IO_L95P_7
P28
R28
R25
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
Pin Description
IO_L95N_7
IO_L94P_7
IO_L94N_7
IO_L93P_7/VREF_7
IO_L93N_7
IO_L92P_7
IO_L92N_7
IO_L91P_7
IO_L91N_7
IO_L78P_7
IO_L78N_7
IO_L77P_7
IO_L77N_7
IO_L76P_7
IO_L76N_7
IO_L75P_7/VREF_7
IO_L75N_7
IO_L74P_7
IO_L74N_7
IO_L73P_7
IO_L73N_7
IO_L72P_7
IO_L72N_7
IO_L71P_7
IO_L71N_7
IO_L70P_7
IO_L70N_7
IO_L69P_7/VREF_7
IO_L69N_7
IO_L68P_7
IO_L68N_7
IO_L67P_7
IO_L67N_7
IO_L54P_7
IO_L54N_7
IO_L53P_7
IO_L53N_7
Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
R24
R29
T29
R27
P27
R23
P23
N30
P30
P26
R26
R22
P22
N29
P29
N27
N26
P25
N25
L30
M30
L28
M28
N24
M24
L29
M29
M27
L27
N23
M23
J30
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
K30
K26
L26
M25
L25
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
Pin Description
IO_L52P_7
IO_L52N_7
IO_L51P_7/VREF_7
IO_L51N_7
IO_L50P_7
IO_L50N_7
IO_L49P_7
IO_L49N_7
IO_L48P_7
IO_L48N_7
IO_L47P_7
IO_L47N_7
IO_L46P_7
IO_L46N_7
IO_L45P_7/VREF_7
IO_L45N_7
IO_L44P_7
IO_L44N_7
IO_L43P_7
IO_L43N_7
IO_L24P_7
IO_L24N_7
IO_L23P_7
IO_L23N_7
IO_L22P_7
IO_L22N_7
IO_L21P_7/VREF_7
IO_L21N_7
IO_L20P_7
IO_L20N_7
IO_L19P_7
IO_L19N_7
IO_L06P_7
IO_L06N_7
IO_L05P_7
IO_L05N_7
IO_L04P_7
Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
J29
K29
K27
J27
L24
K24
H27
J28
H26
J26
K25
J25
H28
H29
G28
F28
L23
K23
F30
G30
F26
G27
J24
H24
F29
G29
G26
G25
H25
G24
D30
E30
E27
F27
J23
H22
C29
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
Pin Description
IO_L04N_7
Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
7
7
7
7
7
7
7
D29
E28
D28
H23
G23
B30
C30
IO_L03P_7/VREF_7
IO_L03N_7
IO_L02P_7/VRN_7
IO_L02N_7/VRP_7
IO_L01P_7
IO_L01N_7
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
K20
K19
K18
K17
K16
J21
J20
J19
J18
C18
B26
K15
K14
K13
K12
K11
J13
J12
J11
J10
C13
B5
R10
P10
N10
N9
N3
M10
M9
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
5
Pin Description
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
L10
L9
K9
E2
AF2
AA9
Y10
Y9
W10
W9
V10
V9
V3
U10
T10
AJ5
AH13
AB13
AB12
AB11
AB10
AA15
AA14
AA13
AA12
AA11
AJ26
AH18
AB21
AB20
AB19
AB18
AA20
AA19
AA18
AA17
AA16
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
6
Pin Description
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
AF29
AA22
Y22
Y21
W22
W21
V28
V22
V21
U21
T21
R21
P21
N28
N22
N21
M22
M21
L22
6
6
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
7
L21
7
K22
E29
7
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
CCLK
PROG_B
DONE
M0
AF6
B28
AG5
AF25
AG26
AH27
C27
D5
M1
M2
HSWAP_EN
TCK
TDI
A29
B3
TDO
TMS
C4
PWRDWN_B
DXN
AH4
D26
E25
DXP
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
NA
Pin Description
VBATT
Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
A2
E6
NA
RSVD
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
AK28
AK16
AK3
T1
R30
A28
A15
A3
AB22
AB9
AA21
AA10
Y20
Y19
Y18
Y17
Y16
Y15
Y14
Y13
Y12
Y11
W20
W11
V20
V11
U20
U11
T20
T11
R20
R11
P20
P11
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
GND
Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
N20
N11
M20
M11
L20
L19
L18
L17
L16
L15
L14
L13
L12
L11
K21
K10
J22
J9
AK23
AK8
AJ29
AJ2
GND
GND
GND
GND
AH28
AH21
AH10
AH3
AG27
AG4
AF26
AF19
AF12
AF5
AE25
AE6
AD17
AD14
AC30
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
AC1
AA28
AA3
W26
W19
W18
W17
W16
W15
W14
W13
W12
W5
V19
V18
V17
V16
V15
V14
V13
V12
U24
U19
U18
U17
U16
U15
U14
U13
U12
U7
T19
T18
T17
T16
T15
T14
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
T13
T12
R19
R18
R17
R16
R15
R14
R13
R12
P24
P19
P18
P17
P16
P15
P14
P13
P12
P7
N19
N18
N17
N16
N15
N14
N13
N12
M26
M19
M18
M17
M16
M15
M14
M13
M12
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
M5
K28
K3
H30
H1
G17
G14
F25
F6
E26
E19
E12
E5
D27
D4
C28
C21
C10
C3
B29
B2
A23
A8
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FF896 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch)
Figure 7: FF896 Flip-Chip Fine-Pitch BGA Package Specifications
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
FF1152 Flip-Chip Fine-Pitch BGA Package
As shown in Table 12, XC2V3000, XC2V4000, XC2V6000, and XC2V8000 Virtex-II devices are available in the FF1152
flip-chip fine-pitch BGA package. Pins in each of these devices are the same, except for the pin differences in the XC2V3000
device shown in the No Connect column. Following this table are the FF1152 Flip-Chip Fine-Pitch BGA Package
Specifications (1.00mm pitch).
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank
0
Pin Description
IO_L01N_0
Pin Number
D29
C29
H26
G26
E28
E27
F25
No Connect in the XC2V3000
0
IO_L01P_0
0
IO_L02N_0
0
IO_L02P_0
0
IO_L03N_0/VRP_0
IO_L03P_0/VRN_0
IO_L04N_0/VREF_0
IO_L04P_0
0
0
0
F26
0
IO_L05N_0
H25
H24
E26
F27
0
IO_L05P_0
0
IO_L06N_0
0
IO_L06P_0
0
IO_L19N_0
B32
C33
J24
0
IO_L19P_0
0
IO_L20N_0
0
IO_L20P_0
J23
0
IO_L21N_0
C27
C28
B30
B31
K23
K22
C26
D27
A30
A31
G24
G25
E25
E24
D25
0
IO_L21P_0/VREF_0
IO_L22N_0
0
0
IO_L22P_0
0
IO_L23N_0
0
IO_L23P_0
0
IO_L24N_0
0
IO_L24P_0
0
IO_L25N_0
0
IO_L25P_0
0
IO_L26N_0
0
IO_L26P_0
0
IO_L27N_0
0
IO_L27P_0/VREF_0
IO_L28N_0
0
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Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pin Description
IO_L28P_0
IO_L29N_0
IO_L29P_0
IO_L30N_0
IO_L30P_0
IO_L49N_0
IO_L49P_0
IO_L50N_0
IO_L50P_0
IO_L51N_0
IO_L51P_0/VREF_0
IO_L52N_0
IO_L52P_0
IO_L53N_0
IO_L53P_0
IO_L54N_0
IO_L54P_0
IO_L60N_0
IO_L60P_0
IO_L67N_0
IO_L67P_0
IO_L68N_0
IO_L68P_0
IO_L69N_0
IO_L69P_0/VREF_0
IO_L70N_0
IO_L70P_0
IO_L71N_0
IO_L71P_0
IO_L72N_0
IO_L72P_0
IO_L73N_0
IO_L73P_0
IO_L74N_0
IO_L74P_0
IO_L75N_0
Pin Number
D26
H23
H22
F23
F24
B28
B29
J22
No Connect in the XC2V3000
J21
A28
A29
A26
B27
C24
D24
D22
D23
B25
B26
B23
B24
G22
G23
F22
F21
A23
A24
K21
K20
C22
C23
E21
E22
H21
H20
G20
NC
NC
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Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank
0
Pin Description
IO_L75P_0/VREF_0
IO_L76N_0
Pin Number
F20
B21
B22
J20
No Connect in the XC2V3000
0
0
IO_L76P_0
0
IO_L77N_0
0
IO_L77P_0
K19
D20
D21
A21
A22
L19
0
IO_L78N_0
0
IO_L78P_0
0
IO_L79N_0
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
0
IO_L79P_0
0
IO_L80N_0
0
IO_L80P_0
L18
0
IO_L81N_0
B19
A20
A18
B18
H19
H18
C20
C21
D19
D18
G18
G19
F18
F19
C19
C18
K18
J18
0
IO_L81P_0/VREF_0
IO_L82N_0
0
0
IO_L82P_0
0
IO_L83N_0
0
IO_L83P_0
0
IO_L84N_0
0
IO_L84P_0
0
IO_L91N_0/VREF_0
IO_L91P_0
0
0
IO_L92N_0
0
IO_L92P_0
0
IO_L93N_0
0
IO_L93P_0
0
IO_L94N_0/VREF_0
IO_L94P_0
0
0
IO_L95N_0/GCLK7P
IO_L95P_0/GCLK6S
IO_L96N_0/GCLK5P
IO_L96P_0/GCLK4S
0
0
E19
E18
0
1
1
1
1
IO_L96N_1/GCLK3P
IO_L96P_1/GCLK2S
IO_L95N_1/GCLK1P
IO_L95P_1/GCLK0S
E17
E16
H17
H16
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Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Description
IO_L94N_1
IO_L94P_1/VREF_1
IO_L93N_1
IO_L93P_1
Pin Number
D17
D16
F16
F17
G16
G17
C16
C15
D14
D15
J17
No Connect in the XC2V3000
IO_L92N_1
IO_L92P_1
IO_L91N_1
IO_L91P_1/VREF_1
IO_L84N_1
IO_L84P_1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IO_L83N_1
IO_L83P_1
K17
B17
A17
A15
B16
L17
IO_L82N_1
IO_L82P_1
IO_L81N_1/VREF_1
IO_L81P_1
IO_L80N_1
IO_L80P_1
L16
IO_L79N_1
IO_L79P_1
A13
A14
C13
C14
K16
K15
B13
B14
F15
G15
H15
H14
A11
A12
E13
E14
J15
IO_L78N_1
IO_L78P_1
IO_L77N_1
IO_L77P_1
IO_L76N_1
IO_L76P_1
IO_L75N_1/VREF_1
IO_L75P_1
IO_L74N_1
IO_L74P_1
IO_L73N_1
IO_L73P_1
IO_L72N_1
IO_L72P_1
IO_L71N_1
IO_L71P_1
J14
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Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Description
IO_L70N_1
IO_L70P_1
IO_L69N_1/VREF_1
IO_L69P_1
IO_L68N_1
IO_L68P_1
IO_L67N_1
IO_L67P_1
IO_L60N_1
IO_L60P_1
IO_L54N_1
IO_L54P_1
IO_L53N_1
IO_L53P_1
IO_L52N_1
IO_L52P_1
IO_L51N_1/VREF_1
IO_L51P_1
IO_L50N_1
IO_L50P_1
IO_L49N_1
IO_L49P_1
IO_L30N_1
IO_L30P_1
IO_L29N_1
IO_L29P_1
IO_L28N_1
IO_L28P_1
IO_L27N_1/VREF_1
IO_L27P_1
IO_L26N_1
IO_L26P_1
IO_L25N_1
IO_L25P_1
IO_L24N_1
IO_L24P_1
Pin Number
D12
D13
F14
F13
C11
C12
B11
B12
F11
F12
D10
D11
G12
G13
B9
No Connect in the XC2V3000
NC
NC
B10
B8
A9
K14
K13
A6
A7
D9
C9
H13
H12
C7
C8
E11
E10
J13
K12
B6
B7
E8
E9
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Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank
1
Pin Description
IO_L23N_1
Pin Number
G10
G11
A4
No Connect in the XC2V3000
1
IO_L23P_1
1
IO_L22N_1
1
IO_L22P_1
A5
1
IO_L21N_1/VREF_1
IO_L21P_1
F10
G9
1
1
IO_L20N_1
J12
J11
B4
1
IO_L20P_1
1
IO_L19N_1
1
IO_L19P_1
B5
1
IO_L06N_1
D6
1
IO_L06P_1
C6
1
IO_L05N_1
H11
J10
D8
1
IO_L05P_1
1
IO_L04N_1
1
IO_L04P_1/VREF_1
IO_L03N_1/VRP_1
IO_L03P_1/VRN_1
IO_L02N_1
E7
1
F9
1
F8
1
H10
H9
1
IO_L02P_1
1
IO_L01N_1
C2
1
IO_L01P_1
B3
2
2
2
2
2
2
2
2
2
2
2
2
2
IO_L01N_2
IO_L01P_2
E2
D2
K11
K10
F5
IO_L02N_2/VRP_2
IO_L02P_2/VRN_2
IO_L03N_2
IO_L03P_2/VREF_2
IO_L04N_2
G5
E3
D3
J9
IO_L04P_2
IO_L05N_2
IO_L05P_2
K9
F4
IO_L06N_2
IO_L06P_2
E4
E1
IO_L19N_2
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Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Pin Description
IO_L19P_2
IO_L20N_2
IO_L20P_2
IO_L21N_2
IO_L21P_2/VREF_2
IO_L22N_2
IO_L22P_2
IO_L23N_2
IO_L23P_2
IO_L24N_2
IO_L24P_2
IO_L25N_2
IO_L25P_2
IO_L26N_2
IO_L26P_2
IO_L27N_2
IO_L27P_2/VREF_2
IO_L28N_2
IO_L28P_2
IO_L29N_2
IO_L29P_2
IO_L30N_2
IO_L30P_2
IO_L43N_2
IO_L43P_2
IO_L44N_2
IO_L44P_2
IO_L45N_2
IO_L45P_2/VREF_2
IO_L46N_2
IO_L46P_2
IO_L47N_2
IO_L47P_2
IO_L48N_2
IO_L48P_2
IO_L49N_2
Pin Number
D1
J8
No Connect in the XC2V3000
K8
H7
J7
H6
G6
L10
L9
G3
F3
G2
F2
M10
N10
J6
K6
J5
H5
L7
K7
J4
H4
G1
F1
L8
M8
J1
H2
J3
H3
M9
N9
L5
K5
K2
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Pin Description
IO_L49P_2
IO_L50N_2
IO_L50P_2
IO_L51N_2
IO_L51P_2/VREF_2
IO_L52N_2
IO_L52P_2
IO_L53N_2
IO_L53P_2
IO_L54N_2
IO_L54P_2
IO_L67N_2
IO_L67P_2
IO_L68N_2
IO_L68P_2
IO_L69N_2
IO_L69P_2/VREF_2
IO_L70N_2
IO_L70P_2
IO_L71N_2
IO_L71P_2
IO_L72N_2
IO_L72P_2
IO_L73N_2
IO_L73P_2
IO_L74N_2
IO_L74P_2
IO_L75N_2
IO_L75P_2/VREF_2
IO_L76N_2
IO_L76P_2
IO_L77N_2
IO_L77P_2
IO_L78N_2
IO_L78P_2
IO_L79N_2
Pin Number
J2
No Connect in the XC2V3000
N7
M7
L6
M6
M3
L3
L4
K4
N4
M4
M2
L2
N8
P8
N6
P6
P5
N5
P10
R10
P3
N3
M1
L1
P9
R9
P2
N2
R4
P4
R8
T8
T3
R3
P1
NC
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank
2
Pin Description
IO_L79P_2
IO_L80N_2
IO_L80P_2
IO_L81N_2
IO_L81P_2/VREF_2
IO_L82N_2
IO_L82P_2
IO_L83N_2
IO_L83P_2
IO_L84N_2
IO_L84P_2
IO_L91N_2
IO_L91P_2
IO_L92N_2
IO_L92P_2
IO_L93N_2
IO_L93P_2/VREF_2
IO_L94N_2
IO_L94P_2
IO_L95N_2
IO_L95P_2
IO_L96N_2
IO_L96P_2
Pin Number
N1
No Connect in the XC2V3000
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
2
T11
U11
R7
2
2
2
R6
2
U5
2
T5
2
T10
U10
U4
2
2
2
T4
2
T2
2
R1
2
U7
2
T7
2
T6
2
U6
2
U1
2
U2
2
U9
2
U8
2
U3
2
V4
3
3
3
3
3
3
3
3
3
3
3
3
IO_L96N_3
IO_L96P_3
V6
W6
V5
IO_L95N_3
IO_L95P_3
W5
V7
IO_L94N_3
IO_L94P_3
W7
V10
W10
V1
IO_L93N_3/VREF_3
IO_L93P_3
IO_L92N_3
IO_L92P_3
V2
IO_L91N_3
IO_L91P_3
W3
Y3
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Description
IO_L84N_3
IO_L84P_3
IO_L83N_3
IO_L83P_3
IO_L82N_3
IO_L82P_3
IO_L81N_3/VREF_3
IO_L81P_3
IO_L80N_3
IO_L80P_3
IO_L79N_3
IO_L79P_3
IO_L78N_3
IO_L78P_3
IO_L77N_3
IO_L77P_3
IO_L76N_3
IO_L76P_3
IO_L75N_3/VREF_3
IO_L75P_3
IO_L74N_3
IO_L74P_3
IO_L73N_3
IO_L73P_3
IO_L72N_3
IO_L72P_3
IO_L71N_3
IO_L71P_3
IO_L70N_3
IO_L70P_3
IO_L69N_3/VREF_3
IO_L69P_3
IO_L68N_3
IO_L68P_3
IO_L67N_3
IO_L67P_3
Pin Number
V9
No Connect in the XC2V3000
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
V8
W4
Y4
W11
V11
W8
Y8
W2
Y1
AA3
AB3
Y6
AA6
AA4
AB4
Y7
AA8
Y10
AA10
AA1
AB1
AA5
AB5
AA9
Y9
AA2
AB2
AB6
AC6
AD1
AC1
AC3
AD3
AC4
AD4
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Description
IO_L54N_3
IO_L54P_3
IO_L53N_3
IO_L53P_3
IO_L52N_3
IO_L52P_3
IO_L51N_3/VREF_3
IO_L51P_3
IO_L50N_3
IO_L50P_3
IO_L49N_3
IO_L49P_3
IO_L48N_3
IO_L48P_3
IO_L47N_3
IO_L47P_3
IO_L46N_3
IO_L46P_3
IO_L45N_3/VREF_3
IO_L45P_3
IO_L44N_3
IO_L44P_3
IO_L43N_3
IO_L43P_3
IO_L30N_3
IO_L30P_3
IO_L29N_3
IO_L29P_3
IO_L28N_3
IO_L28P_3
IO_L27N_3/VREF_3
IO_L27P_3
IO_L26N_3
IO_L26P_3
IO_L25N_3
IO_L25P_3
Pin Number
AB7
AC7
AC2
AD2
AC8
AB8
AB10
AC10
AD5
AE5
AE4
AF4
No Connect in the XC2V3000
AB9
AC9
AE2
AF1
AD6
AE6
AD9
AE9
AF2
AG2
AF3
AG3
AD7
AE7
AF5
AG5
AE8
AD8
AF8
AF9
AH1
AJ1
AG4
AH5
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Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank
3
Pin Description
IO_L24N_3
Pin Number
AF6
No Connect in the XC2V3000
3
IO_L24P_3
AG6
AH3
3
IO_L23N_3
3
IO_L23P_3
AJ3
3
IO_L22N_3
AF7
3
IO_L22P_3
AG7
AL1
3
IO_L21N_3/VREF_3
IO_L21P_3
3
AK1
3
IO_L20N_3
AH2
3
IO_L20P_3
AJ2
3
IO_L19N_3
AJ4
3
IO_L19P_3
AK4
3
IO_L06N_3
AE10
AD10
AK2
3
IO_L06P_3
3
IO_L05N_3
3
IO_L05P_3
AL2
3
IO_L04N_3
AH6
3
IO_L04P_3
AJ5
3
IO_L03N_3/VREF_3
IO_L03P_3
AE11
AF11
AK3
3
3
IO_L02N_3/VRP_3
IO_L02P_3/VRN_3
IO_L01N_3
3
AL3
3
AF10
AG9
3
IO_L01P_3
4
4
4
4
4
4
4
4
4
4
4
IO_L01N_4/DOUT
IO_L01P_4/INIT_B
IO_L02N_4/D0
AM4
AL5
AG10
AH11
AK7
AK8
AL6
IO_L02P_4/D1
IO_L03N_4/D2/ALT_VRP_4
IO_L03P_4/D3/ALT_VRN_4
IO_L04N_4/VREF_4
IO_L04P_4
AM6
AK9
AJ8
IO_L05N_4/VRP_4
IO_L05P_4/VRN_4
IO_L06N_4
AM8
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Pin Description
IO_L06P_4
IO_L19N_4
IO_L19P_4
IO_L20N_4
IO_L20P_4
IO_L21N_4
IO_L21P_4/VREF_4
IO_L22N_4
IO_L22P_4
IO_L23N_4
IO_L23P_4
IO_L24N_4
IO_L24P_4
IO_L25N_4
IO_L25P_4
IO_L26N_4
IO_L26P_4
IO_L27N_4
IO_L27P_4/VREF_4
IO_L28N_4
IO_L28P_4
IO_L29N_4
IO_L29P_4
IO_L30N_4
IO_L30P_4
IO_L49N_4
IO_L49P_4
IO_L50N_4
IO_L50P_4
IO_L51N_4
IO_L51P_4/VREF_4
IO_L52N_4
IO_L52P_4
IO_L53N_4
IO_L53P_4
IO_L54N_4
Pin Number
AM7
AN3
No Connect in the XC2V3000
AM2
AJ10
AJ9
AH9
AH10
AN5
AN4
AE12
AE13
AM9
AL8
AP5
AP4
AG11
AG12
AN7
AN6
AL10
AL9
AF12
AF13
AK10
AK11
AP7
AP6
AH13
AH12
AJ11
AJ12
AP9
AN8
AG13
AG14
AM11
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Pin Description
IO_L54P_4
IO_L60N_4
IO_L60P_4
IO_L67N_4
IO_L67P_4
IO_L68N_4
IO_L68P_4
IO_L69N_4
IO_L69P_4/VREF_4
IO_L70N_4
IO_L70P_4
IO_L71N_4
IO_L71P_4
IO_L72N_4
IO_L72P_4
IO_L73N_4
IO_L73P_4
IO_L74N_4
IO_L74P_4
IO_L75N_4
IO_L75P_4/VREF_4
IO_L76N_4
IO_L76P_4
IO_L77N_4
IO_L77P_4
IO_L78N_4
IO_L78P_4
IO_L79N_4
IO_L79P_4
IO_L80N_4
IO_L80P_4
IO_L81N_4
IO_L81P_4/VREF_4
IO_L82N_4
IO_L82P_4
IO_L83N_4
Pin Number
AL11
AN10
AN9
No Connect in the XC2V3000
NC
NC
AN12
AN11
AE14
AE15
AJ13
AJ14
AL13
AL12
AF14
AF15
AM13
AM12
AP12
AP11
AG15
AG16
AN14
AN13
AP14
AP13
AD16
AD17
AK14
AK13
AN16
AP15
AE16
AE17
AH15
AJ15
NC
NC
NC
NC
NC
NC
NC
NC
NC
AP17
AN17
AH17
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank
Pin Description
IO_L83P_4
Pin Number
AH16
AL15
No Connect in the XC2V3000
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
NC
NC
NC
IO_L84N_4
IO_L84P_4
AL14
IO_L91N_4/VREF_4
IO_L91P_4
AL16
AL17
IO_L92N_4
AJ17
IO_L92P_4
AJ16
IO_L93N_4
AM15
AM14
AM16
AM17
AF17
AG17
AK16
AK17
IO_L93P_4
IO_L94N_4/VREF_4
IO_L94P_4
IO_L95N_4/GCLK3S
IO_L95P_4/GCLK2P
IO_L96N_4/GCLK1S
IO_L96P_4/GCLK0P
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
IO_L96N_5/GCLK7S
IO_L96P_5/GCLK6P
IO_L95N_5/GCLK5S
IO_L95P_5/GCLK4P
IO_L94N_5
AK18
AK19
AG18
AF18
AL18
AL19
AJ19
AJ18
AH19
AH18
AM19
AM20
AL21
AL20
AM22
AM21
AN18
AP18
AP20
AN19
IO_L94P_5/VREF_5
IO_L93N_5
IO_L93P_5
IO_L92N_5
IO_L92P_5
IO_L91N_5
IO_L91P_5/VREF_5
IO_L84N_5
NC
NC
NC
NC
NC
NC
NC
NC
IO_L84P_5
IO_L83N_5
IO_L83P_5
IO_L82N_5
IO_L82P_5
IO_L81N_5/VREF_5
IO_L81P_5
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
Pin Description
IO_L80N_5
IO_L80P_5
IO_L79N_5
IO_L79P_5
IO_L78N_5
IO_L78P_5
IO_L77N_5
IO_L77P_5
IO_L76N_5
IO_L76P_5
IO_L75N_5/VREF_5
IO_L75P_5
IO_L74N_5
IO_L74P_5
IO_L73N_5
IO_L73P_5
IO_L72N_5
IO_L72P_5
IO_L71N_5
IO_L71P_5
IO_L70N_5
IO_L70P_5
IO_L69N_5/VREF_5
IO_L69P_5
IO_L68N_5
IO_L68P_5
IO_L67N_5
IO_L67P_5
IO_L60N_5
IO_L60P_5
IO_L54N_5
IO_L54P_5
IO_L53N_5
IO_L53P_5
IO_L52N_5
IO_L52P_5
Pin Number
AE18
AE19
AP22
AP21
AK22
AK21
AD18
AD19
AN22
AN21
AJ20
No Connect in the XC2V3000
NC
NC
NC
NC
AH20
AG19
AG20
AP24
AP23
AL23
AL22
AF20
AF21
AM24
AM23
AJ21
AJ22
AJ24
AJ23
AN24
AN23
AN26
AN25
AL25
AL24
AE20
AE21
AN27
AP26
NC
NC
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
Pin Description
IO_L51N_5/VREF_5
IO_L51P_5
Pin Number
AP29
AP28
AG21
AG22
AN29
AN28
AK24
AK25
AH23
AH22
AP31
AP30
AH24
AH25
AF22
AF23
AM27
AM26
AL27
AL26
AH26
AJ25
No Connect in the XC2V3000
IO_L50N_5
IO_L50P_5
IO_L49N_5
IO_L49P_5
IO_L30N_5
IO_L30P_5
IO_L29N_5
IO_L29P_5
IO_L28N_5
IO_L28P_5
IO_L27N_5/VREF_5
IO_L27P_5
IO_L26N_5
IO_L26P_5
IO_L25N_5
IO_L25P_5
IO_L24N_5
IO_L24P_5
IO_L23N_5
IO_L23P_5
IO_L22N_5
AN31
AN30
AK26
AK27
AG23
AF24
AM33
AN32
AJ27
IO_L22P_5
IO_L21N_5/VREF_5
IO_L21P_5
IO_L20N_5
IO_L20P_5
IO_L19N_5
IO_L19P_5
IO_L06N_5
IO_L06P_5
AJ26
IO_L05N_5/VRP_5
IO_L05P_5/VRN_5
IO_L04N_5
AE22
AE23
AM28
AM29
IO_L04P_5/VREF_5
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank
Pin Description
IO_L03N_5/D4/ALT_VRP_5
IO_L03P_5/D5/ALT_VRN_5
IO_L02N_5/D6
Pin Number
AK28
No Connect in the XC2V3000
5
5
5
5
5
5
AL29
AG24
IO_L02P_5/D7
AG25
IO_L01N_5/RDWR_B
IO_L01P_5/CS_B
AL30
AM31
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
IO_L01P_6
IO_L01N_6
AE24
AD25
AJ30
AH30
AL32
AK32
AF25
AE25
AJ31
AK31
AH29
AG29
AG26
AF26
AL33
AK33
AJ32
AH32
AG28
AF28
AG30
AF30
AF29
AE29
AF27
AE27
AL34
AK34
AE28
IO_L02P_6/VRN_6
IO_L02N_6/VRP_6
IO_L03P_6
IO_L03N_6/VREF_6
IO_L04P_6
IO_L04N_6
IO_L05P_6
IO_L05N_6
IO_L06P_6
IO_L06N_6
IO_L19P_6
IO_L19N_6
IO_L20P_6
IO_L20N_6
IO_L21P_6
IO_L21N_6/VREF_6
IO_L22P_6
IO_L22N_6
IO_L23P_6
IO_L23N_6
IO_L24P_6
IO_L24N_6
IO_L25P_6
IO_L25N_6
IO_L26P_6
IO_L26N_6
IO_L27P_6
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
Pin Description
IO_L27N_6/VREF_6
IO_L28P_6
IO_L28N_6
IO_L29P_6
IO_L29N_6
IO_L30P_6
IO_L30N_6
IO_L43P_6
IO_L43N_6
IO_L44P_6
IO_L44N_6
IO_L45P_6
IO_L45N_6/VREF_6
IO_L46P_6
IO_L46N_6
IO_L47P_6
IO_L47N_6
IO_L48P_6
IO_L48N_6
IO_L49P_6
IO_L49N_6
IO_L50P_6
IO_L50N_6
IO_L51P_6
IO_L51N_6/VREF_6
IO_L52P_6
IO_L52N_6
IO_L53P_6
IO_L53N_6
IO_L54P_6
IO_L54N_6
IO_L67P_6
IO_L67N_6
IO_L68P_6
IO_L68N_6
IO_L69P_6
Pin Number
AD28
AE26
AD26
AF31
AG31
AF32
AG32
AC25
AB25
AJ33
No Connect in the XC2V3000
AH33
AE31
AD32
AD27
AC27
AJ34
AH34
AE30
AD30
AC26
AB26
AD29
AC29
AF33
AG33
AC28
AB28
AF34
AE33
AB27
AA27
AA25
Y25
AD33
AC33
AC32
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
Pin Description
IO_L69N_6/VREF_6
IO_L70P_6
IO_L70N_6
IO_L71P_6
IO_L71N_6
IO_L72P_6
IO_L72N_6
IO_L73P_6
IO_L73N_6
IO_L74P_6
IO_L74N_6
IO_L75P_6
IO_L75N_6/VREF_6
IO_L76P_6
IO_L76N_6
IO_L77P_6
IO_L77N_6
IO_L78P_6
IO_L78N_6
IO_L79P_6
IO_L79N_6
IO_L80P_6
IO_L80N_6
IO_L81P_6
IO_L81N_6/VREF_6
IO_L82P_6
IO_L82N_6
IO_L83P_6
IO_L83N_6
IO_L84P_6
IO_L84N_6
IO_L91P_6
IO_L91N_6
IO_L92P_6
IO_L92N_6
IO_L93P_6
Pin Number
AB32
AA26
Y26
No Connect in the XC2V3000
AD34
AC34
AC31
AD31
Y27
W27
AB29
AA29
AB31
AA31
Y28
Y29
AB33
AA33
AA30
AB30
W24
V24
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
AB34
AA34
W33
Y34
W25
V25
Y32
AA32
W29
V29
W28
V28
V33
V34
Y31
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank
Pin Description
IO_L93N_6/VREF_6
IO_L94P_6
Pin Number
W31
No Connect in the XC2V3000
6
6
6
6
6
6
6
V26
IO_L94N_6
V27
IO_L95P_6
W30
IO_L95N_6
V30
IO_L96P_6
V32
IO_L96N_6
W32
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
IO_L96P_7
IO_L96N_7
IO_L95P_7
IO_L95N_7
IO_L94P_7
IO_L94N_7
IO_L93P_7/VREF_7
IO_L93N_7
IO_L92P_7
IO_L92N_7
IO_L91P_7
IO_L91N_7
IO_L84P_7
IO_L84N_7
IO_L83P_7
IO_L83N_7
IO_L82P_7
IO_L82N_7
IO_L81P_7/VREF_7
IO_L81N_7
IO_L80P_7
IO_L80N_7
IO_L79P_7
IO_L79N_7
IO_L78P_7
IO_L78N_7
IO_L77P_7
IO_L77N_7
U31
V31
T28
U28
U33
U34
U29
T29
U27
U26
T30
U30
R32
T32
U25
T25
R34
T33
N34
P34
U24
T24
R31
T31
N32
P32
T27
R27
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
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R
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
Pin Description
IO_L76P_7
IO_L76N_7
IO_L75P_7/VREF_7
IO_L75N_7
IO_L74P_7
IO_L74N_7
IO_L73P_7
IO_L73N_7
IO_L72P_7
IO_L72N_7
IO_L71P_7
IO_L71N_7
IO_L70P_7
IO_L70N_7
IO_L69P_7/VREF_7
IO_L69N_7
IO_L68P_7
IO_L68N_7
IO_L67P_7
IO_L67N_7
IO_L54P_7
IO_L54N_7
IO_L53P_7
IO_L53N_7
IO_L52P_7
IO_L52N_7
IO_L51P_7/VREF_7
IO_L51N_7
IO_L50P_7
IO_L50N_7
IO_L49P_7
IO_L49N_7
IO_L48P_7
IO_L48N_7
IO_L47P_7
IO_L47N_7
Pin Number
N33
P33
R29
R28
R26
P26
N31
P31
N30
P30
R25
P25
L34
No Connect in the XC2V3000
M34
P29
N29
P27
N27
L32
M32
L31
M31
K29
L30
L33
M33
M29
L29
M28
N28
K30
K31
H32
J32
N26
M26
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Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
Pin Description
IO_L46P_7
IO_L46N_7
IO_L45P_7/VREF_7
IO_L45N_7
IO_L44P_7
IO_L44N_7
IO_L43P_7
IO_L43N_7
IO_L30P_7
IO_L30N_7
IO_L29P_7
IO_L29N_7
IO_L28P_7
IO_L28N_7
IO_L27P_7/VREF_7
IO_L27N_7
IO_L26P_7
IO_L26N_7
IO_L25P_7
IO_L25N_7
IO_L24P_7
IO_L24N_7
IO_L23P_7
IO_L23N_7
IO_L22P_7
IO_L22N_7
IO_L21P_7/VREF_7
IO_L21N_7
IO_L20P_7
IO_L20N_7
IO_L19P_7
IO_L19N_7
IO_L06P_7
IO_L06N_7
IO_L05P_7
IO_L05N_7
Pin Number
J33
No Connect in the XC2V3000
K33
H33
J34
M27
L27
H31
J31
F32
G32
N25
M25
F34
G34
J30
H30
K28
L28
H28
J29
G29
H29
L26
K26
F33
G33
J28
J27
K27
J26
E31
F31
D32
E32
L25
K24
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank
Pin Description
IO_L04P_7
Pin Number
D34
No Connect in the XC2V3000
7
7
7
7
7
7
7
7
IO_L04N_7
E34
IO_L03P_7/VREF_7
IO_L03N_7
G30
F30
IO_L02P_7/VRN_7
IO_L02N_7/VRP_7
IO_L01P_7
K25
J25
D33
IO_L01N_7
E33
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
2
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_2
M22
M21
M20
M19
M18
L23
L22
L21
L20
E20
D28
A25
A19
M17
M16
M15
M14
M13
L15
L14
L13
L12
E15
D7
A16
A10
U12
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
Pin Description
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
Pin Number
T12
No Connect in the XC2V3000
T1
R12
R11
R5
P12
P11
N12
N11
M11
K1
G4
AH4
AE1
AC11
AB12
AB11
AA12
AA11
Y12
Y11
Y5
W12
W1
V12
AP16
AP10
AL7
AK15
AD15
AD14
AD13
AD12
AC17
AC16
AC15
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Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank
4
4
5
5
5
5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
Pin Description
VCCO_4
VCCO_4
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
Pin Number
AC14
AC13
AP25
AP19
AL28
AK20
AD23
AD22
AD21
AD20
AC22
AC21
AC20
AC19
AC18
AH31
AE34
AC24
AB24
AB23
AA24
AA23
Y30
No Connect in the XC2V3000
Y24
Y23
W34
W23
V23
U23
T34
T23
R30
R24
R23
P24
P23
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Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank
Pin Description
VCCO_7
Pin Number
N24
No Connect in the XC2V3000
7
7
7
7
7
VCCO_7
N23
VCCO_7
M24
VCCO_7
K34
VCCO_7
G31
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
CCLK
PROG_B
DONE
AH8
D30
AJ7
M0
AH27
AJ28
AK29
E29
F7
M1
M2
HSWAP_EN
TCK
TDI
C31
D5
TDO
TMS
E6
PWRDWN_B
DXN
AK6
F28
DXP
G27
C4
VBATT
RSVD
G8
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
AM30
AM18
AM5
V3
U32
C30
C17
C5
AD24
AD11
AC23
AC12
AB22
AB21
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
Pin Number
AB20
AB19
AB18
AB17
AB16
AB15
AB14
AB13
AA22
AA13
Y22
No Connect in the XC2V3000
Y13
W22
W13
V22
V13
U22
U13
T22
T13
R22
R13
P22
P13
N22
N21
N20
N19
N18
N17
N16
N15
N14
N13
M23
M12
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank
NA
Pin Description
VCCINT
Pin Number
L24
No Connect in the XC2V3000
NA
VCCINT
L11
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AP33
AP32
AP27
AP8
AP3
AP2
AN34
AN33
AN20
AN15
AN2
AN1
AM34
AM32
AM25
AM10
AM3
AM1
AL31
AL4
AK30
AK23
AK12
AK5
AJ29
AJ6
AH28
AH21
AH14
AH7
AG34
AG27
AG8
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin Number
AG1
No Connect in the XC2V3000
AF19
AF16
AE32
AE3
AC30
AC5
AA28
AA21
AA20
AA19
AA18
AA17
AA16
AA15
AA14
AA7
Y33
Y21
Y20
Y19
Y18
Y17
Y16
Y15
Y14
Y2
W26
W21
W20
W19
W18
W17
W16
W15
W14
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Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin Number
W9
No Connect in the XC2V3000
V21
V20
V19
V18
V17
V16
V15
V14
U21
U20
U19
U18
U17
U16
U15
U14
T26
T21
T20
T19
T18
T17
T16
T15
T14
T9
R33
R21
R20
R19
R18
R17
R16
R15
R14
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin Number
R2
No Connect in the XC2V3000
P28
P21
P20
P19
P18
P17
P16
P15
P14
P7
M30
M5
K32
K3
J19
J16
H34
H27
H8
H1
G28
G21
G14
G7
F29
F6
E30
E23
E12
E5
D31
D4
C34
C32
C25
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Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
Pin Number
C10
C3
No Connect in the XC2V3000
GND
GND
C1
GND
B34
B33
B20
B15
B2
GND
GND
GND
GND
GND
B1
GND
A33
A32
A27
A8
GND
GND
GND
GND
A3
GND
A2
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FF1152 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch)
Figure 8: FF1152 Flip-Chip Fine-Pitch BGA Package Specifications
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FF1517 Flip-Chip Fine-Pitch BGA Package
As shown in Table 13, XC2V4000, XC2V6000, and XC2V8000 Virtex-II devices are available in the FF1517 flip-chip
fine-pitch BGA package. Pins in each of these devices are the same, except for the pin differences in the XC2V4000 and
XC2V6000 devices shown in the No Connect columns. Following this table are the FF1517 Flip-Chip Fine-Pitch BGA
Package Specifications (1.00mm pitch).
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank
0
Pin Description
IO_L01N_0
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
B36
C36
J30
0
IO_L01P_0
0
IO_L02N_0
0
IO_L02P_0
J29
0
IO_L03N_0/VRP_0
IO_L03P_0/VRN_0
IO_L04N_0/VREF_0
IO_L04P_0
D33
D34
C34
C35
H30
G30
D32
E33
0
0
0
0
IO_L05N_0
0
IO_L05P_0
0
IO_L06N_0
0
IO_L06P_0
0
IO_L07N_0
A35
A36
K28
J28
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
0
IO_L07P_0
0
IO_L08N_0
0
IO_L08P_0
0
IO_L09N_0
E32
F32
B34
B35
H29
H28
F31
G31
C32
C33
M26
M25
E30
E31
A33
0
IO_L09P_0/VREF_0
IO_L10N_0
0
0
IO_L10P_0
0
IO_L11N_0
0
IO_L11P_0
0
IO_L12N_0
0
IO_L12P_0
0
IO_L19N_0
0
IO_L19P_0
0
IO_L20N_0
0
IO_L20P_0
0
IO_L21N_0
0
IO_L21P_0/VREF_0
IO_L22N_0
0
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Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pin Description
IO_L22P_0
IO_L23N_0
IO_L23P_0
IO_L24N_0
IO_L24P_0
IO_L25N_0
IO_L25P_0
IO_L26N_0
IO_L26P_0
IO_L27N_0
IO_L27P_0/VREF_0
IO_L28N_0
IO_L28P_0
IO_L29N_0
IO_L29P_0
IO_L30N_0
IO_L30P_0
IO_L31N_0
IO_L31P_0
IO_L32N_0
IO_L32P_0
IO_L33N_0
IO_L33P_0/VREF_0
IO_L34N_0
IO_L34P_0
IO_L35N_0
IO_L35P_0
IO_L36N_0
IO_L36P_0
IO_L49N_0
IO_L49P_0
IO_L50N_0
IO_L50P_0
IO_L51N_0
IO_L51P_0/VREF_0
IO_L52N_0
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
A34
K27
K26
F29
F30
B32
B33
L26
L25
G28
G29
C30
C31
J27
J26
D30
D31
A31
A32
H27
H26
F27
F28
B30
B31
M24
M23
D28
D29
C28
C29
K25
L24
E27
E28
A29
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
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Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pin Description
IO_L52P_0
IO_L53N_0
IO_L53P_0
IO_L54N_0
IO_L54P_0
IO_L55N_0
IO_L55P_0
IO_L56N_0
IO_L56P_0
IO_L57N_0
IO_L57P_0/VREF_0
IO_L58N_0
IO_L58P_0
IO_L59N_0
IO_L59P_0
IO_L60N_0
IO_L60P_0
IO_L67N_0
IO_L67P_0
IO_L68N_0
IO_L68P_0
IO_L69N_0
IO_L69P_0/VREF_0
IO_L70N_0
IO_L70P_0
IO_L71N_0
IO_L71P_0
IO_L72N_0
IO_L72P_0
IO_L73N_0
IO_L73P_0
IO_L74N_0
IO_L74P_0
IO_L75N_0
IO_L75P_0/VREF_0
IO_L76N_0
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
A30
G26
G25
D26
D27
B27
B28
H25
H24
F25
F26
A27
A28
K24
K23
E24
E25
C26
C27
J24
J23
D24
D25
A25
A26
M22
M21
G23
G24
B25
C25
L22
L21
F23
F24
C23
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank
0
Pin Description
IO_L76P_0
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
C24
K22
K21
E22
E23
B23
B24
J22
0
IO_L77N_0
0
IO_L77P_0
0
IO_L78N_0
0
IO_L78P_0
0
IO_L79N_0
0
IO_L79P_0
0
IO_L80N_0
0
IO_L80P_0
J21
0
IO_L81N_0
G21
G22
A23
A24
H22
H21
F21
F22
B21
B22
L20
M20
E21
D22
A21
A22
H20
J20
0
IO_L81P_0/VREF_0
IO_L82N_0
0
0
IO_L82P_0
0
IO_L83N_0
0
IO_L83P_0
0
IO_L84N_0
0
IO_L84P_0
0
IO_L91N_0/VREF_0
IO_L91P_0
0
0
IO_L92N_0
0
IO_L92P_0
0
IO_L93N_0
0
IO_L93P_0
0
IO_L94N_0/VREF_0
IO_L94P_0
0
0
IO_L95N_0/GCLK7P
IO_L95P_0/GCLK6S
IO_L96N_0/GCLK5P
IO_L96P_0/GCLK4S
0
0
C21
D21
0
1
1
1
1
1
1
IO_L96N_1/GCLK3P
IO_L96P_1/GCLK2S
IO_L95N_1/GCLK1P
IO_L95P_1/GCLK0S
IO_L94N_1
F19
F20
H19
H18
C19
C20
IO_L94P_1/VREF_1
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Description
IO_L93N_1
IO_L93P_1
IO_L92N_1
IO_L92P_1
IO_L91N_1
IO_L91P_1/VREF_1
IO_L84N_1
IO_L84P_1
IO_L83N_1
IO_L83P_1
IO_L82N_1
IO_L82P_1
IO_L81N_1/VREF_1
IO_L81P_1
IO_L80N_1
IO_L80P_1
IO_L79N_1
IO_L79P_1
IO_L78N_1
IO_L78P_1
IO_L77N_1
IO_L77P_1
IO_L76N_1
IO_L76P_1
IO_L75N_1/VREF_1
IO_L75P_1
IO_L74N_1
IO_L74P_1
IO_L73N_1
IO_L73P_1
IO_L72N_1
IO_L72P_1
IO_L71N_1
IO_L71P_1
IO_L70N_1
IO_L70P_1
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
E19
E20
J19
J18
A18
A19
D18
D19
K19
K18
B18
B19
G18
G19
E18
E17
A16
A17
F17
F18
L19
L18
B16
B17
G16
G17
M19
M18
C16
C17
D15
D16
J17
J16
A14
A15
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Description
IO_L69N_1/VREF_1
IO_L69P_1
IO_L68N_1
IO_L68P_1
IO_L67N_1
IO_L67P_1
IO_L60N_1
IO_L60P_1
IO_L59N_1
IO_L59P_1
IO_L58N_1
IO_L58P_1
IO_L57N_1/VREF_1
IO_L57P_1
IO_L56N_1
IO_L56P_1
IO_L55N_1
IO_L55P_1
IO_L54N_1
IO_L54P_1
IO_L53N_1
IO_L53P_1
IO_L52N_1
IO_L52P_1
IO_L51N_1/VREF_1
IO_L51P_1
IO_L50N_1
IO_L50P_1
IO_L49N_1
IO_L49P_1
IO_L36N_1
IO_L36P_1
IO_L35N_1
IO_L35P_1
IO_L34N_1
IO_L34P_1
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
E15
E16
K17
K16
C15
B15
F15
F16
H16
H15
C13
C14
D13
D14
M17
M16
A12
A13
B12
B13
G15
G14
C11
C12
F13
F14
L16
L15
A10
A11
E12
E13
K15
J14
B9
NC
NC
NC
NC
NC
NC
B10
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Description
IO_L33N_1/VREF_1
IO_L33P_1
IO_L32N_1
IO_L32P_1
IO_L31N_1
IO_L31P_1
IO_L30N_1
IO_L30P_1
IO_L29N_1
IO_L29P_1
IO_L28N_1
IO_L28P_1
IO_L27N_1/VREF_1
IO_L27P_1
IO_L26N_1
IO_L26P_1
IO_L25N_1
IO_L25P_1
IO_L24N_1
IO_L24P_1
IO_L23N_1
IO_L23P_1
IO_L22N_1
IO_L22P_1
IO_L21N_1/VREF_1
IO_L21P_1
IO_L20N_1
IO_L20P_1
IO_L19N_1
IO_L19P_1
IO_L12N_1
IO_L12P_1
IO_L11N_1
IO_L11P_1
IO_L10N_1
IO_L10P_1
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
D11
D12
H14
H13
A8
NC
NC
NC
NC
NC
NC
A9
F11
F12
K14
L14
C9
C10
G11
G12
M15
M14
B7
B8
D9
D10
J13
J12
A6
A7
E9
E10
D8
E7
C7
C8
F9
NC
NC
NC
NC
NC
NC
F10
H12
H11
B5
B6
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank
1
Pin Description
IO_L09N_1/VREF_1
IO_L09P_1
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
G9
G10
K13
K12
A4
NC
NC
NC
NC
NC
NC
1
1
IO_L08N_1
1
IO_L08P_1
1
IO_L07N_1
1
IO_L07P_1
A5
1
IO_L06N_1
F8
1
IO_L06P_1
E8
1
IO_L05N_1
J11
K11
C5
1
IO_L05P_1
1
IO_L04N_1
1
IO_L04P_1/VREF_1
IO_L03N_1/VRP_1
IO_L03P_1/VRN_1
IO_L02N_1
C6
1
D6
1
D7
1
H10
J10
C4
1
IO_L02P_1
1
IO_L01N_1
1
IO_L01P_1
B4
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO_L01N_2
IO_L01P_2
E3
D2
IO_L02N_2/VRP_2
IO_L02P_2/VRN_2
IO_L03N_2
L13
M13
F4
IO_L03P_2/VREF_2
IO_L04N_2
E4
E1
IO_L04P_2
D1
IO_L05N_2
L12
M11
G6
IO_L05P_2
IO_L06N_2
IO_L06P_2
F5
IO_L07N_2
F2
NC
NC
NC
NC
NC
IO_L07P_2
E2
IO_L08N_2
M12
N12
H6
IO_L08P_2
IO_L09N_2
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Pin Description
IO_L09P_2/VREF_2
IO_L10N_2
IO_L10P_2
IO_L11N_2
IO_L11P_2
IO_L12N_2
IO_L12P_2
IO_L19N_2
IO_L19P_2
IO_L20N_2
IO_L20P_2
IO_L21N_2
IO_L21P_2/VREF_2
IO_L22N_2
IO_L22P_2
IO_L23N_2
IO_L23P_2
IO_L24N_2
IO_L24P_2
IO_L25N_2
IO_L25P_2
IO_L26N_2
IO_L26P_2
IO_L27N_2
IO_L27P_2/VREF_2
IO_L28N_2
IO_L28P_2
IO_L29N_2
IO_L29P_2
IO_L30N_2
IO_L30P_2
IO_L31N_2
IO_L31P_2
IO_L32N_2
IO_L32P_2
IO_L33N_2
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
H7
G3
F3
NC
NC
NC
NC
NC
NC
NC
J8
K8
H5
G5
G1
F1
K9
L10
K7
J7
H2
G2
L9
M9
H4
G4
J3
H3
M10
N10
K6
J6
K5
J5
N11
P11
M7
L7
J1
NC
NC
NC
NC
NC
H1
L8
M8
K4
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Pin Description
IO_L33P_2/VREF_2
IO_L34N_2
IO_L34P_2
IO_L35N_2
IO_L35P_2
IO_L36N_2
IO_L36P_2
IO_L43N_2
IO_L43P_2
IO_L44N_2
IO_L44P_2
IO_L45N_2
IO_L45P_2/VREF_2
IO_L46N_2
IO_L46P_2
IO_L47N_2
IO_L47P_2
IO_L48N_2
IO_L48P_2
IO_L49N_2
IO_L49P_2
IO_L50N_2
IO_L50P_2
IO_L51N_2
IO_L51P_2/VREF_2
IO_L52N_2
IO_L52P_2
IO_L53N_2
IO_L53P_2
IO_L54N_2
IO_L54P_2
IO_L55N_2
IO_L55P_2
IO_L56N_2
IO_L56P_2
IO_L57N_2
J4
K2
NC
NC
NC
NC
NC
NC
NC
J2
P12
R12
M6
L6
L3
K3
N9
P9
M4
L4
L1
K1
P10
R10
N5
M5
N3
M3
N8
P8
T11
R11
N2
M2
T12
U12
P6
N6
N1
M1
R8
T8
R7
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Pin Description
IO_L57P_2/VREF_2
IO_L58N_2
IO_L58P_2
IO_L59N_2
IO_L59P_2
IO_L60N_2
IO_L60P_2
IO_L67N_2
IO_L67P_2
IO_L68N_2
IO_L68P_2
IO_L69N_2
IO_L69P_2/VREF_2
IO_L70N_2
IO_L70P_2
IO_L71N_2
IO_L71P_2
IO_L72N_2
IO_L72P_2
IO_L73N_2
IO_L73P_2
IO_L74N_2
IO_L74P_2
IO_L75N_2
IO_L75P_2/VREF_2
IO_L76N_2
IO_L76P_2
IO_L77N_2
IO_L77P_2
IO_L78N_2
IO_L78P_2
IO_L79N_2
IO_L79P_2
IO_L80N_2
IO_L80P_2
IO_L81N_2
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
P7
R3
P3
T10
U10
P4
N4
T6
R6
T9
U9
T5
R5
R1
P1
V12
W12
T4
R4
T2
R2
V11
W11
U7
T7
U3
T3
V10
W10
V6
U6
U1
T1
V9
W9
V5
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank
2
Pin Description
IO_L81P_2/VREF_2
IO_L82N_2
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
U5
V2
2
2
IO_L82P_2
U2
2
IO_L83N_2
V8
2
IO_L83P_2
W8
W7
V7
2
IO_L84N_2
2
IO_L84P_2
2
IO_L91N_2
W1
V1
2
IO_L91P_2
2
IO_L92N_2
Y11
Y12
W4
V4
2
IO_L92P_2
2
IO_L93N_2
2
IO_L93P_2/VREF_2
IO_L94N_2
2
W2
W3
Y8
2
IO_L94P_2
2
IO_L95N_2
2
IO_L95P_2
Y9
2
IO_L96N_2
W5
W6
2
IO_L96P_2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO_L96N_3
IO_L96P_3
IO_L95N_3
IO_L95P_3
IO_L94N_3
IO_L94P_3
IO_L93N_3/VREF_3
IO_L93P_3
IO_L92N_3
IO_L92P_3
IO_L91N_3
IO_L91P_3
IO_L84N_3
IO_L84P_3
IO_L83N_3
IO_L83P_3
AB8
AA8
Y3
AA3
Y6
AA6
AB9
AA9
AA1
AB1
Y5
AA5
AB10
AA10
AA2
AB2
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Description
IO_L82N_3
IO_L82P_3
IO_L81N_3/VREF_3
IO_L81P_3
IO_L80N_3
IO_L80P_3
IO_L79N_3
IO_L79P_3
IO_L78N_3
IO_L78P_3
IO_L77N_3
IO_L77P_3
IO_L76N_3
IO_L76P_3
IO_L75N_3/VREF_3
IO_L75P_3
IO_L74N_3
IO_L74P_3
IO_L73N_3
IO_L73P_3
IO_L72N_3
IO_L72P_3
IO_L71N_3
IO_L71P_3
IO_L70N_3
IO_L70P_3
IO_L69N_3/VREF_3
IO_L69P_3
IO_L68N_3
IO_L68P_3
IO_L67N_3
IO_L67P_3
IO_L60N_3
IO_L60P_3
IO_L59N_3
IO_L59P_3
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
AA4
AB4
AB11
AA11
AC1
AD1
AA7
AB7
AB12
AA12
AC2
AC3
AB5
AC5
AD9
AC9
AD2
AE2
AB6
AC6
AD10
AC10
AD3
AE3
AC7
AD7
AE8
AD8
AE1
AF1
AD4
AE4
AD12
AC12
AF3
AG3
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R
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Description
IO_L58N_3
IO_L58P_3
IO_L57N_3/VREF_3
IO_L57P_3
IO_L56N_3
IO_L56P_3
IO_L55N_3
IO_L55P_3
IO_L54N_3
IO_L54P_3
IO_L53N_3
IO_L53P_3
IO_L52N_3
IO_L52P_3
IO_L51N_3/VREF_3
IO_L51P_3
IO_L50N_3
IO_L50P_3
IO_L49N_3
IO_L49P_3
IO_L48N_3
IO_L48P_3
IO_L47N_3
IO_L47P_3
IO_L46N_3
IO_L46P_3
IO_L45N_3/VREF_3
IO_L45P_3
IO_L44N_3
IO_L44P_3
IO_L43N_3
IO_L43P_3
IO_L36N_3
IO_L36P_3
IO_L35N_3
IO_L35P_3
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
AD5
AE5
AE11
AD11
AG1
AH1
AD6
AE6
AF10
AE10
AG2
AH2
AF4
AG4
AG8
AF8
AH3
AJ3
AE7
AF7
AG9
AF9
AF6
AG6
AG5
AH5
AF12
AE12
AJ1
AK1
AH4
AJ4
AG11
AF11
AK2
NC
NC
NC
NC
AL2
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Description
IO_L34N_3
IO_L34P_3
IO_L33N_3/VREF_3
IO_L33P_3
IO_L32N_3
IO_L32P_3
IO_L31N_3
IO_L31P_3
IO_L30N_3
IO_L30P_3
IO_L29N_3
IO_L29P_3
IO_L28N_3
IO_L28P_3
IO_L27N_3/VREF_3
IO_L27P_3
IO_L26N_3
IO_L26P_3
IO_L25N_3
IO_L25P_3
IO_L24N_3
IO_L24P_3
IO_L23N_3
IO_L23P_3
IO_L22N_3
IO_L22P_3
IO_L21N_3/VREF_3
IO_L21P_3
IO_L20N_3
IO_L20P_3
IO_L19N_3
IO_L19P_3
IO_L12N_3
IO_L12P_3
IO_L11N_3
IO_L11P_3
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
AH6
AJ6
NC
NC
NC
NC
NC
NC
NC
NC
AJ8
AH8
AL1
AM1
AH7
AJ7
AH10
AG10
AK3
AL3
AK4
AL4
AJ9
AH9
AM2
AN2
AK5
AL5
AK9
AK8
AN1
AP1
AK6
AL6
AH12
AG12
AM3
AN3
AM4
AN4
AJ12
AH11
AP2
AR2
NC
NC
NC
NC
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank
3
Pin Description
IO_L10N_3
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
AK7
AL7
NC
NC
NC
NC
NC
NC
NC
NC
3
IO_L10P_3
3
IO_L09N_3/VREF_3
IO_L09P_3
AK11
AJ10
AR1
AT1
3
3
IO_L08N_3
3
IO_L08P_3
3
IO_L07N_3
AM5
AN5
AM7
AL8
3
IO_L07P_3
3
IO_L06N_3
3
IO_L06P_3
3
IO_L05N_3
AP3
AP4
AM6
AN6
AJ13
AH13
AR3
AT2
3
IO_L05P_3
3
IO_L04N_3
3
IO_L04P_3
3
IO_L03N_3/VREF_3
IO_L03P_3
3
3
IO_L02N_3/VRP_3
IO_L02P_3/VRN_3
IO_L01N_3
3
3
AP5
AR4
3
IO_L01P_3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
IO_L01N_4/DOUT
IO_L01P_4/INIT_B
IO_L02N_4/D0
AV4
AU4
AM9
AM10
AT6
IO_L02P_4/D1
IO_L03N_4/D2/ALT_VRP_4
IO_L03P_4/D3/ALT_VRN_4
IO_L04N_4/VREF_4
IO_L04P_4
AR6
AU6
AU5
IO_L05N_4/VRP_4
IO_L05P_4/VRN_4
IO_L06N_4
AL10
AL11
AR8
AR7
AW5
AW4
AK12
IO_L06P_4
IO_L07N_4
NC
NC
NC
IO_L07P_4
IO_L08N_4
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Pin Description
IO_L08P_4
IO_L09N_4
IO_L09P_4/VREF_4
IO_L10N_4
IO_L10P_4
IO_L11N_4
IO_L11P_4
IO_L12N_4
IO_L12P_4
IO_L19N_4
IO_L19P_4
IO_L20N_4
IO_L20P_4
IO_L21N_4
IO_L21P_4/VREF_4
IO_L22N_4
IO_L22P_4
IO_L23N_4
IO_L23P_4
IO_L24N_4
IO_L24P_4
IO_L25N_4
IO_L25P_4
IO_L26N_4
IO_L26P_4
IO_L27N_4
IO_L27P_4/VREF_4
IO_L28N_4
IO_L28P_4
IO_L29N_4
IO_L29P_4
IO_L30N_4
IO_L30P_4
IO_L31N_4
IO_L31P_4
IO_L32N_4
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
AL12
AP9
NC
NC
NC
NC
NC
NC
NC
NC
NC
AP8
AV6
AV5
AM11
AM12
AN10
AN9
AU8
AU7
AH14
AH15
AT8
AT7
AW7
AW6
AK13
AK14
AR10
AR9
AV8
AV7
AJ14
AJ15
AP11
AP10
AU10
AU9
AL13
AL14
AN12
AN11
AW9
AW8
AM13
NC
NC
NC
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Bank
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Pin Description
IO_L32P_4
IO_L33N_4
IO_L33P_4/VREF_4
IO_L34N_4
IO_L34P_4
IO_L35N_4
IO_L35P_4
IO_L36N_4
IO_L36P_4
IO_L49N_4
IO_L49P_4
IO_L50N_4
IO_L50P_4
IO_L51N_4
IO_L51P_4/VREF_4
IO_L52N_4
IO_L52P_4
IO_L53N_4
IO_L53P_4
IO_L54N_4
IO_L54P_4
IO_L55N_4
IO_L55P_4
IO_L56N_4
IO_L56P_4
IO_L57N_4
IO_L57P_4/VREF_4
IO_L58N_4
IO_L58P_4
IO_L59N_4
IO_L59P_4
IO_L60N_4
IO_L60P_4
IO_L67N_4
IO_L67P_4
IO_L68N_4
AM14
AT10
AT9
NC
NC
NC
NC
NC
NC
NC
NC
NC
AV10
AV9
AH16
AH17
AP13
AP12
AU12
AU11
AK15
AJ16
AT12
AT11
AN15
AN14
AR12
AR13
AT14
AT13
AW11
AW10
AM15
AM16
AP15
AP14
AV13
AV12
AK16
AK17
AR16
AR15
AW13
AW12
AL16
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Pin Description
IO_L68P_4
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
AL17
AT16
AT15
AU14
AU13
AH18
AH19
AN17
AN16
AW15
AW14
AJ18
AJ19
AP17
AP16
AV15
AU15
AK18
AK19
AR18
AR17
AU17
AU16
AL18
AL19
AN19
AN18
AV17
AV16
AM18
AM19
AP19
AP18
IO_L69N_4
IO_L69P_4/VREF_4
IO_L70N_4
IO_L70P_4
IO_L71N_4
IO_L71P_4
IO_L72N_4
IO_L72P_4
IO_L73N_4
IO_L73P_4
IO_L74N_4
IO_L74P_4
IO_L75N_4
IO_L75P_4/VREF_4
IO_L76N_4
IO_L76P_4
IO_L77N_4
IO_L77P_4
IO_L78N_4
IO_L78P_4
IO_L79N_4
IO_L79P_4
IO_L80N_4
IO_L80P_4
IO_L81N_4
IO_L81P_4/VREF_4
IO_L82N_4
IO_L82P_4
IO_L83N_4
IO_L83P_4
IO_L84N_4
IO_L84P_4
IO_L85N_4
IO_L85P_4
AW17
AW16
AV19
NC
NC
NC
NC
IO_L91N_4/VREF_4
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank
Pin Description
IO_L91P_4
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
4
4
4
4
4
4
4
4
4
4
4
AV18
AH20
AJ20
AR19
AT18
AW19
AW18
AL20
AM20
AU19
AT19
IO_L92N_4
IO_L92P_4
IO_L93N_4
IO_L93P_4
IO_L94N_4/VREF_4
IO_L94P_4
IO_L95N_4/GCLK3S
IO_L95P_4/GCLK2P
IO_L96N_4/GCLK1S
IO_L96P_4/GCLK0P
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
IO_L96N_5/GCLK7S
IO_L96P_5/GCLK6P
IO_L95N_5/GCLK5S
IO_L95P_5/GCLK4P
IO_L94N_5
AP21
AP20
AN21
AN22
AU21
AU20
AR21
AR20
AM21
AM22
AW22
AW21
IO_L94P_5/VREF_5
IO_L93N_5
IO_L93P_5
IO_L92N_5
IO_L92P_5
IO_L91N_5
IO_L91P_5/VREF_5
IO_L85N_5
AV22
AV21
AT22
AT21
AL21
AL22
AW24
AW23
AR23
AR22
AK21
AK22
NC
NC
NC
NC
IO_L85P_5
IO_L84N_5
IO_L84P_5
IO_L83N_5
IO_L83P_5
IO_L82N_5
IO_L82P_5
IO_L81N_5/VREF_5
IO_L81P_5
IO_L80N_5
IO_L80P_5
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
Pin Description
IO_L79N_5
IO_L79P_5
IO_L78N_5
IO_L78P_5
IO_L77N_5
IO_L77P_5
IO_L76N_5
IO_L76P_5
IO_L75N_5/VREF_5
IO_L75P_5
IO_L74N_5
IO_L74P_5
IO_L73N_5
IO_L73P_5
IO_L72N_5
IO_L72P_5
IO_L71N_5
IO_L71P_5
IO_L70N_5
IO_L70P_5
IO_L69N_5/VREF_5
IO_L69P_5
IO_L68N_5
IO_L68P_5
IO_L67N_5
IO_L67P_5
IO_L60N_5
IO_L60P_5
IO_L59N_5
IO_L59P_5
IO_L58N_5
IO_L58P_5
IO_L57N_5/VREF_5
IO_L57P_5
IO_L56N_5
IO_L56P_5
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
AV24
AV23
AP23
AP22
AJ21
AJ22
AU24
AU23
AT25
AT24
AH21
AH22
AW26
AW25
AR25
AR24
AN23
AN24
AU25
AV25
AL24
AL23
AK23
AK24
AU27
AU26
AP25
AP24
AM24
AM25
AW28
AW27
AT27
AT26
AH23
AH24
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
Pin Description
IO_L55N_5
IO_L55P_5
IO_L54N_5
IO_L54P_5
IO_L53N_5
IO_L53P_5
IO_L52N_5
IO_L52P_5
IO_L51N_5/VREF_5
IO_L51P_5
IO_L50N_5
IO_L50P_5
IO_L49N_5
IO_L49P_5
IO_L36N_5
IO_L36P_5
IO_L35N_5
IO_L35P_5
IO_L34N_5
IO_L34P_5
IO_L33N_5/VREF_5
IO_L33P_5
IO_L32N_5
IO_L32P_5
IO_L31N_5
IO_L31P_5
IO_L30N_5
IO_L30P_5
IO_L29N_5
IO_L29P_5
IO_L28N_5
IO_L28P_5
IO_L27N_5/VREF_5
IO_L27P_5
IO_L26N_5
IO_L26P_5
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
AV28
AV27
AP27
AP26
AN25
AN26
AU29
AU28
AR28
AR27
AJ24
AJ25
AW30
AW29
AT29
AT28
AK25
AL26
AV31
AV30
AP29
AP28
AK26
AJ26
AW32
AW31
AM27
AM26
AN28
AN29
AU31
AU30
AT31
AT30
AH25
AH26
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
Pin Description
IO_L25N_5
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
AV33
AV32
AR31
AR30
AL27
AL28
AW34
AW33
AN30
AP30
AM28
AM29
AU33
AU32
IO_L25P_5
IO_L24N_5
IO_L24P_5
IO_L23N_5
IO_L23P_5
IO_L22N_5
IO_L22P_5
IO_L21N_5/VREF_5
IO_L21P_5
IO_L20N_5
IO_L20P_5
IO_L19N_5
IO_L19P_5
IO_L12N_5
AT33
AT32
AK27
AK28
AV35
AV34
AP32
AP31
AL29
AK29
AW36
AW35
AR33
AR32
AM30
AL30
AU35
AU34
AR34
AT34
AN31
AM31
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IO_L12P_5
IO_L11N_5
IO_L11P_5
IO_L10N_5
IO_L10P_5
IO_L09N_5/VREF_5
IO_L09P_5
IO_L08N_5
IO_L08P_5
IO_L07N_5
IO_L07P_5
IO_L06N_5
IO_L06P_5
IO_L05N_5/VRP_5
IO_L05P_5/VRN_5
IO_L04N_5
IO_L04P_5/VREF_5
IO_L03N_5/D4/ALT_VRP_5
IO_L03P_5/D5/ALT_VRN_5
IO_L02N_5/D6
IO_L02P_5/D7
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank
Pin Description
IO_L01N_5/RDWR_B
IO_L01P_5/CS_B
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
5
5
AU36
AV36
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
IO_L01P_6
IO_L01N_6
AJ27
AH27
AT38
AR37
AP36
AR36
AJ28
AH29
AT39
AR39
AN34
AP35
IO_L02P_6/VRN_6
IO_L02N_6/VRP_6
IO_L03P_6
IO_L03N_6/VREF_6
IO_L04P_6
IO_L04N_6
IO_L05P_6
IO_L05N_6
IO_L06P_6
IO_L06N_6
IO_L07P_6
AH28
AG28
AR38
AP38
AM34
AM33
AL32
AK32
AP37
AN37
AM35
AN35
AK31
AJ30
AP39
AN39
AK33
AL33
AJ31
AH31
AN38
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IO_L07N_6
IO_L08P_6
IO_L08N_6
IO_L09P_6
IO_L09N_6/VREF_6
IO_L10P_6
IO_L10N_6
IO_L11P_6
IO_L11N_6
IO_L12P_6
IO_L12N_6
IO_L19P_6
IO_L19N_6
IO_L20P_6
IO_L20N_6
IO_L21P_6
IO_L21N_6/VREF_6
IO_L22P_6
IO_L22N_6
IO_L23P_6
DS031-4 (v1.8) October 7, 2002
Advance Product Specification
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
Pin Description
IO_L23N_6
IO_L24P_6
IO_L24N_6
IO_L25P_6
IO_L25N_6
IO_L26P_6
IO_L26N_6
IO_L27P_6
IO_L27N_6/VREF_6
IO_L28P_6
IO_L28N_6
IO_L29P_6
IO_L29N_6
IO_L30P_6
IO_L30N_6
IO_L31P_6
IO_L31N_6
IO_L32P_6
IO_L32N_6
IO_L33P_6
IO_L33N_6/VREF_6
IO_L34P_6
IO_L34N_6
IO_L35P_6
IO_L35N_6
IO_L36P_6
IO_L36N_6
IO_L43P_6
IO_L43N_6
IO_L44P_6
IO_L44N_6
IO_L45P_6
IO_L45N_6/VREF_6
IO_L46P_6
IO_L46N_6
IO_L47P_6
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
AM38
AM36
AN36
AH30
AG30
AM37
AL37
AK34
AL34
AG29
AF29
AL35
AK35
AH33
AJ33
AJ32
AH32
AM39
AL39
AK36
AL36
AF28
AE28
AL38
AK38
AH34
AJ34
AG31
AF31
AK37
AJ37
AH36
AJ36
AF30
AE30
AK39
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
Pin Description
IO_L47N_6
IO_L48P_6
IO_L48N_6
IO_L49P_6
IO_L49N_6
IO_L50P_6
IO_L50N_6
IO_L51P_6
IO_L51N_6/VREF_6
IO_L52P_6
IO_L52N_6
IO_L53P_6
IO_L53N_6
IO_L54P_6
IO_L54N_6
IO_L55P_6
IO_L55N_6
IO_L56P_6
IO_L56N_6
IO_L57P_6
IO_L57N_6/VREF_6
IO_L58P_6
IO_L58N_6
IO_L59P_6
IO_L59N_6
IO_L60P_6
IO_L60N_6
IO_L67P_6
IO_L67N_6
IO_L68P_6
IO_L68N_6
IO_L69P_6
IO_L69N_6/VREF_6
IO_L70P_6
IO_L70N_6
IO_L71P_6
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
AJ39
AG35
AH35
AG32
AF32
AH37
AG37
AD29
AE29
AD28
AC28
AH38
AG38
AF34
AG34
AE32
AD32
AH39
AG39
AE33
AF33
AD30
AC30
AF37
AE37
AF36
AG36
AD31
AC31
AE34
AD34
AD35
AE35
AB28
AA28
AF39
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
Pin Description
IO_L71N_6
IO_L72P_6
IO_L72N_6
IO_L73P_6
IO_L73N_6
IO_L74P_6
IO_L74N_6
IO_L75P_6
IO_L75N_6/VREF_6
IO_L76P_6
IO_L76N_6
IO_L77P_6
IO_L77N_6
IO_L78P_6
IO_L78N_6
IO_L79P_6
IO_L79N_6
IO_L80P_6
IO_L80N_6
IO_L81P_6
IO_L81N_6/VREF_6
IO_L82P_6
IO_L82N_6
IO_L83P_6
IO_L83N_6
IO_L84P_6
IO_L84N_6
IO_L91P_6
IO_L91N_6
IO_L92P_6
IO_L92N_6
IO_L93P_6
IO_L93N_6/VREF_6
IO_L94P_6
IO_L94N_6
IO_L95P_6
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
AE39
AD36
AE36
AB29
AA29
AE38
AD38
AC33
AD33
AB30
AA30
AD37
AC37
AB34
AC34
AB31
AA31
AD39
AC39
AB35
AC35
AB32
AA32
AC38
AB38
AA33
AB33
Y28
Y29
AB39
AA39
AA36
AB36
Y31
Y32
AA37
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank
Pin Description
IO_L95N_6
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
6
6
6
AA38
AA35
AA34
IO_L96P_6
IO_L96N_6
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
IO_L96P_7
IO_L96N_7
IO_L95P_7
IO_L95N_7
IO_L94P_7
IO_L94N_7
IO_L93P_7/VREF_7
IO_L93N_7
IO_L92P_7
IO_L92N_7
IO_L91P_7
IO_L91N_7
IO_L84P_7
IO_L84N_7
IO_L83P_7
IO_L83N_7
IO_L82P_7
IO_L82N_7
IO_L81P_7/VREF_7
IO_L81N_7
IO_L80P_7
IO_L80N_7
IO_L79P_7
IO_L79N_7
IO_L78P_7
IO_L78N_7
IO_L77P_7
IO_L77N_7
IO_L76P_7
IO_L76N_7
IO_L75P_7/VREF_7
IO_L75N_7
W34
Y34
W32
V32
W37
Y37
W35
Y35
W31
V31
V39
W39
V36
W36
W30
V30
V38
W38
V33
W33
W29
V29
T39
U39
U35
V35
W28
V28
U37
U38
U34
V34
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
Pin Description
IO_L74P_7
IO_L74N_7
IO_L73P_7
IO_L73N_7
IO_L72P_7
IO_L72N_7
IO_L71P_7
IO_L71N_7
IO_L70P_7
IO_L70N_7
IO_L69P_7/VREF_7
IO_L69N_7
IO_L68P_7
IO_L68N_7
IO_L67P_7
IO_L67N_7
IO_L60P_7
IO_L60N_7
IO_L59P_7
IO_L59N_7
IO_L58P_7
IO_L58N_7
IO_L57P_7/VREF_7
IO_L57N_7
IO_L56P_7
IO_L56N_7
IO_L55P_7
IO_L55N_7
IO_L54P_7
IO_L54N_7
IO_L53P_7
IO_L53N_7
IO_L52P_7
IO_L52N_7
IO_L51P_7/VREF_7
IO_L51N_7
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
U31
T31
R38
T38
T33
U33
U30
T30
R37
T37
R36
T36
T32
R32
P39
R39
R35
T35
U28
T28
N37
P37
R34
T34
T29
R29
M39
N39
N36
P36
R30
P30
M38
N38
P33
R33
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
Pin Description
IO_L50P_7
IO_L50N_7
IO_L49P_7
IO_L49N_7
IO_L48P_7
IO_L48N_7
IO_L47P_7
IO_L47N_7
IO_L46P_7
IO_L46N_7
IO_L45P_7/VREF_7
IO_L45N_7
IO_L44P_7
IO_L44N_7
IO_L43P_7
IO_L43N_7
IO_L36P_7
IO_L36N_7
IO_L35P_7
IO_L35N_7
IO_L34P_7
IO_L34N_7
IO_L33P_7/VREF_7
IO_L33N_7
IO_L32P_7
IO_L32N_7
IO_L31P_7
IO_L31N_7
IO_L30P_7
IO_L30N_7
IO_L29P_7
IO_L29N_7
IO_L28P_7
IO_L28N_7
IO_L27P_7/VREF_7
IO_L27N_7
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
P32
N32
L37
M37
N34
P34
P31
N31
M35
N35
L36
M36
R28
P28
K39
L39
L34
M34
P29
N29
J38
K38
L33
M33
M32
L32
H39
J39
J36
K36
N30
M30
J37
K37
J35
K35
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
Pin Description
IO_L26P_7
IO_L26N_7
IO_L25P_7
IO_L25N_7
IO_L24P_7
IO_L24N_7
IO_L23P_7
IO_L23N_7
IO_L22P_7
IO_L22N_7
IO_L21P_7/VREF_7
IO_L21N_7
IO_L20P_7
IO_L20N_7
IO_L19P_7
IO_L19N_7
IO_L12P_7
IO_L12N_7
IO_L11P_7
IO_L11N_7
IO_L10P_7
IO_L10N_7
IO_L09P_7/VREF_7
IO_L09N_7
IO_L08P_7
IO_L08N_7
IO_L07P_7
IO_L07N_7
IO_L06P_7
IO_L06N_7
IO_L05P_7
IO_L05N_7
IO_L04P_7
IO_L04N_7
IO_L03P_7/VREF_7
IO_L03N_7
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
M31
L31
G38
H38
J34
K34
K32
K31
F39
G39
G36
H36
N28
M28
G37
H37
J33
K33
M29
L28
E38
F38
G35
H35
L30
K29
D39
E39
G34
H34
J32
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
H33
F36
F37
E36
F35
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank
Pin Description
IO_L02P_7/VRN_7
IO_L02N_7/VRP_7
IO_L01P_7
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
7
7
7
7
M27
L27
D38
E37
IO_L01N_7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
P25
P24
P23
P22
P21
N26
N25
N24
N23
N22
N21
L23
J25
G27
E29
C22
B26
P19
P18
P17
P16
P15
N19
N18
N17
N16
N15
N14
L17
J15
G13
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Description
VCCO_1
VCCO_1
VCCO_1
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
E11
C18
B14
W14
W13
V14
V13
V3
U14
U13
U11
T14
T13
R14
R13
R9
P13
P2
N7
L5
AJ5
AG7
AF13
AF2
AE14
AE13
AE9
AD14
AD13
AC14
AC13
AC11
AB14
AB13
AB3
AA14
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6
Pin Description
VCCO_3
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_6
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
AA13
AV14
AU18
AR11
AN13
AL15
AJ17
AG19
AG18
AG17
AG16
AG15
AG14
AF19
AF18
AF17
AF16
AF15
AV26
AU22
AR29
AN27
AL25
AJ23
AG26
AG25
AG24
AG23
AG22
AG21
AF25
AF24
AF23
AF22
AF21
AJ35
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank
6
Pin Description
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
AG33
AF38
AF27
AE31
AE27
AE26
AD27
AD26
AC29
AC27
AC26
AB37
AB27
AB26
AA27
AA26
W27
W26
V37
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
7
7
7
7
V27
7
V26
7
U29
7
U27
7
U26
7
T27
7
T26
7
R31
7
R27
7
R26
7
P38
7
P27
7
N33
7
L35
NA
NA
CCLK
AT5
H31
PROG_B
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
DONE
M0
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
AP7
AN32
AP33
AT35
E34
G8
M1
M2
HSWAP_EN
TCK
TDI
D35
E6
TDO
TMS
F7
PWRDWN_B
DXN
AN8
G32
F33
D5
DXP
VBATT
RSVD
H9
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
AV20
AT37
AT3
Y38
Y2
D37
D3
B20
AG27
AG20
AG13
AF26
AF20
AF14
AE25
AE24
AE23
AE22
AE21
AE20
AE19
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
AE18
AE17
AE16
AE15
AD25
AD24
AD16
AD15
AC25
AC15
AB25
AB15
AA25
AA15
Y27
Y26
Y25
Y15
Y14
Y13
W25
W15
V25
V15
U25
U15
T25
T24
T16
T15
R25
R24
R23
R22
R21
R20
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Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
GND
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
R19
R18
R17
R16
R15
P26
P20
P14
N27
N20
N13
AW38
AW37
AW20
AW3
AW2
AV39
AV38
AV37
AV29
AV11
AV3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AV2
GND
AV1
GND
AU39
AU38
AU37
AU3
GND
GND
GND
GND
AU2
GND
AU1
GND
AT36
AT23
AT20
AT17
AT4
GND
GND
GND
GND
GND
AR35
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
AR26
AR14
AR5
AP34
AP6
AN33
AN20
AN7
AM32
AM23
AM17
AM8
AL31
AL9
AK30
AK20
AK10
AJ38
AJ29
AJ11
AJ2
AF35
AF5
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AC36
AC32
AC24
AC23
AC22
AC21
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
AC20
AC19
AC18
AC17
AC16
AC8
AC4
AB24
AB23
AB22
AB21
AB20
AB19
AB18
AB17
AB16
AA24
AA23
AA22
AA21
AA20
AA19
AA18
AA17
AA16
Y39
Y36
Y33
Y30
Y24
Y23
Y22
Y21
Y20
Y19
Y18
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Y17
Y16
Y10
Y7
Y4
Y1
W24
W23
W22
W21
W20
W19
W18
W17
W16
V24
V23
V22
V21
V20
V19
V18
V17
V16
U36
U32
U24
U23
U22
U21
U20
U19
U18
U17
U16
U8
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
U4
T23
T22
T21
T20
T19
T18
T17
P35
P5
L38
L29
L11
L2
K30
K20
K10
J31
J9
H32
H23
H17
H8
G33
G20
G7
F34
F6
E35
E26
E14
E5
D36
D23
D20
D17
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Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
D4
C39
C38
C37
C3
GND
GND
GND
GND
GND
C2
GND
C1
GND
B39
B38
B37
B29
B11
B3
GND
GND
GND
GND
GND
GND
B2
GND
B1
GND
A38
A37
A20
A3
GND
GND
GND
GND
A2
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FF1517 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch)
Figure 9: FF1517 Flip-Chip Fine-Pitch BGA Package Specifications
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
BF957 Flip-Chip BGA Package
As shown in Table 14, XC2V2000, XC2V3000, XC2V4000, and XC2V6000 Virtex-II devices are available in the BF957
package. Pins in each of these devices are the same, except for the pin differences in the XC2V2000 device shown in the
No Connect column. Following this table are the BF957 Flip-Chip BGA Package Specifications (1.27mm pitch).
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pin Description
IO_L01N_0
Pin Number
H23
H22
G24
E25
B29
C27
F24
No Connect in XC2V2000
IO_L01P_0
IO_L02N_0
IO_L02P_0
IO_L03N_0/VRP_0
IO_L03P_0/VRN_0
IO_L04N_0/VREF_0
IO_L04P_0
F23
IO_L05N_0
D26
D25
A28
A27
J22
IO_L05P_0
IO_L06N_0
IO_L06P_0
IO_L19N_0
IO_L19P_0
J21
IO_L20N_0
G23
G22
B27
B26
K20
K19
C26
C24
D24
D23
E24
E23
G21
G20
A26
A25
H21
H20
B25
B23
IO_L20P_0
IO_L21N_0
IO_L21P_0/VREF_0
IO_L22N_0
IO_L22P_0
IO_L23N_0
IO_L23P_0
IO_L24N_0
IO_L24P_0
IO_L25N_0
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IO_L25P_0
IO_L26N_0
IO_L26P_0
IO_L27N_0
IO_L27P_0/VREF_0
IO_L29N_0
IO_L29P_0
IO_L30N_0
IO_L30P_0
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pin Description
IO_L49N_0
IO_L49P_0
Pin Number
C23
C22
E22
E21
F21
F20
A24
A23
E20
E19
B22
B21
D21
D20
J20
No Connect in XC2V2000
IO_L50N_0
IO_L50P_0
IO_L51N_0
IO_L51P_0/VREF_0
IO_L52N_0
IO_L52P_0
IO_L53N_0
IO_L53P_0
IO_L54N_0
IO_L54P_0
IO_L67N_0
IO_L67P_0
IO_L68N_0
IO_L68P_0
J19
IO_L69N_0
IO_L69P_0/VREF_0
IO_L70N_0
IO_L70P_0
F19
F18
A22
A21
H19
H17
C21
C20
B20
B19
G18
G17
E18
D17
A20
A19
D19
D18
C19
C17
K18
J18
IO_L71N_0
IO_L71P_0
IO_L72N_0
IO_L72P_0
IO_L73N_0
IO_L73P_0
IO_L74N_0
IO_L74P_0
IO_L75N_0
IO_L75P_0/VREF_0
IO_L76N_0
IO_L76P_0
IO_L77N_0
IO_L77P_0
IO_L78N_0
IO_L78P_0
IO_L91N_0/VREF_0
IO_L91P_0
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Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000
Bank
Pin Description
IO_L92N_0
Pin Number
F17
No Connect in XC2V2000
0
0
0
0
0
0
0
0
0
0
IO_L92P_0
F16
IO_L93N_0
B18
IO_L93P_0
B17
IO_L94N_0/VREF_0
IO_L94P_0
J17
J16
IO_L95N_0/GCLK7P
IO_L95P_0/GCLK6S
IO_L96N_0/GCLK5P
IO_L96P_0/GCLK4S
E17
E16
A18
A17
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IO_L96N_1/GCLK3P
IO_L96P_1/GCLK2S
IO_L95N_1/GCLK1P
IO_L95P_1/GCLK0S
IO_L94N_1
C16
C15
H16
H15
A15
A14
F15
F14
G15
G14
B15
B14
D15
E15
J15
IO_L94P_1/VREF_1
IO_L93N_1
IO_L93P_1
IO_L92N_1
IO_L92P_1
IO_L91N_1
IO_L91P_1/VREF_1
IO_L78N_1
IO_L78P_1
IO_L77N_1
IO_L77P_1
K14
D14
D13
E14
E13
A13
A12
F13
F12
J14
IO_L76N_1
IO_L76P_1
IO_L75N_1/VREF_1
IO_L75P_1
IO_L74N_1
IO_L74P_1
IO_L73N_1
IO_L73P_1
IO_L72N_1
IO_L72P_1
J13
IO_L71N_1
B13
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Description
IO_L71P_1
Pin Number
B12
C13
C12
H13
H12
D12
D11
B11
B10
E12
E11
A11
A10
G12
G11
K13
K12
C11
C10
B9
No Connect in XC2V2000
IO_L70N_1
IO_L70P_1
IO_L69N_1/VREF_1
IO_L69P_1
IO_L68N_1
IO_L68P_1
IO_L67N_1
IO_L67P_1
IO_L54N_1
IO_L54P_1
IO_L53N_1
IO_L53P_1
IO_L52N_1
IO_L52P_1
IO_L51N_1/VREF_1
IO_L51P_1
IO_L50N_1
IO_L50P_1
IO_L49N_1
IO_L49P_1
B7
IO_L30N_1
IO_L30P_1
F11
F9
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IO_L29N_1
IO_L29P_1
A9
A8
IO_L27N_1/VREF_1
IO_L27P_1
D9
D8
IO_L26N_1
IO_L26P_1
J12
J11
C9
IO_L25N_1
IO_L25P_1
C8
IO_L24N_1
IO_L24P_1
E10
E9
IO_L23N_1
IO_L23P_1
H11
H10
A7
IO_L22N_1
IO_L22P_1
A6
IO_L21N_1/VREF_1
A5
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Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000
Bank
Pin Description
IO_L21P_1
Pin Number
No Connect in XC2V2000
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A4
G10
G9
B6
C5
C6
D6
H9
G8
D7
E6
E8
E7
F8
IO_L20N_1
IO_L20P_1
IO_L19N_1
IO_L19P_1
IO_L06N_1
IO_L06P_1
IO_L05N_1
IO_L05P_1
IO_L04N_1
IO_L04P_1/VREF_1
IO_L03N_1/VRP_1
IO_L03P_1/VRN_1
IO_L02N_1
IO_L02P_1
F7
IO_L01N_1
B5
B3
IO_L01P_1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO_L01N_2
IO_L01P_2
F5
G4
G6
H6
D3
E4
K10
K9
D2
E3
F4
IO_L02N_2/VRP_2
IO_L02P_2/VRN_2
IO_L03N_2
IO_L03P_2/VREF_2
IO_L04N_2
IO_L04P_2
IO_L05N_2
IO_L05P_2
IO_L06N_2
IO_L06P_2
F3
IO_L19N_2
L10
M10
H7
J8
IO_L19P_2
IO_L20N_2
IO_L20P_2
IO_L21N_2
D1
E1
G5
H5
IO_L21P_2/VREF_2
IO_L22N_2
IO_L22P_2
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Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Pin Description
IO_L23N_2
IO_L23P_2
Pin Number
E2
F2
No Connect in XC2V2000
IO_L24N_2
IO_L24P_2
H4
J4
IO_L25N_2
IO_L25P_2
K8
L8
NC
NC
NC
NC
IO_L27N_2
IO_L27P_2/VREF_2
IO_L43N_2
IO_L43P_2
J7
K7
F1
G1
L9
IO_L44N_2
IO_L44P_2
M9
G2
J2
IO_L45N_2
IO_L45P_2/VREF_2
IO_L46N_2
IO_L46P_2
H3
J3
IO_L47N_2
IO_L47P_2
J6
L6
IO_L48N_2
IO_L48P_2
J5
K5
H1
J1
IO_L49N_2
IO_L49P_2
IO_L50N_2
IO_L50P_2
N10
P10
L7
IO_L51N_2
IO_L51P_2/VREF_2
IO_L52N_2
IO_L52P_2
M7
K3
L3
IO_L53N_2
IO_L53P_2
M8
N8
L5
IO_L54N_2
IO_L54P_2
M5
K2
L2
IO_L67N_2
IO_L67P_2
IO_L68N_2
IO_L68P_2
M6
N6
L4
IO_L69N_2
IO_L69P_2/VREF_2
M4
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000
Bank
2
Pin Description
IO_L70N_2
IO_L70P_2
IO_L71N_2
IO_L71P_2
IO_L72N_2
IO_L72P_2
IO_L73N_2
IO_L73P_2
IO_L74N_2
IO_L74P_2
IO_L75N_2
IO_L75P_2/VREF_2
IO_L76N_2
IO_L76P_2
IO_L77N_2
IO_L77P_2
IO_L78N_2
IO_L78P_2
IO_L91N_2
IO_L91P_2
IO_L92N_2
IO_L92P_2
IO_L93N_2
IO_L93P_2/VREF_2
IO_L94N_2
IO_L94P_2
IO_L95N_2
IO_L95P_2
IO_L96N_2
IO_L96P_2
Pin Number
K1
No Connect in XC2V2000
2
L1
2
N9
P9
2
2
N5
P5
2
2
M3
N3
R8
R9
M2
N2
M1
N1
P7
2
2
2
2
2
2
2
2
2
R7
N4
P4
2
2
2
T8
2
T9
2
P6
2
R6
P2
2
2
R2
R5
T5
2
2
2
P1
2
R1
R4
R3
2
2
3
3
3
3
3
3
3
IO_L96N_3
IO_L96P_3
T6
U5
U6
V6
T3
U3
U1
IO_L95N_3
IO_L95P_3
IO_L94N_3
IO_L94P_3
IO_L93N_3/VREF_3
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000
Bank
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Description
IO_L93P_3
IO_L92N_3
IO_L92P_3
IO_L91N_3
IO_L91P_3
IO_L78N_3
IO_L78P_3
IO_L77N_3
IO_L77P_3
IO_L76N_3
IO_L76P_3
IO_L75N_3/VREF_3
IO_L75P_3
IO_L74N_3
IO_L74P_3
IO_L73N_3
IO_L73P_3
IO_L72N_3
IO_L72P_3
IO_L71N_3
IO_L71P_3
IO_L70N_3
IO_L70P_3
IO_L69N_3/VREF_3
IO_L69P_3
IO_L68N_3
IO_L68P_3
IO_L67N_3
IO_L67P_3
IO_L54N_3
IO_L54P_3
IO_L53N_3
IO_L53P_3
IO_L52N_3
IO_L52P_3
IO_L51N_3/VREF_3
IO_L51P_3
IO_L50N_3
Pin Number
V1
No Connect in XC2V2000
U8
W8
U2
V2
U7
V7
U4
V4
W1
Y1
V5
W5
W2
Y2
W6
Y6
Y5
AA5
W3
Y3
W4
Y4
U9
V9
AA1
AB1
Y7
AA7
AA6
AC6
AA2
AB2
AA4
AC4
V10
W10
AA3
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000
Bank
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Description
IO_L50P_3
Pin Number
AB3
AB5
AC5
W9
No Connect in XC2V2000
IO_L49N_3
IO_L49P_3
IO_L48N_3
IO_L48P_3
Y9
IO_L47N_3
IO_L47P_3
AC1
AD1
AC3
AD3
Y8
IO_L46N_3
IO_L46P_3
IO_L45N_3/VREF_3
IO_L45P_3
AA8
AC2
AE2
AB7
AC7
Y10
IO_L44N_3
IO_L44P_3
IO_L43N_3
IO_L43P_3
IO_L27N_3/VREF_3
IO_L27P_3
NC
NC
NC
NC
AA10
AE1
AF1
AF2
AG2
AA9
AB9
AD4
AE4
AD5
AE5
AB8
AC8
AG1
AH1
AF4
AG4
AB10
AB11
AF3
AG3
AD6
IO_L25N_3
IO_L25P_3
IO_L24N_3
IO_L24P_3
IO_L23N_3
IO_L23P_3
IO_L22N_3
IO_L22P_3
IO_L21N_3/VREF_3
IO_L21P_3
IO_L20N_3
IO_L20P_3
IO_L19N_3
IO_L19P_3
IO_L06N_3
IO_L06P_3
IO_L05N_3
IO_L05P_3
IO_L04N_3
IO_L04P_3
IO_L03N_3/VREF_3
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000
Bank
Pin Description
IO_L03P_3
Pin Number
AD7
No Connect in XC2V2000
3
3
3
3
3
IO_L02N_3/VRP_3
IO_L02P_3/VRN_3
IO_L01N_3
AE6
AF5
AH2
IO_L01P_3
AH3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
IO_L01N_4/DOUT
IO_L01P_4/INIT_B
IO_L02N_4/D0
IO_L02P_4/D1
IO_L03N_4/D2/ALT_VRP_4
IO_L03P_4/D3/ALT_VRN_4
IO_L04N_4/VREF_4
IO_L04P_4
AD9
AD10
AF7
AG7
AK3
AJ5
AE8
AF8
IO_L05N_4/VRP_4
IO_L05P_4/VRN_4
IO_L06N_4
AK4
AK5
AH6
AH7
AC10
AC11
AE9
AE10
AL4
IO_L06P_4
IO_L19N_4
IO_L19P_4
IO_L20N_4
IO_L20P_4
IO_L21N_4
IO_L21P_4/VREF_4
IO_L22N_4
AL5
AB12
AB13
AJ6
IO_L22P_4
IO_L23N_4
IO_L23P_4
AJ8
IO_L24N_4
AK6
AK7
AG8
AG9
AF9
IO_L24P_4
IO_L25N_4
NC
NC
NC
NC
NC
NC
NC
NC
IO_L25P_4
IO_L26N_4
IO_L26P_4
AF11
AH8
AH9
AD11
AD12
IO_L27N_4
IO_L27P_4/VREF_4
IO_L28N_4
IO_L28P_4
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000
Bank
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Pin Description
IO_L29N_4
IO_L29P_4
IO_L30N_4
IO_L30P_4
IO_L49N_4
IO_L49P_4
IO_L50N_4
IO_L50P_4
IO_L51N_4
IO_L51P_4/VREF_4
IO_L52N_4
IO_L52P_4
IO_L53N_4
IO_L53P_4
IO_L54N_4
IO_L54P_4
IO_L67N_4
IO_L67P_4
IO_L68N_4
IO_L68P_4
IO_L69N_4
IO_L69P_4/VREF_4
IO_L70N_4
IO_L70P_4
IO_L71N_4
IO_L71P_4
IO_L72N_4
IO_L72P_4
IO_L73N_4
IO_L73P_4
IO_L74N_4
IO_L74P_4
IO_L75N_4
IO_L75P_4/VREF_4
IO_L76N_4
IO_L76P_4
IO_L77N_4
IO_L77P_4
Pin Number
AL6
No Connect in XC2V2000
NC
NC
NC
NC
AL7
AJ9
AJ10
AE11
AE12
AG10
AG11
AL8
AL9
AF12
AF13
AK9
AK10
AH11
AH12
AC12
AC13
AG12
AG13
AL10
AL11
AD13
AD15
AJ11
AJ12
AK11
AK12
AE14
AE15
AF14
AF15
AL12
AL13
AB14
AC14
AH13
AH14
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000
Bank
Pin Description
IO_L78N_4
Pin Number
AJ13
No Connect in XC2V2000
4
4
4
4
4
4
4
4
4
4
4
4
4
4
IO_L78P_4
AK13
AC15
AC16
AG14
AG15
AK14
AK15
AF16
AG16
AL14
IO_L91N_4/VREF_4
IO_L91P_4
IO_L92N_4
IO_L92P_4
IO_L93N_4
IO_L93P_4
IO_L94N_4/VREF_4
IO_L94P_4
IO_L95N_4/GCLK3S
IO_L95P_4/GCLK2P
IO_L96N_4/GCLK1S
IO_L96P_4/GCLK0P
AL15
AH15
AJ15
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
IO_L96N_5/GCLK7S
IO_L96P_5/GCLK6P
IO_L95N_5/GCLK5S
IO_L95P_5/GCLK4P
IO_L94N_5
AJ16
AH17
AD16
AD17
AL17
AL18
AG17
AF17
AE17
AE18
AK17
AJ17
AK18
AK19
AC17
AB18
AH18
AH19
AL19
AL20
AC18
AC19
AJ19
IO_L94P_5/VREF_5
IO_L93N_5
IO_L93P_5
IO_L92N_5
IO_L92P_5
IO_L91N_5
IO_L91P_5/VREF_5
IO_L78N_5
IO_L78P_5
IO_L77N_5
IO_L77P_5
IO_L76N_5
IO_L76P_5
IO_L75N_5/VREF_5
IO_L75P_5
IO_L74N_5
IO_L74P_5
IO_L73N_5
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000
Bank
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
Pin Description
IO_L73P_5
IO_L72N_5
IO_L72P_5
IO_L71N_5
IO_L71P_5
IO_L70N_5
IO_L70P_5
IO_L69N_5/VREF_5
IO_L69P_5
IO_L68N_5
IO_L68P_5
IO_L67N_5
IO_L67P_5
IO_L54N_5
IO_L54P_5
IO_L53N_5
IO_L53P_5
IO_L52N_5
IO_L52P_5
IO_L51N_5/VREF_5
IO_L51P_5
IO_L50N_5
IO_L50P_5
IO_L49N_5
IO_L49P_5
IO_L30N_5
IO_L30P_5
IO_L29N_5
IO_L29P_5
IO_L28N_5
IO_L28P_5
IO_L27N_5/VREF_5
IO_L27P_5
IO_L26N_5
IO_L26P_5
IO_L25N_5
IO_L25P_5
IO_L24N_5
Pin Number
AJ20
AG18
AG19
AF18
AF19
AK20
AK21
AH20
AH21
AD19
AD20
AL21
AL22
AG20
AG21
AB19
AB20
AJ21
AJ22
AF20
AF21
AE20
AE21
AK22
AK23
AJ23
AJ24
AC20
AC21
AL23
AL24
AL25
AL26
AD21
AD22
AH23
AH24
AG22
No Connect in XC2V2000
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000
Bank
5
Pin Description
IO_L24P_5
Pin Number
AG23
AE22
AE23
AK25
AK26
AH25
AG25
AB21
AC22
AL27
No Connect in XC2V2000
5
IO_L23N_5
5
IO_L23P_5
5
IO_L22N_5
5
IO_L22P_5
5
IO_L21N_5/VREF_5
IO_L21P_5
5
5
IO_L20N_5
5
IO_L20P_5
5
IO_L19N_5
5
IO_L19P_5
AL28
5
IO_L06N_5
AK27
AJ27
5
IO_L06P_5
5
IO_L05N_5/VRP_5
IO_L05P_5/VRN_5
IO_L04N_5
AD23
AE24
AJ26
5
5
5
IO_L04P_5/VREF_5
IO_L03N_5/D4/ALT_VRP_5
IO_L03P_5/D5/ALT_VRN_5
IO_L02N_5/D6
IO_L02P_5/D7
IO_L01N_5/RDWR_B
IO_L01P_5/CS_B
AH26
AF23
AF24
AG24
AF25
AK28
AK29
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
IO_L01P_6
IO_L01N_6
AF27
AF28
AE26
AE27
AH29
AH30
AB22
AB23
AG28
AG29
AH31
AG31
AA22
Y22
IO_L02P_6/VRN_6
IO_L02N_6/VRP_6
IO_L03P_6
IO_L03N_6/VREF_6
IO_L04P_6
IO_L04N_6
IO_L05P_6
IO_L05N_6
IO_L06P_6
IO_L06N_6
IO_L19P_6
IO_L19N_6
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R
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000
Bank
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
Pin Description
IO_L20P_6
Pin Number
AD25
AC24
AG30
AF30
AD26
AC26
AF29
AD29
AE28
AD28
AB24
AA24
AC25
AB25
AF31
AE31
AA23
Y23
No Connect in XC2V2000
IO_L20N_6
IO_L21P_6
IO_L21N_6/VREF_6
IO_L22P_6
IO_L22N_6
IO_L23P_6
IO_L23N_6
IO_L24P_6
IO_L24N_6
IO_L25P_6
NC
NC
NC
NC
IO_L25N_6
IO_L27P_6
IO_L27N_6/VREF_6
IO_L43P_6
IO_L43N_6
IO_L44P_6
IO_L44N_6
IO_L45P_6
AE30
AC30
AC28
AA28
AD27
AC27
AA25
Y25
IO_L45N_6/VREF_6
IO_L46P_6
IO_L46N_6
IO_L47P_6
IO_L47N_6
IO_L48P_6
IO_L48N_6
IO_L49P_6
AC29
AB29
AB27
AA27
AA26
Y26
IO_L49N_6
IO_L50P_6
IO_L50N_6
IO_L51P_6
IO_L51N_6/VREF_6
IO_L52P_6
AD31
AC31
W22
IO_L52N_6
IO_L53P_6
IO_L53N_6
IO_L54P_6
V22
Y27
IO_L54N_6
W27
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R
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000
Bank
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
Pin Description
IO_L67P_6
IO_L67N_6
IO_L68P_6
IO_L68N_6
IO_L69P_6
IO_L69N_6/VREF_6
IO_L70P_6
IO_L70N_6
IO_L71P_6
IO_L71N_6
IO_L72P_6
IO_L72N_6
IO_L73P_6
IO_L73N_6
IO_L74P_6
IO_L74N_6
IO_L75P_6
IO_L75N_6/VREF_6
IO_L76P_6
IO_L76N_6
IO_L77P_6
IO_L77N_6
IO_L78P_6
IO_L78N_6
IO_L91P_6
IO_L91N_6
IO_L92P_6
IO_L92N_6
IO_L93P_6
IO_L93N_6/VREF_6
IO_L94P_6
IO_L94N_6
IO_L95P_6
IO_L95N_6
IO_L96P_6
IO_L96N_6
Pin Number
AB30
AA30
W26
V26
No Connect in XC2V2000
AB31
AA31
AA29
Y29
Y24
W24
V25
U25
Y28
W28
W23
V23
Y30
W30
Y31
W31
V27
U27
W29
U29
U23
T23
U26
T26
V28
U28
U24
T24
V30
U30
V31
U31
7
IO_L96P_7
T27
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R
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000
Bank
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
Pin Description
IO_L96N_7
IO_L95P_7
IO_L95N_7
IO_L94P_7
IO_L94N_7
IO_L93P_7/VREF_7
IO_L93N_7
IO_L92P_7
IO_L92N_7
IO_L91P_7
IO_L91N_7
IO_L78P_7
IO_L78N_7
IO_L77P_7
IO_L77N_7
IO_L76P_7
IO_L76N_7
IO_L75P_7/VREF_7
IO_L75N_7
IO_L74P_7
IO_L74N_7
IO_L73P_7
IO_L73N_7
IO_L72P_7
IO_L72N_7
IO_L71P_7
IO_L71N_7
IO_L70P_7
IO_L70N_7
IO_L69P_7/VREF_7
IO_L69N_7
IO_L68P_7
IO_L68N_7
IO_L67P_7
IO_L67N_7
IO_L54P_7
IO_L54N_7
IO_L53P_7
Pin Number
R27
R24
N24
T29
No Connect in XC2V2000
R29
R31
P31
R26
P26
R30
P30
R25
P25
R28
P28
N31
M31
R23
P23
N30
M30
P27
N27
P22
N22
N29
M29
N28
M28
N26
M26
L31
K31
M27
L27
N23
M23
L30
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000
Bank
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
Pin Description
IO_L53N_7
IO_L52P_7
Pin Number
K30
L28
No Connect in XC2V2000
IO_L52N_7
IO_L51P_7/VREF_7
IO_L51N_7
IO_L50P_7
J28
M24
L24
L29
IO_L50N_7
IO_L49P_7
K29
M25
L25
IO_L49N_7
IO_L48P_7
L26
IO_L48N_7
IO_L47P_7
J26
J31
IO_L47N_7
IO_L46P_7
H31
J29
IO_L46N_7
IO_L45P_7/VREF_7
IO_L45N_7
IO_L44P_7
H29
M22
L22
J30
IO_L44N_7
IO_L43P_7
G30
K27
J27
IO_L43N_7
IO_L27P_7/VREF_7
IO_L27N_7
IO_L25P_7
L23
NC
NC
NC
NC
K23
G31
F31
F30
E30
K25
J25
IO_L25N_7
IO_L24P_7
IO_L24N_7
IO_L23P_7
IO_L23N_7
IO_L22P_7
H28
G28
H27
G27
K24
J24
IO_L22N_7
IO_L21P_7/VREF_7
IO_L21N_7
IO_L20P_7
IO_L20N_7
IO_L19P_7
E31
D31
F28
IO_L19N_7
IO_L06P_7
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000
Bank
Pin Description
IO_L06N_7
Pin Number
E28
No Connect in XC2V2000
7
7
7
7
7
7
7
7
7
7
7
IO_L05P_7
K22
IO_L05N_7
K21
IO_L04P_7
F29
IO_L04N_7
E29
IO_L03P_7/VREF_7
IO_L03N_7
H26
H25
IO_L02P_7/VRN_7
IO_L02N_7/VRP_7
IO_L01P_7
G26
F27
D30
IO_L01N_7
D29
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_2
VCCO_2
VCCO_2
VCCO_2
C18
C25
F22
H18
L17
L18
L19
L20
M17
M18
M19
C7
C14
F10
H14
L12
L13
L14
L15
M13
M14
M15
G3
K6
M11
N11
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000
Bank
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
Pin Description
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
Pin Number
N12
No Connect in XC2V2000
P3
P8
P11
P12
R11
R12
U11
U12
V3
V8
V11
V12
W11
W12
Y11
AB6
AE3
Y13
Y14
Y15
AA12
AA13
AA14
AA15
AD14
AF10
AJ7
AJ14
Y17
Y18
Y19
AA17
AA18
AA19
AA20
AD18
AF22
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000
Bank
5
Pin Description
VCCO_5
VCCO_5
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
Pin Number
AJ18
AJ25
U20
No Connect in XC2V2000
5
6
6
U21
6
V20
6
V21
6
V24
6
V29
6
W20
W21
Y21
6
6
6
AB26
AE29
G29
6
7
7
K26
7
M21
N20
7
7
N21
7
P20
7
P21
7
P24
7
P29
7
R20
7
R21
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
CCLK
PROG_B
DONE
M0
AJ4
D27
AG6
AH27
AJ28
AG26
E26
K11
C28
C4
M1
M2
HSWAP_EN
TCK
TDI
TDO
TMS
J10
PWRDWN_B
DXN
AH5
F25
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000
Bank
NA
Pin Description
DXP
Pin Number
No Connect in XC2V2000
B28
D5
NA
VBATT
NA
RSVD
B4
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
B16
C2
C30
T2
T30
AJ2
AJ30
AK16
K15
K17
L11
L16
L21
M12
M16
M20
N13
N14
N15
N16
N17
N18
N19
P13
P19
R10
R13
R19
R22
T11
T12
T13
T19
T20
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
GND
Pin Number
T21
No Connect in XC2V2000
U10
U13
U19
U22
V13
V19
W13
W14
W15
W16
W17
W18
W19
Y12
Y16
Y20
AA11
AA16
AA21
AB15
AB17
A2
GND
A3
GND
A16
A29
A30
B1
GND
GND
GND
GND
B2
GND
B8
GND
B24
B30
B31
C1
GND
GND
GND
GND
C3
GND
C29
C31
D4
GND
GND
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin Number
D10
D16
D22
D28
E5
No Connect in XC2V2000
E27
F6
F26
G7
G13
G16
G19
G25
H2
H8
H24
H30
J9
J23
K4
K16
K28
N7
N25
P14
P15
P16
P17
P18
R14
R15
R16
R17
R18
T1
T4
T7
T10
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R
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin Number
T14
No Connect in XC2V2000
T15
T16
T17
T18
T22
T25
T28
T31
U14
U15
U16
U17
U18
V14
V15
V16
V17
V18
W7
W25
AB4
AB16
AB28
AC9
AC23
AD2
AD8
AD24
AD30
AE7
AE13
AE16
AE19
AE25
AF6
AF26
AG5
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, and XC2V6000
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
Pin Number
AG27
AH4
No Connect in XC2V2000
GND
GND
AH10
AH16
AH22
AH28
AJ1
GND
GND
GND
GND
GND
AJ3
GND
AJ29
AJ31
AK1
GND
GND
GND
AK2
GND
AK8
GND
AK24
AK30
AK31
AL2
GND
GND
GND
GND
AL3
GND
AL16
AL29
AL30
GND
GND
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
BF957 Flip-Chip BGA Package Specifications (1.27mm pitch)
Figure 10: BF957 Flip-Chip BGA Package Specifications
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Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
Revision History
This section records the change history for this module of the data sheet.
Date
Version
1.0
Revision
11/07/00
11/22/00
Early access draft.
1.1
Initial Xilinx release. Made the following corrections:
CS144 package - Table 5 on page 5:
•
•
Added missing pin D10 in Bank 1.
Changed dedicated pins A2 and B2 to RSVD (from DXN and DXP).
FG256 package - Table 6 on page 10:
Changed dedicated pins A3 and A4 to RSVD (from DXN and DXP).
FG896 package - Table 11 on page 94:
Corrected pin AG1 in Bank 4 to be AG12.
FF1152 package - Table 12 on page 120:
Corrected pin Y3 in Bank 6 to be Y32.
•
•
•
12/19/00
01/25/01
1.2
1.3
Reverse designations were fixed for pins in every package.
The data sheet was divided into four modules (per the current style standard). DXN
and DXP pin information was added for the CS144 package (Table 5) and the FG256
package (Table 6).
02/07/01
04/02/01
1.4
1.5
DXN and DXP pin information was changed back to RSVD for the CS144 package
(Table 5) and the FG256 package (Table 6).
•
ALT_VRN and ALT_VRP pin information was added for each package.
•
Table 8 on page 34 – added No Connect designations for the XC2V1500 device
in the FG676 package.
•
•
Reverted to traditional double-column format.
Updated list of devices supported in the FF1152, FF1517, and BF957 packages.
11/07/01
09/26/02
1.6
1.7
•
•
•
Updated Table 3 to reflect devices supported in the BG728 and BF957 packages.
Added mention of LVPECL to pin definition in Table 4.
Corrected Table 10 heading to reflect supported devices in the BG728 package.
10/07/02
1.8
Virtex-II Data Sheet
The Virtex-II Data Sheet contains the following modules:
•
•
DS031-3, Virtex-II 1.5V FPGAs: DC and Switching
Characteristics (Module 3)
•
DS031-1, Virtex-II 1.5V FPGAs: Introduction and
DS031-4, Virtex-II 1.5V FPGAs: Pinout Tables
(Module 4)
Ordering Information (Module 1)
•
DS031-2, Virtex-II 1.5V FPGAs: Functional Description
(Module 2)
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