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XC3030-100PQ100C [XILINX]

Field Programmable Gate Array, 100 CLBs, 1500 Gates, 100MHz, 100-Cell, CMOS, PQFP100, PLASTIC, QFP-100;
XC3030-100PQ100C
型号： XC3030-100PQ100C
厂家： XILINX, INC    XILINX, INC
描述：

Field Programmable Gate Array, 100 CLBs, 1500 Gates, 100MHz, 100-Cell, CMOS, PQFP100, PLASTIC, QFP-100

时钟 栅 可编程逻辑
文件： 总8页 (文件大小：53K)
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IMPORTANT NOTICE  
All new designs should use XC3000A.  
Information on XC3000 is presented here  
XC3000  
Logic Cell Array Family  
as  
a reference for existing designs.  
XC3000 bitstreams are upward compatible  
to XC3000A without modification.  
Product Specification  
Features  
Description  
• Industry-leading FPGA family with five device types  
– Logic densities from 1,000 to 6,000 gates  
– Up to 144 user-definable I/Os  
XC3000 is the original family of devices in the XC3000  
class of Field Programmable Gate Array (FPGA) architec-  
tures. The XC3000 family has a proven track record in  
addressing a wide range of design applications, including  
general logic replacement and sub-systems integration.  
For a thorough description of the XC3000 architecture see  
the preceding pages of this data book.  
• Guaranteed 70- to 125-MHz toggle rates, 9 to 5.5 ns  
logic delays  
• Advanced CMOS static memory technology  
– Low quiescent and active power consumption  
The XC3000 Family covers a range of nominal device  
densities from 2,000 to 9,000 gates, practically achievable  
densities from 1,000 to 6,000 gates. Device speeds,  
described in terms of maximum guaranteed toggle fre-  
quencies, range from 70 to 125 MHz. The performance of  
a completed design depends upon placement and routing  
implementation, so, like with any gate array, the final  
verification of device utilization and performance can only  
be known after the design has been placed and routed.  
• XC3000-specific features  
– Ultra-low current option in Power-Down mode  
– 4-mA output sink and source current  
– Broad range of package options includes plastic and  
ceramic quad flat packs, plastic leaded chip carriers  
and pin grid arrays  
– 100% bitstream compatible with the XC3100 family  
– Commercial, industrial, military, “high rel”, and MIL-  
STD-883 Class B grade devices  
– Easy migration to XC3300 series of HardWire mask-  
programmed devices for high-volume production  
User I/Os  
Max  
Horizontal  
Longlines  
Configuration  
Data Bits  
Device  
CLBs  
Array  
Flip-Flops  
XC3020  
64  
8 x 8  
64  
256  
16  
14,779  
XC3030  
XC3042  
XC3064  
100  
144  
224  
10 x 10  
12 x 12  
16 x 14  
80  
96  
120  
360  
480  
688  
20  
24  
32  
22,176  
30,784  
46,064  
XC3090  
320  
16 x 20  
144  
928  
40  
64,160  
2-153  
XC3000 Logic Cell Array Family  
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently  
released device performance parameters, please request a copy of the current test-specification revision.  
Absolute Maximum Ratings  
Symbol Description  
Units  
V
VCC  
VIN  
Supply voltage relative to GND  
–0.5 to +7.0  
–0.5 to VCC +0.5  
–0.5 to VCC +0.5  
–65 to +150  
+260  
Input voltage with respect to GND  
Voltage applied to 3-state output  
Storage temperature (ambient)  
V
VTS  
V
TSTG  
TSOL  
°C  
°C  
°C  
°C  
Maximum soldering temperature (10 s @ 1/16 in.)  
Junction temperature plastic  
+125  
TJ  
Junction temperature ceramic  
+150  
Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.  
These are stress ratings only, and functional operation of the device at these or any other conditions beyond  
those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum  
Ratings conditions for extended periods of time may affect device reliability.  
Operating Conditions  
Symbol  
Description  
Min  
4.75  
4.5  
2.0  
0
Max Units  
VCC  
Supply voltage relative to GND Commercial 0°C to +85°C junction  
Supply voltage relative to GND Industrial -40°C to +100°C junction  
High-level input voltage — TTL configuration  
Low-level input voltage — TTL configuration  
High-level input voltage — CMOS configuration  
Low-level input voltage — CMOS configuration  
Input signal transition time  
5.25  
5.5  
V
V
V
V
VIHT  
VILT  
VIHC  
VILC  
TIN  
VCC  
0.8  
70%  
0
100% VCC  
20%  
VCC  
250  
ns  
At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per °C.  
2-154  
DC Characteristics Over Operating Conditions  
Symbol Description  
Min  
Max Units  
VOH  
High-level output voltage (@ IOH = –4.0 mA, VCC min)  
3.86  
V
Commercial  
Industrial  
VOL  
Low-level output voltage (@ IOL = 4.0 mA, VCC min)  
High-level output voltage (@ IOH = –4.0 mA, VCC min)  
Low-level output voltage (@ IOL = 4.0 mA, VCC min)  
0.40  
0.40  
V
V
V
V
VOH  
3.76  
2.30  
VOL  
VCCPD  
ICCPD  
Power-down supply voltage (PWRDWN must be Low)  
1
Power-down supply current (VCC(MAX) @ TMAX  
)
XC3020  
XC3030  
XC3042  
XC3064  
XC3090  
50  
80  
µA  
µA  
µA  
µA  
µA  
120  
170  
250  
2
ICCO  
Quiescent LCA supply current in addition to ICCPD  
Chip thresholds programmed as CMOS levels  
Chip thresholds programmed as TTL levels  
Input Leakage Current  
500  
µA  
10 mA  
IIL  
–10  
+10  
µA  
CIN  
Input capacitance, all packages except PGA175  
(sample tested)  
All Pins except XTL1 and XTL2  
XTL1 and XTL2  
10  
15  
pF  
pF  
Input capacitance, PGA 175  
(sample tested)  
All Pins except XTL1 and XTL2  
XTL1 and XTL2  
15  
20  
pF  
pF  
IRIN  
IRLL  
Pad pull-up (when selected) @ VIN = 0 V (sample tested)  
Horizontal Longline pull-up (when selected) @ logic Low  
0.02  
0.17 mA  
3.4 mA  
Note: 1. Devices with much lower ICCPD tested and guaranteed at VCC = 3.2 V, T = 25°C can be ordered with a  
Special Product Code.  
XC3020 SPC0107: ICCPD = 1 µA  
XC3030 SPC0107: ICCPD = 2 µA  
XC3042 SPC0107: ICCPD = 3 µA  
XC3064 SPC0107: ICCPD= 4 µA  
XC3090 SPC0107: ICCPD= 5 µA  
2. With no output current loads, no active input or Longline pull-up resistors, all package pins at VCC or GND,  
and the LCA configured with a MakeBits tie option.  
2-155  
XC3000 Logic Cell Array Family  
CLB Switching Characteristic Guidelines  
CLB Output (X, Y)  
(Combinatorial)  
1
T
ILO  
CLB Input  
(A,B,C,D,E)  
2
T
3 T  
CKI  
ICK  
CLB Clock  
12 T  
4
11 T  
CH  
CL  
T
5 T  
CKDI  
DICK  
CLB Input  
(Direct In)  
6
T
7 T  
CKEC  
ECCK  
CLB Input  
(Enable Clock)  
8
T
CKO  
CLB Output  
(Flip-Flop)  
CLB Input  
(Reset Direct)  
13 T  
RPW  
9
T
RIO  
CLB Output  
(Flip-Flop)  
X5388  
Buffer (Internal) Switching Characteristic Guidelines  
Speed Grade  
Symbol  
-70  
-100  
-125  
Max  
Units  
Description  
Max  
Max  
Global and Alternate Clock Distribution*  
Either: Normal IOB input pad through clock buffer  
to any CLB or IOB clock input  
TPID  
8.0  
6.5  
7.5  
6.0  
7.0  
5.7  
ns  
ns  
Or:  
Fast (CMOS only) input pad through clock  
buffer to any CLB or IOB clock input  
TPIDC  
TBUF driving a Horizontal Longline (L.L.)*  
I to L.L. while T is Low (buffer active)  
T↓ to L.L. active and valid with single pull-up resistor  
T↓ to L.L. active and valid with pair of pull-up resistors  
T↑ to L.L. High with single pull-up resistor  
T↑ to L.L. High with pair of pull-up resistors  
TIO  
5.0  
11.0  
12.0  
24.0  
17.0  
4.7  
10.0  
11.0  
22.0  
15.0  
4.5  
9.0  
10.0  
17.0  
12.0  
ns  
ns  
ns  
ns  
ns  
TON  
TON  
TPUS  
TPUF  
BIDI  
Bidirectional buffer delay  
TBIDI  
2.0  
1.8  
1.7  
ns  
* Timing is based on the XC3042, for other devices see XACT timing calculator.  
2-156  
CLB Switching Characteristic Guidelines (continued)  
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%  
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing  
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more  
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.  
Speed Grade  
Symbol  
-70  
-100  
-125  
Description  
Min Max  
Min Max Min Max Units  
Combinatorial Delay  
Logic Variables A, B, C, D, E, to outputs X or Y  
1 TILO  
9.0  
7.0  
5.5  
ns  
Sequential delay  
Clock k to outputs X or Y  
Clock k to outputs X or Y when Q is returned  
through function generators F or G to drive X or Y  
8 TCKO  
6.0  
5.0  
4.5  
8.0  
ns  
ns  
TQLO  
13.0  
10.0  
Set-up time before clock K  
Logic Variables  
Data In  
Enable Clock  
A, B, C, D, E  
DI  
EC  
2 TICK  
4 TDICK  
6 TECCK 7.0  
1.0  
8.0  
5.0  
7.0  
4.0  
5.0  
1.0  
5.5  
3.0  
4.5  
1.0  
ns  
ns  
ns  
ns  
Reset Direct inactive RD  
Hold Time after clock K  
Logic Variables  
Data In  
Enable Clock  
A, B, C, D, E  
DI  
EC  
3 TCKI  
5 TCKDI  
7 TCKEC  
0
4.0  
0
0
2.0  
0
0
1.5  
0
ns  
ns  
ns  
Clock  
Clock High time  
Clock Low time  
11 TCH  
12 TCL  
5.0  
5.0  
4.0  
4.0  
3.0  
3.0  
ns  
ns  
Max flip-flop toggle rate  
FCLK 70  
100  
125  
MHz  
Reset Direct (RD)  
RD width  
13 TRPW  
9 TRIO  
8.0  
7.0  
6.0  
ns  
ns  
delay from rd to outputs X or Y  
8.0  
7.0  
6.0  
Global Reset (RESET Pad)*  
RESET width (Low)  
TMRW 25.0  
TMRQ  
21.0  
20.0  
ns  
ns  
delay from RESET pad to outputs X or Y  
23.0  
19.0  
17.0  
*Timing is based on the XC3042, for other devices see XACT timing calculator.  
Note: The CLB K to Q output delay (TCKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than  
the Data In hold time requirement (TCKDI, #5) of any CLB on the same die.  
2-157  
XC3000 Logic Cell Array Family  
IOB Switching Characteristic Guidelines  
I/O Block (I)  
T
3
PID  
I/O Pad Input  
T
1
PICK  
I/O Clock (IK/OK)  
I/O Block (RI)  
T
T
IOH  
11  
12  
IOL  
T
T
RRI  
4
13  
IKRI  
RESET  
T
T
OKO  
6
5
OOK  
T
15  
RPO  
I/O Block (O)  
T
10  
OP  
I/O Pad Output  
(Direct)  
T
7
OKPO  
I/O Pad Output  
(Registered)  
I/O Pad TS  
T
9
T
TSHZ  
8
TSON  
I/O Pad Output  
X5425  
Vcc  
PROGRAM-CONTROLLED MEMORY CELLS  
OUT  
INVERT  
OUTPUT  
SELECT  
SLEW  
RATE  
PASSIVE  
PULL UP  
3-STATE  
INVERT  
T
3- STATE  
(OUTPUT ENABLE)  
O
D
Q
OUTPUT  
BUFFER  
OUT  
FLIP  
FLOP  
I/O PAD  
R
I
DIRECT IN  
Q
REGISTERED IN  
Q
D
FLIP  
FLOP  
or  
TTL or  
CMOS  
INPUT  
LATCH  
THRESHOLD  
R
(GLOBAL RESET)  
CK1  
OK  
IK  
CK2  
PROGRAM  
CONTROLLED  
MULTIPLEXER  
=
PROGRAMMABLE INTERCONNECTION POINT or PIP  
X3029  
2-158  
IOB Switching Characteristic Guidelines (continued)  
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%  
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing  
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more  
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.  
Speed Grade  
Symbol  
-70  
-100  
-125  
Units  
Description  
Min Max Min Max Min Max  
Propagation Delays (Input)  
Pad to Direct In (I)  
Pad to Registered In (Q) with latch transparent  
Clock (IK) to Registered In (Q)  
3
4
TPID  
TPTG  
TIKRI  
6
21  
5.5  
4
17  
4
3
16  
3
ns  
ns  
ns  
Set-up Time (Input)  
Pad to Clock (IK) set-up time  
1
TPICK  
20  
17  
16  
ns  
Propagation Delays (Output)  
Clock (OK) to Pad  
same  
Output (O) to Pad  
same  
3-state to Pad begin hi-Z (fast)  
same  
(fast)  
(slew rate limited)  
(fast)  
7
7
TOKPO  
TOKPO  
13  
33  
9
29  
8
28  
14  
34  
10  
27  
6
23  
8
25  
12  
29  
9
24  
5
20  
7
24  
11  
27  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
10 TOPF  
10 TOPS  
9
9
8
8
(slew-rate limited)  
TTSHZ  
TTSHZ  
TTSON  
TTSON  
(slew-rate limited)  
3-state to Pad active and valid (fast)  
same  
(slew -rate limited)  
Set-up and Hold Times (Output)  
Output (O) to clock (OK) set-up time  
Output (O) to clock (OK) hold time  
5
6
TOOK  
TOKO  
10  
0
9
0
8
0
ns  
ns  
Clock  
Clock High time  
Clock Low time  
Max. flip-flop toggle rate  
11 TIOH  
12 TIOL  
FCLK  
5
5
70  
4
4
100  
3
3
125  
ns  
ns  
MHz  
Global Reset Delays (based on XC3042)  
RESET Pad to Registered In (Q)  
RESET Pad to output pad (fast)  
13 TRRI  
15 TRPO  
15 TRPO  
25  
35  
53  
24  
33  
45  
23  
29  
42  
ns  
ns  
ns  
(slew-rate limited)  
Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). For larger capacitive loads,  
see XAPP 024. Typical slew rate limited output rise/fall times are approximately four times longer.  
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the  
internal pull-up resistor or alternatively configured as a driven output or driven from an external source.  
3. Input pad setup time and hold times are specified with respect to the internal clock (IK). To calculate system setup time,  
subtract clock delay (clock pad to IK) from the specified input pad setup time value, but the subtracted value cannot be  
less than zero (i.e., negative hold time). Negative hold time means that the delay in the input data is adequate for the  
external system hold time to be zero, provided the input clock uses the Global signal distribution from pad to IK .  
2-159  
Ordering Information  
Example:  
XC3030-70PC44C  
Device Type  
Temperature Range  
Toggle Rate  
Number of Pins  
Package Type  
Component Availability  
PINS  
44  
64  
68  
84  
100  
132  
144  
160  
164  
175  
176  
208  
223  
TOP-  
TOP-  
TYPE  
PLAST. PLAST. PLAST. PLAST. CERAM. PLAST. PLAST. PLAST. BRAZED PLAST. CERAM. PLAST. PLAST. BRAZED PLAST. CERAM. PLAST. PLAST. CERAM.  
PLCC VQFP PLCC PLCC PGA PQFP TQFP VQFP CQFP PGA PGA TQFP PQFP CQFP PGA PGA TQFP PQFP PGA  
CODE  
PC44 VQ64 PC68 PC84 PG84 PQ100 TQ100 VQ100 CB100 PP132 PG132 TQ144 PQ160 CB164 PP175 PG175 TQ176 PQ208 PG223  
-50  
-70  
M B  
C I M B  
C I M B  
C
M B  
C I  
C I  
C
C I  
C I  
C
C I  
C I  
C
C M B  
C M B  
XC3020  
-100  
-125  
-50  
M
-70  
C I  
C I  
C
C I  
C I  
C
C I  
C I  
C
C I M  
C I M  
C
C I  
C I  
C
C
C
C
XC3030  
XC3042  
XC3064  
-100  
-125  
-50  
M B  
M B  
M B  
C I M B  
C I M B  
C
-70  
C I  
C I  
C
C I M B  
C I M B  
C
C I  
C I  
C
C
C
C
C M B  
C M B  
C
C
C
-100  
-125  
-50  
M
-70  
C I  
C I  
C
C I  
C I  
C
C I M  
C I M  
C
C I  
C I  
C
-100  
-125  
-50  
M B  
M B  
C I M B  
C I M B  
C
-70  
C I  
C I  
C
C I  
C I  
C
C M B  
C M B  
C I  
C I  
C
C I  
C I  
C
XC3090  
-100  
-125  
C = Commercial = 0° to +70° C  
I = Industrial = -40° to +85° C  
M = Mil Temp = -55° to +125° C  
B = MIL-STD-883C Class B  
Parentheses indicate future product plans  

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