XC3S250E-4FGG484C [XILINX]
Spartan-3E FPGA Family; 的Spartan- 3E FPGA系列
| 型号： | XC3S250E-4FGG484C |
| 厂家： | 
XILINX, INC |
| 描述： | Spartan-3E FPGA Family |
| 文件： | 总193页 (文件大小：1733K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Spartan-3E FPGA Family:
Complete Data Sheet
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DS312 March 21, 2005
Module 1:
Introduction and Ordering Information
Module 3:
DC and Switching Characteristics
DS312-1 (v1.1) March 21, 2005
6 pages
DS312-3 (v1.0) March 1, 2005
18 pages
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•
•
•
•
Introduction
•
DC Electrical Characteristics
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Absolute Maximum Ratings
Supply Voltage Specifications
Recommended Operating Conditions
DC Characteristics
Features
Architectural Overview
Package Marking
Ordering Information
•
Switching Characteristics
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-
DCM Timing
Configuration and JTAG Timing
Module 2:
Functional Description
DS312-2 (v1.1) March 21, 2005
96 pages
Module 4:
Pinout Descriptions
•
Input/Output Blocks (IOBs)
DS312-4 (v1.1) March 21, 2005
72 pages
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Overview
SelectIO™ Signal Standards
•
•
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Pin Descriptions
Package Overview
Pinout Tables
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•
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Configurable Logic Block (CLB)
Block RAM
Dedicated Multipliers
Digital Clock Manager (DCM)
Clock Network
Footprint Diagrams
Configuration
Powering Spartan-3E FPGAs
IMPORTANT NOTE: The Spartan™-3E FPGA data sheet is created and published in separate modules. This complete
version is provided for easy downloading and searching of the complete document. Page, figure, and table numbers begin
at 1 for each module, and each module has its own Revision History at the end. Use the PDF "Bookmarks" for easy
navigation in this volume.
© 2005 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc.
All other trademarks are the property of their respective owners.
DS312 March 21, 2005
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06
Spartan-3E FPGA Family:
Introduction and Ordering
Information
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DS312-1 (v1.1) March 21, 2005
Advance Product Specification
Introduction
The Spartan™-3E family of Field-Programmable Gate
Arrays (FPGAs) is specifically designed to meet the needs
of high volume, cost-sensitive consumer electronic applica-
tions. The five-member family offers densities ranging from
100,000 to 1.6 million system gates, as shown in Table 1.
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-
-
True LVDS, RSDS, mini-LVDS differential I/O
3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
Enhanced Double Data Rate (DDR) support
•
Abundant, flexible logic resources
-
Densities up to 33,192 logic cells, including
optional shift register or distributed RAM support
Efficient wide multiplexers, wide logic
Fast look-ahead carry logic
Enhanced 18 x 18 multipliers with optional pipeline
IEEE 1149.1/1532 JTAG programming/debug port
The Spartan-3E family builds on the success of the earlier
Spartan-3 family by increasing the amount of logic per I/O,
significantly reducing the cost per logic cell. New features
improve system performance and reduce the cost of config-
uration. These Spartan-3E enhancements, combined with
advanced 90 nm process technology, deliver more function-
ality and bandwidth per dollar than was previously possible,
setting new standards in the programmable logic industry.
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•
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Hierarchical SelectRAM™ memory architecture
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Up to 648 Kbits of fast block RAM
Up to 231 Kbits of efficient distributed RAM
Because of their exceptionally low cost, Spartan-3E FPGAs
are ideally suited to a wide range of consumer electronics
applications, including broadband access, home network-
ing, display/projection, and digital television equipment.
Up to eight Digital Clock Managers (DCMs)
-
-
-
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Clock skew elimination (delay locked loop)
Frequency synthesis, multiplication, division
High-resolution phase shifting
The Spartan-3E family is a superior alternative to mask pro-
grammed ASICs. FPGAs avoid the high initial cost, the
lengthy development cycles, and the inherent inflexibility of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary, an impossibility with ASICs.
Wide frequency range (5 MHz to over 300 MHz)
•
•
Eight global clocks and eight clocks for each half of
device, plus abundant low-skew routing
Configuration interface to industry-standard PROMs
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-
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Low-cost, space-saving SPI serial Flash PROM
x8 or x8/x16 parallel NOR Flash PROM
Low-cost Xilinx Platform Flash with JTAG
Features
•
Complete Xilinx ISE™, WebPACK™ development
system support
•
Very low cost, high-performance logic solution for
high-volume, consumer-oriented applications
•
•
•
MicroBlaze™, PicoBlaze™ embedded processor cores
Fully compliant 32-/64-bit 33/66 MHz PCI support
Low-cost QFP and BGA packaging options
•
•
Proven advanced 90-nanometer process technology
Multi-voltage, multi-standard SelectIO™ interface pins
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Up to 376 I/O pins or 156 differential signal pairs
LVCMOS, LVTTL, HSTL, and SSTL single-ended
signal standards
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Common footprints support easy density migration
Pb-free packaging options
Table 1: Summary of Spartan-3E FPGA Attributes
CLB Array
(One CLB = Four Slices)
Equivalent
Logic
Cells
Block
RAM
bits
Maximum
Maximum Differential
System
Gates
Total
Total
Distributed
RAM bits
Dedicated
Multipliers DCMs User I/O
(1)
(1)
Device
XC3S100E
XC3S250E
XC3S500E
Rows Columns CLBs
Slices
I/O Pairs
100K
250K
500K
2,160
5,508
22
34
46
60
76
16
26
34
46
58
240
612
960
2,448
4,656
8,672
14,752
15K
38K
72K
4
2
4
4
8
8
108
172
232
304
376
40
216K
360K
504K
648K
12
20
28
36
68
10,476
19,512
33,192
1,164
2,168
3,688
73K
92
XC3S1200E 1200K
XC3S1600E 1600K
136K
231K
124
156
Notes:
1. By convention, one Kb is equivalent to 1,024 bits.
© 2005 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc.
All other trademarks are the property of their respective owners.
DS312-1 (v1.1) March 21, 2005
Advance Product Specification
www.xilinx.com
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Introduction and Ordering Information
Architectural Overview
The Spartan-3E family architecture consists of five funda-
mental programmable functional elements:
•
Digital Clock Manager (DCM) Blocks provide
self-calibrating, fully digital solutions for distributing,
delaying, multiplying, dividing, and phase-shifting clock
signals.
•
Configurable Logic Blocks (CLBs) contain flexible
Look-Up Tables (LUTs) that implement logic plus
storage elements used as flip-flops or latches. CLBs
perform a wide variety of logical functions as well as
store data.
These elements are organized as shown in Figure 1. A ring
of IOBs surrounds a regular array of CLBs. Each device has
two columns of block RAM except for the XC3S100E, which
has one column. Each RAM column consists of several
18-Kbit RAM blocks. Each block RAM is associated with a
dedicated multiplier. The DCMs are positioned in the center
with two at the top and two at the bottom of the device. The
XC3S100E has only one DCM at the top and bottom, while
the XC3S1200E and XC3S1600E add two DCMs in the
middle of the left and right sides.
•
Input/Output Blocks (IOBs) control the flow of data
between the I/O pins and the internal logic of the
device. Each IOB supports bidirectional data flow plus
3-state operation. Supports a variety of signal
standards, including four high-performance differential
standards. Double Data-Rate (DDR) registers are
included.
•
•
Block RAM provides data storage in the form of
18-Kbit dual-port blocks.
The Spartan-3E family features a rich network of traces that
interconnect all five functional elements, transmitting sig-
nals among them. Each functional element has an associ-
ated switch matrix that permits multiple connections to the
routing.
Multiplier Blocks accept two 18-bit binary numbers as
inputs and calculate the product.
Notes:
1. The XC3S1200E and XC3S1600E have two additional DCMs on both the left and right sides as
indicated by the dashed lines. The XC3S100E has only one DCM at the top and one at the bottom.
Figure 1: Spartan-3E Family Architecture
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DS312-1 (v1.1) March 21, 2005
Advance Product Specification
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Introduction and Ordering Information
Configuration
I/O Capabilities
Spartan-3E FPGAs are programmed by loading configura-
tion data into robust, reprogrammable, static CMOS config-
uration latches (CCLs) that collectively control all functional
elements and routing resources. The FPGA’s configuration
data is stored externally in a PROM or some other non-vol-
atile medium, either on or off the board. After applying
power, the configuration data is written to the FPGA using
any of seven different modes:
The Spartan-3E FPGA SelectIO interface supports many
popular single-ended and differential standards. Table 2
shows the number of user I/Os as well as the number of dif-
ferential I/O pairs available for each device/package combi-
nation.
Spartan-3E FPGAs support the following single-ended
standards:
•
•
3.3V, low-voltage TTL, LVTTL
•
•
Master Serial from a Xilinx Platform Flash PROM
Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V,
1.5V, or 1.2V
Serial Peripheral Interface (SPI) from an
industry-standard SPI serial Flash
•
•
•
3.3V PCI at 33 MHz and 66 MHz
•
Byte Peripheral Interface (BPI) Up or Down from an
industry-standard x8 or x8/x16 parallel NOR Flash
HSTL I and III at 1.8V, typically for memory applications
SSTL I at 1.8V and 2.5V, typically for memory
applications
•
•
•
Slave Serial, typically downloaded from a processor
Slave Parallel, typically downloaded from a processor
Spartan-3E FPGAs support the following differential stan-
dards:
Boundary Scan (JTAG), typically downloaded from a
processor or system tester.
•
•
•
•
LVDS
Bus LVDS
mini-LVDS
RSDS
Table 2: Available User I/Os and Differential (Diff) I/O Pairs
VQ100
CP132
TQ144
PQ208
FT256
FG320
FG400
FG484
VQG100
CPG132
TQG144
PQG208
FTG256
FGG320
FGG400
FGG484
Device
User Diff User Diff User Diff User Diff User Diff User Diff User Diff User Diff
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
66
66
-
30
30
-
-
92
92
-
-
41
41
-
108
40
40
-
-
158
158
-
-
65
65
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
108
172
190
190
-
68
77
77
-
-
-
-
-
-
232
250
250
92
99
99
-
-
-
-
-
304
304
124
124
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-
-
-
-
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376 156
Notes:
1. All Spartan-3E devices in the same package are pin-compatible.
DS312-1 (v1.1) March 21, 2005
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Advance Product Specification
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Introduction and Ordering Information
Package Marking
Figure 2 provides a top marking example for Spartan-3E
FPGAs in the quad-flat packages. Figure 3 shows the top
marking for Spartan-3E FPGAs in BGA packages except
the 132-ball chip-scale package (CP132 and CPG132). The
markings for the BGA packages are nearly identical to those
for the quad-flat packages, except that the marking is
rotated with respect to the ball A1 indicator. Figure 4 shows
the top marking for Spartan-3E FPGAs in the CP132 and
CPG132 packages.
Use the seven digits of the Lot Code to access additional
information for a specific device using the Xilinx web-based
Genealogy Viewer.
Mask Revision Code
Fabrication Code
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Process Technology
SPARTAN
Device Type
XC3S250ETM
Date Code
Lot Code
Package
PQ208AGQ0525
D1234567A
Speed Grade
4C
Temperature Range
Pin P1
DS312-1_06_032105
Figure 2: Spartan-3E QFP Example Package Marking
Mask Revision Code
R
BGA Ball A1
Fabrication Code
Process Code
R
SPARTAN
Device Type
XC3S250ETM
FT256AGQ0525
D1234567A
4C
Date Code
Lot Code
Package
Speed Grade
Temperature Range
DS312-1_02_032105
Figure 3: Spartan-3E BGA Example Package Marking
Ball A1
Device Type
3S250E
F1234567-0525
PHILIPPINES
Lot Code
Date Code
Temperature Range
Package
C5 = CP132
C6 = CPG132
C5AGQ
4C
Speed Grade
Process Code
Mask Revision Code
Fabrication Code
DS312-1_05_032105
Figure 4: Spartan-3E CP132 and CPG132 Example Package Marking
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DS312-1 (v1.1) March 21, 2005
Advance Product Specification
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Introduction and Ordering Information
Ordering Information
Spartan-3E FPGAs are available in both standard and Pb-free packaging options for all device/package combinations. The
Pb-free packages include a ‘G’ character in the ordering code.
Standard Packaging
Example: XC3S250E -4 FT 256 C
Device Type
Speed Grade
Package Type
Temperature Range:
C = Commercial (TJ = 0oC to 85oC)
I = Industrial (TJ = -40oC to 100oC)
Number of Pins
DS312_03_011405
Pb-Free Packaging
Example: XC3S250E -4 FT G 256 C
Device Type
Temperature Range:
C = Commercial (TJ = 0oC to 85oC)
I = Industrial (TJ = -40oC to 100oC)
Speed Grade
Package Type
Number of Pins
Pb-free
DS312_04_011405
Device
Speed Grade
Package Type / Number of Pins
Temperature Range (TJ)
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
–4 Standard Performance VQ(G)100 100-pin Very Thin Quad Flat Pack (VQFP)
Commercial (0°C to 85°C)
C
–5 High Performance
CP(G)132 132-ball Chip-Scale Package (CSP)
TQ(G)144 144-pin Thin Quad Flat Pack (TQFP)
PQ(G)208 208-pin Plastic Quad Flat Pack (PQFP)
FT(G)256 256-ball Fine-Pitch Thin Ball Grid Array (FTBGA)
FG(G)320 320-ball Fine-Pitch Ball Grid Array (FBGA)
I Industrial (–40°C to 100°C)
400-ball Fine-Pitch Ball Grid Array (FBGA)
FG(G)400
FG(G)484 484-ball Fine-Pitch Ball Grid Array (FBGA)
Notes:
1. The –5 speed grade is exclusively available in the Commercial temperature range.
DS312-1 (v1.1) March 21, 2005
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Advance Product Specification
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Introduction and Ordering Information
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revision
03/01/05
03/21/05
Initial Xilinx release.
1.1
Added XC3S250E in CP132 package to Table 2. Corrected number of differential I/O pairs
for CP132 package. Added package markings for QFP packages (Figure 2) and
CP132/CPG132 packages (Figure 4).
The Spartan-3E Family Data Sheet
DS312-1, Spartan-3E FPGA Family: Introduction and Ordering Information (Module 1)
DS312-2, Spartan-3E FPGA Family: Functional Description (Module 2)
DS312-3, Spartan-3E FPGA Family: DC and Switching Characteristics (Module 3)
DS312-4, Spartan-3E FPGA Family: Pinout Descriptions (Module 4)
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DS312-1 (v1.1) March 21, 2005
Advance Product Specification
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Spartan-3E FPGA Family:
Functional Description
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification
the delay element, there are alternate routes through a
pair of storage elements to the IQ1 and IQ2 lines. The
IOB outputs I, IQ1, and IQ2 lead to the FPGA’s internal
logic. The delay element can be set to ensure a hold
time of zero (see Input Delay Functions).
Introduction
As described in Architectural Overview, the Spartan™-3E
FPGA architecture consists of five fundamental functional
elements:
•
•
Input/Output Blocks (IOBs)
•
•
The output path, starting with the O1 and O2 lines,
carries data from the FPGA’s internal logic through a
multiplexer and then a three-state driver to the IOB
pad. In addition to this direct path, the multiplexer
provides the option to insert a pair of storage elements.
Configurable Logic Block (CLB) and Slice
Resources
•
•
•
Block RAM
Dedicated Multipliers
Digital Clock Managers (DCMs)
The 3-state path determines when the output driver is
high impedance. The T1 and T2 lines carry data from
the FPGA’s internal logic through a multiplexer to the
output driver. In addition to this direct path, the
multiplexer provides the option to insert a pair of
storage elements.
The following sections provide detailed information on each
of these functions. In addition, this section also describes
the following functions:
•
•
•
•
Clocking Infrastructure
Interconnect
•
All signal paths entering the IOB, including those
associated with the storage elements, have an inverter
option. Any inverter placed on these paths is
automatically absorbed into the IOB.
Configuration
Powering Spartan-3E FPGAs
Input/Output Blocks (IOBs)
IOB Overview
The Input/Output Block (IOB) provides a programmable,
unidirectional or bidirectional interface between a package
pin and the FPGA’s internal logic. The IOB is similar to that
of the Spartan-3 family with the following differences:
•
•
•
Input-only blocks are added
Programmable input delays are added to all blocks
DDR flip-flops can be shared between adjacent IOBs
The unidirectional input-only block has a subset of the full
IOB capabilities. Thus there are no connections or logic for
an output path. The following paragraphs assume that any
reference to output functionality does not apply to the
input-only blocks. The number of input-only blocks varies
with device size, but is never more than 25% of the total IOB
count.
Figure 1, page 2 is a simplified diagram of the IOB’s internal
structure. There are three main signal paths within the IOB:
the output path, input path, and 3-state path. Each path has
its own pair of storage elements that can act as either regis-
ters or latches. For more information, see Storage Element
Functions. The three main signal paths are as follows:
•
The input path carries data from the pad, which is
bonded to a package pin, through an optional
programmable delay element directly to the I line. After
© 2005 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc.
All other trademarks are the property of their respective owners.
DS312-2 (v1.1) March 21, 2005
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Functional Description
T
TFF1
D
T1
Q
CE
CK
SR REV
DDR
MUX
TCE
T2
D
Q
TFF2
CE
CK
SR REV
Three-state Path
ODDROUT1
V
CCO
OFF1
O1
ODDRIN1
OTCLK1
D
Q
CE
CK
Pull-Up
ESD
ESD
SR REV
DDR
MUX
I/O
Pin
OCE
Program-
Pull-
Down
O2
mable
Output
Driver
Q
D
OFF2
ODDRIN2
CE
CK
OTCLK2
SR REV
Keeper
Latch
Output Path
ODDROUT2
I
LVCMOS, LVTTL, PCI
IQ1
Programmable
Delay
IDDRIN1
IDDRIN2
D
Q
Single-ended Standards
using V
IFF1
REF
CE
V
REF
Pin
ICLK1
ICE
CK
SR REV
Differential Standards
IQ2
I/O Pin
from
Adjacent
IOB
D
Q
IFF2
CE
CK
ICLK2
SR REV
SR
REV
Input Path
DS312-2_19_030105
Notes:
1. All IOB signals communicating with the FPGA’s internal logic have the option of inverting polarity inside the IOB.
2. Signals shown with dashed lines connect to the adjacent IOB in a differential pair only, not to the FPGA fabric.
Figure 1: Simplified IOB Diagram
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DS312-2 (v1.1) March 21, 2005
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Functional Description
The delay values are set up in the silicon once at configura-
tion time—they are non-modifiable in device operation.
Input Delay Functions
Each IOB has a programmable delay block that can delay
the input signal from 0 to nominally 4000 ps. In Figure 2, the
signal is first delayed by either 0 or 2000 ps (nominal) and is
then applied to an 8 tap delay line. This delay line has a
nominal value of 250 ps per tap. All 8 taps are available via
a multiplexer for use as an asynchronous input directly into
the FPGA fabric. In this way, the delay is programmable
from 0 to 4000 ps in 250 ps steps. Four of the 8 taps are
also available via a multiplexer to the D inputs of the syn-
chronous storage elements. The delay inserted in the path
to the storage element can be varied from 0 to 4000 ps in
500 ps steps. The first, coarse delay element is common to
both asynchronous and synchronous paths, and must be
either used or not used for both paths.
The primary use for the input delay element is as an ade-
quate delay to ensure that there is no hold time requirement
when using the input flip-flop(s) with a global clock. The
necessary value for this function is chosen by the Xilinx soft-
ware tools and depends on device size. If the design is
using a DCM in the clock path, then the delay element can
be safely set to zero in the user's design, and there is still no
hold time requirement.
Both asynchronous and synchronous values can be modi-
fied by the user, which is useful where extra delay is
required on clock or data inputs, for example, in interfaces to
various types of RAM.
See Module 3 of the Spartan-3E data sheet for exact values
for the delay elements.
Synchronous input (IQ1)
D Q
Synchronous input (IQ2)
D Q
PAD
Asynchronous input (I)
DS312-2_18_022205
Figure 2: Input Delay Elements
DS312-2 (v1.1) March 21, 2005
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Functional Description
This is accomplished by taking data synchronized to the
clock signal’s rising edge and converting it to bits syn-
chronized on both the rising and the falling edge. The com-
bination of two registers and a multiplexer is referred to as a
Double-Data-Rate D-type flip-flop (ODDR2).
Storage Element Functions
There are three pairs of storage elements in each IOB, one
pair for each of the three paths. It is possible to configure
each of these storage elements as an edge-triggered
D-type flip-flop (FD) or a level-sensitive latch (LD).
Table 1 describes the signal paths associated with the stor-
age element.
The storage-element pair on either the Output path or the
Three-State path can be used together with a special multi-
plexer to produce Double-Data-Rate (DDR) transmission.
Table 1: Storage Element Signal Description
Storage
Element
Signal
Description
Data input
Function
D
Data at this input is stored on the active edge of CK and enabled by CE. For latch
operation when the input is enabled, data passes directly to the output Q.
Q
Data output
The data on this output reflects the state of the storage element. For operation as a latch
in transparent mode, Q mirrors the data at D.
CK
CE
Clock input
Data is loaded into the storage element on this input’s active edge with CE asserted.
Clock Enable input
When asserted, this input enables CK. If not connected, CE defaults to the asserted
state.
SR
Set/Reset input
Reverse input
This input forces the storage element into the state specified by the SRHIGH/SRLOW
attributes. The SYNC/ASYNC attribute setting determines if the SR input is
synchronized to the clock or not. If both SR and REV are active at the same time, the
storage element gets a value of 0.
REV
This input is used together with SR. It forces the storage element into the state opposite
from what SR does. The SYNC/ASYNC attribute setting determines whether the REV
input is synchronized to the clock or not. If both SR and REV are active at the same time,
the storage element gets a value of 0.
trols the CE inputs for the register pair on the three-state
path and ICE does the same for the register pair on the
input path.
As shown in Figure 1, the upper registers in both the output
and three-state paths share a common clock. The OTCLK1
clock signal drives the CK clock inputs of the upper registers
on the output and three-state paths. Similarly, OTCLK2
drives the CK inputs for the lower registers on the output
and three-state paths. The upper and lower registers on the
input path have independent clock lines: ICLK1 and ICLK2.
The Set/Reset (SR) line entering the IOB controls all six
registers, as is the Reverse (REV) line.
In addition to the signal polarity controls described in IOB
Overview, each storage element additionally supports the
controls described in Table 2.
The OCE enable line controls the CE inputs of the upper
and lower registers on the output path. Similarly, TCE con-
Table 2: Storage Element Options
Option Switch
Function
Specificity
FF/Latch
Chooses between an edge-triggered flip-flop
or a level-sensitive latch
Independent for each storage element
SYNC/ASYNC
Determines whether the SR set/reset control is Independent for each storage element
synchronous or asynchronous
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Functional Description
Table 2: Storage Element Options
Option Switch
Function
Specificity
SRHIGH/SRLOW Determines whether SR acts as a Set, which
forces the storage element to a logic "1"
Independent for each storage element, except
when using ODDR2. In the latter case, the selection
(SRHIGH) or a Reset, which forces a logic "0" for the upper element will apply to both elements.
(SRLOW)
INIT1/INIT0
When Global Set/Reset (GSR) is asserted or
after configuration this option specifies the
initial state of the storage element, either set
(INIT1) or reset (INIT0). By default, choosing
Independent for each storage element, except
when using ODDR2, which uses two IOBs. In the
ODDR2 case, selecting INIT0 for one IOBs applies
to both elements within the IOB, although INIT1
SRLOW also selects INIT0; choosing SRHIGH could be selected for the elements in the other IOB.
also selects INIT1.
The storage-element pair on the Three-State path (TFF1
Double-Data-Rate Transmission
and TFF2) also can be combined with a local multiplexer to
form a DDR primitive. This permits synchronizing the output
enable to both the rising and falling edges of a clock. This
DDR operation is realized in the same way as for the output
path.
Double-Data-Rate (DDR) transmission describes the tech-
nique of synchronizing signals to both the rising and falling
edges of the clock signal. Spartan-3E devices use register
pairs in all three IOB paths to perform DDR operations.
The pair of storage elements on the IOB’s Output path
(OFF1 and OFF2), used as registers, combine with a spe-
cial multiplexer to form a DDR D-type flip-flop (ODDR2).
This primitive permits DDR transmission where output data
bits are synchronized to both the rising and falling edges of
a clock. DDR operation requires two clock signals (usually
50% duty cycle), one the inverted form of the other. These
signals trigger the two registers in alternating fashion, as
shown in Figure 3. The Digital Clock Manager (DCM) gen-
erates the two clock signals by mirroring an incoming signal,
and then shifting it 180 degrees. This approach ensures
minimal skew between the two signals. Alternatively, the
inverter inside the IOB can be used to invert the clock sig-
nal, thus only using one clock line and both rising and falling
edges of that clock line as the two clocks for the DDR
flip-flops.
The storage-element pair on the input path (IFF1 and IFF2)
allows an I/O to receive a DDR signal. An incoming DDR
clock signal triggers one register, and the inverted clock sig-
nal triggers the other register. The registers take turns cap-
turing bits of the incoming DDR data signal. The primitive to
allow this functionality is called IDDR2.
Aside from high bandwidth data transfers, DDR outputs also
can be used to reproduce, or mirror, a clock signal on the
output. This approach is used to transmit clock and data sig-
nals together (source synchronously). A similar approach is
used to reproduce a clock signal at multiple outputs. The
advantage for both approaches is that skew across the out-
puts is minimal.
DCM
DCM
0˚
180˚ 0˚
FDDR
FDDR
D1
D1
Q1
Q1
CLK1
CLK1
DDR MUX
DDR MUX
Q
Q
D2
Q2
D2
Q2
CLK2
CLK2
DS312-2_20_021105
Figure 3: Two Methods for Clocking the DDR Register
DS312-2 (v1.1) March 21, 2005
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Functional Description
Register Cascade Feature
In the Spartan-3E family, one of the IOBs in a differential
pair can cascade either its input or output storage elements
with those in the other IOB of the differential pair. This is
intended to make DDR operation at high speed much sim-
pler to implement. The new DDR connections that are avail-
able are shown in Figure 1 (dashed lines), and are only
available for routing between IOBs and are not accessible to
the FPGA fabric. Note that this feature is only available
when using differential I/O.
Q
Q
D
D
D1
PAD
To Fabric
D2
IDDRIN2
IQ2
Q
D
ICLK1
ICLK2
IDDR2
As a DDR input pair, the master IOB registers incoming
data on the rising edge of ICLK1 (= D1) and the rising edge
of ICLK2 (= D2), which is typically the same as the falling
edge of ICLK1. This data is then transferred into the FPGA
fabric. At some point, both signals must be brought into the
same clock domain, typically ICLK1. This can be difficult at
high frequencies because the available time is only one half
of a clock cycle assuming a 50% duty cycle. See Figure 4
for a graphical illustration of this function.
ICLK1
ICLK2
d
d+1 d+2 d+3 d+4 d+5 d+6 d+7 d+8
PAD
D1
d
d+2
d+1
d+4
d+3
d+6
d+5
d+8
d+7
D2
d-1
DS312-2_22_030105
In the Spartan-3E device, the signal D2 can be cascaded
into the storage element of the adjacent slave IOB. There it
is re-registered to ICLK1, and only then fed to the FPGA
fabric where it is now already in the same time domain as
D1. Here, the FPGA fabric uses only the clock ICLK1 to pro-
cess the received data. See Figure 5 for a graphical illustra-
tion of this function.
Figure 5: Input DDR Using Spartan-3E Cascade Feature
ODDR2
As a DDR output pair, the master IOB registers data coming
from the FPGA fabric on the rising edge of OCLK1 (= D1)
and the rising edge of OCLK2 (= D2), which is typically the
same as the falling edge of OCLK1. These two bits of data
are multiplexed by the DDR mux and forwarded to the out-
put pin. At some point in the FPGA fabric, the signal D2
must be brought into the clock domain OCLK2 from the
domain OCLK1. This can be difficult at high frequencies,
because the time available is only one half a clock cycle.
See Figure 6 for a graphical illustration of this function.
Q
Q
D
D
D1
PAD
To Fabric
D2
In the Spartan-3E device, the signal D2 can be cascaded
via the storage element of the adjacent slave IOB. Here, it is
registered by OCLK1 and then forwarded to the master IOB
where it is re-registered to OCLK2, selected as usual by the
DDR multiplexer, and then forwarded to the output pin. This
way the data for transmission can be processed using just
the clock OCLK1 in the FPGA fabric. See Figure 7 for a
graphical illustration of this function.
ICLK2
ICLK1
ICLK1
ICLK2
PAD
D1
d
d+1 d+2 d+3 d+4 d+5 d+6 d+7 d+8
d+2 d+4 d+6
d
d+8
d+7
D2 d-1
d+1
d+3
d+5
DS312-2_21_021105
Figure 4: Input DDR (without Cascade Feature)
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification
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Functional Description
Q
Q
Q
Q
D
D
D
D
D1
D1
From
PAD
PAD
From
Fabric
Fabric
ODDROUT1
D2
D2
Q
D
ODDRIN2
OCLK1
OCLK2
OCLK1
OCLK2
OCLK1
OCLK1
OCLK2
D1
OCLK2
D1
d
d+2
d+3
d+4
d+5
d+6
d+7
d+8
d+9
d
d+2
d+4
d+6
d+8
d+10
d+9
D2
d+1
D2
d+1
d+3
d+5
d+7
d+5 d+6
PAD
d+6
d+5
d+7 d+8
d
d+1 d+2 d+3 d+4
d+8
PAD
d+7
d
d+1 d+2 d+3 d+4
DS312-2_23_030105
DS312-2_36_030105
Figure 7: Output DDR Using Spartan-3E Cascade
Figure 6: Output DDR (without Cascade Feature)
Feature
SelectIO Signal Standards
The Spartan-3E I/Os feature inputs and outputs that sup-
port a wide range of I/O signaling standards (Table 3 and
Table 4). The majority of the I/Os also can be used to form
differential pairs to support any of the differential signaling
standards (Table 4).
To define the I/O signaling standard in a design, set the
IOSTANDARD attribute to the appropriate setting. Xilinx
provides a variety of different methods for applying the
IOSTANDARD for maximum flexibility. For a full description
of different methods of applying attributes to control
IOSTANDARD, refer to “Entry Strategies for Xilinx Con-
straints” in the Xilinx Software Manuals and Help.
Spartan-3E FPGAs provide additional input flexibility by
allowing I/O standards to be mixed in different banks. Spe-
cial care must be taken to ensure the input voltages do not
exceed VCCO (see Module 3 for the specifications). For a
particular VCCO voltage, Table 3 and Table 4 list all of the
IOSTANDARDs that can be combined and if the IOSTAN-
DARD is supported as an input only or can be used for both
inputs and outputs.
DS312-2 (v1.1) March 21, 2005
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Functional Description
Table 3: Single-Ended IOSTANDARD Bank Compatibility
VCCO Supply/Compatibility
Input Requirements
Board
VREF for
Termination
Single-Ended
IOSTANDARD
Inputs
N/R
N/R
N/R
N/R
N/R
N/R(1)
N/R
N/R
N/R
0.9
1.2 V
1.5 V
1.8 V
2.5 V
3.0 V
3.3 V
Voltage (VTT)
Input/
Output
LVTTL
-
-
-
-
-
N/R
Input/
Output
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI33_3
-
-
-
-
-
-
-
-
-
-
-
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
0.9
Input/
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input/
Output
Input
Input
Input
-
Input/
Output
Input
Input/
Output
Input
Input
Input/
Output
-
-
-
-
-
-
Input/
Output
PCI66_3
-
Input/
Output
PCIX
Input/
Output
HSTL_I_18
HSTL_III_18
SSTL18_I
-
-
-
-
-
-
-
-
Input
Input
Input
Input
Input
Input
Input
Input/
Output
1.1
1.8
Input/
Output
0.9
0.9
Input/
Output
SSTL2_I
-
1.25
1.25
Notes:
1. N/R - Not required for input operation.
8
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification
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Functional Description
Input Requirements: VREF
Table 4: Differential IOSTANDARD Bank Compatibility
VCCO Supply
Differential
IOSTANDARD
2.5V
3.3V
Input,
LVDS_25
On-chip Differential Termination,
Output(1)
Input
Input,
On-chip Differential Termination,
Output(1)
RSDS_25
Input
N/R
Input,
On-chip Differential Termination,
Output(1)
MINI_LVDS_25
LVPECL_25
Input
Input
Input
(Not Required)
Input,
On-chip Differential Termination
Input,
On-chip Differential Termination,
Output
BLVDS_25
Notes:
1. Each bank can support any two of the following: LVDS_25 outputs, MINI_LVDS_25 outputs, RSDS_25 outputs.
HSTL and SSTL inputs use the Reference Voltage (VREF) to
bias the input-switching threshold. Once a configuration
data file is loaded into the FPGA that calls for the I/Os of a
given bank to use HSTL/SSTL, a few specifically reserved
I/O pins on the same bank automatically convert to VREF
inputs. For banks that do not contain HSTL or SSTL, VREF
pins remain available for user I/Os or input pins.
(See Module 3 for the specific range). The on-chip input dif-
ferential termination in Spartan-3E devices eliminates the
external 100Ω termination resistor commonly found in dif-
ferential receiver circuits. Use differential termination for
LVDS, mini-LVDS, and BLVDS as applications permit.
On-chip Differential Termination is available in banks with
V
CCO = 2.5V and is not supported on dedicated input pins.
Differential standards employ a pair of signals, one the
opposite polarity of the other. The noise canceling proper-
ties (for example, Common-Mode Rejection) of these stan-
dards permit exceptionally high data transfer rates. This
subsection introduces the differential signaling capabilities
of Spartan-3E devices.
Set the DIFF_TERM attribute to TRUE to enable Differential
Termination on a differential I/O pin pair.
The DIFF_TERM attribute uses the following syntax in the
UCF file:
INST <I/O_BUFFER_INSTANTIATION_NAME>
DIFF_TERM = “<TRUE/FALSE>”;
Each device-package combination designates specific I/O
pairs specially optimized to support differential standards.
Differential pairs can be shown in the Pin and Area Con-
straints Editor (PACE) with the “Show Differential Pairs”
option. A unique L-number, part of the pin name, identifies
the line-pairs associated with each bank (see Module 4).
For each pair, the letters P and N designate the true and
inverted lines, respectively. For example, the pin names
IO_L43P_3 and IO_L43N_3 indicate the true and inverted
lines comprising the line pair L43 on Bank 3.
Spartan-3E
Differential
Output
Spartan-3E
Differential Input
Z
= 50Ω
0
Z
Z
= 50Ω
= 50Ω
0
0
Spartan-3E
Differential Input
with On-Chip
Differential
Spartan-3E
Differential
Output
VCCO provides current to the outputs and additionally pow-
Terminator
ers the On-Chip Differential Termination. VCCO must be
2.5V when using the On-Chip Differential Termination. The
V
REF lines are not required for differential operation.
Z
= 50Ω
0
To further understand how to combine multiple IOSTAN-
DARDs within a bank, refer to IOBs Organized into Banks,
page 10.
DS312-2_24_021505
Figure 8: Differential Inputs and Outputs
Pull-Up and Pull-Down Resistors
On-Chip Differential Termination
Pull-up and pull-down resistors inside each IOB optionally
force a floating I/O pin to a determined state. Pull-up and
Spartan-3E devices provide an on-chip 100Ω differential
termination across the input differential receiver terminals
DS312-2 (v1.1) March 21, 2005
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Advance Product Specification
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Functional Description
pull-down resistors are commonly applied to unused I/Os,
inputs, and three-state outputs, but can be used on any I/O.
The pull-up resistor connects an I/O to VCCO through a
resistor. The resistance value depends on the VCCO voltage
(see Module 3 for the specifications). The pull-down resistor
similarly connects an I/O to ground with a resistor. The PUL-
LUP and PULLDOWN attributes and library primitives turn
on these optional resistors.
To adjust the drive strength for each output set the DRIVE
attribute to the desired drive strength: 2, 4, 6, 8, 12, and 16.
Table 5: Programmable Output Drive Current
Output Drive Current (mA)
Signal
Standard
2
4
6
8
ꢀ
ꢀ
ꢀ
ꢀ
-
12
ꢀ
ꢀ
ꢀ
-
16
ꢀ
ꢀ
-
LVTTL
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
-
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
-
By default, PULLDOWN resistors terminate all unused I/Os.
Unused I/Os can alternatively be set to PULLUP or FLOAT.
To change the unused I/O Pad setting, set the Bitstream
Generator (BitGen) option UnusedPin to PULLUP, PULL-
DOWN, or FLOAT. The UnusedPin option is accessed
through the Properties for Generate Programming File in
ISE.
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
-
-
-
During configuration a Low logic level on HSWAP activates
the pull-up resistors for all I/Os not used directly in the
selected configuration mode.
-
-
-
High output current drive strength and FAST output slew
rates generally result in fastest I/O performance. However,
these same settings generally also result in transmission
line effects on the printed circuit board (PCB) for all but the
shortest board traces. Each IOB has independent slew rate
and drive strength controls. Use the slowest slew rate and
lowest output drive current that meets the performance
requirements for the end application.
Keeper Circuit
Each I/O has an optional keeper circuit (see Figure 9) that
keeps bus lines from floating when not being actively driven.
The KEEPER circuit retains the last logic level on a line after
all drivers have been turned off. Apply the KEEPER
attribute or use the KEEPER library primitive to use the
KEEPER circuitry. Pull-up and pull-down resistors override
the KEEPER settings.
Likewise, due to lead inductance, a given package supports
a limited number of simultaneous switching outputs (SSOs)
when using fast, high-drive outputs. Only use fast,
high-drive outputs when required by the application.
Weak Pull-up
IOBs Organized into Banks
Output Path
Input Path
The Spartan-3E architecture organizes IOBs into four I/O
banks as shown in Figure 10. Each bank maintains sepa-
rate VCCO and VREF supplies. The separate supplies allow
each bank to independently set VCCO. Similarly, the VREF
supplies may be set for each bank. Refer to Table 3 and
Table 4 for VCCO and VREF requirements.
Keeper
Weak Pull-down
DS312-2_25_022805
When working with Spartan-3E devices, most of the differ-
ential I/O standards are compatible and can be combined
within any given bank. Each bank can support any two of
the following differential standards: LVDS_25 outputs,
MINI_LVDS_25 outputs, and RSDS_25 outputs. As an
example, LVDS_25 outputs, RSDS_25 outputs, and any
other differential inputs while using on-chip differential ter-
mination are a valid combination. A combination not allowed
is a single bank with LVDS_25 outputs, RSDS_25 outputs,
and MINI_LVDS_25 outputs.
Figure 9: Keeper Circuit
Slew Rate Control and Drive Strength
Each IOB has a slew-rate control that sets the output
switching edge-rate for LVCMOS and LVTTL outputs. The
SLEW attribute controls the slew rate and can either be set
to SLOW (default) or FAST.
Each LVCMOS and LVTTL output additionally supports up
to six different drive current strengths as shown in Table 5.
10
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Functional Description
are outlined for each package, such as pins that are uncon-
nected on one device but connected on another in the same
package or pins that are dedicated inputs on one package
but full I/O on another. When designing the printed circuit
board (PCB), plan for potential future upgrades and pack-
age migration.
Bank 0
The Spartan-3E family is not pin-compatible with any previ-
ous Xilinx FPGA family.
Dedicated Inputs
Bank 2
Dedicated Inputs are IOBs used only as inputs. Pin names
designate a Dedicated Input if the name starts with IP, for
example, IP or IP_Lxxx_x. Dedicated inputs retain the full
functionality of the IOB for input functions with a single
exception for differential inputs (IP_Lxxx_x). For the differ-
ential Dedicated Inputs, the on-chip differential termination
is not available. To replace the on-chip differential termina-
tion, choose a differential pair that supports outputs
(IO_Lxxx_x) or use an external 100Ω termination resistor on
the board.
DS312-2_26_021205
Figure 10: Spartan-3E I/O Banks (top view)
I/O Banking Rules
When assigning I/Os to banks, these VCCO rules must be
followed:
1. All VCCO pins on the FPGA must be connected even if a
bank is unused.
2. All VCCO lines associated within a bank must be set to
the same voltage level.
ESD Protection
Clamp diodes protect all device pads against damage from
Electro-Static Discharge (ESD) as well as excessive voltage
transients. Each I/O has two clamp diodes: one diode
extends P-to-N from the pad to VCCO and a second diode
extends N-to-P from the pad to GND. During operation,
these diodes are normally biased in the off state. These
clamp diodes are always connected to the pad, regardless
of the signal standard selected. The presence of diodes lim-
its the ability of Spartan-3E I/Os to tolerate high signal volt-
ages. The VIN absolute maximum rating in Table 1 of
Module 3 specifies the voltage range that I/Os can tolerate.
3. The VCCO levels used by all standards assigned to the
I/Os of any given bank must agree. The Xilinx
development software checks for this. Table 3 and
Table 4 describe how different standards use the VCCO
supply.
4. If a bank does not have any VCCO requirements,
connect VCCO to an available voltage, such as 2.5V or
3.3V. Some configuration modes might place additional
VCCO requirements. Refer to Configuration, page 56
for more information.
If any of the standards assigned to the Inputs of the bank
use VREF, then the following additional rules must be
observed:
Supply Voltages for the IOBs
The IOBs are powered by three supplies:
1. All VREF pins must be connected within a bank.
1. The VCCO supplies, one for each of the FPGA’s I/O
banks, power the output drivers. The voltage on the
2. All VREF lines associated with the bank must be set to
the same voltage level.
V
CCO pins determines the voltage swing of the output
signal.
CCINT is the main power supply for the FPGA’s internal
logic.
3. The VREF levels used by all standards assigned to the
Inputs of the bank must agree. The Xilinx development
software checks for this. Table 3 describes how different
standards use the VREF supply.
2.
V
3. VCCAUX is an auxiliary source of power, primarily to
optimize the performance of various FPGA functions
such as I/O switching.
If VREF is not required to bias the input switching thresholds,
all associated VREF pins within the bank can be used as
user I/Os or input pins.
The I/Os During Power-On, Configuration, and
User Mode
Package Footprint Compatibility
Sometimes, applications outgrow the logic capacity of a
specific Spartan-3E FPGA. Fortunately, the Spartan-3E
family is designed so that multiple part types are available in
pin-compatible package footprints, as described in Module
4. In some cases, there are subtle differences between
devices available in the same footprint. These differences
All I/Os have ESD clamp diodes to their respective VCCO
supply and from GND, as shown in Figure 1. The VCCINT
(1.2V), VCCAUX (2.5V), and VCCO supplies can be applied in
any order. Before the FPGA can start its configuration pro-
cess, VCCINT, VCCO Bank 2, and VCCAUX must have
reached their respective minimum recommended operating
DS312-2 (v1.1) March 21, 2005
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Advance Product Specification
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Functional Description
levels (see Table 2 of Module 3). At this time, all I/O drivers
are in a high-impedance state. VCCO Bank 2, VCCINT, and
loaded design reverses the polarity of their respective SR
inputs.
V
CCAUX serve as inputs to the internal Power-On Reset cir-
The Global Three State (GTS) net is released during
Start-Up, marking the end of configuration and the begin-
ning of design operation in the User mode. After the GTS
net is released, all user I/Os go active while all unused I/Os
are weakly pulled down (PULLDOWN). The designer can
control how the unused I/Os are terminated after GTS is
released by setting the Bitstream Generator (BitGen) option
UnusedPin to PULLUP, PULLDOWN, or FLOAT.
cuit (POR).
A Low level applied to the HSWAP input enables pull-up
resistors on User I/Os from power-on throughout configura-
tion. A High level on HSWAP disables the pull-up resistors,
allowing the I/Os to float. HSWAP contains a weak pull-up
and defaults to High if left floating. As soon as power is
applied, the FPGA begins initializing its configuration mem-
ory. At the same time, the FPGA internally asserts the Glo-
bal Set-Reset (GSR), which asynchronously resets all IOB
storage elements to a default Low state.
One clock cycle later (default), the Global Write Enable
(GWE) net is released allowing the RAM and registers to
change states. Once in User mode, any pull-up resistors
enabled by HSWAP revert to the user settings and HSWAP
is available as a general-purpose I/O. For more information
on PULLUP and PULLDOWN, see Pull-Up and Pull-Down
Resistors.
Upon the completion of initialization and the beginning of
configuration, INIT_B goes High, sampling the M0, M1, and
M2 inputs to determine the configuration mode. At this point
in time, the configuration data is loaded into the FPGA. The
I/O drivers remain in a high-impedance state (with or with-
out pull-up resistors, as determined by the HSWAP input)
throughout configuration.
JTAG Boundary-Scan Capability
All Spartan-3E IOBs support boundary-scan testing com-
patible with IEEE 1149.1/1532 standards. See JTAG Mode,
page 86 for more information on programming via JTAG.
At the end of configuration, the GSR net is released, placing
the IOB registers in a Low state by default, unless the
12
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Functional Description
and additional multiplexers and carry logic simplify wide
logic and arithmetic functions. Most general-purpose logic
in a design is automatically mapped to the slice resources in
the CLBs. Each CLB is identical, and the Spartan-3E family
CLB structure is identical to that for the Spartan-3 family.
Configurable Logic Block (CLB) and
Slice Resources
CLB Overview
The Configurable Logic Blocks (CLBs) constitute the main
logic resource for implementing synchronous as well as
combinatorial circuits. Each CLB contains four slices, and
each slice contains two Look-Up Tables (LUTs) to imple-
ment logic and two dedicated storage elements that can be
used as flip-flops or latches. The LUTs can be used as a
16x1 memory (RAM16) or as a 16-bit shift register (SRL16),
CLB Array
The CLBs are arranged in a regular array of rows and col-
umns as shown in Figure 11.
Each density varies by the number of rows and columns of
CLBs (see Table 6).
X0Y3 X1Y3
X0Y2 X1Y2
X2Y3 X3Y3
X2Y2 X3Y2
X0Y1 X1Y1
X0Y0 X1Y0
X2Y1 X3Y1
X2Y0 X3Y0
Spartan-3E
FPGA
IOBs
Slice
CLB
DS312-2_31_021205
Figure 11: CLB Locations
Table 6: Spartan-3E CLB Resources
CLB
Rows
CLB
Columns
CLB
LUTs /
Flip-Flops
Equivalent
Logic Cells
RAM16 /
SRL16
Distributed
RAM Bits
Device
Total(1)
Slices
960
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
22
34
46
60
76
16
26
34
46
58
240
1920
2160
5508
960
2448
4656
8672
14752
15360
39168
74496
138752
236032
612
2448
4656
8672
14752
4896
1164
2168
3688
9312
10476
19512
33192
17344
29504
Notes:
1. The number of CLBs is less than the multiple of the rows and columns because the block RAM/multiplier blocks and the DCMs are
embedded in the array (see Module 1, Figure 1).
LUTs support both logic and memory (including both
Slices
RAM16 and SRL16 shift registers) while half support logic
Each CLB comprises four interconnected slices, as shown
only, and the two types alternate throughout the array col-
in Figure 13. These slices are grouped in pairs. Each pair is
umns. The SLICEL reduces the size of the CLB and lowers
organized as a column with an independent carry chain.
the cost of the device, and can also provide a performance
The left pair supports both logic and memory functions and
advantage over the SLICEM.
its slices are called SLICEM. The right pair supports logic
only and its slices are called SLICEL. Therefore half the
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Advance Product Specification
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Functional Description
.
WF[4:1]
DS312-2_32_021205
Notes:
1. Options to invert signal polarity as well as other options that enable lines for various functions are not shown.
2. The index i can be 6, 7, or 8, depending on the slice. The upper SLICEL has an F8MUX, and the upper SLICEM has
an F7MUX. The lower SLICEL and SLICEM both have an F6MUX.
Figure 12: Simplified Diagram of the Left-Hand SLICEM
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Functional Description
Left-Hand SLICEM
(Logic or Distributed RAM
or Shift Register)
Right-Hand SLICEL
(Logic Only)
COUT
CLB
SLICE
X1Y1
SLICE
X1Y0
COUT
Switch
Matrix
Interconnect
to Neighbors
CIN
SLICE
X0Y1
SHIFTOUT
SHIFTIN
SLICE
X0Y0
CIN
DS099-2_05_082104
Figure 13: Arrangement of Slices within the CLB
Slice Location Designations
Slice Overview
The Xilinx development software designates the location of
a slice according to its X and Y coordinates, starting in the
bottom left corner, as shown in Figure 11. The letter ’X’ fol-
lowed by a number identifies columns of slices, increment-
ing from the left side of the die to the right. The letter ’Y’
followed by a number identifies the position of each slice in
a pair as well as indicating the CLB row, incrementing from
the bottom of the die. Figure 13 shows the CLB located in
the lower left-hand corner of the die. The SLICEM always
has an even ’X’ number, and the SLICEL always has an odd
’X’ number.
A slice includes two LUT function generators and two stor-
age elements, along with additional logic, as shown in
Figure 14.
Both SLICEM and SLICEL have the following elements in
common to provide logic, arithmetic, and ROM functions:
•
•
•
•
Two 4-input LUT function generators, F and G
Two storage elements
Two wide-function multiplexers, F5MUX and FiMUX
Carry and arithmetic logic
FiMUX
SRL16
FiMUX
RAM16
Carry
Carry
LUT4 (G)
LUT4 (G)
Register
Register
F5MUX
F5MUX
SRL16
RAM16
Carry
Carry
Register
Register
LUT4 (F)
LUT4 (F)
Arithmetic Logic
Arithmetic Logic
DS312-2_13_020905
SLICEM
SLICEL
Figure 14: Resources in a Slice
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Functional Description
The SLICEM pair supports two additional functions:
Enable (CE), Slice Write Enable (SLICEWE1), and
Reset/Set (RS) are shared in common between the two
halves.
•
•
Two 16x1 distributed RAM blocks, RAM16
Two 16-bit shift registers, SRL16
The LUTs located in the top and bottom portions of the slice
are referred to as "G" and "F", respectively, or the "G-LUT"
and the "F-LUT". The storage elements in the top and bot-
tom portions of the slice are called FFY and FFX, respec-
tively.
Each of these elements is described in more detail in the fol-
lowing sections.
Logic Cells
The combination of a LUT and a storage element is known
as a "Logic Cell". The additional features in a slice, such as
the wide multiplexers, carry logic, and arithmetic gates, add
to the capacity of a slice, implementing logic that would oth-
erwise require additional LUTs. Benchmarks have shown
that the overall slice is equivalent to 2.25 simple logic cells.
This calculation provides the equivalent logic cell count
shown in Table 6.
Each slice has two multiplexers with F5MUX in the bottom
portion of the slice and FiMUX in the top portion. Depending
on the slice, the FiMUX takes on the name F6MUX,
F7MUX, or F8MUX, according to its position in the multi-
plexer chain. The lower SLICEL and SLICEM both have an
F6MUX. The upper SLICEM has an F7MUX, and the upper
SLICEL has an F8MUX.
The carry chain enters the bottom of the slice as CIN and
exits at the top as COUT. Five multiplexers control the chain:
CYINIT, CY0F, and CYMUXF in the bottom portion and
CY0G and CYMUXG in the top portion. The dedicated arith-
metic logic includes the exclusive-OR gates XORF and
XORG (bottom and top portions of the slice, respectively)
as well as the AND gates FAND and GAND (bottom and top
portions, respectively).
Slice Details
Figure 16 is a detailed diagram of the SLICEM. It represents
a superset of the elements and connections to be found in
all slices. The dashed and gray lines (blue when viewed in
color) indicate the resources found only in the SLICEM and
not in the SLICEL.
Each slice has two halves, which are differentiated as top
and bottom to keep them distinct from the upper and lower
slices in a CLB. The control inputs for the clock (CLK), Clock
See Table 7 for a description of all the slice input and output
signals.
Table 7: Slice Inputs and Outputs
Name
F[4:1]
Location
SLICEL/M Bottom
SLICEL/M Top
Direction
Input
Description
F-LUT and FAND inputs
G[4:1]
BX
Input
G-LUT and GAND inputs or Write Address (SLICEM)
SLICEL/M Bottom
Input
Bypass to or output (SLICEM) or storage element, or control input to
F5MUX, input to carry logic, or data input to RAM (SLICEM)
BY
SLICEL/M Top
Input
Bypass to or output (SLICEM) or storage element, or control input to
FiMUX, input to carry logic, or data input to RAM (SLICEM)
BXOUT
BYOUT
ALTDIG
DIG
SLICEM Bottom
SLICEM Top
SLICEM Top
SLICEM Top
Output
Output
Input
BX bypass output
BY bypass output
Alternate data input to RAM
Output
Input
ALTDIG or SHIFTIN bypass output
RAM Write Enable
SLICEWE1 SLICEM Common
F5
SLICEL/M Bottom
SLICEL/M Top
Output
Input
Output from F5MUX; direct feedback to FiMUX
Input to FiMUX; direct feedback from F5MUX or another FiMUX
Input to FiMUX; direct feedback from F5MUX or another FiMUX
Output from FiMUX; direct feedback to another FiMUX
FFX/Y Clock Enable
FXINA
FXINB
Fi
SLICEL/M Top
Input
SLICEL/M Top
Output
Input
CE
SLICEL/M Common
SLICEL/M Common
SR
Input
FFX/Y Set or Reset or RAM Write Enable (SLICEM)
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Functional Description
Table 7: Slice Inputs and Outputs (Continued)
Name
CLK
SHIFTIN
Location
SLICEL/M Common
SLICEM Top
Direction
Input
Description
FFX/Y Clock or RAM Clock (SLICEM)
Data input to G-LUT RAM
Shift data output from F-LUT RAM
Carry chain input
Input
SHIFTOUT SLICEM Bottom
Output
Input
CIN
COUT
X
SLICEL/M Bottom
SLICEL/M Top
Output
Output
Output
Output
Output
Output
Output
Carry chain output
SLICEL/M Bottom
SLICEL/M Top
Combinatorial output
Y
Combinatorial output
XB
YB
XQ
YQ
SLICEL/M Bottom
SLICEL/M Top
Combinatorial output from carry or F-LUT SRL16 (SLICEM)
Combinatorial output from carry or G-LUT SRL16 (SLICEM)
SLICEL/M Bottom
SLICEL/M Top
FFX output
FFY output
BY in the top half) can take any of several possible
branches:
Main Logic Paths
Central to the operation of each slice are two nearly identi-
cal data paths at the top and bottom of the slice. The
description that follows uses names associated with the bot-
tom path. (The top path names appear in parentheses.) The
basic path originates at an interconnect switch matrix out-
side the CLB. See Interconnect for more information on the
switch matrix and the routing connections.
1. Bypass both the LUT and the storage element, and
then exit the slice as BXOUT (or BYOUT) and return to
interconnect.
2. Bypass the LUT, and then pass through a storage
element via the D input before exiting as XQ (or YQ).
3. Control the wide function multiplexer F5MUX (or
FiMUX).
Four lines, F1 through F4 (or G1 through G4 on the upper
path), enter the slice and connect directly to the LUT. Once
inside the slice, the lower 4-bit path passes through a LUT
"F" (or "G") that performs logic operations. The LUT Data
output, "D", offers five possible paths:
4. Via multiplexers, serve as an input to the carry chain.
5. Drive the DI input of the LUT.
6. BY can control the REV inputs of both the FFY and FFX
storage elements. See Storage Element Functions.
1. Exit the slice via line "X" (or "Y") and return to
interconnect.
7. Finally, the DIG_MUX multiplexer can switch BY onto
the DIG line, which exits the slice.
2. Inside the slice, "X" (or "Y") serves as an input to the
DXMUX (or DYMUX) which feeds the data input, "D", of
the FFY (or FFX) storage element. The "Q" output of
the storage element drives the line XQ (or YQ) which
exits the slice.
The control inputs CLK, CE, SR, BX and BY have program-
mable polarity. The LUT inputs do not need programmable
polarity because their function can be inverted inside the
LUT.
3. Control the CYMUXF (or CYMUXG) multiplexer on the
carry chain.
The sections that follow provide more detail on individual
functions of the slice.
4. With the carry chain, serve as an input to the XORF (or
XORG) exclusive-OR gate that performs arithmetic
operations, producing a result on "X" (or "Y").
Look-Up Tables
The Look-Up Table or LUT is a RAM-based function gener-
ator and is the main resource for implementing logic func-
tions. Furthermore, the LUTs in each SLICEM pair can be
configured as Distributed RAM or a 16-bit shift register, as
described later.
5. Drive the multiplexer F5MUX to implement logic
functions wider than four bits. The "D" outputs of both
the F-LUT and G-LUT serve as data inputs to this
multiplexer.
Each of the two LUTs (F and G) in a slice have four logic
inputs (A1-A4) and a single output (D). Any four-variable
Boolean logic operation can be implemented in one LUT.
Functions with more inputs can be implemented by cascad-
In addition to the main logic paths described above, there
are two bypass paths that enter the slice as BX and BY.
Once inside the FPGA, BX in the bottom half of the slice (or
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Functional Description
ing LUTs or by using the wide function multiplexers that are
described later.
Wide Multiplexers
Wide-function multiplexers effectively combine LUTs in
order to permit more complex logic operations. Each slice
has two of these multiplexers with F5MUX in the bottom por-
tion of the slice and FiMUX in the top portion. The F5MUX
multiplexes the two LUTs in a slice. The FiMUX multiplexes
two CLB inputs which connect directly to the F5MUX and
FiMUX results from the same slice or from other slices. See
Figure 16.
The output of the LUT can connect to the wide multiplexer
logic, the carry and arithmetic logic, or directly to a CLB out-
put or to the CLB storage element. See Figure 15.
Y
D
YQ
G[4:1]
A[4:1]
G-LUT
FFY
X
4
F[4:1]
A[4:1]
F-LUT
D
XQ
FFX
DS312-2_33_022205
Figure 15: LUT Resources in a Slice
FiMUX
FXINA
1
0
FX (Local Feedback to FXIN)
Y (General Interconnect)
YQ
FXINB
BY
D Q
F5MUX
1
LUT
LUT
F[4:1]
G[4:1]
BX
F5 (Local Feedback to FXIN)
X (General Interconnect)
XQ
0
D Q
x312-2_34_021205
Figure 16: Dedicated Multiplexers in Spartan-3E CLB
Depending on the slice, FiMUX takes on the name F6MUX,
F7MUX, or F8MUX. The designation indicates the number
of inputs possible without restriction on the function. For
example, an F7MUX can generate any function of seven
inputs. Figure 17 shows the names of the multiplexers in
each position in the Spartan-3E CLB. The figure also
includes the direct connections within the CLB, along with
the F7MUX connection to the CLB below.
ate any function of five inputs, with four inputs duplicated to
two LUTs and the fifth input controlling the mux. Because
each LUT can implement independent 2:1 muxes, the
F5MUX can combine them to create a 4:1 mux, which is a
six-input function. If the two LUTs have completely indepen-
dent sets of inputs, some functions of all nine inputs can be
implemented. Table 8 shows the connections for each mul-
tiplexer and the number of inputs possible for different types
of functions.
Each mux can create logic functions of more inputs than
indicated by its name. The F5MUX, for example, can gener-
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Functional Description
FXINB
FXINA
F8
F5
X
F5
FXINB
FXINA
FX
F6
F5
F5
FXINB
FXINA
FX
F7
F5
F5
FXINB
FXINA
F6
F5
FX
F5
DS312-2_38_021305
Figure 17: Muxes and Dedicated Feedback in
Spartan-3E CLB
Table 8: Mux Capabilities
Total Number of Inputs per Function
For Any
Function
For Limited
Functions
Mux
Usage
F5MUX
F6MUX
F7MUX
F8MUX
Input Source
LUTs
For Mux
F5MUX
FiMUX
5
6
7
8
6 (4:1 mux)
9
F5MUX
11 (8:1 mux)
20 (16:1 mux)
37 (32:1 mux)
19
39
79
F6MUX
F7MUX
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Functional Description
The wide multiplexers can be used by the automatic tools or
instantiated in a design using a component such as the
F5MUX. The symbol, signals, and function are described
below. The description is similar for the F6MUX, F7MUX,
and F8MUX. Each has versions with a general output, local
output, or both.
Table 10: F5MUX Function
Inputs
Outputs
S
0
0
1
1
I0
1
I1
X
X
1
O
1
0
1
0
LO
1
0
0
I0
I1
S
0
1
LO
O
X
X
1
0
0
DS312-2_35_021205
For more details on using the multiplexers, see XAPP466:
"Using Dedicated Multiplexers in Spartan-3 FPGAs".
Figure 18: F5MUX with Local and General Outputs
Carry and Arithmetic Logic
Table 9: F5MUX Inputs and Outputs
The carry chain, together with various dedicated arithmetic
logic gates, support fast and efficient implementations of
math operations. The carry logic is automatically used for
most arithmetic functions in a design. The gates and multi-
plexers of the carry and arithmetic logic can also be used for
general-purpose logic, including simple wide Boolean func-
tions.
Signal
Function
Input selected when S is Low
Input selected when S is High
Select input
I0
I1
S
LO
Local Output that connects to the F5 or FX CLB
pins, which use local feedback to the FXIN
inputs to the FiMUX for cascading
The carry chain enters the slice as CIN and exits as COUT,
controlled by several multiplexers. The carry chain connects
directly from one CLB to the CLB above. The carry chain
can be initialized at any point from the BX (or BY) inputs.
O
General Output that connects to the
general-purpose combinatorial or registered
outputs of the CLB
The dedicated arithmetic logic includes the exclusive-OR
gates XORF and XORG (upper and lower portions of the
slice, respectively) as well as the AND gates GAND and
FAND (upper and lower portions, respectively). These gates
work in conjunction with the LUTs to implement efficient
arithmetic functions, including counters and multipliers, typ-
ically at two bits per slice. See Figure 19 and Table 11.
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Functional Description
COUT
YB
1
CYMUXG
Y
G[4:1]
A[4:1]
G-LUT
CYSELG
CY0G
G1 G2
YQ
D
FFY
XORG
GAND
1
0
BY
XB
X
1
4
CYMUXF
F[4:1]
A[4:1]
F-LUT
CYSELF
CY0F
F1
F2
XQ
D
FFX
XORF
CYINIT
FAND
1
0
BX
DS312-2_14_021305
CIN
Figure 19: Carry Logic
Table 11: Carry Logic Functions
Function
Description
CYINIT
Initializes carry chain for a slice. Fixed selection of:
• CIN carry input from the slice below
• BX input
CY0F
Carry generation for bottom half of slice. Fixed selection of:
• F1 or F2 inputs to the LUT (both equal 1 when a carry is to be generated)
• FAND gate for multiplication
• BX input for carry initialization
• Fixed "1" or "0" input for use as a simple Boolean function
CY0G
Carry generation for top half of slice. Fixed selection of:
• G1 or G2 inputs to the LUT (both equal 1 when a carry is to be generated)
• GAND gate for multiplication
• BY input for carry initialization
• Fixed "1" or "0" input for use as a simple Boolean function
CYMUXF
Carry generation or propagation mux for bottom half of slice. Dynamic selection via CYSELF of:
• CYINIT carry propagation (CYSELF = 1)
• CY0F carry generation (CYSELF = 0)
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Functional Description
Table 11: Carry Logic Functions (Continued)
Function
Description
CYMUXG Carry generation or propagation mux for top half of slice. Dynamic selection via CYSELF of:
• CYMUXF carry propagation (CYSELG = 1)
• CY0G carry generation (CYSELG = 0)
CYSELF
CYSELG
XORF
Carry generation or propagation select for bottom half of slice. Fixed selection of:
• F-LUT output (typically XOR result)
• Fixed "1" to always propagate
Carry generation or propagation select for top half of slice. Fixed selection of:
• G-LUT output (typically XOR result)
• Fixed "1" to always propagate
Sum generation for bottom half of slice. Inputs from:
• F-LUT
• CYINIT carry signal from previous stage
Result is sent to either the combinatorial or registered output for the top of the slice.
XORG
FAND
GAND
Sum generation for top half of slice. Inputs from:
• G-LUT
• CYMUXF carry signal from previous stage
Result is sent to either the combinatorial or registered output for the top of the slice.
Multiplier partial product for bottom half of slice. Inputs:
• F-LUT F1 input
• F-LUT F2 input
Result is sent through CY0F to become the carry generate signal into CYMUXF
Multiplier partial product for top half of slice. Inputs:
• G-LUT G1 input
• G-LUT G2 input
Result is sent through CY0G to become the carry generate signal into CYMUXG
The basic usage of the carry logic is to generate a half-sum
in the LUT via an XOR function, which generates or propa-
gates a carry out COUT via the carry mux CYMUXF (or
CYMUXG), and then complete the sum with the dedicated
XORF (or XORG) gate and the carry input CIN. This struc-
ture allows two bits of an arithmetic function in each slice.
The CYMUXF (or CYMUXG) can be instantiated using the
MUXCY element, and the XORF (or XORG) can be instan-
tiated using the XORCY element.
The FAND (or GAND) gate is used for partial product multi-
plication and can be instantiated using the MULT_AND
component. Partial products are generated by two-input
AND gates and then added. The carry logic is efficient for
the adder, but one of the inputs must be outside the LUT as
shown in Figure 20. The FAND (or GAND) gate is used to
duplicate one of the partial products, while the LUT gener-
ates both partial products and the XOR function, as shown
in Figure 21.
LUT
COUT
LUT
B
COUT
Am
Bn+1
MUXCY
A
Am+1
Bn
Sum
Pm+1
XORCY
CIN
DS312-2_37_021305
MULT_AND
CIN
DS312-2_39_021305
Figure 20: Using the MUXCY and XORCY in the Carry
Figure 21: Using the MULT_AND for Multiplication in
Logic
Carry Logic
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Functional Description
The MULT_AND is useful for small multipliers. Larger multi-
pliers can be built using the dedicated 18x18 multiplier
blocks (see Dedicated Multipliers).
tom portions of the slice are called FFY and FFX, respec-
tively. FFY has a fixed multiplexer on the D input selecting
either the combinatorial output Y or the bypass signal BY.
FFX selects between the combinatorial output X or the
bypass signal BX.
Storage Elements
The storage element, which is programmable as either a
D-type flip-flop or a level-sensitive transparent latch, pro-
vides a means for synchronizing data to a clock signal,
among other uses. The storage elements in the top and bot-
The functionality of a slice storage element is identical to
that described earlier for the I/O storage elements. All sig-
nals have programmable polarity; the default active-High
function is described.
Table 12: Storage Element Signals
Signal
Description
D
Input. For a flip-flop data on the D input is loaded when R and S (or CLR and PRE) are Low and CE is High
during the Low-to-High clock transition. For a latch, Q reflects the D input while the gate (G) input and gate
enable (GE) are High and R and S (or CLR and PRE) are Low. The data on the D input during the High-to-Low
gate transition is stored in the latch. The data on the Q output of the latch remains unchanged as long as G or
GE remains Low.
Q
Output. Toggles after the Low-to-High clock transition for a flip-flop and immediately for a latch.
Clock for edge-triggered flip-flops.
C
G
Gate for level-sensitive latches.
CE
GE
S
Clock Enable for flip-flops.
Gate Enable for latches.
Synchronous Set (Q = High). When the S input is High and R is Low, the flip-flop is set, output High, during the
Low-to-High clock (C) transition. A latch output is immediately set, output High.
R
Synchronous Reset (Q = Low); has precedence over Set.
PRE
Asynchronous Preset (Q = High). When the PRE input is High and CLR is Low, the flip-flop is set, output High,
during the Low-to-High clock (C) transition. A latch output is immediately set, output High.
CLR
SR
Asynchronous Clear (Q = Low); has precedence over Preset to reset Q output Low
CLB input for R, S, CLR, or PRE
REV
CLB input for opposite of SR. Must be asynchronous or synchronous to match SR.
The control inputs R, S, CE, and C are all shared between
the two flip-flops in a slice.
Table 13: FD Flip-Flop Functionality with Synchronous
Reset, Set, and Clock Enable
Inputs
Outputs
S
R
1
0
0
0
0
S
X
1
0
0
0
CE
X
X
0
D
X
X
X
1
C
↑
↑
X
↑
↑
Q
FDRSE
0
D
CE
C
Q
1
R
No Change
DS312-2_40_021305
1
1
0
Figure 22: FD Flip-Flop Component with Synchronous
Reset, Set, and Clock Enable
1
0
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Functional Description
Initialization
ing a 16x1 configuration in one LUT. Multiple SLICEM LUTs
can be combined in various ways to store larger amounts of
data, including 16x4, 32x2, or 64x1 configurations in one
CLB. The fifth and sixth address lines required for the
32-deep and 64-deep configurations, respectively, are
implemented using the BX and BY inputs, which connect to
the write enable logic for writing and the F5MUX and
F6MUX for reading.
The CLB storage elements are initialized at power-up, dur-
ing configuration, by the global GSR signal, and by the indi-
vidual SR or REV inputs to the CLB.
Table 14: Slice Storage Element Initialization
Signal
Description
SR
Set/Reset input. Forces the storage element
into the state specified by the attribute SRHIGH
or SRLOW. SRHIGH forces a logic “1” when SR
is asserted. SRLOW forces a logic “0”. For each
slice, set and reset can be set to be
Writing to distributed RAM is always synchronous to the
SLICEM clock (WCLK for distributed RAM) and enabled by
the SLICEM SR input which functions as the active-High
Write Enable (WE). The read operation is asynchronous,
and, therefore, during a write, the output initially reflects the
old data at the address being written.
synchronous or asynchronous.
REV
GSR
Reverse of Set/Reset input. A second input
(BY) forces the storage element into the
opposite state. The reset condition is
predominant over the set condition if both are
active. Same synchronous/asynchronous
setting as for SR.
The distributed RAM outputs can be captured using the
flip-flops within the SLICEM element. The WE write-enable
control for the RAM and the CE clock-enable control for the
flip-flop are independent, but the WCLK and CLK clock
inputs are shared. Because the RAM read operation is
asynchronous, the output data always reflects the currently
addressed RAM location.
Global Set/Reset. GSR defaults to active High
but can be inverted by adding an inverter in
front of the GSR input of the
STARTUP_SPARTAN3E element. The initial
state after configuration or GSR is defined by a
separate INIT0 and INIT1 attribute. By default,
setting the SRLOW attribute sets INIT0, and
setting the SRHIGH attribute sets INIT1.
A dual-port option combines two LUTs so that memory
access is possible from two independent data lines. The
same data is written to both 16x1 memories but they have
independent read address lines and outputs. The dual-port
function is implemented by cascading the G-LUT address
lines, which are used for both read and write, to the F-LUT
write address lines (WF[4:1] in Figure 12), and by cascad-
ing the G-LUT data input D1 through the DIF_MUX in
Figure 12 and to the D1 input on the F-LUT. One CLB pro-
vides a 16x1 dual-port memory as shown in Figure 23.
Distributed RAM
The LUTs in the SLICEM can be programmed as distributed
RAM. This type of memory affords moderate amounts of
data buffering anywhere along a data path. One SLICEM
LUT stores 16 bits (RAM16). The four LUT inputs F[4:1] or
G[4:1] become the address lines labeled A[4:1] in the
device model and A[3:0] in the design components, provid-
Any write operation on the D input and any read operation
on the SPO output can occur simultaneously with and inde-
pendently from a read operation on the second read-only
port, DPO.
SLICEM
D
16x1
LUT
RAM
(Read/
Write)
SPO
A[3:0]
Optional
Register
WE
WCLK
DPO
16x1
LUT
RAM
(Read
Only)
DPRA[3:0]
Optional
Register
DS312-2_41_021305
Figure 23: RAM16X1D Dual-Port Usage
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Functional Description
Table 16: Distributed RAM Signals (Continued)
Signal Description
A0, A1, A2, A3 The address inputs select the memory
RAM16X1D
WE
D
WCLK
SPO
DPO
A0
A1
A2
(A4, A5)
cells for read or write. The width of the
port determines the required address
inputs.
A3
DPRA0
DPRA1
DPRA2
DPRA3
D
The data input provides the new data
value to be written into the RAM.
O, SPO, and
DPO
The data output O on single-port RAM
or the SPO and DPO outputs on
DS312-2_42_021305
dual-port RAM reflects the contents of
the memory cells referenced by the
address inputs. Following an active
write clock edge, the data out (O or
SPO) reflects the newly written data.
Figure 24: Dual-Port RAM Component
Table 15: Dual-Port RAM Function
Inputs
WE (mode) WCLK
Outputs
D
X
X
X
D
X
SPO
DPO
The INIT attribute can be used to preload the memory with
data during FPGA configuration. The default initial contents
for RAM is all zeros. If the WE is held Low, the element can
be considered a ROM. The ROM function is possible even
in the SLICEL.
0 (read)
1 (read)
1 (read)
1 (write)
1 (read)
X
0
1
↑
↓
data_a
data_a
data_a
D
data_d
data_d
data_d
data_d
data_d
The global write enable signal, GWE, is asserted automati-
cally at the end of device configuration to enable all writable
elements. The GWE signal guarantees that the initialized
distributed RAM contents are not disturbed during the con-
figuration process.
data_a
Notes:
1. data_a = word addressed by bits A3-A0.
2. data_d = word addressed by bits DPRA3-DPRA0.
The distributed RAM is useful for smaller amounts of mem-
ory. Larger memory requirements can use the dedicated
18Kbit RAM blocks (see Block RAM).
For more information on distributed RAM, see XAPP464:
"Using Look-Up Tables as Distributed RAM in Spartan-3
FPGAs".
Table 16: Distributed RAM Signals
Signal
WCLK
Description
The clock is used for synchronous
writes. The data and the address input
pins have setup times referenced to the
WCLK pin. Active on the positive edge
by default with built-in programmable
polarity.
Shift Registers
It is possible to program each SLICEM LUT as a 16-bit shift
register (see Figure 25). Used in this way, each LUT can
delay serial data anywhere from 1 to 16 clock cycles without
using any of the dedicated flip-flops. The resulting program-
mable delays can be used to balance the timing of data
pipelines.
WE
The enable pin affects the write
functionality of the port. An inactive
Write Enable prevents any writing to
memory cells. An active Write Enable
causes the clock edge to write the data
input signal to the memory location
pointed to by the address inputs. Active
High by default with built-in
The SLICEM LUTs cascade from the G-LUT to the F-LUT
through the DIFMUX (see Figure 12). SHIFTIN and
SHIFTOUT lines cascade a SLICEM to the SLICEM below
to form larger shift registers. The four SLICEM LUTs of a
single CLB can be combined to produce delays up to 64
clock cycles. It is also possible to combine shift registers
across more than one CLB.
programmable polarity.
DS312-2 (v1.1) March 21, 2005
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25
Advance Product Specification
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Functional Description
I
SRLC16
SHIFTIN
SRLC16E
D
CE
Q
Q15
CLK
SHIFT-REG
A0
A1
A2
A3
4
Output
D
A[3:0]
A[3:0]
MC15
Registered
Output
D
Q
DI
WS
DS312-2_43_021305
DI (BY)
(optional)
Figure 26: SRL16 Shift Register Component with
WSG
Cascade and Clock Enable
CE (SR)
CLK
WE
CK
The functionality of the shift register is shown in Table 17.
The SRL16 shifts on the rising edge of the clock input when
the Clock Enable control is High. This shift register cannot
be initialized either during configuration or during operation
except by shifting data into it. The clock enable and clock
inputs are shared between the two LUTs in a SLICEM. The
clock enable input is automatically kept active if unused.
SHIFTOUT
or YB
X465_03_040203
Figure 25: Logic Cell SRL16 Structure
Each shift register provides a shift output MC15 for the last
bit in each LUT, in addition to providing addressable access
to any bit in the shift register through the normal D output.
The address inputs A[3:0] are the same as the distributed
RAM address lines, which come from the LUT inputs F[4:1]
or G[4:1]. At the end of the shift register, the CLB flip-flop
can be used to provide one more shift delay for the addres-
sable bit.
Table 17: SRL16 Shift Register Function
Inputs
Outputs
Am
Am
Am
CLK
CE
0
D
X
D
Q
Q15
Q[15]
Q[15]
X
Q[Am]
↑
1
Q[Am-1]
The shift register element is known as the SRL16 (Shift
Register LUT 16-bit), with a ‘C’ added to signify a cascade
ability (Q15 output) and ‘E’ to indicate a Clock Enable. See
Figure 26 for an example of the SRLC16E component.
Notes:
1. m = 0, 1, 2, 3.
For more information on the SRL16, refer to XAPP465:
"Using Look-Up Tables as Shift Registers (SRL16) in
Spartan-3 FPGAs".
26
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Functional Description
block RAM’s shared connectivity with the multipliers are
located in XAPP463.
Block RAM
Spartan-3E devices incorporate 4 to 36 dedicated block
RAMs, which are organized as dual-port configurable
18 Kbit blocks. Functionally, the block RAM is identical to
the Spartan-3 architecture block RAM. Block RAM synchro-
nously stores large amounts of data while distributed RAM,
previously described, is better suited for buffering small
amounts of data anywhere along signal paths. This section
describes basic block RAM functions. For detailed imple-
mentation information, refer to XAPP463: "Using Block
RAM in Spartan-3 Series FPGAs".
The Internal Structure of the Block RAM
The block RAM has a dual port structure. The two identical
data ports called A and B permit independent access to the
common block RAM, which has a maximum capacity of
18,432 bits, or 16,384 bits with no parity bits (see parity bits
description in Table 19). Each port has its own dedicated
set of data, control, and clock lines for synchronous read
and write operations. There are four basic data paths, as
shown in Figure 27:
Each block RAM is configurable by setting the content’s ini-
tial values, default signal value of the output registers, port
aspect ratios, and write modes. Block RAM can be used in
single-port or dual-port modes.
1. Write to and read from Port A
2. Write to and read from Port B
3. Data transfer from Port A to Port B
4. Data transfer from Port B to Port A
Arrangement of RAM Blocks on Die
The block RAMs are located together with the multipliers on
the die in one or two columns depending on the size of the
device. The XC3S100E has one column of block RAM. The
Spartan-3E devices ranging from the XC3S250E to
XC3S1600E have two columns of block RAM. Table 18
shows the number of RAM blocks, the data storage capac-
ity, and the number of columns for each device. Row(s) of
CLBs are located above and below each block RAM col-
umn.
3
Write
Read
Read
Write
4
Spartan-3E
Dual-Port
Block RAM
Write
Write
2
1
Read
Read
Table 18: Number of RAM Blocks by Device
DS312-2_01_020705
Total
Number of
RAM
Total
Addressable
Locations
(bits)
Figure 27: Block RAM Data Paths
Number
of
Columns
Number of Ports
Device
Blocks
A choice among primitives determines whether the block
RAM functions as dual- or single-port memory. A name of
the form RAMB16_S[wA]_S[wB] calls out the dual-port prim-
itive, where the integers wA and wB specify the total data
path width at ports A and B, respectively. Thus, a
RAMB16_S9_S18 is a dual-port RAM with a 9-bit Port A
and an 18-bit Port B. A name of the form RAMB16_S[w]
identifies the single-port primitive, where the integer w
specifies the total data path width of the lone port A. A
RAMB16_S18 is a single-port RAM with an 18-bit port.
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
4
73,728
221,184
368,640
516,096
663,552
1
2
2
2
2
12
20
28
36
Immediately adjacent to each block RAM is an embedded
18x18 hardware multiplier. The upper 16 bits of the block
RAM's Port A Data input bus are shared with the upper 16
bits of the A multiplicand input bus of the multiplier. Similarly,
the upper 16 bits of Port B's data input bus are shared with
the B multiplicand input bus of the multiplier. Details on the
Port Aspect Ratios
Each port of the block RAM can be configured indepen-
dently to select a number of different possible widths for the
data input (DI) and data output (DO) signals as shown in
Table 19.
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27
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Functional Description
Table 19: Port Aspect Ratios
DIP/DOP
DI/DO Data ParityBus
ADDR
Bus
Width
(r bits)2 [w-p-1:0]
Total Data
Path Width
(w bits)
No. of
Addressable
Locations (n)3
Block RAM
Capacity
(w*n bits)4
Bus Width
(w-p bits)1
Width
DI/DO
DIP/DOP
[p-1:0]
ADDR
[r-1:0]
(p bits)
1
2
1
2
0
0
0
1
2
4
14
13
12
11
10
9
[0:0]
[1:0]
-
[13:0]
[12:0]
[11:0]
[10:0]
[9:0]
16,384
8,192
4,096
2,048
1,024
512
16,384
16,384
16,384
18,432
18,432
18,432
-
4
4
[3:0]
-
9
8
[7:0]
[0:0]
[1:0]
[3:0]
18
36
16
32
[15:0]
[31:0]
[8:0]
Notes:
1. The width of the total data path (w) is the sum of the DI/DO bus width (w-p) and any parity bits (p).
2. The width selection made for the DI/DO bus determines the number of address lines (r) according to the relationship expressed as:
r = 14 – [log(w–p)/log(2)].
3. The number of address lines delimits the total number (n) of addressable locations or depth according to the following equation: n = 2 .
4. The product of w and n yields the total block RAM capacity.
r
If the data bus width of Port A differs from that of Port B, the
block RAM automatically performs a bus-matching function
as described in Figure 28. When data is written to a port
with a narrow bus and then read from a port with a wide bus,
the latter port effectively combines “narrow” words to form
“wide” words. Similarly, when data is written into a port with
a wide bus and then read from a port with a narrow bus, the
latter port divides “wide” words to form “narrow” words. Par-
ity bits are not available if the data port width is configured
as x4, x2, or x1. For example, if a x36 data word (32 data, 4
parity) is addressed as two x18 halfwords (16 data, 2 par-
ity), the parity bits associated with each data byte are
mapped within the block RAM to the appropriate parity bits.
The same effect happens when the x36 data word is
mapped as four x9 words.
28
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Functional Description
Parity
Data
Address
35 34 33 32 31
P3 P2 P1 P0
24 23
16 15
8 7
0
Byte 3
Byte 2
Byte 1
Byte 0
512x36
0
17 16 15
P3 P2
8
7
0
Byte 3
Byte 1
Byte 2
Byte 0
1
0
1Kx18
P1 P0
8
7
0
P3
P2
P1
P0
Byte 3
Byte 2
Byte 1
Byte 0
3
2
1
0
2Kx9
3
2 1 0
7 6 5 4
3 2 1 0
7
6
4Kx4
7 6 5 4
3 2 1 0
1
0
1
0
7 6
5 4
3 2
1 0
F
E
D
C
8Kx2
7 6
5 4
3 2
1 0
3
2
1
0
0
7
6
5
4
1F
1E
1D
1C
16Kx1
3
2
1
0
3
2
1
0
DS312-2_02_020705
Figure 28: Data Organization and Bus-matching Operation with Different Port Widths on Port A and Port B
defined in Table 20. The control signals (WE, EN, CLK, and
SSR) on the block RAM are active High. However, optional
inverters on the control signals change the polarity of the
active edge to active Low.
Block RAM Port Signal Definitions
Representations
of
the
dual-port
primitive
RAMB16_S[wA]_S[wB] and the single-port primitive
RAMB16_S[w] with their associated signals are shown in
Figure 29a and Figure 29b, respectively. These signals are
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Functional Description
RAMB16_wA_wB
WEA
ENA
SSRA
DOPA[pA–1:0]
CLKA
DOA[wA–pA–1:0]
ADDRA[rA–1:0]
DIA[wA–pA–1:0]
DIPA[pA–1:0]
RAMB16_Sw
WEB
ENB
WE
EN
SSRB
SSR
DOPB[pB–1:0]
DOP[p–1:0]
CLKB
CLK
DOB[wB–pB–1:0]
DO[w–p–1:0]
ADDRB[rB–1:0]
DIB[wB–pB–1:0]
DIPB[pB–1:0]
ADDR[r–1:0]
DI[w–p–1:0]
DIP[p–1:0]
(a) Dual-Port
(b) Single-Port
DS312-2_03_021305
Notes:
1.
2.
3.
w and w are integers representing the total data path width (i.e., data bits plus parity bits) at Ports A and B, respectively.
A B
p
and p are integers that indicate the number of data path lines serving as parity bits.
A
B
r
and r are integers representing the address bus width at ports A and B, respectively.
B
A
4. The control signals CLK, WE, EN, and SSR on both ports have the option of inverted polarity.
Figure 29: Block RAM Primitives
Table 20: Block RAM Port Signals
Port A
Signal
Name
Port B
Signal
Name
Signal
Description
Direction
Function
Address Bus
ADDRA
ADDRB
Input
The Address Bus selects a memory location for read or write
operations. The width (w) of the port’s associated data path
determines the number of available address lines (r), as per
Table 18.
Data Input Bus
DIA
DIB
Input
Input
Data at the DI input bus is written to the RAM location specified
by the address input bus (ADDR) during the active edge of the
CLK input, when the clock enable (EN) and write enable (WE)
inputs are active.
It is possible to configure a port’s DI input bus width (w-p) based
on Table 18. This selection applies to both the DI and DO paths
of a given port.
Parity Data
Input(s)
DIPA
DIPB
Parity inputs represent additional bits included in the data input
path. Although referred to herein as “parity” bits, the parity inputs
and outputs have no special functionality for generating or
checking parity and can be used as additional data bits. The
number of parity bits ‘p’ included in the DI (same as for the DO
bus) depends on a port’s total data path width (w). See Table 18.
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Functional Description
Table 20: Block RAM Port Signals (Continued)
Port A
Signal
Name
Port B
Signal
Name
Signal
Description
Direction
Function
Data Output Bus
DOA
DOB
Output
Data is written to the DO output bus from the RAM location
specified by the address input bus, ADDR. See the DI signal
description for DO port width configurations.
Basic data access occurs on the active edge of the CLK when
WE is inactive and EN is active. The DO outputs mirror the data
stored in the address ADDR memory location. Data access with
WE active if the WRITE_MODE attribute is set to the value:
WRITE_FIRST, which accesses data after the write takes place.
READ_FIRST accesses data before the write occurs. A third
attribute, NO_CHANGE, latches the DO outputs upon the
assertion of WE. See Block RAM Data Operations for details on
the WRITE_MODE attribute.
Parity Data
Output(s)
DOPA
WEA
ENA
DOPB
WEB
ENB
Output
Input
Parity outputs represent additional bits included in the data input
path. The number of parity bits ‘p’ included in the DI bus (same
as for the DO bus) depends on a port’s total data path width (w).
See the DIP signal description for configuration details.
Write Enable
Clock Enable
When asserted together with EN, this input enables the writing of
data to the RAM. When WE is inactive with EN asserted, read
operations are still possible. In this case, a latch passes data
from the addressed memory location to the DO outputs.
Input
When asserted, this input enables the CLK signal to perform
read and write operations to the block RAM. When inactive, the
block RAM does not perform any read or write operations.
Set/Reset
Clock
SSRA
CLKA
SSRB
CLKB
Input
Input
When asserted, this pin forces the DO output latch to the value
of the SRVAL attribute. It is synchronized to the CLK signal.
This input accepts the clock signal to which read and write
operations are synchronized. All associated port inputs are
required to meet setup times with respect to the clock signal’s
active edge. The data output bus responds after a clock-to-out
delay referenced to the clock signal’s active edge.
Block RAM Attribute Definitions
A block RAM has a number of attributes that control its
behavior as shown in Table 21.
Table 21: Block RAM Attributes
Function
Attribute
Possible Values
Initial Content for Data Memory, Loaded
during Configuration
INITxx(INIT_00 through Each initialization string defines 32 hex values
INIT3F)
of the 16384-bit data memory of the block RAM.
Initial Content for Parity Memory, Loaded
during Configuration
INITPxx(INITP_00
through INITP0F)
Each initialization string defines 32 hex values
of the 2048-bit parity data memory of the block
RAM.
Data Output Latch Initialization
INIT(single-port)
Hex value the width of the chosen port.
INITA, INITB(dual-port)
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Functional Description
Table 21: Block RAM Attributes (Continued)
Function
Attribute
Possible Values
Data Output Latch Synchronous
Set/Reset Value
SRVAL(single-port)
SRVAL_A, SRVAL_B
(dual-port)
Hex value the width of the chosen port.
Data Output Latch Behavior during Write
WRITE_MODE
WRITE_FIRST, READ_FIRST, NO_CHANGE
(see Block RAM Data Operations)
The waveforms for the write operation are shown in the top
half of Figure 30, Figure 31, and Figure 32. When the WE
and EN signals enable the active edge of CLK, data at the
DI input bus is written to the block RAM location addressed
by the ADDR lines.
Block RAM Data Operations
Writing data to and accessing data from the block RAM are
synchronous operations that take place independently on
each of the two ports. Table 22 describes the data opera-
tions of each port as a result of the block RAM control sig-
nals in their default active-High edges.
Table 22: Block RAM Function Table
Input Signals
Output Signals
RAM Data
Parity
GSR EN SSR WE CLK ADDR
Immediately After Configuration
Loaded During Configuration
DIP
DI
DOP
DO
Data
X
X
INITP_xx
No Chg
No Chg
No Chg
INIT_xx
No Chg
No Chg
No Chg
Global Set/Reset Immediately After Configuration
1
0
0
0
X
0
1
1
X
X
1
1
X
X
0
1
X
X
↑
↑
X
X
X
X
X
INIT
RAM Disabled
No Chg
INIT
X
X
No Chg
Synchronous Set/Reset
SRVAL
X
X
SRVAL
Synchronous Set/Reset During Write RAM
addr
pdata Data
SRVAL
SRVAL
RAM(addr)
RAM(addr)
← pdata
← data
Read RAM, no Write Operation
RAM(pdata)
0
0
1
1
0
0
0
1
↑
↑
addr
X
X
RAM(data)
No Chg
No Chg
Write RAM, Simultaneous Read Operation
addr pdata Data WRITE_MODE = WRITE_FIRST
pdata
RAM(data)
No Chg
data
RAM(addr)
← pdata
RAM(addr)
← data
WRITE_MODE = READ_FIRST
RAM(data)
RAM(addr)
← pdata
RAM(addr)
← pdata
WRITE_MODE = NO_CHANGE
No Chg
RAM(addr)
RAM(addr)
← pdata
← pdata
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Functional Description
There are a number of different conditions under which data
can be accessed at the DO outputs. Basic data access
always occurs when the WE input is inactive. Under this
condition, data stored in the memory location addressed by
the ADDR lines passes through a output latch to the DO
outputs. The timing for basic data access is shown in the
portions of Figure 30, Figure 31, and Figure 32 during
which WE is Low.
Data also can be accessed on the DO outputs when assert-
ing the WE input based on the value of the WRITE_MODE
attribute as described in Table 23.
Table 23: WRITE_MODE Effect on Data Output Latches During Write Operations
Effect on Opposite Port
(dual-port only with same address)
Write Mode
Effect on Same Port
WRITE_FIRST
Read After Write
Data on DI and DIP inputs is written into
specified RAM location and simultaneously
appears on DO and DOP outputs.
Invalidates data on DO and DOP outputs.
READ_FIRST
Read Before Write
Data from specified RAM location appears on
DO and DOP outputs.
Data from specified RAM location appears on
DO and DOP outputs.
Data on DI and DIP inputs is written into
specified location.
NO_CHANGE
No Read on Write
Data on DO and DOP outputs remains
unchanged.
Invalidates data on DO and DOP outputs.
Data on DI and DIP inputs is written into
specified location.
Internal
Memory
DO
Data_in
CLK
Data_out = Data_in
DI
WE
DI
XXXX
aa
1111
bb
2222
cc
XXXX
ADDR
DO
dd
0000
MEM(aa)
1111
2222
MEM(dd)
EN
DISABLED
READ
WRITE
MEM(bb)=1111
WRITE
MEM(cc)=2222
READ
DS312-2_05_020905
Figure 30: Waveforms of Block RAM Data Operations with WRITE_FIRST Selected
Setting the WRITE_MODE attribute to a value of
Setting the WRITE_MODE attribute to a value of
READ_FIRST, data already stored in the addressed loca-
tion passes to the DO outputs before that location is over-
written with new data from the DI inputs on an enabled
active CLK edge. READ_FIRST timing is shown in the por-
tion of Figure 31 during which WE is High.
WRITE_FIRST, data is written to the addressed memory
location on an enabled active CLK edge and is also passed
to the DO outputs. WRITE_FIRST timing is shown in the
portion of Figure 30 during which WE is High.
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Functional Description
Internal
Memory
DO
Data_in
Prior stored data
DI
CLK
WE
DI
XXXX
aa
1111
bb
2222
cc
XXXX
ADDR
DO
dd
0000
MEM(aa)
old MEM(bb)
old MEM(cc)
MEM(dd)
EN
DISABLED
READ
WRITE
MEM(bb)=1111
WRITE
MEM(cc)=2222
READ
DS312-2_06_020905
Figure 31: Waveforms of Block RAM Data Operations with READ_FIRST Selected
Internal
Memory
DO
Data_in
No change during write
DI
CLK
WE
DI
XXXX
aa
1111
bb
2222
cc
XXXX
ADDR
DO
dd
0000
MEM(aa)
MEM(dd)
EN
DISABLED
READ
WRITE
MEM(bb)=1111
WRITE
MEM(cc)=2222
READ
DS312-2_07_020905
Figure 32: Waveforms of Block RAM Data Operations with NO_CHANGE Selected
Setting the WRITE_MODE attribute to a value of
NO_CHANGE, puts the DO outputs in a latched state when
asserting WE. Under this condition, the DO outputs retain
the data driven just before WE is asserted. NO_CHANGE
timing is shown in the portion of Figure 32 during which WE
is High.
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Functional Description
Implement multipliers with inputs less than 18 bits by
sign-extending the inputs (i.e., replicating the most-signifi-
cant bit). Wider multiplication operations are performed by
combining the dedicated multipliers and slice-based logic in
any viable combination or by time-sharing a single multi-
plier. Perform unsigned multiplication by restricting the
inputs to the positive range. Tie the most-significant bit Low
and represent the unsigned value in the remaining 17
lesser-significant bits.
Dedicated Multipliers
The Spartan-3E devices provide 4 to 36 dedicated multiplier
blocks per device. The multipliers are located together with
the block RAM in one or two columns depending on device
density. See Arrangement of RAM Blocks on Die for
details on the location of these blocks and their connectivity.
The multiplier blocks primarily perform two’s complement
numerical multiplication but can also perform some less
obvious applications such as simple data storage and barrel
shifting. Logic slices also implement efficient small multipli-
ers and thereby supplement the dedicated multipliers. The
Spartan-3E dedicated multiplier blocks have additional fea-
tures beyond those provided in Spartan-3 FPGAs.
As shown in Figure 33, each multiplier block has optional
registers on each of the multiplier inputs and the output. The
registers are named AREG, BREG, and PREG and can be
used in any combination. The clock input is common to all
the registers within a block, but each register has an inde-
pendent clock enable and synchronous reset controls mak-
ing them ideal for storing data samples and coefficients.
When used for pipelining, the registers boost the multiplier
clock rate, beneficial for higher performance applications.
Each multiplier performs the principle operation P = A × B,
where ‘A’ and ‘B’ are 18-bit words in two’s complement
form, and ‘P’ is the full-precision 36-bit product, also in two’s
complement form. The 18-bit inputs represent values rang-
ing from -131,07210 to +131,07110 with a resulting product
ranging from -17,179,738,11210 to +17,179,869,18410.
Figure 33 illustrates the principle features of the multiplier
block.
AREG
(Optional)
CEA
CE
D
A[17:0]
Q
PREG
(Optional)
RST
CEP
CE
D
RSTA
Q
P[35:0]
X
BREG
(Optional)
RST
CEB
CE
RSTP
B[17:0]
D
Q
RST
RSTB
CLK
DS312-2_27_021205
Figure 33: Principle Ports and Functions of Dedicated Multiplier Blocks
Use the MULT18X18SIO primitive shown in Figure 34 to
to the MULT18X18SIO multiplier ports and set the individual
AREG, BREG, and PREG attributes to ‘1’ to insert the asso-
ciated register, or to 0 to remove it and make the signal path
combinatorial.
instantiate a multiplier within a design. Although high-level
logic synthesis software usually automatically infers a multi-
plier, adding the pipeline registers usually requires the
MULT18X18SIO primitive. Connect the appropriate signals
DS312-2 (v1.1) March 21, 2005
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Functional Description
The MULT18X18SIO primitive has two additional ports
called BCIN and BCOUT to cascade or share the multi-
plier’s ‘B’ input among several multiplier bocks. The 18-bit
BCIN "cascade" input port offers an alternate input source
from the more typical ‘B’ input. The B_INPUT attribute spec-
ifies whether the specific implementation uses the BCIN or
‘B’ input path. Setting B_INPUT to DIRECT chooses the ‘B’
input. Setting B_INPUT to CASCADE selects the alternate
BCIN input. The BREG register then optionally holds the
selected input value, if required.
MULT18X18SIO
A[17:0]
B[17:0]
CEA
P[35:0]
CEB
CEP
CLK
RSTA
RSTB
RSTP
BCIN[17:0]
BCOUT is an 18-bit output port that always reflects the
value that is applied to the multiplier’s second input, which is
either the ‘B’ input, the cascaded value from the BCIN input,
or the output of the BREG if it is inserted.
BCOUT[17:0]
DS312-2_28_021205
Figure 35 illustrates the four possible configurations using
different settings for the B_INPUT attribute and the BREG
attribute.
Figure 34: MULT18X18SIO Primitive
BCOUT[17:0]
BCOUT[17:0]
BREG
CE
X
X
CEB
D
Q
BREG = 0
CLK
B_INPUT = CASCADE
RST
BREG = 1
B_INPUT = CASCADE
RSTB
BCIN[17:0]
BCIN[17:0]
BCOUT[17:0]
BCOUT[17:0]
BREG
X
X
CEB
CE
D
B[17:0]
B[17:0]
Q
BREG = 0
B_INPUT = DIRECT
CLK
RST
BREG = 1
B_INPUT = DIRECT
RSTB
DS312-2_29_021505
Figure 35: Four Configurations of the B Input
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Functional Description
The BCIN and BCOUT ports have associated dedicated
routing that connects adjacent multipliers within the same
column. Via the cascade connection, the BCOUT port of
one multiplier block drives the BCIN port of the multiplier
block directly above it. There is no connection to the BCIN
port of the bottom-most multiplier block in a column or a
connection from the BCOUT port of the top-most block in a
column. As an example, Figure 36 shows the multiplier cas-
cade capability within the XC3S100E FPGA, which has a
single column of multiplier, four blocks tall. For clarity, the
figure omits the register control inputs.
BCOUT
P
A
B
B_INPUT = CASCADE
B_INPUT = CASCADE
B_INPUT = CASCADE
B_INPUT = DIRECT
BCIN
BCOUT
P
A
B
BCIN
BCOUT
P
A
B
BCIN
BCOUT
P
A
B
BCIN
DS312-2_30_021505
Figure 36: Multiplier Cascade Connection
When using the BREG register, the cascade connection
forms a shift register structure typically used in DSP algo-
rithms such as direct-form FIR filters. When the BREG reg-
ister is omitted, the cascade structure essentially feeds the
same input value to more than one multiplier. This parallel
connection serves to create wide-input multipliers, imple-
ment transpose FIR filters, and is used in any application
that requires that several multipliers have the same input
value.
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Functional Description
Table 24 defines each port of the MULT18X18SIO primitive.
Table 24: MULT18X18SIO Embedded Multiplier Primitives Description
Signal Name
A[17:0]
Direction
Input
Function
The primary 18-bit two’s complement value for multiplication. The block multiplies by
this value asynchronously if the optional AREG and PREG registers are omitted.
When AREG and/or PREG are used, the value provided on this port is qualified by
the rising edge of CLK, subject to the appropriate register controls.
B[17:0]
Input
The second 18-bit two’s complement value for multiplication if the B_INPUT attribute
is set to DIRECT. The block multiplies by this value asynchronously if the optional
BREG and PREG registers are omitted. When BREG and/or PREG are used, the
value provided on this port is qualified by the rising edge of CLK, subject to the
appropriate register controls.
BCIN[17:0]
P[35:0]
Input
The second 18-bit two’s complement value for multiplication if the B_INPUT attribute
is set to CASCADE. The block multiplies by this value asynchronously if the optional
BREG and PREG registers are omitted. When BREG and/or PREG are used, the
value provided on this port is qualified by the rising edge of CLK, subject to the
appropriate register controls.
Output
The 36-bit two’s complement product resulting from the multiplication of the two input
values applied to the multiplier. If the optional AREG, BREG and PREG registers are
omitted, the output operates asynchronously. Use of PREG causes this output to
respond to the rising edge of CLK with the value qualified by CEP and RSTP. If PREG
is omitted, but AREG and BREG are used, this output responds to the rising edge of
CLK with the value qualified by CEA, RSTA, CEB, and RSTB. If PREG is omitted and
only one of AREG or BREG is used, this output responds to both asynchronous and
synchronous events.
BCOUT[17:0]
Output
Input
The value being applied to the second input of the multiplier. When the optional
BREG register is omitted, this output responds asynchronously in response to
changes at the B[17:0] or BCIN[17:0] ports according to the setting of the B_INPUT
attribute. If BREG is used, this output responds to the rising edge of CLK with the
value qualified by CEB and RSTB.
CEA
Clock enable qualifier for the optional AREG register. The value provided on the
A[17:0] port is captured by AREG in response to a rising edge of CLK when this
signal is High, provided that RSTA is Low.
RSTA
CEB
Input
Input
Synchronous reset for the optional AREG register. AREG content is forced to the
value zero in response to a rising edge of CLK when this signal is High.
Clock enable qualifier for the optional BREG register. The value provided on the
B[17:0] or BCIN[17:0] port is captured by BREG in response to a rising edge of CLK
when this signal is High, provided that RSTB is Low.
RSTB
CEP
Input
Input
Synchronous reset for the optional BREG register. BREG content is forced to the
value zero in response to a rising edge of CLK when this signal is High.
Clock enable qualifier for the optional PREG register. The value provided on the
output of the multiplier port is captured by PREG in response to a rising edge of CLK
when this signal is High, provided that RSTP is Low.
RSTP
Input
Synchronous reset for the optional PREG register. PREG content is forced to the
value zero in response to a rising edge of CLK when this signal is High.
Notes:
1. The control signals CLK, CEA, RSTA, CEB, RSTB, CEP, and RSTP have the option of inverted polarity.
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Functional Description
The DCM supports three major functions:
Digital Clock Managers (DCMs)
•
Clock-skew Elimination: Clock skew describes the
Differences from the Spartan-3 Architecture
extent to which clock signals may, under normal
circumstances, deviate from zero-phase alignment. It
occurs when slight differences in path delays cause the
clock signal to arrive at different points on the die at
different times. This clock skew can increase set-up
and hold time requirements as well as clock-to-out
time, which may be undesirable in applications
operating at a high frequency, when timing is critical.
The DCM eliminates clock skew by aligning the output
clock signal it generates with another version of the
clock signal that is fed back. As a result, the two clock
signals establish a zero-phase relationship. This
effectively cancels out clock distribution delays that
might lie in the signal path leading from the clock
•
•
•
Spartan-3E FPGAs have two, four, or eight DCMs,
depending on device size.
The Spartan-3E DCM has a maximum phase shift
range of 180°. The Spartan-3 DCM range is 360°.
The Spartan-3E DLL supports lower input frequencies,
down to 5 MHz. Spartan-3 DLLs supports down to 24
MHz.
Overview
Spartan-3E Digital Clock Managers (DCMs) provide flexi-
ble, complete control over clock frequency, phase shift and
skew. To accomplish this, the DCM employs a Delay-Locked
Loop (DLL), a fully digital control system that uses feedback
to maintain clock signal characteristics with a high degree of
precision despite normal variations in operating tempera-
ture and voltage. This section provides a fundamental
description of the DCM. See XAPP462: "Using Digital Clock
Managers (DCMs) in Spartan-3 Series FPGAs" for further
information.
output of the DCM to its feedback input.
•
•
Frequency Synthesis: Provided with an input signal,
the DCM can generate a wide range of different output
clock frequencies. This is accomplished by either
multiplying and/or dividing the frequency of the input
clock signal by any of several different factors.
Phase Shifting: The DCM provides the ability to shift
the phase of all its output clock signals with respect to
its input clock signal.
The XC3S100E FPGA has two DCMs, one at the top and
one at the bottom of the device. The XC3S250E and
XC3S500E FPGAs each include four DCMs, two at the top
and two at the bottom. The XC3S1200E and XC3S1600E
FPGAs contain eight DCMs with two on each edge (see
also Figure 42). The DCM in Spartan-3E FPGAs is sur-
rounded by CLBs within the logic array and is no longer
located at the top and bottom of a column of block RAM as
in the Spartan-3 architecture,. The Digital Clock Manager is
instantiated into a design as the “DCM” primitive.
The DCM has four functional components: the
Delay-Locked Loop (DLL), the Digital Frequency Synthe-
sizer (DFS), the Phase Shifter (PS), and the Status Logic.
Each component has its associated signals, as shown in
Figure 37.
DCM
PSINCDEC
Phase
Shifter
PSEN
PSCLK
PSDONE
Clock
CLK0
Distribution
CLKIN
CLKFB
CLK90
Delay
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
CLKFX
DFS
DLL
CLKFX180
LOCKED
Status
Logic
RST
8
STATUS [7:0]
DS099-2_07_040103
Figure 37: DCM Functional Blocks and Associated Signals
DS312-2 (v1.1) March 21, 2005
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Functional Description
CLK0
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
Delay
1
Delay
2
Delay
n-1
Delay
n
CLKIN
Control
LOCKED
Phase
Detection
CLKFB
RST
DS099-2_08_041103
Figure 38: Simplified Functional Diagram of DLL
Table 25: DLL Signals
Signal
CLKIN
Direction
Input
Description
Accepts original clock signal.
CLKFB
Input
Accepts either CLK0 or CLK2X as the feedback signal. (Set CLK_FEEDBACK attribute
accordingly).
CLK0
Output
Output
Output
Output
Output
Output
Generates a clock signal with same frequency and phase as CLKIN.
CLK90
Generates a clock signal with same frequency as CLKIN, only phase-shifted 90°.
Generates a clock signal with same frequency as CLKIN, only phase-shifted 180°.
Generates a clock signal with same frequency as CLKIN, only phase-shifted 270°.
Generates a clock signal with same phase as CLKIN, only twice the frequency.
CLK180
CLK270
CLK2X
CLK2X180
Generates a clock signal with twice the frequency of CLKIN, phase-shifted 180° with
respect to CLKIN.
CLKDV
Output
Divides the CLKIN frequency by CLKDV_DIVIDE value to generate lower frequency
clock signal that is phase-aligned to CLKIN.
neously. Signals that initialize and report the state of the
DLL are discussed in the Status Logic Component section.
Delay-Locked Loop (DLL)
The most basic function of the DLL component is to elimi-
nate clock skew. The main signal path of the DLL consists of
an input stage, followed by a series of discrete delay ele-
ments or taps, which in turn leads to an output stage. This
path together with logic for phase detection and control
forms a system complete with feedback as shown in
Figure 38. In Spartan-3E FPGAs, the DLL is implemented
using a counter-based delay line.
The clock signal supplied to the CLKIN input serves as a
reference waveform. The DLL seeks to align the rising-edge
of feedback signal at the CLKFB input with the rising-edge
of CLKIN input. When eliminating clock skew, the common
approach to using the DLL is as follows: The CLK0 signal is
passed through the clock distribution network to all the reg-
isters it synchronizes. These registers are either internal or
external to the FPGA. After passing through the clock distri-
bution network, the clock signal returns to the DLL via a
feedback line called CLKFB. The control block inside the
DLL measures the phase error between CLKFB and CLKIN.
The DLL component has two clock inputs, CLKIN and
CLKFB, as well as seven clock outputs, CLK0, CLK90,
CLK180, CLK270, CLK2X, CLK2X180, and CLKDV as
described in Table 25. The clock outputs drive simulta-
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Functional Description
This phase error is a measure of the clock skew that the
clock distribution network introduces. The control block acti-
vates the appropriate number of delay elements to cancel
out the clock skew. Once the DLL has brought the CLK0 sig-
nal in phase with the CLKIN signal, it asserts the LOCKED
output, indicating a lock on to the CLKIN signal.
DLL Attributes and Related Functions
A number of different functional options can be set for the
DLL component through the use of the attributes described
in Table 26. Each attribute is described in detail in the sec-
tions that follow:
Table 26: DLL Attributes
Attribute
CLK_FEEDBACK
Description
Chooses either the CLK0 or CLK2X output to NONE, 1X, 2X
Values
drive the CLKFB input
CLKIN_DIVIDE_BY_2
CLKDV_DIVIDE
Halves the frequency of the CLKIN signal just TRUE, FALSE
as it enters the DCM
Selects the constant used to divide the CLKIN 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6.0,
input frequency to generate the CLKDV
output frequency
6.5, 7.0, 7.5, 8, 9, 10, 11, 12, 13, 14,
15, and 16
DUTY_CYCLE_CORRECTION Enables 50% duty cycle correction for the
CLK0, CLK90, CLK180, and CLK270 outputs
TRUE, FALSE
The feedback loop is essential for DLL operation and is
established by driving the CLKFB input with either the CLK0
or the CLK2X signal so that any undesirable clock distribu-
tion delay is included in the loop. It is possible to use either
of these two signals for synchronizing any of the seven DLL
outputs: CLK0, CLK90, CLK180, CLK270, CLKDV, CLK2X,
or CLK2X180. The value assigned to the CLK_FEEDBACK
attribute must agree with the physical feedback connection:
a value of 1X for the CLK0 case, 2X for the CLK2X case. If
the DCM is used in an application that does not require the
DLL — that is, only the DFS is used — then there is no
required feedback loop so CLK_FEEDBACK is set to
NONE.
DLL Clock Input Connections
An external clock source enters the FPGA using a Global
Clock Input Buffer (IBUFG), which directly accesses the glo-
bal clock network or via an Input Buffer (IBUF). Clock sig-
nals within the FPGA drive a global clock net using a Global
Clock Multiplexer Buffer (BUFGMUX). The global clock net
connects directly to the CLKIN input. The internal and exter-
nal connections are shown in Figure 39a and Figure 39c,
respectively. A differential clock (e.g., LVDS) can serve as
an input to CLKIN.
DLL Clock Output and Feedback Connections
As many as four of the nine DCM clock outputs can simulta-
neously drive four of the BUFGMUX buffers on the same die
edge. All DCM clock outputs can simultaneously drive gen-
eral routing resources, including interconnect leading to
OBUF buffers.
There are two basic cases that determine how to connect
the DLL clock outputs and feedback connections: on-chip
synchronization and off-chip synchronization, which are
illustrated in Figure 39a through Figure 39d.
DS312-2 (v1.1) March 21, 2005
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Functional Description
FPGA
FPGA
BUFGMUX
BUFGMUX
CLK0
CLK90
CLK180
CLK270
CLKDV
CLK90
CLK180
CLK270
CLKDV
CLK2X
CLK2X180
BUFG
CLKIN
BUFG
CLKIN
Clock
Net Delay
Clock
Net Delay
DCM
DCM
CLK2X180
CLK2X
CLKFB
CLKFB
CLK0
BUFGMUX
BUFGMUX
CLK0
CLK2X
(a) On-Chip with CLK0 Feedback
FPGA
(b) On-Chip with CLK2X Feedback
FPGA
OBUF
CLK0
CLK90
CLK180
CLK270
CLKDV
CLK90
CLK180
CLK270
CLKDV
CLK2X
CLK2X180
OBUF
IBUFG
IBUFG
CLKIN
CLKIN
Clock
Net Delay
Clock
Net Delay
DCM
DCM
CLK2X180
CLKFB
CLK0
CLKFB
CLK2X
OBUF
IBUFG
IBUFG
OBUF
CLK0
CLK2X
(c) Off-Chip with CLK0 Feedback
(d) Off-Chip with CLK2X Feedback
DS099-2_09_082104
Figure 39: Input Clock, Output Clock, and Feedback Connections for the DLL
In the on-chip synchronization case in Figure 39a and
Figure 39b, it is possible to connect any of the DLL’s seven
output clock signals through general routing resources to
the FPGA’s internal registers. Either a Global Clock Buffer
(BUFG) or a BUFGMUX affords access to the global clock
network. As shown in Figure 39a, the feedback loop is cre-
ated by routing CLK0 (or CLK2X, in Figure 39b to a global
clock net, which in turn drives the CLKFB input.
Coarse Phase Shift Outputs of the DLL Compo-
nent
In addition to CLK0 for zero-phase alignment to the CLKIN
signal, the DLL also provides the CLK90, CLK180, and
CLK270 outputs for 90°, 180°, and 270° phase-shifted sig-
nals, respectively. These signals are described in Table 25.
Their relative timing is shown in Figure 40. For control in
finer increments than 90°, see Phase Shifter (PS).
In the off-chip synchronization case in Figure 39c and
Figure 39d, CLK0 (or CLK2X) plus any of the DLL’s other
output clock signals exit the FPGA using output buffers
(OBUF) to drive an external clock network plus registers on
the board. As shown in Figure 39c, the feedback loop is
formed by feeding CLK0 (or CLK2X, in Figure 39d) back
into the FPGA using an IBUFG, which directly accesses the
global clock network, or an IBUF. Then, the global clock net
is connected directly to the CLKFB input.
Basic Frequency Synthesis Outputs of the DLL
Component
The DLL component provides basic options for frequency
multiplication and division in addition to the more flexible
synthesis capability of the DFS component, described in a
later section. These operations result in output clock signals
with frequencies that are either a fraction (for division) or a
multiple (for multiplication) of the incoming clock frequency.
The CLK2X output produces an in-phase signal that is twice
the frequency of CLKIN. The CLK2X180 output also dou-
bles the frequency, but is 180° out-of-phase with respect to
CLKIN. The CLKDIV output generates a clock frequency
that is a predetermined fraction of the CLKIN frequency.
The CLKDV_DIVIDE attribute determines the factor used to
divide the CLKIN frequency. The attribute can be set to var-
Accommodating High Input Frequencies
If the frequency of the CLKIN signal is high such that it
exceeds the maximum permitted, divide it down to an
acceptable value using the CLKIN_DIVIDE_BY_2 attribute.
When this attribute is set to TRUE, the CLKIN frequency is
divided by a factor of two just as it enters the DCM.
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Functional Description
ious values as described in Table 26. The basic frequency
synthesis outputs are described in Table 25.
2. The fCLKFX frequency calculated from the above
expression accords with the DCM’s operating frequency
specifications.
Duty Cycle Correction of DLL Clock Outputs
For example, if CLKFX_MULTIPLY = 5 and CLKFX_DIVIDE
= 3, then the frequency of the output clock signal is 5/3 that
of the input clock signal.
The CLK2X(1), CLK2X180, and CLKDV(2) output signals
ordinarily exhibit a 50% duty cycle – even if the incoming
CLKIN signal has a different duty cycle. Fifty-percent duty
cycle means that the High and Low times of each clock
cycle are equal. The DUTY_CYCLE_CORRECTION
attribute determines whether or not duty cycle correction is
applied to the CLK0, CLK90, CLK180, and CLK270 outputs.
If DUTY_CYCLE_CORRECTION is set to TRUE, then the
duty cycle of these four outputs is corrected to 50%. If
DUTY_CYCLE_CORRECTION is set to FALSE, then these
outputs exhibit the same duty cycle as the CLKIN signal.
Figure 40 compares the characteristics of the DLL’s output
signals to those of the CLKIN signal.
0o 90o 180o 270o 0o 90o 180o 270o 0o
Phase:
Input Signal (30% Duty Cycle)
t
CLKIN
Output Signal - Duty Cycle is Always Corrected
The CLK2X output generates a 25% duty cycle clock at the
same frequency as the CLKIN signal until the DLL has
achieved lock.
CLK2X
The duty cycle of the CLKDV outputs may differ somewhat
from 50% (i.e., the signal is High for less than 50% of the
period) when the CLKDV_DIVIDE attribute is set to a
non-integer value and the DLL is operating in the High Fre-
quency mode.
CLK2X180
(1)
CLKDV
Output Signal - Attribute Corrects Duty Cycle
Digital Frequency Synthesizer (DFS)
DUTY_CYCLE_CORRECTION = FALSE
The DFS component generates clock signals the frequency
of which is a product of the clock frequency at the CLKIN
input and a ratio of two user-determined integers. Because
of the wide range of possible output frequencies such a ratio
permits, the DFS feature provides still further flexibility than
the DLL’s basic synthesis options as described in the pre-
ceding section. The DFS component’s two dedicated out-
puts, CLKFX and CLKFX180, are defined in Table 28.
CLK0
CLK90
CLK180
CLK270
The signal at the CLKFX180 output is essentially an inver-
sion of the CLKFX signal. These two outputs always exhibit
a 50% duty cycle. This is true even when the CLKIN signal
does not. These DFS clock outputs are driven at the same
time as the DLL’s seven clock outputs.
DUTY_CYCLE_CORRECTION = TRUE
CLK0
The numerator of the ratio is the integer value assigned to
the attribute CLKFX_MULTIPLY and the denominator is the
integer value assigned to the attribute CLKFX_DIVIDE.
These attributes are described in Table 27.
CLK90
CLK180
The output frequency (fCLKFX) can be expressed as a func-
tion of the incoming clock frequency (fCLKIN) as follows:
CLK270
fCLKFX = fCLKIN*(CLKFX_MULTIPLY/CLKFX_DIVIDE) (3)
DS099-2_10_031303
Regarding the two attributes, it is possible to assign any
combination of integer values, provided that two conditions
are met:
Figure 40: Characteristics of the DLL Clock Outputs
DFS With or Without the DLL
1. The two values fall within their corresponding ranges,
as specified in Table 27.
The DFS component can be used with or without the DLL
component: Without the DLL, the DFS component multi-
plies or divides the CLKIN signal frequency according to the
respective CLKFX_MULTIPLY and CLKFX_DIVIDE values,
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Functional Description
generating a clock with the new target frequency on the
CLKFX and CLKFX180 outputs. Though classified as
belonging to the DLL component, the CLKIN input is shared
with the DFS component. This case does not employ feed-
back loop. Therefore, it cannot correct for clock distribution
delay.
DFS Clock Output Connections
There are two basic cases that determine how to connect
the DFS clock outputs: on-chip and off-chip, which are illus-
trated in Figure 39a and Figure 39c, respectively. This is
similar to what has already been described for the DLL com-
ponent. See DLL Clock Output and Feedback Connec-
tions.
With the DLL, the DFS operates as described in the preced-
ing case, only with the additional benefit of eliminating the
clock distribution delay. In this case, a feedback loop from
the CLK0 output to the CLKFB input must be present.
In the on-chip case, it is possible to connect either of the
DFS’s two output clock signals through general routing
resources to the FPGA’s internal registers. Either a Global
Clock Buffer (BUFG) or a BUFGMUX affords access to the
global clock network. The optional feedback loop is formed
in this way, routing CLK0 to a global clock net, which in turn
drives the CLKFB input.
The DLL and DFS components work together to achieve
this phase correction as follows: Given values for the
CLKFX_MULTIPLY and CLKFX_DIVIDE attributes, the DLL
selects the delay element for which the output clock edge
coincides with the input clock edge whenever mathemati-
cally possible. For example, when CLKFX_MULTIPLY = 5
and CLKFX_DIVIDE = 3, the input and output clock edges
coincide every three input periods, which is equivalent in
time to five output periods.
In the off-chip case, the DFS’s two output clock signals, plus
CLK0 for an optional feedback loop, can exit the FPGA
using output buffers (OBUF) to drive a clock network plus
registers on the board. The feedback loop is formed by
feeding the CLK0 signal back into the FPGA using an
IBUFG, which directly accesses the global clock network, or
an IBUF. Then the global clock net is connected directly to
the CLKFB input.
Smaller CLKFX_MULTIPLY and CLKFX_DIVIDE values
achieve faster lock times. With no factors common to the
two attributes, alignment occurs once with every number of
cycles equal to the CLKFX_DIVIDE value. Therefore, it is
recommended that the user reduce these values by factor-
Phase Shifter (PS)
ing
wherever
possible.
For
example,
given
The DCM provides two approaches to controlling the phase
of a DCM clock output signal relative to the CLKIN signal:
First, there are nine clock outputs that employ the DLL to
achieve a desired phase relationship: CLK0, CLK90,
CLK180, CLK270, CLK2X, CLK2X180, CLKDV CLKFX, and
CLKFX180. These outputs afford “coarse” phase control.
CLKFX_MULTIPLY = 9 and CLKFX_DIVIDE = 6, removing
a factor of three yields CLKFX_MULTIPLY = 3 and
CLKFX_DIVIDE = 2. While both value-pairs result in the
multiplication of clock frequency by 3/2, the latter value-pair
enables the DLL to lock more quickly.
The second approach uses the PS component described in
this section to provide a still finer degree of control. The PS
component accomplishes this by introducing a "fine phase
shift" (TPS) between the CLKFB and CLKIN signals inside
the DLL component. The user can control this fine phase
shift down to a resolution of 1/512 of a CLKIN cycle or one
tap delay (DCM_TAP), whichever is greater. When in use,
the PS component shifts the phase of all nine DCM clock
output signals together. If the PS component is used
together with a DCM clock output such as the CLK90,
CLK180, CLK270, CLK2X180, and CLKFX180, then the
fine phase shift of the former gets added to the coarse
phase shift of the latter.
Table 27: DFS Attributes
Attribute
Description
Values
CLKFX_MULTIPLY
Frequency
Integer from
2 to 32,
inclusive
multiplier
constant
CLKFX_DIVIDE
Frequency divisor Integer from
constant
1 to 32,
inclusive
Table 28: DFS Signals
Signal
Direction Description
PS Component Enabling and Mode Selection
CLKFX
Output
Multiplies the CLKIN frequency
by the attribute-value ratio
(CLKFX_MULTIPLY/
CLKFX_DIVIDE) to generate a
clock signal with a new target
frequency.
The CLKOUT_PHASE_SHIFT attribute enables the PS
component for use in addition to selecting between two
operating modes. As described in Table 29, this attribute
has three possible values: NONE, FIXED, and VARIABLE.
When CLKOUT_PHASE_SHIFT is set to NONE, the PS
component is disabled and its inputs, PSEN, PSCLK, and
PSINCDEC, must be tied to GND. The set of waveforms in
Figure 41a shows the disabled case, where the DLL main-
tains a zero-phase alignment of signals CLKFB and CLKIN
upon which the PS component has no effect. The PS com-
CLKFX180 Output
Generates a clock signal with
same frequency as CLKFX,
only shifted 180° out-of-phase.
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ponent is enabled by setting the attribute to either the
FIXED or VARIABLE values, which select the Fixed Phase
mode and the Variable Phase mode, respectively. These
two modes are described in the sections that follow.
Table 29: PS Attributes
Attribute
Description
Disables the PS component or chooses between
Values
CLKOUT_PHASE_SHIFT
NONE, FIXED, VARIABLE
Fixed Phase and Variable Phase modes.
PHASE_SHIFT
Determines size and direction of initial fine phase
shift.
Integers from –255 to +255
Determining the Fine Phase Shift
The Fixed Phase Mode
The user controls the phase shift of CLKFB relative to
CLKIN by setting and/or adjusting the value of the
PHASE_SHIFT attribute. This value must be an integer
ranging from –255 to +255. This corresponds to a phase
shift range of –180 to +180 degrees, which is different from
the original Spartan-3 DCM. The PS component uses this
value to calculate the desired fine phase shift (TPS) as a
fraction of the CLKIN period (TCLKIN). Given values for
PHASE_SHIFT and TCLKIN, it is possible to calculate TPS
as follows:
This mode fixes the desired fine phase shift to a fraction of
the TCLKIN, as determined by Equation (4) and its
user-selected PHASE_SHIFT value P. The set of wave-
forms in Figure 41b illustrates the relationship between
CLKFB and CLKIN in the Fixed Phase mode. In the Fixed
Phase mode, the PSEN, PSCLK, and PSINCDEC inputs
are not used and must be tied to GND.
In Figure 41:
•
P represents the integer value ranging from –255 to
+255 to which the PHASE_SHIFT attribute is assigned.
(P = approximately -90 as shown)
TPS = (PHASE_SHIFT/512) * TCLKIN (4)
Both the Fixed Phase and Variable Phase operating modes
employ this calculation. If the PHASE_SHIFT value is zero,
then CLKFB and CLKIN are in phase, the same as when the
PS component is disabled. When the PHASE_SHIFT value
is positive, the CLKFB signal is shifted later in time with
respect to CLKIN. If the attribute value is negative, the
CLKFB signal is shifted earlier in time with respect to
CLKIN.
•
N is an integer value ranging from (P – 255) to
(+255 – P) that represents the net phase shift effect
from a series of increment and/or decrement
operations.
•
N = {Total number of increments} – {Total number of
decrements} provided the user does not try to
increment past + 255 or decrement past -255. A
positive value for N indicates a net increment; a
negative value indicates a net decrement.
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Functional Description
a. CLKOUT_PHASE_SHIFT = NONE
CLKIN
CLKFB
b. CLKOUT_PHASE_SHIFT = FIXED
CLKIN
0
–255
+255
Shift Range over all P Values:
CLKFB
P
512
* T
CLKIN
c. CLKOUT_PHASE_SHIFT = VARIABLE
CLKIN
–255
+255
0
Shift Range over all P Values:
P
512
* T
CLKIN
CLKFB before
Increment
Shift Range over all N Values:
N
512
* T
CLKIN
CLKFB after
Increment
DS312-2_61_021505
Figure 41: Phase Shifter Waveforms
nent (PSEN, PSCLK, and PSINCDEC), as defined in
Table 30.
The Variable Phase Mode
The Variable Phase mode dynamically adjusts the fine
phase shift over time using three inputs to the PS compo-
Table 30: Signals for Variable Phase Mode
Signal
PSEN(1)
Direction
Input
Description
Enables PSCLK for variable phase adjustment.
PSCLK(1)
Input
Input
Clock to synchronize phase shift adjustment.
PSINCDEC(1)
Chooses between increment and decrement for phase adjustment. It is
synchronized to the PSCLK signal.
PSDONE
Output
Goes High to indicate that present phase adjustment is complete and PS component
is ready for next phase adjustment request. It is synchronized to the PSCLK signal.
Notes:
1. It is possible to program this input for either a true or inverted polarity.
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Functional Description
Just following device configuration, the PS component ini-
tially determines TPS by evaluating Equation (4) for the
value assigned to the PHASE_SHIFT attribute. Then to
dynamically adjust that phase shift, use the three PS inputs
to increase or decrease the fine phase shift.
Asserting the Reset (RST) input, returns TPS to its original
shift time, as determined by the PHASE_SHIFT attribute
value. The set of waveforms in Figure 41c illustrates the
relationship between CLKFB and CLKIN in the Variable
Phase mode.
PSINCDEC is synchronized to the PSCLK clock signal,
which is enabled by asserting PSEN. It is possible to drive
the PSCLK input with the CLKIN signal or any other clock
signal. A request for phase adjustment is entered as follows:
For each PSCLK cycle that PSINCDEC is High, the PS
component adds 1/512 of a CLKIN cycle to TPS. Similarly,
for each enabled PSCLK cycle that PSINCDEC is Low, the
The Status Logic Component
The Status Logic component not only reports on the state of
the DCM but also provides a means of resetting the DCM to
an initial known state. The signals associated with the Sta-
tus Logic component are described in Table 31.
As a rule, the Reset (RST) input is asserted only upon con-
figuring the device or changing the CLKIN frequency. A
DCM reset does not affect attribute values (e.g.,
CLKFX_MULTIPLY and CLKFX_DIVIDE). If not used, tie
RST to GND.
PS component subtracts 1/512 of a CLKIN cycle from TPS
.
The phase adjustment may require as many as 100 CLKIN
cycles plus three PSCLK cycles to take effect, at which
point the output PSDONE goes High for one PSCLK cycle.
This pulse indicates that the PS component has finished the
present adjustment and is now ready for the next request.
The eight bits of the STATUS bus are defined in Table 32.
Table 31: Status Logic Signals
Signal
Direction
Input
Description
RST
A High resets the entire DCM to its initial power-on state. Initializes the DLL taps for
a delay of zero. Sets the LOCKED output Low. This input is asynchronous.
STATUS[7:0]
LOCKED
Output
Output
The bit values on the STATUS bus provide information regarding the state of DLL and
PS operation
Indicates that the CLKIN and CLKFB signals are in phase by going High. The two
signals are out-of-phase when Low.
Table 32: DCM Status Bus
Bit
0
Name
Reserved
CLKIN Stopped
Description
-
1
A value of 1 indicates that the CLKIN input signal is not toggling. A value of 0 indicates toggling.
This bit functions only when the CLKFB input is connected.(1)
2
CLKFX Stopped A value of 1 indicates that the CLKFX output is not toggling. A value of 0 indicates toggling.
This bit functions only when the CLKFX or CLKFX180 output are connected.
3-6 Reserved
-
Notes:
1. If only the DFS clock outputs are used, but none of the DLL clock outputs, this bit does not go High when the CLKIN signal stops.
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Functional Description
Stabilizing DCM Clocks Before User Mode
Clock Buffers/Multiplexers
The STARTUP_WAIT attribute shown in Table 33 optionally
delays the end of the FPGA’s configuration process until
after the DCM locks to the incoming clock frequency. This
option ensures that the FPGA remains in the Startup phase
of configuration until all clock outputs generated by the
DCM are stable. When all the DCMs with their
STARTUP_WAIT attribute set to TRUE assert the LOCKED
signal, then the FPGA completes its configuration process
and proceeds to user mode. The associated bitstream gen-
erator (BitGen) option LCK_cycle specifies one of the six
cycles in the Startup phase. The selected cycle defines the
point at which configuration halts until the all the LOCKED
outputs go High. Also see Start-Up, page 91.
Clock Buffers/Multiplexers either drive clock input signals
directly onto a clock line (BUFG) or optionally provide a mul-
tiplexer to switch between two unrelated, possibly asynchro-
nous clock signals (BUFGMUX).
Each BUFGMUX element, shown in Figure 43, is a 2-to-1
multiplexer. The select line, S, chooses which of the two
inputs, I0 or I1, drives the BUFGMUX’s output signal, O, as
described in Table 34. The switching from one clock to the
other is glitch-less, and done in such a way that the output
High and Low times are never shorter than the shortest
High or Low time of either input clock.
Table 34: BUFGMUX Select Mechanism
Table 33: STARTUP_WAIT Attribute
S Input
O Output
I0 Input
Attribute
Description
Values
0
1
STARTUP_WAIT Delays transition
fromconfiguration
to user mode until
TRUE, FALSE
I1 Input
The BUFG clock buffer primitive drives a single clock signal
onto the clock network and is essentially the same element
as a BUFGMUX, just without the clock select mechanism.
Similarly, the BUFGCE primitive creates an enabled clock
buffer using the BUFGMUX select mechanism.
DCM locks to
input clock.
Clocking Infrastructure
The Spartan-3E clocking infrastructure, shown in Figure 42,
provides a series of low-capacitance, low-skew interconnect
lines well-suited to carrying high-frequency signals through-
out the FPGA. The infrastructure also includes the clock
inputs and BUFGMUX clock buffers/multiplexers. The Xilinx
Place-and-Route (PAR) software automatically routes
high-fanout clock signals using these resources.
The I0 and I1 inputs to an BUFGMUX element originate
from clock input pins, DCMs, or Double-Line interconnect,
as shown in Figure 43. As shown in Figure 42, there are 24
BUFGMUX elements distributed around the four edges of
the device. Clock signals from the four BUFGMUX elements
at the top edge and the four at the bottom edge are truly glo-
bal and connect to all clocking quadrants. The eight
left-edge BUFGMUX elements only connect to the two clock
quadrants in the left half of the device. Similarly, the eight
right-edge BUFGMUX elements only connect to the right
half of the device.
Clock Inputs
Clock pins accept external clock signals and connect directly
to DCMs and BUFGMUX elements. Each Spartan-3E FPGA
has:
BUFGMUX elements are organized in pairs and share I0
and I1 connections with adjacent BUFGMUX elements from
a common clock switch matrix as shown in Figure 43. For
example, the input on I0 of one BUFGMUX also a shared
input to I1 of the adjacent BUFGMUX.
•
•
•
16 Global Clock inputs (GCLK0 through GCLK15)
located along the top and bottom edges of the FPGA
8 Right-Half Clock inputs (RHCLK0 through RHCLK7)
located along the right edge
8 Left-Half Clock inputs (LHCLK0 through LHCLK7)
located along the left edge
The clock switch matrix for the left- and right-edge BUFG-
MUX elements receive signals from any of the three follow-
ing sources: an LHCLK or RHCLK pin as appropriate, a
Double-Line interconnect, or a DCM in the XC3S1200E and
XC3S1600E devices.
Clock inputs optionally connect directly to DCMs using ded-
icated connections. Table 35 shows the clock inputs that
feed a specific DCM within a given Spartan-3E part number.
Different Spartan-3E FPGA densities have different num-
bers of DCMs.
By contrast, the clock switch matrixes on the top and bottom
edges receive signals from any of the five following sources:
two GCLK pins, two DCM outputs, or one Double-Line inter-
connect.
Each clock input is also optionally a user-I/O pin and con-
nects to internal interconnect. Some clock pad pins are
input-only pins as indicated in Module 4 of the Spartan-3E
Data Sheet.
Table 36 indicates permissible connections between clock
inputs and BUFGMUX elements. The four BUFGMUX ele-
ments on the top edge are paired together and share inputs
from the eight global clock inputs along the top edge. Each
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Functional Description
BUFGMUX pair connects to four of the eight global clock
inputs, as shown in Figure 42. This optionally allows differ-
ential inputs to the global clock inputs without wasting a
BUFGMUX element.
The connections for the bottom-edge BUFGMUX elements
is similar to the top-edge connections.
On the left and right edges, only two clock inputs feed each
pair of BUFGMUX elements.
Global Clock Inputs
GCLK11 GCLK7
GCLK9 GCLK5
GCLK10 GCLK6
GCLK8 GCLK4
BUFGMUX
pair
DCM
Clock Line
DCM
XC3S100E (X0Y1)
XC3S250E (X1Y1)
XC3S500E (X1Y1)
XC3S1200E (X2Y3)
XC3S1600E (X2Y3)
in Quadrant
XC3S250E (X0Y1)
XC3S500E (X0Y1)
XC3S1200E (X1Y3)
XC3S1600E (X1Y3)
4
4
X1Y10 X1Y11
X2Y10 X2Y11
BUFGMUX
4
4
H
G
F
E
H
G
H
Top Left Quadrant (TL)
Top Right Quadrant (TR)
4
G
4
4
4
•
•
4
DCM
XC3S1200E (X0Y2)
XC3S1600E (X0Y2)
8
DCM
XC3S1200E (X3Y2)
XC3S1600E (X3Y2)
8
•
•
•
4
4
4
4
F
F
•
E
D
E
D
Figure 44a
Figure 44b
8
8
8
8
Left Spine
Right Spine
Horizontal
Spine
Figure 44b
Figure 44a
•
8
•
8
C
C
4
4
4
4
DCM
XC3S1200E (X0Y1)
XC3S1600E (X0Y1)
DCM
XC3S1200E (X3Y1)
XC3S1600E (X3Y1)
•
•
4
4
4
4
•
•
B
A
B
A
4
Bottom Right Quadrant (BR)
Bottom Left Quadrant (BL)
4
4
DCM
DCM
D
C
B
A
XC3S100E (X0Y0)
XC3S250E (X1Y0)
XC3S500E (X1Y0)
XC3S1200E (X2Y0)
XC3S1600E (X2Y0)
XC3S250E (X0Y0)
XC3S500E (X0Y0)
XC3S1200E (X1Y0)
XC3S1600E (X1Y0)
4
4
X1Y0 X1Y1
X2Y0 X2Y1
GCLK2 GCLK14
GCLK0 GCLK12
GCLK3 GCLK15
GCLK1 GCLK13
DS312-2_04_030205
Global Clock Inputs
Notes:
1. Number of DCMs and locations of these DCM varies for different device densities.
2. The left and right DCMs are only in the XC3S1200E and XC3S1600E. The XC3S100E has only two DCMs, one on the top right
and one on the bottom right of the die.
Figure 42: Spartan-3E Internal Quadrant-Based Clock Network (Top View)
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Table 35: Direct Connections from Clock Inputs to DCMs and Associated DCM Location String
Clock Input
GCLK[3:0]
XC3S100E
DCM_X0Y0
N/A
XC3S250E/XC3S500E
DCM_X1Y0
N/A
XC3S1200E/XC3S1600E
DCM_X2Y0
RHCLK[3:0]
RHCLK[7:4]
GCLK[7:4]
DCM_X3Y1
N/A
N/A
DCM_X3Y2
DCM_X0Y1
N/A
DCM_X1Y1
DCM_X0Y1
N/A
DCM_X2Y2
GCLK[11:8]
LHCLK[3:0]
LHCLK[7:4]
GCLK[15:12]
DCM_X1Y3
N/A
DCM_X0Y2
N/A
N/A
DCM_X0Y1
N/A
DCM_X0Y0
DCM_X1Y0
Table 36: Connections from Clock Inputs to BUFGMUX Elements and Associated Quadrant Clock
Quadrant
Clock
Line(1)
Left-Half BUFGMUX
Top or Bottom BUFGMUX
Right-Half BUFGMUX
(2)
(2)
(2)
Location
Location
Location
I0 Input
I1 Input
I0 Input
I1 Input
I0 Input
I1 Input
GCLK0 or GCLK1 or
GCLK12 GCLK13
A
B
C
D
E
F
X0Y2
X0Y3
X0Y4
X0Y5
X0Y6
X0Y7
X0Y8
X0Y9
LHCLK7 LHCLK6
LHCLK6 LHCLK7
LHCLK5 LHCLK4
LHCLK4 LHCLK5
LHCLK3 LHCLK2
LHCLK2 LHCLK3
LHCLK1 LHCLK0
LHCLK0 LHCLK1
X2Y1
X2Y0
X3Y2
X3Y3
X3Y4
X3Y5
X3Y6
X3Y7
X3Y8
X3Y9
RHCLK0 RHCLK1
RHCLK1 RHCLK0
RHCLK2 RHCLK3
RHCLK3 RHCLK2
RHCLK4 RHCLK5
RHCLK5 RHCLK4
RHCLK6 RHCLK7
RHCLK7 RHCLK6
GCLK1 or GCLK0 or
GCLK13 GCLK12
GCLK2 or GCLK3 or
GCLK14 GCLK15
X1Y1
GCLK3 or GCLK2 or
GCLK15 GCLK14
X1Y0
GCLK4 or GCLK5 or
GCLK8 GCLK9
X2Y11
X2Y10
X1Y11
X1Y10
GCLK5 or GCLK4 or
GCLK9 GCLK8
GCLK6 or GCLK7 or
GCLK10 GCLK11
G
GCLK7 or GCLK6 or
GCLK11 GCLK10
H
Notes:
1. See Quadrant Clock Routing for connectivity details for the eight quadrant clocks.
2. See Figure 42 for specific BUFGMUX locations and Figure 44 for information on how BUFGMUX elements drive onto a specific clock line
within a quadrant.
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Functional Description
Left-/Right-Half BUFGMUX
Top/Bottom (Global) BUFGMUX
CLK Switch
Matrix
CLK Switch
Matrix
BUFGMUX
O
BUFGMUX
O
S
S
I0
I0
0
1
0
1
I1
I1
I0
I1
I0
I1
0
1
0
1
O
O
S
S
LHCLK or
RHCLK input
1st GCLK pin
1st DCM output
Double Line
Double Line
DCM output*
*(XC3S1200E and
and XC3S1600E only)
2nd DCM output
2nd GCLK pin
DS312-2_16_022505
Figure 43: Clock Switch Matrix to BUFGMUX Pair Connectivity
The four quadrants of the device are:
Quadrant Clock Routing
•
•
•
•
Top Right (TR)
Bottom Right (BR)
Bottom Left (BL)
Top Left (TL)
The clock routing within the FPGA is quadrant-based, as
shown in Figure 42. Each clock quadrant supports eight
total clock signals, labeled ‘A’ through ‘H’ in Table 36 and
Figure 44. The clock source for an individual clock line orig-
inates either from a global BUFGMUX element along the
top and bottom edges or from a BUFGMUX element along
the associated edge, as shown in Figure 44. The clock lines
feed the synchronous resource elements (CLBs, IOBs,
block RAM, multipliers, and DCMs) within the quadrant.
Note that the quadrant clock notation (TR, BR, BL, TL) is
separate from that used for similar IOB placement con-
straints.
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Clock Line
BUFGMUX Output
Clock Line
BUFGMUX Output
X2Y1 (Global)
X2Y1 (Global)
A
A
X0Y2 (Left Half)
X3Y2 (Right Half)
X2Y0 (Global)
X2Y0 (Global)
B
C
D
E
F
B
C
D
E
F
X0Y3 (Left Half)
X3Y3 (Right Half)
X1Y1 (Global)
X1Y1 (Global)
X0Y4 (Left Half)
X3Y4 (Right Half)
X1Y0 (Global)
X1Y0 (Global)
X0Y5 (Left Half)
X3Y5 (Right Half)
X2Y11 (Global)
X0Y6 (Left Half)
X2Y11 (Global)
X3Y6 (Right Half)
X2Y10 (Global)
X0Y7 (Left Half)
X2Y10 (Global)
X3Y7 (Right Half)
X1Y11 (Global)
X0Y8 (Left Half)
X1Y11 (Global)
G
H
G
H
X3Y8 (Right Half)
X1Y10 (Global)
X0Y9 (Left Half)
X1Y10 (Global)
X3Y9 (Right Half)
a. Left (TL and BL Quadrants) Half of Die
b. Right (TR and BR Quadrants) Half of Die
DS312-2_17_030105
Figure 44: Clock Sources for the Eight Clock Lines within a Clock Quadrant
The outputs of the top or bottom BUFGMUX elements con-
nect to two vertical spines, each comprising four vertical
clock lines as shown in Figure 42. At the center of the die,
these clock signals connect to the eight-line horizontal clock
spine.
in a single clock quadrant. Figure 44 shows how the clock
lines in each quadrant are selected from associated BUFG-
MUX sources. For example, if quadrant clock ‘A’ in the bot-
tom left (BL) quadrant originates from BUFGMUX_X2Y1,
then the clock signal from BUFGMUX_X0Y2 is unavailable
in the bottom left quadrant. However, the top left (TL) quad-
rant clock ‘A’ can still solely use the output from either
BUFGMUX_X2Y1 or BUFGMUX_X0Y2 as the source.
Outputs of the left and right BUFGMUX elements are routed
onto the left or right horizontal spines, each comprising
eight horizontal clock lines.
To minimize the dynamic power dissipation of the clock net-
work, the Xilinx development software automatically dis-
ables all clock segments not in use.
Each of the eight clock signals in a clock quadrant derives
either from a global clock signal or a half clock signal. In
other words, there are up to 24 total potential clock inputs to
the FPGA, eight of which can connect to clocked elements
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Functional Description
The switch matrix connects to the different kinds of intercon-
nects across the device. An interconnect tile, shown in
Figure 45, is defined as a single switch matrix connected to
a functional element, such as a CLB, IOB, or DCM. If a func-
tional element spans across multiple switch matrices such
as the block RAM or multipliers, then an interconnect tile is
defined by the number of switch matrices connected to that
functional element. A Spartan-3E device can be repre-
sented as an array of interconnect tiles where interconnect
resources are for the channel between any two adjacent
interconnect tile rows or columns as shown in Figure 46.
Interconnect
Interconnect is the programmable network of signal path-
ways between the inputs and outputs of functional elements
within the FPGA, such as IOBs, CLBs, DCMs, block RAM,
etc.
Interconnect, also called routing, is segmented for optimal
connectivity. Functionally, interconnect resources are identi-
cal to that of the Spartan-3 architecture. There are four
kinds of interconnects: long lines, hex lines, double lines,
and direct lines. The Xilinx Place and Route (PAR) software
exploits the rich interconnect array to deliver optimal system
performance and the fastest compile times.
Switch
Matrix
Switch
CLB
Matrix
Switch
Matrix
Switch
IOB
18Kb
Block
RAM
MULT
18 x 18
Matrix
Switch
Matrix
Switch
DCM
Matrix
Switch
Matrix
DS312_08_020905
Figure 45: Four Types of Interconnect Tiles (CLBs, IOBs, DCMs, and Block RAM/Multiplier)
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
IOB
IOB
IOB
IOB
IOB
IOB
CLB
CLB
CLB
CLB
IOB
CLB
CLB
CLB
CLB
IOB
CLB
CLB
CLB
CLB
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
DS312_09_020905
Figure 46: Array of Interconnect Tiles in Spartan-3E FPGA
DS312-2 (v1.1) March 21, 2005
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Functional Description
There are four type of general-purpose interconnect avail-
able in each channel, as shown in Figure 47 and described
below.
Global Controls (STARTUP_SPARTAN3E)
In addition to the general-purpose interconnect, Spartan-3E
FPGAs have two global logic control signals, as described
in Table 37. These signals are available to the FPGA appli-
cation via the STARTUP_SPARTAN3E primitive.
Long Lines
Each set of 24 long line signals spans the die both horizon-
tally and vertically and connects to one out of every six inter-
connect tiles. At any tile, four of the long lines drive or
receive signals from a switch matrix. Because of their low
capacitance, these lines are well-suited for carrying
high-frequency signals with minimal loading effects (e.g.
skew). If all global clock lines are already committed and
additional clock signals remain to be assigned, long lines
serve as a good alternative.
Table 37: Spartan-3E Global Logic Control Signals
Global
Description
Control Input
When driven High, asynchronously
places all registers and flip-flops in their
initial state (see Initialization, page 24).
Asserted automatically during the FPGA
GSR
configuration process (see Start-Up,
page 91).
Hex Lines
Each set of eight hex lines are connected to one out of
every three tiles, both horizontally and vertically. Thirty-two
hex lines are available between any given interconnect tile.
Hex lines are only driven from one end of the route.
When driven High, asynchronously
forces all I/O pins to a high-impedance
state (Hi-Z, three-state).
GTS
The Global Set/Reset (GSR) signal replaces the global
reset signal included in many ASIC-style designs. Use the
GSR control instead of a separate global reset signal in the
design to free up CLB inputs, resulting in a smaller, more
efficient design. Similarly, the GSR signal is asserted auto-
matically during the FPGA configuration process, guaran-
teeing that the FPGA starts-up in a known state.
Double Lines
Each set of eight double lines are connected to every other
tile, both horizontally and vertically. in all four directions.
Thirty-two double lines available between any given inter-
connect tile. Double lines are more connections and more
flexibility, compared to long line and hex lines.
The STARTUP_SPARTAN3E primitive also includes two
other signals used specifically during configuration. The
MBT signals are for Dynamically Loading Multiple Con-
figuration Images Using MultiBoot Option, page 78. The
CLK input is an alternate clock for configuration Start-Up,
page 91.
Direct Connections
Direct connect lines route signals to neighboring tiles: verti-
cally, horizontally, and diagonally. These lines most often
drive a signal from a "source" tile to a double, hex, or long
line and conversely from the longer interconnect back to a
direct line accessing a "destination" tile.
Horizontal and
24
Vertical Long Lines
(horizontal channel
shown as an example)
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
6
6
6
6
6
DS312-2_10_022305
Horizontal and
8
Vertical Hex Lines
(horizontal channel
shown as an example)
CLB
CLB
CLB
CLB
CLB
CLB
CLB
DS312-2_11_020905
Figure 47: Interconnect Types between Two Adjacent Interconnect Tiles
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Functional Description
Horizontal and
Vertical Double
Lines
8
(horizontal channel
shown as an example)
CLB
CLB
CLB
DS312-2_15_022305
Direct Connections
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
DS312-2_12_020905
Figure 47: Interconnect Types between Two Adjacent Interconnect Tiles
DS312-2 (v1.1) March 21, 2005
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Functional Description
borrowed and returned to the application as general-pur-
pose user I/Os after configuration completes.
Configuration
Differences from Spartan-3 FPGAs
Spartan-3E FPGAs offer several configuration options to
minimize the impact of configuration on the overall system
design. In some configuration modes, the FPGA generates
a clock and loads itself from an external memory source,
either serially or via a byte-wide data path. Alternatively, an
external host such as a microprocessor downloads the
FPGA’s configuration data using a simple synchronous
serial interface or via a byte-wide peripheral-style interface.
Furthermore, multiple-FPGA designs share a single config-
uration memory source, creating a structure called a daisy
chain.
In general, Spartan-3E FPGA configuration modes are a
superset to those available in Spartan-3 FPGAs. Two new
modes added in Spartan-3E FPGAs provide a glue-less
configuration interface to industry-standard parallel NOR
Flash and SPI serial Flash memories. Unlike Spartan-3
FPGAs, nearly all of the Spartan-3E configuration pins
become available as user I/Os after configuration.
Configuration Process
The function of a Spartan-3E FPGA is defined by loading
application-specific configuration data into the FPGA’s
internal, reprogrammable CMOS configuration latches
(CCLs), similar to the way a microprocessor’s function is
defined by its application program. For FPGAs, this configu-
ration process uses a subset of the device pins, some of
which are dedicated to configuration; other pins are merely
Three FPGA pins—M2, M1, and M0—select the desired
configuration mode. The mode pin settings appear in
Table 38. The mode pin values are sampled during the start
of configuration when the FPGA’s INIT_B output goes High.
After the FPGA completes configuration, the mode pins are
available as user I/Os.
Table 38: Spartan-3E Configuration Mode Pin Settings
Master
Serial
SPI
BPI
Slave Parallel
Slave Serial
JTAG
M[2:0] mode pin
settings
<0:0:0>
<0:0:1>
<0:1:0>=Up
<1:1:0>
<1:1:1>
<1:0:1>
<0:1:1>=Down
Data width
Serial
Serial
Byte-wide
Byte-wide
Serial
Serial
Configuration memory
source
Xilinx
Platform
Flash
Industry-standard Industry-standard Any source via
Any source via
Any source via
SPI Serial Flash
parallel NOR
Flash
microcontroller, microcontroller, microcontroller,
CPU, Xilinx
parallel
CPU, Xilinx
Platform Flash, System Ace CF
etc.
CPU, etc. and
Platform Flash,
etc.
Clock source
Internal
oscillator
Internal oscillator Internal oscillator
External clock
on CCLK pin
External clock
on CCLK pin
External clock
on TCK pin
Total I/O pins
borrowed during
configuration
8
13
46
21
8
0
Configuration mode
for downstream
daisy-chained FPGAs
Slave Serial
Slave Serial
Slave Parallel
Slave Parallel
or Memory
Mapped
Slave Serial
JTAG
Possible using
XCFxxP Platform
Flash, which
optionally
generates CCLK
Possible using
XCFxxP Platform
Flash, which
optionally
generates CCLK
Self-configuring
applications (no
external download
host)
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Uses low-cost,
industry-standard
Flash
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Functional Description
A specific Spartan-3E part type always requires a constant
number of configuration bits, regardless of design complex-
ity, as shown in Table 39. The configuration file size for a
multiple-FPGA daisy-chain design equals the sum of the
individual file sizes.
Pin Behavior During Configuration
Table 40 shows how various pins behave during the FPGA
configuration process. The actual behavior depends on the
values applied to the M2, M1, and M0 mode select pins and
the HSWAP pin. The mode select pins determine which of
the I/O pins are borrowed during configuration and how they
function. In JTAG configuration mode, no user-I/O pins are
borrowed for configuration.
Table 39: Number of Bits to Program a Spartan-3E
FPGA (Uncompressed Bitstreams)
All I/O pins are high impedance (floating, three-stated, Hi-Z)
during the configuration process. These pins are indicated
in Table 40 as shaded table entries or cells. If the HSWAP
input is Low, these pins have a pull-up resistor to their asso-
ciated VCCO supply that is active throughout configuration.
After configuration, pull-up and pull-down resistors are
available in the FPGA application as described in Pull-Up
and Pull-Down Resistors, page 9.
Number of Configuration
Device
Bits
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
581,344
1,352,192
2,267,136
3,832,320
5,957,760
Spartan-3E FPGAs have only six dedicated configuration
pins, including the DONE and PROG_B pins, and the four
JTAG boundary-scan pins: TDI, TDO, TMS, and TCK.
Table 40: Pin Behavior during Configuration
Master
Serial
SPI (Serial BPI(Parallel
Slave
Parallel
Supply/
I/O Bank
Pin Name
TDI
Flash)
NOR Flash)
JTAG
TDI
Slave Serial
TDI
TMS
TCK
TDO
PROG_B
DONE
HSWAP
0
TDI
TDI
TDI
TMS
TCK
TDO
PROG_B
DONE
HSWAP
1
TDI
TMS
TCK
TDO
PROG_B
DONE
HSWAP
1
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
0
TMS
TMS
TCK
TDO
PROG_B
DONE
HSWAP
0
TMS
TMS
TCK
TDO
PROG_B
DONE
HSWAP
1
TCK
TCK
TDO
TDO
PROG_B
DONE
HSWAP
M2
PROG_B
DONE
HSWAP
0
2
M1
0
0
1
0
1
1
2
M0
0
1
0 = Up
1
0
1
2
1 = Down
CCLK
INIT_B
CSO_B
DOUT/BUSY
MOSI/CSI_B
D7
CCLK (O)
INIT_B
CCLK (O)
INIT_B
CSO_B
DOUT
CCLK (O)
INIT_B
CSO_B
BUSY
CSI_B
D7
CCLK (I)
INIT_B
CSO_B
BUSY
CSI_B
D7
CCLK (I)
INIT_B
2
2
2
2
2
2
2
2
2
DOUT
DOUT
MOSI
D6
D6
D6
D5
D5
D5
D4
D4
D4
DS312-2 (v1.1) March 21, 2005
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Functional Description
Table 40: Pin Behavior during Configuration (Continued)
Master
Serial
SPI (Serial BPI(Parallel
Slave
Parallel
Supply/
I/O Bank
Pin Name
D3
Flash)
NOR Flash)
JTAG
Slave Serial
D3
D3
D2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D2
D2
D1
D1
D1
D0/DIN
RDWR_B
A23
DIN
DIN
D0
D0
DIN
RDWR_B
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
RDWR_B
A22
A21
A20
A19/VS2
A18/VS1
A17/VS0
A16
VS2
VS1
VS0
A15
A14
A13
A12
A11
A10
A9
A8
A8
A7
A7
A6
A6
A5
A5
A4
A4
A3
A3
A2
A2
A1
A1
A0
A0
LDC0
LDC1
LDC2
HDC
LDC0
LDC1
LDC2
HDC
LDC0
LDC1
LDC2
HDC
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Functional Description
Table 41 shows the default I/O standard setting for the vari-
ous configuration pins during the configuration process. The
configuration interface is designed primarily for 2.5V opera-
tion when the VCCO_2 (and VCCO_1 in BPI mode) con-
nects to 2.5V.
drive characteristics. For example, with VCCO = 3.3V, the
output current when driving High, IOH, increases to approx-
imately 12 to 16 mA, while the current when driving Low,
IOL, remains 8 mA. At VCCO = 1.8V, the output current
when driving High, IOH, decreases slightly to approximately
6 to 8 mA. Again, the current when driving Low, IOL, remains
8 mA.
The configuration pins also operate at other voltages by set-
ting VCCO_2 (and VCCO_1 in BPI mode) to either 3.3V or
1.8V. The change on the VCCO supply also changes the I/O
Table 41: Default I/O Standard Setting During Configuration (VCCO_2 = 2.5V)
Pin(s)
I/O Standard
Output Drive
Slew Rate
All, including CCLK
LVCMOS25
8 mA
Slow
attached Platform Flash PROM. In response, the Platform
Flash PROM supplies bit-serial data to the FPGA’s DIN
input and the FPGA accepts this data on each rising CCLK
edge.
Master Serial Mode
In Master Serial mode (M[2:0] = <0:0:0>), the Spartan-3E
FPGA configures itself from an attached Xilinx Platform
Flash PROM, as illustrated in Figure 48. The FPGA sup-
plies the CCLK output clock from its internal oscillator to the
+1.2V
XCFxxS = +3.3V
XCFxxP = +1.8V
V
VCCINT
P
HSWAP
VCCO_0
VCCO_0
VCCINT
VCCO_2
DIN
V
D0
VCCO
V
Serial Master
Mode
CCLK
DOUT
INIT_B
CLK
‘0’
‘0’
‘0’
M2
M1
M0
OE/RESET
+2.5V
Spartan-3E
Platform Flash
XCFxx
CE
CF
CEO
+2.5V
JTAG
VCCAUX
TDO
+2.5V
VCCJ
TDO
+2.5V
TDI
TDI
TDI
TMS
TCK
TDO
TMS
TCK
TMS
TCK
GND
PROG_B
DONE
GND
PROG_B
Recommend
open-drain
driver
DS312-2_44_021405
Figure 48: Master Serial Mode using Platform Flash PROM
DS312-2 (v1.1) March 21, 2005
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Functional Description
The mode select pins, M[2:0], must all be Low when sam-
pled, when the FPGA’s INIT_B output goes High. After con-
figuration, when the FPGA’s DONE output goes High, the
mode select pins are available as full-featured user-I/O pins.
FPGA configuration. After configuration, when the FPGA’s
DONE output goes High, the HSWAP pin is available as
full-featured user-I/O pin and is powered by the VCCO_0
supply.
P
Similarly, the FPGA’s HSWAP pin must be Low to
The FPGA's DOUT pin is used in daisy-chain applications,
described later. In a single-FPGA application, the FPGA’s
DOUT pin is not used but is actively driving during the con-
figuration process.
enable pull-up resistors on all user-I/O pins during configu-
ration or High to disable the pull-up resistors. The HSWAP
control must remain at a constant logic level throughout
Table 42: Serial Master Mode Connections
Pin Name
FPGA Direction
Description
During Configuration
After Configuration
HSWAP
Input
User I/O Pull-Up Control. When Low
during configuration, enables pull-up
resistors in all I/O pins to respective I/O
bank VCCO input.
Drive at valid logic level
throughout configuration.
User I/O
P
0: Pull-ups during configuration
1: No pull-ups
M[2:0]
Input
Mode Select. Selects the FPGA
configuration mode.
M2 = 0, M1 = 0, M0 = 0.
Sampled when INIT_B goes
High.
User I/O
DIN
Input
Serial Data Input.
Receives serial data from
PROM’s D0 output.
User I/O
User I/O
CCLK
Output
Configuration Clock. Generated by
FPGA internal oscillator. Frequency
controlled by ConfigRate bitstream
generator option. If CCLK PCB trace is
long or has multiple connections,
terminate this output to maintain signal
integrity.
Drives PROM’s CLK clock
input.
DOUT
Output
Serial Data Output.
Actively drives. Not used in
single-FPGA designs. In a
daisy-chain configuration,
this pin connects to DIN input
of the next FPGA in the chain.
User I/O
User I/O
INIT_B
Open-drain
InitializationIndicator. ActiveLow. Goes Connects to PROM’s
bidirectional I/O Low at start of configuration during
Initialization memory clearing process.
Released at end of memory clearing,
OE/RESET input. FPGA
clears PROM’s address
counter at start of
when mode select pins are sampled.
configuration, enables
Requires external 4.7 kΩ pull-up resistor outputs during configuration.
to VCCO_2.
PROM also holds FPGA in
Initialization state until PROM
reaches Power-On Reset
(POR) state. If CRC error
detected during
configuration, FPGA drives
INIT_B Low.
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Functional Description
After Configuration
Table 42: Serial Master Mode Connections (Continued)
Pin Name
FPGA Direction
Description
During Configuration
DONE
Open-drain
FPGA Configuration Done. Low during Connects to PROM’s
Pulled High via
external pull-up.
When High, indicates
that the FPGA
successfully
bidirectional I/O configuration. Goes High when FPGA
successfully completes configuration.
Requires external 330 Ω pull-up resistor
to 2.5V.
chip-enable (CE) input.
Enables PROM during
configuration. Disables
PROM after configuration.
configured.
PROG_B
Input
Program FPGA. Active Low. When
asserted Low for 300 ns or longer, forces configuration to allow
the FPGA to restart its configuration
process by clearing configuration
memory and resetting the DONE and
Must be High during
Drive PROG_B Low
and release to
reprogram FPGA.
configuration to start.
Connects to PROM’s CF pin,
allowing JTAG PROM
INIT_B pins once PROG_B returns High. programming algorithm to
Requires external 4.7 kΩ pull-up resistor reprogram the FPGA.
to 2.5V. If driving externally, use an
open-drain or open-collector driver.
The XC3S1600E requires an 8 Mbit PROM. There are two
possible solutions. Either use a single 8 Mbit XCF08P par-
allel/serial PROM or cascade two 4 Mbit XCF04S serial
PROMs. The two XCF04S PROMs use a 3.3V VCCINT sup-
ply while the XCF08P requires a 1.8V VCCINT supply. If the
board does not already have a 1.8V supply available, the
two cascaded XCF04S PROM solution is recommended.
Voltage Compatibility
The PROM’s VCCINT supply must be either 3.3V for the
serial XCFxxS Platform Flash PROMs or 1.8V for the
serial/parallel XCFxxP PROMs.
V
The FPGA’s VCCO_2 supply input and the Platform
Flash PROM’s VCCO supply input must be the same volt-
age, ideally +2.5V. Both devices also support 1.8V and 3.3V
interfaces but the FPGA’s PROG_B and DONE pins require
special attention as they are powered by the FPGA’s
VCCAUX supply, nominally 2.5V. See application note
XAPP453: "The 3.3V Configuration of Spartan-3 FPGAs"
for additional information.
CCLK Frequency
In Master Serial mode, the FPGA’s internal oscillator gener-
ates the configuration clock frequency. The FPGA provides
this clock on its CCLK output pin, driving the PROM’s CLK
input pin. The FPGA starts configuration at its lowest fre-
quency and increases its frequency for the remainder of the
configuration process if so specified in the configuration bit-
stream. The maximum frequency is specified using the
ConfigRate bitstream generator option. Table 44 shows the
maximum ConfigRate settings, approximately equal to
MHz, for various Platform Flash devices and I/O voltages.
For the serial XCFxxS PROMs, the maximum frequency
also depends on the interface voltage.
Supported Platform Flash PROMs
Table 43 shows the smallest available Platform Flash
PROM to program a single Spartan-3E FPGA. A multi-
ple-FPGA daisy-chain application requires a Platform Flash
PROM large enough to contain the sum of the various
FPGA file sizes.
Table 43: Number of Bits to Program a Spartan-3E
FPGA and Smallest Platform Flash PROM
Table 44: Maximum ConfigRate Settings for Platform
Flash
Number of
Configuration
Bits
SmallestAvailable
Platform Flash
Maximum
ConfigRate
Setting
Device
Platform Flash
Part Number
I/O Voltage
(VCCO_2, VCCO)
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
581,344
1,352,192
2,267,136
3,832,320
5,957,760
XCF01S
XCF02S
XCF04S
XCF04S
XCF01S
XCF02S
XCF04S
3.3V or 2.5V
1.8V
25
12
XCF08P
XCF16P
XCF32P
3.3V, 2.5V, or 1.8V
25
XCF08P
or 2 x XCF04S
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Functional Description
CCLK
+1.2V
+1.2V
XCFxxS = +3.3V
XCFxxP = +1.8V
VCCINT
VCCINT
P
HSWAP
VCCO_0
VCCO_0
P
HSWAP
VCCO_0
VCCO_0
VCCINT
VCCO_2
DIN
V
VCCO_2
V
Slave
Serial
Mode
D0
VCCO
V
Serial Master
Mode
CCLK
DOUT
INIT_B
CLK
‘0’
‘0’
‘0’
M2
M1
M0
‘1’
‘1’
‘1’
M2
M1
M0
DOUT
INIT_B
DOUT
OE/RESET
Platform Flash
Spartan-3E
FPGA
Spartan-3E
FPGA
XCFxx
CE
CF
CEO
CCLK
DIN
+2.5V
JTAG
VCCAUX
+2.5V
VCCJ
TDO
+2.5V
VCCAUX
+2.5V
TDI
TDI
TDO
TDI
TDI
TDO
TMS
TCK
TDO
TMS
TCK
TMS
TCK
TMS
TCK
V
+2.5V
GND
PROG_B
DONE
PROG_B
DONE
GND
GND
PROG_B
PROG_B
Recommend
open-drain
driver
TCK
TMS
DONE
INIT_B
DS312-2_45_021405
Figure 49: Daisy-Chaining from Master Serial Mode
provided by the Xilinx iMPACT programming software and
the associated Xilinx Parallel Cable IV, MultiPRO, or Plat-
form Cable USB programming cables.
Daisy-Chaining
If the application requires multiple FPGAs with different con-
figurations, then configure the FPGAs using a daisy chain,
as shown in Figure 49. Use Master Serial mode
(M[2:0] = <0:0:0>) for the FPGA connected to the Platform
Flash PROM and Slave Serial mode (M[2:0] = <1:1:1>) for
all other FPGAs in the daisy-chain. After the master
FPGA—the FPGA on the left in the diagram—finishes load-
ing its configuration data from the Platform Flash, the mas-
ter device supplies data using its DOUT output pin to the
next device in the daisy-chain, on the falling CCLK edge.
Storing Additional User Data in Platform Flash
After configuration, the FPGA application can continue to
use the Master Serial interface pins to communicate with
the Platform Flash PROM. If desired, use a larger Platform
Flash PROM to hold additional non-volatile application data,
such as MicroBlaze processor code, or other user data such
as serial numbers and Ethernet MAC IDs. The FPGA first
configures from Platform Flash PROM. Then using FPGA
logic after configuration, the FPGA copies MicroBlaze code
from Platform Flash into external DDR SDRAM for code
execution.
JTAG Interface
Both the Spartan-3E FPGA and the Platform Flash PROM
have a four-wire IEEE 1149.1/1532 JTAG port. Both devices
share the TCK clock input and the TMS mode select input.
The devices may connect in either order on the JTAG chain
with the TDO output of one device feeding the TDI input of
the following device in the chain. The TDO output of the last
device in the JTAG chain drives the JTAG connector.
See XAPP694: "Reading User Data from Configuration
PROMs" and XAPP482: "MicroBlaze Platform Flash/PROM
Boot Loader and User Data Storage" for specific details on
how to implement such an interface.
SPI Serial Flash Mode
The JTAG interface on Spartan-3E FPGAs is powered by
the 2.5V VCCAUX supply. Consequently, the PROM’s VCCJ
supply input must also be 2.5V. To create a 3.3V JTAG inter-
face, please refer to application note XAPP453: "The 3.3V
Configuration of Spartan-3 FPGAs" for additional informa-
tion.
In SPI Serial Flash mode (M[2:0] = <0:0:0>), the Spartan-3E
FPGA configures itself from an attached industry-standard
SPI serial Flash PROM, as illustrated in Figure 50 and
Figure 52. The FPGA supplies the CCLK output clock from
its internal oscillator to the clock input of the attached SPI
Flash PROM.
In-System Programming Support
Both the FPGA and the Platform Flash PROM are in-system
programmable via the JTAG chain. Download support is
62
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Functional Description
+1.2V
+3.3V
SPI
Serial
Flash
VCCINT
P
P
HSWAP
VCCO_0
VCCO_0
+3.3V
I
VCC
DATA_IN
VCCO_2
MOSI
SPI Mode
DIN
DATA_OUT
SELECT
‘0’
‘0’
‘1’
M2
M1
M0
CSO_B
W
WR_PROTECT
HOLD
‘1’
CLOCK
Variant Select
Spartan-3E
FPGA
GND
‘1’
S
VS2
VS1
VS0
+3.3V
‘1’
CCLK
DOUT
INIT_B
+2.5V
JTAG
+2.5V
VCCAUX
TDO
+2.5V
TDI
TMS
TCK
TDO
TDI
TMS
TCK
PROG_B
DONE
GND
PROG_B
Recommend
open-drain
driver
DS312-2_46_021405
Figure 50: SPI Flash PROM Interface for PROMs Supporting READ (0x03) and FAST_READ (0x0B)
S
Although SPI is a standard four-wire interface, various
Figure 50 shows the general connection diagram for those
SPI Flash PROMs that support the 0x03 READ command
or the 0x0B FAST READ commands.
available SPI Flash PROMs use different command proto-
cols. The FPGA’s variant select pins, VS[2:0], define how
the FPGA communicates with the SPI Flash, including
which SPI Flash command the FPGA issues to start the
read operation and the number of dummy bytes inserted
before the FPGA expects to receive valid data from the SPI
Flash. Table 45 shows the available SPI Flash PROMs
expected to operate with Spartan-3E FPGAs. Other com-
patible devices might work but have not been tested for suit-
ability with Spartan-3E FPGAs. All other VS[2:0] values are
reserved for future use.
Figure 51 shows the connection diagram for Atmel
DataFlash serial PROMs, which also use an SPI-based pro-
tocol.
Figure 54 demonstrates how to configure multiple FPGAs
with different configurations, all stored in a single SPI Flash.
The diagram uses standard SPI Flash memories but the
same general technique applies for Atmel DataFlash.
DS312-2 (v1.1) March 21, 2005
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Functional Description
+1.2V
+3.3V
Atmel
AT45DB
VCCINT
DataFlash
P
P
HSWAP
VCCO_0
VCCO_0
+3.3V
I
VCC
VCCO_2
MOSI
SI
Power-on monitor is only required if
SPI Mode
DIN
SO
CS
WP
+3.3V (VCCO_2) supply is last supply
in power-on sequence, after VCCINT
and VCCAUX. Must delay FPGA
configuration for > 20 ms after SPI
DataFlash reaches its minimum VCC.
‘0’
‘0’
‘1’
M2
M1
M0
CSO_B
W
‘1’
RESET
RDY/BUSY
SCK
Force FPGA INIT_B input or
PROG_B
input Low with an open-drain or open-
collector driver.
Variant Select
Spartan-3E
FPGA
‘1’
‘1’
‘0’
VS2
VS1
VS0
GND
+3.3V
+3.3V
CCLK
DOUT
INIT_B
Power-On
Monitor
INIT_B
+2.5V
JTAG
TDI
+2.5V
VCCAUX
TDO
+2.5V
TDI
TMS
TCK
TDO
TMS
TCK
or
PROG_B
DONE
+3.3V
GND
Power-On
Monitor
PROG_B
PROG_B
Recommend
open-drain
driver
DS312-2_50a_022305
Figure 51: Atmel SPI-based DataFlash Configuration Interface
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Functional Description
Table 45: Variant Select Codes for SPI Serial Flash PROMs
SPI Read
Command
Dummy
Bytes
VS2 VS1 VS0
SPI Serial Flash Vendor
STMicroelectronics (ST)
SPI Flash Family
M25Pxx
NexFlash
NX25Pxx
FAST READ (0x0B)
(see Figure 50)
1
1
0
1
1
SST25LFxxxA
SST25VFxxxA
Silicon Storage Technology (SST)
Programmable Microelectronics Corp. (PMC) Pm25LVxxx
STMicroelectronics (ST)
NexFlash
M25Pxx
NX25Pxx
READ (0x03)
SST25LFxxxA
SST25VFxxxA
SST25VFxxx
1
1
1
0
0
3
(see Figure 50)
Silicon Storage Technology (SST)
Programmable Microelectronics Corp. (PMC) Pm25LVxxx
READ ARRAY
(0xE8)
1
Atmel Corporation AT45DB DataFlash
(see Figure 51)
Others
Reserved
W
Table 46 shows the connections between the SPI Flash
are not used by the FPGA during configuration. However,
the HOLD pin must be High during the configuration pro-
cess. The PROM’s write protect input must be High in order
to write or program the Flash memory.
PROM and the FPGA’s SPI configuration interface. Each
SPI Flash PROM vendor uses slightly different signal nam-
ing. The SPI Flash PROM’s write protect and hold controls
Table 46: SPI Flash PROM Connections and Pin Naming
Silicon
Storage
Atmel
SPI Flash Pin
DATA_IN
FPGA Connection
STMicro
NexFlash Technology
DataFlash
MOSI
DIN
D
Q
S
C
DI
DO
CS
SI
SI
SO
DATA_OUT
SELECT
SO
CSO_B
CCLK
CE#
SCK
CS
CLOCK
CLK
SCK
Not required for FPGA configuration. Must be
High to program SPI Flash. Optional
connection to FPGA user I/O after
configuration.
WR_PROTECT
W
WP
WP#
WP
N/A
W
Not required for FPGA configuration but must
be High during configuration. Optional
connection to FPGA user I/O after
configuration. Not applicable to Atmel
DataFlash.
HOLD
HOLD
HOLD
HOLD#
(see Figure 50)
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Advance Product Specification
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Functional Description
Table 46: SPI Flash PROM Connections and Pin Naming (Continued)
Silicon
Storage
Atmel
SPI Flash Pin
FPGA Connection
STMicro
NexFlash Technology
DataFlash
Only applicable to Atmel DataFlash. Not
required for FPGA configuration but must be
High during configuration. Optional
connection to FPGA user I/O after
configuration. Do not connect to FPGA’s
PROG_B as this will prevent direct
programming of the DataFlash.
RESET
N/A
N/A
N/A
N/A
N/A
RESET
(see Figure 51)
Only applicable to Atmel DataFlash and only
available on certain packages. Not required
for FPGA configuration. Output from
DataFlash PROM. Optional connection to
FPGA user I/O after configuration.
RDY/BUSY
N/A
RDY/BUSY
(see Figure 51)
The mode select pins, M[2:0], and the variant select pins,
VS[2:0] are sampled when the FPGA’s INIT_B output goes
High and must be at defined logic levels during this time.
After configuration, when the FPGA’s DONE output goes
High, these pins are all available as full-featured user-I/O
pins.
able the pull-up resistors. The HSWAP control must remain
at a constant logic level throughout FPGA configuration.
After configuration, when the FPGA’s DONE output goes
High, the HSWAP pin is available as full-featured user-I/O
pin and is powered by the VCCO_0 supply.
In a single-FPGA application, the FPGA’s DOUT pin is not
used but is actively driving during the configuration process.
Similarly, the FPGA’s HSWAP pin must be Low to
P
enable pull-up resistors on all user-I/O pins or High to dis-
Table 47: Serial Peripheral Interface (SPI) Connections
Pin Name
FPGA Direction
Description
During Configuration
After Configuration
User I/O
Input
User I/O Pull-Up Control. When
Drive at valid logic level
HSWAP
Low during configuration, enables throughout configuration.
pull-up resistors in all I/O pins to
P
respective I/O bank VCCO input.
0: Pull-ups during configuration
1: No pull-ups
Input
Input
Mode Select. Selects the FPGA
configuration mode.
M2 = 0, M1 = 0, M0 = 1.
Sampled when INIT_B goes
High.
M[2:0]
User I/O
User I/O
User I/O
Variant Select. Instructs the
FPGA how to communicate with
the attached SPI Flash PROM.
Must be at the logic levels
shown in Table 45. Sampled
when INIT_B goes High.
VS[2:0]
S
Output
Serial Data Output.
FPGA sends SPI Flash memory
read commands and starting
address to the PROM’s serial
data input.
MOSI
DIN
Input
Serial Data Input.
FPGA receives serial data from
PROM’s serial data output.
User I/O
66
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R
Functional Description
After Configuration
Table 47: Serial Peripheral Interface (SPI) Connections (Continued)
Pin Name
FPGA Direction
Description
During Configuration
Output
Chip Select Output. Active Low.
Connects to the SPI Flash
PROM’s chip-select input. If
HSWAP = 1, connect this signal
to a 4.7 kΩ pull-up resistor to
3.3V.
CSO_B
Drive CSO_B High after
configuration to disable the
SPI Flash and reclaim the
MOSI, DIN, and CCLK pins.
Optionally, re-use this pin
and MOSI, DIN, and CCLK
to continue communicating
with SPI Flash.
Output
Configuration Clock. Generated Drives PROM’s clock input.
by FPGA internal oscillator.
CCLK
User I/O
Frequency controlled by
ConfigRate bitstream generator
option. If CCLK PCB trace is long
or has multiple connections,
terminate this output to maintain
signal integrity.
Output
Serial Data Output.
Actively drives. Not used in
single-FPGA designs. In a
daisy-chain configuration, this
pin connects to DIN input of the
next FPGA in the chain.
DOUT
User I/O
User I/O
Open-drain
Initialization Indicator. Active
Active during configuration. If
SPI Flash PROM requires > 2
ms to awake after powering on,
hold INIT_B Low until PROM is
ready. If CRC error detected
during configuration, FPGA
drives INIT_B Low.
INIT_B
bidirectional I/O Low. Goes Low at start of
configuration during Initialization
memory clearing process.
Released at end of memory
clearing, when mode select pins
are sampled. In daisy-chain
applications, this signal requires
an external 4.7 kΩ pull-up resistor
to VCCO_2.
Open-drain
FPGA Configuration Done. Low
Low indicates that the FPGA is
not yet configured.
DONE
Pulled High via external
pull-up. When High,
indicates that the FPGA
successfully configured.
bidirectional I/O during configuration. Goes High
when FPGA successfully
completes configuration. Requires
external 330 Ω pull-up resistor to
2.5V.
Input
Program FPGA. Active Low.
When asserted Low for 300 ns or
longer, forces the FPGA to restart
its configuration process by
clearingconfigurationmemory and
resetting the DONE and INIT_B
pins once PROG_B returns High.
Requires external 4.7 kΩ pull-up
resistor to 2.5V. If driving
Must be High to allow
configuration to start.
PROG_B
Drive PROG_B Low and
release to reprogram
FPGA. Hold PROG_B to
force FPGA I/O pins into
Hi-Z, allowing direct
programming access to SPI
Flash PROM pins.
externally, use an open-drain or
open-collector driver.
I/O Bank 2. Consequently, the FPGA’s VCCO_2 supply volt-
age must also be 3.3V to match the SPI Flash PROM.
Voltage Compatibility
Available SPI Flash PROMs use a single 3.3V supply volt-
age. All of the FPGA’s SPI Flash interface signals are within
DS312-2 (v1.1) March 21, 2005
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Functional Description
The SPI Flash PROM is powered by the same voltage sup-
ply feeding the FPGA's VCCO_2 voltage input, typically
3.3V. SPI Flash PROMs specify that they cannot be
accessed until their VCC supply reaches its minimum data
sheet voltage, followed by an additional delay. For some
devices, this additional delay is as little as 10 µs as shown in
Table 48. For other vendors, it is as much as 20 ms.
Power-On Precautions if 3.3V Supply is Last in
Sequence
Spartan-3E FPGAs have a built-in power-on reset (POR)
circuit, as shown in Figure 63. The FPGA waits for its three
power supplies — VCCINT, VCCAUX, and VCCO to I/O
Bank 2 (VCCO_2) — to reach their respective power-on
thresholds before beginning the configuration process.
Table 48: Example Minimum Power-On to Select Times for Various SPI Flash PROMs
Data Sheet Minimum Time from VCC, min. to Select = Low
SPI Flash PROM
Part Number
Vendor
Symbol
TVSL
Value
10
Units
µs
STMicroelectronics
NexFlash
M25Pxx
NX25xx
TVSL
10
µs
Silicon Storage Technology
SST25LFxx
TPU-READ
10
µs
Programmable
Microelectronics Corporation
Pm25LVxxx
AT45DBxx
TVCS
50
20
µs
Atmel Corporation
ms
In many systems, the 3.3V supply feeding the FPGA's
VCCO_2 input is valid before the FPGA's other VCCINT
and VCCAUX supplies, and consequently, there is no issue.
However, if the 3.3V supply feeding the FPGA's VCCO_2
supply is last in the sequence, a potential race occurs
between the FPGA and the SPI Flash PROM, as shown in
Figure 52.
minimum in Module 3), after which the FPGA deasserts
INIT_B, selects the SPI Flash PROM, and starts sending
the appropriate read command. The SPI Flash PROM must
be ready for read operations at this time.
If the 3.3V supply is last in the sequence and does not ramp
fast enough, or if the SPI Flash PROM cannot be ready
when required by the FPGA, delay the FPGA configuration
process by holding either the FPGA's PROG_B input or
INIT_B input Low, as highlighted in Figure 51. Release the
FPGA when the SPI Flash PROM is ready. For example, a
simple R-C delay circuit attached to the INIT_B pin forces
the FPGA to wait for a preselected amount of time. Alter-
nately, a Power Good signal from the 3.3V supply or a sys-
tem reset signal accomplishes the same purpose. Use an
open-drain or open-collector output when driving PROG_B
or INIT_B.
If the FPGA's VCCINT and VCCAUX supplies are already
valid, then the FPGA waits for VCCO_2 to reach its mini-
mum threshold voltage before starting configuration. This
threshold voltage is labeled as VCCO2T in Module 3 and
ranges from approximately 0.4V to 1.0V, substantially lower
than the SPI Flash PROM's minimum voltage. Once all
three FPGA supplies reach their respective Power On
Reset (POR) thresholds, the FPGA starts the configuration
process and begins initializing its internal configuration
memory. Initialization requires approximately 1 ms (TPOR
,
3.3V Supply
SPI Flash cannot be selected
SPI Flash PROM
minimum voltage
SPI Flash available for
read operations
SPI Flash
PROM CS
SPI Flash PROM must
be ready for FPGA
access otherwise delay
FPGA configuration
delay(tVSL
)
FPGA VCCO_2 minimum
Power On Reset Voltage
(VCCO2T
)
FPGA accesses
SPI Flash PROM
FPGA initializes configuration
(VCCINT, VCCAUX
already valid)
memory (T
)
POR
Time
DS312-2_50b_022405
Figure 52: SPI Flash PROM/FPGA Power-On Timing if 3.3V Supply is Last in Power-On Sequence
68
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Functional Description
ing for the SPI Flash device. Without examining the timing
for a specific SPI Flash PROM, use ConfigRate = 12,
which is approximately 12 MHz. SPI Flash PROMs that sup-
port the FAST READ command support higher data rates.
Some such PROMs support up to ConfigRate = 25 and
beyond but require careful data sheet analysis.
SPI Flash PROM Density Requirements
Table 49 shows the smallest usable SPI Flash PROM to
program a single Spartan-3E FPGA. Commercially avail-
able SPI Flash PROMs range in density from 1 Mbit to 128
Mbits. A multiple-FPGA daisy-chained application requires
a SPI Flash PROM large enough to contain the sum of the
FPGA file sizes. An application can also use a larger-den-
sity SPI Flash PROM to hold additional data beyond just
FPGA configuration data. For example, the SPI Flash
PROM can also store application code for a MicroBlaze™
RISC processor core integrated in the Spartan-3E FPGA.
See Using the SPI Flash Interface after Configuration.
Using the SPI Flash Interface after Configuration
After the FPGA successfully completes configuration, all of
the pins connected to the SPI Flash PROM are available as
user-I/O pins.
If not using the SPI Flash PROM after configuration, drive
CSO_B High to disable the PROM. The MOSI, DIN, and
CCLK pins are then available to the FPGA application.
Table 49: Number of Bits to Program a Spartan-3E
Because all the interface pins are user I/O after configura-
tion, the FPGA application can continue to use the SPI
Flash interface pins to communicate with the SPI Flash
PROM, as shown in Figure 53. SPI Flash PROMs offer ran-
dom-accessible, byte-addressable, read/write, non-volatile
storage to the FPGA application.
FPGA and Smallest SPI Flash PROM
Number of
Configuration
Bits
Smallest Usable
SPI Flash PROM
Device
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
581,344
1,352,192
2,267,136
3,832,320
5,957,760
1 Mbit
2 Mbit
4 Mbit
4 Mbit
8 Mbit
SPI Flash PROMs are available in densities ranging from
1 Mbit up to 128 Mbits. However, a single Spartan-3E FPGA
requires less than 6 Mbits. If desired, use a larger SPI Flash
PROM to contain additional non-volatile application data,
such as MicroBlaze processor code, or other user data such
as serial numbers and Ethernet MAC IDs. In the example
shown in Figure 53, the FPGA configures from SPI Flash
PROM. Then using FPGA logic after configuration, the
FPGA copies MicroBlaze code from SPI Flash into external
DDR SDRAM for code execution. Similarly, the FPGA appli-
cation can store non-volatile application data within the SPI
Flash PROM.
CCLK Frequency
In SPI Flash mode, the FPGA’s internal oscillator generates
the configuration clock frequency. The FPGA provides this
clock on its CCLK output pin, driving the PROM’s clock input
pin. The FPGA starts configuration at its lowest frequency
and increases its frequency for the remainder of the config-
uration process if so specified in the configuration bitstream.
The maximum frequency is specified using the ConfigRate
bitstream generator option. The maximum frequency sup-
ported by the FPGA configuration logic depends on the tim-
The FPGA configuration data is stored starting at location 0.
Store any additional data beginning in the next available SPI
Flash PROM sector or page. Do not mix configuration data
and user data in the same sector or page.
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Functional Description
Spartan-3E FPGA
SPI Serial Flash PROM
FFFFF
User Data
MOSI
DATA_IN
DATA_OUT
CLOCK
MicroBlaze
Code
DIN
CCLK
FPGA-based
SPI Master
FPGA
CSO_B
SELECT
Configuration
+3.3V
0
User-I/O
SPI Peripherals
• A/D Converter
• D/A Converter
• CAN Controller
DATA_IN
DATA_OUT
CLOCK
• Temperature Sensor
• Displays
• Temperature Sensor
• Microcontroller
• ASSP
SELECT
DS312-2_47_022205
To other SPI slave peripherals
Figure 53: Using the SPI Flash Interface After Configuration
Similarly, the SPI bus can be expanded to additional SPI
peripherals. Because SPI is a common industry-standard
interface, there are a variety of SPI-based peripherals avail-
able, including analog-to-digital (A/D) converters, digi-
tal-to-analog (D/A) converters, CAN controllers, and
temperature sensors.
peripheral data sheet for specific interface and communica-
tion protocol requirements.
Daisy-Chaining
If the application requires multiple FPGAs with different con-
figurations, then configure the FPGAs using a daisy chain,
as shown in Figure 54. Use SPI Flash mode
(M[2:0] = <0:0:1>) for the FPGA connected to the Platform
Flash PROM and Slave Serial mode (M[2:0] = <1:1:1>) for
all other FPGAs in the daisy-chain. After the master
FPGA—the FPGA on the left in the diagram—finishes load-
ing its configuration data from the SPI Flash PROM, the
master device uses its DOUT output pin to supply data to
the next device in the daisy-chain, on the falling CCLK edge.
The MOSI, DIN, and CCLK pins are common to all SPI
peripherals. Connect the select input on each additional SPI
peripheral to one of the FPGA user I/O pins. If HSWAP = 0
during configuration, the FPGA holds the select line High. If
HSWAP = 1, connect the select line to +3.3V via an external
4.7 kΩ pull-up resistor to avoid spurious read or write oper-
ations. After configuration, drive the select line Low to select
the desired SPI peripheral. Refer to the individual SPI
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Functional Description
CCLK
+1.2V
+1.2V
+3.3V
SPI
Serial
Flash
VCCINT
VCCINT
P
P
HSWAP
VCCO_0
VCCO_0
+3.3V
P
HSWAP
VCCO_0
VCCO_0
+3.3V
I
VCC
DATA_IN
VCCO_2
MOSI
VCCO_2
Slave
Serial
Mode
SPI Mode
DIN
DATA_OUT
SELECT
‘0’
‘0’
‘1’
M2
M1
M0
CSO_B
‘1’
‘1’
‘1’
M2
M1
M0
W
WR_PROTECT
HOLD
‘1’
CLOCK
Variant Select
Spartan-3E
FPGA
Spartan-3E
FPGA
GND
‘1’
S
VS2
VS1
VS0
‘1’
CCLK
CCLK
DIN
DOUT
INIT_B
DOUT
DOUT
INIT_B
+2.5V
JTAG
TDI
VCCAUX
TDO
+2.5V
VCCAUX
TDO
+2.5V
TDI
TDI
TMS
TCK
TDO
TMS
TCK
TMS
TCK
+2.5V
+3.3V
PROG_B
DONE
PROG_B
DONE
GND
GND
PROG_B
PROG_B
Recommend
open-drain
driver
TCK
TMS
DONE
INIT_B
DS312-2_48_021405
Figure 54: Daisy-Chaining from SPI Flash Mode
to a 24-bit address lines to access an attached parallel
Flash. Only 20 address lines are generated for Spartan-3E
FPGAs in the TQ144 package. The BPI mode is not avail-
able for Spartan-3E FPGAs in the VQ100 package.
In-System Programming Support
I
In a production application, the SPI Flash PROM is usu-
ally pre-programmed before it is mounted on the printed cir-
cuit board. In-system programming support is available
from some third-party PROM programmers using a socket
adapter with attached wires. To gain access to the SPI
Flash signals, drive the FPGA’s PROG_B input Low with an
open-drain driver. This action places all FPGA I/O pins,
including those attached to the SPI Flash, in high-imped-
ance (Hi-Z). If the HSWAP input is High, the I/Os have
pull-up resistors to the VCCO input on their respective I/O
bank. The external programming hardware then has direct
access to the SPI Flash pins. The programming access
points are highlighted in the gray box in Figure 50,
Figure 51, and Figure 54.
The interface is designed for standard parallel NOR Flash
PROMs and supports both byte-wide (x8) and
byte-wide/halfword (x8/x16) PROMs. The interface does not
support halfword-only (x16) PROMs. The interface works
equally wells with other memories that use a similar inter-
face such as SRAM, NVRAM, EEPROM, EPROM, or
masked ROM but is primarily designed for Flash memory.
There is another type of Flash memory called NAND Flash,
which is commonly used in memory cards for digital cam-
eras, etc. Spartan-3E FPGAs do not configure directly from
NAND Flash memories.
The FPGA’s internal oscillator controls the interface timing
and the FPGA supplies the clock on the CCLK output pin.
However, the CCLK signal is not used in single FPGA appli-
cations. Similarly, the FPGA drives three pins Low during
configuration (LDC[2:0]) and one pin High during configura-
tion (HDC) to the PROM’s control inputs.
Byte-Wide Peripheral Interface (BPI) Parallel
Flash Mode
In
Byte-wide
Peripheral
Interface
(BPI)
mode
(M[2:0] = <0:1:0> or <0:1:1>), a Spartan-3E FPGA config-
ures itself from an industry-standard parallel NOR Flash
PROM, as illustrated in Figure 55. The FPGA generates up
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+1.2V
V
VCCINT
HSWAP
VCCO_0
VCCO_0
P
I
VCCO
VCCO_1
LDC0
V
CE#
x8 or
x8/x16
Flash
LDC1
OE#
HDC
WE#
BYTE#
PROM
LDC2
Not available
in VQ100
package
D
A[16:0]
DQ[15:7]
BPI Mode
VCCO_2
D[7:0]
V
‘0’
‘1’
A
M2
M1
M0
DQ[7:0]
A[n:0]
A[23:17]
GND
V
Spartan-3E
FPGA
BUSY
CCLK
‘0’
‘0’
CSI_B
CSO_B
INIT_B
RDWR_B
+2.5V
JTAG
+2.5V
VCCAUX
TDO
+2.5V
TDI
TDI
TMS
TCK
TDO
TMS
TCK
PROG_B
DONE
GND
PROG_B
Recommend
open-drain
driver
DS312-2_49_022305
Figure 55: Byte-wide Peripheral Interface (BPI) Mode Configured from Parallel NOR Flash PROMs
A
During configuration, the value of the M0 mode pin
Depending on the specific processor architecture, the pro-
cessor boots either from the top or bottom of memory. The
FPGA is flexible and boots from the opposite end of mem-
ory from the processor. Only the processor or the FPGA can
boot at any given time. The FPGA can configure first, hold-
ing the processor in reset or the processor can boot first,
asserting the FPGA’s PROG_B pin.
determines how the FPGA generates addresses, as shown
Table 50. When M0 = 0, the FPGA generates addresses
starting at 0 and increments the address on every falling
CCLK edge. Conversely, when M0 = 1, the FPGA gener-
ates addresses starting at 0xFF_FFFF (all ones) and decre-
ments the address on every falling CCLK edge.
The mode select pins, M[2:0], are sampled when the
FPGA’s INIT_B output goes High and must be at defined
logic levels during this time. After configuration, when the
FPGA’s DONE output goes High, the mode pins are avail-
able as full-featured user-I/O pins.
Table 50: BPI Addressing Control
M2
M1
M0 Start Address
Addressing
Incrementing
Decrementing
0
1
0
0
1
Similarly, the FPGA’s HSWAP pin must be Low to
P
0xFF_FFFF
enable pull-up resistors on all user-I/O pins or High to dis-
able the pull-up resistors. The HSWAP control must remain
at a constant logic level throughout FPGA configuration.
After configuration, when the FPGA’s DONE output goes
This addressing flexibility allows the FPGA to share the par-
allel Flash PROM with an external or embedded processor.
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High, the HSWAP pin is available as full-featured user-I/O
pin and is powered by the VCCO_0 supply.
actively drives during configuration and is available as a
user I/O after configuration.
The RDWR_B and CSI_B must be Low throughout the con-
figuration process. After configuration, these pins also
become user I/O.
After configuration, all of the interface pins except DONE
and PROG_B are available as user I/Os. Furthermore, the
bidirectional SelectMAP configuration peripheral interface
(see Slave Parallel Mode) is available after configuration.
To continue using SelectMAP mode, set the Persist bit-
stream generator option to Yes. An external host can then
read and verify configuration data.
In a single-FPGA application, the FPGA’s CSO_B and
CCLK pins are not used but are actively driving during the
configuration process. The BUSY pin is not used but also
Table 51: Byte-Wide Peripheral Interface (BPI) Connections
Pin Name
FPGA Direction
Description
During Configuration
After Configuration
User I/O
Input
User I/O Pull-Up Control. When
Drive at valid logic level
HSWAP
Low during configuration, enables throughout configuration.
pull-up resistors in all I/O pins to
P
respective I/O bank VCCO input.
0: Pull-ups during configuration
1: No pull-ups
M[2:0]
Input
Mode Select. Selects the FPGA
configuration mode.
M2 = 0, M1 = 1. Set M0 = 0 to
start at address 0, increment
addresses. Set M0 = 1 to start at
address 0xFFFFFF and
User I/O
A
decrement addresses. Sampled
when INIT_B goes High.
CSI_B
Input
Input
Chip Select Input. Active Low.
Must be Low throughout
configuration.
User I/O. If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
RDWR_B
Read/Write Control. Active Low
write enable. Read functionality
typically only used after
Must be Low throughout
configuration.
User I/O. If bitstream
option Persist=Yes,
becomes part of
configuration, if bitstream option
Persist=Yes.
SelectMap parallel
peripheral interface.
LDC0
LDC1
HDC
Output
Output
Output
Output
PROM Chip Enable
PROM Output Enable
PROM Write Enable
PROM Byte Mode
Connect to PROM chip-select
input (CE#). FPGA drives this
signal Low throughout
configuration.
User I/O
Connect to PROM output-enable User I/O
input (OE#). FPGA drives this
signal Low throughout
configuration.
Connect to PROM write-enable
input (WE#). FPGA drives this
signal High throughout
configuration.
User I/O
LDC2
D
This signal is not used for x8
PROMs. For PROMs with a
x8/x16 data width control,
connect to PROM byte-mode
input (BYTE#). See Precautions
Using x8/x16 Flash PROMs.
FPGA drives this signal Low
throughout configuration.
User I/O. Drive this pin
High after configuration to
use a x8/x16 PROM in
x16 mode.
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Table 51: Byte-Wide Peripheral Interface (BPI) Connections (Continued)
Pin Name
FPGA Direction
Description
During Configuration
After Configuration
User I/O
A[23:0]
Output
Address
Connect to PROM address
inputs. High order address lines
may not be available in all
packages and not all may be
required. Number of address
lines required depends on the
size of the attached Flash PROM.
FPGA address generation
controlled by M0 mode pin.
Addresses presented on falling
CCLK edge.
Only 20 address lines are
available in TQ144 package.
D[7:0]
CSO_B
BUSY
CCLK
Input
Data Input
FPGA receives byte-wide data on User I/O If bitstream
these pins in response the
address presented on A[23:0].
Data captured by FPGA
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
Output
Output
Output
Chip Select Output. Active Low.
Not used in single FPGA
User I/O
applications. In a daisy-chain
configuration, this pin connects to
the CSI_B pin of the next FPGA in
the chain. Actively drives.
Busy Indicator. Typically only
used after configuration, if
bitstream option Persist=Yes.
Not used during configuration but User I/O. If bitstream
actively drives.
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
Configuration Clock. Generated Not used in single FPGA
User I/O If bitstream
by FPGA internal oscillator.
Frequency controlled by
applications but actively drives. In option Persist=Yes,
a daisy-chain configuration, becomes part of
drives the CCLK inputs of all other SelectMap parallel
ConfigRate bitstream generator
option. If CCLK PCB trace is long
or has multiple connections,
terminate this output to maintain
signal integrity.
FPGAs in the daisy-chain.
peripheral interface.
INIT_B
Open-drain
Initialization Indicator. Active
Active during configuration. If
CRC error detected during
configuration, FPGA drives
INIT_B Low.
User I/O
bidirectional I/O Low. Goes Low at start of
configuration during Initialization
memory clearing process.
Released at end of memory
clearing, when mode select pins
are sampled. In daisy-chain
applications, this signal requires
an external 4.7 kΩ pull-up resistor
to VCCO_2.
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After Configuration
Table 51: Byte-Wide Peripheral Interface (BPI) Connections (Continued)
Pin Name
FPGA Direction
Description
During Configuration
DONE
Open-drain
FPGA Configuration Done. Low
Low indicates that the FPGA is
not yet configured.
Pulled High via external
pull-up. When High,
indicates that the FPGA
successfully configured.
bidirectional I/O during configuration. Goes High
when FPGA successfully
completes configuration. Requires
external 330 Ω pull-up resistor to
2.5V.
PROG_B
Input
Program FPGA. Active Low.
When asserted Low for 300 ns or
longer, forces the FPGA to restart
its configuration process by
clearingconfigurationmemory and
resetting the DONE and INIT_B
pins once PROG_B returns High.
Requires external 4.7 kΩ pull-up
resistor to 2.5V. If driving
Must be High to allow
configuration to start.
Drive PROG_B Low and
release to reprogram
FPGA. Hold PROG_B to
force FPGA I/O pins into
Hi-Z, allowing direct
programming access to
Flash PROM pins.
externally, use an open-drain or
open-collector driver.
shows the minimum required number of address lines
between the FPGA and parallel Flash PROM. The actual
number of address line required depends on the density of
the attached parallel Flash PROM.
Voltage Compatibility
V
The FPGA’s parallel Flash interface signals are within
I/O Banks 1 and 2. The majority of parallel Flash PROMs
use a single 3.3V supply voltage. Consequently, in most
cases, the FPGA’s VCCO_1 and VCCO_2 supply voltages
must also be 3.3V to match the parallel Flash PROM. There
are some 1.8V parallel Flash PROMs available and the
FPGA interfaces with these devices if the VCCO_1 and
VCCO_2 supplies are also 1.8V.
A multiple-FPGA daisy-chained application requires a par-
allel Flash PROM large enough to contain the sum of the
FPGA file sizes. An application may also use a larger-den-
sity parallel Flash PROM to hold additional data beyond just
FPGA configuration data. For example, the parallel Flash
PROM could also contain the application code for a Micro-
Blaze RISC processor core implemented within the Spar-
tan-3E FPGA. After configuration, the MicroBlaze processor
could execute directly from external Flash or could copy the
code to other, faster system memory before executing the
code.
Supported Parallel NOR Flash PROM Densities
Table 52 indicates the smallest usable parallel Flash PROM
to program a single Spartan-3E FPGA. Parallel Flash den-
sity is specified in bits but addressed as bytes. The FPGA
presents up to 24 address lines during configuration but not
all are required for single FPGA applications. Table 52
Table 52: Number of Bits to Program a Spartan-3E FPGA and Smallest Parallel Flash PROM
Uncompressed
File Sizes (bits)
Smallest Usable Parallel
Flash PROM
Minimum Required Address
Lines
Device
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
581,344
1,352,192
2,267,136
3,832,320
5,957,760
1 Mbit
2 Mbit
4 Mbit
4 Mbit
8 Mbit
A[16:0]
A[17:0]
A[18:0]
A[18:0]
A[19:0]
stream. The maximum frequency is specified using the
ConfigRate bitstream generator option. Table 53 shows the
maximum ConfigRate settings, approximately equal to
MHz, for various PROM read access times. Despite using
slower ConfigRate settings, BPI mode is equally fast as the
other configuration modes. In BPI mode, data is accessed
CCLK Frequency
In BPI mode, the FPGA’s internal oscillator generates the
configuration clock frequency that controls all the interface
timing. The FPGA starts configuration at its lowest fre-
quency and increases its frequency for the remainder of the
configuration process if so specified in the configuration bit-
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Functional Description
at the ConfigRate frequency and internally serialized with
an 8X clock frequency.
ous read or write operations. After configuration, drive the
select line Low to select the desired peripheral. Refer to the
individual peripheral data sheet for specific interface and
communication protocol requirements.
Table 53: Maximum ConfigRate Settings for Parallel
Flash PROMs
The FPGA optionally supports a 16-bit peripheral interface
by driving the LDC2 (BYTE#) control pin High after configu-
ration. See Precautions Using x8/x16 Flash PROMs for
additional information.
Maximum ConfigRate
Flash Read Access Time
< 200 ns
Setting
3
6
The FPGA provides up to 24 address lines during configu-
ration, addressing up to 128 Mbits (16 Mbytes). If using a
larger parallel PROM, connect the upper address lines to
FPGA user I/O. During configuration, the upper address
lines will be pulled High if HSWAP = 0. Otherwise, use
external pull-up or pull-down resistors on these address
lines to define their values during configuration.
< 90 ns
Using the BPI Interface after Configuration
After the FPGA successfully completes configuration, all of
the pins connected to the parallel Flash PROM are available
as user I/Os.
If not using the parallel Flash PROM after configuration,
drive LDC0 High to disable the PROM’s chip-select input.
The remainder of the BPI pins then become available to the
FPGA application, including all 24 address lines, the eight
data lines, and the LDC2, LDC1, and HDC control pins.
Precautions Using x8/x16 Flash PROMs
D
Most low- to mid-density PROMs are byte-wide (x8)
only. Many higher-density Flash PROMs support both
byte-wide (x8) and halfword-wide (x16) data paths and
include a mode input called BYTE# that switches between
x8 or x16. During configuration, Spartan-3E FPGAs only
support byte-wide data. However, after configuration, the
FPGA supports either x8 or x16 modes. In x16 mode, up to
eight additional user I/O pins are required for the upper data
bits, D[15:8].
Because all the interface pins are user I/Os after configura-
tion, the FPGA application can continue to use the interface
pins to communicate with the parallel Flash PROM. Parallel
Flash PROMs are available in densities ranging from 1 Mbit
up to 128 Mbits and beyond. However, a single Spartan-3E
FPGA requires less than 6 Mbits for configuration. If
desired, use a larger parallel Flash PROM to contain addi-
tional non-volatile application data, such as MicroBlaze pro-
cessor code, or other user data such as serial numbers,
Ethernet MAC IDs, etc. In such an example, the FPGA con-
figures from parallel Flash PROM. Then using FPGA logic
after configuration, a MicroBlaze processor embedded
within the FPGA can either execute code directly from par-
allel Flash PROM or copy the code to external DDR
SDRAM and execute from DDR SDRAM. Similarly, the
FPGA application can store non-volatile application data
within the parallel Flash PROM.
Connecting a Spartan-3E FPGA to a x8/x16 Flash PROM is
simple, but does require a precaution. Various Flash PROM
vendors use slightly different interfaces to support both x8
and x16 modes. Some vendors (Intel, Micron, some STMi-
croelectronics devices) use a straightforward interface with
pin naming that matches the FPGA connections. However,
the PROM’s A0 pin is wasted in x16 applications and a sep-
arate FPGA user-I/O pin is required for the D15 data line.
Fortunately, the FPGA A0 pin is still available as a user I/O
after configuration, even though it connects to the Flash
PROM.
Other vendors (AMD, Atmel, Silicon Storage Technology,
some STMicroelectronics devices) use a pin-efficient inter-
face but change the function of one pin, called IO15/A-1,
depending if the PROM is in x8 or x16 mode. In x8 mode,
BYTE# = 0, this pin is the least-significant address line. The
A0 address line selects the halfword location. The A-1
address line selects the byte location. When in x16 mode,
BYTE# = 1, the IO15/A-1 pin becomes the most-significant
data bit, D15 because byte addressing is not required in this
mode. Check to see if the Flash PROM has a pin named
“IO15/A-1" or "DQ15/A-1". If so, be careful to connect
x8/x16 Flash PROMs correctly, as shown in Table 54. Also,
remember that the D[14:8] data connections require FPGA
user I/O pins but that the D15 data is already connected for
the FPGA’s A0 pin.
The FPGA configuration data is stored starting at either at
location 0 or the top of memory (addresses all ones) or at
both locations for MultiBoot mode. Store any additional data
beginning in other available parallel Flash PROM sectors.
Do not mix configuration data and user data in the same
sector.
Similarly, the parallel Flash PROM interface can be
expanded to additional parallel peripherals.
The address, data, and LDC1 (OE#) and HDC (WE#) con-
trol signals are common to all parallel peripherals. Connect
the chip-select input on each additional peripheral to one of
the FPGA user I/O pins. If HSWAP = 0 during configuration,
the FPGA holds the chip-select line High via an internal
pull-up resistor. If HSWAP = 1, connect the select line to
+3.3V via an external 4.7 kΩ pull-up resistor to avoid spuri-
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Table 54: FPGA Connections to Flash PROM with "IO15/A-1" Pin
Connection to Flash PROM with
IO15/A-1 Pin
x8 Flash PROM Interface After x16 Flash PROM Interface After
FPGA Pin
FPGA Configuration
FPGA Configuration
LDC2
BYTE#
Drive LDC2 Low or leave
unconnected and tie PROM
BYTE# input to GND
Drive LCD2 High
LDC1
LDC0
HDC
OE#
CS#
WE#
Active-Low Flash PROM
output-enable control
Active-Low Flash PROM
output-enable control
Active-Low Flash PROM
chip-select control
Active-Low Flash PROM
chip-select control
Flash PROM write-enable
control
Flash PROM write-enable control
A[23:1]
A0
A[n:0]
A[n:0]
A[n:0]
IO15/A-1
IO15/A-1 is least-significant
address input
IO15/A-1 is most-significant data
line, IO15
D[7:0]
IO[7:0]
IO[7:0]
IO[7:0]
User I/O
Upper data lines IO[14:8] not
required unless used as x16 Flash
interface after configuration
Upper data lines IO[14:8] not
required
IO[14:8]
next FPGA in the daisy-chain. The next FPGA then receives
parallel configuration data from the Flash PROM. The mas-
ter FPGA’s CCLK output synchronizes data capture.
Daisy-Chaining
If the application requires multiple FPGAs with different con-
figurations, then configure the FPGAs using a daisy chain,
as shown in Figure 56. Use BPI mode (M[2:0] = <0:1:0> or
<0:1:1>) for the FPGA connected to the parallel NOR Flash
PROM and Slave Parallel mode (M[2:0] = <1:1:0>) for all
other FPGAs in the daisy-chain. After the master
FPGA—the FPGA on the left in the diagram—finishes load-
ing its configuration data from the parallel Flash PROM, the
master device continues generating addresses to the Flash
PROM and asserts its CSO_B output Low, enabling the
The downstream devices in Slave Parallel mode also
actively drive their LDC[2:0] and HDC outputs during config-
uration, although these signal are not used for configura-
tion. These pins are in I/O Bank 1, powered by VCCO_1.
Because these pins do not connect elsewhere in the config-
uration circuit, the voltage on VCCO_1 can be whatever is
required by the end application.
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CCLK
D[7:0]
+1.2V
+1.2V
V
VCCINT
VCCINT
P
HSWAP
VCCO_0
VCCO_0
P
HSWAP
VCCO_0
VCCO_0
VCCO_1
I
VCC
VCCO_1
LDC0
V
VCCO_1
LDC0
LDC1
HDC
CE#
x8 or
x8/x16
Flash
PROM
LDC1
OE#
HDC
WE#
BYTE#
LDC2
LDC2
Not available
in VQ100
package
D
A[16:0]
Slave
Parallel
Mode
DQ[15:7]
BPI Mode
VCCO_2
D[7:0]
VCCO_2
D[7:0]
V
V
‘0’
‘1’
A
M2
M1
M0
DQ[7:0]
A[n:0]
‘1’
‘1’
‘0’
M2
M1
M0
A[23:17]
GND
Spartan-3E
FPGA
Spartan-3E
FPGA
BUSY
CCLK
BUSY
CCLK
‘0’
CSI_B
CSO_B
INIT_B
CSI_B
CSO_B
INIT_B
CSO_B
‘0’
RDWR_B
‘0’
RDWR_B
2.5V
JTAG
VCCAUX
TDO
+2.5V
VCCAUX
TDO
+2.5V
TDI
TDI
TDI
TMS
TMS
TCK
TMS
TCK
TCK
V
+2.5V
TDO
PROG_B
DONE
PROG_B
DONE
GND
GND
PROG_B
PROG_B
Recommend
open-drain
driver
TCK
TMS
DONE
INIT_B
DS312-2_50_021405
Figure 56: Daisy-Chaining from BPI Flash Mode
In-System Programming Support
Dynamically Loading Multiple Configuration
Images Using MultiBoot Option
I
In a production application, the parallel Flash PROM is
usually preprogrammed before it is mounted on the printed
circuit board. In-system programming support is available
from third-party boundary-scan tool vendors and from some
third-party PROM programmers using a socket adapter with
attached wires. To gain access to the parallel Flash signals,
drive the FPGA’s PROG_B input Low with an open-drain
driver. This action places all FPGA I/O pins, including those
attached to the parallel Flash, in high-impedance (Hi-Z). If
the HSWAP input is High, the I/Os have pull-up resistors to
the VCCO input on their respective I/O bank. The external
programming hardware then has direct access to the paral-
lel Flash pins. The programming access points are high-
lighted in the gray boxes in Figure 55 and Figure 56.
After the FPGA configures itself using BPI mode from one
end of the parallel Flash PROM, then the FPGA can trigger
a MultiBoot event and reconfigure itself from the opposite
end of the parallel Flash PROM. MultiBoot is only available
when using BPI mode and only for applications with a single
Spartan-3E FPGA.
By default, MultiBoot mode is disabled. To trigger a Multi-
Boot event, assert a Low pulse lasting at least 300 ns on the
MultiBoot Trigger (MBT) input to the STARTUP_SPARTAN3E
library primitive. Figure 57 shows an example usage. At
power up, the FPGA loads itself from the attached parallel
Flash PROM. In this example, the M0 mode pin is Low so
the FPGA starts at address 0 and increments through the
Flash PROM memory locations. After the FPGA completes
configuration, the application loaded into the FPGA per-
forms a board-level or system test using FPGA logic. If the
test is successful, the FPGA triggers a MultiBoot event,
causing the FPGA to reconfigure from the opposite end of
the Flash PROM memory. This second configuration con-
tains the FPGA application for normal operation.
The FPGA itself can also be used as a parallel Flash PROM
programmer during development and test phases. Initially,
an FPGA-based programmer is downloaded into the FPGA
via JTAG. Then the FPGA performs the Flash PROM pro-
gramming algorithms and receives programming data from
the host via the FPGA’s JTAG interface. See Chapter 11 in
"Embedded System Tools Reference Manual".
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Parallel Flash PROM
Parallel Flash PROM
FFFFFF
FFFFFF
General
FPGA
Application
General
FPGA
Application
STARTUP_SPARTAN3E
GSR
User Area
GTS
MBT
User Area
> 300 ns
CLK
Diagnostics
FPGA
Application
Diagnostics
FPGA
Application
Reconfigure
0
0
Second Configuration
First Configuration
DS312-2_51_021405
Figure 57: Use MultiBoot to Load Alternate Configuration Images
Similarly, the general FPGA application could trigger a
MultiBoot event at any time to reload the diagnostics design.
ever, the FPGA does not assert the PROG_B pin. The sys-
tem design must ensure that no other device drives on
these same pins during the reconfiguration process. The
FPGA’s DONE, LDC[2:0], or HDC pins can temporarily dis-
able any conflicting drivers during reconfiguration.
In another potential application, the initial design loaded into
the FPGA image contains a “golden” or “fail-safe” configura-
tion image, which then communicates with the outside world
and checks for a newer image. If there is a new configura-
tion revision and the new image verifies as good, the
“golden” configuration triggers a MultiBoot event to load the
new image.
Slave Parallel Mode
In Slave Parallel mode (M[2:0] = <1:1:0>), an external host
such as a microprocessor or microcontroller writes
byte-wide configuration data into the FPGA, using a typical
peripheral interface as shown in Figure 58.
When a MultiBoot event is triggered, the FPGA then again
drives its configuration pins as described in Table 51. How-
DS312-2 (v1.1) March 21, 2005
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Functional Description
+1.2V
VCCINT
P
HSWAP
VCCO_0
VCCO_0
VCCO_1
VCCO_1
LDC0
LDC1
HDC
Slave
Parallel
Mode
LDC2
VCCO_2
V
V
‘1’
‘1’
‘0’
M2
M1
M0
Intelligent
Download Host
V
VCC
Spartan-3E
FPGA
D[7:0]
D[7:0]
BUSY
CSI_B
Configuration
Memory
Source
BUSY
SELECT
CSO_B
INIT_B
READ/WRITE
CLOCK
RDWR_B
CCLK
• Internal memory
• Disk drive
PROG_B
DONE
• Over network
• Over RF link
VCCAUX
TDO
+2.5V
INIT_B
TDI
TMS
TCK
GND
+2.5V
• Microcontroller
• Processor
• Tester
PROG_B
DONE
GND
• Computer
PROG_B
Recommend
open-drain +2.5V
driver
JTAG
TDI
TMS
TCK
TDO
DS312-2_52_022205
Figure 58: Slave Parallel Configuration Mode
The external download host starts the configuration process
by pulsing PROG_B and monitoring that the INIT_B pin
goes High, indicating that the FPGA is ready to receive its
first data. The host asserts the active-Low chip-select signal
(CSI_B) and the active-Low Write signal (RDWR_B). The
host then continues supplying data and clock signals until
either the FPGA’s DONE pin goes High, indicating a suc-
cessful configuration, or until the FPGA’s INIT_B pin goes
Low, indicating a configuration error.
is 50 MHz or below, the BUSY pin may be ignored but
actively drives during configuration.
The configuration process requires more clock cycles than
indicated from the configuration file size. Additional clocks
are required during the FPGA’s start-up sequence, espe-
cially if the FPGA is programmed to wait for selected Digital
Clock Managers (DCMs) to lock to their respective clock
inputs (see Start-Up, page 91).
If the Slave Parallel interface is only used to configure the
FPGA, never to read data back, then the RDWR_B signal
can also be eliminated from the interface. However,
RDWR_B must remain Low during configuration.
The FPGA captures data on the rising CCLK edge. If the
CCLK frequency exceeds 50 MHz, then the host must also
monitor the FPGA’s BUSY output. If the FPGA asserts
BUSY High, the host must hold the data for an additional
clock cycle, until BUSY returns Low. If the CCLK frequency
80
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Functional Description
After configuration, all of the interface pins except DONE
and PROG_B are available as user I/Os. Alternatively, the
bidirectional SelectMAP configuration interface is available
after configuration. To continue using SelectMAP mode, set
the Persist bitstream generator option to Yes. The external
host can then read and verify configuration data.
The Slave Parallel mode is also used with BPI mode to cre-
ate multi-FPGA daisy-chains. The lead FPGA is set for BPI
mode configuration; all the downstream daisy-chain FPGAs
are set for Slave Parallel configuration, as highlighted in
Figure 56.
Table 55: Slave Parallel Mode Connections
Pin Name
FPGA Direction
Description
During Configuration
After Configuration
User I/O
HSWAP
Input
User I/O Pull-Up Control. When
Low during configuration, enables
pull-up resistors in all I/O pins to
respective I/O bank VCCO input.
Drive at valid logic level
throughout configuration.
0: Pull-ups during configuration
1: No pull-ups
M[2:0]
D[7:0]
Input
Input
Mode Select. Selects the FPGA
configuration mode.
M2 = 1, M1 = 1, M0 = 0 Sampled User I/O
when INIT_B goes High.
Data Input.
Byte-wide data provided by host. User I/O. If bitstream
FPGA captures data on rising
CCLK edge.
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
BUSY
Output
Busy Indicator.
If CCLK frequency is < 50 MHz,
this pin may be ignored. When
User I/O. If bitstream
option Persist=Yes,
High, indicates that the FPGA is becomes part of
not ready to receive additional
configuration data. Host must
hold data an additional clock
cycle.
SelectMap parallel
peripheral interface.
CSI_B
Input
Input
Input
Chip Select Input. Active Low.
Must be Low throughout
configuration.
User I/O. If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
RDWR_B
CCLK
Read/Write Control. Active Low
write enable.
Must be Low throughout
configuration.
User I/O. If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
Configuration Clock. If CCLK
PCB trace is long or has multiple
connections, terminate this output
to maintain signal integrity.
External clock.
User I/O If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
LDC[2:0]
HDC
Output
Output
Low During Configuration.
High During Configuration.
These pins are not used during
configuration. Low throughout
configuration.
User I/O
This pin is not used during
configuration. High throughout
configuration.
User I/O
DS312-2 (v1.1) March 21, 2005
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Functional Description
Table 55: Slave Parallel Mode Connections (Continued)
Pin Name
FPGA Direction
Description
During Configuration
After Configuration
User I/O
CSO_B
Output
Chip Select Output. Active Low.
Not used in single FPGA
applications. In a daisy-chain
configuration, this pin connects
to the CSI_B pin of the next
FPGA in the chain. Actively
drives.
INIT_B
Open-drain
InitializationIndicator. ActiveLow. Active during configuration. If
User I/O
bidirectional I/O Goes Low at start of configuration
during Initialization memory
CRC error detected during
configuration, FPGA drives
INIT_B Low.
clearing process. Released at end
of memory clearing, when mode
select pins are sampled. In
daisy-chain applications, this signal
requires an external 4.7 kΩ pull-up
resistor to VCCO_2.
DONE
Open-drain
FPGA Configuration Done. Low
Low indicates that the FPGA is
not yet configured.
Pulled High via external
pull-up. When High,
indicates that the FPGA
successfully configured.
bidirectional I/O during configuration. Goes High
when FPGA successfully
completes configuration. Requires
external 330 Ω pull-up resistor to
2.5V.
PROG_B
Input
Program FPGA. Active Low. When Must be High to allow
Drive PROG_B Low and
release to reprogram
FPGA.
asserted Low for 300 ns or longer,
forces the FPGA to restart its
configuration to start.
configuration process by clearing
configuration memory and resetting
the DONE and INIT_B pins once
PROG_B returns High. Requires
external 4.7 kΩ pull-up resistor to
2.5V. If driving externally, use an
open-drain or open-collector driver.
Voltage Compatibility
Daisy-Chaining
V
Most Slave Parallel interface signals are within the
If the application requires multiple FPGAs with different con-
figurations, then configure the FPGAs using a daisy chain.
Use Slave Parallel mode (M[2:0] = <1:1:0>) for all FPGAs in
the daisy-chain. The schematic in Figure 59 is optimized for
FPGA downloading and does not support the SelectMAP
read interface. The FPGA’s RDWR_B pin must be Low dur-
ing configuration.
FPGA’s I/O Bank 2, supplied by the VCCO_2 supply input.
The VCCO_2 voltage can be 1.8V, 2.5V, or 3.3V to match
the requirements of the external host, ideally 2.5V. Using
1.8V or 3.3V requires additional design considerations as
the DONE and PROG_B pins are powered by the FPGA’s
2.5V VCCAUX supply. See application note XAPP453: "The
3.3V Configuration of Spartan-3 FPGAs" for additional infor-
mation.
After the lead FPGA is filled with its configuration data, the
lead FPGA enables the next FPGA in the daisy-chain by
asserting is chip-select output, CSO_B.
The LDC[2:0] and HDC signal are active in I/O Bank 1 but
are not used in the interface. Consequently, VCCO_1 can
be set the appropriate voltage for the application.
82
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Functional Description
D[7:0]
CCLK
+1.2V
+1.2V
VCCINT
VCCINT
P
HSWAP
VCCO_0
VCCO_0
VCCO_1
P
HSWAP
VCCO_0
VCCO_0
VCCO_1
VCCO_1
LDC0
LDC1
HDC
VCCO_1
LDC0
LDC1
HDC
Slave
Parallel
Mode
Slave
Parallel
Mode
LDC2
LDC2
VCCO_2
VCCO_2
V
V
V
V
‘1’
‘1’
‘0’
M2
M1
M0
‘1’
‘1’
‘0’
M2
M1
M0
Intelligent
Download Host
VCC
DATA[7:0]
BUSY
Spartan-3E
FPGA
Spartan-3E
FPGA
D[7:0]
BUSY
CSI_B
D[7:0]
BUSY
Configuration
Memory
Source
SELECT
READ/WRITE
CLOCK
CSO_B
INIT_B
CSI_B
CSO_B
INIT_B
CSO_B
‘0’
RDWR_B
CCLK
‘0’
RDWR_B
CCLK
•Internal memory
•Disk drive
PROG_B
DONE
•Over network
•Over RF link
VCCAUX
TDO
+2.5V
VCCAUX
TDO
+2.5V
INIT_B
TDI
TDI
TMS
TCK
TMS
TCK
GND
+2.5V
•Microcontroller
•Processor
•Tester
PROG_B
DONE
PROG_B
DONE
GND
GND
PROG_B
PROG_B
DONE
Recommend
open-drain
driver
2.5V
JTAG
INIT_B
TDI
TMS
TCK
TDO
TMS
TCK
DS312-2_53_022305
Figure 59: Daisy-Chaining using Slave Parallel Mode
indicating that the FPGA is ready to receive its first data.
The host then continues supplying data and clock signals
until either the DONE pin goes High, indicating a successful
configuration, or until the INIT_B pin goes Low, indicating a
configuration error. The configuration process requires
more clock cycles than indicated from the configuration file
size. Additional clocks are required during the FPGA’s
start-up sequence, especially if the FPGA is programmed to
wait for selected Digital Clock Managers (DCMs) to lock to
their respective clock inputs (see Start-Up, page 91).
Slave Serial Mode
In Slave Serial mode (M[2:0] = <1:1:1>), an external host
such as a microprocessor or microcontroller writes serial
configuration data into the FPGA, using the synchronous
serial interface shown in Figure 60. The serial configuration
data is presented on the FPGA’s DIN input pin with suffi-
cient setup time before each rising edge of the externally
generated CCLK clock input.
The intelligent host starts the configuration process by puls-
ing PROG_B and monitoring that the INIT_B pin goes High,
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Functional Description
+1.2V
VCCINT
P
HSWAP
VCCO_0
VCCO_0
VCCO_2
V
Slave
Serial
Mode
V
‘1’
‘1’
‘1’
M2
M1
M0
Intelligent
Download Host
V
VCC
Spartan-3E
FPGA
Configuration
Memory
CLOCK
CCLK
DIN
Source
SERIAL_OUT
PROG_B
DONE
DOUT
INIT_B
• Internal memory
• Disk drive
VCCAUX
TDO
+2.5V
INIT_B
TDI
• Over network
• Over RF link
GND
TMS
TCK
+2.5V
• Microcontroller
• Processor
• Tester
PROG_B
DONE
GND
• Computer
PROG_B
Recommend
open-drain
driver
+2.5V
JTAG
TDI
TMS
TCK
TDO
DS312-2_54_022305
Figure 60: Slave Serial Configuration
The mode select pins, M[2:0], are sampled when the
FPGA’s INIT_B output goes High and must be at defined
logic levels during this time. After configuration, when the
FPGA’s DONE output goes High, the mode pins are avail-
able as full-featured user-I/O pins.
Similarly, the FPGA’s HSWAP pin must be Low to
P
enable pull-up resistors on all user-I/O pins or High to dis-
able the pull-up resistors. The HSWAP control must remain
at a constant logic level throughout FPGA configuration.
After configuration, when the FPGA’s DONE output goes
High, the HSWAP pin is available as full-featured user-I/O
pin and is powered by the VCCO_0 supply.
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Functional Description
Table 56: Slave Serial Mode Connections
Pin Name
FPGA Direction
Description
During Configuration
After Configuration
HSWAP
Input
User I/O Pull-Up Control. When Drive at valid logic level
Low during configuration, enables throughout configuration.
pull-up resistors in all I/O pins to
User I/O
respective I/O bank VCCO input.
0: Pull-up during configuration
1: No pull-ups
M[2:0]
DIN
Input
Input
Mode Select. Selects the FPGA
configuration mode.
M2 = 1, M1 = 1, M0 = 1 Sampled User I/O
when INIT_B goes High.
Data Input.
Serial data provided by host.
FPGA captures data on rising
CCLK edge.
User I/O
User I/O
CCLK
Input
Configuration Clock. If CCLK
PCB trace is long or has multiple
connections, terminate this output
to maintain signal integrity.
External clock.
INIT_B
Open-drain
Initialization Indicator. Active
Active during configuration. If
CRC error detected during
configuration, FPGA drives
INIT_B Low.
User I/O
bidirectional I/O Low. Goes Low at start of
configuration during Initialization
memory clearing process.
Released at end of memory
clearing, when mode select pins
are sampled. In daisy-chain
applications, this signal requires
an external 4.7 kΩ pull-up resistor
to VCCO_2.
DONE
Open-drain
FPGA Configuration Done. Low Low indicates that the FPGA is
Pulled High via external
pull-up. When High,
indicates that the FPGA
successfully configured.
bidirectional I/O during configuration. Goes High
when FPGA successfully
not yet configured.
completes configuration.
Requires external 330 Ω pull-up
resistor to 2.5V.
PROG_B
Input
Program FPGA. Active Low.
Must be High to allow
Drive PROG_B Low and
release to reprogram
FPGA.
When asserted Low for 300 ns or configuration to start.
longer, forces the FPGA to restart
its configuration process by
clearing configuration memory
and resetting the DONE and
INIT_B pins once PROG_B
returns High. Requires external
4.7 kΩ pull-up resistor to 2.5V. If
driving externally, use an
open-drain or open-collector
driver.
Voltage Compatibility
Daisy-Chaining
V
Most Slave Serial interface signals are within the
If the application requires multiple FPGAs with different con-
figurations, then configure the FPGAs using a daisy chain,
as shown in Figure 61. Use Slave Serial mode
(M[2:0] = <1:1:1>) for all FPGAs in the daisy-chain. After
the lead FPGA is filled with its configuration data, the lead
FPGA passes configuration data via its DOUT output pin to
the next FPGA on the falling CCLK edge.
FPGA’s I/O Bank 2, supplied by the VCCO_2 supply input.
The VCCO_2 voltage can be 3.3V, 2.5V, or 1.8V to match
the requirements of the external host, ideally 2.5V. Using
3.3V or 1.8V requires additional design considerations as
the DONE and PROG_B pins are powered by the FPGA’s
2.5V VCCAUX supply. See application note XAPP453: "The
3.3V Configuration of Spartan-3 FPGAs" for additional infor-
mation.
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Functional Description
CCLK
+1.2V
+1.2V
VCCINT
VCCINT
P
HSWAP
VCCO_0
VCCO_0
P
HSWAP
VCCO_0
VCCO_0
VCCO_2
VCCO_2
V
VCCO_2
Slave
Serial
Mode
Slave
Serial
Mode
V
‘1’
‘1’
‘1’
M2
M1
M0
‘1’
‘1’
‘1’
M2
M1
M0
Intelligent
Download Host
V
VCC
Spartan-3E
FPGA
Spartan-3E
FPGA
Configuration
Memory
Source
CLOCK
CCLK
DIN
CCLK
DIN
SERIAL_OUT
PROG_B
DONE
DOUT
DOUT
DOUT
INIT_B
INIT_B
•
•
•
•
Internal memory
Disk drive
Over network
Over RF link
VCCAUX
TDO
+2.5V
VCCAUX
TDO
+2.5V
INIT_B
TDI
TDI
GND
TMS
TCK
TMS
TCK
+2.5V
•
•
•
•
Microcontroller
Processor
Tester
PROG_B
DONE
PROG_B
DONE
GND
GND
Computer
PROG_B
PROG_B
DONE
Recommend
open-drain
driver
INIT_B
+2.5V
JTAG
TDI
TMS
TCK
TDO
TMS
TCK
DS312-2_55_022305
Figure 61: Daisy-Chaining using Slave Serial Mode
other configuration modes. No other pins are required as
part of the configuration interface.
JTAG Mode
The Spartan-3E FPGA has a dedicated four-wire IEEE
1149.1/1532 JTAG port that is always available any time the
FPGA is powered and regardless of the mode pin settings.
However, when the FPGA mode pins are set for JTAG mode
(M[2:0] = <1:0:1>), the FPGA waits to be configured via the
JTAG port after a power-on event or when PROG_B is
asserted. Selecting the JTAG mode simply disables the
Figure 62 illustrates a JTAG-only configuration interface.
The JTAG interface is easily cascaded to any number of
FPGAs by connecting the TDO output of one device to the
TDI input of the next device in the chain. The TDO output of
the last device in the chain loops back to the port connector.
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Functional Description
+1.2V
+1.2V
VCCINT
VCCINT
P
HSWAP
M2
VCCO_0
VCCO_0
VCCO_2
HSWAP
M2
VCCO_0
VCCO_0
VCCO_2
P
VCCO_2
VCCO_2
JTAG
Mode
JTAG
Mode
‘1’
‘0’
‘1’
‘1’
‘0’
‘1’
Spartan-3E
FPGA
Spartan-3E
FPGA
M1
M0
M1
M0
VCCAUX
+2.5V
VCCAUX
+2.5V
TDI
TDO
TDI
TDO
TMS
TCK
TMS
TCK
PROG_B
DONE
PROG_B
DONE
GND
GND
+2.5V
JTAG
TDI
TMS
TCK
TDO
TMS
TCK
DS312-2_56_021405
Figure 62: JTAG Configuration Mode
or after the PROG_B input is asserted. Power-On Reset
(POR) occurs after the VCCINT, VCCAUX, and the VCCO Bank
2 supplies reach their respective input threshold levels.
After either a POR or PROG_B event, the three-stage con-
figuration process begins.
Voltage Compatibility
The 2.5V VCCAUX supply powers the JTAG interface. All of
the user I/Os are separately powered by their respective
VCCO_# supplies.
When connecting the Spartan-3E JTAG port to a 3.3V inter-
face, the JTAG input pins must be current-limited to 10 mA
or less using series resistors. Similarly, the TDO pin is a
CMOS output powered from +2.5V. The TDO output can
directly drive a 3.3V input but with reduced noise immunity.
See application note XAPP453: "The 3.3V Configuration of
Spartan-3 FPGAs" for additional information.
1. The FPGA clears (initializes) the internal configuration
memory.
2. Configuration data is loaded into the internal memory.
3. The user-application is activated by a start-up process.
Figure 63 is a generalized block diagram of the Spartan-3E
configuration logic, showing the interaction of different
device inputs and Bitstream Generator (BitGen) options. A
flow diagram for the configuration sequence of the Serial
and Parallel modes appears in Figure 64. Figure 65 shows
the Boundary-Scan or JTAG configuration sequence.
Maximum Bitstream Size for Daisy-Chains
The maximum bitstream length supported by Spartan-3E
FPGAs in serial daisy-chains is 4,294,967,264 bits (4
Gbits), roughly equivalent to a daisy-chain with 720
XC3S1600E FPGAs. This is a limit only for serial
daisy-chains where configuration data is passed via the
FPGA’s DOUT pin. There is no such limit for JTAG chains.
Initialization
Configuration automatically begins after power-on or after
asserting the FPGA PROG_B pin, unless delayed using the
FPGA’s INIT_B pin. The FPGA holds the open-drain INIT_B
signal Low while it clears its internal configuration memory.
Externally holding the INIT_B pin Low forces the configura-
tion sequencer to wait until INIT_B again goes High.
Configuration Sequence
The Spartan-3E configuration process is three-stage pro-
cess that begins after the FPGA powers on (a POR event)
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Functional Description
Z
gae
tie
elwr
iasnot
galments
roecalI/Os-Hi
F
t
s
a
e
stor
/IOpins
eptloigcadn
nEab
oinltahcse
lACDMs
adintoCMOS
dLplacitno
ocnfiugr
pAlctoain
anlCMOS
CDMinUser
oinltahcse
t
coniufgr
DS312-2_57_022405
Figure 63: Generalized Spartan-3E FPGA Configuration Logic Block Diagram
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Functional Description
Set PROG_B Low
after Power-On
Power-On
VCCINT >1V
and VCCAUX > 2V
No
and VCCO Bank 4 > 1V
Yes
Yes
Clear configuration
memory
PROG_B = Low
No
No
INIT_ B = High?
Yes
M[2:0] and VS[2:0]
pins are sampled on
INIT_B rising edge
Sample mode pins
Load configuration
data frames
No
INIT_B goes Low.
Abort Start-Up
CRC
correct?
Yes
DONE pin goes High,
signaling end of
configuration
Start-Up
sequence
User mode
No
Yes
Reconfigure?
DS312-2_58_021404
Figure 64: General Configuration Process
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Functional Description
Set PROG_B Low
after Power-On
Power-On
VCCINT >1V
and VCCAUX > 2V
No
and VCCO Bank 4 > 1V
Load
Yes
JPROG
instruction
Clear
configuration
memory
Yes
PROG_B = Low
No
No
INIT_B = High?
Yes
Sample
mode pins
(JTAG port becomes
available)
Load CFG_IN
instruction
Load configuration
data frames
No
CRC
correct?
INIT_B goes Low.
Abort Start-Up
Yes
Synchronous
TAP reset
(Clock five 1's
on TMS)
Load JSTART
instruction
Start-Up
sequence
User mode
No
Yes
Reconfigure?
DS312-2_59_022505
Figure 65: Boundary-Scan Configuration Flow Diagram
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Functional Description
The FPGA signals when the memory-clearing phase is
complete by releasing the open-drain INIT_B pin, allowing
the pin to go High via the external pull-up resistor to
VCCO_2.
Start-Up
At the end of configuration, the Global Set/Reset (GSR) sig-
nal is pulsed, placing all flip-flops in a known state. After
configuration completes, the FPGA switches over to the
user application loaded into the FPGA. The sequence and
timing of how the FPGA switches over is programmable as
is the clock source controlling the sequence.
Loading Configuration Data
Configuration data is then written to the FPGA’s internal
memory. The FPGA holds the Global Set/Reset (GSR) sig-
nal active throughout configuration, holding all FPGA
flip-flops in a reset state. The FPGA signals when the entire
configuration process completes be releasing the DONE
pin, allowing it to go High.
The default start-up sequence appears in Figure 66, where
the Global Three-State signal (GTS) is released one clock
cycle after DONE goes High. This sequence allows the
DONE signal to enable or disable any external logic used
during configuration before the user application in the FPGA
starts driving output signals. One clock cycle later, the Glo-
bal Write Enable (GWE) signal is released. This allows sig-
nals to propagate within the FPGA before any clocked
storage elements such as flip-flops and block ROM are
enabled.
The FPGA configuration sequence can also be initiated by
asserting the PROG_B. Once release, the FPGA begins
clearing its internal configuration memory, and progresses
through the remainder of the configuration process.
Default Cycles
Start-Up Clock
Phase
0
1
2
3
4
5
6 7
DONE
GTS
GWE
Sync-to-DONE
Start-Up Clock
Phase
0
1
2
3
4
5
6 7
DONE High
DONE
GTS
GWE
DS312-2_60_022305
Figure 66: Default Start-Up Sequence
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Functional Description
The relative timing of configuration events is programmed
via the Bitstream Generator (BitGen) options in the Xilinx
development software. For example, the GTS and GWE
events can be programmed to wait for all the DONE pins to
High on all the devices in a multiple-FPGA daisy-chain, forc-
ing the FPGAs to start synchronously. Similarly, the start-up
sequence can be paused at any stage, waiting for selected
DCMs to lock to their respective input clock signals. See
also Stabilizing DCM Clocks Before User Mode, page 48.
Along with the configuration data, it is possible to read back
the contents of all registers, distributed RAM, and block
RAM resources. This capability is used for real-time debug-
ging.
To synchronously control when registers values are cap-
tured for readback, using the CAPTURE_SPARTAN3 library
primitive, which applies for both Spartan-3 and Spartan-3E
FPGA families.
Bitstream Generator (BitGen) Options
The start-up sequence can by synchronized to a clock
within
the
FPGA
application
using
the
Various Spartan-3E FPGA functions are controlled by spe-
cific bits in the configuration bitstream image. These values
are specified when creating the bitstream image with the
Bitstream Generator (BitGen) software.
STARTUP_SPARTAN3E library primitive and by setting the
StartupClk bitstream generator option. The FPGA applica-
tion can optionally assert the Global Set/Reset (GSR) and
Global Three-State signal (GTS) signals via the
STARTUP_SPARTAN3E primitive.
Table 57 provides a list of all BitGen options for Spartan-3E
FPGAs.
Readback
Using Slave Parallel mode, configuration data from the
FPGA can be read back. Readback is supported only in the
Slave Parallel and JTAG modes.
Table 57: Spartan-3E FPGA Bitstream Generator (BitGen) Options
Pins/Function
Affected
Values
(default)
Option Name
Description
ConfigRate
CCLK,
Configuration
3, 6,
12, 25
Sets the approximate frequency, in MHz, of the internal oscillator using for Master
Serial, SPI, and BPI configuration modes. The internal oscillator powers up at its lowest
frequency and the new setting is loaded as part of the configuration bitstream. The
software default value is 6 (~6 MHz).
StartupClk
Configuration,
Startup
Cclk
Default. The CCLK signal (internally or externally generated) controls the startup
sequence when the FPGA transitions from configuration mode to the user mode. See
Start-Up, page 91.
UserClk
A clock signal from within the FPGA application controls the startup sequence when
the FPGA transitions from configuration mode to the user mode. See Start-Up,
page 91. The FPGA application supplies the user clock on the CLK pin on the
STARTUP_SPARTAN3E primitive.
Jtag
The JTAG TCK input controls the startup sequence when the FPGA transitions from
configuration mode to the user mode. See Start-Up, page 91.
UnusedPin
Unused I/O
Pins
Pulldown Default. All unused I/O pins have a pull-down resistor to GND.
Pullup
All unused I/O pins have a pull-up resistor to the VCCO_# supply for its associated I/O
bank.
Pullnone All unused I/O pins are left floating (Hi-Z, high-impedance, three-state). Use external
pull-up or pull-down resistors or logic to apply a valid signal level.
DONE_cycle
DONE pin,
Configuration
Startup
1, 2, 3, 4, Selects the Configuration Startup phase that activates the FPGA’s DONE pin. See
5, 6
Start-Up, page 91.
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Functional Description
Table 57: Spartan-3E FPGA Bitstream Generator (BitGen) Options (Continued)
Pins/Function
Affected
Values
(default)
Option Name
Description
GWE_cycle
All flip-flops,
LUT RAMs,
and SRL16
shift registers,
Block RAM,
Configuration
Startup
1, 2, 3, 4, Selects the Configuration Startup phase that asserts the internal write-enable signal to
5, 6
all flip-flops, LUT RAMs and shift registers (SRL16). It also enables block RAM read
and write operations. See Start-Up, page 91.
Done
Waits for the DONE pin input to go High before asserting the internal write-enable
signal to all flip-flops, LUT RAMs and shift registers (SRL16). Block RAM read and
write operations are enabled at this time.
Keep
Retains the current GWE_cycle setting for partial reconfiguration applications.
GTS_cycle
All I/O pins,
1, 2, 3, 4, Selects the Configuration Startup phase that releases the internal three-state control,
Configuration
5, 6
holding all I/O buffers in high-impedance (Hi-Z). Output buffers actively drive, if so
configured, after this point. See Start-Up, page 91.
Done
Waits for the DONE pin input to go High before releasing the internal three-state
control, holding all I/O buffers in high-impedance (Hi-Z). Output buffers actively drive,
if so configured, after this point.
Keep
Retains the current GTS_cycle setting for partial reconfiguration applications.
The FPGA does not wait for selected DCMs to lock before completing configuration.
LCK_cycle
DCMs,
Configuration
Startup
NoWait
0, 1, 2, 3, If one or more DCMs in the design have the STARTUP_WAIT attribute set to TRUE,
4, 5, 6
the FPGA waits for such DCMs to acquire their respective input clock and assert their
LOCKED output. This setting selects the Configuration Startup phase where the FPGA
waits for the DCMs to lock.
DonePin
DONE pin
DONE pin
Pullup
Internally connects a pull-up resistor between DONE pin and VCCAUX. An external
330 Ω pull-up resistor to VCCAUX is still recommended.
Pullnone No internal pull-up resistor on DONE pin. An external 330 Ω pull-up resistor to
VCCAUX is required.
DriveDone
No
When configuration completes, the DONE pin stops driving Low and relies on an
external 330 Ω pull-up resistor to VCCAUX for a valid logic High.
Yes
When configuration completes, the DONE pin actively drives High. When using this
option, an external pull-up resistor is no longer required. Only one device in an FPGA
daisy-chain should use this setting.
DonePipe
ProgPin
DONE pin
No
The input path from DONE pin input back to the Startup sequencer is not pipelined.
Yes
This option adds a pipeline register stage between the DONE pin input and the Startup
sequencer. Used for high-speed daisy-chain configurations when DONE cannot rise in
a single CCLK cycle. Releases GWE and GTS signals on the first rising edge of
StartupClk after the DONE pin input goes High.
PROG_B pin
Pullup
Internally connects a pull-up resistor or between PROG_B pin and VCCAUX. An
external 4.7 kΩ pull-up resistor to VCCAUX is still recommended.
Pullnone No internal pull-up resistor on PROG_B pin. An external 4.7 kΩ pull-up resistor to
VCCAUX is required.
TckPin
TdiPin
JTAG TCK pin
JTAG TDI pin
Pullup
Internally connects a pull-up resistor between JTAG TCK pin and VCCAUX.
Pulldown Internally connects a pull-down resistor between JTAG TCK pin and GND.
Pullnone No internal pull-up resistor on JTAG TCK pin.
Pullup
Internally connects a pull-up resistor between JTAG TDI pin and VCCAUX.
Pulldown Internally connects a pull-down resistor between JTAG TDI pin and GND.
Pullnone No internal pull-up resistor on JTAG TDI pin.
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Table 57: Spartan-3E FPGA Bitstream Generator (BitGen) Options (Continued)
Pins/Function
Affected
Values
(default)
Option Name
Description
TdoPin
JTAG TDO pin
Pullup
Internally connects a pull-up resistor between JTAG TDO pin and VCCAUX.
Pulldown Internally connects a pull-down resistor between JTAG TDO pin and GND.
Pullnone No internal pull-up resistor on JTAG TDO pin.
TmsPin
JTAG TMS pin
Pullup
Internally connects a pull-up resistor between JTAG TMS pin and VCCAUX.
Pulldown Internally connects a pull-down resistor between JTAG TMS pin and GND.
Pullnone No internal pull-up resistor on JTAG TMS pin.
UserID
JTAG User ID
register
User
string
The 32-bit JTAG User ID register value is loaded during configuration. The default
value is all ones, 0xFFFF_FFFF hexadecimal. To specify another value, enter an
8-character hexadecimal value.
Security
JTAG,
SelectMAP,
Readback,
Partial
None
Readback and partial reconfiguration are available via the JTAG port or via the
SelectMAP interface, if the Persist option is set to Yes.
Level1
Readback function is disabled. Partial reconfiguration is still available via the JTAG port
or via the SelectMAP interface, if the Persist option is set to Yes.
reconfiguration
Level
Readback function is disabled. Partial reconfiguration is disabled.
CRC
Configuration
Enable
Default. Enable CRC checking on the FPGA bitstream. If error detected, FPGA
asserts INIT_B Low and DONE pin stays Low.
Disable
No
Turn off CRC checking.
Persist
SelectMAP
interface pins,
BPI mode,
Slave mode,
Configuration
All BPI and Slave mode configuration pins are available as user-I/O after configuration.
Yes
This option is required for Readback and partial reconfiguration using the SelectMAP
interface. The SelectMAP interface pins (see Slave Parallel Mode, page 79) are
reserved after configuration and are not available as user-I/O.
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Functional Description
VCCAUX. Each of the four I/O banks has a separate VCCO
supply input that powers the output buffers within the asso-
ciated I/O bank. All of the VCCO connections to a specific I/O
bank must be connected and must connect to the same
voltage.
Powering Spartan-3E FPGAs
Voltage Supplies
Like Spartan-3 FPGAs, Spartan-3E FPGAs have multiple
voltage supply inputs, as shown in Table 58. There are two
supply inputs for internal logic functions, VCCINT and
Table 58: Spartan-3E Voltage Supplies
Supply
Nominal Supply
Voltage
Description
Input
VCCINT
Internal core supply voltage. Supplies all internal logic functions such as
CLBs, block RAM, multipliers, etc. Input to Power-On Reset (POR) circuit.
1.2V
VCCAUX
Auxiliary supply voltage. Supplies Digital Clock Managers (DCMs),
differential drivers, dedicated configuration pins, JTAG interface. Input to
Power-On Reset (POR) circuit.
2.5V
VCCO_0
VCCO_1
Supplies the output buffers in I/O Bank 0, the bank along the top edge of the
FPGA.
Selectable, 3.3V, 3.0V,
2.5V, 1.8, 1.5V, or 1.2V.
Supplies the output buffers in I/O Bank 1, the bank along the right edge of the
FPGA. In Byte-Wide Peripheral Interface (BPI) Parallel Flash Mode,
connects to the save voltage as the Flash PROM.
Selectable, 3.3V, 3.0V,
2.5V, 1.8, 1.5V, or 1.2V.
VCCO_2
VCCO_3
Supplies the output buffers in I/O Bank 2 the bank along the bottom edge of
the FPGA. Connects to the same voltage as the FPGA configuration source.
Input to Power-On Reset (POR) circuit.
Selectable, 3.3V, 3.0V,
2.5V, 1.8, 1.5V, or 1.2V.
Supplies the output buffers in I/O Bank 0, the bank along the top edge of the
FPGA.
Selectable, 3.3V, 3.0V,
2.5V, 1.8, 1.5V, or 1.2V.
In a 3.3V-only application, all four VCCO supplies connect to
3.3V. However, Spartan-3E FPGAs provide the ability to
bridge between different I/O voltages and standards by
applying different voltages to the VCCO inputs of different
banks. Refer to I/O Banking Rules for which I/O standards
can be intermixed within a single I/O bank.
three-rail regulators specifically designed for Spartan-3 and
Spartan-3E FPGAs. The Xilinx Power Corner web site pro-
vides links to vendor solution guides and Xilinx power esti-
mation and analysis tools.
Power Distribution System (PDS) Design and
Decoupling/Bypass Capacitors
Each I/O bank also has an separate, optional input voltage
reference supply, called VREF. If the I/O bank includes an
I/O standard that requires a voltage reference such as
HSTL or SSTL, then all VREF pins within the I/O bank must
be connected to the same voltage.
Good power distribution system (PDS) design is important
for all FPGA designs, but especially so for high performance
applications, greater than 100 MHz. Proper design results in
better overall performance, lower clock and DCM jitter, and
a generally more robust system. Before designing the
printed circuit board (PCB) for the FPGA design, please
review XAPP623: "Power Distribution System (PDS)
Design: Using Bypass/Decoupling Capacitors".
Voltage Regulators
Various power supply manufacturers offer complete power
solutions for Xilinx FPGAs including some with integrated
DS312-2 (v1.1) March 21, 2005
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Functional Description
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revision
03/01/05
03/21/05
Initial Xilinx release.
Updated Figure 42. Modified title on Table 33 and Table 39.
1.1
The Spartan-3E Family Data Sheet
DS312-1, Spartan-3E FPGA Family: Introduction and Ordering Information (Module 1)
DS312-2, Spartan-3E FPGA Family: Functional Description (Module 2)
DS312-3, Spartan-3E FPGA Family: DC and Switching Characteristics (Module 3)
DS312-4, Spartan-3E FPGA Family: Pinout Descriptions (Module 4)
96
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification
018
Spartan-3E FPGA Family:
DC and Switching
Characteristics
R
0
0
DS312-3 (v1.0) March 1, 2005
Advance Product Specification
DC Electrical Characteristics
In this section, specifications may be designated as
Advance, Preliminary, or Production. These terms are
defined as follows:
All parameter limits are representative of worst-case supply
voltage and junction temperature conditions. The following
applies unless otherwise noted: The parameter values
published in this module apply to all Spartan™-3E
devices. AC and DC characteristics are specified using
the same numbers for both commercial and industrial
grades.
Advance: Initial estimates are based on simulation, early
characterization, and/or extrapolation from the characteris-
tics of other families. Values are subject to change. Use as
estimates, not for production.
If a particular Spartan-3E FPGA differs in functional
behavior or electrical characteristic from this data
sheet, those differences are described in a separate
errata document. The errata documents for Spartan-3E
FPGAs are living documents and are available online.
Preliminary: Based on characterization. Further changes
are not expected.
Production: These specifications are approved once the
silicon has been characterized over numerous production
lots. Parameter values are considered stable with no future
changes expected.
Table 1: Absolute Maximum Ratings
Symbol
VCCINT
VCCAUX
VCCO
Description
Internal supply voltage
Conditions
Min
–0.5
–0.5
–0.5
–0.5
–0.5
Max
1.32
Units
V
V
V
V
V
Auxiliary supply voltage
Output driver supply voltage
Input reference voltage
3.00
3.75
VREF
VCCO + 0.5(3)
VCCO + 0.5(3)
(2)
VIN
Voltage applied to all User I/O pins and
Dual-Purpose pins
Driver in a high-impedance state
Voltage applied to all Dedicated pins
Electrostatic Discharge Voltage
–0.5
–2000
–500
–200
-
VCCAUX+0.5(4)
+2000
+500
V
V
VESD
Human body model
Charged device model
Machine model
V
+200
V
TJ
Junction temperature
Storage temperature
125
°C
°C
TSTG
–65
150
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only;
functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions is not
implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time adversely affects device reliability.
2. As a rule, the V limits apply to both the DC and AC components of signals. Simple application solutions are available that show how to
IN
handle overshoot/undershoot as well as achieve PCI compliance. Refer to the following application notes: "Virtex™-II Pro and Spartan-3
3.3V PCI Reference Design" (XAPP653) and "Using 3.3V I/O Guidelines in a Virtex-II Pro Design" (XAPP659).
3. Each of the User I/O and Dual-Purpose pins is associated with one of the four banks’ V
rails. Meeting the V max limit ensures that the
CCO
IN
internal diode junctions that exist between these pins and their associated V
rails do not turn on. Table 4 specifies the V
range used
CCO
CCO
to determine the max limit. When V
is at its maximum recommended operating level (3.45V), V max is 3.95V. The maximum voltage
= 4.05V. As long as the V max specification is met, oxide stress is not possible.
CCO
IN
that avoids oxide stress is V
INX
IN
4. All Dedicated pins (PROG_B, DONE, TCK, TDI, TDO, and TMS) draw power from the V
rail (2.5V). Meeting the V max limit ensures
IN
CCAUX
that the internal diode junctions that exist between each of these pins and the V
rail do not turn on. Table 4 specifies the V
range
CCAUX
CCAUX
used to determine the max limit. When V
is at its maximum recommended operating level (2.625V), V max < 3.125V. As long as the
CCAUX
IN
V
max specification is met, oxide stress is not possible.
IN
5. For soldering guidelines, see "Device Packaging and Thermal Characteristics" at www.xilinx.com/bvdocs/userguides/ug112.pdf. Also see
"Implementation and Solder Reflow Guidelines for Pb-Free Packages" at www.xilinx.com/bvdocs/appnotes/xapp427.pdf.
© 2005 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc.
All other trademarks are the property of their respective owners.
DS312-3 (v1.0) March 1, 2005
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Advance Product Specification
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DC and Switching Characteristics
Table 2: Supply Voltage Thresholds for Power-On Reset
Symbol
VCCINTT
VCCAUXT
VCCO2T
Description
Threshold for the VCCINT supply
Threshold for the VCCAUX supply
Threshold for the VCCO Bank 2 supply
Min
0.4
0.8
0.4
Max
1.0
Units
V
V
V
2.0
1.0
Notes:
1.
V
, V
, and V
supplies may be applied in any order.
CCO
CCINT CCAUX
2. To ensure successful power-on, V
no dips at any point.
, V
Bank 2, and V
supplies must rise through their respective threshold-voltage ranges with
CCINT CCO
CCAUX
Table 3: Power Voltage Levels Necessary for Preserving RAM Contents
Symbol
VDRINT
VDRAUX
VDRO
Description
VCCINT level required to retain RAM data
Min
1.0
2.0
1.0
Units
V
V
V
VCCAUX level required to retain RAM data
VCCO level required to retain RAM data
Notes:
1. RAM contents include configuration data.
Table 4: General Recommended Operating Conditions
Symbol
Description
Junction temperature
Min
0
Nom
Max
85
Units
°C
°C
V
TJ
Commercial
Industrial
-
–40
-
100
VCCINT
Internal supply voltage
Output driver supply voltage
Auxiliary supply voltage
1.140
1.140
2.375
1.200
-
1.260
3.450
2.625
(1)
VCCO
V
(2)
VCCAUX
2.500
V
Notes:
1. The V
range given here spans the lowest and highest operating voltages of all supported I/O standards. The recommended V
range
CCO
CCO
specific to each of the single-ended I/O standards is given in Table 7, and that specific to the differential standards is given in Table 9.
2. Only during DCM operation, it is recommended that the rate of change of V not exceed 10 mV/ms.
CCAUX
2
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Advance Product Specification
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DC and Switching Characteristics
Table 5: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins
Symbol
Description
Test Conditions
Min
Typ
Max Units
(2)
IL
Leakage current at User I/O,
Dual-Purpose, and Dedicated pins
Driver is in a high-impedance state,
VIN = 0V or VCCO max, sample-tested
–10
-
+10
µA
(3)
IRPU
Current through pull-up resistor at
User I/O, Dual-Purpose, and
Dedicated pins
V
V
V
IN = 0V, VCCO = 3.3V
IN = 0V, VCCO = 3.0V
IN = 0V, VCCO = 2.5V
mA
mA
mA
mA
mA
mA
mA
VIN = 0V, VCCO = 1.8V
V
V
IN = 0V, VCCO = 1.5V
IN = 0V, VCCO = 1.2V
(3)
IRPD
Current through pull-down resistor at
User I/O, Dual-Purpose, and
Dedicated pins
VIN = VCCO
IREF
CIN
VREF current per pin
Input capacitance
All VCCO levels
–10
3
-
-
+10
10
µA
pF
Notes:
1. The numbers in this table are based on the conditions set forth in Table 4.
2. The I specification applies to every I/O pin throughout power-on as long as the voltage on that pin stays between the absolute V minimum
L
IN
and maximum values (Table 1). For hot-swap applications, at the time of card connection, be sure to keep all I/O voltages within this range
before applying V power. Also consider applying V power before the connection of data lines occurs. When the FPGA is completely
CCO
CCO
unpowered, the impedance at the I/O pins is high.
3. This parameter is based on characterization. The pull-up resistance R = V
/ I
. The pull-down resistance R = V / I
.
PU
CCO RPU
PD
IN RPD
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DC and Switching Characteristics
Table 6: Quiescent Supply Current Characteristics
Symbol
Description
Device
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
Typ(4)
15
Max
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
ICCINTQ
Quiescent VCCINT supply current
38
68
98
108
1.0
1.5
1.7
1.8
2.2
10
ICCOQ
Quiescent VCCO supply current
ICCAUXQ
Quiescent VCCAUX supply current
15
25
35
45
Notes:
1. The numbers in this table are based on the conditions set forth in Table 4. Quiescent supply current is measured with all I/O drivers in a
high-impedance state and with all pull-up/pull-down resistors at the I/O pads disabled. For typical values, the ambient temperature (T ) is
A
25°C with V
= 1.2V, V
= 2.5V, and V
= 2.5V. The FPGA is programmed with a "blank" configuration data file (i.e., a design
CCINT
CCO
CCAUX
with no functional elements instantiated). For conditions other than those described above, (e.g., a design including functional elements),
measured quiescent current levels may be higher than the values in the table.
2. There are two recommended ways to estimate the total power consumption (quiescent plus dynamic) for a specific design: a) The
Spartan-3E Web Power Tool, a future web-based application, provides quick, approximate, typical estimates, and does not require a netlist
of the design. b) XPower, which will be included in a future release of the Xilinx development software, takes a netlist as input to provide
more accurate maximum and typical estimates.
3. The maximum numbers in this table indicate the minimum current each power rail requires in order for the FPGA to power-on successfully.
4. All typical quiescent current values are early estimates.
4
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Advance Product Specification
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DC and Switching Characteristics
Table 7: Recommended Operating Conditions for User I/Os Using Single-Ended Standards
V
CCO for Drivers(2)
VREF
VIL
VIH
Min (V)
VREF + 0.1
VREF + 0.1
0.8
IOSTANDARD
Attribute
Min (V) Nom (V) Max (V) Min (V)
Nom (V)
Max (V)
Max (V)
HSTL_I_18
HSTL_III_18
LVCMOS12(4)
LVCMOS15(4)
LVCMOS18(4)
LVCMOS25(4,5)
LVCMOS33(4)
LVTTL
1.7
1.7
1.1
1.4
1.65
2.3
3.0
3.0
-
1.8
1.8
1.2
1.5
1.8
2.5
3.3
3.3
3.0
3.0
TBD
1.80
2.5
1.9
1.9
1.3
1.6
1.95
2.7
3.45
3.45
-
0.8
0.9
1.1
V
REF - 0.1
VREF - 0.1
0.38
-
1.1
-
-
-
-
-
-
-
0.38
0.8
-
-
-
0.38
0.8
-
-
-
0.7
1.7
-
-
-
0.8
2.0
-
-
-
0.8
2.0
PCI33_3(7)
PCI66_3(7)
PCIX(7)
-
-
-
0.9
1.5
-
-
-
-
-
-
-
-
0.9
1.5
-
-
TBD
TBD
SSTL18_I
1.70
2.3
1.90
2.7
0.833
1.15
0.900
1.25
0.969
1.35
V
REF - 0.125 VREF + 0.125
SSTL2_I
VREF - 0.15 VREF + 0.15
Notes:
1. Descriptions of the symbols used in this table are as follows:
V
V
V
V
-- the supply voltage for output drivers
-- the reference voltage for setting the input switching threshold
-- the input voltage that indicates a Low logic level
-- the input voltage that indicates a High logic level
CCO
REF
IL
IH
2. The V
rails supply only output drivers, not input circuits.
CCO
3. For device operation, the maximum signal voltage (V max) may be as high as V max. See Table 1.
IH
IN
4. There is approximately 100 mV of hysteresis on inputs using any LVCMOS standard.
5. All Dedicated pins (PROG_B, DONE, TCK, TDI, TDO, and TMS) use the LVCMOS25 standard and draw power from the V
rail (2.5V).
CCAUX
The Dual-Purpose configuration pins use the LVCMOS25 standard before the User mode. When using these pins as part of a standard 2.5V
configuration interface, apply 2.5V to the V lines of Banks 0, 1, and 2 at power-on as well as throughout configuration.
CCO
6. The Global Clock Inputs (GCLK0-GCLK15, RHCLK0-RHCLK7, and LHCLK0-LHCLK7) are Dual-Purpose pins to which any signal standard
may be assigned.
7. For more information, see "Virtex-II Pro and Spartan-3 3.3V PCI Reference Design" (XAPP653).
DS312-3 (v1.0) March 1, 2005
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5
Advance Product Specification
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DC and Switching Characteristics
Table 8: DC Characteristics of User I/Os Using Single-Ended Standards
Test Conditions
Logic Level Characteristics
IOL
IOH
VOL
VOH
IOSTANDARD Attribute
HSTL_I_18
(mA)
(mA)
Max (V)
Min (V)
8
24
2
–8
–8
0.4
0.4
0.4
0.4
VCCO - 0.4
HSTL_III_18
VCCO - 0.4
LVCMOS12(3)
LVCMOS15(3)
2
2
–2
VCCO - 0.4
VCCO - 0.4
2
–2
4
4
–4
6
6
–6
LVCMOS18(3)
2
2
–2
0.4
0.4
VCCO - 0.4
4
4
–4
6
6
–6
8
8
–8
LVCMOS25(3,4)
2
2
–2
VCCO - 0.4
4
4
–4
6
6
–6
8
8
–8
12
2
12
2
–12
–2
LVCMOS33(3)
0.4
VCCO - 0.4
4
4
–4
6
6
–6
8
8
–8
12
16
2
12
16
2
–12
–16
–2
LVTTL(3)
0.4
2.4
4
4
–4
6
6
–6
8
8
–8
12
16
12
16
1.5
1.5
TBD
6.7
–12
–16
–0.5
–0.5
TBD
–6.7
PCI33_3(5)
PCI66_3(5)
PCIX
0.10VCCO
0.10VCCO
TBD
0.90VCCO
0.90VCCO
TBD
SSTL18_I
V
TT - 0.475
VTT + 0.475
6
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Advance Product Specification
R
DC and Switching Characteristics
Table 8: DC Characteristics of User I/Os Using Single-Ended Standards (Continued)
Test Conditions Logic Level Characteristics
IOL
IOH
VOL
VOH
IOSTANDARD Attribute
SSTL2_I
(mA)
(mA)
Max (V)
Min (V)
8.1
–8.1
VTT - 0.61
VTT + 0.61
Notes:
1. The numbers in this table are based on the conditions set forth in Table 4 and Table 7.
2. Descriptions of the symbols used in this table are as follows:
I
I
-- the output current condition under which V is tested
OL
OL
-- the output current condition under which V is tested
OH
OH
V
-- the output voltage that indicates a Low logic level
OL
V
-- the output voltage that indicates a High logic level
-- the input voltage that indicates a Low logic level
-- the input voltage that indicates a High logic level
-- the supply voltage for output drivers
-- the reference voltage for setting the input switching threshold
OH
V
V
V
V
V
IL
IH
CCO
REF
-- the voltage applied to a resistor termination
TT
3. For the LVCMOS and LVTTL standards: the same V and V limits apply for both the Fast and Slow slew attributes.
OL
OH
4. All Dedicated output pins (DONE and TDO) as well as Dual-Purpose totem-pole output pins (CCLK, D0-D7, BUSY/DOUT, CSO_B, MOSI,
HDC, LDC0-LDC2, and A0-A23) exhibit the characteristics of LVCMOS25 with Slow slew rate; all have 8 mA drive except CCLK, which has
12 mA drive.
5. Tested according to the relevant PCI specifications. For more information, see "Virtex-II Pro and Spartan-3 3.3V PCI Reference Design"
(XAPP653).
DS312-3 (v1.0) March 1, 2005
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7
Advance Product Specification
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DC and Switching Characteristics
VINP
VINN
Differential
I/O Pair Pins
P
N
Internal
Logic
VINN
V
50%
ID
VINP
V
ICM
GND level
VINP + VINN
V
ICM = Input common mode voltage =
2
V
VINP - VINN
ID = Differential input voltage =
DS099-3_01_012304
Figure 1: Differential Input Voltages
Table 9: Recommended Operating Conditions for User I/Os Using Differential Signal Standards
VCCO for Drivers(1)
VID
VICM
VIH
VIL
IOSTANDARD
Attribute
Min
(V)
Nom
(V)
Max
(V)
Min
(mV)
Nom
(mV)
Max
(mV)
Min
(V)
Nom
(V)
Max
(V)
Min
(V)
Max
(V)
Min
(V)
Max
(V)
LVDS_25
2.375
2.375
2.375
2.50
2.50
2.625
2.625
2.625
100
100
200
100
100
350
350
-
600
600
600
1000
-
0.30
0.30
0.30
0.3
1.25
1.25
-
2.20
2.20
2.2
-
-
-
-
-
-
-
-
BLVDS_25
MINI_LVDS_25
LVPECL_25(2)
RSDS_25
2.50
Inputs Only
2.50
800
200
1.2
1.20
2.2
0.8
-
2.0
-
0.5
-
1.7
-
2.375
2.625
0.3
1.4
Notes:
1. The V
rails supply only differential output drivers, not input circuits.
CCO
2. Spartan-3E devices support this standard for inputs only, not for outputs.
3. inputs are not used for any of the differential I/O standards.
V
REF
8
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DC and Switching Characteristics
VOUTP
VOUTN
Differential
I/O Pair Pins
P
N
Internal
Logic
VOH
VOUTN
VOD
50%
VOUTP
VOL
VOCM
GND level
VOUTP + VOUTN
V
OCM = Output common mode voltage =
2
VOUTP - VOUTN
= Output voltage indicating a High logic level
= Output voltage indicating a Low logic level
V
OD = Output differential voltage =
VOH
VOL
DS312-3_03_021505
Figure 2: Differential Output Voltages
Table 10: DC Characteristics of User I/Os Using Differential Signal Standards
VOD
∆VOD
VOCM
∆VOCM
VOH
VOL
IOSTANDARD
Attribute
Min
(mV)
Typ
(mV)
Max
(mV)
Min
(mV)
Max
(mV)
Min
(V)
Min
(mV)
Max
(mV)
Min
(V)
Max
(V)
Typ (V) Max (V)
LVDS_25
250
250
300
100
350
450
450
600
400
-
-
-
-
-
-
1.125
-
-
1.375
-
-
-
-
-
-
-
1.25
-
1.25
-
BLVDS_25
MINI_LVDS_25
RSDS_25
350
1.20
-
-
50
-
1.0
1.1
-
-
1.4
1.4
50
-
1.15
1.15
1.25
1.35
Notes:
1. The numbers in this table are based on the conditions set forth in Table 4 and Table 9.
2. Output voltage measurements for all differential standards are made with a termination resistor (R ) of 100Ω across the N and P pins of the
T
differential signal pair.
3. At any given time, no more than two differential standards may be assigned to each bank.
DS312-3 (v1.0) March 1, 2005
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9
Advance Product Specification
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DC and Switching Characteristics
Switching Characteristics
All Spartan-3E FPGAs ship in two speed grades: –4 and the
higher performance –5. Switching characteristics in this
document may be designated as Advance, Preliminary, or
Production, as shown in Table 11. Each category is defined
as follows:
data, use the values reported by the Xilinx static timing ana-
lyzer (TRACE in the Xilinx development software) and
back-annotated to the simulation netlist.
Table 11: Spartan-3E v1.10 Speed Grade Designations
Device
Preview
–4
Advance
Preliminary
Production
Advance: These specifications are based on simulations
only and are typically available soon after establishing
FPGA specifications. Although speed grades with this des-
ignation are considered relatively stable and conservative,
some under-reporting might still occur.
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
–4
–4
Preliminary: These specifications are based on complete
early silicon characterization. Devices and speed grades
with this designation are intended to give a better indication
of the expected performance of production silicon. The
probability of under-reporting preliminary delays is greatly
reduced compared to Advance data.
–4
–4
System
Usage
Prototyping Only
Production
Production: These specifications are approved once
enough production silicon of a particular device family mem-
ber has been characterized to provide full correlation
between speed files and devices over numerous production
lots. There is no under-reporting of delays, and customers
receive formal notification of any subsequent changes. Typ-
ically, the slowest speed grades transition to Production
before faster speed grades.
Digital Clock Manager (DCM) Timing
For specification purposes, the DCM consists of three key
components: the Delay-Locked Loop (DLL), the Digital Fre-
quency Synthesizer (DFS), and the Phase Shifter (PS).
Aspects of DLL operation play a role in all DCM applica-
tions. All such applications inevitably use the CLKIN and the
CLKFB inputs connected to either the CLK0 or the CLK2X
feedback, respectively. Thus, specifications in the DLL
tables (Table 12 and Table 13) apply to any application that
only employs the DLL component. When the DFS and/or
the PS components are used together with the DLL, then
the specifications listed in the DFS and PS tables super-
sede any corresponding ones in the DLL tables. (See
Table 14 and Table 15 for the DFS; tables for the PS are not
yet available.) DLL specifications that do not change with
the addition of DFS or PS functions are presented in
Table 12 and Table 13.
Production-quality systems must use FPGA designs com-
piled using a speed file designated as Production status.
FPGAs designs using a less mature speed file designation
should only be used during system prototyping or pre-pro-
duction qualification. FPGA designs with speed files desig-
nated as Preview, Advance, or Preliminary should not be
used in a production-quality system.
Whenever a speed file designation changes, as a device
matures toward Production status, Xilinx recommends
rerunning the Xilinx ISE software on the FPGA design. This
ensures that the FPGA design incorporates the latest timing
information and software updates.
All DCM clock output signals exhibit an approximate duty
cycle of 50%.
Period jitter and cycle-cycle jitter are two (of many) different
ways of characterizing clock jitter. Both specifications
describe statistical variation from a mean value.
All specified limits are representative of worst-case supply
voltage and junction temperature conditions. Unless other-
wise noted, the following applies: Parameter values apply to
all Spartan-3E devices. All parameters representing volt-
ages are measured with respect to GND.
Period jitter is the worst-case deviation from the average
clock period of all clock cycles in the collection of clock peri-
ods sampled (usually from 100,000 to more than a million
samples for specification purposes). In a histogram of
period jitter, the mean value is the clock period.
Timing parameters and their representative values are
selected for inclusion below either because they are impor-
tant as general design requirements or they indicate funda-
mental device performance characteristics. The Spartan-3E
speed files (v1.10), part of the Xilinx Development Software,
are the original source for many but not all of the values.
The speed grade designations for these files are shown in
Table 11. For more complete, more precise, and worst-case
Cycle-cycle jitter is the worst-case difference in clock period
between adjacent clock cycles in the collection of clock peri-
ods sampled. In a histogram of cycle-cycle jitter, the mean
value is zero.
10
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R
DC and Switching Characteristics
Table 12: Recommended Operating Conditions for the DLL
Speed Grade
-4
-5
Symbol
Description
Min
Max
Min
Max
Units
Input Frequency Ranges
FCLKIN
CLKIN_FREQ_DLL
Frequency for the CLKIN input
5
326
5(2)
280
MHz
Notes:
1. DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.
2. Use of the DFS permits lower F frequencies. See Table 14.
CLKIN
Table 13: Switching Characteristics for the DLL
Speed Grade
-5
-4
Symbol
Description
Min
Max
Min
Max
Units
Output Frequency Ranges
CLKOUT_FREQ_1X
Frequency for the CLK0 and CLK180 outputs
Frequency for the CLK90 and CLK270 outputs
5
5
326
165
400
5
5
280
165
330
MHz
MHz
MHz
CLKOUT_FREQ_2X
Frequency for the CLK2X and CLK2X180
outputs
10
10
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 4 and Table 12.
2. DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.
DS312-3 (v1.0) March 1, 2005
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11
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DC and Switching Characteristics
Table 14: Recommended Operating Conditions for the DFS
Speed Grade
-5
-4
Symbol
Description
Min
Max
Min
Max
Units
Input Frequency Ranges(2)
FCLKIN
CLKIN_FREQ_FX
Frequency for the CLKIN input
0.2
326
0.2
326
MHz
Notes:
1. DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) are in use.
2. If both DFS and DLL outputs are used on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in Table 12.
Table 15: Switching Characteristics for the DFS
Speed Grade
-5
-4
Symbol
Description
Min
Max
Min
Max
Units
Output Frequency Ranges
CLKOUT_FREQ_FX
Frequency for the CLKFX and CLKFX180 outputs
5
326
5
280
MHz
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 4 and Table 14.
2. DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) is in use.
12
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DS312-3 (v1.0) March 1, 2005
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R
DC and Switching Characteristics
Configuration and JTAG Timing
1.2V
2.5V
V
CCINT
1.0V
2.0V
1.0V
(Supply)
V
CCAUX
(Supply)
V
CCO
Bank 2
(Supply)
TPOR
PROG_B
(Input)
TPL
TPROG
INIT_B
(Open-Drain)
TICCK
CCLK
(Output)
DS312-3_01_020505
Notes:
1. The V
, V
, and V
supplies may be applied in any order.
CCO
CCINT CCAUX
2. The Low-going pulse on PROG_B is optional after power-on but necessary for reconfiguration without a power cycle.
3. The rising edge of INIT_B samples the voltage levels applied to the mode pins (M0 - M2).
Figure 3: Waveforms for Power-On and the Beginning of Configuration
Table 16: Power-On Timing and the Beginning of Configuration
All Speed Grades
Symbol
(2)
Description
Device
Min
Max
5
Units
ms
ms
ms
ms
ms
µs
TPOR
The time from the application of VCCINT, VCCAUX, and VCCO XC3S100E
Bank 2 supply voltage ramps (whichever occurs last) to the
rising transition of the INIT_B pin
XC3S500E
-
XC3S250E
-
5
-
5
XC3S1200E
XC3S1600E
-
5
-
7
TPROG
The width of the low-going pulse on the PROG_B pin
All
0.3
-
(2)
TPL
The time from the rising edge of the PROG_B pin to the
rising transition on the INIT_B pin
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
All
-
2
ms
ms
ms
ms
ms
µs
-
-
2
2
-
2
-
3
(3)
TICCK
The time from the rising edge of the INIT_B pin to the
generation of the configuration clock signal at the CCLK
output pin
0.5
4.0
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 4. This means power must be applied to all V
, V
,
CCINT CCO
and V
lines.
CCAUX
2. Power-on reset and the clearing of configuration memory occurs during this period.
3. This specification applies only to the Master Serial, SPI, BPI-Up, and BPI-Down modes.
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DC and Switching Characteristics
PROG_B
(Input)
INIT_B
(Open-Drain)
TCCL
TCCH
CCLK
(Input/Output)
TDCC
1/FCCSER
TCCD
DIN
(Input)
Bit n+1
TCCO
Bit n
Bit 0
Bit 1
DOUT
(Output)
Bit n-63
Bit n-64
DS099-3_04_071604
Figure 4: Waveforms for Master and Slave Serial Configuration
Table 17: Timing for the Master and Slave Serial Configuration Modes
All Speed Grades
Slave/
Symbol
Description
Master
Min
Max
Units
Clock-to-Output Times
TCCO
The time from the falling transition on the CCLK pin to data
appearing at the DOUT pin
Both
Both
Both
Slave
1.5
12.0
ns
Setup Times
TDCC
The time from the setup of data at the DIN pin to the rising transition
at the CCLK pin
10.0
0
-
-
ns
ns
Hold Times
TCCD
The time from the rising transition at the CCLK pin to the point when
data is last held at the DIN pin
Clock Timing
TCCH
The High pulse width at the CCLK input pin
The Low pulse width at the CCLK input pin
5.0
-
-
ns
ns
TCCL
5.0
FCCSER
Frequency of the clock signal at
the CCLK input pin
No bitstream compression
With bitstream compression
-
-
66(2)
20
MHz
MHz
-
∆FCCSER Variation from the CCLK output frequency set using the ConfigRate
Master
–50%
+50%
BitGen option
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 4.
2. For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz.
14
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DC and Switching Characteristics
PROG_B
(Input)
INIT_B
(Open-Drain)
TSMCSCC
TSMCCCS
CS_B
(Input)
TSMCCW
TSMWCC
RDWR_B
(Input)
TCCH
TCCL
CCLK
(Input)
1/FCCPAR
Byte n
TSMDCC
TSMCCD
D0 - D7
(Inputs)
Byte 0
Byte 1
Byte n+1
TSMCKBY
TSMCKBY
High-Z
High-Z
BUSY
(Output)
BUSY
DS312-3_02_020805
Notes:
1. It is possible to abort configuration by pulling CS_B Low in a given CCLK cycle, then switching RDWR_B Low or High in any subsequent
cycle for which CS_B remains Low. The RDWR_B pin asynchronously controls the driver impedance of the D0 - D7 bus. When RDWR_B
switches High, be careful to avoid contention on the D0 - D7 bus.
Figure 5: Waveforms for Slave Parallel Configuration
Table 18: Timing for the Slave Parallel Configuration Mode
All Speed Grades
Symbol
Description
Min
Max
Units
Clock-to-Output Times
TSMCKBY
The time from the rising transition on the CCLK pin to a signal transition at the
BUSY pin
-
12.0
ns
Setup Times
TSMDCC
The time from the setup of data at the D0-D7 pins to the rising transition at the
CCLK pin
10.0
10.0
10.0
-
-
-
ns
ns
ns
TSMCSCC
The time from the setup of a logic level at the CS_B pin to the rising transition
at the CCLK pin
(2)
TSMCCW
The time from the setup of a logic level at the RDWR_B pin to the rising
transition at the CCLK pin
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Advance Product Specification
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DC and Switching Characteristics
Table 18: Timing for the Slave Parallel Configuration Mode (Continued)
All Speed Grades
Symbol
Hold Times
TSMCCD
Description
Min
Max
Units
The time from the rising transition at the CCLK pin to the point when data is
last held at the D0-D7 pins
0
0
0
-
-
-
ns
ns
ns
TSMCCCS
TSMWCC
The time from the rising transition at the CCLK pin to the point when a logic
level is last held at the CS_B pin
The time from the rising transition at the CCLK pin to the point when a logic
level is last held at the RDWR_B pin
Clock Timing
TCCH
The High pulse width at the CCLK input pin
The Low pulse width at the CCLK input pin
5
5
-
-
ns
TCCL
-
ns
FCCPAR
Frequency of the clock
signal at the CCLK input
pin
No bitstream
compression
Not using the BUSY pin(2)
Using the BUSY pin
50
66
20
MHz
MHz
MHz
-
With bitstream compression
-
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 4.
2. In the Slave Parallel mode, it is necessary to use the BUSY pin when the CCLK frequency exceeds this maximum specification.
3. Some Xilinx documents may refer to Parallel modes as "SelectMAP" modes.
16
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R
DC and Switching Characteristics
TCCH
TCCL
TCK
(Input)
1/FTCK
TTCKTMS
TTMSTCK
TMS
(Input)
TTDITCK
TTCKTDI
TDI
(Input)
TTCKTDO
TDO
(Output)
DS099_06_040703
Figure 6: JTAG Waveforms
Table 19: Timing for the JTAG Test Access Port
All Speed Grades
Symbol
Description
Min
Max
Units
Clock-to-Output Times
TTCKTDO
The time from the falling transition on the TCK pin
to data appearing at the TDO pin
1.0
11.0
ns
Setup Times
TTDITCK
The time from the setup of data at the TDI pin to
the rising transition at the TCK pin
7.0
7.0
-
-
ns
ns
TTMSTCK
The time from the setup of a logic level at the TMS
pin to the rising transition at the TCK pin
Hold Times
TTCKTDI
The time from the rising transition at the TCK pin
to the point when data is last held at the TDI pin
0
0
-
-
ns
ns
TTCKTMS
The time from the rising transition at the TCK pin
to the point when a logic level is last held at the
TMS pin
Clock Timing
TCCH
The High pulse width at the TCK pin
The Low pulse width at the TCK pin
Frequency of the TCK signal
5
5
-
-
-
ns
ns
TCCL
FTCK
33
MHz
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 4.
DS312-3 (v1.0) March 1, 2005
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17
Advance Product Specification
R
DC and Switching Characteristics
Revision History
The following table shows the revision history for this document.
Date
Version
Revision
03/01/05
1.0
Initial Xilinx release.
The Spartan-3E Family Data Sheet
DS312-1, Spartan-3E FPGA Family: Introduction and Ordering Information (Module 1)
DS312-2, Spartan-3E FPGA Family: Functional Description (Module 2)
DS312-3, Spartan-3E FPGA Family: DC and Switching Characteristics (Module 3)
DS312-4, Spartan-3E FPGA Family: Pinout Descriptions (Module 4)
18
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Spartan-3E FPGA Family:
Pinout Descriptions
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification
Introduction
Pin Types
This section describes the various pins on a Spartan™-3E
FPGA and how they connect within the supported compo-
nent packages.
A majority of the pins on a Spartan-3E FPGA are gen-
eral-purpose, user-defined I/O pins. There are, however, up
to 11 different functional types of pins on Spartan-3E pack-
ages, as outlined in Table 1. In the package footprint draw-
ings that follow, the individual pins are color-coded
according to pin type as in the table.
Table 1: Types of Pins on Spartan-3E FPGAs
Type /
Color Code
Description
Pin Name(s) in Type
I/O
Unrestricted, general-purpose user-I/O pin. Most pins can be paired together to IO
form differential I/Os.
IO_Lxxy_#
INPUT
DUAL
Unrestricted, general-purpose input-only pin. This pin does not have an output IP
structure.
IP_Lxxy_#
Dual-purpose pin used in some configuration modes during the configuration
M[2:0]
process and then usually available as a user I/O after configuration. If the pin is HSWAP
not used during configuration, this pin behaves as an I/O-type pin. Some of the CCLK
dual-purpose pins are also global or edge clock inputs (GCLK).
MOSI/CSI_B
D[7:1]
D0/DIN
CSO_B
RDWR_B
BUSY/DOUT
INIT_B
A[23:20]
A19/VS2
A18/VS1
A17/VS0
A[16:0]
LDC[2:0]
HDC
VREF
Dual-purpose pin that is either a user-I/O pin or, along with all other VREF pins IP/VREF_#
in the same bank, provides a reference voltage input for certain I/O standards. IP_Lxx_#/VREF_#
If used for a reference voltage within a bank, all VREF pins within the bank must
be connected.
GCLK
Either a user-I/O pin or an input to a specific clock buffer driver. Every package GCLK[15:0],
LHCLK
RHCLK
has 16 global clock inputs that optionally clock the entire device. The RHCLK
inputs optionally clock the right-hand side of the device. The LHCLK inputs
optionally clock the left-hand side of the device. Some of the clock pins are
shared with the dual-purpose configuration pins and are considered DUAL-type.
LHCLK[7:0],
RHCLK[7:0]
CONFIG
Dedicated configuration pin. Not available as a user-I/O pin. Every package has DONE, PROG_B
two dedicated configuration pins. These pins are powered by VCCAUX.
© 2005 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc.
All other trademarks are the property of their respective owners.
DS312-4 (v1.1) March 21, 2005
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1
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Pinout Descriptions
Table 1: Types of Pins on Spartan-3E FPGAs
Type /
Color Code
Description
Pin Name(s) in Type
JTAG
Dedicated JTAG pin. Not available as a user-I/O pin. Every package has four
dedicated JTAG pins. These pins are powered by VCCAUX.
TDI, TMS, TCK, TDO
GND
Dedicated ground pin. The number of GND pins depends on the package used. GND
All must be connected.
VCCAUX
VCCINT
VCCO
Dedicated auxiliary power supply pin. The number of VCCAUX pins depends on VCCAUX
the package used. All must be connected to +2.5V.
Dedicated internal core logic power supply pin. The number of VCCINT pins
depends on the package used. All must be connected to +1.2V.
VCCINT
Along with all the other VCCO pins in the same bank, this pin supplies power to VCCO_#
the output buffers within the I/O bank and sets the input threshold voltage for
some I/O standards.
N.C.
This package pin is not connected in this specific device/package combination N.C.
but may be connected in larger devices in the same package.
Notes:
1. # = I/O bank number, an integer between 0 and 3.
I/Os with Lxxy_# are part of a differential output pair. ‘L’ indi-
cates differential output capability. The “xx” field is a
two-digit integer, unique to each bank that identifies a differ-
ential pin-pair. The ‘y’ field is either ‘P’ for the true signal or
‘N’ for the inverted signal in the differential pair. The ‘#’ field
is the I/O bank number.
significance. Figure 1 provides a specific example showing
a differential input to and a differential output from Bank 1.
‘L’ indicates that the pin is part of a differentiaL pair.
"xx" is a two-digit integer, unique for each bank, that
identifies a differential pin-pair.
‘y’ is replaced by ‘P’ for the true signal or ‘N’ for the
inverted. These two pins form one differential pin-pair.
Differential Pair Labeling
A pin supports differential standards if the pin is labeled in
the format “Lxxy_#”. The pin name suffix has the following
‘#’ is an integer, 0 through 3, indicating the associated
I/O bank.
Pair Number
Bank 0
Bank Number
IO_L38P_1
IO_L38N_1
Positive Polarity,
True Driver
IO_L39P_1
Spartan-3E
FPGA
IO_L39N_1
Negative Polarity,
Inverted Driver
Bank 2
DS312-4_00_022305
Figure 1: Differential Pair Labeling
2
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Pinout Descriptions
mechanical dimensions of the standard and Pb-free pack-
ages are similar, as shown in the mechanical drawings pro-
vided in Table 4.
Package Overview
Table 2 shows the eight low-cost, space-saving production
package styles for the Spartan-3E family. Each package
style is available as a standard and an environmen-
tally-friendly lead-free (Pb-free) option. The Pb-free pack-
ages include an extra ‘G’ in the package style name. For
example, the standard "VQ100" package becomes
"VQG100" when ordered as the Pb-free option. The
Not all Spartan-3E densities are available in all packages.
For a specific package, however, there is a common foot-
print that supports all the devices available in that package.
See the footprint diagrams that follow.
Table 2: Spartan-3E Family Package Options
Maximum
I/O
Pitch
(mm)
Height
(mm)
Package
Leads
100
132
144
208
256
320
400
484
Type
Area (mm)
16 x 16
8 x 8
VQ100 / VQG100
CP132 / CPG132
TQ144 / TQG144
PQ208 / PQG208
FT256 / FTG256
FG320 / FGG320
FG400 / FGG400
FG484 / FGG484
Very-thin Quad Flat Pack (VQFP)
Chip-Scale Package (CSP)
66
0.5
0.5
0.5
0.5
1.0
1.0
1.0
1.0
1.20
1.10
1.60
4.10
1.55
2.00
2.60
2.60
92
Thin Quad Flat Pack (TQFP)
Plastic Quad Flat Pack (PQFP)
Fine-pitch, Thin Ball Grid Array (FBGA)
Fine-pitch Ball Grid Array (FBGA)
Fine-pitch Ball Grid Array (FBGA)
Fine-pitch Ball Grid Array (FBGA)
108
158
190
250
304
376
22 x 22
30.6 x 30.6
17 x 17
19 x 19
21 x 21
23 x 23
packages are superior in almost every other aspect, as
summarized in Table 3. Consequently, Xilinx recommends
using BGA packaging whenever possible.
Selecting the Right Package Option
Spartan-3 FPGAs are available in both quad-flat pack
(QFP) and ball grid array (BGA) packaging options. While
QFP packaging offers the lowest absolute cost, the BGA
Table 3: QFP and BGA Comparison
Characteristic
Quad Flat Pack (QFP)
Ball Grid Array (BGA)
Maximum User I/O
158
Good
Fair
376
Better
Better
Better
Better
6
Packing Density (Logic/Area)
Signal Integrity
Simultaneous Switching Output (SSO) Support
Thermal Dissipation
Limited
Fair
Minimum Printed Circuit Board (PCB) Layers
Hand Assembly/Rework
4
Possible
Difficult
DS312-4 (v1.1) March 21, 2005
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Pinout Descriptions
Mechanical Drawings
Detailed mechanical drawings for each package type are
available from the Xilinx website at the specified location in
Table 4.
Table 4: Xilinx Package Mechanical Drawings
Package
Web Link (URL)
VQ100 / VQG100
CP132 / CPG132
TQ144 / TQG144
PQ208 / PQG208
FT256 / FTG256
FG320 / FGG320
FG400 / FGG400
FG484 / FGG484
http://www.xilinx.com/bvdocs/packages/vq100.pdf
http://www.xilinx.com/bvdocs/packages/cp132.pdf
http://www.xilinx.com/bvdocs/packages/tq144.pdf
http://www.xilinx.com/bvdocs/packages/pq208.pdf
http://www.xilinx.com/bvdocs/packages/ft256.pdf
http://www.xilinx.com/bvdocs/packages/fg320.pdf
http://www.xilinx.com/bvdocs/packages/fg400.pdf
http://www.xilinx.com/bvdocs/packages/fg484.pdf
A majority of package pins are user-defined I/O or input
pins. However, the numbers and characteristics of these I/O
depend on the device type and the package in which it is
available, as shown in Table 6. The table shows the maxi-
mum number of single-ended I/O pins available, assuming
that all I/O-, INPUT-, DUAL-, VREF-, and GCLK-type pins
are used as general-purpose I/O. Likewise, the table shows
the maximum number of differential pin-pairs available on
the package. Finally, the table shows how the total maxi-
mum user-I/Os are distributed by pin type, including the
number of unconnected—i.e., N.C.—pins on the device.
Package Pins by Type
Each package has three separate voltage supply
inputs—VCCINT, VCCAUX, and VCCO—and a common
ground return, GND. The numbers of pins dedicated to
these functions vary by package, as shown in Table 5.
Table 5: Power and Ground Supply Pins by Package
Package
VQ100
CP132
TQ144
PQ208
FT256
VCCINT
VCCAUX
VCCO
8
GND
12
4
6
4
4
8
16
4
4
9
13
4
8
12
16
20
24
28
20
8
8
28
FG320
FG400
FG484
8
8
28
16
16
8
42
10
48
4
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Pinout Descriptions
Table 6: Maximum User I/O by Package
Maximum
Differential
Pairs
All Possible I/Os by Type
Maximum
User I/Os
Device
XC3S100E
XC3S250E
XC3S250E
XC3S500E
XC3S100E
XC3S250E
XC3S250E
XC3S500E
XC3S250E
XC3S500E
XC3S1200E
XC3S500E
XC3S1200E
XC3S1600E
XC3S1200E
XC3S1600E
XC3S1600E
Package
I/O
16
INPUT
1
DUAL
21
21
46
46
42
42
46
46
46
46
46
46
46
46
46
46
46
VREF
4
GCLK
24
24
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
N.C.
0
66
30
30
VQ100
66
16
1
4
0
92
41
22
0
8
0
CP132
TQ144
PQ208
92
41
22
0
8
0
108
108
158
158
172
190
190
232
250
250
304
304
376
40
22
19
21
25
25
33
33
31
48
47
48
62
62
72
9
0
40
20
9
0
65
58
13
13
15
19
19
20
21
21
24
24
28
0
65
58
0
68
62
16
0
FT256
FG320
77
76
77
78
0
92
102
120
119
156
156
214
18
0
99
99
0
124
124
156
0
FG400
FG484
0
0
Electronic versions of the package pinout tables and foot-
prints are available for download from the Xilinx web site.
Download the files from the following location: Using a
spreadsheet program, the data can be sorted and reformat-
ted according to any specific needs. Similarly, the
ASCII-text file is easily parsed by most scripting programs.
http://www.xilinx.com/bvdocs/publications/s3e_pin.zip
DS312-4 (v1.1) March 21, 2005
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Pinout Descriptions
Table 7: VQ100 Package Pinout
VQ100: 100-lead Very-thin Quad Flat
Package
The XC3S100E and the XC3S250E devices are available in
the 100-lead very-thin quad flat package, VQ100. Both
devices share a common footprint for this package as
shown in Table 7 and Figure 2.
XC3S100E
XC3S250E
VQ100
Pin
Bank
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Pin Name
Number
Type
VCCO
I/O
VCCO_0
P97
P54
P53
P58
P57
P61
P60
P63
P62
P66
P65
P68
P67
P71
P70
P69
P55
P73
P34
P42
P25
P24
P27
P26
P33
P32
P36
P35
P41
P40
P44
P43
P48
P47
IO_L01N_1
Table 7 lists all the package pins. They are sorted by bank
number and then by pin name of the largest device. Pins
that form a differential I/O pair appear together in the table.
The table also shows the pin number for each pin and the
pin type, as defined earlier.
IO_L01P_1
I/O
IO_L02N_1
I/O
IO_L02P_1
I/O
IO_L03N_1/RHCLK1
IO_L03P_1/RHCLK0
IO_L04N_1/RHCLK3
IO_L04P_1/RHCLK2
IO_L05N_1/RHCLK5
IO_L05P_1/RHCLK4
IO_L06N_1/RHCLK7
IO_L06P_1/RHCLK6
IO_L07N_1
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
I/O
The VQ100 package does not support the Byte-wide
Peripheral Interface (BPI) configuration mode. Conse-
quently, the VQ100 footprint has fewer DUAL-type pins than
other packages.
An electronic version of this package pinout table and foot-
print diagram is available for download from the Xilinx web
site at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip.
Pinout Table
Table 7 shows the pinout for production Spartan-3E FPGAs
in the VQ100 package. The XC3S100 engineering samples
have a slightly different pinout, as described in Table 9.
IO_L07P_1
I/O
Table 7: VQ100 Package Pinout
IP/VREF_1
VREF
VCCO
VCCO
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
XC3S100E
XC3S250E
Pin Name
VQ100
Pin
Number
VCCO_1
Bank
Type
I/O
VCCO_1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO
P92
P79
P78
P84
P83
P86
P85
P91
P90
P95
P94
P99
P98
P89
P88
P82
IO/D5
IO_L01N_0
I/O
IO/M1
IO_L01P_0
I/O
IO_L01N_2/INIT_B
IO_L01P_2/CSO_B
IO_L02N_2/MOSI/CSI_B
IO_L02P_2/DOUT/BUSY
IO_L03N_2/D6/GCLK13
IO_L03P_2/D7/GCLK12
IO_L04N_2/D3/GCLK15
IO_L04P_2/D4/GCLK14
IO_L06N_2/D1/GCLK3
IO_L06P_2/D2/GCLK2
IO_L07N_2/DIN/D0
IO_L07P_2/M0
IO_L02N_0/GCLK5
IO_L02P_0/GCLK4
IO_L03N_0/GCLK7
IO_L03P_0/GCLK6
IO_L05N_0/GCLK11
IO_L05P_0/GCLK10
IO_L06N_0/VREF_0
IO_L06P_0
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
VREF
I/O
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL
IO_L07N_0/HSWAP
IO_L07P_0
DUAL
I/O
IP_L04N_0/GCLK9
IP_L04P_0/GCLK8
VCCO_0
GCLK
GCLK
VCCO
DUAL
IO_L08N_2/VS1
IO_L08P_2/VS2
DUAL
DUAL
6
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Table 7: VQ100 Package Pinout
Table 7: VQ100 Package Pinout
XC3S100E
XC3S250E
VQ100
Pin
XC3S100E
XC3S250E
VQ100
Pin
Bank
Pin Name
IO_L09N_2/CCLK
IO_L09P_2/VS0
IP/VREF_2
Number
Type
DUAL
Bank
GND
GND
Pin Name
Number
P87
P93
P51
P1
Type
GND
2
2
2
2
2
P50
P49
P30
P39
P38
GND
GND
DUAL
GND
VREF
VCCAUX DONE
CONFIG
CONFIG
JTAG
IP_L05N_2/M2/GCLK1
DUAL/GCLK
DUAL/GCLK
VCCAUX PROG_B
VCCAUX TCK
IP_L05P_2/RDWR_B/
GCLK0
P77
P100
P76
P75
P21
P46
P74
P96
P6
VCCAUX TDI
JTAG
2
VCCO_2
P31
P45
P3
VCCO
VCCO
I/O
VCCAUX TDO
JTAG
2
VCCO_2
VCCAUX TMS
JTAG
3
IO_L01N_3
IO_L01P_3
IO_L02N_3/VREF_3
IO_L02P_3
IO_L03N_3/LHCLK1
IO_L03P_3/LHCLK0
IO_L04N_3/LHCLK3
IO_L04P_3/LHCLK2
IO_L05N_3/LHCLK5
IO_L05P_3/LHCLK4
IO_L06N_3/LHCLK7
IO_L06P_3/LHCLK6
IO_L07N_3
IO_L07P_3
IP
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
3
P2
I/O
3
3
P5
VREF
I/O
P4
3
P10
P9
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
I/O
3
P28
P56
P80
3
P12
P11
P16
P15
P18
P17
P23
P22
P13
P8
3
3
3
3
3
3
3
I/O
3
INPUT
VCCO
VCCO
GND
3
VCCO_3
3
VCCO_3
P20
P7
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
P14
P19
P29
P37
P52
P59
P64
P72
P81
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
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User I/Os by Bank
Table 8 indicates how the 66 available user-I/O pins are dis-
tributed between the four I/O banks on the VQ100 package.
Table 8: User I/Os Per Bank for XC3S100E and XC3S250E in the VQ100 Package
All Possible I/O Pins by Type
Package
Edge
Maximum
I/O
I/O Bank
I/O
5
INPUT
DUAL
VREF
GCLK
Top
0
1
2
3
15
15
19
17
66
0
0
0
1
1
1
0
1
1
1
1
4
8
8
Right
Bottom
Left
6
0
18
2
0
5
8
TOTAL
16
21
24
Footprint Migration Differences
Table 9: XC3S100E Pinout Changes between
Production Devices and Engineering Samples
The production XC3S100E and XC3S250E FPGAs have
identical footprints in the VQ100 package. Designs can
migrate between the XC3S100E and XC3S250E without
further consideration.
XC3S100E
Production
Devices
XC3S100E
Engineering
Samples
VQ100 Pin
P40
The pinout changed slightly between the XC3S100E engi-
neering samples and the production devices, as shown in
Table 9. In the engineering samples, the mode select pins
M1 and M0 overlap with two global clock inputs feeding the
bottom-edge global buffers and DCMs. In the production
devices, the mode pins are swapped with parallel mode
data pins, D1 and D2. This way, these two mode pins do not
interfere with global clock inputs.
D2/GCLK2
D1/GCLK3
M1
M1/GCLK2
M0/GCLK3
D2
P41
P42
P43
M0
D1
8
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Pinout Descriptions
VQ100 Footprint
In Figure 2, note pin 1 indicator in top-left corner and logo
orientation. The engineering sample footprint is slightly dif-
ferent.
PROG_B
IO_L01P_3
1
2
75 TMS
74 VCCAUX
Bank 0
IO_L01N_3
IO_L02P_3
3
4
5
6
7
8
9
73 VCCO_1
72 GND
IO_L02N_3/VREF_3
VCCINT
71 IO_L07N_1
70 IO_L07P_1
69 IP/VREF_1
GND
VCCO_3
68 IO_L06N_1/RHCLK7
67 IO_L06P_1/RHCLK6
66 IO_L05N_1/RHCLK5
65 IO_L05P_1/RHCLK4
64 GND
IO_L03P_3/LHCLK0
IO_L03N_3/LHCLK1 10
IO_L04P_3/LHCLK2 11
IO_L04N_3/LHCLK3 12
IP 13
63 IO_L04N_1/RHCLK3
62 IO_L04P_1/RHCLK2
61 IO_L03N_1/RHCLK1
60 IO_L03P_1/RHCLK0
59 GND
GND 14
IO_L05P_3/LHCLK4 15
IO_L05N_3/LHCLK5 16
IO_L06P_3/LHCLK6 17
IO_L06N_3/LHCLK7 18
GND 19
58 IO_L02N_1
57 IO_L02P_1
VCCO_3 20
56 VCCINT
VCCAUX 21
55 VCCO_1
IO_L07P_3 22
54 IO_L01N_1
IO_L07N_3 23
53 IO_L01P_1
IO_L01P_2/CSO_B 24
IO_L01N_2/INIT_B 25
52 GND
Bank 2
51 DONE
DS312-4_02_030705
Figure 2: VQ100 Package Production Footprint (top view). Engineering Samples have slightly different footprint.
I/O: Unrestricted,
general-purpose user I/O
DUAL: Configuration pin, then
possible user-I/O
VREF: User I/O or input
voltage reference for bank
16
1
21
24
4
4
8
4
4
INPUT: Unrestricted,
general-purpose input pin
GCLK: User I/O, input, or
global buffer input
VCCO: Output voltage supply
for bank
CONFIG: Dedicated
configuration pins
JTAG: Dedicated JTAG port
pins
VCCINT: Internal core supply
voltage (+1.2V)
2
N.C.: Not connected
GND: Ground
VCCAUX: Auxiliary supply
voltage (+2.5V)
0
12
DS312-4 (v1.1) March 21, 2005
www.xilinx.com
9
Advance Product Specification
R
Pinout Descriptions
Table 10: CP132 Package Pinout
CP132: 132-ball Chip-scale Package
XC3S250E
XC3S500E
The XC3S250E and the XC3S500E FPGAs are available in
the 132-lead chip-scale package, CP132. Both devices
share a common footprint for this package as shown in
Table 10 and Figure 3.
CP132
Ball
Bank
Pin Name
IP_L06N_0/GCLK9
IP_L06P_0/GCLK8
VCCO_0
Type
GCLK
GCLK
VCCO
VCCO
DUAL
VREF
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
0
0
0
0
1
1
1
1
1
1
1
1
1
C8
B8
Table 10 lists all the CP132 package pins. They are sorted
by bank number and then by pin name. Pins that form a dif-
ferential I/O pair appear together in the table. The table also
shows the pin number for each pin and the pin type, as
defined earlier.
A6
VCCO_0
B10
F12
K13
N14
N13
M13
M12
L14
L13
J12
IO/A0
Physically, the D14 and K2 balls on the XC3S250E FPGA
are not connected but should be connected to VCCINT to
maintain density migration compatibility.
IO/VREF_1
IO_L01N_1/A15
IO_L01P_1/A16
IO_L02N_1/A13
IO_L02P_1/A14
IO_L03N_1/A11
IO_L03P_1/A12
IO_L04N_1/A9/RHCLK1
An electronic version of this package pinout table and foot-
print diagram is available for download from the Xilinx web-
site at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip
.
Pinout Table
Table 10: CP132 Package Pinout
XC3S250E
XC3S500E
Pin Name
RHCLK/
DUAL
CP132
Ball
Bank
0
Type
I/O
1
1
1
1
1
1
1
IO_L04P_1/A10/RHCLK0
K14
J14
RHCLK/
DUAL
IO_L01N_0
C12
A13
A12
B12
B11
C11
C9
0
IO_L01P_0
I/O
IO_L05N_1/A7/RHCLK3/
TRDY1
RHCLK/
DUAL
0
IO_L02N_0
I/O
IO_L05P_1/A8/RHCLK2
J13
RHCLK/
DUAL
0
IO_L02P_0
I/O
0
IO_L03N_0/VREF_0
IO_L03P_0
VREF
I/O
IO_L06N_1/A5/RHCLK5
H12
H13
G13
G14
RHCLK/
DUAL
0
0
IO_L04N_0/GCLK5
IO_L04P_0/GCLK4
IO_L05N_0/GCLK7
IO_L05P_0/GCLK6
IO_L07N_0/GCLK11
IO_L07P_0/GCLK10
IO_L08N_0/VREF_0
IO_L08P_0
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
VREF
I/O
IO_L06P_1/A6/RHCLK4/
IRDY1
RHCLK/
DUAL
0
A10
A9
IO_L07N_1/A3/RHCLK7
RHCLK/
DUAL
0
0
B9
IO_L07P_1/A4/RHCLK6
RHCLK/
DUAL
0
B7
1
1
1
1
1
1
1
1
1
2
IO_L08N_1/A1
IO_L08P_1/A2
IO_L09N_1/LDC0
IO_L09P_1/HDC
IO_L10N_1/LDC2
IO_L10P_1/LDC1
IP/VREF_1
F13
F14
D12
D13
C13
C14
G12
E13
M14
P4
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
VREF
VCCO
VCCO
DUAL
0
A7
0
C6
0
B6
0
IO_L09N_0
C5
I/O
0
IO_L09P_0
B5
I/O
0
IO_L10N_0
C4
I/O
0
IO_L10P_0
B4
I/O
VCCO_1
0
IO_L11N_0/HSWAP
IO_L11P_0
B3
DUAL
I/O
VCCO_1
0
A3
IO/D5
10
www.xilinx.com
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
Table 10: CP132 Package Pinout
Table 10: CP132 Package Pinout
XC3S250E
XC3S500E
Pin Name
XC3S250E
XC3S500E
Pin Name
CP132
Ball
CP132
Bank
Type
DUAL
VREF
DUAL
DUAL
DUAL
DUAL
Bank
Ball
B2
C2
C3
D1
D2
F2
Type
I/O
2
2
2
2
2
2
2
IO/M1
N7
P11
N1
M2
N2
P1
3
3
IO_L01P_3
IO/VREF_2
IO_L02N_3
IO_L02P_3
IO_L03N_3
IO_L03P_3
IO_L04N_3/LHCLK1
IO_L04P_3/LHCLK0
IO_L05N_3/LHCLK3/IRDY2
IO_L05P_3/LHCLK2
IO_L06N_3/LHCLK5
IO_L06P_3/LHCLK4/TRDY2
IO_L07N_3/LHCLK7
IO_L07P_3/LHCLK6
IO_L08N_3
IO_L08P_3
IO_L09N_3
IO_L09P_3
IP/VREF_3
VCCO_3
I/O
IO_L01N_2/INIT_B
IO_L01P_2/CSO_B
IO_L02N_2/MOSI/CSI_B
IO_L02P_2/DOUT/BUSY
IO_L03N_2/D6/GCLK13
3
I/O
3
I/O
3
I/O
3
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
I/O
N4
DUAL/
GCLK
3
F3
3
G1
F1
2
2
2
2
2
IO_L03P_2/D7/GCLK12
IO_L04N_2/D3/GCLK15
IO_L04P_2/D4/GCLK14
IO_L06N_2/D1/GCLK3
IO_L06P_2/D2/GCLK2
M4
N5
M5
P7
P6
DUAL/
GCLK
3
3
H1
G3
H3
H2
L2
DUAL/
GCLK
3
DUAL/
GCLK
3
3
DUAL/
GCLK
3
3
L1
I/O
DUAL/
GCLK
3
M1
L3
I/O
2
2
2
2
2
2
2
2
2
2
2
2
IO_L07N_2/DIN/D0
IO_L07P_2/M0
N8
P8
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
VREF
3
I/O
3
E2
E1
J2
VREF
VCCO
VCCO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
IO_L08N_2/A22
M9
3
IO_L08P_2/A23
N9
3
VCCO_3
IO_L09N_2/A20
M10
N10
M11
N11
N12
P12
N3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A4
A8
C1
C7
C10
E3
E14
G2
H14
J1
IO_L09P_2/A21
GND
IO_L10N_2/VS1/A18
IO_L10P_2/VS2/A19
IO_L11N_2/CCLK
IO_L11P_2/VS0/A17
IP/VREF_2
GND
GND
GND
GND
GND
IP_L05N_2/M2/GCLK1
N6
DUAL/
GCLK
GND
GND
2
IP_L05P_2/RDWR_B/
GCLK0
M6
DUAL/
GCLK
GND
2
2
3
3
3
VCCO_2
VCCO_2
IO
M8
P3
J3
VCCO
VCCO
I/O
GND
K12
M3
M7
P5
GND
GND
IO/VREF_3
IO_L01N_3
K3
B1
VREF
I/O
GND
DS312-4 (v1.1) March 21, 2005
www.xilinx.com
11
Advance Product Specification
R
Pinout Descriptions
Table 10: CP132 Package Pinout
Table 10: CP132 Package Pinout
XC3S250E
XC3S500E
Pin Name
XC3S250E
XC3S500E
Pin Name
CP132
Ball
CP132
Ball
Bank
GND
GND
Type
GND
Bank
Type
GND
GND
P10
P14
P13
A1
VCCAUX VCCAUX
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
P9
A11
D3
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
GND
VCCAUX DONE
VCCAUX PROG_B
VCCAUX TCK
CONFIG
CONFIG
JTAG
D14
K2
B13
A2
VCCAUX TDI
JTAG
L12
P2
VCCAUX TDO
A14
B14
A5
JTAG
VCCAUX TMS
JTAG
User I/Os by Bank
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX
VCCAUX
VCCAUX
Table 20 indicates how the 92 available user-I/O pins are
distributed between the four I/O banks on the CP132 pack-
age.
E12
K1
Table 11: User I/Os Per Bank for the XC3S250E and XC3S500E in the CP132 Package
All Possible I/O Pins by Type
Package
Edge
Maximum
I/O
I/O Bank
I/O
11
0
INPUT
DUAL
1
VREF
GCLK
Top
0
1
2
3
22
23
26
21
92
0
0
0
0
0
2
2
2
2
8
8
0
Right
21
24
0
Bottom
Left
0
0
11
22
8
TOTAL
46
16
migrate between the XC3S250E and XC3S500E without
further consideration.
Footprint Migration Differences
The production XC3S250E and XC3S500E FPGAs have
identical footprints in the CP132 package. Designs can
12
www.xilinx.com
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
CP132 Footprint
Bank 0
8
1
2
3
4
5
6
7
9
10
11
12
13
I/O
14
I/O
I/O
L05N_0
GCLK7
I/O
L04P_0
GCLK4
I/O
L11P_0
I/O
L02N_0
VCCAUX
PROG_B
GND
GND
TDI
VCCINT
TDO
VCCO_0 L07P_0
A
B
C
D
E
F
L01P_0
GCLK10
I/O
L11N_0
HSWAP
I/O
I/O
INPUT
L06P_0
GCLK8
I/O
L05P_0
I/O
L03N_0
I/O
L01N_3
I/O
L01P_3
I/O
L10P_0
I/O
L09P_0
I/O
L02P_0
VCCO_0
TCK
TMS
L07N_0
L08P_0
GCLK11
GCLK6
VREF_0
I/O
I/O
L04N_0
GCLK5
I/O
L10N_1
LDC2
I/O
L10P_1
LDC1
INPUT
L06N_0
GCLK9
I/O
L02N_3
I/O
L02P_3
I/O
L10N_0
I/O
L09N_0
I/O
L03P_0
I/O
L01N_0
L08N_0
GND
GND
GND
VREF_0
I/O
L09N_1
LDC0
I/O
L09P_1
HDC
I/O
L03N_3
I/O
L03P_3
VCCINT
GND
VCCINT
GND
INPUT
VREF_3
VCCO_3
VCCAUX
VCCO_1
I/O
L05P_3
I/O
L04N_3
I/O
L04P_3
I/O
L08N_1
A1
I/O
L08P_1
A2
I/O
A0
LHCLK2 LHCLK1 LHCLK0
I/O
L05N_3
LHCLK3
IRDY2
I/O
L06P_3
LHCLK4
TRDY2
I/O
I/O
INPUT
VREF_1
L07N_1
A3
L07P_1
A4
G
H
J
GND
RHCLK7 RHCLK6
I/O
I/O
I/O
L06N_3
I/O
L07P_3
I/O
L07N_3
L06P_1
L06N_1
A5
A6
RHCLK4
IRDY1
GND
I/O
LHCLK5 LHCLK6 LHCLK7
RHCLK5
I/O
L04N_1
A9
I/O
L05P_1
A8
L05N_1
A7
VCCO_3
I/O
GND
RHCLK3
TRDY1
RHCLK1 RHCLK2
I/O
I/O
VREF_3
I/O
GND
L04P_1
A10
VCCINT
VCCAUX
K
L
VREF_1
RHCLK0
I/O
L03P_1
A12
I/O
L03N_1
A11
I/O
L08P_3
I/O
L08N_3
I/O
L09P_3
VCCINT
I/O
I/O
INPUT
L05P_2
RDWR_B
GCLK0
I/O
I/O
L01P_2
CSO_B
I/O
L08N_2
A22
I/O
L09N_2
A20
I/O
L02P_1
A14
I/O
L02N_1
A13
I/O
L09N_3
L03P_2
D7
L04P_2
D4
L10N_2
VS1
GND
M
N
P
GND
VCCO_2
VCCO_1
GCLK12 GCLK14
A18
I/O
I/O
I/O
INPUT
I/O
I/O
I/O
L01N_2
INIT_B
I/O
L08P_2
A23
I/O
L09P_2
A21
I/O
L11N_2
CCLK
I/O
L01P_1
A16
I/O
L01N_1
A15
I/O
M1
INPUT
VREF_2
L02N_2
MOSI
L03N_2
D6
L04N_2
D3
L05N_2
L07N_2
DIN
L10P_2
VS2
M2
CSI_B
GCLK13 GCLK15
GCLK1
D0
A19
I/O
L02P_2
DOUT
BUSY
I/O
I/O
I/O
I/O
L07P_2
M0
I/O
I/O
VREF_2
L06P_2
D2
L06N_2
D1
L11P_2
VS0
VCCO_2
GND
D5
VCCAUX
GND
GND
VCCINT
DONE
GCLK2
GCLK3
A17
Bank 2
DS312-4_07_031105
Figure 3: CP132 Package Footprint (top view)
I/O: Unrestricted,
general-purpose user I/O
DUAL: Configuration pin, then
possible user I/O
VREF: User I/O or input
voltage reference for bank
22
0
42
16
4
8
INPUT: Unrestricted,
general-purpose input pin
GCLK: User I/O, input, or
global buffer input
VCCO: Output voltage supply
for bank
8
6
4
CONFIG: Dedicated
configuration pins
JTAG: Dedicated JTAG port
pins
VCCINT: Internal core supply
voltage (+1.2V)
2
N.C.: Not connected
GND: Ground
VCCAUX: Auxiliary supply
voltage (+2.5V)
0
16
DS312-4 (v1.1) March 21, 2005
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13
Advance Product Specification
R
Pinout Descriptions
mode. In larger packages, there are 24 BPI address out-
puts.
TQ144: 144-lead Thin Quad Flat
Package
The XC3S100E and the XC3S250E FPGAs are available in
the 144-lead thin quad flat package, TQ144. Both devices
share a common footprint for this package as shown in
Table 12 and Figure 4.
An electronic version of this package pinout table and foot-
print diagram is available for download from the Xilinx web
site at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip.
Pinout Table
Table 12 lists all the package pins. They are sorted by bank
number and then by pin name of the largest device. Pins
that form a differential I/O pair appear together in the table.
The table also shows the pin number for each pin and the
pin type, as defined earlier.
Table 12 shows the pinout for production Spartan-3E
FPGAs in the VQ100 package. The XC3S100 engineering
samples have a slightly different pinout, as described in
Table 15.
The TQ144 package only supports 20 address output pins
in the Byte-wide Peripheral Interface (BPI) configuration
Table 12: TQ144 Package Pinout
Bank
0
XC3S100E Pin Name
XC3S250E Pin Name
TQ144 Pin
P132
P124
P113
P112
P117
P116
P123
P122
P126
P125
P131
P130
P135
P134
P140
P139
P143
P142
P111
P114
P136
P141
P120
P119
P129
P128
Type
I/O
IO
IO
0
IO/VREF_0
IO/VREF_0
VREF
I/O
0
IO_L01N_0
IO_L01N_0
0
IO_L01P_0
IO_L01P_0
I/O
0
IO_L02N_0
IO_L02N_0
I/O
0
IO_L02P_0
IO_L02P_0
I/O
0
IO_L04N_0/GCLK5
IO_L04P_0/GCLK4
IO_L05N_0/GCLK7
IO_L05P_0/GCLK6
IO_L07N_0/GCLK11
IO_L07P_0/GCLK10
IO_L08N_0/VREF_0
IO_L08P_0
IO_L04N_0/GCLK5
IO_L04P_0/GCLK4
IO_L05N_0/GCLK7
IO_L05P_0/GCLK6
IO_L07N_0/GCLK11
IO_L07P_0/GCLK10
IO_L08N_0/VREF_0
IO_L08P_0
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
VREF
I/O
0
0
0
0
0
0
0
0
IO_L09N_0
IO_L09N_0
I/O
0
IO_L09P_0
IO_L09P_0
I/O
0
IO_L10N_0/HSWAP
IO_L10P_0
IO_L10N_0/HSWAP
IO_L10P_0
DUAL
I/O
0
0
IP
IP
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
GCLK
GCLK
0
IP
IP
0
IP
IP
0
IP
IP
0
IP_L03N_0
IP_L03N_0
0
IP_L03P_0
IP_L03P_0
0
IP_L06N_0/GCLK9
IP_L06P_0/GCLK8
IP_L06N_0/GCLK9
IP_L06P_0/GCLK8
0
14
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
Table 12: TQ144 Package Pinout (Continued)
Bank
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
XC3S100E Pin Name
VCCO_0
XC3S250E Pin Name
VCCO_0
TQ144 Pin
P121
P138
P98
Type
VCCO
VCCO_0
VCCO_0
VCCO
IO/A0
IO/A0
DUAL
IO/VREF_1
IO/VREF_1
P83
VREF
IO_L01N_1/A15
IO_L01P_1/A16
IO_L02N_1/A13
IO_L02P_1/A14
IO_L03N_1/A11
IO_L03P_1/A12
IO_L04N_1/A9/RHCLK1
IO_L04P_1/A10/RHCLK0
IO_L05N_1/A7/RHCLK3/TRDY1
IO_L05P_1/A8/RHCLK2
IO_L06N_1/A5/RHCLK5
IO_L06P_1/A6/RHCLK4/IRDY1
IO_L07N_1/A3/RHCLK7
IO_L07P_1/A4/RHCLK6
IO_L08N_1/A1
IO_L08P_1/A2
IO_L09N_1/LDC0
IO_L09P_1/HDC
IO_L10N_1/LDC2
IO_L10P_1/LDC1
IP
IO_L01N_1/A15
IO_L01P_1/A16
IO_L02N_1/A13
IO_L02P_1/A14
IO_L03N_1/A11
IO_L03P_1/A12
IO_L04N_1/A9/RHCLK1
IO_L04P_1/A10/RHCLK0
IO_L05N_1/A7/RHCLK3
IO_L05P_1/A8/RHCLK2
IO_L06N_1/A5/RHCLK5
IO_L06P_1/A6/RHCLK4
IO_L07N_1/A3/RHCLK7
IO_L07P_1/A4/RHCLK6
IO_L08N_1/A1
IO_L08P_1/A2
IO_L09N_1/LDC0
IO_L09P_1/HDC
IO_L10N_1/LDC2
IO_L10P_1/LDC1
IP
P75
DUAL
P74
DUAL
P77
DUAL
P76
DUAL
P82
DUAL
P81
DUAL
P86
RHCLK/DUAL
RHCLK/DUAL
RHCLK/DUAL
RHCLK/DUAL
RHCLK/DUAL
RHCLK/DUAL
RHCLK/DUAL
RHCLK/DUAL
DUAL
P85
P88
P87
P92
P91
P94
P93
P97
P96
DUAL
P104
P103
P106
P105
P78
DUAL
DUAL
DUAL
DUAL
INPUT
IP
IP
P84
INPUT
IP
IP
P89
INPUT
IP
IP
P101
P107
P95
INPUT
IP
IP
INPUT
IP/VREF_1
IP/VREF_1
VREF
VCCO_1
VCCO_1
P79
VCCO
VCCO_1
VCCO_1
P100
P52
VCCO
IO/D5
IO/D5
DUAL
IO/M1
IO/M1
P60
DUAL
IP/VREF_2
IO/VREF_2
P66
100E: VREF(INPUT)
250E: VREF(I/O)
DS312-4 (v1.1) March 21, 2005
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15
Advance Product Specification
R
Pinout Descriptions
Table 12: TQ144 Package Pinout (Continued)
Bank
2
XC3S100E Pin Name
IO_L01N_2/INIT_B
XC3S250E Pin Name
IO_L01N_2/INIT_B
TQ144 Pin
P40
P39
P44
P43
P51
P50
P54
P53
P59
P58
P63
P62
P68
P67
P71
P70
P38
P41
P69
P48
P47
P57
P56
P42
P49
P64
P31
Type
DUAL
2
IO_L01P_2/CSO_B
IO_L02N_2/MOSI/CSI_B
IO_L02P_2/DOUT/BUSY
IO_L04N_2/D6/GCLK13
IO_L04P_2/D7/GCLK12
IO_L05N_2/D3/GCLK15
IO_L05P_2/D4/GCLK14
IO_L07N_2/D1/GCLK3
IO_L07P_2/D2/GCLK2
IO_L08N_2/DIN/D0
IO_L08P_2/M0
IO_L01P_2/CSO_B
IO_L02N_2/MOSI/CSI_B
IO_L02P_2/DOUT/BUSY
IO_L04N_2/D6/GCLK13
IO_L04P_2/D7/GCLK12
IO_L05N_2/D3/GCLK15
IO_L05P_2/D4/GCLK14
IO_L07N_2/D1/GCLK3
IO_L07P_2/D2/GCLK2
IO_L08N_2/DIN/D0
IO_L08P_2/M0
DUAL
2
DUAL
2
DUAL
2
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL
2
2
2
2
2
2
2
DUAL
2
IO_L09N_2/VS1/A18
IO_L09P_2/VS2/A19
IO_L10N_2/CCLK
IO_L10P_2/VS0/A17
IP
IO_L09N_2/VS1/A18
IO_L09P_2/VS2/A19
IO_L10N_2/CCLK
IO_L10P_2/VS0/A17
IP
DUAL
2
DUAL
2
DUAL
2
DUAL
2
INPUT
2
IP
IP
INPUT
2
IP
IP
INPUT
2
IP_L03N_2/VREF_2
IP_L03P_2
IP_L03N_2/VREF_2
IP_L03P_2
VREF
2
INPUT
2
IP_L06N_2/M2/GCLK1
IP_L06P_2/RDWR_B/GCLK0
VCCO_2
IP_L06N_2/M2/GCLK1
IP_L06P_2/RDWR_B/GCLK0
VCCO_2
DUAL/GCLK
DUAL/GCLK
VCCO
2
2
2
VCCO_2
VCCO_2
VCCO
2
VCCO_2
VCCO_2
VCCO
3
IP/VREF_3
IO/VREF_3
100E: VREF(INPUT)
250E: VREF(I/O)
3
3
3
3
3
3
3
3
IO_L01N_3
IO_L01N_3
P3
P2
I/O
I/O
IO_L01P_3
IO_L01P_3
IO_L02N_3/VREF_3
IO_L02P_3
IO_L02N_3/VREF_3
IO_L02P_3
P5
VREF
I/O
P4
IO_L03N_3
IO_L03N_3
P8
I/O
IO_L03P_3
IO_L03P_3
P7
I/O
IO_L04N_3/LHCLK1
IO_L04P_3/LHCLK0
IO_L04N_3/LHCLK1
IO_L04P_3/LHCLK0
P15
P14
LHCLK
LHCLK
16
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
Table 12: TQ144 Package Pinout (Continued)
Bank
XC3S100E Pin Name
IO_L05N_3/LHCLK3/IRDY2
IO_L05P_3/LHCLK2
IO_L06N_3/LHCLK5
IO_L06P_3/LHCLK4/TRDY2
IO_L07N_3/LHCLK7
IO_L07P_3/LHCLK6
IO_L08N_3
XC3S250E Pin Name
IO_L05N_3/LHCLK3
TQ144 Pin
P17
P16
P21
P20
P23
P22
P26
P25
P33
P32
P35
P34
P6
Type
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
I/O
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO_L05P_3/LHCLK2
IO_L06N_3/LHCLK5
IO_L06P_3/LHCLK4
IO_L07N_3/LHCLK7
IO_L07P_3/LHCLK6
IO_L08N_3
IO_L08P_3
IO_L08P_3
I/O
IO_L09N_3
IO_L09N_3
I/O
IO_L09P_3
IO_L09P_3
I/O
IO_L10N_3
IO_L10N_3
I/O
IO_L10P_3
IO_L10P_3
I/O
IP
IP
INPUT
IO
IP
P10
100E: I/O
250E: INPUT
3
3
3
IP
IP
IO
IP
IP
IP
P18
P24
P29
INPUT
INPUT
100E: I/O
250E: INPUT
3
IP
IP
P36
P12
P13
P28
P11
P19
P27
P37
P46
P55
P61
P73
P90
P99
P118
P127
P133
INPUT
VREF
VCCO
VCCO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
3
IP/VREF_3
VCCO_3
VCCO_3
GND
IP/VREF_3
VCCO_3
VCCO_3
GND
3
3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DS312-4 (v1.1) March 21, 2005
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17
Advance Product Specification
R
Pinout Descriptions
Table 12: TQ144 Package Pinout (Continued)
Bank
XC3S100E Pin Name
XC3S250E Pin Name
TQ144 Pin
P72
Type
CONFIG
CONFIG
JTAG
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
DONE
DONE
PROG_B
TCK
PROG_B
TCK
P1
P110
P144
P109
P108
P30
TDI
TDI
JTAG
TDO
TDO
JTAG
TMS
TMS
JTAG
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
P65
P102
P137
P9
P45
P80
P115
User I/Os by Bank
Table 13 and Table 14 indicate how the 108 available
user-I/O pins are distributed between the four I/O banks on
the TQ144 package.
Table 13: User I/Os Per Bank for the XC3S100E in the TQ144 Package
All Possible I/O Pins by Type
Package
Edge
Maximum
I/O
I/O Bank
I/O
9
INPUT
DUAL
1
VREF
GCLK
Top
0
1
2
3
26
28
6
5
2
2
2
3
9
8
0
Right
0
21
20
0
Bottom
Left
26
0
4
0
28
13
22
4
8
TOTAL
108
19
42
16
Table 14: User I/Os Per Bank for the XC3S250E in TQ144 Package
All Possible I/O Pins by Type
Package
Edge
Maximum
I/O
I/O Bank
I/O
9
INPUT
DUAL
1
VREF
GCLK
Top
0
1
2
3
26
28
6
5
2
2
2
3
9
8
0
Right
0
21
20
0
Bottom
Left
26
0
4
0
28
11
20
6
8
TOTAL
108
21
42
16
18
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
The arrows indicate the direction for easy migration. For
example, a left-facing arrow indicates that the pin on the
XC3S250E unconditionally migrates to the pin on the
XC3S100E. It may be possible to migrate the opposite
direction depending on the I/O configuration. For example,
an I/O pin (Type = I/O) can migrate to an input-only pin
(Type = INPUT) if the I/O pin is configured as an input.
Footprint Migration Differences
Table 15 summarizes any footprint and functionality differ-
ences between the XC3S100E and the XC3S250E FPGAs
that may affect easy migration between devices. There are
four such pins. All other pins not listed in Table 15 uncondi-
tionally migrate between Spartan-3E devices available in
the TQ144 package.
Table 15: TQ144 Footprint Migration Differences
TQ144 Pin
P10
Bank
XC3S100E Type
Migration
XC3S250E Type
INPUT
3
3
3
2
I/O
I/O
ꢁ
ꢁ
ꢂ
ꢂ
4
P29
INPUT
P31
VREF(INPUT)
VREF(INPUT)
VREF(I/O)
VREF(I/O)
P66
DIFFERENCES
Legend:
ꢂ
This pin can unconditionally migrate from the device on the left to the device on the right. Migration in the other direction may be
possible depending on how the pin is configured for the device on the right.
ꢁ
This pin can unconditionally migrate from the device on the right to the device on the left. Migration in the other direction may be
possible depending on how the pin is configured for the device on the left.
The pinout changed slightly between the XC3S100E engi-
neering samples and the production devices, as shown in
Table 16. In the engineering samples, the mode select pins
M1 and M0 overlap with two global clock inputs feeding the
bottom edge global buffers and DCMs. In the production
devices, the mode pins are swapped with parallel mode
data pins, D1 and D2. This way, these two mode pins do not
interfere with global clock inputs.
Table 16: XC3S100E Pinout Changes between
Production Devices and Engineering Samples
XC3S100E
Production
Devices
XC3S100E
Engineering
Samples
TQ144 Pin
P58
D2/GCLK2
D1/GCLK3
M1
M1/GCLK2
M0/GCLK3
D2
P59
P60
P62
M0
D1
DS312-4 (v1.1) March 21, 2005
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19
Advance Product Specification
R
Pinout Descriptions
between the XC3S100E and XC3S250E. Engineering sam-
ple footprint is slightly different.
TQ144 Footprint
Note pin 1 indicator in top-left corner and logo orientation.
Double arrows (ꢁꢂ) indicates a pinout migration difference
PROG_B
1
2
108 TMS
107 IP
Bank 0
IO_L01P_3
IO_L01N_3
IO_L02P_3
IO_L02N_3/VREF_3
IP
3
4
106 IO_L10N_1/LDC2
105 IO_L10P_1/LDC1
104 IO_L09N_1/LDC0
103 IO_L09P_1/HDC
102 VCCAUX
5
6
IO_L03P_3
IO_L03N_3
VCCINT
7
8
101 IP
9
100 VCCO_1
(ꢁꢂ) IP
10
99 GND
GND 11
IP/VREF_3 12
98 IO/A0
97 IO_L08N_1/A1
96 IO_L08P_1/A2
95 IP/VREF_1
VCCO_3 13
IO_L04P_3/LHCLK0 14
IO_L04N_3/LHCLK1 15
IO_L05P_3/LHCLK2 16
IO_L05N_3/LHCLK3 17
IP 18
94 IO_L07N_1/A3/RHCLK7
93 IO_L07P_1/A4/RHCLK6
92 IO_L06N_1/A5/RHCLK5
91 IO_L06P_1/A6/RHCLK4
90 GND
GND 19
IO_L06P_3/LHCLK4 20
IO_L06N_3/LHCLK5 21
IO_L07P_3/LHCLK6 22
IO_L07N_3/LHCLK7 23
IP 24
89 IP
88 IO_L05N_1/A7/RHCLK3
87 IO_L05P_1/A8/RHCLK2
86 IO_L04N_1/A9/RHCLK1
85 IO_L04P_1/A10/RHCLK0
84 IP
IO_L08P_3 25
IO_L08N_3 26
83 IO/VREF_1
GND 27
82 IO_L03N_1/A11
81 IO_L03P_1/A12
80 VCCINT
VCCO_3 28
(ꢁꢂ) IP
VCCAUX 30
29
79 VCCO_1
(ꢁꢂ) IO/VREF_3
31
IO_L09P_3 32
IO_L09N_3 33
IO_L10P_3 34
IO_L10N_3 35
IP 36
78 IP
77 IO_L02N_1/A13
76 IO_L02P_1/A14
75 IO_L01N_1/A15
74
73
IO_L01P_1/A16
GND
Bank 2
DS312-4_01_030705
Figure 4: TQ144 Package Production Footprint (top view)
DUAL: Configuration pin, then
I/O: Unrestricted,
VREF: User I/O or input
20
21
2
42
16
4
9
9
4
4
general-purpose user I/O
possible user I/O
voltage reference for bank
INPUT: Unrestricted,
GCLK: User I/O, input, or
global buffer input
VCCO: Output voltage supply
for bank
general-purpose input pin
CONFIG: Dedicated
configuration pins
JTAG: Dedicated JTAG port
pins
VCCINT: Internal core supply
voltage (+1.2V)
N.C.: Not connected
GND: Ground
VCCAUX: Auxiliary supply
voltage (+2.5V)
0
13
20
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
Table 17: PQ208 Package Pinout
PQ208: 208-pin Plastic Quad Flat
Package
The 208-pin plastic quad flat package, PQ208, supports two
different Spartan-3E FPGAs, including the XC3S250E and
the XC3S500E.
XC3S250E
XC3S500E
Pin Name
PQ208
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin
Type
I/O
IO_L13P_0
P196
P200
P199
P203
P202
P206
P205
P159
P169
P194
P204
P175
P174
P184
P183
P176
P191
P201
P107
P106
P109
P108
P113
P112
P116
P115
P120
P119
P123
P122
Table 17 lists all the PQ208 package pins. They are sorted
by bank number and then by pin name. Pairs of pins that
form a differential I/O pair appear together in the table. The
table also shows the pin number for each pin and the pin
type, as defined earlier.
IO_L14N_0/VREF_0
IO_L14P_0
VREF
I/O
IO_L15N_0
I/O
IO_L15P_0
I/O
An electronic version of this package pinout table and foot-
print diagram is available for download from the Xilinx web-
site at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip.
IO_L16N_0/HSWAP
IO_L16P_0
DUAL
I/O
IP
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
GCLK
GCLK
VCCO
VCCO
VCCO
DUAL
DUAL
DUAL
DUAL
VREF
I/O
Pinout Table
IP
Table 17: PQ208 Package Pinout
IP
XC3S250E
IP
XC3S500E
Pin Name
PQ208
Pin
Bank
0
Type
I/O
IP_L06N_0
IO
P187
P179
P161
P160
P163
P162
P165
P164
P168
P167
P172
P171
P178
P177
P181
P180
P186
P185
P190
P189
P193
P192
P197
IP_L06P_0
0
IO/VREF_0
VREF
I/O
IP_L09N_0/GCLK9
IP_L09P_0/GCLK8
VCCO_0
0
IO_L01N_0
0
IO_L01P_0
I/O
0
IO_L02N_0/VREF_0
IO_L02P_0
VREF
I/O
VCCO_0
0
VCCO_0
0
IO_L03N_0
I/O
IO_L01N_1/A15
IO_L01P_1/A16
IO_L02N_1/A13
IO_L02P_1/A14
IO_L03N_1/VREF_1
IO_L03P_1
0
IO_L03P_0
I/O
0
IO_L04N_0/VREF_0
IO_L04P_0
VREF
I/O
0
0
IO_L05N_0
I/O
0
IO_L05P_0
I/O
0
IO_L07N_0/GCLK5
IO_L07P_0/GCLK4
IO_L08N_0/GCLK7
IO_L08P_0/GCLK6
IO_L10N_0/GCLK11
IO_L10P_0/GCLK10
IO_L11N_0
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
I/O
IO_L04N_1
I/O
0
IO_L04P_1
I/O
0
IO_L05N_1/A11
IO_L05P_1/A12
IO_L06N_1/VREF_1
IO_L06P_1
DUAL
DUAL
VREF
I/O
0
0
0
0
IO_L07N_1/A9/RHCLK1
IO_L07P_1/A10/RHCLK0
IO_L08N_1/A7/RHCLK3
IO_L08P_1/A8/RHCLK2
P127 RHCLK/DUAL
P126 RHCLK/DUAL
P129 RHCLK/DUAL
P128 RHCLK/DUAL
0
IO_L11P_0
I/O
0
IO_L12N_0/VREF_0
IO_L12P_0
VREF
I/O
0
0
IO_L13N_0
I/O
DS312-4 (v1.1) March 21, 2005
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21
Advance Product Specification
R
Pinout Descriptions
Table 17: PQ208 Package Pinout
Table 17: PQ208 Package Pinout
XC3S250E
XC3S500E
XC3S250E
XC3S500E
Pin Name
PQ208
Pin
PQ208
Pin
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
Pin Name
IO_L09N_1/A5/RHCLK5
IO_L09P_1/A6/RHCLK4
IO_L10N_1/A3/RHCLK7
IO_L10P_1/A4/RHCLK6
IO_L11N_1/A1
IO_L11P_1/A2
IO_L12N_1/A0
IO_L12P_1
Type
Bank
2
Type
I/O
P133 RHCLK/DUAL
P132 RHCLK/DUAL
P135 RHCLK/DUAL
P134 RHCLK/DUAL
IO_L04N_2
P63
P62
P65
P64
P69
P68
P75
P74
P78
P77
P83
P82
P87
P86
P90
P89
P94
P93
P97
P96
P100
P99
P103
P102
P54
P91
P101
P58
P57
P72
P71
P81
P80
2
IO_L04P_2
I/O
2
IO_L05N_2
I/O
2
IO_L05P_2
I/O
P138
P137
P140
P139
P145
P144
P147
P146
P151
P150
P153
P152
P110
P118
P124
P130
P142
P148
P154
P136
P114
P125
P143
P76
DUAL
DUAL
DUAL
I/O
2
IO_L06N_2
I/O
2
IO_L06P_2
I/O
2
IO_L08N_2/D6/GCLK13
IO_L08P_2/D7/GCLK12
IO_L09N_2/D3/GCLK15
IO_L09P_2/D4/GCLK14
IO_L11N_2/D1/GCLK3
IO_L11P_2/D2/GCLK2
IO_L12N_2/DIN/D0
IO_L12P_2/M0
IO_L13N_2
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL
2
IO_L13N_1
I/O
2
IO_L13P_1
I/O
2
IO_L14N_1
I/O
2
IO_L14P_1
I/O
2
IO_L15N_1/LDC0
IO_L15P_1/HDC
IO_L16N_1/LDC2
IO_L16P_1/LDC1
IP
DUAL
DUAL
DUAL
DUAL
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VREF
VCCO
VCCO
VCCO
DUAL
DUAL
VREF
DUAL
DUAL
DUAL
DUAL
2
2
DUAL
2
I/O
2
IO_L13P_2
I/O
2
IO_L14N_2/A22
IO_L14P_2/A23
IO_L15N_2/A20
IO_L15P_2/A21
IO_L16N_2/VS1/A18
IO_L16P_2/VS2/A19
IO_L17N_2/CCLK
IO_L17P_2/VS0/A17
IP
DUAL
IP
2
DUAL
IP
2
DUAL
IP
2
DUAL
IP
2
DUAL
IP
2
DUAL
IP
2
DUAL
IP/VREF_1
2
DUAL
VCCO_1
2
INPUT
INPUT
INPUT
INPUT
INPUT
VREF
VCCO_1
2
IP
VCCO_1
2
IP
IO/D5
2
IP_L02N_2
IO/M1
P84
2
IP_L02P_2
IO/VREF_2
P98
2
IP_L07N_2/VREF_2
IP_L07P_2
IO_L01N_2/INIT_B
IO_L01P_2/CSO_B
IO_L03N_2/MOSI/CSI_B
IO_L03P_2/DOUT/BUSY
P56
2
INPUT
DUAL/GCLK
DUAL/GCLK
P55
2
IP_L10N_2/M2/GCLK1
P61
2
IP_L10P_2/RDWR_B/
GCLK0
P60
2
VCCO_2
P59
VCCO
22
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
Table 17: PQ208 Package Pinout
Table 17: PQ208 Package Pinout
XC3S250E
XC3S500E
Pin Name
XC3S250E
XC3S500E
Pin Name
PQ208
Pin
PQ208
Bank
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Type
VCCO
VCCO
VREF
I/O
Bank
3
Pin
P49
P6
Type
I/O
VCCO_2
P73
P88
P45
P3
IO_L16P_3
VCCO_2
3
IP
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VREF
VCCO
VCCO
VCCO
GND
IO/VREF_3
3
IP
P14
P26
P32
P43
P51
P20
P21
P38
P46
P10
P17
P27
P37
P52
P53
P70
P79
P85
P95
P105
P121
P131
P141
P156
P173
P182
P188
P198
P208
P104
P1
IO_L01N_3
3
IP
IO_L01P_3
P2
I/O
3
IP
IO_L02N_3/VREF_3
IO_L02P_3
P5
VREF
I/O
3
IP
P4
3
IP
IO_L03N_3
P9
I/O
3
IP/VREF_3
VCCO_3
VCCO_3
VCCO_3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
IO_L03P_3
P8
I/O
3
IO_L04N_3
P12
P11
P16
P15
P19
P18
P23
P22
P25
P24
P29
P28
P31
P30
P34
P33
P36
P35
P40
P39
P42
P41
P48
P47
P50
I/O
3
IO_L04P_3
I/O
3
IO_L05N_3
I/O
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
IO_L05P_3
I/O
GND
IO_L06N_3
I/O
GND
IO_L06P_3
I/O
GND
IO_L07N_3/LHCLK1
IO_L07P_3/LHCLK0
IO_L08N_3/LHCLK3
IO_L08P_3/LHCLK2
IO_L09N_3/LHCLK5
IO_L09P_3/LHCLK4
IO_L10N_3/LHCLK7
IO_L10P_3/LHCLK6
IO_L11N_3
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
I/O
GND
GND
GND
GND
GND
GND
GND
GND
GND
IO_L11P_3
I/O
GND
IO_L12N_3
I/O
GND
IO_L12P_3
I/O
GND
IO_L13N_3
I/O
GND
IO_L13P_3
I/O
GND
IO_L14N_3
I/O
GND
IO_L14P_3
I/O
GND
IO_L15N_3
I/O
VCCAUX DONE
VCCAUX PROG_B
VCCAUX TCK
CONFIG
CONFIG
JTAG
IO_L15P_3
I/O
IO_L16N_3
I/O
P158
DS312-4 (v1.1) March 21, 2005
www.xilinx.com
23
Advance Product Specification
R
Pinout Descriptions
Table 17: PQ208 Package Pinout
Table 17: PQ208 Package Pinout
XC3S250E
XC3S500E
Pin Name
XC3S250E
XC3S500E
Pin Name
PQ208
Pin
PQ208
Pin
Bank
Type
Bank
Type
VCCAUX TDI
VCCAUX TDO
VCCAUX TMS
P207
P157
P155
P7
JTAG
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
P67
P117
P170
VCCINT
VCCINT
VCCINT
JTAG
JTAG
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCINT VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
User I/Os by Bank
P44
Table 18 indicates how the 158 available user-I/O pins are
distributed between the four I/O banks on the PQ208 pack-
age.
P66
P92
P111
P149
P166
P195
P13
Footprint Migration Differences
The XC3S250E and XC3S500E FPGAs have identical foot-
prints in the PQ208 package. Designs can migrate between
the XC3S250E and XC3S500E without further consider-
ation.
Table 18: User I/Os Per Bank for the XC3S250E and XC3S500E in the PQ208 Package
All Possible I/O Pins by Type
Package
Edge
Maximum
I/O
I/O Bank
I/O
18
9
INPUT
DUAL
1
VREF
GCLK
Top
0
1
2
3
38
40
6
7
5
3
8
0
Right
21
24
0
Bottom
Left
40
8
6
2
0
40
23
58
6
3
8
TOTAL
158
25
46
13
16
24
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
PQ208 Footprint (Left)
PROG_B
IO_L01P_3
1
2
Bank 0
IO_L01N_3
IO_L02P_3
IO_L02N_3/VREF_3
IP
3
4
5
6
7
8
9
VCCAUX
IO_L03P_3
IO_L03N_3
GND 10
IO_L04P_3 11
IO_L04N_3 12
VCCINT 13
IP 14
IO_L05P_3 15
IO_L05N_3 16
GND 17
IO_L06P_3 18
IO_L06N_3 19
IP/VREF_3 20
VCCO_3 21
IO_L07P_3/LHCLK0 22
IO_L07N_3/LHCLK1 23
IO_L08P_3/LHCLK2 24
IO_L08N_3/LHCLK3 25
IP 26
GND 27
IO_L09P_3/LHCLK4 28
IO_L09N_3/LHCLK5 29
IO_L10P_3/LHCLK6 30
IO_L10N_3/LHCLK7 31
IP 32
IO_L11P_3 33
IO_L11N_3 34
IO_L12P_3 35
IO_L12N_3 36
GND 37
VCCO_3 38
IO_L13P_3 39
IO_L13N_3 40
IO_L14P_3 41
IO_L14N_3 42
IP 43
VCCAUX 44
IO/VREF_3 45
VCCO_3 46
IO_L15P_3 47
IO_L15N_3 48
IO_L16P_3 49
IO_L16N_3 50
IP 51
Bank 2
GND 52
DS312-4_03_030705
Figure 5: PQ208 Footprint (Left)
DS312-4 (v1.1) March 21, 2005
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25
Advance Product Specification
R
Pinout Descriptions
PQ208 Footprint (Right)
156 GND
155 TMS
Bank 0
154 IP
153 IO_L16N_1/LDC2
152 IO_L16P_1/LDC1
151 IO_L15N_1/LDC0
150 IO_L15P_1/HDC
149 VCCAUX
148 IP
147 IO_L14N_1
146 IO_L14P_1
145 IO_L13N_1
144 IO_L13P_1
143 VCCO_1
142 IP
141 GND
140 IO_L12N_1/A0
139 IO_L12P_1
138 IO_L11N_1/A1
137 IO_L11P_1/A2
136 IP/VREF_1
135 IO_L10N_1/A3/RHCLK7
134 IO_L10P_1/A4/RHCLK6
133 IO_L09N_1/A5/RHCLK5
132 IO_L09P_1/A6/RHCLK4
131 GND
130 IP
129 IO_L08N_1/A7/RHCLK3
128 IO_L08P_1/A8/RHCLK2
127 IO_L07N_1/A9/RHCLK1
126 IO_L07P_1/A10/RHCLK
125 VCCO_1
124 IP
123 IO_L06N_1/VREF_1
122 IO_L06P_1
121 GND
120 IO_L05N_1/A11
119 IO_L05P_1/A12
118 IP
117 VCCINT
116 IO_L04N_1
115 IO_L04P_1
114 VCCO_1
113 IO_L03N_1/VREF_1
112 IO_L03P_1
111 VCCAUX
110 IP
109 IO_L02N_1/A13
108 IO_L02P_1/A14
107 IO_L01N_1/A15
106 IO_L01P_1/A16
105 GND
Bank 2
DS312-4_04_030705
Figure 6: PQ208 Footprint (Right)
26
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
If the table row is highlighted in tan, then this is an instance
where an unconnected pin on the XC3S250E FPGA maps
to a VREF pin on the XC3S500E and XC3S1200E FPGA. If
the FPGA application uses an I/O standard that requires a
VREF voltage reference, connect the highlighted pin to the
VREF voltage supply, even though this does not actually
connect to the XC3S250E FPGA. This VREF connection on
the board allows future migration to the larger devices with-
out modifying the printed-circuit board.
FT256: 256-ball Fine-pitch, Thin Ball
Grid Array
The 256-lead fine-pitch, thin ball grid array package, FT256,
supports three different Spartan-3E FPGAs, including the
XC3S250E, the XC3S500E, and the XC3S1200E.
Table 19 lists all the package pins. They are sorted by bank
number and then by pin name of the largest device. Pins
that form a differential I/O pair appear together in the table.
The table also shows the pin number for each pin and the
pin type, as defined earlier.
All other balls have nearly identical functionality on all three
devices. Table 23 summarizes the Spartan-3E footprint
migration differences for the FT256 package.
The highlighted rows indicate pinout differences between
the XC3S250E, the XC3S500E, and the XC3S1200E
FPGAs. The XC3S250E has 18 unconnected balls, indi-
cated as N.C. (No Connection) in Table 19 and with the
black diamond character (ꢃ) in both Table 19 and in
Figure 7.
An electronic version of this package pinout table and foot-
print diagram is available for download from the Xilinx web
site at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip.
Pinout Table
Table 19: FT256 Package Pinout
FT256
Bank
XC3S250E Pin Name
XC3S500E Pin Name
XC3S1200E Pin Name
Ball
Type
I/O
0
0
0
0
IO
IO
IO
IP
IO
IO
IO
IP
IO
IO
IO
IO
A7
A12
B4
I/O
I/O
B6
250E: INPUT
500E: INPUT
1200E: I/O
0
IP
IP
IO
B10
250E: INPUT
500E: INPUT
1200E: I/O
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO/VREF_0
IO/VREF_0
IO/VREF_0
D9
A14
B14
A13
B13
E11
D11
B11
C11
E10
D10
F9
VREF
I/O
IO_L01N_0
IO_L01N_0
IO_L01N_0
IO_L01P_0
IO_L01P_0
IO_L01P_0
I/O
IO_L03N_0/VREF_0
IO_L03P_0
IO_L03N_0/VREF_0
IO_L03P_0
IO_L03N_0/VREF_0
IO_L03P_0
VREF
I/O
IO_L04N_0
IO_L04N_0
IO_L04N_0
I/O
IO_L04P_0
IO_L04P_0
IO_L04P_0
I/O
IO_L05N_0/VREF_0
IO_L05P_0
IO_L05N_0/VREF_0
IO_L05P_0
IO_L05N_0/VREF_0
IO_L05P_0
VREF
I/O
IO_L06N_0
IO_L06N_0
IO_L06N_0
I/O
IO_L06P_0
IO_L06P_0
IO_L06P_0
I/O
IO_L08N_0/GCLK5
IO_L08P_0/GCLK4
IO_L09N_0/GCLK7
IO_L08N_0/GCLK5
IO_L08P_0/GCLK4
IO_L09N_0/GCLK7
IO_L08N_0/GCLK5
IO_L08P_0/GCLK4
IO_L09N_0/GCLK7
GCLK
GCLK
GCLK
E9
A9
DS312-4 (v1.1) March 21, 2005
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27
Advance Product Specification
R
Pinout Descriptions
Table 19: FT256 Package Pinout (Continued)
FT256
Ball
Bank
XC3S250E Pin Name
IO_L09P_0/GCLK6
IO_L11N_0/GCLK11
IO_L11P_0/GCLK10
IO_L12N_0
XC3S500E Pin Name
IO_L09P_0/GCLK6
IO_L11N_0/GCLK11
IO_L11P_0/GCLK10
IO_L12N_0
XC3S1200E Pin Name
IO_L09P_0/GCLK6
IO_L11N_0/GCLK11
IO_L11P_0/GCLK10
IO_L12N_0
Type
GCLK
GCLK
GCLK
I/O
0
0
0
0
0
0
A10
D8
C8
F8
IO_L12P_0
IO_L12P_0
IO_L12P_0
E8
C7
I/O
N.C. (ꢃ)
IO_L13N_0
IO_L13N_0
250E: N.C.
500E: I/O
1200E: I/O
0
N.C. (ꢃ)
IO_L13P_0
IO_L13P_0
B7
250E: N.C.
500E: I/O
1200E: I/O
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
IO_L14N_0/VREF_0
IO_L14P_0
IO_L15N_0
IO_L15P_0
IO_L17N_0/VREF_0
IO_L17P_0
IO_L18N_0
IO_L18P_0
IO_L19N_0/HSWAP
IO_L19P_0
IP
IO_L14N_0/VREF_0
IO_L14P_0
IO_L15N_0
IO_L15P_0
IO_L17N_0/VREF_0
IO_L17P_0
IO_L18N_0
IO_L18P_0
IO_L19N_0/HSWAP
IO_L19P_0
IP
IO_L14N_0/VREF_0
IO_L14P_0
IO_L15N_0
IO_L15P_0
IO_L17N_0/VREF_0
IO_L17P_0
IO_L18N_0
IO_L18P_0
IO_L19N_0/HSWAP
IO_L19P_0
IP
D7
E7
VREF
I/O
D6
I/O
C6
I/O
A4
VREF
I/O
A5
C4
I/O
C5
I/O
B3
DUAL
I/O
C3
A3
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
GCLK
GCLK
INPUT
INPUT
VCCO
VCCO
VCCO
VCCO
DUAL
IP
IP
IP
C13
C12
D12
C9
IP_L02N_0
IP_L02P_0
IP_L07N_0
IP_L07P_0
IP_L10N_0/GCLK9
IP_L10P_0/GCLK8
IP_L16N_0
IP_L16P_0
VCCO_0
IP_L02N_0
IP_L02P_0
IP_L07N_0
IP_L07P_0
IP_L10N_0/GCLK9
IP_L10P_0/GCLK8
IP_L16N_0
IP_L16P_0
VCCO_0
IP_L02N_0
IP_L02P_0
IP_L07N_0
IP_L07P_0
IP_L10N_0/GCLK9
IP_L10P_0/GCLK8
IP_L16N_0
IP_L16P_0
VCCO_0
C10
B8
A8
E6
D5
B5
VCCO_0
VCCO_0
VCCO_0
B12
F7
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
F10
R15
IO_L01N_1/A15
IO_L01N_1/A15
IO_L01N_1/A15
28
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
Table 19: FT256 Package Pinout (Continued)
FT256
Bank
XC3S250E Pin Name
IO_L01P_1/A16
IO_L02N_1/A13
IO_L02P_1/A14
N.C. (ꢃ)
XC3S500E Pin Name
IO_L01P_1/A16
XC3S1200E Pin Name
IO_L01P_1/A16
Ball
R16
P15
P16
N15
Type
DUAL
DUAL
DUAL
1
1
1
1
IO_L02N_1/A13
IO_L02N_1/A13
IO_L02P_1/A14
IO_L02P_1/A14
IO_L03N_1/VREF_1
IO_L03N_1/VREF_1
250E: N.C.
500E: VREF
1200E: VREF
1
N.C. (ꢃ)
IO_L03P_1
IO_L03P_1
N14
250E: N.C.
500E: I/O
1200E: I/O
1
1
1
IO_L04N_1/VREF_1
IO_L04P_1
IO_L04N_1/VREF_1
IO_L04P_1
IO_L04N_1/VREF_1
IO_L04P_1
M16
N16
L13
VREF
I/O
N.C. (ꢃ)
IO_L05N_1
IO_L05N_1
250E: N.C.
500E: I/O
1200E: I/O
1
N.C. (ꢃ)
IO_L05P_1
IO_L05P_1
L12
250E: N.C.
500E: I/O
1200E: I/O
1
1
1
1
1
1
1
1
1
IO_L06N_1
IO_L06N_1
IO_L06N_1
L15
L14
K12
K13
K14
K15
J16
K16
J13
I/O
I/O
IO_L06P_1
IO_L06P_1
IO_L06P_1
IO_L07N_1/A11
IO_L07P_1/A12
IO_L08N_1/VREF_1
IO_L08P_1
IO_L07N_1/A11
IO_L07P_1/A12
IO_L08N_1/VREF_1
IO_L08P_1
IO_L07N_1/A11
IO_L07P_1/A12
IO_L08N_1/VREF_1
IO_L08P_1
DUAL
DUAL
VREF
I/O
IO_L09N_1/A9/RHCLK1
IO_L09P_1/A10/RHCLK0
IO_L09N_1/A9/RHCLK1
IO_L09P_1/A10/RHCLK0
IO_L09N_1/A9/RHCLK1
IO_L09P_1/A10/RHCLK0
RHCLK/DUAL
RHCLK/DUAL
RHCLK/DUAL
IO_L10N_1/A7/RHCLK3/
TRDY1
IO_L10N_1/A7/RHCLK3/
TRDY1
IO_L10N_1/A7/RHCLK3/
TRDY1
1
1
1
IO_L10P_1/A8/RHCLK2
IO_L11N_1/A5/RHCLK5
IO_L10P_1/A8/RHCLK2
IO_L11N_1/A5/RHCLK5
IO_L10P_1/A8/RHCLK2
IO_L11N_1/A5/RHCLK5
J14
H14
H15
RHCLK/DUAL
RHCLK/DUAL
RHCLK/DUAL
IO_L11P_1/A6/RHCLK4/
IRDY1
IO_L11P_1/A6/RHCLK4/
IRDY1
IO_L11P_1/A6/RHCLK4/
IRDY1
1
1
1
1
1
1
1
IO_L12N_1/A3/RHCLK7
IO_L12P_1/A4/RHCLK6
IO_L13N_1/A1
IO_L12N_1/A3/RHCLK7
IO_L12P_1/A4/RHCLK6
IO_L13N_1/A1
IO_L12N_1/A3/RHCLK7
IO_L12P_1/A4/RHCLK6
IO_L13N_1/A1
H11
H12
G16
G15
G14
G13
F15
RHCLK/DUAL
RHCLK/DUAL
DUAL
IO_L13P_1/A2
IO_L13P_1/A2
IO_L13P_1/A2
DUAL
IO_L14N_1/A0
IO_L14N_1/A0
IO_L14N_1/A0
DUAL
IO_L14P_1
IO_L14P_1
IO_L14P_1
I/O
IO_L15N_1
IO_L15N_1
IO_L15N_1
I/O
DS312-4 (v1.1) March 21, 2005
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29
Advance Product Specification
R
Pinout Descriptions
Table 19: FT256 Package Pinout (Continued)
FT256
Ball
Bank
XC3S250E Pin Name
IO_L15P_1
XC3S500E Pin Name
IO_L15P_1
XC3S1200E Pin Name
IO_L15P_1
Type
I/O
1
1
1
1
F14
F12
F13
E16
IO_L16N_1
IO_L16P_1
N.C. (ꢃ)
IO_L16N_1
IO_L16P_1
IO_L17N_1
IO_L16N_1
I/O
IO_L16P_1
I/O
IO_L17N_1
250E: N.C.
500E: I/O
1200E: I/O
1
N.C. (ꢃ).
IO_L17P_1
IO_L17P_1
E13
250E: N.C.
500E: I/O
1200E: I/O
1
1
1
1
1
1
1
1
1
1
1
1
IO_L18N_1/LDC0
IO_L18N_1/LDC0
IO_L18N_1/LDC0
D14
D15
C15
C16
B16
E14
G12
H16
J11
DUAL
DUAL
DUAL
DUAL
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
IO_L18P_1/HDC
IO_L18P_1/HDC
IO_L18P_1/HDC
IO_L19N_1/LDC2
IO_L19N_1/LDC2
IO_L19N_1/LDC2
IO_L19P_1/LDC1
IO_L19P_1/LDC1
IO_L19P_1/LDC1
IP
IP
IP
IP
IP
IP
IP
IO
IP
IP
IP
IP
IP
IP
IP
IO
IP
IP
IP
IP
IP
IP
IP
IP
J12
M13
M14
250E: I/O
500E: I/O
1200E: INPUT
1
IO/VREF_1
IP/VREF_1
IP/VREF_1
D16
250E: VREF(I/O)
500E:
VREF(INPUT)
1200E:
VREF(INPUT)
1
1
1
1
1
2
IP/VREF_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
IP
IP/VREF_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
IP
IP/VREF_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
IO
H13
E15
G11
K11
M15
M7
VREF
VCCO
VCCO
VCCO
VCCO
250E: INPUT
500E: INPUT
1200E: I/O
2
IP
IP
IO
T12
250E: INPUT
500E: INPUT
1200E: I/O
30
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Advance Product Specification
R
Pinout Descriptions
Table 19: FT256 Package Pinout (Continued)
FT256
Bank
XC3S250E Pin Name
IO/D5
XC3S500E Pin Name
IO/D5
XC3S1200E Pin Name
IO/D5
Ball
Type
DUAL
DUAL
VREF
VREF
DUAL
DUAL
DUAL
DUAL
I/O
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
T8
IO/M1
IO/M1
IO/M1
T10
P13
R4
P4
P3
N5
P5
T5
IO/VREF_2
IO/VREF_2
IO/VREF_2
IO/VREF_2
IO/VREF_2
IO/VREF_2
IO_L01N_2/INIT_B
IO_L01P_2/CSO_B
IO_L03N_2/MOSI/CSI_B
IO_L03P_2/DOUT/BUSY
IO_L04N_2
IO_L01N_2/INIT_B
IO_L01P_2/CSO_B
IO_L03N_2/MOSI/CSI_B
IO_L03P_2/DOUT/BUSY
IO_L04N_2
IO_L01N_2/INIT_B
IO_L01P_2/CSO_B
IO_L03N_2/MOSI/CSI_B
IO_L03P_2/DOUT/BUSY
IO_L04N_2
IO_L04P_2
IO_L04P_2
IO_L04P_2
T4
I/O
IO_L05N_2
IO_L05N_2
IO_L05N_2
N6
M6
P6
R6
P7
I/O
IO_L05P_2
IO_L05P_2
IO_L05P_2
I/O
IO_L06N_2
IO_L06N_2
IO_L06N_2
I/O
IO_L06P_2
IO_L06P_2
IO_L06P_2
I/O
N.C. (ꢃ)
IO_L07N_2
IO_L07N_2
250E: N.C.
500E: I/O
1200E: I/O
2
N.C. (ꢃ)
IO_L07P_2
IO_L07P_2
N7
250E: N.C.
500E: I/O
1200E: I/O
2
2
2
2
2
2
2
2
2
IO_L09N_2/D6/GCLK13
IO_L09P_2/D7/GCLK12
IO_L10N_2/D3/GCLK15
IO_L10P_2/D4/GCLK14
IO_L12N_2/D1/GCLK3
IO_L12P_2/D2/GCLK2
IO_L13N_2/DIN/D0
IO_L13P_2/M0
IO_L09N_2/D6/GCLK13
IO_L09P_2/D7/GCLK12
IO_L10N_2/D3/GCLK15
IO_L10P_2/D4/GCLK14
IO_L12N_2/D1/GCLK3
IO_L12P_2/D2/GCLK2
IO_L13N_2/DIN/D0
IO_L09N_2/D6/GCLK13
IO_L09P_2/D7/GCLK12
IO_L10N_2/D3/GCLK15
IO_L10P_2/D4/GCLK14
IO_L12N_2/D1/GCLK3
IO_L12P_2/D2/GCLK2
IO_L13N_2/DIN/D0
L8
M8
P8
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL
N8
N9
P9
M9
L9
IO_L13P_2/M0
IO_L13P_2/M0
DUAL
N.C. (ꢃ)
IO_L14N_2/VREF_2
IO_L14N_2/VREF_2
R10
250E: N.C.
500E: VREF
1200E: VREF
2
N.C. (ꢃ)
IO_L14P_2
IO_L14P_2
P10
250E: N.C.
500E: I/O
1200E: I/O
2
2
2
IO_L15N_2
IO_L15N_2
IO_L15N_2
M10
N10
P11
I/O
I/O
IO_L15P_2
IO_L15P_2
IO_L15P_2
IO_L16N_2/A22
IO_L16N_2/A22
IO_L16N_2/A22
DUAL
DS312-4 (v1.1) March 21, 2005
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31
Advance Product Specification
R
Pinout Descriptions
Table 19: FT256 Package Pinout (Continued)
FT256
Ball
Bank
XC3S250E Pin Name
IO_L16P_2/A23
IO_L18N_2/A20
IO_L18P_2/A21
IO_L19N_2/VS1/A18
IO_L19P_2/VS2/A19
IO_L20N_2/CCLK
IO_L20P_2/VS0/A17
IP
XC3S500E Pin Name
IO_L16P_2/A23
IO_L18N_2/A20
IO_L18P_2/A21
IO_L19N_2/VS1/A18
IO_L19P_2/VS2/A19
IO_L20N_2/CCLK
IO_L20P_2/VS0/A17
IP
XC3S1200E Pin Name
IO_L16P_2/A23
IO_L18N_2/A20
IO_L18P_2/A21
IO_L19N_2/VS1/A18
IO_L19P_2/VS2/A19
IO_L20N_2/CCLK
IO_L20P_2/VS0/A17
IP
Type
DUAL
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
R11
N12
P12
R13
T13
R14
P14
T2
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
INPUT
INPUT
INPUT
INPUT
VREF
IP
IP
IP
T14
R3
IP_L02N_2
IP_L02N_2
IP_L02N_2
IP_L02P_2
IP_L02P_2
IP_L02P_2
T3
IP_L08N_2/VREF_2
IP_L08P_2
IP_L08N_2/VREF_2
IP_L08P_2
IP_L08N_2/VREF_2
IP_L08P_2
T7
R7
INPUT
DUAL/GCLK
DUAL/GCLK
IP_L11N_2/M2/GCLK1
IP_L11N_2/M2/GCLK1
IP_L11N_2/M2/GCLK1
R9
IP_L11P_2/RDWR_B/
GCLK0
IP_L11P_2/RDWR_B/
GCLK0
IP_L11P_2/RDWR_B/
GCLK0
T9
2
2
2
2
2
2
3
3
3
3
3
3
3
IP_L17N_2
IP_L17P_2
VCCO_2
IP_L17N_2
IP_L17P_2
VCCO_2
IP_L17N_2
IP_L17P_2
VCCO_2
M11
N11
L7
INPUT
INPUT
VCCO
VCCO
VCCO
VCCO
I/O
VCCO_2
VCCO_2
VCCO_2
L10
R5
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
R12
B2
IO_L01N_3
IO_L01P_3
IO_L02N_3/VREF_3
IO_L02P_3
IO_L03N_3
IO_L03P_3
N.C. (ꢃ)
IO_L01N_3
IO_L01P_3
IO_L02N_3/VREF_3
IO_L02P_3
IO_L03N_3
IO_L03P_3
IO_L04N_3/VREF_3
IO_L01N_3
IO_L01P_3
IO_L02N_3/VREF_3
IO_L02P_3
IO_L03N_3
IO_L03P_3
IO_L04N_3/VREF_3
B1
I/O
C2
VREF
I/O
C1
E4
I/O
E3
I/O
F4
250E: N.C.
500E: VREF
1200E: VREF
3
N.C. (ꢃ)
IO_L04P_3
IO_L04P_3
F3
250E: N.C.
500E: I/O
1200E: I/O
3
3
IO_L05N_3
IO_L05P_3
IO_L05N_3
IO_L05P_3
IO_L05N_3
IO_L05P_3
E1
D1
I/O
I/O
32
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
Table 19: FT256 Package Pinout (Continued)
FT256
Bank
XC3S250E Pin Name
IO_L06N_3
XC3S500E Pin Name
IO_L06N_3
XC3S1200E Pin Name
IO_L06N_3
Ball
G4
G5
G2
G3
H6
H5
H4
Type
I/O
3
3
3
3
3
3
3
IO_L06P_3
IO_L06P_3
IO_L06P_3
I/O
IO_L07N_3
IO_L07N_3
IO_L07N_3
I/O
IO_L07P_3
IO_L07P_3
IO_L07P_3
I/O
IO_L08N_3/LHCLK1
IO_L08P_3/LHCLK0
IO_L08N_3/LHCLK1
IO_L08P_3/LHCLK0
IO_L08N_3/LHCLK1
IO_L08P_3/LHCLK0
LHCLK
LHCLK
LHCLK
IO_L09N_3/LHCLK3/
IRDY2
IO_L09N_3/LHCLK3/
IRDY2
IO_L09N_3/LHCLK3/
IRDY2
3
3
3
IO_L09P_3/LHCLK2
IO_L10N_3/LHCLK5
IO_L09P_3/LHCLK2
IO_L10N_3/LHCLK5
IO_L09P_3/LHCLK2
IO_L10N_3/LHCLK5
H3
J3
J2
LHCLK
LHCLK
LHCLK
IO_L10P_3/LHCLK4/
TRDY2
IO_L10P_3/LHCLK4/
TRDY2
IO_L10P_3/LHCLK4/
TRDY2
3
3
3
3
3
3
3
IO_L11N_3/LHCLK7
IO_L11P_3/LHCLK6
IO_L12N_3
IO_L11N_3/LHCLK7
IO_L11P_3/LHCLK6
IO_L12N_3
IO_L11N_3/LHCLK7
IO_L11P_3/LHCLK6
IO_L12N_3
J4
J5
K1
J1
K3
K2
L2
LHCLK
LHCLK
I/O
IO_L12P_3
IO_L12P_3
IO_L12P_3
I/O
IO_L13N_3
IO_L13N_3
IO_L13N_3
I/O
IO_L13P_3
IO_L13P_3
IO_L13P_3
I/O
N.C. (ꢃ)
IO_L14N_3/VREF_3
IO_L14N_3/VREF_3
250E: N.C.
500E: VREF
1200E: VREF
3
N.C. (ꢃ)
IO_L14P_3
IO_L14P_3
L3
250E: N.C.
500E: I/O
1200E: I/O
3
3
3
3
3
IO_L15N_3
IO_L15P_3
IO_L16N_3
IO_L16P_3
N.C. (ꢃ)
IO_L15N_3
IO_L15P_3
IO_L16N_3
IO_L16P_3
IO_L17N_3
IO_L15N_3
IO_L15P_3
IO_L16N_3
IO_L16P_3
IO_L17N_3
L5
K5
N1
M1
L4
I/O
I/O
I/O
I/O
250E: N.C.
500E: I/O
1200E: I/O
3
N.C. (ꢃ)
IO_L17P_3
IO_L17P_3
M4
250E: N.C.
500E: I/O
1200E: I/O
3
3
3
3
IO_L18N_3
IO_L18P_3
IO_L19N_3
IO_L19P_3
IO_L18N_3
IO_L18P_3
IO_L19N_3
IO_L19P_3
IO_L18N_3
IO_L18P_3
IO_L19N_3
IO_L19P_3
P1
P2
R1
R2
I/O
I/O
I/O
I/O
DS312-4 (v1.1) March 21, 2005
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33
Advance Product Specification
R
Pinout Descriptions
Table 19: FT256 Package Pinout (Continued)
FT256
Ball
Bank
XC3S250E Pin Name
XC3S500E Pin Name
XC3S1200E Pin Name
Type
INPUT
INPUT
3
3
3
IP
IP
IO
IP
IP
IO
IP
IP
IP
D2
F2
F5
250E: I/O
500E: I/O
1200E: INPUT
3
3
3
3
3
3
3
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
H1
J6
INPUT
INPUT
INPUT
INPUT
INPUT
VREF
K4
M3
N3
G1
N2
IP/VREF_3
IO/VREF_3
IP/VREF_3
IO/VREF_3
IP/VREF_3
IP/VREF_3
250E: VREF(I/O)
500E: VREF(I/O)
1200E:
VREF(INPUT)
3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
GND
VCCO_3
VCCO_3
VCCO_3
VCCO_3
GND
VCCO_3
VCCO_3
VCCO_3
VCCO_3
GND
E2
G6
K6
VCCO
VCCO
VCCO
VCCO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
3
3
3
M2
A1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A16
B9
GND
GND
GND
GND
GND
GND
F6
GND
GND
GND
F11
G7
G8
G9
G10
H2
H7
H8
H9
H10
J7
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
J8
GND
GND
GND
J9
34
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
Table 19: FT256 Package Pinout (Continued)
FT256
Bank
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
XC3S250E Pin Name
GND
XC3S500E Pin Name
GND
XC3S1200E Pin Name
GND
Ball
J10
J15
K7
Type
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
K8
GND
GND
GND
K9
GND
GND
GND
K10
L6
GND
GND
GND
GND
GND
GND
L11
R8
GND
GND
GND
GND
GND
GND
T1
GND
GND
GND
T16
T15
D3
GND
VCCAUX DONE
VCCAUX PROG_B
VCCAUX TCK
DONE
PROG_B
TCK
DONE
PROG_B
TCK
CONFIG
CONFIG
JTAG
A15
A2
VCCAUX TDI
TDI
TDI
JTAG
VCCAUX TDO
TDO
TDO
C14
B15
A6
JTAG
VCCAUX TMS
TMS
TMS
JTAG
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
A11
F1
F16
L1
L16
T6
T11
D4
D13
E5
E12
M5
M12
N4
N13
DS312-4 (v1.1) March 21, 2005
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35
Advance Product Specification
R
Pinout Descriptions
The XC3S250E FPGA in the FT256 package has 18 uncon-
nected balls, labeled with an “N.C.” type. These pins are
also indicated with the black diamond (ꢃ) symbol in
Figure 7.
User I/Os by Bank
Table 20, Table 21, and Table 22 indicate how the available
user-I/O pins are distributed between the four I/O banks on
the FT256 package.
Table 20: User I/Os Per Bank on XC3S250E in the FT256 Package
All Possible I/O Pins by Type
Package
Edge
Maximum
I/O
I/O Bank
I/O
20
10
8
INPUT
DUAL
1
VREF
GCLK
Top
0
1
2
3
44
42
10
7
5
4
8
0
Right
21
24
0
Bottom
Left
44
9
3
0
42
24
62
7
3
8
TOTAL
172
33
46
15
16
Table 21: User I/Os Per Bank on XC3S500E in the FT256 Package
All Possible I/O Pins by Type
Package
Edge
Maximum
I/O
I/O Bank
I/O
22
15
11
28
76
INPUT
DUAL
1
VREF
GCLK
Top
0
1
2
3
46
48
10
7
5
5
8
0
Right
21
24
0
Bottom
Left
48
9
4
0
48
7
5
8
TOTAL
190
33
46
19
16
Table 22: User I/Os Per Bank on XC3S1200E in the FT256 Package
All Possible I/O Pins by Type
Package
Edge
Maximum
I/O
I/O Bank
I/O
24
14
13
27
78
INPUT
DUAL
1
VREF
GCLK
Top
0
1
2
3
46
48
8
8
5
5
8
0
Right
21
24
0
Bottom
Left
48
7
4
0
48
8
5
8
TOTAL
190
31
46
19
16
36
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
and the XC3S1200E. The arrows indicate the direction for
easy migration. A double-ended arrow (ꢁꢂ) indicates that
the two pins have identical functionality. A left-facing arrow
(ꢁ) indicates that the pin on the device on the right uncon-
ditionally migrates to the pin on the device on the left. It may
be possible to migrate the opposite direction depending on
the I/O configuration. For example, an I/O pin (Type = I/O)
can migrate to an input-only pin (Type = INPUT) if the I/O
pin is configured as an input.
Footprint Migration Differences
Table 23 summarizes any footprint and functionality differ-
ences between the XC3S250E, the XC3S500E, and the
XC3S1200E FPGAs that may affect easy migration
between devices in the FG256 package. There are 26 such
balls. All other pins not listed in Table 23 unconditionally
migrate between Spartan-3E devices available in the FT256
package.
The XC3S250E is duplicated on both the left and right sides
of the table to show migrations to and from the XC3S500E
Table 23: FT256 Footprint Migration Differences
FT256
Ball
XC3S250E
Type
XC3S500E
Type
XC3S1200E
Type
XC3S250E
Type
Bank
0
Migration
ꢁꢂ
ꢂ
Migration
ꢂ
Migration
ꢁ
B6
B7
INPUT
N.C.
INPUT
I/O
INPUT
N.C.
0
I/O
ꢁꢂ
ꢂ
I/O
ꢁ
B10
C7
0
INPUT
N.C.
ꢁꢂ
ꢂ
INPUT
I/O
I/O
ꢁ
INPUT
N.C.
0
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢁ
I/O
ꢁ
D16
E13
E16
F3
1
VREF(I/O)
N.C.
ꢁ
VREF(INPUT)
I/O
VREF(INPUT)
ꢂ
VREF(I/O)
N.C.
1
ꢂ
I/O
ꢁ
1
N.C.
ꢂ
I/O
I/O
ꢁ
N.C.
3
N.C.
ꢂ
I/O
I/O
ꢁ
N.C.
F4
3
N.C.
ꢂ
VREF
I/O
VREF
INPUT
VREF
I/O
ꢁ
N.C.
F5
3
I/O
ꢁꢂ
ꢂ
ꢂ
I/O
L2
3
N.C.
VREF
I/O
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢂ
ꢁ
N.C.
L3
3
N.C.
ꢂ
ꢁ
N.C.
L4
3
N.C.
ꢂ
I/O
I/O
ꢁ
N.C.
L12
L13
M4
M7
M14
N2
1
N.C.
ꢂ
I/O
I/O
ꢁ
N.C.
1
N.C.
ꢂ
I/O
I/O
ꢁ
N.C.
3
N.C.
ꢂ
I/O
I/O
ꢁ
N.C.
2
INPUT
I/O
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢂ
INPUT
I/O
I/O
ꢁ
INPUT
I/O
1
ꢁ
INPUT
VREF(INPUT)
I/O
ꢂ
3
VREF(I/O)
N.C.
VREF(I/O)
I/O
ꢁ
ꢂ
VREF(I/O)
N.C.
N7
2
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢂ
ꢁ
N14
N15
P7
1
N.C.
ꢂ
I/O
I/O
ꢁ
N.C.
1
N.C.
ꢂ
VREF
I/O
VREF
I/O
ꢁ
N.C.
2
N.C.
ꢂ
ꢁ
N.C.
P10
R10
T12
2
N.C.
ꢂ
I/O
I/O
ꢁ
N.C.
2
N.C.
ꢂ
VREF
INPUT
VREF
I/O
ꢁ
N.C.
2
INPUT
ꢁꢂ
19
ꢁ
INPUT
DIFFERENCES
7
26
Legend:
This pin is identical on both the device on the left and the right.
ꢁꢂ
ꢂ
This pin can unconditionally migrate from the device on the left to the device on the right. Migration in the other direction may be possible
depending on how the pin is configured for the device on the right.
This pin can unconditionally migrate from the device on the right to the device on the left. Migration in the other direction may be possible
depending on how the pin is configured for the device on the left.
ꢁ
DS312-4 (v1.1) March 21, 2005
www.xilinx.com
37
Advance Product Specification
R
Pinout Descriptions
FT256 Footprint
Bank 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
I/O
L17N_0
VREF_0
INPUT
L10P_0
GCLK8
I/O
L09N_0
GCLK7
I/O
L09P_0
GCLK6
I/O
L03N_0
VREF_0
I/O
L17P_0
I/O
L01N_0
VCCAUX
VCCAUX
GND
TDI
INPUT
I/O
I/O
TCK
GND
A
B
C
D
E
F
I/O
L13P_0
I/O
L19N_0
HSWAP
INPUT
L10N_0
GCLK9
I/O
L05N_0
VREF_0
INPUT
ꢁꢂ
INPUT
ꢁꢂ
I/O
L01P_3
I/O
L01N_3
I/O
L03P_0
I/O
L01P_0
VCCO_0
VCCO_0
I/O
GND
TMS
INPUT
ꢃ
I/O
L13N_0
I/O
L02N_3
VREF_3
I/O
L11P_0
GCLK10
I/O
L19N_1
LDC2
I/O
L19P_1
LDC1
I/O
L02P_3
I/O
L19P_0
I/O
L18N_0
I/O
L18P_0
I/O
L15P_0
INPUT INPUT
I/O
L05P_0
INPUT
L02N_0
INPUT
TDO
L07N_0
L07P_0
ꢃ
INPUT
VREF_1
I/O
L14N_0
VREF_0 GCLK11
I/O
L11N_0
I/O
L18N_1
LDC0
I/O
L18P_1
HDC
I/O
L05P_3
INPUT
L16P_0
I/O
L15N_0
I/O
VREF_0
I/O
L06P_0
I/O
L04P_0
INPUT
L02P_0
PROG_B
INPUT
VCCINT
VCCINT
ꢁꢂ
I/O
L17P_1
I/O
L17N_1
I/O
L08P_0
GCLK4
I/O
L05N_3
I/O
L03P_3
I/O
L03N_3
INPUT
L16N_0
I/O
L14P_0
I/O
L12P_0
I/O
L06N_0
I/O
L04N_0
VCCO_3
VCCO_1
VCCINT
VCCINT
INPUT
ꢃ
ꢃ
I/O
L04N_3
VREF_3
ꢃ
I/O
L04P_3
I/O
L08N_0
GCLK5
INPUT
ꢁꢂ
I/O
L12N_0
I/O
L16N_1
I/O
L16P_1
I/O
L15P_1
I/O
L15N_1
VCCAUX
VCCO_0
GND
VCCO_0
GND
VCCAUX
INPUT
I/O
GND
GND
ꢃ
I/O
L14N_1
A0
I/O
L13P_1
A2
I/O
L13N_1
A1
INPUT
VREF_3 L07N_3
I/O
L07P_3
I/O
L06N_3
I/O
L06P_3
I/O
L14P_1
VCCO_3
VCCO_1
GND
GND
GND
GND
GND
GND
GND
INPUT
I/O
L12P_1
A4
G
H
J
I/O
L11P_1
A6
I/O
L09N_3
LHCLK3
IRDY2
I/O
I/O
I/O
L09P_3
LHCLK2
I/O
L08P_3
I/O
L08N_3
LHCLK0 LHCLK1
INPUT
VREF_1
L12N_1
A3
L11N_1
A5
INPUT
GND
I/O
L10P_3
LHCLK4
TRDY2
GND
GND
INPUT
I/O
L09N_1
A9
RHCLK1
RHCLK4
IRDY1
RHCLK7 RHCLK6
RHCLK5
I/O
I/O
I/O
L10N_3
I/O
L11N_3
I/O
L11P_3
L10N_1
I/O
L12P_3
L10P_1
A8
INPUT
VCCO_3
GND
GND
GND
INPUT INPUT
GND
A7
RHCLK3
LHCLK5 LHCLK7 LHCLK6
RHCLK2
TRDY1
I/O
I/O
I/O
L07P_1
A12
I/O
L08N_1
VREF_1
I/O
L12N_3
I/O
L13P_3
I/O
L13N_3
I/O
L15P_3
I/O
L08P_1
L09P_1
A10
VCCO_1
L07N_1
INPUT
GND
GND
I/O
L09N_2
D6
GCLK13
GND
K
L
A11
RHCLK0
I/O
L14N_3
VREF_3
ꢃ
I/O
L14P_3
I/O
L17N_3
I/O
L05P_1
I/O
L05N_1
I/O
L13P_2
M0
I/O
L15N_3
I/O
L06P_1
I/O
L06N_1
VCCAUX
VCCO_2
VCCO_2
VCCAUX
GND
ꢃ
ꢃ
ꢃ
ꢃ
I/O
I/O
I/O
I/O
L04N_1
VREF_1
INPUT
ꢁꢂ
INPUT
ꢁꢂ
I/O
L16P_3
I/O
L05P_2
I/O
L15N_2
INPUT
L17N_2
L09P_2
D7
L13N_2
DIN
VCCO_3
VCCO_1
INPUT L17P_3 VCCINT
VCCINT INPUT
M
N
P
R
T
ꢃ
GCLK12
D0
I/O
INPUT
VREF_3
I/O
L07P_2
I/O
L03P_1
I/O
I/O
I/O
I/O
L18N_2
A20
I/O
L16N_3
I/O
L05N_2
I/O
L15P_2
INPUT
L17P_2
I/O
L04P_1
L03N_1
VREF_1
L03N_2
L10P_2
D4
L12N_2
D1
INPUT VCCINT
VCCINT
MOSI
CSI_B
ꢁꢂ
ꢃ
ꢃ
GCLK14
GCLK3
ꢃ
I/O
L07N_2
I/O
L14P_2
I/O
L03P_2
DOUT
BUSY
I/O
I/O
I/O
I/O
L01P_2
I/O
L01N_2
I/O
L16N_2
A22
I/O
L18P_2
A21
I/O
L02N_1
A13
I/O
L02P_1
A14
I/O
L18N_3
I/O
L18P_3
I/O
L06N_2
I/O
VREF_2
L10N_2
D3
L12P_2
D2
L20P_2
VS0
CSO_B
INIT_B
ꢃ
ꢃ
GCLK15
GCLK2
A17
I/O
L14N_2
VREF_2
ꢃ
INPUT
I/O
I/O
L16P_2
A23
I/O
L20N_2
CCLK
I/O
L01N_1
A15
I/O
L01P_1
A16
I/O
L19N_3
I/O
L19P_3
INPUT
I/O
I/O
L06P_2
INPUT
L08P_2
L11N_2
M2
L19N_2
VS1
VCCO_2
VCCO_2
GND
L02N_2 VREF_2
GCLK1
A18
INPUT
L11P_2
RDWR_B
GCLK0
I/O
INPUT
L08N_2
VREF_2
INPUT
ꢁꢂ
INPUT
L02P_2
I/O
L04P_2
I/O
L04N_2
I/O
D5
I/O
M1
L19P_2
VS2
VCCAUX
VCCAUX
GND
INPUT
INPUT DONE
GND
A19
Bank 2
DS312-4_05_021705
Figure 7: FT256 Package Footprint (top view)
JTAG: Dedicated JTAG port
CONFIG: Dedicated
configuration pins
VCCINT: Internal core supply
voltage (+1.2V)
2
4
8
pins
GND: Ground
VCCO: Output voltage supply
for bank
VCCAUX: Auxiliary supply
voltage (+2.5V)
28
16
8
Migration Difference: For
flexible package migration,
use these pins as inputs.
Unconnected pins on
XC3S250E
6
18
ꢁꢂ
ꢃ
38
www.xilinx.com
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
If the table row is highlighted in tan, then this is an instance
where an unconnected pin on the XC3S500E FPGA maps
to a VREF pin on the XC3S1200E and XC3S1600E FPGA.
If the FPGA application uses an I/O standard that requires a
VREF voltage reference, connect the highlighted pin to the
VREF voltage supply, even though this does not actually
connect to the XC3S500E FPGA. This VREF connection on
the board allows future migration to the larger devices with-
out modifying the printed-circuit board.
FG320: 320-ball Fine-pitch Ball Grid
Array
The 320-lead fine-pitch ball grid array package, FG320,
supports three different Spartan-3E FPGAs, including the
XC3S500E, the XC3S1200E, and the XC3S1600E, as
shown in Table 24 and Figure 8.
The FG320 package is an 18 x 18 array of solder balls
minus the four center balls.
All other balls have nearly identical functionality on all three
devices. Table 23 summarizes the Spartan-3E footprint
migration differences for the FG320 package.
Table 24 lists all the package pins. They are sorted by bank
number and then by pin name of the largest device. Pins
that form a differential I/O pair appear together in the table.
The table also shows the pin number for each pin and the
pin type, as defined earlier.
An electronic version of this package pinout table and foot-
print diagram is available for download from the Xilinx web
site at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip.
The highlighted rows indicate pinout differences between
the XC3S500E, the XC3S1200E, and the XC3S1600E
FPGAs. The XC3S500E has 18 unconnected balls, indi-
cated as N.C. (No Connection) in Table 24 and with the
black diamond character (ꢃ) in both Table 24 and in
Figure 8.
Pinout Table
Table 24: FG320 Package Pinout
FG320
Bank
XC3S500E Pin Name
XC3S1200E Pin Name
XC3S1600E Pin Name
Ball
Type
0
IP
IO
IO
A7
500E: INPUT
1200E: I/O
1600E: I/O
0
0
0
0
IO
IO
IO
IP
IO
IO
IO
IO
IO
IO
IO
IO
A8
A11
C4
I/O
I/O
I/O
D13
500E: INPUT
1200E: I/O
1600E: I/O
0
0
0
0
0
0
0
0
0
0
0
0
0
IO
IO
IO
IO
IO
IO
E13
G9
I/O
I/O
IO/VREF_0
IO/VREF_0
IO/VREF_0
B11
A16
B16
C14
D14
A14
B14
B13
A13
E12
F12
VREF
I/O
IO_L01N_0
IO_L01N_0
IO_L01N_0
IO_L01P_0
IO_L01P_0
IO_L01P_0
I/O
IO_L03N_0/VREF_0
IO_L03P_0
IO_L03N_0/VREF_0
IO_L03P_0
IO_L03N_0/VREF_0
IO_L03P_0
VREF
I/O
IO_L04N_0
IO_L04N_0
IO_L04N_0
I/O
IO_L04P_0
IO_L04P_0
IO_L04P_0
I/O
IO_L05N_0/VREF_0
IO_L05P_0
IO_L05N_0/VREF_0
IO_L05P_0
IO_L05N_0/VREF_0
IO_L05P_0
VREF
I/O
IO_L06N_0
IO_L06N_0
IO_L06N_0
I/O
IO_L06P_0
IO_L06P_0
IO_L06P_0
I/O
DS312-4 (v1.1) March 21, 2005
www.xilinx.com
39
Advance Product Specification
R
Pinout Descriptions
Table 24: FG320 Package Pinout (Continued)
FG320
Ball
Bank
0
XC3S500E Pin Name
IO_L08N_0
XC3S1200E Pin Name
IO_L08N_0
XC3S1600E Pin Name
IO_L08N_0
Type
I/O
F11
E11
D11
C11
E10
D10
A10
B10
D9
0
IO_L08P_0
IO_L08P_0
IO_L08P_0
I/O
0
IO_L09N_0
IO_L09N_0
IO_L09N_0
I/O
0
IO_L09P_0
IO_L09P_0
IO_L09P_0
I/O
0
IO_L11N_0/GCLK5
IO_L11P_0/GCLK4
IO_L12N_0/GCLK7
IO_L12P_0/GCLK6
IO_L14N_0/GCLK11
IO_L14P_0/GCLK10
IO_L15N_0
IO_L11N_0/GCLK5
IO_L11P_0/GCLK4
IO_L12N_0/GCLK7
IO_L12P_0/GCLK6
IO_L14N_0/GCLK11
IO_L14P_0/GCLK10
IO_L15N_0
IO_L11N_0/GCLK5
IO_L11P_0/GCLK4
IO_L12N_0/GCLK7
IO_L12P_0/GCLK6
IO_L14N_0/GCLK11
IO_L14P_0/GCLK10
IO_L15N_0
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
I/O
0
0
0
0
0
C9
0
F9
0
IO_L15P_0
IO_L15P_0
IO_L15P_0
E9
I/O
0
IO_L17N_0
IO_L17N_0
IO_L17N_0
F8
I/O
0
IO_L17P_0
IO_L17P_0
IO_L17P_0
E8
I/O
0
IO_L18N_0/VREF_0
IO_L18P_0
IO_L18N_0/VREF_0
IO_L18P_0
IO_L18N_0/VREF_0
IO_L18P_0
D7
VREF
I/O
0
C7
0
IO_L19N_0/VREF_0
IO_L19P_0
IO_L19N_0/VREF_0
IO_L19P_0
IO_L19N_0/VREF_0
IO_L19P_0
E7
VREF
I/O
0
F7
0
IO_L20N_0
IO_L20N_0
IO_L20N_0
A6
I/O
0
IO_L20P_0
IO_L20P_0
IO_L20P_0
B6
I/O
0
N.C. (ꢃ)
IO_L21N_0
IO_L21N_0
E6
500E: N.C.
1200E: I/O
1600E: I/O
0
N.C. (ꢃ)
IO_L21P_0
IO_L21P_0
D6
500E: N.C.
1200E: I/O
1600E: I/O
0
0
0
0
0
0
0
0
IO_L23N_0/VREF_0
IO_L23P_0
IO_L24N_0
IO_L24P_0
IO_L25N_0/HSWAP
IO_L25P_0
IP
IO_L23N_0/VREF_0
IO_L23P_0
IO_L24N_0
IO_L24P_0
IO_L25N_0/HSWAP
IO_L25P_0
IP
IO_L23N_0/VREF_0
IO_L23P_0
IO_L24N_0
IO_L24P_0
IO_L25N_0/HSWAP
IO_L25P_0
IP
D5
C5
B4
VREF
I/O
I/O
A4
I/O
B3
DUAL
I/O
C3
A3
INPUT
N.C. (ꢃ)
IO
IP
A12
500E: N.C.
1200E: I/O
1600E: INPUT
40
www.xilinx.com
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
Table 24: FG320 Package Pinout (Continued)
FG320
Bank
0
XC3S500E Pin Name
XC3S1200E Pin Name
XC3S1600E Pin Name
Ball
C15
A15
B15
D12
C12
G10
F10
B9
Type
IP
IP
IP
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
GCLK
GCLK
INPUT
INPUT
INPUT
INPUT
VCCO
VCCO
VCCO
VCCO
VCCO
0
IP_L02N_0
IP_L02P_0
IP_L07N_0
IP_L07P_0
IP_L10N_0
IP_L10P_0
IP_L13N_0/GCLK9
IP_L13P_0/GCLK8
IP_L16N_0
IP_L16P_0
IP_L22N_0
IP_L22P_0
VCCO_0
IP_L02N_0
IP_L02P_0
IP_L07N_0
IP_L07P_0
IP_L10N_0
IP_L10P_0
IP_L13N_0/GCLK9
IP_L13P_0/GCLK8
IP_L16N_0
IP_L16P_0
IP_L22N_0
IP_L22P_0
VCCO_0
IP_L02N_0
IP_L02P_0
IP_L07N_0
IP_L07P_0
IP_L10N_0
IP_L10P_0
IP_L13N_0/GCLK9
IP_L13P_0/GCLK8
IP_L16N_0
IP_L16P_0
IP_L22N_0
IP_L22P_0
VCCO_0
0
0
0
0
0
0
0
B8
0
D8
0
C8
0
B5
0
A5
0
A9
0
VCCO_0
VCCO_0
VCCO_0
C6
0
VCCO_0
VCCO_0
VCCO_0
C13
G8
0
VCCO_0
VCCO_0
VCCO_0
0
VCCO_0
VCCO_0
VCCO_0
G11
P16
1
N.C. (ꢃ)
IO
IO
500E: N.C.
1200E: I/O
1600E: I/O
1
1
1
1
1
1
1
IO_L01N_1/A15
IO_L01P_1/A16
IO_L02N_1/A13
IO_L02P_1/A14
IO_L03N_1/VREF_1
IO_L03P_1
IO_L01N_1/A15
IO_L01P_1/A16
IO_L02N_1/A13
IO_L02P_1/A14
IO_L03N_1/VREF_1
IO_L03P_1
IO_L01N_1/A15
IO_L01P_1/A16
IO_L02N_1/A13
IO_L02P_1/A14
IO_L03N_1/VREF_1
IO_L03P_1
T17
U18
T18
R18
R16
R15
N14
DUAL
DUAL
DUAL
DUAL
VREF
I/O
N.C. (ꢃ)
IO_L04N_1
IO_L04N_1
500E: N.C.
1200E: I/O
1600E: INPUT
1
N.C. (ꢃ)
IO_L04P_1
IO_L04P_1
N15
500E: N.C.
1200E: I/O
1600E: INPUT
1
1
1
IO_L05N_1/VREF_1
IO_L05P_1
IO_L05N_1/VREF_1
IO_L05P_1
IO_L05N_1/VREF_1
IO_L05P_1
M13
M14
P18
VREF
I/O
IO_L06N_1
IO_L06N_1
IO_L06N_1
I/O
DS312-4 (v1.1) March 21, 2005
www.xilinx.com
41
Advance Product Specification
R
Pinout Descriptions
Table 24: FG320 Package Pinout (Continued)
FG320
Ball
Bank
XC3S500E Pin Name
IO_L06P_1
XC3S1200E Pin Name
IO_L06P_1
XC3S1600E Pin Name
IO_L06P_1
Type
1
1
1
1
1
1
1
1
1
1
1
1
P17
M16
M15
M18
N18
L15
L16
L17
L18
K12
K13
K14
I/O
I/O
IO_L07N_1
IO_L07N_1
IO_L07N_1
IO_L07P_1
IO_L07P_1
IO_L07P_1
I/O
IO_L08N_1
IO_L08N_1
IO_L08N_1
I/O
IO_L08P_1
IO_L08P_1
IO_L08P_1
I/O
IO_L09N_1/A11
IO_L09P_1/A12
IO_L10N_1/VREF_1
IO_L10P_1
IO_L09N_1/A11
IO_L09P_1/A12
IO_L10N_1/VREF_1
IO_L10P_1
IO_L09N_1/A11
IO_L09P_1/A12
IO_L10N_1/VREF_1
IO_L10P_1
DUAL
DUAL
VREF
I/O
IO_L11N_1/A9/RHCLK1
IO_L11P_1/A10/RHCLK0
IO_L11N_1/A9/RHCLK1
IO_L11P_1/A10/RHCLK0
IO_L11N_1/A9/RHCLK1
IO_L11P_1/A10/RHCLK0
RHCLK/DUAL
RHCLK/DUAL
RHCLK/DUAL
IO_L12N_1/A7/RHCLK3/
TRDY1
IO_L12N_1/A7/RHCLK3/
TRDY1
IO_L12N_1/A7/RHCLK3/
TRDY1
1
1
1
IO_L12P_1/A8/RHCLK2
IO_L13N_1/A5/RHCLK5
IO_L12P_1/A8/RHCLK2
IO_L13N_1/A5/RHCLK5
IO_L12P_1/A8/RHCLK2
IO_L13N_1/A5/RHCLK5
K15
J16
J17
RHCLK/DUAL
RHCLK/DUAL
RHCLK/DUAL
IO_L13P_1/A6/RHCLK4/
IRDY1
IO_L13P_1/A6/RHCLK4/
IRDY1
IO_L13P_1/A6/RHCLK4/
IRDY1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IO_L14N_1/A3/RHCLK7
IO_L14P_1/A4/RHCLK6
IO_L15N_1/A1
IO_L15P_1/A2
IO_L16N_1/A0
IO_L16P_1
IO_L14N_1/A3/RHCLK7
IO_L14P_1/A4/RHCLK6
IO_L15N_1/A1
IO_L15P_1/A2
IO_L16N_1/A0
IO_L16P_1
IO_L14N_1/A3/RHCLK7
IO_L14P_1/A4/RHCLK6
IO_L15N_1/A1
IO_L15P_1/A2
IO_L16N_1/A0
IO_L16P_1
J14
J15
J13
J12
H17
H16
H15
H14
G16
G15
F17
F18
G13
G14
F14
F15
E16
RHCLK/DUAL
RHCLK/DUAL
DUAL
DUAL
DUAL
I/O
IO_L17N_1
IO_L17N_1
IO_L17N_1
I/O
IO_L17P_1
IO_L17P_1
IO_L17P_1
I/O
IO_L18N_1
IO_L18N_1
IO_L18N_1
I/O
IO_L18P_1
IO_L18P_1
IO_L18P_1
I/O
IO_L19N_1
IO_L19N_1
IO_L19N_1
I/O
IO_L19P_1
IO_L19P_1
IO_L19P_1
I/O
IO_L20N_1
IO_L20N_1
IO_L20N_1
I/O
IO_L20P_1
IO_L20P_1
IO_L20P_1
I/O
IO_L21N_1
IO_L21N_1
IO_L21N_1
I/O
IO_L21P_1
IO_L21P_1
IO_L21P_1
I/O
N.C. (ꢃ)
IO_L22N_1
IO_L22N_1
500E: N.C.
1200E: I/O
1600E: I/O
42
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
Table 24: FG320 Package Pinout (Continued)
FG320
Bank
XC3S500E Pin Name
N.C. (ꢃ)
XC3S1200E Pin Name
XC3S1600E Pin Name
Ball
Type
1
IO_L22P_1
IO_L22P_1
E15
500E: N.C.
1200E: I/O
1600E: I/O
1
1
1
1
1
1
IO_L23N_1/LDC0
IO_L23P_1/HDC
IO_L24N_1/LDC2
IO_L24P_1/LDC1
IP
IO_L23N_1/LDC0
IO_L23P_1/HDC
IO_L24N_1/LDC2
IO_L24P_1/LDC1
IP
IO_L23N_1/LDC0
IO_L23P_1/HDC
IO_L24N_1/LDC2
IO_L24P_1/LDC1
IP
D16
D17
C17
C18
B18
E17
DUAL
DUAL
DUAL
DUAL
INPUT
IO
IP
IP
500E: I/O
1200E: INPUT
1600E: INPUT
1
1
1
1
1
1
1
1
1
IP
IP
IP
IP
IP
IP
IP
IP
IO
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
E18
G18
H13
K17
K18
L13
L14
N17
P15
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
500E: I/O
1200E: INPUT
1600E: INPUT
1
1
1
1
1
1
1
1
2
2
2
IP
IP
IP
R17
D18
H18
F16
H12
J18
L12
N16
P9
INPUT
VREF
VREF
VCCO
VCCO
VCCO
VCCO
VCCO
I/O
IP/VREF_1
IP/VREF_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
IO
IP/VREF_1
IP/VREF_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
IO
IP/VREF_1
IP/VREF_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
IO
IO
IO
IO
R11
U6
I/O
IP
IO
IO
500E: INPUT
1200E: I/O
1600E: I/O
DS312-4 (v1.1) March 21, 2005
www.xilinx.com
43
Advance Product Specification
R
Pinout Descriptions
Table 24: FG320 Package Pinout (Continued)
FG320
Ball
Bank
XC3S500E Pin Name
XC3S1200E Pin Name
XC3S1600E Pin Name
Type
2
IP
IO
IO
IO
IO
U13
500E: INPUT
1200E: I/O
1600E: I/O
2
N.C. (ꢃ)
V7
500E: N.C.
1200E: I/O
1600E: I/O
2
2
2
2
2
2
2
2
2
2
2
2
2
IO/D5
IO/D5
IO/D5
R9
V11
T15
U5
T3
DUAL
DUAL
VREF
VREF
DUAL
DUAL
DUAL
DUAL
I/O
IO/M1
IO/M1
IO/M1
IO/VREF_2
IO/VREF_2
IO/VREF_2
IO/VREF_2
IO/VREF_2
IO/VREF_2
IO_L01N_2/INIT_B
IO_L01P_2/CSO_B
IO_L03N_2/MOSI/CSI_B
IO_L03P_2/DOUT/BUSY
IO_L04N_2
IO_L01N_2/INIT_B
IO_L01P_2/CSO_B
IO_L03N_2/MOSI/CSI_B
IO_L03P_2/DOUT/BUSY
IO_L04N_2
IO_L01N_2/INIT_B
IO_L01P_2/CSO_B
IO_L03N_2/MOSI/CSI_B
IO_L03P_2/DOUT/BUSY
IO_L04N_2
U3
T4
U4
T5
IO_L04P_2
IO_L04P_2
IO_L04P_2
R5
P6
I/O
IO_L05N_2
IO_L05N_2
IO_L05N_2
I/O
IO_L05P_2
IO_L05P_2
IO_L05P_2
R6
V6
I/O
N.C. (ꢃ)
IO_L06N_2/VREF_2
IO_L06N_2/VREF_2
500E: N.C.
1200E: VREF
1600E: VREF
2
N.C. (ꢃ)
IO_L06P_2
IO_L06P_2
V5
500E: N.C.
1200E: I/O
1600E: I/O
2
2
2
2
2
2
2
2
2
2
2
2
2
IO_L07N_2
IO_L07N_2
IO_L07N_2
P7
N7
N8
P8
I/O
I/O
IO_L07P_2
IO_L07P_2
IO_L07P_2
IO_L09N_2
IO_L09N_2
IO_L09N_2
I/O
IO_L09P_2
IO_L09P_2
IO_L09P_2
I/O
IO_L10N_2
IO_L10N_2
IO_L10N_2
T8
I/O
IO_L10P_2
IO_L10P_2
IO_L10P_2
R8
M9
N9
V9
I/O
IO_L12N_2/D6/GCLK13
IO_L12P_2/D7/GCLK12
IO_L13N_2/D3/GCLK15
IO_L13P_2/D4/GCLK14
IO_L15N_2/D1/GCLK3
IO_L15P_2/D2/GCLK2
IO_L16N_2/DIN/D0
IO_L12N_2/D6/GCLK13
IO_L12P_2/D7/GCLK12
IO_L13N_2/D3/GCLK15
IO_L13P_2/D4/GCLK14
IO_L15N_2/D1/GCLK3
IO_L15P_2/D2/GCLK2
IO_L16N_2/DIN/D0
IO_L12N_2/D6/GCLK13
IO_L12P_2/D7/GCLK12
IO_L13N_2/D3/GCLK15
IO_L13P_2/D4/GCLK14
IO_L15N_2/D1/GCLK3
IO_L15P_2/D2/GCLK2
IO_L16N_2/DIN/D0
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL
U9
P10
R10
N10
44
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
Table 24: FG320 Package Pinout (Continued)
FG320
Bank
XC3S500E Pin Name
IO_L16P_2/M0
XC3S1200E Pin Name
IO_L16P_2/M0
IO_L18N_2
XC3S1600E Pin Name
IO_L16P_2/M0
IO_L18N_2
Ball
M10
N11
P11
V13
V12
R12
T12
P12
Type
DUAL
I/O
2
2
2
2
2
2
2
2
IO_L18N_2
IO_L18P_2
IO_L19N_2/VREF_2
IO_L19P_2
IO_L20N_2
IO_L20P_2
N.C. (ꢃ)
IO_L18P_2
IO_L18P_2
I/O
IO_L19N_2/VREF_2
IO_L19P_2
IO_L19N_2/VREF_2
IO_L19P_2
VREF
I/O
IO_L20N_2
IO_L20N_2
I/O
IO_L20P_2
IO_L20P_2
I/O
IO_L21N_2
IO_L21N_2
500E: N.C.
1200E: I/O
1600E: I/O
2
N.C. (ꢃ)
IO_L21P_2
IO_L21P_2
N12
500E: N.C.
1200E: I/O
1600E: I/O
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO_L22N_2/A22
IO_L22P_2/A23
IO_L24N_2/A20
IO_L24P_2/A21
IO_L25N_2/VS1/A18
IO_L25P_2/VS2/A19
IO_L26N_2/CCLK
IO_L26P_2/VS0/A17
IP
IO_L22N_2/A22
IO_L22P_2/A23
IO_L24N_2/A20
IO_L24P_2/A21
IO_L25N_2/VS1/A18
IO_L25P_2/VS2/A19
IO_L26N_2/CCLK
IO_L26P_2/VS0/A17
IP
IO_L22N_2/A22
IO_L22P_2/A23
IO_L24N_2/A20
IO_L24P_2/A21
IO_L25N_2/VS1/A18
IO_L25P_2/VS2/A19
IO_L26N_2/CCLK
IO_L26P_2/VS0/A17
IP
R13
P13
R14
T14
U15
V15
U16
T16
V2
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VREF
IP
IP
IP
V16
V3
IP_L02N_2
IP_L02N_2
IP_L02N_2
IP_L02P_2
IP_L02P_2
IP_L02P_2
V4
IP_L08N_2
IP_L08N_2
IP_L08N_2
R7
IP_L08P_2
IP_L08P_2
IP_L08P_2
T7
IP_L11N_2/VREF_2
IP_L11P_2
IP_L11N_2/VREF_2
IP_L11P_2
IP_L11N_2/VREF_2
IP_L11P_2
V8
U8
INPUT
DUAL/GCLK
DUAL/GCLK
IP_L14N_2/M2/GCLK1
IP_L14N_2/M2/GCLK1
IP_L14N_2/M2/GCLK1
T10
U10
IP_L14P_2/RDWR_B/
GCLK0
IP_L14P_2/RDWR_B/
GCLK0
IP_L14P_2/RDWR_B/
GCLK0
2
2
2
2
IP_L17N_2
IP_L17P_2
IP_L23N_2
IP_L23P_2
IP_L17N_2
IP_L17P_2
IP_L23N_2
IP_L23P_2
IP_L17N_2
IP_L17P_2
IP_L23N_2
IP_L23P_2
U11
T11
U14
V14
INPUT
INPUT
INPUT
INPUT
DS312-4 (v1.1) March 21, 2005
www.xilinx.com
45
Advance Product Specification
R
Pinout Descriptions
Table 24: FG320 Package Pinout (Continued)
FG320
Ball
Bank
XC3S500E Pin Name
VCCO_2
XC3S1200E Pin Name
VCCO_2
XC3S1600E Pin Name
VCCO_2
Type
2
2
2
2
2
3
M8
M11
T6
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO_2
VCCO_2
VCCO_2
VCCO_2
N.C. (ꢃ)
VCCO_2
VCCO_2
VCCO_2
VCCO_2
IO
VCCO_2
VCCO_2
VCCO_2
VCCO_2
IO
T13
V10
D4
500E: N.C.
1200E: I/O
1600E: I/O
3
3
3
3
3
3
3
IO_L01N_3
IO_L01P_3
IO_L02N_3/VREF_3
IO_L02P_3
IO_L03N_3
IO_L03P_3
N.C. (ꢃ)
IO_L01N_3
IO_L01N_3
C2
C1
D2
D1
E1
E2
E3
I/O
I/O
IO_L01P_3
IO_L01P_3
IO_L02N_3/VREF_3
IO_L02P_3
IO_L02N_3/VREF_3
IO_L02P_3
VREF
I/O
IO_L03N_3
IO_L03N_3
I/O
IO_L03P_3
IO_L03P_3
I/O
IO_L04N_3
IO_L04N_3
500E: N.C.
1200E: I/O
1600E: I/O
3
N.C. (ꢃ)
IO_L04P_3
IO_L04P_3
E4
500E: N.C.
1200E: I/O
1600E: I/O
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO_L05N_3
IO_L05N_3
IO_L05N_3
F2
F1
G4
G3
G5
G6
H5
H6
H3
H4
H1
H2
J4
I/O
I/O
IO_L05P_3
IO_L05P_3
IO_L05P_3
IO_L06N_3/VREF_3
IO_L06P_3
IO_L06N_3/VREF_3
IO_L06P_3
IO_L06N_3/VREF_3
IO_L06P_3
VREF
I/O
IO_L07N_3
IO_L07N_3
IO_L07N_3
I/O
IO_L07P_3
IO_L07P_3
IO_L07P_3
I/O
IO_L08N_3
IO_L08N_3
IO_L08N_3
I/O
IO_L08P_3
IO_L08P_3
IO_L08P_3
I/O
IO_L09N_3
IO_L09N_3
IO_L09N_3
I/O
IO_L09P_3
IO_L09P_3
IO_L09P_3
I/O
IO_L10N_3
IO_L10N_3
IO_L10N_3
I/O
IO_L10P_3
IO_L10P_3
IO_L10P_3
I/O
IO_L11N_3/LHCLK1
IO_L11P_3/LHCLK0
IO_L11N_3/LHCLK1
IO_L11P_3/LHCLK0
IO_L11N_3/LHCLK1
IO_L11P_3/LHCLK0
LHCLK
LHCLK
LHCLK
J5
IO_L12N_3/LHCLK3/
IRDY2
IO_L12N_3/LHCLK3/
IRDY2
IO_L12N_3/LHCLK3/
IRDY2
J2
3
IO_L12P_3/LHCLK2
IO_L12P_3/LHCLK2
IO_L12P_3/LHCLK2
J1
LHCLK
46
www.xilinx.com
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
Table 24: FG320 Package Pinout (Continued)
FG320
Bank
XC3S500E Pin Name
XC3S1200E Pin Name
XC3S1600E Pin Name
Ball
Type
3
3
IO_L13N_3/LHCLK5
IO_L13N_3/LHCLK5
IO_L13N_3/LHCLK5
K4
LHCLK
LHCLK
IO_L13P_3/LHCLK4/
TRDY2
IO_L13P_3/LHCLK4/
TRDY2
IO_L13P_3/LHCLK4/
TRDY2
K3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO_L14N_3/LHCLK7
IO_L14P_3/LHCLK6
IO_L15N_3
IO_L14N_3/LHCLK7
IO_L14P_3/LHCLK6
IO_L15N_3
IO_L14N_3/LHCLK7
IO_L14P_3/LHCLK6
IO_L15N_3
K5
K6
L2
LHCLK
LHCLK
I/O
IO_L15P_3
IO_L15P_3
IO_L15P_3
L1
I/O
IO_L16N_3
IO_L16N_3
IO_L16N_3
L4
I/O
IO_L16P_3
IO_L16P_3
IO_L16P_3
L3
I/O
IO_L17N_3/VREF_3
IO_L17P_3
IO_L17N_3/VREF_3
IO_L17P_3
IO_L17N_3/VREF_3
IO_L17P_3
L5
VREF
I/O
L6
IO_L18N_3
IO_L18N_3
IO_L18N_3
M3
M4
M6
M5
N5
N4
P1
P2
P4
I/O
IO_L18P_3
IO_L18P_3
IO_L18P_3
I/O
IO_L19N_3
IO_L19N_3
IO_L19N_3
I/O
IO_L19P_3
IO_L19P_3
IO_L19P_3
I/O
IO_L20N_3
IO_L20N_3
IO_L20N_3
I/O
IO_L20P_3
IO_L20P_3
IO_L20P_3
I/O
IO_L21N_3
IO_L21N_3
IO_L21N_3
I/O
IO_L21P_3
IO_L21P_3
IO_L21P_3
I/O
N.C. (ꢃ)
IO_L22N_3
IO_L22N_3
500E: N.C.
1200E: I/O
1600E: I/O
3
N.C. (ꢃ)
IO_L22P_3
IO_L22P_3
P3
500E: N.C.
1200E: I/O
1600E: I/O
3
3
3
3
3
3
IO_L23N_3
IO_L23P_3
IO_L24N_3
IO_L24P_3
IP
IO_L23N_3
IO_L23P_3
IO_L24N_3
IO_L24P_3
IP
IO_L23N_3
IO_L23P_3
IO_L24N_3
IO_L24P_3
IP
R2
R3
T1
T2
D3
F4
I/O
I/O
I/O
I/O
INPUT
IO
IP
IP
500E: I/O
1200E: INPUT
1600E: INPUT
3
3
3
3
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
F5
G1
J7
INPUT
INPUT
INPUT
INPUT
K2
DS312-4 (v1.1) March 21, 2005
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47
Advance Product Specification
R
Pinout Descriptions
Table 24: FG320 Package Pinout (Continued)
FG320
Ball
Bank
XC3S500E Pin Name
XC3S1200E Pin Name
XC3S1600E Pin Name
Type
INPUT
3
3
3
3
3
3
3
3
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
K7
M1
N1
N2
R1
U1
J6
INPUT
INPUT
INPUT
INPUT
INPUT
IP/VREF_3
IO/VREF_3
IP/VREF_3
IP/VREF_3
IP/VREF_3
IP/VREF_3
VREF
R4
500E: VREF(I/O)
1200E:
VREF(INPUT)
1600E:
VREF(INPUT)
3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
GND
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
GND
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
GND
F3
H7
VCCO
VCCO
VCCO
VCCO
VCCO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
3
3
K1
3
L7
3
N3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A1
GND
GND
GND
A18
B2
GND
GND
GND
GND
GND
GND
B17
C10
G7
G12
H8
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
H9
GND
GND
GND
H10
H11
J3
GND
GND
GND
GND
GND
GND
GND
GND
GND
J8
GND
GND
GND
J11
K8
GND
GND
GND
GND
GND
GND
K11
K16
L8
GND
GND
GND
GND
GND
GND
GND
GND
GND
L9
48
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
Table 24: FG320 Package Pinout (Continued)
FG320
Bank
GND
GND
GND
GND
GND
GND
GND
GND
GND
XC3S500E Pin Name
GND
XC3S1200E Pin Name
GND
XC3S1600E Pin Name
GND
Ball
L10
L11
M7
Type
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
M12
T9
GND
GND
GND
GND
GND
GND
U2
GND
GND
GND
U17
V1
GND
GND
GND
GND
GND
GND
V18
V17
B1
GND
VCCAUX DONE
VCCAUX PROG_B
VCCAUX TCK
DONE
DONE
CONFIG
CONFIG
JTAG
PROG_B
TCK
PROG_B
TCK
A17
A2
VCCAUX TDI
TDI
TDI
JTAG
VCCAUX TDO
TDO
TDO
C16
D15
B7
JTAG
VCCAUX TMS
TMS
TMS
JTAG
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
B12
G2
G17
M2
M17
U7
U12
E5
E14
F6
F13
N6
N13
P5
P14
DS312-4 (v1.1) March 21, 2005
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49
Advance Product Specification
R
Pinout Descriptions
User I/Os by Bank
Table 25, Table 26, and Table 27 indicate how the available
user-I/O pins are distributed between the four I/O banks on
the FG320 package.
Table 25: User I/Os Per Bank for XC3S500E in the FG320 Package
All Possible I/O Pins by Type
Package
Edge
Maximum
I/O
I/O Bank
I/O
29
INPUT
DUAL
1
VREF
GCLK
Top
0
1
2
3
58
58
14
10
13
11
48
6
5
8
0
Right
22
21
24
0
Bottom
Left
58
17
4
0
58
34
5
8
TOTAL
232
102
46
20
16
Table 26: User I/Os Per Bank for XC3S1200E in the FG320 Package
All Possible I/O Pins by Type
Package
Edge
Maximum
I/O
I/O Bank
I/O
34
INPUT
DUAL
1
VREF
GCLK
Top
0
1
2
3
61
63
12
12
11
12
47
6
5
8
0
Right
25
21
24
0
Bottom
Left
63
23
5
0
63
38
5
8
TOTAL
250
120
46
21
16
Table 27: User I/Os Per Bank for XC3S1600E in the FG320 Package
All Possible I/O Pins by Type
Package
Edge
Maximum
I/O
I/O Bank
I/O
33
INPUT
DUAL
1
VREF
GCLK
Top
0
1
2
3
61
63
13
12
11
12
48
6
5
8
0
Right
25
21
24
0
Bottom
Left
63
23
5
0
63
38
5
8
TOTAL
250
119
46
21
16
The XC3S500E is duplicated on both the left and right sides
of the table to show migrations to and from the XC3S1200E
and the XC3S1600E. The arrows indicate the direction for
easy migration. A double-ended arrow (ꢁꢂ) indicates that
the two pins have identical functionality. A left-facing arrow
(ꢁ) indicates that the pin on the device on the right uncon-
ditionally migrates to the pin on the device on the left. It may
be possible to migrate the opposite direction depending on
the I/O configuration. For example, an I/O pin (Type = I/O)
Footprint Migration Differences
Table 28 summarizes any footprint and functionality differ-
ences between the XC3S500E, the XC3S1200E, and the
XC3S1600E FPGAs that may affect easy migration
between devices available in the FG320 package. There are
26 such balls. All other pins not listed in Table 28 uncondi-
tionally migrate between Spartan-3E devices available in
the FG320 package.
50
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
can migrate to an input-only pin (Type = INPUT) if the I/O
pin is configured as an input.
Table 28: FG320 Footprint Migration Differences
Pin
A7
Bank
0
XC3S500E
INPUT
N.C.
Migration
ꢂ
XC3S1200E
I/O
Migration
ꢁꢂ
ꢁ
XC3S1600E
I/O
Migration
XC3S500E
INPUT
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢂ
ꢁ
ꢂ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
26
A12
D4
0
ꢂ
I/O
INPUT
I/O
N.C.
N.C.
N.C.
INPUT
N.C.
N.C.
N.C.
N.C.
N.C.
I/O
3
N.C.
ꢂ
I/O
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢁꢂ
1
D6
0
N.C.
ꢂ
I/O
I/O
D13
E3
0
INPUT
N.C.
ꢂ
I/O
I/O
3
ꢂ
I/O
I/O
E4
3
N.C.
ꢂ
I/O
I/O
E6
0
N.C.
ꢂ
I/O
I/O
E15
E16
E17
F4
1
N.C.
ꢂ
I/O
I/O
1
N.C.
ꢂ
I/O
I/O
1
I/O
ꢁ
INPUT
INPUT
I/O
INPUT
INPUT
I/O
3
I/O
ꢁ
I/O
N12
N14
N15
P3
2
N.C.
ꢂ
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
I/O
1
N.C.
ꢂ
I/O
I/O
1
N.C.
ꢂ
I/O
I/O
3
N.C.
ꢂ
I/O
I/O
P4
3
N.C.
ꢂ
I/O
I/O
P12
P15
P16
R4
2
N.C.
ꢂ
I/O
I/O
1
I/O
ꢁ
INPUT
I/O
INPUT
I/O
1
N.C.
ꢂ
N.C.
VREF(I/O)
INPUT
INPUT
N.C.
N.C.
N.C.
3
VREF(I/O)
INPUT
INPUT
N.C.
ꢁ
VREF(INPUT)
I/O
VREF(INPUT)
I/O
U6
2
ꢂ
U13
V5
2
ꢂ
I/O
I/O
2
ꢂ
I/O
I/O
V6
2
N.C.
ꢂ
VREF
I/O
VREF
I/O
V7
2
N.C.
ꢂ
DIFFERENCES
26
Legend:
This pin is identical on both the device on the left and the right.
ꢁꢂ
ꢂ
This pin can unconditionally migrate from the device on the left to the device on the right. Migration in the other direction may be possible
depending on how the pin is configured for the device on the right.
This pin can unconditionally migrate from the device on the right to the device on the left. Migration in the other direction may be possible
depending on how the pin is configured for the device on the left.
ꢁ
DS312-4 (v1.1) March 21, 2005
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51
Advance Product Specification
R
Pinout Descriptions
FG320 Footprint
Bank 0
1
2
3
4
5
6
7
8
9
10
11
I/O
12
13
14
15
16
17
18
INPUT
ꢁꢂ
ꢃ
I/O
L12N_0
GCLK7
INPUT
ꢁꢂ
I/O
L24P_0
INPUT
L22P_0
I/O
L20N_0
I/O
L05P_0
I/O
L04N_0
INPUT
L02N_0
I/O
L01N_0
VCCO_0
GND
TDI
INPUT
I/O
TCK
GND
A
B
C
D
E
F
I/O
L25N_0
HSWAP
INPUT INPUT
I/O
L12P_0
GCLK6
I/O
L05N_0
VREF_0
I/O
L24N_0
INPUT
L22N_0
I/O
L20P_0
I/O
VREF_0
I/O
L04P_0
INPUT
L02P_0
I/O
L01P_0
PROG_B
VCCAUX
VCCAUX
GND
GND
INPUT
L13P_0
L13N_0
GCLK8
GCLK9
I/O
L14P_0
GCLK10
I/O
L03N_0
VREF_0
I/O
L24N_1
LDC2
I/O
L24P_1
LDC1
I/O
L01P_3
I/O
L01N_3
I/O
L25P_0
I/O
L23P_0
I/O
L18P_0
INPUT
L16P_0
I/O
L09P_0
INPUT
L07P_0
VCCO_0
VCCO_0
I/O
GND
INPUT
TMS
TDO
I/O
L21P_0
I/O
L02N_3
VREF_3
I/O
L23N_0
VREF_0
I/O
L18N_0
VREF_0
I/O
L14N_0
GCLK11
I/O
L11P_0
GCLK4
I/O
L23N_1
LDC0
I/O
L23P_1
HDC
INPUT
ꢁꢂ
I/O
ꢃ
I/O
L02P_3
INPUT
L16N_0
I/O
L09N_0
INPUT
L07N_0
I/O
L03P_0
INPUT
VREF_1
INPUT
ꢃ
I/O
L04N_3
I/O
L04P_3
I/O
L21N_0
I/O
L22P_1
I/O
L22N_1
I/O
L19N_0
VREF_0
I/O
L11N_0
GCLK5
INPUT
ꢁꢂ
I/O
L03N_3
I/O
L03P_3
I/O
L17P_0
I/O
L15P_0
I/O
L08P_0
I/O
L06N_0
VCCINT
I/O
VCCINT
INPUT
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
INPUT
ꢁꢂ
I/O
L05P_3
I/O
L05N_3
I/O
L19P_0
I/O
L17N_0
I/O
L15N_0
INPUT
L10P_0
I/O
L08N_0
I/O
L06P_0
I/O
L21N_1
I/O
L21P_1
I/O
L19N_1
I/O
L19P_1
VCCO_3
VCCO_1
INPUT VCCINT
VCCINT
I/O
L06N_3
VREF_3
I/O
L06P_3
I/O
L07N_3
I/O
L07P_3
INPUT
L10N_0
I/O
L20N_1
I/O
L20P_1
I/O
L18P_1
I/O
L18N_1
VCCAUX
VCCO_0
VCCO_0
VCCAUX
INPUT
GND
I/O
GND
INPUT
G
H
J
I/O
L16N_1
A0
I/O
L10N_3
I/O
L10P_3
I/O
L09N_3
I/O
L09P_3
I/O
L08N_3
I/O
L08P_3
I/O
L17P_1
I/O
L17N_1
I/O
L16P_1
INPUT
VREF_1
VCCO_3
VCCO_1
GND
GND
GND
GND
GND
GND
INPUT
I/O
L13P_1
A6
RHCLK4
IRDY1
I/O
L12N_3
LHCLK3
IRDY2
I/O
L14N_1
A3
I/O
L14P_1
A4
I/O
L13N_1
A5
I/O
L12P_3
LHCLK2
I/O
L11N_3
LHCLK1 LHCLK0
I/O
L11P_3
I/O
L15P_1
A2
I/O
L15N_1
A1
INPUT
VREF_3
VCCO_1
GND
I/O
L13P_3
LHCLK4
TRDY2
INPUT
INPUT
VCCO_3
GND
RHCLK7 RHCLK6 RHCLK5
I/O
I/O
I/O
I/O
L11P_1
A10
I/O
L13N_3
I/O
L14N_3
I/O
L14P_3
L12N_1
L11N_1
A9
L12P_1
VCCO_3
INPUT
GND
GND
A7
GND
INPUT INPUT
K
L
A8
RHCLK3
TRDY1
LHCLK5 LHCLK7 LHCLK6
RHCLK1 RHCLK0
RHCLK2
I/O
L17N_3
VREF_3
I/O
L09N_1
A11
I/O
L09P_1
A12
I/O
I/O
L15P_3
I/O
L15N_3
I/O
L16P_3
I/O
L16N_3
I/O
L17P_3
I/O
VCCO_1
GND
GND
I/O
L12N_2
D6
GCLK13
GND
GND
INPUT INPUT
L10N_1
L10P_1
VREF_1
I/O
L16P_2
M0
I/O
I/O
L18N_3
I/O
L18P_3
I/O
L19P_3
I/O
L19N_3
I/O
I/O
L07P_1
I/O
L07N_1
I/O
L08N_1
VCCAUX
VCCO_2
VCCO_2
VCCAUX
INPUT
GND
L05N_1
L05P_1
VREF_1
M
N
P
R
T
I/O
L21P_2
I/O
L04N_1
I/O
L04P_1
I/O
I/O
I/O
L20P_3
I/O
L20N_3
I/O
L07P_2
I/O
L09N_2
I/O
L18N_2
I/O
INPUT
L12P_2
D7
L16N_2
DIN
VCCO_3
VCCO_1
INPUT INPUT
VCCINT
VCCINT
L08P_1
ꢃ
ꢃ
ꢃ
GCLK12
D0
I/O
L22P_3
I/O
L22N_3
I/O
L21N_2
I/O
I/O
L22P_2
A23
INPUT
ꢁꢂ
I/O
ꢃ
I/O
L21N_3
I/O
L21P_3
I/O
L05N_2
I/O
L07N_2
I/O
L09P_2
I/O
L18P_2
I/O
L06P_1
I/O
L06N_1
L15N_2
D1
VCCINT
I/O
VCCINT
ꢃ
ꢃ
ꢃ
GCLK3
INPUT
VREF_3
I/O
I/O
L22N_2
A22
I/O
L24N_2
A20
I/O
L03N_1
VREF_1
I/O
L02P_1
A14
I/O
L23N_3
I/O
L23P_3
I/O
L04P_2
I/O
L05P_2
INPUT
L08N_2
I/O
L10P_2
I/O
D5
I/O
L20N_2
I/O
L03P_1
L15P_2
D2
INPUT
I/O
INPUT
ꢁꢂ
GCLK2
INPUT
I/O
I/O
I/O
L01N_2
INIT_B
I/O
L24P_2
A21
I/O
L01N_1
A15
I/O
L02N_1
A13
I/O
L24N_3
I/O
L24P_3
I/O
L04N_2
INPUT
L08P_2
I/O
L10N_2
INPUT
L17P_2
I/O
L20P_2
I/O
VREF_2
L03N_2
MOSI
L14N_2
L26P_2
VS0
VCCO_2
VCCO_2
GND
I/O
M2
CSI_B
GCLK1
A17
I/O
L03P_2
DOUT
BUSY
INPUT
L14P_2
RDWR_B L17N_2
GCLK0
I/O
I/O
L01P_2
CSO_B
I/O
L26N_2
CCLK
I/O
L01P_1
A16
INPUT
ꢁꢂ
INPUT
ꢁꢂ
I/O
VREF_2
INPUT
L11P_2
INPUT
INPUT
L23N_2
L13P_2
L25N_2
VS1
VCCAUX
VCCAUX
INPUT
GND
GND
GND
U
V
D4
GCLK14
A18
I/O
I/O
L06P_2
I/O
I/O
INPUT
L11N_2
VREF_2
I/O
L19N_2
VREF_2
I/O
ꢃ
INPUT INPUT
L02N_2 L02P_2
I/O
M1
I/O
L19P_2
INPUT
L23P_2
L06N_2
L13N_2
D3
L25P_2
VS2
VCCO_2
INPUT
INPUT DONE
GND
VRꢃEF_2
ꢃ
GCLK15
A19
Bank 2
DS312-4_06_021605
Figure 8: FG320 Package Footprint (top view)
I/O: Unrestricted,
general-purpose user I/O
DUAL: Configuration pin, then
possible user-I/O
VREF: User I/O or input
voltage reference for bank
46
INPUT: Unrestricted,
general-purpose input pin
GCLK: User I/O, input, or
global buffer input
VCCO: Output voltage supply
for bank
16
4
20
CONFIG: Dedicated
configuration pins
JTAG: Dedicated JTAG port
pins
VCCINT: Internal core supply
voltage (+1.2V)
2
0
8
8
N.C.: Not connected
GND: Ground
VCCAUX: Auxiliary supply
voltage (+2.5V)
28
52
www.xilinx.com
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
FG400: 400-ball Fine-pitch Ball Grid Array
The 400-ball fine-pitch ball grid array, FG400, supports two
different Spartan-3E FPGAs, including the XC3S1200E and
the XC3S1600E. Both devices share a common footprint for
this package as shown in Table 29 and Figure 9.
Table 29: FG400 Package Pinout
XC3S1200E
XC3S1600E
FG400
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pin Name
Ball
A14
B13
C13
C12
D12
E12
F12
G11
F11
E10
E11
A9
Type
I/O
Table 29 lists all the FG400 package pins. They are sorted
by bank number and then by pin name. Pairs of pins that
form a differential I/O pair appear together in the table. The
table also shows the pin number for each pin and the pin
type, as defined earlier.
IO_L09P_0
IO_L10N_0
I/O
IO_L10P_0
I/O
IO_L11N_0
I/O
An electronic version of this package pinout table and foot-
print diagram is available for download from the Xilinx web-
IO_L11P_0
I/O
site at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip
.
IO_L12N_0
I/O
Pinout Table
IO_L12P_0
I/O
IO_L14N_0/GCLK5
IO_L14P_0/GCLK4
IO_L15N_0/GCLK7
IO_L15P_0/GCLK6
IO_L17N_0/GCLK11
IO_L17P_0/GCLK10
IO_L18N_0
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
I/O
Table 29: FG400 Package Pinout
XC3S1200E
XC3S1600E
Pin Name
FG400
Ball
Bank
0
Type
I/O
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
A3
A8
0
I/O
A10
F9
0
A12
C7
I/O
0
I/O
IO_L18P_0
E9
I/O
0
C10
E8
I/O
IO_L20N_0
C9
I/O
0
I/O
IO_L20P_0
D9
I/O
0
E13
E16
F13
F14
G7
I/O
IO_L21N_0/VREF_0
IO_L21P_0
B8
VREF
I/O
0
I/O
B9
0
I/O
IO_L23N_0/VREF_0
IO_L23P_0
F7
VREF
I/O
0
I/O
F8
0
I/O
IO_L24N_0
A6
I/O
0
IO/VREF_0
C11
B17
C17
A18
A19
A17
A16
A15
B15
C14
D14
A13
VREF
I/O
IO_L24P_0
A7
I/O
0
IO_L01N_0
IO_L26N_0
B5
I/O
0
IO_L01P_0
I/O
IO_L26P_0
B6
I/O
0
IO_L03N_0/VREF_0
IO_L03P_0
VREF
I/O
IO_L27N_0
D6
I/O
0
IO_L27P_0
C6
I/O
0
IO_L04N_0
I/O
IO_L29N_0/VREF_0
IO_L29P_0
C5
VREF
I/O
0
IO_L04P_0
I/O
D5
0
IO_L06N_0
I/O
IO_L30N_0
A2
I/O
0
IO_L06P_0
I/O
IO_L30P_0
B2
I/O
0
IO_L07N_0
I/O
IO_L31N_0/HSWAP
IO_L31P_0
D4
DUAL
I/O
0
IO_L07P_0
I/O
C4
0
IO_L09N_0/VREF_0
VREF
DS312-4 (v1.1) March 21, 2005
www.xilinx.com
53
Advance Product Specification
R
Pinout Descriptions
Table 29: FG400 Package Pinout
Table 29: FG400 Package Pinout
XC3S1200E
XC3S1600E
Pin Name
XC3S1200E
XC3S1600E
Pin Name
FG400
Ball
FG400
Ball
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
Type
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
GCLK
GCLK
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
DUAL
DUAL
DUAL
DUAL
VREF
I/O
Bank
1
Type
I/O
IP
IP
B18
E5
IO_L04N_1
W20
V20
R18
R17
T20
U20
P18
P17
P20
R20
P16
N16
N19
N18
N15
M15
M18
M17
L19
M19
L16
1
IO_L04P_1
I/O
IP_L02N_0
IP_L02P_0
IP_L05N_0
IP_L05P_0
IP_L08N_0
IP_L08P_0
IP_L10N_0
IP_L10P_0
IP_L13N_0
IP_L13P_0
IP_L16N_0/GCLK9
IP_L16P_0/GCLK8
IP_L19N_0
IP_L19P_0
IP_L22N_0
IP_L22P_0
IP_L25N_0
IP_L25P_0
IP_L28N_0
IP_L28P_0
VCCO_0
C16
D16
D15
C15
E14
E15
G14
G13
B11
B12
G10
H10
G9
1
IO_L05N_1
I/O
1
IO_L05P_1
I/O
1
IO_L06N_1
I/O
1
IO_L06P_1
I/O
1
IO_L07N_1
I/O
1
IO_L07P_1
I/O
1
IO_L08N_1/VREF_1
IO_L08P_1
VREF
I/O
1
1
IO_L09N_1
I/O
1
IO_L09P_1
I/O
1
IO_L10N_1
I/O
1
IO_L10P_1
I/O
1
IO_L11N_1
I/O
G8
1
IO_L11P_1
I/O
C8
1
IO_L12N_1/A11
IO_L12P_1/A12
IO_L13N_1/VREF_1
IO_L13P_1
DUAL
DUAL
VREF
I/O
D8
1
E6
1
E7
1
A4
1
IO_L14N_1/A9/RHCLK1
RHCLK/
DUAL
A5
1
1
1
1
1
1
1
IO_L14P_1/A10/RHCLK0
M16
L14
L15
K14
K13
J20
K20
RHCLK/
DUAL
B4
VCCO_0
B10
B16
D7
IO_L15N_1/A7/RHCLK3/
TRDY1
RHCLK/
DUAL
VCCO_0
IO_L15P_1/A8/RHCLK2
RHCLK/
DUAL
VCCO_0
VCCO_0
D13
F10
U18
U17
T18
T17
V19
U19
IO_L16N_1/A5/RHCLK5
RHCLK/
DUAL
VCCO_0
IO_L01N_1/A15
IO_L01P_1/A16
IO_L02N_1/A13
IO_L02P_1/A14
IO_L03N_1/VREF_1
IO_L03P_1
IO_L16P_1/A6/RHCLK4/
IRDY1
RHCLK/
DUAL
IO_L17N_1/A3/RHCLK7
RHCLK/
DUAL
IO_L17P_1/A4/RHCLK6
RHCLK/
DUAL
1
1
IO_L18N_1/A1
IO_L18P_1/A2
K16
J16
DUAL
DUAL
54
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
Table 29: FG400 Package Pinout
Table 29: FG400 Package Pinout
XC3S1200E
XC3S1600E
Pin Name
XC3S1200E
XC3S1600E
Pin Name
FG400
Ball
FG400
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Type
DUAL
I/O
Bank
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Ball
R16
R19
E19
K18
D19
G17
K15
K19
N17
T19
P8
Type
INPUT
INPUT
VREF
VREF
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
I/O
IO_L19N_1/A0
J13
J14
IP
IP
IO_L19P_1
IO_L20N_1
IO_L20P_1
IO_L21N_1
IO_L21P_1
IO_L22N_1
IO_L22P_1
IO_L23N_1
IO_L23P_1
IO_L24N_1/VREF_1
IO_L24P_1
IO_L25N_1
IO_L25P_1
IO_L26N_1
IO_L26P_1
IO_L27N_1
IO_L27P_1
IO_L28N_1
IO_L28P_1
IO_L29N_1/LDC0
IO_L29P_1/HDC
IO_L30N_1/LDC2
IO_L30P_1/LDC1
IP
J17
I/O
IP/VREF_1
IP/VREF_1
VCCO_1
J18
I/O
H19
J19
I/O
I/O
VCCO_1
H15
H16
H18
H17
H20
G20
G16
F16
F19
F20
F18
F17
D20
E20
D18
E18
C19
C20
B20
G15
G18
H14
J15
I/O
VCCO_1
I/O
VCCO_1
I/O
VCCO_1
I/O
VCCO_1
VREF
I/O
IO
IO
P13
R9
I/O
I/O
IO
I/O
I/O
IO
R13
W15
Y5
I/O
I/O
IO
I/O
I/O
IO
I/O
I/O
IO
Y7
I/O
I/O
IO
Y13
N11
T11
Y3
I/O
I/O
IO/D5
DUAL
DUAL
VREF
VREF
DUAL
DUAL
DUAL
DUAL
I/O
I/O
IO/M1
DUAL
DUAL
DUAL
DUAL
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
IO/VREF_2
IO/VREF_2
IO_L01N_2/INIT_B
IO_L01P_2/CSO_B
IO_L03N_2/MOSI/CSI_B
IO_L03P_2/DOUT/BUSY
IO_L04N_2
IO_L04P_2
IO_L06N_2
IO_L06P_2
IO_L07N_2
IO_L07P_2
IO_L09N_2/VREF_2
IO_L09P_2
Y17
V4
U4
V5
IP
U5
IP
Y4
IP
W4
T6
I/O
IP
I/O
IP
L18
M20
N14
N20
P15
T5
I/O
IP
U7
I/O
IP
V7
I/O
IP
R7
VREF
I/O
IP
T7
DS312-4 (v1.1) March 21, 2005
www.xilinx.com
55
Advance Product Specification
R
Pinout Descriptions
Table 29: FG400 Package Pinout
Table 29: FG400 Package Pinout
XC3S1200E
XC3S1600E
Pin Name
XC3S1200E
XC3S1600E
Pin Name
IO_L32P_2/VS0/A17
IP
FG400
Ball
FG400
Ball
Bank
Type
I/O
Bank
Type
DUAL
2
2
2
2
2
2
2
IO_L10N_2
V8
W8
U9
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Y19
T16
W3
Y2
IO_L10P_2
I/O
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VREF
INPUT
IO_L12N_2
I/O
IP
IO_L12P_2
V9
I/O
IP_L02N_2
IO_L13N_2
Y8
I/O
IP_L02P_2
W2
V6
IO_L13P_2
Y9
I/O
IP_L05N_2
IO_L15N_2/D6/GCLK13
W10
DUAL/
GCLK
IP_L05P_2
U6
IP_L08N_2
Y6
2
2
2
2
2
IO_L15P_2/D7/GCLK12
IO_L16N_2/D3/GCLK15
IO_L16P_2/D4/GCLK14
IO_L18N_2/D1/GCLK3
IO_L18P_2/D2/GCLK2
W9
P10
R10
V11
V10
DUAL/
GCLK
IP_L08P_2
W6
R8
IP_L11N_2
DUAL/
GCLK
IP_L11P_2
T8
DUAL/
GCLK
IP_L14N_2/VREF_2
IP_L14P_2
T10
T9
DUAL/
GCLK
IP_L17N_2/M2/GCLK1
P12
DUAL/
GCLK
DUAL/
GCLK
2
IP_L17P_2/RDWR_B/
GCLK0
P11
DUAL/
GCLK
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO_L19N_2/DIN/D0
IO_L19P_2/M0
IO_L21N_2
Y12
Y11
U12
V12
W12
W13
U13
V13
P14
R14
Y14
Y15
T15
U15
V16
U16
Y18
W18
W19
DUAL
DUAL
I/O
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
IP_L20N_2
IP_L20P_2
IP_L23N_2/VREF_2
IP_L23P_2
IP_L26N_2
IP_L26P_2
IP_L29N_2
IP_L29P_2
VCCO_2
T12
R12
T13
T14
V14
V15
W16
Y16
R11
U8
INPUT
INPUT
VREF
INPUT
INPUT
INPUT
INPUT
INPUT
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
I/O
IO_L21P_2
I/O
IO_L22N_2/VREF_2
IO_L22P_2
VREF
I/O
IO_L24N_2
I/O
IO_L24P_2
I/O
IO_L25N_2
I/O
IO_L25P_2
I/O
VCCO_2
IO_L27N_2/A22
IO_L27P_2/A23
IO_L28N_2
DUAL
DUAL
I/O
VCCO_2
U14
W5
VCCO_2
VCCO_2
W11
W17
D2
IO_L28P_2
I/O
VCCO_2
IO_L30N_2/A20
IO_L30P_2/A21
IO_L31N_2/VS1/A18
IO_L31P_2/VS2/A19
IO_L32N_2/CCLK
DUAL
DUAL
DUAL
DUAL
DUAL
IO_L01N_3
IO_L01P_3
IO_L02N_3/VREF_3
IO_L02P_3
D3
I/O
E3
VREF
I/O
E4
56
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
Table 29: FG400 Package Pinout
Table 29: FG400 Package Pinout
XC3S1200E
XC3S1600E
Pin Name
XC3S1200E
XC3S1600E
FG400
Ball
FG400
Bank
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Type
I/O
Bank
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Name
IO_L20N_3/VREF_3
IO_L20P_3
IO_L21N_3
IO_L21P_3
IO_L22N_3
IO_L22P_3
IO_L23N_3
IO_L23P_3
IO_L24N_3
IO_L24P_3
IO_L25N_3
IO_L25P_3
IO_L26N_3
IO_L26P_3
IO_L27N_3
IO_L27P_3
IO_L28N_3/VREF_3
IO_L28P_3
IO_L29N_3
IO_L29P_3
IO_L30N_3
IO_L30P_3
IP
Ball
N6
M6
N2
N1
P7
N7
N4
N3
R1
P1
R5
P5
T2
R2
R4
R3
T1
U1
T3
U3
V1
V2
F5
G1
G6
H1
J5
Type
VREF
I/O
IO_L03N_3
C1
B1
E1
D1
F3
F4
F1
F2
G4
G3
G5
H5
H3
H2
H7
H6
J4
IO_L03P_3
I/O
IO_L04N_3
I/O
I/O
IO_L04P_3
I/O
I/O
IO_L05N_3
I/O
I/O
IO_L05P_3
I/O
I/O
IO_L06N_3
I/O
I/O
IO_L06P_3
I/O
I/O
IO_L07N_3
I/O
I/O
IO_L07P_3
I/O
I/O
IO_L08N_3
I/O
I/O
IO_L08P_3
I/O
I/O
IO_L09N_3/VREF_3
IO_L09P_3
VREF
I/O
I/O
I/O
IO_L10N_3
I/O
I/O
IO_L10P_3
I/O
I/O
IO_L11N_3
I/O
VREF
I/O
IO_L11P_3
J3
I/O
IO_L12N_3
J1
I/O
I/O
IO_L12P_3
J2
I/O
I/O
IO_L13N_3
J6
I/O
I/O
IO_L13P_3
K6
K2
K3
L7
I/O
I/O
IO_L14N_3/LHCLK1
IO_L14P_3/LHCLK0
IO_L15N_3/LHCLK3/IRDY2
IO_L15P_3/LHCLK2
IO_L16N_3/LHCLK5
IO_L16P_3/LHCLK4/TRDY2
IO_L17N_3/LHCLK7
IO_L17P_3/LHCLK6
IO_L18N_3
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
I/O
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
IP
IP
K7
L1
IP
IP
M1
L3
IP
L5
IP
L8
M3
M7
M8
M4
M5
IP
M2
N5
P3
T4
W1
IP
IO_L18P_3
I/O
IP
IO_L19N_3
I/O
IP
IO_L19P_3
I/O
IP
DS312-4 (v1.1) March 21, 2005
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57
Advance Product Specification
R
Pinout Descriptions
Table 29: FG400 Package Pinout
Table 29: FG400 Package Pinout
XC3S1200E
XC3S1600E
Pin Name
XC3S1200E
XC3S1600E
Pin Name
FG400
Ball
FG400
Ball
Bank
3
Type
VREF
VREF
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Bank
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Type
GND
IP/VREF_3
K5
P6
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
M10
M12
N13
P2
3
IP/VREF_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
GND
GND
3
E2
GND
3
H4
GND
3
L2
P9
GND
3
L6
P19
R6
GND
3
P4
GND
3
U2
R15
U11
V3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A1
GND
GND
A11
A20
B7
GND
GND
V18
W7
W14
Y1
GND
GND
GND
GND
B14
C3
GND
GND
GND
GND
C18
D10
F6
Y10
Y20
V17
C2
GND
GND
GND
GND
VCCAUX DONE
VCCAUX PROG_B
VCCAUX TCK
CONFIG
CONFIG
JTAG
GND
F15
G2
G12
G19
H8
GND
D17
B3
GND
VCCAUX TDI
JTAG
GND
VCCAUX TDO
B19
E17
D11
H12
J7
JTAG
GND
VCCAUX TMS
JTAG
GND
J9
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
GND
J11
K1
GND
GND
K8
K4
GND
K10
K12
K17
L4
L17
M14
N9
GND
GND
GND
U10
H9
GND
L9
GND
L11
L13
L20
H11
H13
J8
GND
GND
58
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
Table 29: FG400 Package Pinout
Table 29: FG400 Package Pinout
XC3S1200E
XC3S1600E
Pin Name
XC3S1200E
XC3S1600E
Pin Name
FG400
Ball
FG400
Bank
Type
Bank
Ball
M13
N8
Type
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
J10
J12
K9
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
N10
N12
K11
L10
L12
M9
User I/Os by Bank
Table 30 indicates how the 304 available user-I/O pins are
distributed between the four I/O banks on the FG400 pack-
age.
M11
Table 30: User I/Os Per Bank for the XC3S250E and XC3S500E in the FG400 Package
All Possible I/O Pins by Type
Package
Edge
Maximum
I/O
I/O Bank
I/O
43
INPUT
DUAL
1
VREF
GCLK
Top
0
1
2
3
78
74
20
12
18
12
62
6
6
8
0
Right
35
21
24
0
Bottom
Left
78
30
6
0
74
48
6
8
TOTAL
304
156
46
24
16
between the XC3S1200E and XC3S1600E FPGAs without
further consideration.
Footprint Migration Differences
The XC3S1200E and XC3S1600E FPGAs have identical
footprints in the FG400 package. Designs can migrate
DS312-4 (v1.1) March 21, 2005
www.xilinx.com
59
Advance Product Specification
R
Pinout Descriptions
FG400 Footprint
Bank 0
1
2
3
4
5
6
7
8
10
9
Left Half of Package
(top view)
I/O
L17N_0
GCLK11
I/O
L17P_0
GCLK10
I/O
L30N_0
INPUT
L28N_0
INPUT
L28P_0
I/O
L24N_0
I/O
L24P_0
GND
I/O
I/O
A
B
C
D
E
F
I/O
L21N_0
VREF_0
I/O
L03P_3
I/O
L30P_0
I/O
L26N_0
I/O
L26P_0
I/O
L21P_0
VCCO_0
VCCO_0
I/O
TDI
GND
I/O
I/O: Unrestricted,
156
general-purpose user I/O
I/O
L29N_0
VREF_0
I/O
L03N_3
I/O
L31P_0
I/O
L27P_0
INPUT
L22N_0
I/O
L20N_0
PROG_B
GND
INPUT: User I/O or
reference resistor input for
bank
62
I/O
L31N_0
HSWAP
I/O
L04P_3
I/O
L01N_3
I/O
L01P_3
I/O
L29P_0
I/O
L27N_0
INPUT
L22P_0
I/O
L20P_0
VCCO_0
GND
DUAL: Configuration pin,
then possible user I/O
46
24
16
2
I/O
L02N_3
VREF_3
I/O
L15N_0
GCLK7
I/O
L04N_3
I/O
L02P_3
INPUT
L25N_0
INPUT
L25P_0
I/O
L18P_0
VCCO_3
INPUT
INPUT
I/O
VREF: User I/O or input
voltage reference for bank
I/O
L23N_0
VREF_0
I/O
L06N_3
I/O
L06P_3
I/O
L05N_3
I/O
L05P_3
I/O
L23P_0
I/O
L18N_0
VCCO_0
GND
GCLK: User I/O, input, or
clock buffer input
INPUT
L16N_0
GCLK9
I/O
L07P_3
I/O
L07N_3
I/O
L08N_3
INPUT
L19P_0
INPUT
L19N_0
INPUT
INPUT
GND
INPUT
I/O
G
H
J
CONFIG: Dedicated
configuration pins
I/O
L09N_3
VREF_3
INPUT
L16P_0
GCLK8
I/O
L09P_3
I/O
L08P_3
I/O
L10P_3
I/O
L10N_3
VCCO_3
GND
VCCINT
GND
VCCINT
GND
JTAG: Dedicated JTAG
port pins
4
I/O
L12N_3
I/O
L12P_3
I/O
L11P_3
I/O
L11N_3
I/O
L13N_3
VCCAUX
INPUT
VCCINT
GND
GND: Ground
I/O
L14N_3
LHCLK1
I/O
L14P_3
LHCLK0
I/O
L15P_3
LHCLK2
42
24
16
8
INPUT
VREF_3
I/O
L13P_3
VCCAUX
GND
VCCINT
GND
K
L
VCCO: Output voltage
supply for bank
I/O
L15N_3
LHCLK3
IRDY2
I/O
L16N_3
LHCLK5
I/O
L17N_3
LHCLK7
VCCO_3
VCCO_3
GND
INPUT
INPUT
VCCINT
GND
VCCINT: Internal core
supply voltage (+1.2V)
I/O
L16P_3
LHCLK4
TRDY2
I/O
L17P_3
LHCLK6
I/O
L19N_3
I/O
L19P_3
I/O
L20P_3
I/O
L18N_3
I/O
L18P_3
INPUT
VCCINT
VCCAUX
GND
M
N
P
R
T
VCCAUX: Auxiliary supply
voltage (+2.5V)
I/O
L20N_3
VREF_3
I/O
L21P_3
I/O
L21N_3
I/O
L23P_3
I/O
L23N_3
I/O
L22P_3
INPUT
VCCINT
I/O
VCCINT
I/O
L16N_2
D3
GCLK15
N.C.: Not connected
0
I/O
L24P_3
I/O
L25P_3
INPUT
VREF_3
I/O
L22N_3
VCCO_3
GND
INPUT
I/O
I/O
L09N_2
VREF_2
I/O
L24N_3
I/O
L26P_3
I/O
L27P_3
I/O
L27N_3
I/O
L25N_3
INPUT
L11N_2
L16P_2
D4
GND
I/O
GCLK14
I/O
L28N_3
VREF_3
INPUT
L14N_2
VREF_2
I/O
L26N_3
I/O
L29N_3
I/O
L06P_2
I/O
L06N_2
I/O
L09P_2
INPUT
L11P_2
INPUT
L14P_2
INPUT
I/O
L03P_2
DOUT
BUSY
I/O
L01P_2
CSO_B
I/O
L28P_3
I/O
L29P_3
INPUT
L05P_2
I/O
L07N_2
I/O
L12N_2
VCCO_3
VCCO_2
VCCAUX
U
V
W
Y
I/O
I/O
I/O
L01N_2
INIT_B
I/O
L30N_3
I/O
L30P_3
INPUT
L05N_2
I/O
L07P_2
I/O
L10N_2
I/O
L12P_2
L03N_2
MOSI
L18P_2
D2
GND
CSI_B
GCLK2
I/O
I/O
INPUT
L02P_2
I/O
L04P_2
INPUT
L08P_2
I/O
L10P_2
L15P_2
D7
L15N_2
D6
VCCO_2
INPUT
GND
INPUT
GND
I/O
GCLK12
GCLK13
INPUT
L02N_2
I/O
VREF_2
I/O
L04N_2
INPUT
L08N_2
I/O
L13N_2
I/O
L13P_2
I/O
GND
Bank 2
DS312-4_08_031105
Figure 9: FG400 Package Footprint (top view)
60
www.xilinx.com
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
Bank 0
11
12
I/O
13
14
15
16
17
18
19
20
Right Half of Package
(top view)
I/O
L09N_0
VREF_0
I/O
L03N_0
VREF_0
I/O
L09P_0
I/O
L06N_0
I/O
L04P_0
I/O
L04N_0
I/O
L03P_0
GND
GND
A
B
C
D
E
F
INPUT
L13N_0
INPUT
L13P_0
I/O
L10N_0
I/O
L06P_0
I/O
L01N_0
VCCO_0
GND
INPUT
GND
TDO
INPUT
I/O
L30N_1
LDC2
I/O
L30P_1
LDC1
I/O
VREF_0
I/O
L11N_0
I/O
L10P_0
I/O
L07N_0
INPUT
L05P_0
INPUT
L02N_0
I/O
L01P_0
I/O
L29N_1
LDC0
I/O
L11P_0
I/O
L07P_0
INPUT
L05N_0
INPUT
L02P_0
I/O
L28N_1
VCCAUX
VCCO_0
I/O
VCCO_1
TCK
TMS
I/O
L15P_0
GCLK6
I/O
L29P_1
HDC
I/O
L12N_0
INPUT
L08N_0
INPUT
L08P_0
INPUT
VREF_1
I/O
L28P_1
I/O
I/O
L14P_0
GCLK4
I/O
L12P_0
I/O
L25P_1
I/O
L27P_1
I/O
L27N_1
I/O
L26N_1
I/O
L26P_1
I/O
I/O
GND
I/O
L14N_0
GCLK5
INPUT
L10P_0
INPUT
L10N_0
I/O
L25N_1
I/O
L24P_1
VCCO_1
GND
VCCAUX
VCCINT
GND
INPUT
INPUT
GND
G
H
J
I/O
L24N_1
VREF_1
I/O
L22N_1
I/O
L22P_1
I/O
L23P_1
I/O
L23N_1
I/O
L21N_1
VCCINT
GND
VCCINT INPUT
I/O
I/O
I/O
I/O
L18P_1
A2
I/O
L20N_1
I/O
L20P_1
I/O
L21P_1
L17N_1
A3
INPUT
L19N_1
L19P_1
A0
RHCLK7
I/O
L16P_1
A6
RHCLK4
IRDY1
I/O
I/O
I/O
L18N_1
A1
INPUT
VREF_1
L16N_1
A5
L17P_1
A4
VCCO_1
VCCO_1
VCCINT
GND
GND
K
L
RHCLK5
RHCLK6
I/O
L15N_1
A7
RHCLK3
TRDY1
I/O
I/O
I/O
L13N_1
VREF_1
L15P_1
A8
L14N_1
A9
VCCAUX
VCCINT
GND
GND
VCCINT
GND
I/O
INPUT
GND
RHCLK2
RHCLK1
I/O
I/O
L12P_1
A12
I/O
L12N_1
A11
I/O
L11P_1
I/O
L13P_1
L14P_1
A10
VCCAUX
VCCINT
INPUT
INPUT
M
N
P
R
T
RHCLK0
I/O
D5
I/O
L11N_1
I/O
L09P_1
I/O
L10P_1
I/O
L10N_1
VCCO_1
VCCINT
INPUT
L17N_2
M2
GCLK1
INPUT
INPUT
L17P_2
RDWR_B
GCLK0
I/O
L08N_1
VREF_1
I/O
L25N_2
I/O
L09N_1
I/O
L07P_1
I/O
L07N_1
INPUT
GND
GND
INPUT
VCCO_1
INPUT
L20P_2
I/O
L25P_2
I/O
L05P_1
I/O
L05N_1
I/O
L08P_1
VCCO_2
I/O
INPUT
INPUT
INPUT
L23N_2
VREF_2
I/O
L02P_1
A14
I/O
L02N_1
A13
I/O
M1
INPUT
L20N_2
INPUT
L23P_2
I/O
L28N_2
I/O
L06N_1
I/O
L30P_2
A21
I/O
L01P_1
A16
I/O
L01N_1
A15
I/O
L21N_2
I/O
L24N_2
I/O
L28P_2
I/O
L03P_1
I/O
L06P_1
VCCO_2
GND
I/O
U
V
W
Y
I/O
L30N_2
A20
I/O
L03N_1
VREF_1
I/O
L21P_2
I/O
L24P_2
INPUT
L26N_2
INPUT
L26P_2
I/O
L04P_1
L18N_2
D1
DONE
GND
I/O
L31P_2
VS2
A19
GCLK3
I/O
L22N_2
VREF_2
I/O
L32N_2
CCLK
I/O
L22P_2
INPUT
L29N_2
I/O
L04N_1
VCCO_2
VCCO_2
GND
I/O
I/O
I/O
I/O
I/O
L19P_2
M0
I/O
L27N_2
A22
I/O
L27P_2
A23
INPUT
L29P_2
I/O
VREF_2
L19N_2
DIN
L31N_2
VS1
L32P_2
VS0
I/O
GND
D0
A18
A17
Bank 2
DS312-4_09_031105
DS312-4 (v1.1) March 21, 2005
www.xilinx.com
61
Advance Product Specification
R
Pinout Descriptions
FG484: 484-ball Fine-pitch Ball Grid Array
The 484-ball fine-pitch ball grid array, FG484, supports the
XC3S1600E FPGA.
Table 31: FG484 Package Pinout
XC3S1600E
FG484
Ball
Table 31 lists all the FG484 package pins. They are sorted
by bank number and then by pin name. Pairs of pins that
form a differential I/O pair appear together in the table. The
table also shows the pin number for each pin and the pin
type, as defined earlier.
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pin Name
Type
I/O
IO_L10P_0
F15
D14
E14
A14
A15
H14
G14
G13
F13
J13
H13
E12
F12
C12
B12
B11
C11
D11
E11
A9
IO_L11N_0
I/O
IO_L11P_0
I/O
An electronic version of this package pinout table and foot-
print diagram is available for download from the Xilinx web-
IO_L12N_0/VREF_0
IO_L12P_0
VREF
I/O
site at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip
.
IO_L13N_0
I/O
Pinout Table
IO_L13P_0
I/O
Table 31: FG484 Package Pinout
IO_L15N_0
I/O
XC3S1600E
Pin Name
FG484
Ball
IO_L15P_0
I/O
Bank
0
Type
I/O
IO_L16N_0
I/O
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
B6
IO_L16P_0
I/O
0
B13
C5
I/O
IO_L18N_0/GCLK5
IO_L18P_0/GCLK4
IO_L19N_0/GCLK7
IO_L19P_0/GCLK6
IO_L21N_0/GCLK11
IO_L21P_0/GCLK10
IO_L22N_0
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
I/O
0
I/O
0
C14
E16
F9
I/O
0
I/O
0
I/O
0
F16
G8
I/O
0
I/O
0
H10
H15
J11
G12
C18
C19
A20
A21
A19
A18
C16
D16
A16
A17
B15
C15
G15
I/O
IO_L22P_0
I/O
0
I/O
IO_L24N_0
I/O
0
I/O
IO_L24P_0
A10
D10
C10
H8
I/O
0
IO/VREF_0
VREF
I/O
IO_L25N_0/VREF_0
IO_L25P_0
VREF
I/O
0
IO_L01N_0
0
IO_L01P_0
I/O
IO_L27N_0
I/O
0
IO_L03N_0/VREF_0
IO_L03P_0
VREF
I/O
IO_L27P_0
H9
I/O
0
IO_L28N_0
C9
I/O
0
IO_L04N_0
I/O
IO_L28P_0
B9
I/O
0
IO_L04P_0
I/O
IO_L29N_0
E9
I/O
0
IO_L06N_0
I/O
IO_L29P_0
D9
I/O
0
IO_L06P_0
I/O
IO_L30N_0
B8
I/O
0
IO_L07N_0
I/O
IO_L30P_0
A8
I/O
0
IO_L07P_0
I/O
IO_L32N_0/VREF_0
IO_L32P_0
F7
VREF
I/O
0
IO_L09N_0/VREF_0
IO_L09P_0
VREF
I/O
F8
0
IO_L33N_0
A6
I/O
0
IO_L10N_0
I/O
62
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
FG484
Table 31: FG484 Package Pinout
Table 31: FG484 Package Pinout
XC3S1600E
FG484
Ball
XC3S1600E
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pin Name
Type
I/O
Bank
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Name
Ball
Type
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
DUAL
DUAL
DUAL
DUAL
VREF
I/O
IO_L33P_0
A7
A4
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
B5
IO_L35N_0
IO_L35P_0
IO_L36N_0
IO_L36P_0
IO_L38N_0/VREF_0
IO_L38P_0
IO_L39N_0
IO_L39P_0
IO_L40N_0/HSWAP
IO_L40P_0
IP
I/O
B10
B14
B18
E8
A5
I/O
E7
I/O
D7
I/O
D6
VREF
I/O
F14
G11
Y22
AA22
W21
Y21
W20
V20
U19
V19
V22
W22
T19
T18
U20
U21
T22
U22
R19
R18
R16
T16
R21
R20
P18
P17
P22
R22
P15
P16
D5
B4
I/O
IO_L01N_1/A15
IO_L01P_1/A16
IO_L02N_1/A13
IO_L02P_1/A14
IO_L03N_1/VREF_1
IO_L03P_1
B3
I/O
D4
DUAL
I/O
C4
B19
E6
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
GCLK
GCLK
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
IP
IP_L02N_0
IP_L02P_0
IP_L05N_0
IP_L05P_0
IP_L08N_0
IP_L08P_0
IP_L14N_0
IP_L14P_0
IP_L17N_0
IP_L17P_0
IP_L20N_0/GCLK9
IP_L20P_0/GCLK8
IP_L23N_0
IP_L23P_0
IP_L26N_0
IP_L26P_0
IP_L31N_0
IP_L31P_0
IP_L34N_0
IP_L34P_0
IP_L37N_0
IP_L37P_0
D17
D18
C17
B17
E15
D15
D13
C13
A12
A13
H11
H12
F10
F11
G9
IO_L04N_1
I/O
IO_L04P_1
I/O
IO_L05N_1
I/O
IO_L05P_1
I/O
IO_L06N_1
I/O
IO_L06P_1
I/O
IO_L07N_1/VREF_1
IO_L07P_1
VREF
I/O
IO_L08N_1
I/O
IO_L08P_1
I/O
IO_L09N_1
I/O
IO_L09P_1
I/O
IO_L10N_1
I/O
IO_L10P_1
I/O
IO_L11N_1
I/O
G10
C8
IO_L11P_1
I/O
IO_L12N_1/VREF_1
IO_L12P_1
VREF
I/O
D8
C7
IO_L13N_1
I/O
C6
IO_L13P_1
I/O
A3
IO_L14N_1
I/O
A2
IO_L14P_1
I/O
DS312-4 (v1.1) March 21, 2005
www.xilinx.com
63
Advance Product Specification
R
Pinout Descriptions
Table 31: FG484 Package Pinout
Table 31: FG484 Package Pinout
XC3S1600E
Pin Name
FG484
Ball
XC3S1600E
Pin Name
FG484
Ball
Bank
Type
I/O
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Type
I/O
1
1
1
1
1
1
1
IO_L15N_1
N18
N19
N16
N17
M20
N20
M22
IO_L30N_1
H17
G17
F22
G22
F20
G20
G18
G19
D22
E22
F19
F18
E20
E19
C21
C22
B21
B22
D20
F21
G16
H16
J16
IO_L15P_1
I/O
IO_L30P_1
I/O
IO_L16N_1/A11
IO_L16P_1/A12
IO_L17N_1/VREF_1
IO_L17P_1
DUAL
DUAL
VREF
I/O
IO_L31N_1
I/O
IO_L31P_1
I/O
IO_L32N_1
I/O
IO_L32P_1
I/O
IO_L18N_1/A9/RHCLK1
RHCLK/
DUAL
IO_L33N_1
I/O
IO_L33P_1
I/O
1
1
1
1
1
1
1
IO_L18P_1/A10/RHCLK0
N22
M16
M15
L21
L20
L19
L18
RHCLK/
DUAL
IO_L34N_1
I/O
IO_L34P_1
I/O
IO_L19N_1/A7/RHCLK3/
TRDY1
RHCLK/
DUAL
IO_L35N_1
I/O
IO_L19P_1/A8/RHCLK2
RHCLK/
DUAL
IO_L35P_1
I/O
IO_L36N_1
I/O
IO_L20N_1/A5/RHCLK5
RHCLK/
DUAL
IO_L36P_1
I/O
IO_L37N_1/LDC0
DUAL
DUAL
DUAL
DUAL
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VREF
IO_L20P_1/A6/RHCLK4/
IRDY1
RHCLK/
DUAL
IO_L37P_1/HDC
IO_L21N_1/A3/RHCLK7
RHCLK/
DUAL
IO_L38N_1/LDC2
IO_L38P_1/LDC1
IO_L21P_1/A4/RHCLK6
RHCLK/
DUAL
IP
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IO_L22N_1/A1
IO_L22P_1/A2
IO_L23N_1/A0
IO_L23P_1
K22
L22
K17
K16
K19
K18
K15
J15
J20
J21
J17
J18
H21
H22
H20
H19
DUAL
DUAL
DUAL
I/O
IP
IP
IP
IP
IO_L24N_1
IO_L24P_1
I/O
IP
J22
I/O
IP
K20
L15
M18
N15
N21
P20
R15
T17
T20
U18
D21
IO_L25N_1
IO_L25P_1
I/O
IP
I/O
IP
IO_L26N_1
IO_L26P_1
I/O
IP
I/O
IP
IO_L27N_1
IO_L27P_1
I/O
IP
I/O
IP
IO_L28N_1/VREF_1
IO_L28P_1
VREF
I/O
IP
IP
IO_L29N_1
IO_L29P_1
I/O
IP
I/O
IP/VREF_1
64
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
FG484
Table 31: FG484 Package Pinout
Table 31: FG484 Package Pinout
XC3S1600E
FG484
Ball
XC3S1600E
Bank
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Pin Name
Type
VREF
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
I/O
Bank
Pin Name
Ball
AA8
W9
Type
IP/VREF_1
L17
E21
H18
K21
L16
P21
R17
V21
Y8
2
2
2
2
2
2
2
2
2
2
2
2
IO_L11P_2
I/O
VCCO_1
IO_L12N_2
I/O
VCCO_1
IO_L12P_2
V9
I/O
VCCO_1
IO_L13N_2/VREF_2
IO_L13P_2
R9
VREF
I/O
VCCO_1
T9
VCCO_1
IO_L14N_2
AB9
AB10
U10
T10
R10
P10
U11
I/O
VCCO_1
IO_L14P_2
I/O
VCCO_1
IO_L16N_2
I/O
IO
IO_L16P_2
I/O
IO
Y9
I/O
IO_L17N_2
I/O
IO
AA10
AB5
AB13
AB14
AB16
AB18
AB11
AA12
AB4
AB21
AB3
AA3
Y5
I/O
IO_L17P_2
I/O
IO
I/O
IO_L19N_2/D6/GCLK13
DUAL/
GCLK
IO
I/O
2
2
2
2
2
IO_L19P_2/D7/GCLK12
IO_L20N_2/D3/GCLK15
IO_L20P_2/D4/GCLK14
IO_L22N_2/D1/GCLK3
IO_L22P_2/D2/GCLK2
V11
T11
R11
W12
Y12
DUAL/
GCLK
IO
I/O
IO
I/O
DUAL/
GCLK
IO
I/O
DUAL/
GCLK
IO/D5
DUAL
DUAL
VREF
VREF
DUAL
DUAL
DUAL
DUAL
I/O
IO/M1
DUAL/
GCLK
IO/VREF_2
IO/VREF_2
IO_L01N_2/INIT_B
IO_L01P_2/CSO_B
IO_L03N_2/MOSI/CSI_B
IO_L03P_2/DOUT/BUSY
IO_L04N_2
IO_L04P_2
IO_L06N_2
IO_L06P_2
IO_L07N_2
IO_L07P_2
IO_L09N_2/VREF_2
IO_L09P_2
IO_L10N_2
IO_L10P_2
IO_L11N_2
DUAL/
GCLK
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO_L23N_2/DIN/D0
IO_L23P_2/M0
IO_L25N_2
U12
V12
DUAL
DUAL
I/O
Y13
W5
IO_L25P_2
W13
U14
U13
T14
I/O
W6
IO_L26N_2/VREF_2
IO_L26P_2
VREF
I/O
V6
I/O
W7
I/O
IO_L27N_2
I/O
Y7
I/O
IO_L27P_2
R14
Y14
I/O
U7
I/O
IO_L28N_2
I/O
V7
I/O
IO_L28P_2
AA14
W14
V14
I/O
V8
VREF
I/O
IO_L29N_2
I/O
W8
IO_L29P_2
I/O
T8
I/O
IO_L30N_2
AB15
AA15
I/O
U8
I/O
IO_L30P_2
I/O
AB8
I/O
DS312-4 (v1.1) March 21, 2005
www.xilinx.com
65
Advance Product Specification
R
Pinout Descriptions
Table 31: FG484 Package Pinout
Table 31: FG484 Package Pinout
XC3S1600E
Pin Name
FG484
Ball
XC3S1600E
Pin Name
FG484
Ball
Bank
2
Type
I/O
Bank
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Type
INPUT
INPUT
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
I/O
IO_L32N_2
W15
Y15
U16
V16
AB17
AA17
W17
Y17
Y18
W18
AA20
AB20
W19
Y19
V17
AB2
AA4
Y4
IP_L37N_2
AA19
AB19
T12
U9
2
IO_L32P_2
I/O
IP_L37P_2
VCCO_2
2
IO_L33N_2
I/O
2
IO_L33P_2
I/O
VCCO_2
2
IO_L35N_2/A22
IO_L35P_2/A23
IO_L36N_2
DUAL
DUAL
I/O
VCCO_2
V15
AA5
AA9
AA13
AA18
C1
2
VCCO_2
2
VCCO_2
2
IO_L36P_2
I/O
VCCO_2
2
IO_L38N_2/A20
IO_L38P_2/A21
IO_L39N_2/VS1/A18
IO_L39P_2/VS2/A19
IO_L40N_2/CCLK
IO_L40P_2/VS0/A17
IP
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VREF
INPUT
VCCO_2
2
IO_L01N_3
IO_L01P_3
IO_L02N_3/VREF_3
IO_L02P_3
IO_L03N_3
IO_L03P_3
IO_L04N_3
IO_L04P_3
IO_L05N_3
IO_L05P_3
IO_L06N_3
IO_L06P_3
IO_L07N_3
IO_L07P_3
IO_L08N_3/VREF_3
IO_L08P_3
IO_L09N_3
IO_L09P_3
IO_L10N_3
IO_L10P_3
IO_L11N_3
IO_L11P_3
IO_L12N_3
IO_L12P_3
IO_L13N_3/VREF_3
IO_L13P_3
2
C2
I/O
2
D2
VREF
I/O
2
D3
2
E3
I/O
2
E4
I/O
2
IP
E1
I/O
2
IP_L02N_2
D1
I/O
2
IP_L02P_2
F4
I/O
2
IP_L05N_2
Y6
F3
I/O
2
IP_L05P_2
AA6
AB7
AB6
Y10
W10
AA11
Y11
P12
G5
G4
F1
I/O
2
IP_L08N_2
I/O
2
IP_L08P_2
I/O
2
IP_L15N_2
G1
G6
G7
H4
I/O
2
IP_L15P_2
VREF
I/O
2
IP_L18N_2/VREF_2
IP_L18P_2
2
I/O
2
IP_L21N_2/M2/GCLK1
DUAL/
GCLK
H5
I/O
H2
I/O
2
IP_L21P_2/RDWR_B/
GCLK0
R12
DUAL/
GCLK
H3
I/O
H1
I/O
2
2
2
2
2
2
IP_L24N_2
R13
T13
T15
U15
Y16
W16
INPUT
INPUT
VREF
J1
I/O
IP_L24P_2
J6
I/O
IP_L31N_2/VREF_2
IP_L31P_2
J5
I/O
INPUT
INPUT
INPUT
J3
VREF
I/O
IP_L34N_2
K3
IP_L34P_2
66
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
FG484
Table 31: FG484 Package Pinout
Table 31: FG484 Package Pinout
XC3S1600E
FG484
Ball
XC3S1600E
Bank
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Name
Type
I/O
Bank
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Name
Ball
U1
T4
Type
IO_L14N_3
J8
K8
K4
K5
K1
L1
IO_L31P_3
I/O
IO_L14P_3
I/O
IO_L32N_3
I/O
IO_L15N_3
I/O
IO_L32P_3
T5
I/O
IO_L15P_3
I/O
IO_L33N_3
W1
V1
U4
U3
V4
V3
W3
W2
Y2
Y1
AA1
AA2
F2
I/O
IO_L16N_3
I/O
IO_L33P_3
I/O
IO_L16P_3
I/O
IO_L34N_3
I/O
IO_L17N_3
L7
I/O
IO_L34P_3
I/O
IO_L17P_3
K7
L5
I/O
IO_L35N_3
I/O
IO_L18N_3/LHCLK1
IO_L18P_3/LHCLK0
IO_L19N_3/LHCLK3/IRDY2
IO_L19P_3/LHCLK2
IO_L20N_3/LHCLK5
IO_L20P_3/LHCLK4/TRDY2
IO_L21N_3/LHCLK7
IO_L21P_3/LHCLK6
IO_L22N_3
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
I/O
IO_L35P_3
I/O
M5
M8
L8
IO_L36N_3/VREF_3
VREF
I/O
IO_L36P_3
IO_L37N_3
I/O
N1
M1
M4
M3
N6
N7
P8
N8
N4
N5
P2
P1
R7
P7
P6
P5
R2
R1
R3
R4
T6
R6
U2
IO_L37P_3
I/O
IO_L38N_3
I/O
IO_L38P_3
I/O
IP
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VREF
VREF
VCCO
VCCO
IP
F5
IO_L22P_3
I/O
IP
G3
H7
J7
IO_L23N_3
I/O
IP
IO_L23P_3
I/O
IP
IO_L24N_3/VREF_3
IO_L24P_3
VREF
I/O
IP
K2
K6
M2
M6
N3
P3
R8
T1
IP
IO_L25N_3
I/O
IP
IO_L25P_3
I/O
IP
IO_L26N_3
I/O
IP
IO_L26P_3
I/O
IP
IO_L27N_3
I/O
IP
IO_L27P_3
I/O
IP
IO_L28N_3
I/O
IP
T7
IO_L28P_3
I/O
IP
U5
W4
L3
IO_L29N_3
I/O
IP
IO_L29P_3
I/O
IP/VREF_3
IP/VREF_3
VCCO_3
VCCO_3
IO_L30N_3
I/O
T3
IO_L30P_3
I/O
E2
H6
IO_L31N_3
I/O
DS312-4 (v1.1) March 21, 2005
www.xilinx.com
67
Advance Product Specification
R
Pinout Descriptions
Table 31: FG484 Package Pinout
Table 31: FG484 Package Pinout
XC3S1600E
Pin Name
FG484
Ball
XC3S1600E
Pin Name
FG484
Ball
Bank
3
Type
VCCO
VCCO
VCCO
VCCO
VCCO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Bank
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Type
GND
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
GND
J2
M7
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
P4
P9
3
GND
3
N2
P11
P14
P19
T2
GND
3
R5
GND
3
V2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A1
GND
GND
A11
A22
B7
T21
U6
GND
GND
GND
GND
U17
V10
V13
Y3
GND
GND
B16
C3
GND
GND
GND
GND
C20
E10
E13
F6
GND
GND
Y20
AA7
AA16
AB1
AB12
AB22
AA21
B1
GND
GND
GND
GND
GND
GND
F17
G2
GND
GND
GND
GND
G21
J4
GND
GND
VCCAUX DONE
VCCAUX PROG_B
VCCAUX TCK
CONFIG
CONFIG
JTAG
GND
J9
GND
J12
J14
J19
K10
K12
L2
E17
B2
GND
VCCAUX TDI
JTAG
GND
VCCAUX TDO
B20
D19
D12
E5
JTAG
GND
VCCAUX TMS
JTAG
GND
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCINT VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
GND
GND
L6
E18
K14
L4
GND
L9
GND
L13
M10
M14
M17
M21
N11
N13
GND
M19
N9
GND
GND
V5
GND
V18
W11
J10
GND
GND
68
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
FG484
Table 31: FG484 Package Pinout
Table 31: FG484 Package Pinout
XC3S1600E
FG484
Ball
XC3S1600E
Bank
Pin Name
Type
Bank
Pin Name
Ball
M13
N10
N12
N14
P13
Type
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
K9
K11
K13
L10
L11
L12
L14
M9
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
User I/Os by Bank
Table 32 indicates how the 304 available user-I/O pins are
distributed between the four I/O banks on the FG484 pack-
age.
M11
M12
Table 32: User I/Os Per Bank for the XC3S1600E in the FG484 Package
All Possible I/O Pins by Type
Package
Edge
Maximum
I/O
I/O Bank
I/O
56
INPUT
DUAL
1
VREF
GCLK
Top
0
1
2
3
94
94
22
16
18
16
72
7
7
8
0
Right
50
21
24
0
Bottom
Left
94
45
7
0
94
63
7
8
TOTAL
376
214
46
28
16
Footprint Migration Differences
The XC3S1600E FPGA is the only Spartan-3E device
offered in the FG484 package.
DS312-4 (v1.1) March 21, 2005
www.xilinx.com
69
Advance Product Specification
R
Pinout Descriptions
FG484 Footprint
Bank 0
1
2
3
4
5
6
7
8
9
10
11
Left Half of Package
(top view)
INPUT INPUT
L37P_0
I/O
L35N_0
I/O
L35P_0
I/O
L33N_0
I/O
L33P_0
I/O
L30P_0
I/O
L24N_0
I/O
L24P_0
GND
GND
A
B
C
D
E
F
L37N_0
I/O
L21N_0
GCLK11
I/O
L39P_0
I/O
L39N_0
I/O
L30N_0
I/O
L28P_0
PROG_B
VCCO_0
VCCO_0
TDI
I/O
GND
I/O: Unrestricted,
214
I/O
L21P_0
GCLK10
I/O
L01N_3
I/O
L01P_3
I/O
L40P_0
INPUT INPUT INPUT
L34P_0
I/O
L28N_0
I/O
L25P_0
general-purpose user I/O
GND
I/O
L34N_0
L31N_0
INPUT: User I/O or
I/O
L02N_3
VREF_3
I/O
L40N_0
HSWAP
I/O
L38N_0
VREF_0
I/O
L25N_0
VREF_0
I/O
L04P_3
I/O
L02P_3
I/O
L38P_0
I/O
L36P_0
INPUT
L31P_0
I/O
L29P_0
I/O
L22N_0
reference resistor input for
bank
72
I/O
L04N_3
I/O
L03N_3
I/O
L03P_3
I/O
L36N_0
I/O
L29N_0
I/O
L22P_0
VCCO_3
INPUT
GND
VCCAUX
VCCO_0
INPUT
GND
GND
DUAL: Configuration pin,
then possible user I/O
46
28
16
2
I/O
L32N_0
VREF_0
I/O
L07N_3
I/O
L05P_3
I/O
L05N_3
I/O
L32P_0
INPUT INPUT
L23N_0
INPUT
I/O
L23P_0
VREF: User I/O or input
voltage reference for bank
I/O
L08N_3
VREF_3
I/O
L07P_3
I/O
L06P_3
I/O
L06N_3
I/O
L08P_3
INPUT INPUT
L26N_0
VCCO_0
INPUT
I/O
G
H
J
L26P_0
GCLK: User I/O, input, or
clock buffer input
INPUT
L20N_0
GCLK9
I/O
L11N_3
I/O
L10N_3
I/O
L10P_3
I/O
L09N_3
I/O
L09P_3
I/O
L27N_0
I/O
L27P_0
VCCO_3
INPUT
INPUT
I/O
CONFIG: Dedicated
configuration pins
I/O
L13N_3
VREF_3
I/O
L11P_3
I/O
L12P_3
I/O
L12N_3
I/O
L14N_3
VCCO_3
INPUT
GND
GND
GND VCCINT
I/O
JTAG: Dedicated JTAG
port pins
4
I/O
L16N_3
I/O
L13P_3
I/O
L15N_3
I/O
L15P_3
I/O
L17P_3
I/O
L14P_3
INPUT
GND
VCCINT GND VCCINT
GND VCCINT VCCINT
VCCINT GND VCCINT
K
L
GND: Ground
I/O
L18N_3
LHCLK1
I/O
L19P_3
LHCLK2
48
28
16
10
0
I/O
L16P_3
INPUT
VREF_3
I/O
L17N_3
VCCAUX
I/O
L20P_3
LHCLK4
TRDY2
I/O
L19N_3
LHCLK3
IRDY2
I/O
L21P_3
I/O
L21N_3
I/O
L18P_3
VCCO: Output voltage
supply for bank
VCCO_3
INPUT
VCCO_3
INPUT
M
N
P
R
T
LHCLK6 LHCLK7 LHCLK0
I/O
L20N_3
LHCLK5
I/O
I/O
VCCINT: Internal core
supply voltage (+1.2V)
I/O
L22N_3
I/O
L22P_3
I/O
L23P_3
VCCAUX
INPUT
INPUT
VCCINT GND
L24N_3
VREF_3
L24P_3
I/O
L25P_3
I/O
L25N_3
I/O
L27P_3
I/O
L27N_3
I/O
L26P_3
I/O
L23N_3
I/O
VCCAUX: Auxiliary supply
voltage (+2.5V)
GND
GND
GND
L17P_2
I/O
I/O
L13N_2
VREF_2
I/O
L28P_3
I/O
L28N_3
I/O
L29N_3
I/O
L29P_3
I/O
L30P_3
I/O
L26N_3
I/O
L17N_2
L20P_2
VCCO_3
INPUT
N.C.: Not connected
D4
GCLK14
I/O
INPUT
VREF_3
I/O
L32N_3
I/O
L32P_3
I/O
L30N_3
I/O
L10N_2
I/O
L13P_2
I/O
L16P_2
L20N_2
D3
INPUT
GND
INPUT
GCLK15
I/O
I/O
L31P_3
I/O
L31N_3
I/O
L34P_3
I/O
L34N_3
I/O
L07N_2
I/O
L10P_2
I/O
L16N_2
L19N_2
D6
VCCO_2
INPUT
GND
U
V
W
Y
GCLK13
I/O
I/O
L09N_2
VREF_2
I/O
L33P_3
I/O
L35P_3
I/O
L35N_3
I/O
L04P_2
I/O
L07P_2
I/O
L12P_2
L19P_2
D7
VCCO_3
VCCAUX
GND
GCLK12
I/O
L03P_2
DOUT
BUSY
I/O
L36N_3
VREF_3
I/O
L33N_3
I/O
L36P_3
I/O
L04N_2
I/O
L06N_2
I/O
L09P_2
I/O
L12N_2
INPUT
L15P_2
VCCAUX
INPUT
I/O
I/O
L37P_3
I/O
L37N_3
INPUT
L02P_2
INPUT
L05N_2
I/O
L06P_2
INPUT INPUT
L03N_2
MOSI
GND
I/O
I/O
L15N_2
L18P_2
CSI_B
I/O
L01P_2
CSO_B
INPUT
L18N_2
VREF_2
A
A
I/O
L38N_3
I/O
L38P_3
INPUT
L02N_2
INPUT
L05P_2
I/O
L11P_2
VCCO_2
VCCO_2
GND
I/O
I/O
L01N_2
INIT_B
A
B
I/O
VREF_2
INPUT INPUT
I/O
L11N_2
I/O
L14N_2
I/O
L14P_2
I/O
D5
GND
INPUT
I/O
L08P_2
L08N_2
Bank 2
DS312_10_031105
Figure 10: FG484 Package Footprint (top view)
70
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
Bank 0
12
13
14
15
16
17
18
19
20
21
22
Right Half of Package
(top view)
I/O
L12N_0
VREF_0
I/O
L03N_0
VREF_0
INPUT INPUT
L17N_0
I/O
L12P_0
I/O
L07N_0
I/O
L07P_0
I/O
L04P_0
I/O
L04N_0
I/O
L03P_0
GND
A
B
C
D
E
F
L17P_0
I/O
L19P_0
GCLK6
I/O
L09N_0
VREF_0
I/O
L38N_1
LDC2
I/O
L38P_1
LDC1
INPUT
L05P_0
VCCO_0
VCCO_0
I/O
GND
INPUT
TDO
GND
I/O
L19N_0
GCLK7
I/O
L37N_1
LDC0
I/O
L37P_1
HDC
INPUT
L14P_0
I/O
L09P_0
I/O
L06N_0
INPUT
L05N_0
I/O
L01N_0
I/O
L01P_0
I/O
INPUT
L14N_0
I/O
L11N_0
INPUT
L08P_0
I/O
L06P_0
INPUT INPUT
L02N_0
INPUT
VREF_1
I/O
L34N_1
VCCAUX
TMS
INPUT
L02P_0
I/O
L18N_0
GCLK5
I/O
L11P_0
INPUT
L08N_0
I/O
L36P_1
I/O
L36N_1
I/O
L34P_1
VCCAUX
VCCO_1
INPUT
GND
GND
I/O
TCK
I/O
L18P_0
GCLK4
I/O
L15P_0
I/O
L10P_0
I/O
L35P_1
I/O
L35N_1
I/O
L32N_1
I/O
L31N_1
VCCO_0
I/O
GND
I/O
VREF_0
I/O
L15N_0
I/O
L13P_0
I/O
L10N_0
I/O
L30P_1
I/O
L33N_1
I/O
L33P_1
I/O
L32P_1
I/O
L31P_1
INPUT
INPUT
INPUT
G
H
J
INPUT
L20P_0
GCLK8
I/O
L28N_1
VREF_1
I/O
L16P_0
I/O
L13N_0
I/O
L30N_1
I/O
L29P_1
I/O
L29N_1
I/O
L28P_1
VCCO_1
I/O
I/O
L16N_0
I/O
L25P_1
I/O
L27N_1
I/O
L27P_1
I/O
L26N_1
I/O
L26P_1
GND
GND
GND
INPUT
I/O
L23N_1
A0
I/O
L22N_1
A1
I/O
L25N_1
I/O
L23P_1
I/O
L24P_1
I/O
L24N_1
VCCAUX
VCCO_1
GND VCCINT
INPUT
K
L
I/O
L20P_1
A6
I/O
L21P_1
A4
I/O
L21N_1
A3
I/O
I/O
L22P_1
A2
INPUT
VREF_1
L20N_1
A5
VCCO_1
VCCINT GND VCCINT INPUT
I/O
RHCLK4
RHCLK6 RHCLK7
RHCLK5
IRDY1
I/O
I/O
I/O
L17N_1
VREF_1
L19N_1
L19P_1
L18N_1
A9
VCCAUX
VCCINT VCCINT GND
GND
INPUT
GND
INPUT
VCCO_1
A7
M
N
P
R
T
A8
RHCLK3
RHCLK2
RHCLK1
TRDY1
I/O
I/O
L16N_1
A11
I/O
L16P_1
A12
I/O
L15N_1
I/O
L15P_1
I/O
L17P_1
L18P_1
A10
VCCINT GND VCCINT INPUT
INPUT
RHCLK0
I/O
L12N_1
VREF_1
I/O
L21N_2
I/O
L14P_1
I/O
L12P_1
I/O
L13N_1
VCCINT GND
GND
INPUT
M2
GCLK1
L14N_1
INPUT
INPUT
I/O
L27P_2
I/O
L10N_1
I/O
L09P_1
I/O
L09N_1
I/O
L11P_1
I/O
L11N_1
I/O
L13P_1
L21P_2
VCCO_1
INPUT
GND
INPUT
RDWR_B L24N_2
GCLK0
INPUT
L31N_2
VREF_2
INPUT
VCCO_2
I/O
L27N_2
I/O
L10P_1
I/O
L06P_1
I/O
L06N_1
I/O
L08N_1
INPUT
GND
L24P_2
I/O
I/O
L26N_2
VREF_2
I/O
L07N_1
VREF_1
I/O
L26P_2
INPUT
L31P_2
I/O
L33N_2
I/O
L04N_1
I/O
L07P_1
I/O
L08P_1
L23N_2
INPUT
U
V
W
Y
DIN
D0
I/O
L23P_2
M0
I/O
L29P_2
I/O
L33P_2
I/O
L04P_1
I/O
L03P_1
I/O
L05N_1
VCCO_2
VCCAUX
VCCO_1
GND
INPUT
I/O
I/O
L38P_2
A21
I/O
L40N_2
CCLK
I/O
L03N_1
VREF_1
I/O
L02N_1
A13
I/O
L25P_2
I/O
L29N_2
I/O
L32N_2
INPUT
L34P_2
I/O
L36N_2
I/O
L05P_1
L22N_2
D1
GCLK3
I/O
I/O
I/O
L38N_2
A20
I/O
L02P_1
A14
I/O
L01N_1
A15
I/O
L25N_2
I/O
L28N_2
I/O
L32P_2
INPUT
L34N_2
I/O
L36P_2
L22P_2
D2
L40P_2
VS0
GND
I/O
L39N_2
VS1
A18
GCLK2
A17
I/O
L35P_2
A23
I/O
L01P_1
A16
A
A
I/O
M1
I/O
L28P_2
I/O
L30P_2
INPUT
L37N_2
VCCO_2
VCCO_2
GND
I/O
DONE
I/O
I/O
L35N_2
A22
A
B
I/O
L30N_2
INPUT
L37P_2
I/O
VREF_2
L39P_2
VS2
GND
I/O
I/O
I/O
GND
A19
Bank 2
DS312_11_031105
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
www.xilinx.com
71
R
Pinout Descriptions
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revision
03/01/05
03/21/05
Initial Xilinx release.
1.1
Added XC3S250E in the CP132 package to Table 6. Corrected number of differential I/O
pairs on CP132. Added pinout and footprint information for the CP132, FG400, and FG484
packages. Removed IRDY and TRDY pins from the VQ100, TQ144, and PQ208 packages.
The Spartan-3E Family Data Sheet
DS312-1, Spartan-3E FPGA Family: Introduction and Ordering Information (Module 1)
DS312-2, Spartan-3E FPGA Family: Functional Description (Module 2)
DS312-3, Spartan-3E FPGA Family: DC and Switching Characteristics (Module 3)
DS312-4, Spartan-3E FPGA Family: Pinout Descriptions (Module 4)
72
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification
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