XC3S250E-5VQ100CS1 [XILINX]
Field Programmable Gate Array, 657MHz, 5508-Cell, CMOS, PQFP100,;
| 型号： | XC3S250E-5VQ100CS1 |
| 厂家： | 
XILINX, INC |
| 描述： | Field Programmable Gate Array, 657MHz, 5508-Cell, CMOS, PQFP100, 时钟 栅 可编程逻辑 |
| 文件： | 总227页 (文件大小：6371K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1
Spartan-3E FPGA Family
Data Sheet
DS312 July 19, 2013
Product Specification
Module 1:
Introduction and Ordering Information
Module 3:
DC and Switching Characteristics
DS312 (v4.1) July 19, 2013
DS312 (v4.1) July 19, 2013
•
•
•
•
•
Introduction
•
DC Electrical Characteristics
Features
•
•
•
•
Absolute Maximum Ratings
Supply Voltage Specifications
Recommended Operating Conditions
DC Characteristics
Architectural Overview
Package Marking
Ordering Information
•
Switching Characteristics
Module 2:
•
•
•
•
•
•
I/O Timing
Functional Description
SLICE Timing
DS312 (v4.1) July 19, 2013
DCM Timing
•
Input/Output Blocks (IOBs)
Block RAM Timing
Multiplier Timing
Configuration and JTAG Timing
•
•
Overview
SelectIO™ Signal Standards
•
•
•
•
•
•
•
•
Configurable Logic Block (CLB)
Block RAM
Module 4:
Pinout Descriptions
DS312 (v4.1) July 19, 2013
Dedicated Multipliers
Digital Clock Manager (DCM)
Clock Network
•
•
•
•
Pin Descriptions
Package Overview
Pinout Tables
Configuration
Powering Spartan®-3E FPGAs
Production Stepping
Footprint Diagrams
© Copyright 2005–2013 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, Artix, Kintex, Zynq, Vivado, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
DS312 July 19, 2013
www.xilinx.com
Product Specification
1
8
Spartan-3E FPGA Family:
Introduction and Ordering Information
DS312 (v4.1) July 19, 2013
Product Specification
Introduction
•
LVCMOS, LVTTL, HSTL, and SSTL single-ended signal
standards
3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
622+ Mb/s data transfer rate per I/O
True LVDS, RSDS, mini-LVDS, differential HSTL/SSTL
differential I/O
Enhanced Double Data Rate (DDR) support
DDR SDRAM support up to 333 Mb/s
The Spartan®-3E family of Field-Programmable Gate
Arrays (FPGAs) is specifically designed to meet the needs
of high volume, cost-sensitive consumer electronic
applications. The five-member family offers densities
ranging from 100,000 to 1.6 million system gates, as shown
in Table 1.
•
•
•
•
•
The Spartan-3E family builds on the success of the earlier
Spartan-3 family by increasing the amount of logic per I/O,
significantly reducing the cost per logic cell. New features
improve system performance and reduce the cost of
configuration. These Spartan-3E FPGA enhancements,
combined with advanced 90 nm process technology, deliver
more functionality and bandwidth per dollar than was
previously possible, setting new standards in the
programmable logic industry.
•
Abundant, flexible logic resources
•
Densities up to 33,192 logic cells, including optional shift
register or distributed RAM support
Efficient wide multiplexers, wide logic
Fast look-ahead carry logic
Enhanced 18 x 18 multipliers with optional pipeline
IEEE 1149.1/1532 JTAG programming/debug port
•
•
•
•
•
•
Hierarchical SelectRAM™ memory architecture
•
•
Up to 648 Kbits of fast block RAM
Up to 231 Kbits of efficient distributed RAM
Because of their exceptionally low cost, Spartan-3E FPGAs
are ideally suited to a wide range of consumer electronics
applications, including broadband access, home
networking, display/projection, and digital television
equipment.
Up to eight Digital Clock Managers (DCMs)
•
•
•
•
Clock skew elimination (delay locked loop)
Frequency synthesis, multiplication, division
High-resolution phase shifting
Wide frequency range (5 MHz to over 300 MHz)
The Spartan-3E family is a superior alternative to mask
programmed ASICs. FPGAs avoid the high initial cost, the
lengthy development cycles, and the inherent inflexibility of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary, an impossibility with ASICs.
•
•
Eight global clocks plus eight additional clocks per each half
of device, plus abundant low-skew routing
Configuration interface to industry-standard PROMs
•
•
•
Low-cost, space-saving SPI serial Flash PROM
x8 or x8/x16 parallel NOR Flash PROM
Low-cost Xilinx® Platform Flash with JTAG
•
•
•
Complete Xilinx ISE® and WebPACK™ software
MicroBlaze™ and PicoBlaze embedded processor cores
Fully compliant 32-/64-bit 33 MHz PCI support (66 MHz in
some devices)
Low-cost QFP and BGA packaging options
Common footprints support easy density migration
Pb-free packaging options
Features
•
Very low cost, high-performance logic solution for
high-volume, consumer-oriented applications
•
•
•
•
•
•
Proven advanced 90-nanometer process technology
Multi-voltage, multi-standard SelectIO™ interface pins
XA Automotive version available
•
Up to 376 I/O pins or 156 differential signal pairs
Table 1: Summary of Spartan-3E FPGA Attributes
CLB Array
Block
RAM
Maximum
Differential
I/O Pairs
(One CLB = Four Slices)
System Equivalent
Gates Logic Cells
Distributed
RAM bits(1)
Dedicated
Multipliers
Maximum
User I/O
Device
DCMs
Total
Total
Slices
bits(1)
Rows Columns
CLBs
XC3S100E
XC3S250E
XC3S500E
XC3S1200E 1200K
XC3S1600E 1600K
Notes:
100K
250K
500K
2,160
5,508
10,476
19,512
33,192
22
34
46
60
76
16
26
34
46
58
240
612
1,164
2,168
3,688
960
15K
38K
73K
136K
231K
72K
4
2
4
4
8
8
108
172
232
304
376
40
68
92
124
156
2,448
4,656
8,672
14,752
216K
360K
504K
648K
12
20
28
36
1. By convention, one Kb is equivalent to 1,024 bits.
© Copyright 2005–2013 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, Artix, Kintex, Zynq, Vivado, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
DS312 (v4.1) July 19, 2013
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Product Specification
2
Spartan-3E FPGA Family: Introduction and Ordering Information
Architectural Overview
The Spartan-3E family architecture consists of five
fundamental programmable functional elements:
•
Digital Clock Manager (DCM) Blocks provide
self-calibrating, fully digital solutions for distributing,
delaying, multiplying, dividing, and phase-shifting clock
signals.
•
Configurable Logic Blocks (CLBs) contain flexible
Look-Up Tables (LUTs) that implement logic plus
storage elements used as flip-flops or latches. CLBs
perform a wide variety of logical functions as well as
store data.
These elements are organized as shown in Figure 1. A ring
of IOBs surrounds a regular array of CLBs. Each device has
two columns of block RAM except for the XC3S100E, which
has one column. Each RAM column consists of several
18-Kbit RAM blocks. Each block RAM is associated with a
dedicated multiplier. The DCMs are positioned in the center
with two at the top and two at the bottom of the device. The
XC3S100E has only one DCM at the top and bottom, while
the XC3S1200E and XC3S1600E add two DCMs in the
middle of the left and right sides.
•
Input/Output Blocks (IOBs) control the flow of data
between the I/O pins and the internal logic of the
device. Each IOB supports bidirectional data flow plus
3-state operation. Supports a variety of signal
standards, including four high-performance differential
standards. Double Data-Rate (DDR) registers are
included.
The Spartan-3E family features a rich network of traces that
interconnect all five functional elements, transmitting
signals among them. Each functional element has an
associated switch matrix that permits multiple connections
to the routing.
•
•
Block RAM provides data storage in the form of
18-Kbit dual-port blocks.
Multiplier Blocks accept two 18-bit binary numbers as
inputs and calculate the product.
X-Ref Target - Figure 1
Figure 1: Spartan-3E Family Architecture
DS312 (v4.1) July 19, 2013
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Product Specification
3
Spartan-3E FPGA Family: Introduction and Ordering Information
Configuration
I/O Capabilities
Spartan-3E FPGAs are programmed by loading
configuration data into robust, reprogrammable, static
The Spartan-3E FPGA SelectIO interface supports many
popular single-ended and differential standards. Table 2
CMOS configuration latches (CCLs) that collectively control
all functional elements and routing resources. The FPGA’s
configuration data is stored externally in a PROM or some
other non-volatile medium, either on or off the board. After
applying power, the configuration data is written to the
FPGA using any of seven different modes:
shows the number of user I/Os as well as the number of
differential I/O pairs available for each device/package
combination.
Spartan-3E FPGAs support the following single-ended
standards:
•
•
3.3V low-voltage TTL (LVTTL)
•
•
Master Serial from a Xilinx Platform Flash PROM
Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V,
1.5V, or 1.2V
Serial Peripheral Interface (SPI) from an
industry-standard SPI serial Flash
•
•
3V PCI at 33 MHz, and in some devices, 66 MHz
•
Byte Peripheral Interface (BPI) Up or Down from an
industry-standard x8 or x8/x16 parallel NOR Flash
HSTL I and III at 1.8V, commonly used in memory
applications
•
•
•
Slave Serial, typically downloaded from a processor
Slave Parallel, typically downloaded from a processor
•
SSTL I at 1.8V and 2.5V, commonly used for memory
applications
Boundary Scan (JTAG), typically downloaded from a
processor or system tester.
Spartan-3E FPGAs support the following differential
standards:
Furthermore, Spartan-3E FPGAs support MultiBoot
configuration, allowing two or more FPGA configuration
bitstreams to be stored in a single parallel NOR Flash. The
FPGA application controls which configuration to load next
and when to load it.
•
•
•
•
•
•
•
LVDS
Bus LVDS
mini-LVDS
RSDS
Differential HSTL (1.8V, Types I and III)
Differential SSTL (2.5V and 1.8V, Type I)
2.5V LVPECL inputs
Table 2: Available User I/Os and Differential (Diff) I/O Pairs
VQ100
VQG100
CP132
CPG132
TQ144
TQG144
PQ208
PQG208
FT256
FTG256
FG320
FGG320
FG400
FGG400
FG484
FGG484
Package
Footprint
Size (mm)
16 x 16
8 x 8
22 x 22
30.5 x 30.5
17 x 17
19 x 19
21 x 21
23 x 23
Device
User
Diff User Diff User Diff User Diff User Diff User Diff User Diff User Diff
66(2)
30
83
35
108
40
XC3S100E
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
9(7)
(2)
(11)
(2)
(28)
(4)
66
(7)
30
(2)
92
(7)
41
(2)
108
(28)
40
(4)
158
(32)
65
(5)
172
(40)
68
(8)
XC3S250E
XC3S500E
XC3S1200E
66(3)
(7)
30
(2)
92
(7)
41
(2)
158
(32)
65
(5)
190
(41)
77
(8)
232
(56)
92
(12)
-
-
-
-
-
-
190
(40)
77
(8)
250
(56)
99
(12)
304
(72)
124
(20)
-
-
-
-
-
-
-
-
-
-
-
-
250
(56)
99
(12)
304
(72)
124
(20)
376 156
(82) (21)
XC3S1600E
Notes:
-
-
1. All Spartan-3E devices provided in the same package are pin-compatible as further described in Module 4, Pinout Descriptions.
2. The number shown in bold indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the number
of input-only pins.
3. The XC3S500E is available in the VQG100 Pb-free package and not the standard VQ100. The VQG100 and VQ100 pin-outs are identical
and general references to the VQ100 will apply to the XC3S500E.
DS312 (v4.1) July 19, 2013
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Product Specification
4
Spartan-3E FPGA Family: Introduction and Ordering Information
Package Marking
Figure 2 provides a top marking example for Spartan-3E
FPGAs in the quad-flat packages. Figure 3 shows the top
marking for Spartan-3E FPGAs in BGA packages except
the 132-ball chip-scale package (CP132 and CPG132). The
markings for the BGA packages are nearly identical to those
for the quad-flat packages, except that the marking is
rotated with respect to the ball A1 indicator. Figure 4 shows
the top marking for Spartan-3E FPGAs in the CP132 and
CPG132 packages.
On the QFP and BGA packages, the optional numerical
Stepping Code follows the Lot Code.
The “5C” and “4I” part combinations can have a dual mark
of “5C/4I”. Devices with a single mark are only guaranteed
for the marked speed grade and temperature range. All “5C”
and “4I” part combinations use the Stepping 1 production
silicon.
X-Ref Target
-
Figure
2
Mask Revision Code
Fabrication Code
R
R
Process Technology
SPARTAN
Device Type
XC3S250ETM
Date Code
Package
PQ208AGQ0525
D1234567A
Stepping Code (optional)
Lot Code
Speed Grade
4C
Temperature Range
Pin P1
DS312-1_06_102905
Figure 2: Spartan-3E QFP Package Marking Example
X-Ref Target - Figure 3
Mask Revision Code
R
BGA Ball A1
Fabrication Code
Process Code
R
SPARTAN
Device Type
XC3S250ETM
FT256AGQ0525
D1234567A
4C
Date Code
Package
Stepping Code (optional)
Lot Code
Speed Grade
Temperature Range
DS312-1_02_090105
Figure 3: Spartan-3E BGA Package Marking Example
X-Ref Target - Figure 4
Ball A1
Device Type
3S250E
F1234567-0525
PHILIPPINES
Lot Code
Date Code
Temperature Range
Package
C5 = CP132
C6 = CPG132
C5AGQ
4C
Speed Grade
Process Code
Mask Revision Code
Fabrication Code
DS312-1_05_032105
Figure 4: Spartan-3E CP132 and CPG132 Package Marking Example
DS312 (v4.1) July 19, 2013
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Product Specification
5
Spartan-3E FPGA Family: Introduction and Ordering Information
Ordering Information
Spartan-3E FPGAs are available in both standard and
Pb-free packaging options for all device/package
temperature ranges. Both the standard –4 and faster –5
speed grades are available for the Commercial temperature
combinations. All devices are available in Pb-free packages,
which adds a ‘G’ character to the ordering code. All devices
are available in either Commercial (C) or Industrial (I)
range. However, only the –4 speed grade is available for the
Industrial temperature range. See Table 2 for valid
device/package combinations.
(optional code to specify Stepping 1)
Example: XC3S250E -4 FT 256 C S1
Device Type
Speed Grade
Package Type
Temperature Range
Number of Pins
DS312_03_082409
Device
Speed Grade
Package Type / Number of Pins
Temperature Range (TJ)
XC3S100E
-4 Standard Performance VQ100
VQG100
100-pin Very Thin Quad Flat Pack (VQFP)
C Commercial (0°C to 85°C)
XC3S250E
-5 High Performance(1)
CP132
CPG132
132-ball Chip-Scale Package (CSP)
I Industrial (–40°C to 100°C)
XC3S500E(2)
XC3S1200E
XC3S1600E
TQ144
TQG144
144-pin Thin Quad Flat Pack (TQFP)
PQ208
PQG208
208-pin Plastic Quad Flat Pack (PQFP)
256-ball Fine-Pitch Thin Ball Grid Array (FTBGA)
320-ball Fine-Pitch Ball Grid Array (FBGA)
400-ball Fine-Pitch Ball Grid Array (FBGA)
484-ball Fine-Pitch Ball Grid Array (FBGA)
FT256
FTG256
FG320
FGG320
FG400
FGG400
FG484
FGG484
Notes:
1. The -5 speed grade is exclusively available in the Commercial temperature range.
2. The XC3S500E VQG100 is available only in the -4 Speed Grade.
3. See DS635 for the XA Automotive Spartan-3E FPGAs.
Production Stepping
The Spartan-3E FPGA family uses production stepping to
indicate improved capabilities or enhanced features.
Table 3: Spartan-3E Optional Stepping Level Ordering
Stepping
Number
Suffix Code
Status
Stepping 1 is, by definition, a functional superset of
Stepping 0. Furthermore, configuration bitstreams
generated for any stepping are forward compatible. See
Table 72 for additional details.
0
1
None or S0
S1
Production
Production
The stepping level is optionally marked on the device using
a single number character, as shown in Figure 2, Figure 3,
and Figure 4.
Xilinx has shipped both Stepping 0 and Stepping 1. Designs
operating on the Stepping 0 devices perform similarly on a
Stepping 1 device. Stepping 1 devices have been shipping
since 2006. The faster speed grade (-5), Industrial (I grade),
Automotive devices, and -4C devices with date codes 0901
(2009) and later, are always Stepping 1 devices. Only -4C
devices have shipped as Stepping 0 devices.
To specify only the later stepping for the -4C, append an S#
suffix to the standard ordering code, where # is the stepping
number, as indicated in Table 3.
DS312 (v4.1) July 19, 2013
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Product Specification
6
Spartan-3E FPGA Family: Introduction and Ordering Information
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revision
03/01/2005
03/21/2005
Initial Xilinx release.
1.1
Added XC3S250E in CP132 package to Table 2. Corrected number of differential I/O pairs for CP132
package. Added package markings for QFP packages (Figure 2) and CP132/CPG132 packages
(Figure 4).
11/23/2005
03/22/2006
2.0
3.0
Added differential HSTL and SSTL I/O standards. Updated Table 2 to indicate number of input-only
pins. Added Production Stepping information, including example top marking diagrams.
Upgraded data sheet status to Preliminary. Added XC3S100E in CP132 package and updated I/O
counts for the XC3S1600E in FG320 package (Table 2). Added information about dual markings for
–5C and –4I product combinations to Package Marking.
11/09/2006
3.4
Added 66 MHz PCI support and links to the Xilinx PCI LogiCORE data sheet. Indicated that Stepping
1 parts are Production status. Promoted Module 1 to Production status. Synchronized all modules to
v3.4.
04/18/2008
08/26/2009
3.7
3.8
Added XC3S500E VQG100 package. Added reference to XA Automotive version. Updated links.
Added paragraph to Configuration indicating the device supports MultiBoot configuration. Added
package sizes to Table 2. Described the speed grade and temperature range guarantee for devices
having a single mark in paragraph 3 under Package Marking. Deleted Pb-Free Packaging example
under Ordering Information. Revised information under Production Stepping. Revised description of
Table 3.
10/29/2012
07/19/2013
4.0
4.1
Added Notice of Disclaimer. This product is not recommended for new designs.
Updated Table 2 footprint size of PQ208.
Removed banner. This product IS recommended for new designs.
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED
WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE
SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
CRITICAL APPLICATIONS DISCLAIMER
XILINX PRODUCTS (INCLUDING HARDWARE, SOFTWARE AND/OR IP CORES) ARE NOT DESIGNED OR INTENDED TO BE
FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS IN LIFE-SUPPORT OR
SAFETY DEVICES OR SYSTEMS, CLASS III MEDICAL DEVICES, NUCLEAR FACILITIES, APPLICATIONS RELATED TO THE
DEPLOYMENT OF AIRBAGS, OR ANY OTHER APPLICATIONS THAT COULD LEAD TO DEATH, PERSONAL INJURY OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE (INDIVIDUALLY AND COLLECTIVELY, “CRITICAL APPLICATIONS”). FURTHERMORE,
XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN ANY APPLICATIONS THAT AFFECT CONTROL OF A
VEHICLE OR AIRCRAFT, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF
SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE
OPERATOR. CUSTOMER AGREES, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE XILINX
PRODUCTS, TO THOROUGHLY TEST THE SAME FOR SAFETY PURPOSES. TO THE MAXIMUM EXTENT PERMITTED BY
APPLICABLE LAW, CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN CRITICAL
APPLICATIONS.
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Product Specification
7
Spartan-3E FPGA Family: Introduction and Ordering Information
AUTOMOTIVE APPLICATIONS DISCLAIMER
XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING
FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A
VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN
THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III)
USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY
USE OF XILINX PRODUCTS IN SUCH APPLICATIONS.
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Product Specification
8
114
Spartan-3E FPGA Family:
Functional Description
DS312 (v4.1) July 19, 2013
Product Specification
Design Documentation Available
Xilinx Alerts
The functionality of the Spartan®-3E FPGA family is now
described and updated in the following documents. The
topics covered in each guide are listed below.
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•
UG331: Spartan-3 Generation FPGA User Guide
•
•
•
•
Clocking Resources
Digital Clock Managers (DCMs)
Block RAM
Spartan-3E FPGA Starter Kit
Configurable Logic Blocks (CLBs)
For specific hardware examples, please see the Spartan-3E
FPGA Starter Kit board web page, which has links to
various design examples and the user guide.
-
-
-
Distributed RAM
SRL16 Shift Registers
Carry and Arithmetic Logic
•
Spartan-3E FPGA Starter Kit Board page
http://www.xilinx.com/s3estarter
•
•
•
•
•
•
•
•
•
•
I/O Resources
Embedded Multiplier Blocks
Programmable Interconnect
ISE® Design Tools
•
UG230: Spartan-3E FPGA Starter Kit User Guide
IP Cores
Embedded Processing and Control Solutions
Pin Types and Package Overview
Package Drawings
Powering FPGAs
Power Management
•
UG332: Spartan-3 Generation Configuration User
Guide
•
Configuration Overview
-
-
Configuration Pins and Behavior
Bitstream Sizes
•
Detailed Descriptions by Mode
-
-
-
Master Serial Mode using Xilinx® Platform
Flash PROM
Master SPI Mode using Commodity SPI Serial
Flash PROM
Master BPI Mode using Commodity Parallel
NOR Flash PROM
-
-
-
Slave Parallel (SelectMAP) using a Processor
Slave Serial using a Processor
JTAG Mode
•
•
ISE iMPACT Programming Examples
MultiBoot Reconfiguration
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Product Specification
9
Spartan-3E FPGA Family: Functional Description
pair of storage elements to the IQ1 and IQ2 lines. The
IOB outputs I, IQ1, and IQ2 lead to the FPGA’s internal
logic. The delay element can be set to ensure a hold
time of zero (see Input Delay Functions).
Introduction
As described in Architectural Overview, the Spartan-3E
FPGA architecture consists of five fundamental functional
elements:
•
•
The output path, starting with the O1 and O2 lines,
carries data from the FPGA’s internal logic through a
multiplexer and then a three-state driver to the IOB
pad. In addition to this direct path, the multiplexer
provides the option to insert a pair of storage elements.
•
•
•
•
•
Input/Output Blocks (IOBs)
Configurable Logic Block (CLB) and Slice Resources
Block RAM
Dedicated Multipliers
The 3-state path determines when the output driver is
high impedance. The T1 and T2 lines carry data from
the FPGA’s internal logic through a multiplexer to the
output driver. In addition to this direct path, the
multiplexer provides the option to insert a pair of
storage elements.
Digital Clock Managers (DCMs)
The following sections provide detailed information on each
of these functions. In addition, this section also describes
the following functions:
•
•
•
•
Clocking Infrastructure
Interconnect
•
All signal paths entering the IOB, including those
associated with the storage elements, have an inverter
option. Any inverter placed on these paths is
automatically absorbed into the IOB.
Configuration
Powering Spartan-3E FPGAs
Input/Output Blocks (IOBs)
For additional information, refer to the “Using I/O
Resources” chapter in UG331.
IOB Overview
The Input/Output Block (IOB) provides a programmable,
unidirectional or bidirectional interface between a package
pin and the FPGA’s internal logic. The IOB is similar to that
of the Spartan-3 family with the following differences:
•
•
•
Input-only blocks are added
Programmable input delays are added to all blocks
DDR flip-flops can be shared between adjacent IOBs
The unidirectional input-only block has a subset of the full
IOB capabilities. Thus there are no connections or logic for
an output path. The following paragraphs assume that any
reference to output functionality does not apply to the
input-only blocks. The number of input-only blocks varies
with device size, but is never more than 25% of the total IOB
count.
Figure 5 is a simplified diagram of the IOB’s internal
structure. There are three main signal paths within the IOB:
the output path, input path, and 3-state path. Each path has
its own pair of storage elements that can act as either
registers or latches. For more information, see Storage
Element Functions. The three main signal paths are as
follows:
•
The input path carries data from the pad, which is
bonded to a package pin, through an optional
programmable delay element directly to the I line. After
the delay element, there are alternate routes through a
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Product Specification
10
Spartan-3E FPGA Family: Functional Description
X-Ref Target - Figure 5
T
TFF1
D
T1
Q
CE
CK
SR REV
DDR
MUX
TCE
T2
D
Q
TFF2
CE
CK
SR REV
Three-state Path
V
CCO
OFF1
D
O1
Q
CE
CK
OTCLK1
Pull-Up
ESD
ESD
SR REV
DDR
MUX
I/O
Pin
OCE
O2
Program-
mable
Output
Driver
Pull-
Down
Q
D
OFF2
CE
CK
OTCLK2
SR REV
Keeper
Latch
Output Path
Programmable
Delay
I
LVCMOS, LVTTL, PCI
IQ1
Programmable
Delay
Single-ended Standards
using V
REF
D
IDDRIN1
IDDRIN2
Q
V
REF
IFF1
CE
CK
Pin
ICLK1
ICE
SR REV
Differential Standards
I/O Pin
from
Adjacent
IOB
IQ2
D
Q
IFF2
CE
CK
ICLK2
SR REV
SR
REV
Input Path
DS312-2_19_110606
Figure 5: Simplified IOB Diagram
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Product Specification
11
Spartan-3E FPGA Family: Functional Description
Input Delay Functions
Each IOB has a programmable delay block that optionally
delays the input signal. In Figure 6, the signal path has a
coarse delay element that can be bypassed. The input
signal then feeds a 6-tap delay line. The coarse and tap
delays vary; refer to timing reports for specific delay values.
All six taps are available via a multiplexer for use as an
asynchronous input directly into the FPGA fabric. In this
way, the delay is programmable in 12 steps. Three of the six
taps are also available via a multiplexer to the D inputs of
the synchronous storage elements. The delay inserted in
the path to the storage element can be varied in six steps.
The first, coarse delay element is common to both
asynchronous and synchronous paths, and must be either
used or not used for both paths.
report generated by the implementation tools, and the
resulting effects on input timing are reported using the
Timing Analyzer tool.
If the design uses a DCM in the clock path, then the delay
element can be safely set to zero because the
Delay-Locked Loop (DLL) compensation automatically
ensures that there is still no input hold time requirement.
Both asynchronous and synchronous values can be
modified, which is useful where extra delay is required on
clock or data inputs, for example, in interfaces to various
types of RAM.
These delay values are defined through the
IBUF_DELAY_VALUE and the IFD_DELAY_VALUE
parameters. The default IBUF_DELAY_VALUE is 0,
bypassing the delay elements for the asynchronous input.
The user can set this parameter to 0-12. The default
IFD_DELAY_VALUE is AUTO. IBUF_DELAY_VALUE and
IFD_DELAY_VALUE are independent for each input. If the
same input pin uses both registered and non-registered
input paths, both parameters can be used, but they must
both be in the same half of the total delay (both either
bypassing or using the coarse delay element).
The delay values are set up in the silicon once at
configuration time—they are non-modifiable in device
operation.
The primary use for the input delay element is to adjust the
input delay path to ensure that there is no hold time
requirement when using the input flip-flop(s) with a global
clock. The default value is chosen automatically by the
Xilinx software tools as the value depends on device size
and the specific device edge where the flip-flop resides. The
value set by the Xilinx ISE software is indicated in the Map
X-Ref Target - Figure 6
IFD_DELAY_VALUE
Synchronous input (IQ1)
D Q
Synchronous input (IQ2)
D Q
Coarse Delay
PAD
Asynchronous input (I)
IBUF_DELAY_VALUE
UG331_c10_09_011508
Figure 6: Programmable Fixed Input Delay Elements
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Product Specification
12
Spartan-3E FPGA Family: Functional Description
Storage Element Functions
There are three pairs of storage elements in each IOB, one
pair for each of the three paths. It is possible to configure
each of these storage elements as an edge-triggered
D-type flip-flop (FD) or a level-sensitive latch (LD).
synchronized to the clock signal’s rising edge and
converting it to bits synchronized on both the rising and the
falling edge. The combination of two registers and a
multiplexer is referred to as a Double-Data-Rate D-type
flip-flop (ODDR2).
The storage-element pair on either the Output path or the
Three-State path can be used together with a special
multiplexer to produce Double-Data-Rate (DDR)
transmission. This is accomplished by taking data
Table 4 describes the signal paths associated with the
storage element.
Table 4: Storage Element Signal Description
Storage
Element
Signal
Description
Data input
Function
D
Data at this input is stored on the active edge of CK and enabled by CE. For latch operation when
the input is enabled, data passes directly to the output Q.
Q
Data output
The data on this output reflects the state of the storage element. For operation as a latch in
transparent mode, Q mirrors the data at D.
CK
CE
SR
Clock input
Data is loaded into the storage element on this input’s active edge with CE asserted.
When asserted, this input enables CK. If not connected, CE defaults to the asserted state.
Clock Enable input
Set/Reset input
This input forces the storage element into the state specified by the SRHIGH/SRLOW attributes.
The SYNC/ASYNC attribute setting determines if the SR input is synchronized to the clock or not.
If both SR and REV are active at the same time, the storage element gets a value of 0.
REV
Reverse input
This input is used together with SR. It forces the storage element into the state opposite from what
SR does. The SYNC/ASYNC attribute setting determines whether the REV input is synchronized
to the clock or not. If both SR and REV are active at the same time, the storage element gets a
value of 0.
As shown in Figure 5, the upper registers in both the output
and three-state paths share a common clock. The OTCLK1
clock signal drives the CK clock inputs of the upper registers
on the output and three-state paths. Similarly, OTCLK2
drives the CK inputs for the lower registers on the output
and three-state paths. The upper and lower registers on the
input path have independent clock lines: ICLK1 and ICLK2.
controls the CE inputs for the register pair on the three-state
path and ICE does the same for the register pair on the
input path.
The Set/Reset (SR) line entering the IOB controls all six
registers, as is the Reverse (REV) line.
In addition to the signal polarity controls described in IOB
Overview, each storage element additionally supports the
controls described in Table 5.
The OCE enable line controls the CE inputs of the upper
and lower registers on the output path. Similarly, TCE
Table 5: Storage Element Options
Option Switch
FF/Latch
Function
Specificity
Chooses between an edge-triggered flip-flop or a
level-sensitive latch
Independent for each storage element
SYNC/ASYNC
Determines whether the SR set/reset control is
synchronous or asynchronous
Independent for each storage element
SRHIGH/SRLOW
Determines whether SR acts as a Set, which forces Independent for each storage element, except when using
the storage element to a logic 1 (SRHIGH) or a
Reset, which forces a logic 0 (SRLOW)
ODDR2. In the latter case, the selection for the upper
element will apply to both elements.
INIT1/INIT0
When Global Set/Reset (GSR) is asserted or after
configuration this option specifies the initial state of ODDR2, which uses two IOBs. In the ODDR2 case,
Independent for each storage element, except when using
the storage element, either set (INIT1) or reset
(INIT0). By default, choosing SRLOW also selects
INIT0; choosing SRHIGH also selects INIT1.
selecting INIT0 for one IOBs applies to both elements
within the IOB, although INIT1 could be selected for the
elements in the other IOB.
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Spartan-3E FPGA Family: Functional Description
Double-Data-Rate Transmission
Double-Data-Rate (DDR) transmission describes the
technique of synchronizing signals to both the rising and
falling edges of the clock signal. Spartan-3E devices use
register pairs in all three IOB paths to perform DDR
operations.
The storage-element pair on the Three-State path (TFF1
and TFF2) also can be combined with a local multiplexer to
form a DDR primitive. This permits synchronizing the output
enable to both the rising and falling edges of a clock. This
DDR operation is realized in the same way as for the output
path.
The pair of storage elements on the IOB’s Output path
(OFF1 and OFF2), used as registers, combine with a
special multiplexer to form a DDR D-type flip-flop (ODDR2).
This primitive permits DDR transmission where output data
bits are synchronized to both the rising and falling edges of
a clock. DDR operation requires two clock signals (usually
50% duty cycle), one the inverted form of the other. These
signals trigger the two registers in alternating fashion, as
shown in Figure 7. The Digital Clock Manager (DCM)
generates the two clock signals by mirroring an incoming
signal, and then shifting it 180 degrees. This approach
ensures minimal skew between the two signals.
The storage-element pair on the input path (IFF1 and IFF2)
allows an I/O to receive a DDR signal. An incoming DDR
clock signal triggers one register, and the inverted clock
signal triggers the other register. The registers take turns
capturing bits of the incoming DDR data signal. The
primitive to allow this functionality is called IDDR2.
Aside from high bandwidth data transfers, DDR outputs also
can be used to reproduce, or mirror, a clock signal on the
output. This approach is used to transmit clock and data
signals together (source synchronously). A similar
approach is used to reproduce a clock signal at multiple
outputs. The advantage for both approaches is that skew
across the outputs is minimal.
Alternatively, the inverter inside the IOB can be used to
invert the clock signal, thus only using one clock line and
both rising and falling edges of that clock line as the two
clocks for the DDR flip-flops.
X-Ref Target - Figure 7
DCM
DCM
0˚
180˚ 0˚
FDDR
FDDR
D1
D1
Q1
CLK1
Q1
CLK1
DDR MUX
DDR MUX
Q
Q
D2
D2
Q2
CLK2
Q2
CLK2
DS312-2_20_021105
Figure 7: Two Methods for Clocking the DDR Register
Register Cascade Feature
IDDR2
In the Spartan-3E family, one of the IOBs in a differential
pair can cascade its input storage elements with those in
the other IOB as part of a differential pair. This is intended to
make DDR operation at high speed much simpler to
implement. The new DDR connections that are available
are shown in Figure 5 (dashed lines), and are only available
for routing between IOBs and are not accessible to the
FPGA fabric. Note that this feature is only available when
using the differential I/O standards LVDS, RSDS, and
MINI_LVDS.
As a DDR input pair, the master IOB registers incoming
data on the rising edge of ICLK1 (= D1) and the rising edge
of ICLK2 (= D2), which is typically the same as the falling
edge of ICLK1. This data is then transferred into the FPGA
fabric. At some point, both signals must be brought into the
same clock domain, typically ICLK1. This can be difficult at
high frequencies because the available time is only one half
of a clock cycle assuming a 50% duty cycle. See Figure 8
for a graphical illustration of this function.
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Product Specification
14
Spartan-3E FPGA Family: Functional Description
X-Ref Target - Figure 8
and the rising edge of OCLK2 (= D2), which is typically the
same as the falling edge of OCLK1. These two bits of data
are multiplexed by the DDR mux and forwarded to the
output pin. The D2 data signal must be re-synchronized
from the OCLK1 clock domain to the OCLK2 domain using
FPGA slice flip-flops. Placement is critical at high
frequencies, because the time available is only one half a
clock cycle. See Figure 10 for a graphical illustration of this
function.
Q
Q
D
D
D1
PAD
To Fabric
D2
ICLK2
ICLK1
The C0 or C1 alignment feature of the ODDR2 flip-flop,
originally introduced in the Spartan-3E FPGA family, is not
recommended or supported in the ISE development
software. The ODDR2 flip-flop without the alignment feature
remains fully supported. Without the alignment feature, the
ODDR2 feature behaves equivalent to the ODDR flip-flop
on previous Xilinx FPGA families.
ICLK1
ICLK2
PAD
D1
d
d+1 d+2 d+3 d+4 d+5 d+6 d+7 d+8
d+2 d+4 d+6
d
d+8
d+7
X-Ref Target - Figure 10
D2 d-1
d+1
d+3
d+5
Q
D
D1
PAD
DS312-2_21_021105
From
Fabric
Figure 8: Input DDR (without Cascade Feature)
In the Spartan-3E device, the signal D2 can be cascaded
into the storage element of the adjacent slave IOB. There it
is re-registered to ICLK1, and only then fed to the FPGA
fabric where it is now already in the same time domain as
D1. Here, the FPGA fabric uses only the clock ICLK1 to
process the received data. See Figure 9 for a graphical
illustration of this function.
D2
Q
D
OCLK1
OCLK2
X-Ref Target - Figure 9
OCLK1
Q
D
D1
OCLK2
D1
PAD
d
d+2
d+4
d+6
d+8
d+10
d+9
To Fabric
D2
D2
d+1
d+3
d+5
d+7
d+5 d+6
IDDRIN2
IQ2
Q
D
Q
D
d+8
PAD
d+7
d
d+1 d+2 d+3 d+4
DS312-2_23_030105
Figure 10: Output DDR
ICLK1
ICLK2
SelectIO Signal Standards
The Spartan-3E I/Os feature inputs and outputs that
support a wide range of I/O signaling standards (Table 6
and Table 7). The majority of the I/Os also can be used to
form differential pairs to support any of the differential
signaling standards (Table 7).
ICLK1
ICLK2
d
d+1 d+2 d+3 d+4 d+5 d+6 d+7 d+8
PAD
D1
d
d+2
d+1
d+4
d+3
d+6
d+5
d+8
d+7
To define the I/O signaling standard in a design, set the
IOSTANDARD attribute to the appropriate setting. Xilinx
provides a variety of different methods for applying the
IOSTANDARD for maximum flexibility. For a full description
of different methods of applying attributes to control
IOSTANDARD, refer to the Xilinx Software Manuals and
Help.
D2
d-1
DS312-2_22_030105
Figure 9: Input DDR Using Spartan-3E Cascade Feature
ODDR2
As a DDR output pair, the master IOB registers data coming
from the FPGA fabric on the rising edge of OCLK1 (= D1)
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Product Specification
15
Spartan-3E FPGA Family: Functional Description
Spartan-3E FPGAs provide additional input flexibility by
allowing I/O standards to be mixed in different banks. For a
IOSTANDARDs that can be combined and if the
IOSTANDARD is supported as an input only or can be used
for both inputs and outputs.
particular V
voltage, Table 6 and Table 7 list all of the
CCO
Table 6: Single-Ended IOSTANDARD Bank Compatibility
VCCO Supply/Compatibility
Input Requirements
Board
Single-Ended
IOSTANDARD
1.2V
1.5V
1.8V
2.5V
3.3V
VREF
Termination
Voltage (VTT
)
Input/
Output
LVTTL
-
-
-
-
-
-
-
-
-
-
-
-
-
-
N/R(1)
N/R
N/R
N/R
N/R
N/R
N/R
N/R
0.9
N/R
Input/
Output
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI33_3
N/R
N/R
N/R
N/R
N/R
N/R
N/R
0.9
Input/
Output
Input
Input
Input
Input
Input/
Output
Input
Input
Input
-
Input/
Output
Input
Input/
Output
Input
Input
Input/
Output
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Input/
Output
PCI66_3
-
Input/
Output
HSTL_I_18
HSTL_III_18
SSTL18_I
Input
Input
Input
Input
Input
Input
Input
Input/
Output
1.1
1.8
Input/
Output
0.9
0.9
Input/
Output
SSTL2_I
-
1.25
1.25
Notes:
1. N/R - Not required for input operation.
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Product Specification
16
Spartan-3E FPGA Family: Functional Description
Table 7: Differential IOSTANDARD Bank Compatibility
VCCO Supply
Input
Differential
IOSTANDARD
Differential Bank
Requirements:
Restriction(1)
1.8V
2.5V
3.3V
VREF
Input,
On-chip Differential Termination,
Output
Applies to Outputs
LVDS_25
Input
Input
Only
Input,
On-chip Differential Termination,
Output
Applies to Outputs
RSDS_25
Input
Input
Input
Only
Input,
On-chip Differential Termination,
Output
Applies to Outputs
MINI_LVDS_25
Input
Only
LVPECL_25
BLVDS_25
Input
Input
Input
Input
VREF is not used for
these I/O standards
Input,
Output
Input
Input,
Output
NoDifferentialBank
Input
DIFF_HSTL_I_18
DIFF_HSTL_III_18
DIFF_SSTL18_I
Input
Input
Input
Restriction
(other I/O bank
restrictions might
Input,
Output
Input
apply)
Input,
Output
Input
Input,
Output
DIFF_SSTL2_I
Input
Input
Notes:
1. Each bank can support any two of the following: LVDS_25 outputs, MINI_LVDS_25 outputs, RSDS_25 outputs.
HSTL and SSTL inputs use the Reference Voltage (V
bias the input-switching threshold. Once a configuration
) to
On-Chip Differential Termination
REF
Spartan-3E devices provide an on-chip ~120Ω differential
termination across the input differential receiver terminals.
The on-chip input differential termination in Spartan-3E
devices potentially eliminates the external 100Ω termination
resistor commonly found in differential receiver circuits.
Differential termination is used for LVDS, mini-LVDS, and
RSDS as applications permit.
data file is loaded into the FPGA that calls for the I/Os of a
given bank to use HSTL/SSTL, a few specifically reserved
I/O pins on the same bank automatically convert to V
REF
inputs. For banks that do not contain HSTL or SSTL, V
pins remain available for user I/Os or input pins.
REF
Differential standards employ a pair of signals, one the
opposite polarity of the other. The noise canceling
properties (for example, Common-Mode Rejection) of these
standards permit exceptionally high data transfer rates. This
subsection introduces the differential signaling capabilities
of Spartan-3E devices.
On-chip Differential Termination is available in banks with
V
= 2.5V and is not supported on dedicated input pins.
CCO
Set the DIFF_TERM attribute to TRUE to enable Differential
Termination on a differential I/O pin pair.
The DIFF_TERM attribute uses the following syntax in the
UCF file:
Each device-package combination designates specific I/O
pairs specially optimized to support differential standards. A
unique L-number, part of the pin name, identifies the
line-pairs associated with each bank (see Module 4, Pinout
Descriptions). For each pair, the letters P and N designate
the true and inverted lines, respectively. For example, the
pin names IO_L43P_3 and IO_L43N_3 indicate the true
and inverted lines comprising the line pair L43 on Bank 3.
INST <I/O_BUFFER_INSTANTIATION_NAME>
DIFF_TERM = "<TRUE/FALSE>";
V
provides current to the outputs and additionally
CCO
powers the On-Chip Differential Termination. V
must be
CCO
2.5V when using the On-Chip Differential Termination. The
lines are not required for differential operation.
V
REF
To further understand how to combine multiple
IOSTANDARDs within a bank, refer to IOBs Organized into
Banks, page 19.
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Product Specification
17
Spartan-3E FPGA Family: Functional Description
X-Ref Target
-
Figure 11
X-Ref Target - Figure 12
Spartan-3E
Differential
Output
Spartan-3E
Differential Input
Z
= 50Ω
0
Pull-up
Output Path
Input Path
Z
Z
= 50Ω
= 50Ω
0
Spartan-3E
Differential Input
with On-Chip
Differential
Keeper
Pull-down
Spartan-3E
Differential
Output
0
Terminator
DS312-2_25_020807
Figure 12: Keeper Circuit
Z
= 50Ω
0
Slew Rate Control and Drive Strength
DS312-2_24_082605
Each IOB has a slew-rate control that sets the output
switching edge-rate for LVCMOS and LVTTL outputs. The
SLEW attribute controls the slew rate and can either be set
to SLOW (default) or FAST.
Figure 11: Differential Inputs and Outputs
Pull-Up and Pull-Down Resistors
Pull-up and pull-down resistors inside each IOB optionally
force a floating I/O or Input-only pin to a determined state.
Pull-up and pull-down resistors are commonly applied to
unused I/Os, inputs, and three-state outputs, but can be
used on any I/O or Input-only pin. The pull-up resistor
Each LVCMOS and LVTTL output additionally supports up
to six different drive current strengths as shown in Table 8.
To adjust the drive strength for each output, the DRIVE
attribute is set to the desired drive strength: 2, 4, 6, 8, 12,
and 16. Unless otherwise specified in the FPGA application,
the software default IOSTANDARD is LVCMOS25, SLOW
slew rate, and 12 mA output drive.
connects an IOB to V
through a resistor. The resistance
CCO
value depends on the V
voltage (see Module 3, DC and
CCO
Switching Characteristics for the specifications). The
pull-down resistor similarly connects an IOB to ground with
a resistor. The PULLUP and PULLDOWN attributes and
library primitives turn on these optional resistors.
Table 8: Programmable Output Drive Current
Output Drive Current (mA)
IOSTANDARD
2
4
✔
✔
✔
✔
✔
-
6
✔
✔
✔
✔
✔
-
8
✔
✔
✔
✔
-
12
✔
✔
✔
-
16
✔
✔
-
By default, PULLDOWN resistors terminate all unused I/O
and Input-only pins. Unused I/O and Input-only pins can
alternatively be set to PULLUP or FLOAT. To change the
unused I/O Pad setting, set the Bitstream Generator
(BitGen) option UnusedPin to PULLUP, PULLDOWN, or
FLOAT. The UnusedPin option is accessed through the
Properties for Generate Programming File in ISE. See
Bitstream Generator (BitGen) Options.
LVTTL
✔
✔
✔
✔
✔
✔
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
-
-
-
-
-
-
During configuration a Low logic level on the HSWAP pin
activates pull-up resistors on all I/O and Input-only pins not
actively used in the selected configuration mode.
High output current drive strength and FAST output slew
rates generally result in fastest I/O performance. However,
these same settings generally also result in transmission
line effects on the printed circuit board (PCB) for all but the
shortest board traces. Each IOB has independent slew rate
and drive strength controls. Use the slowest slew rate and
lowest output drive current that meets the performance
requirements for the end application.
Keeper Circuit
Each I/O has an optional keeper circuit (see Figure 12) that
keeps bus lines from floating when not being actively driven.
The KEEPER circuit retains the last logic level on a line after
all drivers have been turned off. Apply the KEEPER
attribute or use the KEEPER library primitive to use the
KEEPER circuitry. Pull-up and pull-down resistors override
the KEEPER settings.
Likewise, due to lead inductance, a given package supports
a limited number of simultaneous switching outputs (SSOs)
when using fast, high-drive outputs. Only use fast,
high-drive outputs when required by the application.
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Product Specification
18
Spartan-3E FPGA Family: Functional Description
1. All V
pins must be connected within a bank.
IOBs Organized into Banks
REF
REF
2. All V
lines associated with the bank must be set to
The Spartan-3E architecture organizes IOBs into four I/O
banks as shown in Figure 13. Each bank maintains
the same voltage level.
3. The V
levels used by all standards assigned to the
separate V
and V
supplies. The separate supplies
REF
CCO
REF
Inputs of the bank must agree. The Xilinx development
software checks for this. Table 6 describes how different
standards use the V
allow each bank to independently set V
. Similarly, the
CCO
V
supplies can be set for each bank. Refer to Table 6
REF
supply.
and Table 7 for V
and V
requirements.
REF
CCO
REF
If V
is not required to bias the input switching thresholds,
When working with Spartan-3E devices, most of the
differential I/O standards are compatible and can be
combined within any given bank. Each bank can support
any two of the following differential standards: LVDS_25
outputs, MINI_LVDS_25 outputs, and RSDS_25 outputs. As
an example, LVDS_25 outputs, RSDS_25 outputs, and any
other differential inputs while using on-chip differential
termination are a valid combination. A combination not
allowed is a single bank with LVDS_25 outputs, RSDS_25
outputs, and MINI_LVDS_25 outputs.
REF
all associated V
user I/Os or input pins.
pins within the bank can be used as
REF
Package Footprint Compatibility
Sometimes, applications outgrow the logic capacity of a
specific Spartan-3E FPGA. Fortunately, the Spartan-3E
family is designed so that multiple part types are available in
pin-compatible package footprints, as described in
Module 4, Pinout Descriptions. In some cases, there are
subtle differences between devices available in the same
footprint. These differences are outlined for each package,
such as pins that are unconnected on one device but
connected on another in the same package or pins that are
dedicated inputs on one package but full I/O on another.
When designing the printed circuit board (PCB), plan for
potential future upgrades and package migration.
X-Ref Target - Figure 13
Bank 0
The Spartan-3E family is not pin-compatible with any
previous Xilinx FPGA family.
Bank 2
Dedicated Inputs
DS312-2_26_021205
Dedicated Inputs are IOBs used only as inputs. Pin names
designate a Dedicated Input if the name starts with IP, for
example, IP or IP_Lxxx_x. Dedicated inputs retain the full
functionality of the IOB for input functions with a single
exception for differential inputs (IP_Lxxx_x). For the
differential Dedicated Inputs, the on-chip differential
termination is not available. To replace the on-chip
differential termination, choose a differential pair that
supports outputs (IO_Lxxx_x) or use an external 100Ω
termination resistor on the board.
Figure 13: Spartan-3E I/O Banks (top view)
I/O Banking Rules
When assigning I/Os to banks, these V
followed:
rules must be
CCO
1. All V
pins on the FPGA must be connected even if a
CCO
bank is unused.
2. All V
lines associated within a bank must be set to
CCO
the same voltage level.
ESD Protection
3. The V
levels used by all standards assigned to the
CCO
I/Os of any given bank must agree. The Xilinx
Clamp diodes protect all device pads against damage from
Electro-Static Discharge (ESD) as well as excessive voltage
transients. Each I/O has two clamp diodes: one diode
development software checks for this. Table 6 and
Table 7 describe how different standards use the V
supply.
CCO
extends P-to-N from the pad to V
and a second diode
CCO
4. If a bank does not have any V
requirements,
CCO
extends N-to-P from the pad to GND. During operation,
these diodes are normally biased in the off state. These
clamp diodes are always connected to the pad, regardless
of the signal standard selected. The presence of diodes
limits the ability of Spartan-3E I/Os to tolerate high signal
connect V
to an available voltage, such as 2.5V or
CCO
3.3V. Some configuration modes might place additional
requirements. Refer to Configuration for more
V
CCO
information.
voltages. The V absolute maximum rating in Table 73 of
Module 3, DC and Switching Characteristics specifies the
voltage range that I/Os can tolerate.
IN
If any of the standards assigned to the Inputs of the bank
use V , then the following additional rules must be
REF
observed:
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Product Specification
19
Spartan-3E FPGA Family: Functional Description
beginning of design operation in the User mode. After the
GTS net is released, all user I/Os go active while all unused
I/Os are pulled down (PULLDOWN). The designer can
control how the unused I/Os are terminated after GTS is
released by setting the Bitstream Generator (BitGen) option
UnusedPin to PULLUP, PULLDOWN, or FLOAT.
Supply Voltages for the IOBs
The IOBs are powered by three supplies:
1. The V
supplies, one for each of the FPGA’s I/O
CCO
banks, power the output drivers. The voltage on the
pins determines the voltage swing of the output
V
CCO
signal.
One clock cycle later (default), the Global Write Enable
(GWE) net is released allowing the RAM and registers to
change states. Once in User mode, any pull-up resistors
enabled by HSWAP revert to the user settings and HSWAP
is available as a general-purpose I/O. For more information
on PULLUP and PULLDOWN, see Pull-Up and Pull-Down
Resistors.
2.
3.
V
is the main power supply for the FPGA’s internal
CCINT
logic.
V
is an auxiliary source of power, primarily to
CCAUX
optimize the performance of various FPGA functions
such as I/O switching.
I/O and Input-Only Pin Behavior During
Power-On, Configuration, and User Mode
Behavior of Unused I/O Pins After
Configuration
In this section, all behavior described for I/O pins also
applies to input-only pins and dual-purpose I/O pins that are
not actively involved in the currently-selected configuration
mode.
By default, the Xilinx ISE development software
automatically configures all unused I/O pins as input pins
with individual internal pull-down resistors to GND.
This default behavior is controlled by the UnusedPin
bitstream generator (BitGen) option, as described in
Table 69.
All I/O pins have ESD clamp diodes to their respective V
CCO
CCINT
supply and from GND, as shown in Figure 5. The V
(1.2V), V (2.5V), and V supplies can be applied in
CCAUX
CCO
any order. Before the FPGA can start its configuration
process, V , V Bank 2, and V must have
JTAG Boundary-Scan Capability
CCINT CCO
CCAUX
reached their respective minimum recommended operating
levels indicated in Table 74. At this time, all output drivers
All Spartan-3E IOBs support boundary-scan testing
compatible with IEEE 1149.1/1532 standards. During
boundary-scan operations such as EXTEST and HIGHZ the
pull-down resistor is active. See JTAG Mode for more
information on programming via JTAG.
are in a high-impedance state. V
Bank 2, V
, and
CCO
CCINT
V
serve as inputs to the internal Power-On Reset
CCAUX
circuit (POR).
A Low level applied to the HSWAP input enables pull-up
resistors on user-I/O and input-only pins from power-on
throughout configuration. A High level on HSWAP disables
the pull-up resistors, allowing the I/Os to float. HSWAP
contains an internal pull-up resistor and defaults to High if
left floating. As soon as power is applied, the FPGA begins
initializing its configuration memory. At the same time, the
FPGA internally asserts the Global Set-Reset (GSR), which
asynchronously resets all IOB storage elements to a default
Low state. Also see Pin Behavior During Configuration.
Upon the completion of initialization and the beginning of
configuration, INIT_B goes High, sampling the M0, M1, and
M2 inputs to determine the configuration mode.
Configuration data is then loaded into the FPGA. The I/O
drivers remain in a high-impedance state (with or without
pull-up resistors, as determined by the HSWAP input)
throughout configuration.
At the end of configuration, the GSR net is released, placing
the IOB registers in a Low state by default, unless the
loaded design reverses the polarity of their respective SR
inputs.
The Global Three State (GTS) net is released during
Start-Up, marking the end of configuration and the
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Product Specification
20
Spartan-3E FPGA Family: Functional Description
(SRL16), and additional multiplexers and carry logic simplify
wide logic and arithmetic functions. Most general-purpose
logic in a design is automatically mapped to the slice
resources in the CLBs. Each CLB is identical, and the
Spartan-3E family CLB structure is identical to that for the
Spartan-3 family.
Configurable Logic Block (CLB) and
Slice Resources
For additional information, refer to the “Using Configurable
Logic Blocks (CLBs)” chapter in UG331.
CLB Overview
CLB Array
The Configurable Logic Blocks (CLBs) constitute the main
logic resource for implementing synchronous as well as
combinatorial circuits. Each CLB contains four slices, and
each slice contains two Look-Up Tables (LUTs) to
implement logic and two dedicated storage elements that
can be used as flip-flops or latches. The LUTs can be used
as a 16x1 memory (RAM16) or as a 16-bit shift register
The CLBs are arranged in a regular array of rows and
columns as shown in Figure 14.
Each density varies by the number of rows and columns of
CLBs (see Table 9).
X-Ref Target - Figure 14
X0Y3 X1Y3
X0Y2 X1Y2
X2Y3 X3Y3
X2Y2 X3Y2
X0Y1 X1Y1
X0Y0 X1Y0
X2Y1 X3Y1
X2Y0 X3Y0
Spartan-3E
FPGA
IOBs
Slice
CLB
DS312-2_31_021205
Figure 14: CLB Locations
Table 9: Spartan-3E CLB Resources
CLB
CLB
CLB
LUTs /
Slices
Equivalent
Logic Cells
RAM16 /
SRL16
Distributed
RAM Bits
Device
Rows
Columns
Total(1)
240
Flip-Flops
1,920
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
22
34
46
60
76
16
26
34
46
58
960
2,448
4,656
8,672
14,752
2,160
5,508
960
2,448
4,656
8,672
14,752
15,360
39,168
74,496
138,752
236,032
612
4,896
1,164
2,168
3,688
9,312
10,476
19,512
33,192
17,344
29,504
Notes:
1. The number of CLBs is less than the multiple of the rows and columns because the block RAM/multiplier blocks and the DCMs are
embedded in the array (see Figure 1 in Module 1).
LUTs support both logic and memory (including both
RAM16 and SRL16 shift registers) while half support logic
Slices
Each CLB comprises four interconnected slices, as shown
in Figure 16. These slices are grouped in pairs. Each pair is
organized as a column with an independent carry chain.
The left pair supports both logic and memory functions and
its slices are called SLICEM. The right pair supports logic
only and its slices are called SLICEL. Therefore half the
only, and the two types alternate throughout the array
columns. The SLICEL reduces the size of the CLB and
lowers the cost of the device, and can also provide a
performance advantage over the SLICEM.
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Product Specification
21
Spartan-3E FPGA Family: Functional Description
.
X-Ref Target
-
Figure 15
WS DI
DI
D
WF[4:1]
DS312-2_32_042007
Notes:
1. Options to invert signal polarity as well as other options that enable lines for various functions are not shown.
2. The index i can be 6, 7, or 8, depending on the slice. The upper SLICEL has an F8MUX, and the upper SLICEM has
an F7MUX. The lower SLICEL and SLICEM both have an F6MUX.
Figure 15: Simplified Diagram of the Left-Hand SLICEM
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Product Specification
22
Spartan-3E FPGA Family: Functional Description
X-Ref Target - Figure 16
Left-Hand SLICEM
(Logic or Distributed RAM
or Shift Register)
Right-Hand SLICEL
(Logic Only)
COUT
CLB
SLICE
X1Y1
SLICE
X1Y0
COUT
Switch
Matrix
Interconnect
to Neighbors
CIN
SLICE
X0Y1
SHIFTOUT
SHIFTIN
SLICE
X0Y0
CIN
DS099-2_05_082104
Figure 16: Arrangement of Slices within the CLB
Slice Location Designations
Slice Overview
The Xilinx development software designates the location of
a slice according to its X and Y coordinates, starting in the
bottom left corner, as shown in Figure 14. The letter ‘X’
followed by a number identifies columns of slices,
incrementing from the left side of the die to the right. The
letter ‘Y’ followed by a number identifies the position of each
slice in a pair as well as indicating the CLB row,
incrementing from the bottom of the die. Figure 16 shows
the CLB located in the lower left-hand corner of the die. The
SLICEM always has an even ‘X’ number, and the SLICEL
always has an odd ‘X’ number.
A slice includes two LUT function generators and two
storage elements, along with additional logic, as shown in
Figure 17.
Both SLICEM and SLICEL have the following elements in
common to provide logic, arithmetic, and ROM functions:
•
•
•
•
Two 4-input LUT function generators, F and G
Two storage elements
Two wide-function multiplexers, F5MUX and FiMUX
Carry and arithmetic logic
X-Ref Target - Figure 17
FiMUX
Carry
FiMUX
SRL16
RAM16
LUT4 (G)
Carry
LUT4 (G)
Register
Register
Register
F5MUX
Carry
F5MUX
SRL16
RAM16
LUT4 (F)
Carry
Register
LUT4 (F)
Arithmetic Logic
Arithmetic Logic
DS312-2_13_020905
SLICEM
SLICEL
Figure 17: Resources in a Slice
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Product Specification
23
Spartan-3E FPGA Family: Functional Description
The SLICEM pair supports two additional functions:
Enable (CE), Slice Write Enable (SLICEWE1), and
Reset/Set (RS) are shared in common between the two
halves.
•
•
Two 16x1 distributed RAM blocks, RAM16
Two 16-bit shift registers, SRL16
The LUTs located in the top and bottom portions of the slice
are referred to as “G” and “F”, respectively, or the “G-LUT”
and the “F-LUT”. The storage elements in the top and
bottom portions of the slice are called FFY and FFX,
respectively.
Each of these elements is described in more detail in the
following sections.
Logic Cells
Each slice has two multiplexers with F5MUX in the bottom
portion of the slice and FiMUX in the top portion. Depending
on the slice, the FiMUX takes on the name F6MUX,
F7MUX, or F8MUX, according to its position in the
multiplexer chain. The lower SLICEL and SLICEM both
have an F6MUX. The upper SLICEM has an F7MUX, and
the upper SLICEL has an F8MUX.
The combination of a LUT and a storage element is known
as a “Logic Cell”. The additional features in a slice, such as
the wide multiplexers, carry logic, and arithmetic gates, add
to the capacity of a slice, implementing logic that would
otherwise require additional LUTs. Benchmarks have
shown that the overall slice is equivalent to 2.25 simple logic
cells. This calculation provides the equivalent logic cell
count shown in Table 9.
The carry chain enters the bottom of the slice as CIN and
exits at the top as COUT. Five multiplexers control the chain:
CYINIT, CY0F, and CYMUXF in the bottom portion and
CY0G and CYMUXG in the top portion. The dedicated
arithmetic logic includes the exclusive-OR gates XORF and
XORG (bottom and top portions of the slice, respectively)
as well as the AND gates FAND and GAND (bottom and top
portions, respectively).
Slice Details
Figure 15 is a detailed diagram of the SLICEM. It represents
a superset of the elements and connections to be found in
all slices. The dashed and gray lines (blue when viewed in
color) indicate the resources found only in the SLICEM and
not in the SLICEL.
See Table 10 for a description of all the slice input and
output signals.
Each slice has two halves, which are differentiated as top
and bottom to keep them distinct from the upper and lower
slices in a CLB. The control inputs for the clock (CLK), Clock
Table 10: Slice Inputs and Outputs
Name
F[4:1]
Location
SLICEL/M Bottom
SLICEL/M Top
Direction
Input
Description
F-LUT and FAND inputs
G[4:1]
BX
Input
G-LUT and GAND inputs or Write Address (SLICEM)
SLICEL/M Bottom
Input
Bypass to or output (SLICEM) or storage element, or control input to F5MUX,
input to carry logic, or data input to RAM (SLICEM)
BY
SLICEL/M Top
Input
Bypass to or output (SLICEM) or storage element, or control input to FiMUX,
input to carry logic, or data input to RAM (SLICEM)
BXOUT
BYOUT
ALTDIG
DIG
SLICEM Bottom
SLICEM Top
Output
Output
Input
BX bypass output
BY bypass output
SLICEM Top
Alternate data input to RAM
SLICEM Top
Output
Input
ALTDIG or SHIFTIN bypass output
RAM Write Enable
SLICEWE1
F5
SLICEM Common
SLICEL/M Bottom
SLICEL/M Top
SLICEL/M Top
SLICEL/M Top
SLICEL/M Common
SLICEL/M Common
SLICEL/M Common
SLICEM Top
Output
Input
Output from F5MUX; direct feedback to FiMUX
Input to FiMUX; direct feedback from F5MUX or another FiMUX
Input to FiMUX; direct feedback from F5MUX or another FiMUX
Output from FiMUX; direct feedback to another FiMUX
FFX/Y Clock Enable
FXINA
FXINB
Fi
Input
Output
Input
CE
SR
Input
FFX/Y Set or Reset or RAM Write Enable (SLICEM)
FFX/Y Clock or RAM Clock (SLICEM)
Data input to G-LUT RAM
CLK
Input
SHIFTIN
Input
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Product Specification
24
Spartan-3E FPGA Family: Functional Description
Description
Table 10: Slice Inputs and Outputs (Cont’d)
Name
Location
SLICEM Bottom
SLICEL/M Bottom
SLICEL/M Top
Direction
Output
Input
SHIFTOUT
Shift data output from F-LUT RAM
CIN
COUT
X
Carry chain input
Output
Output
Output
Output
Output
Output
Output
Carry chain output
SLICEL/M Bottom
SLICEL/M Top
Combinatorial output
Y
Combinatorial output
XB
YB
XQ
YQ
SLICEL/M Bottom
SLICEL/M Top
Combinatorial output from carry or F-LUT SRL16 (SLICEM)
Combinatorial output from carry or G-LUT SRL16 (SLICEM)
SLICEL/M Bottom
SLICEL/M Top
FFX output
FFY output
2. Bypass the LUT, and then pass through a storage
element via the D input before exiting as XQ (or YQ).
Main Logic Paths
Central to the operation of each slice are two nearly
3. Control the wide function multiplexer F5MUX (or
identical data paths at the top and bottom of the slice. The
description that follows uses names associated with the
bottom path. (The top path names appear in parentheses.)
The basic path originates at an interconnect switch matrix
outside the CLB. See Interconnect for more information on
the switch matrix and the routing connections.
FiMUX).
4. Via multiplexers, serve as an input to the carry chain.
5. Drive the DI input of the LUT.
6. BY can control the REV inputs of both the FFY and FFX
storage elements. See Storage Element Functions.
Four lines, F1 through F4 (or G1 through G4 on the upper
path), enter the slice and connect directly to the LUT. Once
inside the slice, the lower 4-bit path passes through a LUT
‘F’ (or ‘G’) that performs logic operations. The LUT Data
output, ‘D’, offers five possible paths:
7. Finally, the DIG_MUX multiplexer can switch BY onto
the DIG line, which exits the slice.
The control inputs CLK, CE, SR, BX and BY have
programmable polarity. The LUT inputs do not need
programmable polarity because their function can be
inverted inside the LUT.
1. Exit the slice via line “X” (or “Y”) and return to
interconnect.
The sections that follow provide more detail on individual
functions of the slice.
2. Inside the slice, “X” (or “Y”) serves as an input to the
DXMUX (or DYMUX) which feeds the data input, “D”, of
the FFX (or FFY) storage element. The “Q” output of the
storage element drives the line XQ (or YQ) which exits
the slice.
Look-Up Tables
The Look-Up Table or LUT is a RAM-based function
generator and is the main resource for implementing logic
functions. Furthermore, the LUTs in each SLICEM pair can
be configured as Distributed RAM or a 16-bit shift register,
as described later.
3. Control the CYMUXF (or CYMUXG) multiplexer on the
carry chain.
4. With the carry chain, serve as an input to the XORF (or
XORG) exclusive-OR gate that performs arithmetic
operations, producing a result on “X” (or “Y”).
Each of the two LUTs (F and G) in a slice have four logic
inputs (A1-A4) and a single output (D). Any four-variable
Boolean logic operation can be implemented in one LUT.
Functions with more inputs can be implemented by
cascading LUTs or by using the wide function multiplexers
that are described later.
5. Drive the multiplexer F5MUX to implement logic
functions wider than four bits. The “D” outputs of both
the F-LUT and G-LUT serve as data inputs to this
multiplexer.
In addition to the main logic paths described above, there
are two bypass paths that enter the slice as BX and BY.
Once inside the FPGA, BX in the bottom half of the slice (or
BY in the top half) can take any of several possible
branches:
The output of the LUT can connect to the wide multiplexer
logic, the carry and arithmetic logic, or directly to a CLB
output or to the CLB storage element. See Figure 18.
1. Bypass both the LUT and the storage element, and
then exit the slice as BXOUT (or BYOUT) and return to
interconnect.
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Product Specification
25
Spartan-3E FPGA Family: Functional Description
X-Ref Target - Figure 18
Wide Multiplexers
Y
For additional information, refer to the “Using Dedicated
Multiplexers” chapter in UG331.
4
D
YQ
G[4:1]
A[4:1]
G-LUT
FFY
FFX
Wide-function multiplexers effectively combine LUTs in
order to permit more complex logic operations. Each slice
has two of these multiplexers with F5MUX in the bottom
portion of the slice and FiMUX in the top portion. The
F5MUX multiplexes the two LUTs in a slice. The FiMUX
multiplexes two CLB inputs which connect directly to the
F5MUX and FiMUX results from the same slice or from
other slices. See Figure 19.
X
4
F[4:1]
A[4:1]
F-LUT
XQ
D
DS312-2_33_111105
Figure 18: LUT Resources in a Slice
X-Ref Target - Figure 19
FiMUX
FXINA
1
0
FX (Local Feedback to FXIN)
Y (General Interconnect)
YQ
FXINB
BY
D Q
F5MUX
1
LUT
LUT
F[4:1]
G[4:1]
BX
F5 (Local Feedback to FXIN)
X (General Interconnect)
XQ
0
D Q
x312-2_34_021205
Figure 19: Dedicated Multiplexers in Spartan-3E CLB
Depending on the slice, FiMUX takes on the name F6MUX,
F7MUX, or F8MUX. The designation indicates the number
of inputs possible without restriction on the function. For
example, an F7MUX can generate any function of seven
inputs. Figure 20 shows the names of the multiplexers in
each position in the Spartan-3E CLB. The figure also
includes the direct connections within the CLB, along with
the F7MUX connection to the CLB below.
Each mux can create logic functions of more inputs than
indicated by its name. The F5MUX, for example, can
generate any function of five inputs, with four inputs
duplicated to two LUTs and the fifth input controlling the
mux. Because each LUT can implement independent 2:1
muxes, the F5MUX can combine them to create a 4:1 mux,
which is a six-input function. If the two LUTs have
completely independent sets of inputs, some functions of all
nine inputs can be implemented. Table 11 shows the
connections for each multiplexer and the number of inputs
possible for different types of functions.
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Product Specification
26
Spartan-3E FPGA Family: Functional Description
X-Ref Target - Figure 20
FXINB
FXINA
F8
X
F5
F5
FXINB
FXINA
FX
F6
F5
F5
FXINB
FXINA
FX
F7
F5
F5
FXINB
FXINA
F6
F5
FX
F5
DS312-2_38_021305
Figure 20: MUXes and Dedicated Feedback in Spartan-3E CLB
Table 11: MUX Capabilities
Total Number of Inputs per Function
MUX
Usage
Input Source
For Limited
Functions
For Any Function
For MUX
F5MUX
FiMUX
F5MUX
F6MUX
F7MUX
F8MUX
LUTs
5
6
7
8
6 (4:1 MUX)
11 (8:1 MUX)
20 (16:1 MUX)
37 (32:1 MUX)
9
F5MUX
F6MUX
F7MUX
19
39
79
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27
Spartan-3E FPGA Family: Functional Description
The wide multiplexers can be used by the automatic tools or
instantiated in a design using a component such as the
F5MUX. The symbol, signals, and function are described in
Figure 21, Table 12, and Table 13. The description is similar
for the F6MUX, F7MUX, and F8MUX. Each has versions
with a general output, local output, or both.
X-Ref Target - Figure 21
I0
I1
S
0
1
LO
O
DS312-2_35_021205
Figure 21: F5MUX with Local and General Outputs
Table 12: F5MUX Inputs and Outputs
Signal
I0
Function
Input selected when S is Low
Input selected when S is High
Select input
I1
S
LO
Local Output that connects to the F5 or FX CLB pins,
which use local feedback to the FXIN inputs to the
FiMUX for cascading
O
General Output that connects to the general-purpose
combinatorial or registered outputs of the CLB
Table 13: F5MUX Function
Inputs
Outputs
S
0
0
1
1
I0
1
I1
X
X
1
O
1
0
1
0
LO
1
0
0
X
X
1
0
0
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Spartan-3E FPGA Family: Functional Description
The carry chain enters the slice as CIN and exits as COUT,
controlled by several multiplexers. The carry chain connects
directly from one CLB to the CLB above. The carry chain
can be initialized at any point from the BX (or BY) inputs.
Carry and Arithmetic Logic
For additional information, refer to the “Using Carry and
Arithmetic Logic” chapter in UG331.
The carry chain, together with various dedicated arithmetic
logic gates, support fast and efficient implementations of
math operations. The carry logic is automatically used for
most arithmetic functions in a design. The gates and
multiplexers of the carry and arithmetic logic can also be
used for general-purpose logic, including simple wide
Boolean functions.
The dedicated arithmetic logic includes the exclusive-OR
gates XORF and XORG (upper and lower portions of the
slice, respectively) as well as the AND gates GAND and
FAND (upper and lower portions, respectively). These gates
work in conjunction with the LUTs to implement efficient
arithmetic functions, including counters and multipliers,
typically at two bits per slice. See Figure 22 and Table 14.
X-Ref Target - Figure 22
COUT
YB
1
CYMUXG
Y
G[4:1]
A[4:1]
G-LUT
CYSELG
CY0G
G1 G2
YQ
D
FFY
XORG
GAND
1
0
BY
XB
1
4
CYMUXF
X
F[4:1]
A[4:1]
F-LUT
CYSELF
CY0F
F1
F2
XQ
D
FFX
XORF
CYINIT
FAND
1
0
BX
DS312-2_14_021305
CIN
Figure 22: Carry Logic
Table 14: Carry Logic Functions
Function
Description
CYINIT
Initializes carry chain for a slice. Fixed selection of:
·
·
CIN carry input from the slice below
BX input
CY0F
Carry generation for bottom half of slice. Fixed selection of:
·
·
·
·
F1 or F2 inputs to the LUT (both equal 1 when a carry is to be generated)
FAND gate for multiplication
BX input for carry initialization
Fixed 1 or 0 input for use as a simple Boolean function
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Spartan-3E FPGA Family: Functional Description
Table 14: Carry Logic Functions (Cont’d)
Function
Description
CY0G
Carry generation for top half of slice. Fixed selection of:
·
·
·
·
G1 or G2 inputs to the LUT (both equal 1 when a carry is to be generated)
GAND gate for multiplication
BY input for carry initialization
Fixed 1 or 0 input for use as a simple Boolean function
CYMUXF
CYMUXG
CYSELF
CYSELG
XORF
Carry generation or propagation mux for bottom half of slice. Dynamic selection via CYSELF of:
·
·
CYINIT carry propagation (CYSELF = 1)
CY0F carry generation (CYSELF = 0)
Carry generation or propagation mux for top half of slice. Dynamic selection via CYSELF of:
·
·
CYMUXF carry propagation (CYSELG = 1)
CY0G carry generation (CYSELG = 0)
Carry generation or propagation select for bottom half of slice. Fixed selection of:
·
·
F-LUT output (typically XOR result)
Fixed 1 to always propagate
Carry generation or propagation select for top half of slice. Fixed selection of:
·
·
G-LUT output (typically XOR result)
Fixed 1 to always propagate
Sum generation for bottom half of slice. Inputs from:
·
·
F-LUT
CYINIT carry signal from previous stage
Result is sent to either the combinatorial or registered output for the top of the slice.
XORG
FAND
GAND
Sum generation for top half of slice. Inputs from:
·
·
G-LUT
CYMUXF carry signal from previous stage
Result is sent to either the combinatorial or registered output for the top of the slice.
Multiplier partial product for bottom half of slice. Inputs:
·
·
F-LUT F1 input
F-LUT F2 input
Result is sent through CY0F to become the carry generate signal into CYMUXF
Multiplier partial product for top half of slice. Inputs:
·
·
G-LUT G1 input
G-LUT G2 input
Result is sent through CY0G to become the carry generate signal into CYMUXG
X-Ref Target - Figure 23
The basic usage of the carry logic is to generate a half-sum
in the LUT via an XOR function, which generates or
propagates a carry out COUT via the carry mux CYMUXF
(or CYMUXG), and then complete the sum with the
dedicated XORF (or XORG) gate and the carry input CIN.
This structure allows two bits of an arithmetic function in
each slice. The CYMUXF (or CYMUXG) can be instantiated
using the MUXCY element, and the XORF (or XORG) can
be instantiated using the XORCY element.
LUT
COUT
B
A
MUXCY
Sum
XORCY
CIN
DS312-2_37_021305
Figure 23: Using the MUXCY and XORCY in the Carry
The FAND (or GAND) gate is used for partial product
multiplication and can be instantiated using the MULT_AND
component. Partial products are generated by two-input
AND gates and then added. The carry logic is efficient for
the adder, but one of the inputs must be outside the LUT as
shown in Figure 23.
Logic
The FAND (or GAND) gate is used to duplicate one of the
partial products, while the LUT generates both partial
products and the XOR function, as shown in Figure 24.
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Spartan-3E FPGA Family: Functional Description
X-Ref Target - Figure 24
Storage Elements
LUT
COUT
Am
Bn+1
The storage element, which is programmable as either a
D-type flip-flop or a level-sensitive transparent latch,
provides a means for synchronizing data to a clock signal,
among other uses. The storage elements in the top and
bottom portions of the slice are called FFY and FFX,
respectively. FFY has a fixed multiplexer on the D input
selecting either the combinatorial output Y or the bypass
signal BY. FFX selects between the combinatorial output X
or the bypass signal BX.
Am+1
Bn
Pm+1
MULT_AND
CIN
DS312-2_39_021305
Figure 24: Using the MULT_AND for Multiplication in
Carry Logic
The functionality of a slice storage element is identical to
that described earlier for the I/O storage elements. All
signals have programmable polarity; the default active-High
function is described.
The MULT_AND is useful for small multipliers. Larger
multipliers can be built using the dedicated 18x18 multiplier
blocks (see Dedicated Multipliers).
Table 15: Storage Element Signals
Signal
Description
D
Input. For a flip-flop data on the D input is loaded when R and S (or CLR and PRE) are Low and CE is High during the
Low-to-High clock transition. For a latch, Q reflects the D input while the gate (G) input and gate enable (GE) are High and R
and S (or CLR and PRE) are Low. The data on the D input during the High-to-Low gate transition is stored in the latch. The
data on the Q output of the latch remains unchanged as long as G or GE remains Low.
Q
Output. Toggles after the Low-to-High clock transition for a flip-flop and immediately for a latch.
Clock for edge-triggered flip-flops.
C
G
Gate for level-sensitive latches.
CE
GE
S
Clock Enable for flip-flops.
Gate Enable for latches.
Synchronous Set (Q = High). When the S input is High and R is Low, the flip-flop is set, output High, during the Low-to-High
clock (C) transition. A latch output is immediately set, output High.
R
Synchronous Reset (Q = Low); has precedence over Set.
PRE
Asynchronous Preset (Q = High). When the PRE input is High and CLR is Low, the flip-flop is set, output High, during the
Low-to-High clock (C) transition. A latch output is immediately set, output High.
CLR
SR
Asynchronous Clear (Q = Low); has precedence over Preset to reset Q output Low
CLB input for R, S, CLR, or PRE
REV
CLB input for opposite of SR. Must be asynchronous or synchronous to match SR.
The control inputs R, S, CE, and C are all shared between
the two flip-flops in a slice.
Table 16: FD Flip-Flop Functionality with Synchronous
Reset, Set, and Clock Enable
X-Ref Target - Figure 25
Inputs
Outputs
S
R
1
0
0
0
0
S
X
1
0
0
0
CE
X
D
X
X
X
1
C
↑
↑
X
↑
↑
Q
FDRSE
0
D
CE
C
Q
X
1
0
No Change
R
1
1
0
DS312-2_40_021305
1
0
Figure 25: FD Flip-Flop Component with Synchronous
Reset, Set, and Clock Enable
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Spartan-3E FPGA Family: Functional Description
Initialization
Distributed RAM
The CLB storage elements are initialized at power-up,
during configuration, by the global GSR signal, and by the
individual SR or REV inputs to the CLB. The storage
elements can also be re-initialized using the GSR input on
the STARTUP_SPARTAN3E primitive. See Global Controls
(STARTUP_SPARTAN3E).
For additional information, refer to the “Using Look-Up
Tables as Distributed RAM” chapter in UG331.
The LUTs in the SLICEM can be programmed as distributed
RAM. This type of memory affords moderate amounts of
data buffering anywhere along a data path. One SLICEM
LUT stores 16 bits (RAM16). The four LUT inputs F[4:1] or
G[4:1] become the address lines labeled A[4:1] in the
device model and A[3:0] in the design components,
providing a 16x1 configuration in one LUT. Multiple SLICEM
LUTs can be combined in various ways to store larger
amounts of data, including 16x4, 32x2, or 64x1
configurations in one CLB. The fifth and sixth address lines
required for the 32-deep and 64-deep configurations,
respectively, are implemented using the BX and BY inputs,
which connect to the write enable logic for writing and the
F5MUX and F6MUX for reading.
Table 17: Slice Storage Element Initialization
Signal
SR
Description
Set/Reset input. Forces the storage element into the
state specified by the attribute SRHIGH or SRLOW.
SRHIGH forces a logic 1 when SR is asserted.
SRLOW forces a logic 0. For each slice, set and reset
can be set to be synchronous or asynchronous.
REV
GSR
Reverse of Set/Reset input. A second input (BY)
forces the storage element into the opposite state.
The reset condition is predominant over the set
condition if both are active. Same
synchronous/asynchronous setting as for SR.
Writing to distributed RAM is always synchronous to the
SLICEM clock (WCLK for distributed RAM) and enabled by
the SLICEM SR input which functions as the active-High
Write Enable (WE). The read operation is asynchronous,
and, therefore, during a write, the output initially reflects the
old data at the address being written.
Global Set/Reset. GSR defaults to active High but can
be inverted by adding an inverter in front of the GSR
input of the STARTUP_SPARTAN3E element. The
initial state after configuration or GSR is defined by a
separate INIT0 and INIT1 attribute. By default, setting
the SRLOW attribute sets INIT0, and setting the
SRHIGH attribute sets INIT1.
The distributed RAM outputs can be captured using the
flip-flops within the SLICEM element. The WE write-enable
control for the RAM and the CE clock-enable control for the
flip-flop are independent, but the WCLK and CLK clock
inputs are shared. Because the RAM read operation is
asynchronous, the output data always reflects the currently
addressed RAM location.
A dual-port option combines two LUTs so that memory
access is possible from two independent data lines. The
same data is written to both 16x1 memories but they have
independent read address lines and outputs. The dual-port
function is implemented by cascading the G-LUT address
lines, which are used for both read and write, to the F-LUT
write address lines (WF[4:1] in Figure 15), and by
cascading the G-LUT data input D1 through the DIF_MUX
in Figure 15 and to the D1 input on the F-LUT. One CLB
provides a 16x1 dual-port memory as shown in Figure 26.
Any write operation on the D input and any read operation
on the SPO output can occur simultaneously with and
independently from a read operation on the second
read-only port, DPO.
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Spartan-3E FPGA Family: Functional Description
X-Ref Target - Figure 26
SLICEM
D
16x1
LUT
RAM
(Read/
Write)
SPO
A[3:0]
Optional
Register
WE
WCLK
DPO
16x1
LUT
RAM
(Read
Only)
DPRA[3:0]
Optional
Register
DS312-2_41_021305
Figure 26: RAM16X1D Dual-Port Usage
X-Ref Target - Figure 27
Table 19: Distributed RAM Signals
Signal Description
WCLK
RAM16X1D
WE
D
WCLK
SPO
DPO
The clock is used for synchronous writes. The
data and the address input pins have setup
times referenced to the WCLK pin. Active on
the positive edge by default with built-in
programmable polarity.
A0
A1
A2
A3
DPRA0
DPRA1
DPRA2
DPRA3
WE
The enable pin affects the write functionality of
the port. An inactive Write Enable prevents
any writing to memory cells. An active Write
Enable causes the clock edge to write the data
input signal to the memory location pointed to
by the address inputs. Active High by default
with built-in programmable polarity.
DS312-2_42_021305
Figure 27: Dual-Port RAM Component
A0, A1, A2, A3 The address inputs select the memory cells for
Table 18: Dual-Port RAM Function
(A4, A5)
read or write. The width of the port determines
the required address inputs.
Inputs
Outputs
WE (mode)
0 (read)
1 (read)
1 (read)
1 (write)
1 (read)
WCLK
D
X
X
X
D
X
SPO
DPO
D
The data input provides the new data value to
be written into the RAM.
X
0
1
↑
↓
data_a
data_a
data_a
D
data_d
data_d
data_d
data_d
data_d
O, SPO, and
DPO
The data output O on single-port RAM or the
SPO and DPO outputs on dual-port RAM
reflects the contents of the memory cells
referenced by the address inputs. Following an
active write clock edge, the data out (O or
SPO) reflects the newly written data.
data_a
Notes:
The INIT attribute can be used to preload the memory with
data during FPGA configuration. The default initial contents
for RAM is all zeros. If the WE is held Low, the element can
be considered a ROM. The ROM function is possible even
in the SLICEL.
1. data_a = word addressed by bits A3-A0.
2. data_d = word addressed by bits DPRA3-DPRA0.
The global write enable signal, GWE, is asserted
automatically at the end of device configuration to enable all
writable elements. The GWE signal guarantees that the
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Spartan-3E FPGA Family: Functional Description
X-Ref Target - Figure 29
initialized distributed RAM contents are not disturbed during
the configuration process.
SRLC16E
D
CE
CLK
A0
A1
A2
A3
Q
Q15
The distributed RAM is useful for smaller amounts of
memory. Larger memory requirements can use the
dedicated 18Kbit RAM blocks (see Block RAM).
Shift Registers
DS312-2_43_021305
For additional information, refer to the “Using Look-Up
Tables as Shift Registers (SRL16)” chapter in UG331.
Figure 29: SRL16 Shift Register Component with
Cascade and Clock Enable
It is possible to program each SLICEM LUT as a 16-bit shift
register (see Figure 28). Used in this way, each LUT can
delay serial data anywhere from 1 to 16 clock cycles without
using any of the dedicated flip-flops. The resulting
programmable delays can be used to balance the timing of
data pipelines.
The functionality of the shift register is shown in Table 20.
The SRL16 shifts on the rising edge of the clock input when
the Clock Enable control is High. This shift register cannot
be initialized either during configuration or during operation
except by shifting data into it. The clock enable and clock
inputs are shared between the two LUTs in a SLICEM. The
clock enable input is automatically kept active if unused.
The SLICEM LUTs cascade from the G-LUT to the F-LUT
through the DIFMUX (see Figure 15). SHIFTIN and
SHIFTOUT lines cascade a SLICEM to the SLICEM below
to form larger shift registers. The four SLICEM LUTs of a
single CLB can be combined to produce delays up to 64
clock cycles. It is also possible to combine shift registers
across more than one CLB.
Table 20: SRL16 Shift Register Function
Inputs
Outputs
Am
Am
Am
CLK
CE
0
D
X
D
Q
Q15
Q[15]
Q[15]
X
Q[Am]
X-Ref Target - Figure 28
↑
1
Q[Am-1]
SRLC16
SHIFTIN
Notes:
1. m = 0, 1, 2, 3.
SHIFT-REG
4
Output
D
A[3:0]
A[3:0]
MC15
Registered
Output
D
Q
DI
WS
DI (BY)
(optional)
WSG
CE (SR)
CLK
WE
CK
SHIFTOUT
or YB
X465_03_040203
Figure 28: Logic Cell SRL16 Structure
Each shift register provides a shift output MC15 for the last
bit in each LUT, in addition to providing addressable access
to any bit in the shift register through the normal D output.
The address inputs A[3:0] are the same as the distributed
RAM address lines, which come from the LUT inputs F[4:1]
or G[4:1]. At the end of the shift register, the CLB flip-flop
can be used to provide one more shift delay for the
addressable bit.
The shift register element is known as the SRL16 (Shift
Register LUT 16-bit), with a ‘C’ added to signify a cascade
ability (Q15 output) and ‘E’ to indicate a Clock Enable. See
Figure 29 for an example of the SRLC16E component.
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Spartan-3E FPGA Family: Functional Description
and write operations. There are four basic data paths, as
shown in Figure 30:
Block RAM
For additional information, refer to the “Using Block RAM”
chapter in UG331.
1. Write to and read from Port A
2. Write to and read from Port B
3. Data transfer from Port A to Port B
4. Data transfer from Port B to Port A
Spartan-3E devices incorporate 4 to 36 dedicated block
RAMs, which are organized as dual-port configurable
18 Kbit blocks. Functionally, the block RAM is identical to
the Spartan-3 architecture block RAM. Block RAM
synchronously stores large amounts of data while
distributed RAM, previously described, is better suited for
buffering small amounts of data anywhere along signal
paths. This section describes basic block RAM functions.
X-Ref Target - Figure 30
3
Write
Read
Write
4
Read
Spartan-3E
Dual-Port
Block RAM
Each block RAM is configurable by setting the content’s
initial values, default signal value of the output registers,
port aspect ratios, and write modes. Block RAM can be
used in single-port or dual-port modes.
Write
Write
2
1
Read
Read
Arrangement of RAM Blocks on Die
DS312-2_01_020705
The block RAMs are located together with the multipliers on
the die in one or two columns depending on the size of the
device. The XC3S100E has one column of block RAM. The
Spartan-3E devices ranging from the XC3S250E to
XC3S1600E have two columns of block RAM. Table 21
shows the number of RAM blocks, the data storage
capacity, and the number of columns for each device.
Row(s) of CLBs are located above and below each block
RAM column.
Figure 30: Block RAM Data Paths
Number of Ports
A choice among primitives determines whether the block
RAM functions as dual- or single-port memory. A name of
the form RAMB16_S[w ]_S[w ] calls out the dual-port
A
B
primitive, where the integers w and w specify the total
A
B
data path width at ports A and B, respectively. Thus, a
RAMB16_S9_S18 is a dual-port RAM with a 9-bit Port A
and an 18-bit Port B. A name of the form RAMB16_S[w]
identifies the single-port primitive, where the integer w
specifies the total data path width of the lone port A. A
RAMB16_S18 is a single-port RAM with an 18-bit port.
Table 21: Number of RAM Blocks by Device
Total
Total
Addressable
Locations
(bits)
Number of
Columns
Device
Number of
RAM Blocks
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
4
73,728
221,184
368,640
516,096
663,552
1
2
2
2
2
Port Aspect Ratios
12
20
28
36
Each port of the block RAM can be configured
independently to select a number of different possible
widths for the data input (DI) and data output (DO) signals
as shown in Table 22.
Immediately adjacent to each block RAM is an embedded
18x18 hardware multiplier. The upper 16 bits of the block
RAM's Port A Data input bus are shared with the upper 16
bits of the A multiplicand input bus of the multiplier. Similarly,
the upper 16 bits of Port B's data input bus are shared with
the B multiplicand input bus of the multiplier.
The Internal Structure of the Block RAM
The block RAM has a dual port structure. The two identical
data ports called A and B permit independent access to the
common block RAM, which has a maximum capacity of
18,432 bits, or 16,384 bits with no parity bits (see parity bits
description in Table 22). Each port has its own dedicated
set of data, control, and clock lines for synchronous read
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Spartan-3E FPGA Family: Functional Description
Table 22: Port Aspect Ratios
Total Data
Path Width
(w bits)
DI/DO Data
Bus Width
DIP/DOP
ADDR
No. of
Block RAM
Capacity
DI/DO
[w-p-1:0]
DIP/DOP
[p-1:0]
ADDR
[r-1:0]
Parity Bus
Bus Width
Addressable
(w-p bits)(1) Width (p bits)
(r bits)(2)
Locations (n)(3)
(w*n bits)(4)
1
2
1
2
0
0
0
1
2
4
14
13
12
11
10
9
[0:0]
[1:0]
-
[13:0]
[12:0]
[11:0]
[10:0]
[9:0]
16,384
8,192
4,096
2,048
1,024
512
16,384
16,384
16,384
18,432
18,432
18,432
-
4
4
[3:0]
-
9
8
[7:0]
[0:0]
[1:0]
[3:0]
18
36
16
32
[15:0]
[31:0]
[8:0]
Notes:
1. The width of the total data path (w) is the sum of the DI/DO bus width (w-p) and any parity bits (p).
2. The width selection made for the DI/DO bus determines the number of address lines (r) according to the relationship expressed as:
r = 14 – [log(w–p)/log9(2)].
3. The number of address lines delimits the total number (n) of addressable locations or depth according to the following equation: n = 2 .
4. The product of w and n yields the total block RAM capacity.
r
If the data bus width of Port A differs from that of Port B, the
block RAM automatically performs a bus-matching function
as described in Figure 31. When data is written to a port
with a narrow bus and then read from a port with a wide bus,
the latter port effectively combines “narrow” words to form
“wide” words. Similarly, when data is written into a port with
a wide bus and then read from a port with a narrow bus, the
latter port divides “wide” words to form “narrow” words.
Parity bits are not available if the data port width is
configured as x4, x2, or x1. For example, if a x36 data word
(32 data, 4 parity) is addressed as two x18 halfwords (16
data, 2 parity), the parity bits associated with each data byte
are mapped within the block RAM to the appropriate parity
bits. The same effect happens when the x36 data word is
mapped as four x9 words.
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Spartan-3E FPGA Family: Functional Description
X-Ref Target - Figure 31
Parity
Data
Address
35 34 33 32 31
P3 P2 P1 P0
24 23
16 15
8 7
0
0
Byte 3
Byte 2
Byte 1
Byte 0
512x36
0
17 16 15
P3 P2
8 7
Byte 3
Byte 1
Byte 2
Byte 0
1
0
1Kx18
P1 P0
8
7
0
P3
P2
P1
P0
Byte 3
Byte 2
Byte 1
Byte 0
3
2
1
0
2Kx9
3
2 1 0
7 6 5 4
3 2 1 0
7
6
4Kx4
7 6 5 4
3 2 1 0
1
0
1
0
7 6
5 4
3 2
1 0
F
E
D
C
8Kx2
7 6
5 4
3 2
1 0
3
2
1
0
0
7
6
5
4
1F
1E
1D
1C
16Kx1
3
2
1
0
3
2
1
0
DS312-2_02_102105
Figure 31: Data Organization and Bus-matching Operation with Different Port Widths on Port A and Port B
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Spartan-3E FPGA Family: Functional Description
Design Note
Block RAM Port Signal Definitions
Whenever a block RAM port is enabled (ENA or
ENB = High), all address transitions must meet the data
sheet setup and hold times with respect to the port clock
(CLKA or CLKB), as shown in Table 103, page 139.This
requirement must be met even if the RAM read output is of
no interest.
Representations of the dual-port primitive
RAMB16_S[w ]_S[w ] and the single-port primitive
A
B
RAMB16_S[w] with their associated signals are shown in
Figure 32a and Figure 32b, respectively. These signals are
defined in Table 23. The control signals (WE, EN, CLK, and
SSR) on the block RAM are active High. However, optional
inverters on the control signals change the polarity of the
active edge to active Low.
X-Ref Target - Figure 32
RAMB16_SWA_SWB
WEA
ENA
SSRA
DOPA[pA–1:0]
CLKA
DOA[wA–pA–1:0]
ADDRA[rA–1:0]
DIA[wA–pA–1:0]
DIPA[pA–1:0]
RAMB16_Sw
WEB
ENB
WE
EN
SSRB
SSR
DOPB[pB–1:0]
DOP[p–1:0]
CLK
CLKB
DOB[wB–pB–1:0]
DO[w–p–1:0]
ADDRB[rB–1:0]
DIB[wB–pB–1:0]
DIPB[pB–1:0]
ADDR[r–1:0]
DI[w–p–1:0]
DIP[p–1:0]
(a) Dual-Port
(b) Single-Port
DS312-2_03_111105
Notes:
1.
2.
3.
w and w are integers representing the total data path width (i.e., data bits plus parity bits) at Ports A and B, respectively.
A B
p
and p are integers that indicate the number of data path lines serving as parity bits.
B
A
r
and r are integers representing the address bus width at ports A and B, respectively.
A
B
4. The control signals CLK, WE, EN, and SSR on both ports have the option of inverted polarity.
Figure 32: Block RAM Primitives
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Spartan-3E FPGA Family: Functional Description
Table 23: Block RAM Port Signals
Port A
Signal
Name
Port B
Signal
Name
Signal
Description
Direction
Function
Address Bus
ADDRA
ADDRB
Input
The Address Bus selects a memory location for read or write operations.
The width (w) of the port’s associated data path determines the number of
available address lines (r), as per Table 22.
Whenever a port is enabled (ENA or ENB = High), address transitions must
meet the data sheet setup and hold times with respect to the port clock
(CLKA or CLKB), as shown in Table 103, page 139.This requirement must
be met even if the RAM read output is of no interest.
Data Input Bus
DIA
DIB
Input
Input
Data at the DI input bus is written to the RAM location specified by the
address input bus (ADDR) during the active edge of the CLK input, when
the clock enable (EN) and write enable (WE) inputs are active.
It is possible to configure a port’s DI input bus width (w-p) based on
Table 22. This selection applies to both the DI and DO paths of a given port.
ParityDataInput(s)
DIPA
DIPB
Parity inputs represent additional bits included in the data input path.
Although referred to herein as “parity” bits, the parity inputs and outputs
have no special functionality for generating or checking parity and can be
used as additional data bits. The number of parity bits ‘p’ included in the DI
(same as for the DO bus) depends on a port’s total data path width (w). See
Table 22.
Data Output Bus
DOA
DOB
Output
Data is written to the DO output bus from the RAM location specified by the
address input bus, ADDR. See the DI signal description for DO port width
configurations.
Basic data access occurs on the active edge of the CLK when WE is
inactive and EN is active. The DO outputs mirror the data stored in the
address ADDR memory location. Data access with WE active if the
WRITE_MODE attribute is set to the value: WRITE_FIRST, which
accesses data after the write takes place. READ_FIRST accesses data
before the write occurs. A third attribute, NO_CHANGE, latches the DO
outputs upon the assertion of WE. See Block RAM Data Operations for
details on the WRITE_MODE attribute.
Parity Data
Output(s)
DOPA
WEA
ENA
DOPB
WEB
ENB
Output
Input
Parity outputs represent additional bits included in the data input path. The
number of parity bits ‘p’ included in the DI bus (same as for the DO bus)
depends on a port’s total data path width (w). See the DIP signal
description for configuration details.
Write Enable
Clock Enable
When asserted together with EN, this input enables the writing of data to
the RAM. When WE is inactive with EN asserted, read operations are still
possible. In this case, a latch passes data from the addressed memory
location to the DO outputs.
Input
When asserted, this input enables the CLK signal to perform read and write
operations to the block RAM. When inactive, the block RAM does not
perform any read or write operations.
Set/Reset
Clock
SSRA
CLKA
SSRB
CLKB
Input
Input
When asserted, this pin forces the DO output latch to the value of the
SRVAL attribute. It is synchronized to the CLK signal.
This input accepts the clock signal to which read and write operations are
synchronized. All associated port inputs are required to meet setup times
with respect to the clock signal’s active edge. The data output bus responds
after a clock-to-out delay referenced to the clock signal’s active edge.
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Spartan-3E FPGA Family: Functional Description
Block RAM Attribute Definitions
A block RAM has a number of attributes that control its
behavior as shown in Table 24.
Table 24: Block RAM Attributes
Function
Attribute
Possible Values
Initial Content for Data Memory, Loaded during
Configuration
INITxx
(INIT_00 through INIT3F)
Each initialization string defines 32 hex values of the
16384-bit data memory of the block RAM.
Initial Content for Parity Memory, Loaded
during Configuration
INITPxx
Each initialization string defines 32 hex values of the
(INITP_00 through INITP0F) 2048-bit parity data memory of the block RAM.
Data Output Latch Initialization
INIT(single-port)
INITA, INITB(dual-port)
Hex value the width of the chosen port.
Hex value the width of the chosen port.
WRITE_FIRST, READ_FIRST, NO_CHANGE
Data Output Latch Synchronous Set/Reset
Value
SRVAL(single-port)
SRVAL_A, SRVAL_B(dual-port)
Data Output Latch Behavior during Write (see
Block RAM Data Operations)
WRITE_MODE
The waveforms for the write operation are shown in the top
half of Figure 33, Figure 34, and Figure 35. When the WE
and EN signals enable the active edge of CLK, data at the
DI input bus is written to the block RAM location addressed
by the ADDR lines.
Block RAM Data Operations
Writing data to and accessing data from the block RAM are
synchronous operations that take place independently on
each of the two ports. Table 25 describes the data
operations of each port as a result of the block RAM control
signals in their default active-High edges.
Table 25: Block RAM Function Table
Input Signals
Output Signals
RAM Data
Parity
GSR
EN
SSR
WE
CLK
ADDR
DIP
DI
DOP
DO
Data
Immediately After Configuration
Loaded During Configuration
X
X
INITP_xx
No Chg
No Chg
No Chg
INIT_xx
No Chg
No Chg
No Chg
Global Set/Reset Immediately After Configuration
1
0
0
0
X
0
1
1
X
X
1
X
X
0
X
X
↑
↑
X
X
X
X
X
INIT
RAM Disabled
No Chg
INIT
X
X
No Chg
SRVAL
Synchronous Set/Reset
SRVAL
X
X
Synchronous Set/Reset During Write RAM
1
1
addr
pdata Data
SRVAL
SRVAL
RAM(addr)
← pdata
RAM(addr)
← data
Read RAM, no Write Operation
RAM(pdata)
0
0
1
1
0
0
0
1
↑
↑
addr
X
X
RAM(data)
No Chg
No Chg
Write RAM, Simultaneous Read Operation
addr pdata Data WRITE_MODE = WRITE_FIRST
pdata
RAM(data)
No Chg
data
RAM(addr)
← pdata
RAM(addr)
← data
WRITE_MODE = READ_FIRST
RAM(data)
RAM(addr)
← pdata
RAM(addr)
← pdata
WRITE_MODE = NO_CHANGE
No Chg
RAM(addr)
← pdata
RAM(addr)
← pdata
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Spartan-3E FPGA Family: Functional Description
There are a number of different conditions under which data
can be accessed at the DO outputs. Basic data access
always occurs when the WE input is inactive. Under this
condition, data stored in the memory location addressed by
the ADDR lines passes through a output latch to the DO
outputs. The timing for basic data access is shown in the
portions of Figure 33, Figure 34, and Figure 35 during
which WE is Low.
Data also can be accessed on the DO outputs when
asserting the WE input based on the value of the
WRITE_MODE attribute as described in Table 26.
Table 26: WRITE_MODE Effect on Data Output Latches During Write Operations
Effect on Opposite Port
(dual-port only with same address)
Write Mode
Effect on Same Port
WRITE_FIRST
Read After Write
Data on DI and DIP inputs is written into specified
RAM location and simultaneously appears on DO and
DOP outputs.
Invalidates data on DO and DOP outputs.
READ_FIRST
Read Before Write
Data from specified RAM location appears on DO and Data from specified RAM location appears on DO and
DOP outputs.
DOP outputs.
Data on DI and DIP inputs is written into specified
location.
NO_CHANGE
Data on DO and DOP outputs remains unchanged.
Invalidates data on DO and DOP outputs.
No Read on Write
Data on DI and DIP inputs is written into specified
location.
X-Ref Target - Figure 33
Internal
Memory
DO
Data_in
CLK
Data_out = Data_in
DI
WE
DI
XXXX
aa
1111
2222
cc
XXXX
ADDR
DO
bb
dd
0000
MEM(aa)
1111
2222
MEM(dd)
EN
DISABLED
READ
WRITE
MEM(bb)=1111
WRITE
MEM(cc)=2222
READ
DS312-2_05_020905
Figure 33: Waveforms of Block RAM Data Operations with WRITE_FIRST Selected
Setting the WRITE_MODE attribute to a value of
WRITE_FIRST, data is written to the addressed memory
location on an enabled active CLK edge and is also passed
to the DO outputs. WRITE_FIRST timing is shown in the
portion of Figure 33 during which WE is High.
Setting the WRITE_MODE attribute to a value of
READ_FIRST, data already stored in the addressed
location passes to the DO outputs before that location is
overwritten with new data from the DI inputs on an enabled
active CLK edge. READ_FIRST timing is shown in the
portion of Figure 34 during which WE is High.
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Spartan-3E FPGA Family: Functional Description
X-Ref Target - Figure 34
Internal
Memory
DO
Data_in
CLK
Prior stored data
DI
WE
DI
XXXX
aa
1111
2222
XXXX
ADDR
DO
bb
cc
dd
0000
MEM(aa)
old MEM(bb)
old MEM(cc)
MEM(dd)
EN
DISABLED
READ
WRITE
MEM(bb)=1111
WRITE
MEM(cc)=2222
READ
DS312-2_06_020905
Figure 34: Waveforms of Block RAM Data Operations with READ_FIRST Selected
X-Ref Target - Figure 35
Internal
Memory
DO
Data_in
No change during write
DI
CLK
WE
DI
XXXX
aa
1111
2222
cc
XXXX
ADDR
DO
bb
dd
0000
MEM(aa)
MEM(dd)
EN
DISABLED
READ
WRITE
MEM(bb)=1111
WRITE
MEM(cc)=2222
READ
DS312-2_07_020905
Figure 35: Waveforms of Block RAM Data Operations with NO_CHANGE Selected
Setting the WRITE_MODE attribute to a value of
NO_CHANGE, puts the DO outputs in a latched state when
asserting WE. Under this condition, the DO outputs retain
the data driven just before WE is asserted. NO_CHANGE
timing is shown in the portion of Figure 35 during which WE
is High.
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Spartan-3E FPGA Family: Functional Description
product ranging from –17,179,738,112 to
10
Dedicated Multipliers
For additional information, refer to the “Using Embedded
Multipliers” chapter in UG331.
+17,179,869,184 .
10
Implement multipliers with inputs less than 18 bits by
sign-extending the inputs (i.e., replicating the
The Spartan-3E devices provide 4 to 36 dedicated multiplier
blocks per device. The multipliers are located together with
the block RAM in one or two columns depending on device
density. See Arrangement of RAM Blocks on Die for details
on the location of these blocks and their connectivity.
most-significant bit). Wider multiplication operations are
performed by combining the dedicated multipliers and
slice-based logic in any viable combination or by
time-sharing a single multiplier. Perform unsigned
multiplication by restricting the inputs to the positive range.
Tie the most-significant bit Low and represent the unsigned
value in the remaining 17 lesser-significant bits.
Operation
The multiplier blocks primarily perform two’s complement
numerical multiplication but can also perform some less
obvious applications, such as simple data storage and
barrel shifting. Logic slices also implement efficient small
multipliers and thereby supplement the dedicated
multipliers. The Spartan-3E dedicated multiplier blocks
have additional features beyond those provided in
Spartan-3 FPGAs.
Optional Pipeline Registers
As shown in Figure 36, each multiplier block has optional
registers on each of the multiplier inputs and the output. The
registers are named AREG, BREG, and PREG and can be
used in any combination. The clock input is common to all
the registers within a block, but each register has an
independent clock enable and synchronous reset controls
making them ideal for storing data samples and coefficients.
When used for pipelining, the registers boost the multiplier
clock rate, beneficial for higher performance applications.
Each multiplier performs the principle operation P = A × B,
where ‘A’ and ‘B’ are 18-bit words in two’s complement
form, and ‘P’ is the full-precision 36-bit product, also in two’s
complement form. The 18-bit inputs represent values
ranging from –131,072 to +131,071 with a resulting
Figure 36 illustrates the principle features of the multiplier
block.
10
10
X-Ref Target - Figure 36
AREG
(Optional)
CEA
CE
A[17:0]
D
Q
PREG
(Optional)
RST
CEP
CE
D
RSTA
Q
P[35:0]
X
BREG
(Optional)
RST
CEB
CE
RSTP
B[17:0]
D
Q
RST
RSTB
CLK
DS312-2_27_021205
Figure 36: Principle Ports and Functions of Dedicated Multiplier Blocks
Use the MULT18X18SIO primitive shown in Figure 37 to
instantiate a multiplier within a design. Although high-level
logic synthesis software usually automatically infers a
multiplier, adding the pipeline registers might require the
MULT18X18SIO primitive. Connect the appropriate signals
to the MULT18X18SIO multiplier ports and set the individual
AREG, BREG, and PREG attributes to ‘1’ to insert the
associated register, or to 0 to remove it and make the signal
path combinatorial.
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Spartan-3E FPGA Family: Functional Description
X-Ref Target - Figure 37
Cascading Multipliers
MULT18X18SIO
The MULT18X18SIO primitive has two additional ports
called BCIN and BCOUT to cascade or share the
A[17:0]
B[17:0]
CEA
P[35:0]
multiplier’s ‘B’ input among several multiplier bocks. The
18-bit BCIN “cascade” input port offers an alternate input
source from the more typical ‘B’ input. The B_INPUT
attribute specifies whether the specific implementation uses
the BCIN or ‘B’ input path. Setting B_INPUT to DIRECT
chooses the ‘B’ input. Setting B_INPUT to CASCADE
selects the alternate BCIN input. The BREG register then
optionally holds the selected input value, if required.
CEB
CEP
CLK
RSTA
RSTB
RSTP
BCOUT is an 18-bit output port that always reflects the
value that is applied to the multiplier’s second input, which is
either the ‘B’ input, the cascaded value from the BCIN input,
or the output of the BREG if it is inserted.
BCIN[17:0]
BCOUT[17:0]
DS312-2_28_021205
Figure 37: MULT18X18SIO Primitive
Figure 38 illustrates the four possible configurations using
different settings for the B_INPUT attribute and the BREG
attribute.
X-Ref Target - Figure 38
BCOUT[17:0]
BCOUT[17:0]
BREG
CE
X
X
CEB
D
Q
BREG = 0
CLK
B_INPUT = CASCADE
RST
BREG = 1
B_INPUT = CASCADE
RSTB
BCIN[17:0]
BCIN[17:0]
BCOUT[17:0]
BCOUT[17:0]
BREG
X
X
CEB
CE
D
B[17:0]
B[17:0]
Q
BREG = 0
B_INPUT = DIRECT
CLK
RST
BREG = 1
B_INPUT = DIRECT
RSTB
DS312-2_29_021505
Figure 38: Four Configurations of the B Input
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Spartan-3E FPGA Family: Functional Description
The BCIN and BCOUT ports have associated dedicated
routing that connects adjacent multipliers within the same
column. Via the cascade connection, the BCOUT port of
one multiplier block drives the BCIN port of the multiplier
block directly above it. There is no connection to the BCIN
port of the bottom-most multiplier block in a column or a
connection from the BCOUT port of the top-most block in a
column. As an example, Figure 39 shows the multiplier
cascade capability within the XC3S100E FPGA, which has
a single column of multiplier, four blocks tall. For clarity, the
figure omits the register control inputs.
X-Ref Target - Figure 39
BCOUT
A
B
P
P
P
P
B_INPUT = CASCADE
B_INPUT = CASCADE
B_INPUT = CASCADE
B_INPUT = DIRECT
BCIN
BCOUT
A
B
BCIN
BCOUT
A
B
BCIN
BCOUT
A
B
BCIN
DS312-2_30_021505
Figure 39: Multiplier Cascade Connection
When using the BREG register, the cascade connection
forms a shift register structure typically used in DSP
algorithms such as direct-form FIR filters. When the BREG
register is omitted, the cascade structure essentially feeds
the same input value to more than one multiplier. This
parallel connection serves to create wide-input multipliers,
implement transpose FIR filters, and is used in any
application that requires that several multipliers have the
same input value.
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Spartan-3E FPGA Family: Functional Description
The upper 16 bits of the ‘A’ multiplicand input are shared
with the upper 16 bits of the block RAM’s Port A Data input.
Similarly, the upper 16 bits of the ‘B’ multiplicand input are
shared with Port B’s data input. See also Figure 48,
page 63.
Multiplier/Block RAM Interaction
Each multiplier is located adjacent to an 18 Kbit block RAM
and shares some interconnect resources. Configuring an
18 Kbit block RAM for 36-bit wide data (512 x 36 mode)
prevents use of the associated dedicated multiplier.
Table 27 defines each port of the MULT18X18SIO primitive.
Table 27: MULT18X18SIO Embedded Multiplier Primitives Description
Signal Name Direction
A[17:0] Input
Function
The primary 18-bit two’s complement value for multiplication. The block multiplies by this value
asynchronously if the optional AREG and PREG registers are omitted. When AREG and/or
PREG are used, the value provided on this port is qualified by the rising edge of CLK, subject
to the appropriate register controls.
B[17:0]
Input
The second 18-bit two’s complement value for multiplication if the B_INPUT attribute is set to
DIRECT. The block multiplies by this value asynchronously if the optional BREG and PREG
registers are omitted. When BREG and/or PREG are used, the value provided on this port is
qualified by the rising edge of CLK, subject to the appropriate register controls.
BCIN[17:0]
P[35:0]
Input
The second 18-bit two’s complement value for multiplication if the B_INPUT attribute is set to
CASCADE. The block multiplies by this value asynchronously if the optional BREG and PREG
registers are omitted. When BREG and/or PREG are used, the value provided on this port is
qualified by the rising edge of CLK, subject to the appropriate register controls.
Output
The 36-bit two’s complement product resulting from the multiplication of the two input values
applied to the multiplier. If the optional AREG, BREG and PREG registers are omitted, the
output operates asynchronously. Use of PREG causes this output to respond to the rising edge
of CLK with the value qualified by CEP and RSTP. If PREG is omitted, but AREG and BREG
are used, this output responds to the rising edge of CLK with the value qualified by CEA, RSTA,
CEB, and RSTB. If PREG is omitted and only one of AREG or BREG is used, this output
responds to both asynchronous and synchronous events.
BCOUT[17:0]
CEA
Output
Input
The value being applied to the second input of the multiplier. When the optional BREG register
is omitted, this output responds asynchronously in response to changes at the B[17:0] or
BCIN[17:0] ports according to the setting of the B_INPUT attribute. If BREG is used, this output
responds to the rising edge of CLK with the value qualified by CEB and RSTB.
Clock enable qualifier for the optional AREG register. The value provided on the A[17:0] port is
captured by AREG in response to a rising edge of CLK when this signal is High, provided that
RSTA is Low.
RSTA
CEB
Input
Input
Synchronous reset for the optional AREG register. AREG content is forced to the value zero in
response to a rising edge of CLK when this signal is High.
Clock enable qualifier for the optional BREG register. The value provided on the B[17:0] or
BCIN[17:0] port is captured by BREG in response to a rising edge of CLK when this signal is
High, provided that RSTB is Low.
RSTB
CEP
Input
Input
Synchronous reset for the optional BREG register. BREG content is forced to the value zero in
response to a rising edge of CLK when this signal is High.
Clock enable qualifier for the optional PREG register. The value provided on the output of the
multiplier port is captured by PREG in response to a rising edge of CLK when this signal is High,
provided that RSTP is Low.
RSTP
Input
Synchronous reset for the optional PREG register. PREG content is forced to the value zero in
response to a rising edge of CLK when this signal is High.
Notes:
1. The control signals CLK, CEA, RSTA, CEB, RSTB, CEP, and RSTP have the option of inverted polarity.
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Spartan-3E FPGA Family: Functional Description
surrounded by CLBs within the logic array and is no longer
located at the top and bottom of a column of block RAM as
in the Spartan-3 architecture. The Digital Clock Manager is
instantiated within a design using a “DCM” primitive.
Digital Clock Managers (DCMs)
For additional information, refer to the “Using Digital Clock
Managers (DCMs)” chapter in UG331.
The DCM supports three major functions:
Differences from the Spartan-3 Architecture
•
Clock-skew Elimination: Clock skew within a system
occurs due to the different arrival times of a clock signal
at different points on the die, typically caused by the
clock signal distribution network. Clock skew increases
setup and hold time requirements and increases
clock-to-out times, all of which are undesirable in high
frequency applications. The DCM eliminates clock
skew by phase-aligning the output clock signal that it
generates with the incoming clock signal. This
mechanism effectively cancels out the clock distribution
delays.
•
•
•
Spartan-3E FPGAs have two, four, or eight DCMs,
depending on device size.
The variable phase shifting feature functions differently
on Spartan-3E FPGAs than from Spartan-3 FPGAs.
The Spartan-3E DLLs support lower input frequencies,
down to 5 MHz. Spartan-3 DLLs support down to
18 MHz.
Overview
Spartan-3E FPGA Digital Clock Managers (DCMs) provide
flexible, complete control over clock frequency, phase shift
and skew. To accomplish this, the DCM employs a
Delay-Locked Loop (DLL), a fully digital control system that
uses feedback to maintain clock signal characteristics with a
high degree of precision despite normal variations in
operating temperature and voltage. This section provides a
fundamental description of the DCM.
•
•
Frequency Synthesis: The DCM can generate a wide
range of different output clock frequencies derived from
the incoming clock signal. This is accomplished by
either multiplying and/or dividing the frequency of the
input clock signal by any of several different factors.
Phase Shifting: The DCM provides the ability to shift
the phase of all its output clock signals with respect to
the input clock signal.
The XC3S100E FPGA has two DCMs, one at the top and
one at the bottom of the device. The XC3S250E and
XC3S500E FPGAs each include four DCMs, two at the top
and two at the bottom. The XC3S1200E and XC3S1600E
FPGAs contain eight DCMs with two on each edge (see
also Figure 45). The DCM in Spartan-3E FPGAs is
Although a single design primitive, the DCM consists of four
interrelated functional units: the Delay-Locked Loop (DLL),
the Digital Frequency Synthesizer (DFS), the Phase Shifter
(PS), and the Status Logic. Each component has its
associated signals, as shown in Figure 40.
X-Ref Target - Figure 40
DCM
PSINCDEC
PSEN
Phase
Shifter
PSDONE
PSCLK
Clock
CLK0
Distribution
CLKIN
CLKFB
CLK90
Delay
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
CLKFX
DFS
CLKFX180
DLL
LOCKED
Status
Logic
RST
8
STATUS [7:0]
DS099-2_07_101205
Figure 40: DCM Functional Blocks and Associated Signals
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Spartan-3E FPGA Family: Functional Description
Delay-Locked Loop (DLL)
The most basic function of the DLL component is to
eliminate clock skew. The main signal path of the DLL
consists of an input stage, followed by a series of discrete
delay elements or steps, which in turn leads to an output
stage. This path together with logic for phase detection and
control forms a system complete with feedback as shown in
Figure 41. In Spartan-3E FPGAs, the DLL is implemented
using a counter-based delay line.
The DLL component has two clock inputs, CLKIN and
CLKFB, as well as seven clock outputs, CLK0, CLK90,
CLK180, CLK270, CLK2X, CLK2X180, and CLKDV as
described in Table 28. The clock outputs drive
simultaneously. Signals that initialize and report the state of
the DLL are discussed in Status Logic.
X-Ref Target - Figure 41
CLK0
CLK90
CLK180
CLK270
CLK2X
Delay
1
Delay
2
Delay
n-1
Delay
n
CLKIN
CLK2X180
CLKDV
Control
LOCKED
Phase
Detection
CLKFB
RST
DS099-2_08_041103
Figure 41: Simplified Functional Diagram of DLL
Table 28: DLL Signals
Signal Direction
CLKIN
Description
Input
Input
Receives the incoming clock signal. See Table 30, Table 31, and Table 32 for optimal external
inputs to a DCM.
CLKFB
Accepts either CLK0 or CLK2X as the feedback signal. (Set the CLK_FEEDBACK attribute
accordingly).
CLK0
Output
Output
Output
Output
Output
Output
Generates a clock signal with the same frequency and phase as CLKIN.
CLK90
Generates a clock signal with the same frequency as CLKIN, phase-shifted by 90°.
Generates a clock signal with the same frequency as CLKIN, phase-shifted by 180°.
Generates a clock signal with the same frequency as CLKIN, phase-shifted by 270°.
Generates a clock signal with the same phase as CLKIN, and twice the frequency.
CLK180
CLK270
CLK2X
CLK2X180
Generates a clock signal with twice the frequency of CLKIN, and phase-shifted 180° with respect
to CLK2X.
CLKDV
Output
Divides the CLKIN frequency by CLKDV_DIVIDE value to generate lower frequency clock signal
that is phase-aligned to CLKIN.
The clock signal supplied to the CLKIN input serves as a
reference waveform. The DLL seeks to align the rising-edge
of feedback signal at the CLKFB input with the rising-edge
of CLKIN input. When eliminating clock skew, the common
approach to using the DLL is as follows: The CLK0 signal is
passed through the clock distribution network that feeds all
the registers it synchronizes. These registers are either
internal or external to the FPGA. After passing through the
clock distribution network, the clock signal returns to the
DLL via a feedback line called CLKFB. The control block
inside the DLL measures the phase error between CLKFB
and CLKIN. This phase error is a measure of the clock skew
that the clock distribution network introduces. The control
block activates the appropriate number of delay steps to
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Spartan-3E FPGA Family: Functional Description
DLL Attributes and Related Functions
cancel out the clock skew. When the DLL phase-aligns the
CLK0 signal with the CLKIN signal, it asserts the LOCKED
output, indicating a lock on to the CLKIN signal.
The DLL unit has a variety of associated attributes as
described in Table 29. Each attribute is described in detail in
the sections that follow.
Table 29: DLL Attributes
Attribute
Description
Values
CLK_FEEDBACK
CLKIN_DIVIDE_BY_2
CLKDV_DIVIDE
Chooses either the CLK0 or CLK2X output to drive NONE, 1X, 2X
the CLKFB input
Halves the frequency of the CLKIN signal just as it FALSE, TRUE
enters the DCM
Selects the constant used to divide the CLKIN input 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6.0, 6.5, 7.0,
frequency to generate the CLKDV output frequency 7.5, 8, 9, 10, 11, 12, 13, 14, 15, and 16
CLKIN_PERIOD
Additional information that allows the DLL to
operate with the most efficient lock time and the
best jitter tolerance
Floating-point value representing the
CLKIN period in nanoseconds
DLL Clock Input Connections
For best results, an external clock source enters the FPGA
via a Global Clock Input (GCLK). Each specific DCM has
four possible direct, optimal GCLK inputs that feed the
DCM’s CLKIN input, as shown in Table 30. Table 30 also
provides the specific pin numbers by package for each
GCLK input. The two additional DCM’s on the XC3S1200E
and XC3S1600E have similar optimal connections from the
left-edge LHCLK and the right-edge RHCLK inputs, as
described in Table 31 and Table 32.
Design Note
Avoid using global clock input GCLK1 as it is always shared
with the M2 mode select pin. Global clock inputs GCLK0,
GCLK2, GCLK3, GCLK12, GCLK13, GCLK14, and
GCLK15 have shared functionality in some configuration
modes.
•
The DCM supports differential clock inputs (for
example, LVDS, LVPECL_25) via a pair of GCLK inputs
that feed an internal single-ended signal to the DCM’s
CLKIN input.
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Spartan-3E FPGA Family: Functional Description
Table 30: Direct Clock Input Connections and Optional External Feedback to Associated DCMs
Differential Pair Differential Pair Differential Pair
Differential Pair
Package
N
P
N
P
N
P
N
P
Pin Number for Single-Ended Input
Pin Number for Single-Ended Input
VQ100
CP132
TQ144
PQ208
FT256
FG320
FG400
FG484
P91
B7
P90
A7
P89
C8
P88
B8
P86
A9
P85
B9
P84
C9
P83
A10
P131
P186
D8
P130
P185
C8
P129
P184
B8
P128
P183
A8
P126
P181
A9
P125
P180
A10
P123
P178
F9
P122
P177
E9
D9
C9
B9
B8
A10
E10
C12
B10
E10
G11
E12
D10
F11
A9
A10
C11
G10
H11
H10
H12
E11
B11
B12
F12
Associated Global Buffers
GCLK11 GCLK10 GCLK9
GCLK8
GCLK7
GCLK6
GCLK5
GCLK4
Top Left DCM
Top Right DCM
XC3S100: N/A
XC3S100: DCM_X0Y1
XC3S250E, XC3S500E: DCM_X0Y1
XC3S1200E, XC3S1600E: DCM_X1Y3
XC3S250E, XC3S500E: DCM_X1Y1
XC3S1200E, XC3S1600E: DCM_X2Y3
H
G
F
E
Clock Line (see Table 41)
D
C
B
A
Bottom Left DCM
XC3S100: N/A
Bottom Right DCM
XC3S100: DCM_X0Y0
XC3S250E, XC3S500E: DCM_X0Y0
XC3S1200E, XC3S1600E: DCM_X1Y0
XC3S250E, XC3S500E: DCM_X1Y0
XC3S1200E, XC3S1600E: DCM_X2Y0
GCLK12 GCLK13 GCLK14 GCLK15
GCLK0
GCLK1
GCLK2
GCLK3
Associated Global Buffers
Differential Pair
Differential Pair
Differential Pair
Differential Pair
Package
P
N
P
N
P
N
P
N
Pin Number for Single-Ended Input
Pin Number for Single-Ended Input
VQ100
CP132
TQ144
PQ208
FT256
FG320
FG400
FG484
P32
M4
P33
N4
P35
M5
P36
N5
P38
M6
P39
N6
P40
P6
P41
P7
P50
P74
M8
P51
P75
L8
P53
P77
N8
P54
P78
P8
P56
P80
T9
P57
P81
R9
P58
P82
P9
P59
P83
N9
N9
M9
U9
V9
U10
P11
R12
T10
P12
P12
R10
V10
Y12
P10
V11
W12
W9
V11
W10
U11
R10
R11
P10
T11
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Spartan-3E FPGA Family: Functional Description
Table 31: Direct Clock Input and Optional External Feedback to Left-Edge DCMs (XC3S1200E and XC3S1600E)
Single-Ended Pin Number by Package Type
Left Edge
Diff.
Clock
VQ100 CP132 TQ144 PQ208 FT256 FG320 FG400 FG484
LHCLK
DCM/BUFGMUX
BUFGMUX_X0Y5
BUFGMUX_X0Y4
D
C
P
N
P
N
P9
F3
F2
F1
G1
P14
P15
P16
P17
P22
P23
P24
P25
H5
H6
H3
H4
J5
J4
J1
J2
K3
K2
K7
L7
M5
L5
LHCLK0
LHCLK1
LHCLK2
LHCLK3
P10
P11
P12
DCM_X0Y2
L8
M8
BUFGMUX_X0Y3
BUFGMUX_X0Y2
B
A
BUFGMUX_X0Y9
BUFGMUX_X0Y8
H
G
P
N
P
N
P15
P16
P17
P18
G3
H1
H2
H3
P20
P21
P22
P23
P28
P29
P30
P31
J2
J3
J5
J4
K3
K4
K6
K5
M1
L1
M1
N1
M3
M4
LHCLK4
LHCLK5
LHCLK6
LHCLK7
DCM_X0Y1
M3
L3
BUFGMUX_X0Y7
BUFGMUX_X0Y6
F
E
Table 32: Direct Clock Input and Optional External Feedback to Right-Edge DCMs (XC3S1200E and XC3S1600E)
Right Edge
DCM/BUFGMUX
Single-Ended Pin Number by Package Type
Diff.
Clock
RHCLK
VQ100 CP132 TQ144 PQ208 FT256 FG320 FG400 FG484
D
C
BUFGMUX_X3Y5
BUFGMUX_X3Y4
RHCLK7
RHCLK6
RHCLK5
RHCLK4
P68
P67
P66
P65
G13
G14
H12
H13
P94
P93
P92
P91
P135
P134
P133
P132
H11
H12
H14
H15
J14
J15
J16
J17
J20
K20
K14
K13
L19
L18
L21
L20
N
P
N
P
DCM_X3Y2
B
A
BUFGMUX_X3Y3
BUFGMUX_X3Y2
H
G
BUFGMUX_X3Y9
BUFGMUX_X3Y8
RHCLK3
RHCLK2
RHCLK1
RHCLK0
P63
P62
P61
P60
J14
J13
J12
K14
P88
P87
P86
P85
P129
P128
P127
P126
J13
J14
J16
K16
K14
K15
K12
K13
L14
L15
L16
M16
M16
M15
M22
N22
N
P
N
P
DCM_X3Y1
F
E
BUFGMUX_X3Y7
BUFGMUX_X3Y6
Every FPGA input provides a possible DCM clock input, but
the path is not temperature and voltage compensated like
the GCLKs. Alternatively, clock signals within the FPGA
optionally provide a DCM clock input via a Global Clock
Multiplexer Buffer (BUFGMUX). The global clock net
connects directly to the CLKIN input. The internal and
external connections are shown in Figure 42a and
Figure 42c, respectively.
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Spartan-3E FPGA Family: Functional Description
Two basic cases determine how to connect the DLL clock
outputs and feedback connections: on-chip synchronization
and off-chip synchronization, which are illustrated in
Figure 42a through Figure 42d.
DLL Clock Output and Feedback Connections
As many as four of the nine DCM clock outputs can
simultaneously drive four of the BUFGMUX buffers on the
same die edge. All DCM clock outputs can simultaneously
drive general routing resources, including interconnect
leading to OBUF buffers.
In the on-chip synchronization case in Figure 42a and
Figure 42b, it is possible to connect any of the DLL’s seven
output clock signals through general routing resources to
the FPGA’s internal registers. Either a Global Clock Buffer
(BUFG) or a BUFGMUX affords access to the global clock
network. As shown in Figure 42a, the feedback loop is
created by routing CLK0 (or CLK2X) in Figure 42b to a
global clock net, which in turn drives the CLKFB input.
The feedback loop is essential for DLL operation. Either the
CLK0 or CLK2X outputs feed back to the CLKFB input via a
BUFGMUX global buffer to eliminate the clock distribution
delay. The specific BUFGMUX buffer used to feed back the
CLK0 or CLK2X signal is ideally one of the BUFGMUX
buffers associated with a specific DCM, as shown in
Table 30, Table 31, and Table 32.
In the off-chip synchronization case in Figure 42c and
Figure 42d, CLK0 (or CLK2X) plus any of the DLL’s other
output clock signals exit the FPGA using output buffers
(OBUF) to drive an external clock network plus registers on
the board. As shown in Figure 42c, the feedback loop is
formed by feeding CLK0 (or CLK2X) in Figure 42d back into
the FPGA, then to the DCM’s CLKFB input via a Global
Buffer Input, specified in Table 30.
The feedback path also phase-aligns the other seven DLL
outputs: CLK0, CLK90, CLK180, CLK270, CLKDV, CLK2X,
or CLK2X180. The CLK_FEEDBACK attribute value must
agree with the physical feedback connection. Use “1X” for
CLK0 feedback and “2X” for CLK2X feedback. If the DFS
unit is used stand-alone, without the DLL, then no feedback
is required and set the CLK_FEEDBACK attribute to
“NONE”.
X-Ref Target - Figure 42
FPGA
FPGA
BUFGMUX
BUFGMUX
CLK0
CLK90
CLK180
CLK270
CLKDV
CLK90
CLK180
CLK270
CLKDV
CLK2X
CLK2X180
BUFG
BUFG
CLKIN
CLKIN
Clock
Net Delay
Clock
Net Delay
DCM
DCM
CLK2X180
CLK2X
CLKFB
CLKFB
CLK0
BUFGMUX
BUFGMUX
CLK0
CLK2X
(a) On-Chip with CLK0 Feedback
FPGA
(b) On-Chip with CLK2X Feedback
FPGA
OBUF
CLK0
CLK90
CLK180
CLK270
CLKDV
CLK90
CLK180
CLK270
CLKDV
CLK2X
CLK2X180
OBUF
IBUFG
IBUFG
CLKIN
CLKIN
Clock
Net Delay
Clock
Net Delay
DCM
DCM
CLK2X180
CLKFB
CLK0
CLKFB
CLK2X
OBUF
IBUFG
IBUFG
OBUF
CLK0
CLK2X
(c) Off-Chip with CLK0 Feedback
(d) Off-Chip with CLK2X Feedback
DS099-2_09_082104
Figure 42: Input Clock, Output Clock, and Feedback Connections for the DLL
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Spartan-3E FPGA Family: Functional Description
multiple (for multiplication) of the incoming clock frequency.
The CLK2X output produces an in-phase signal that is twice
the frequency of CLKIN. The CLK2X180 output also
doubles the frequency, but is 180° out-of-phase with respect
to CLKIN. The CLKDIV output generates a clock frequency
that is a predetermined fraction of the CLKIN frequency.
The CLKDV_DIVIDE attribute determines the factor used to
divide the CLKIN frequency. The attribute can be set to
various values as described in Table 29. The basic
Accommodating Input Frequencies Beyond Spec-
ified Maximums
If the CLKIN input frequency exceeds the maximum
permitted, divide it down to an acceptable value using the
CLKIN_DIVIDE_BY_2 attribute. When this attribute is set to
“TRUE”, the CLKIN frequency is divided by a factor of two
as it enters the DCM. In addition, the CLKIN_DIVIDE_BY_2
option produces a 50% duty-cycle on the input clock,
although at half the CLKIN frequency.
frequency synthesis outputs are described in Table 28.
Quadrant and Half-Period Phase Shift Outputs
Duty Cycle Correction of DLL Clock Outputs
In addition to CLK0 for zero-phase alignment to the CLKIN
signal, the DLL also provides the CLK90, CLK180, and
CLK270 outputs for 90°, 180°, and 270° phase-shifted
signals, respectively. These signals are described in
Table 28, page 48 and their relative timing is shown in
Figure 43. For control in finer increments than 90°, see
Phase Shifter (PS).
The DLL output signals exhibit a 50% duty cycle, even if the
incoming CLKIN signal has a different duty cycle.
Fifty-percent duty cycle means that the High and Low times
of each clock cycle are equal.
DLL Performance Differences Between Steppings
As indicated in Digital Clock Manager (DCM) Timing
(Module 3), the Stepping 1 revision silicon supports higher
maximum input and output frequencies. Stepping 1 devices
are backwards compatible with Stepping 0 devices.
X-Ref Target - Figure 43
0o 90o 180o 270o 0o 90o 180o 270o 0o
Phase:
Input Signal (40%/60% Duty Cycle)
Digital Frequency Synthesizer (DFS)
t
The DFS unit generates clock signals where the output
frequency is a product of the CLKIN input clock frequency
and a ratio of two user-specified integers. The two
dedicated outputs from the DFS unit, CLKFX and
CLKFX180, are defined in Table 33.
CLKIN
Output Signal - Duty Cycle Corrected
Table 33: DFS Signals
CLK0
Signal
CLKFX
Direction
Description
CLK90
CLK180
CLK270
Output
Multiplies the CLKIN frequency by
the attribute-value ratio
(CLKFX_MULTIPLY/
CLKFX_DIVIDE) to generate a
clock signal with a new target
frequency.
CLKFX180
Output
Generates a clock signal with the
same frequency as CLKFX, but
shifted 180° out-of-phase.
CLK2X
CLK2X180
CLKDV
The signal at the CLKFX180 output is essentially an
inversion of the CLKFX signal. These two outputs always
exhibit a 50% duty cycle, even when the CLKIN signal does
not. The DFS clock outputs are active coincident with the
seven DLL outputs and their output phase is controlled by
the Phase Shifter unit (PS).
DS099-2_10_101105
Figure 43: Characteristics of the DLL Clock Outputs
The output frequency (f
incoming clock frequency (f
attributes, as follows.
) of the DFS is a function of the
) and two integer
CLKFX
Basic Frequency Synthesis Outputs
CLKIN
The DLL component provides basic options for frequency
multiplication and division in addition to the more flexible
synthesis capability of the DFS component, described in a
later section. These operations result in output clock signals
with frequencies that are either a fraction (for division) or a
CLKFX_MULTIPLY
CLKFX_DIVIDE
f
= f
• ---------------------------------------------------
Eq 1
CLKFX
CLKIN
The CLKFX_MULTIPLY attribute is an integer ranging from
2 to 32, inclusive, and forms the numerator in Equation 1.
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Spartan-3E FPGA Family: Functional Description
The CLKFX_DIVIDE is an integer ranging from 1 to 32,
inclusive and forms the denominator in Equation 1. For
example, if CLKFX_MULTIPLY = 5 and CLKFX_DIVIDE = 3,
the frequency of the output clock signal is 5/3 that of the
input clock signal. These attributes and their acceptable
ranges are described in Table 34.
periods, which is equivalent in time to five CLKFX output
periods.
Smaller CLKFX_MULTIPLY and CLKFX_DIVIDE values
result in faster lock times. Therefore, CLKFX_MULTIPLY
and CLKFX_DIVIDE must be factored to reduce their values
wherever possible. For example, given CLKFX_MULTIPLY
= 9 and CLKFX_DIVIDE = 6, removing a factor of three
yields CLKFX_MULTIPLY = 3 and CLKFX_DIVIDE = 2.
While both value-pairs result in the multiplication of clock
frequency by 3/2, the latter value-pair enables the DLL to
lock more quickly.
Table 34: DFS Attributes
Attribute
Description
Values
CLKFX_MULTIPLY
Frequency multiplier Integer from 2
constant
to 32, inclusive
CLKFX_DIVIDE
Frequency divisor
constant
Integer from 1
to 32, inclusive
Phase Shifter (PS)
Any combination of integer values can be assigned to the
CLKFX_MULTIPLY and CLKFX_DIVIDE attributes,
provided that two conditions are met:
The DCM provides two approaches to controlling the phase
of a DCM clock output signal relative to the CLKIN signal:
First, eight of the nine DCM clock outputs – CLK0, CLK90,
CLK180, CLK270, CLK2X, CLK2X180, CLKFX, and
CLKFX180 – provide either quadrant or half-period phase
shifting of the input clock.
1. The two values fall within their corresponding ranges,
as specified in Table 34.
2. The f
output frequency calculated in Equation 1
CLKFX
Second, the PS unit provides additional fine phase shift
control of all nine DCM outputs. The PS unit accomplishes
falls within the DCM’s operating frequency
specifications (see Table 107 in Module 3).
this by introducing a “fine phase shift” delay (T ) between
PS
the CLKFB and CLKIN signals inside the DLL unit. In FIXED
phase shift mode, the fine phase shift is specified at design
DFS With or Without the DLL
Although the CLKIN input is shared with both units, the DFS
unit functions with or separately from the DLL unit. Separate
from the DLL, the DFS generates an output frequency from
the CLKIN frequency according to the respective
CLKFX_MULTIPLY and CLKFX_DIVIDE values. Frequency
synthesis does not require a feedback loop. Furthermore,
without the DLL, the DFS unit supports a broader operating
frequency range.
1
th
time with a resolution down to /
of a CLKIN cycle or
256
one delay step (DCM_DELAY_STEP), whichever is greater.
This fine phase shift value is relative to the coarser quadrant
or half-period phase shift of the DCM clock output. When
used, the PS unit shifts the phase of all nine DCM clock
output signals.
Enabling Phase Shifting and Selecting an Operat-
ing Mode
With the DLL, the DFS unit operates as described above,
only with the additional benefit of eliminating the clock
distribution delay. In this case, a feedback loop from the
CLK0 or CLK2X output to the CLKFB input must be present.
The CLKOUT_PHASE_SHIFT attribute controls the PS unit
for the specific DCM instantiation. As described in Table 35,
this attribute has three possible values: NONE, FIXED, and
VARIABLE. When CLKOUT_PHASE_SHIFT = NONE, the
PS unit is disabled and the DCM output clocks are
phase-aligned to the CLKIN input via the CLKFB feedback
path. Figure 44a shows this case.
When operating with the DLL unit, the DFS’s CLKFX and
CLKFX180 outputs are phase-aligned with the CLKIN input
every CLKFX_DIVIDE cycles of CLKIN and every
CLKFX_MULTIPLY cycles of CLKFX. For example, when
CLKFX_MULTIPLY = 5 and CLKFX_DIVIDE = 3, the input
and output clock edges coincide every three CLKIN input
The PS unit is enabled when the CLKOUT_PHASE_SHIFT
attribute is set to FIXED or VARIABLE modes. These two
modes are described in the sections that follow.
Table 35: PS Attributes
Attribute
Description
Disables the PS component or chooses between Fixed
Values
CLKOUT_PHASE_SHIFT
NONE, FIXED, VARIABLE
Phase and Variable Phase modes.
PHASE_SHIFT
Determines size and direction of initial fine phase shift.
Integers from –255 to +255
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Spartan-3E FPGA Family: Functional Description
FIXED Phase Shift prior to ISE 8.1i, Service Pack 3: See
Equation 3. The value corresponds to a phase shift range of
–180° to +180° degrees, which is different from the
Spartan-3 DCM design primitive and simulation model.
Designs created prior to ISE 8.1i, Service Pack 3 must be
recompiled using the most recent ISE development
software.
FIXED Phase Shift Mode
The FIXED phase shift mode shifts the DCM outputs by a
fixed amount (T ), controlled by the user-specified
PS
PHASE_SHIFT attribute. The PHASE_SHIFT value (shown
as P in Figure 44) must be an integer ranging from –255 to
+255. PHASE_SHIFT specifies a phase shift delay as a
fraction of the T
The phase shift behavior is different
CLKIN.
PHASESHIFT
between ISE 8.1, Service Pack 3 and prior software
versions, as described below.
t
=
---------------------------------------- • T
Eq 3
PS
CLKIN
512
When the PHASE_SHIFT value is zero, CLKFB and CLKIN
are in phase, the same as when the PS unit is disabled.
When the PHASE_SHIFT value is positive, the DCM
outputs are shifted later in time with respect to CLKIN input.
When the attribute value is negative, the DCM outputs are
shifted earlier in time with respect to CLKIN.
Design Note
Prior to ISE 8.1i, Service Pack 3, the FIXED phase shift
feature operated differently than the Spartan-3 DCM design
primitive and simulation model. Designs using software
prior to ISE 8.1i, Service Pack 3 require recompilation using
the latest ISE software release. The following Answer
Record contains additional information:
Figure 44b illustrates the relationship between CLKFB and
CLKIN in the Fixed Phase mode. In the Fixed Phase mode,
the PSEN, PSCLK, and PSINCDEC inputs are not used
and must be tied to GND.
http://www.xilinx.com/support/answers/23153.htm.
FIXED Phase Shift using ISE 8.1i, Service Pack 3 and
later: See Equation 2. The value corresponds to a phase
shift range of –360° to +360°, which matches behavior of
the Spartan-3 DCM design primitive and simulation model.
Equation 2 or Equation 3 applies only to FIXED phase shift
mode. The VARIABLE phase shift mode operates
differently.
PHASESHIFT
t
=
---------------------------------------- • T
Eq 2
PS
CLKIN
256
X-Ref Target - Figure 44
a. CLKOUT_PHASE_SHIFT = NONE
CLKIN
CLKFB
(via CLK0 or CLK2X feedback)
b. CLKOUT_PHASE_SHIFT = FIXED
CLKIN
0
–255
+255
Shift Range over all P Values:
P
256
* T
CLKIN
CLKFB
(via CLK0 or CLK2X feedback)
DS312-2_61_021606
Figure 44: NONE and FIXED Phase Shifter Waveforms (ISE 8.1i, Service Pack 3 and later)
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55
Spartan-3E FPGA Family: Functional Description
VARIABLE Phase Shift Mode
In VARIABLE phase shift mode, the FPGA application
dynamically adjusts the fine phase shift value using three
inputs to the PS unit (PSEN, PSCLK, and PSINCDEC), as
defined in Table 36 and shown in Figure 40.
Table 36: Signals for Variable Phase Mode
Signal
PSEN(1)
Direction
Input
Description
Enables the Phase Shift unit for variable phase adjustment.
PSCLK(1)
Input
Input
Clock to synchronize phase shift adjustment.
PSINCDEC(1)
When High, increments the current phase shift value. When Low, decrements the current
phase shift value. This signal is synchronized to the PSCLK signal.
PSDONE
Output
Goes High to indicate that the present phase adjustment is complete and PS unit is ready for
next phase adjustment request. This signal is synchronized to the PSCLK signal.
Notes:
1. This input supports either a true or inverted polarity.
The FPGA application uses the three PS inputs on the
Phase Shift unit to dynamically and incrementally increase
or decrease the phase shift amount on all nine DCM clock
outputs.
phase shift range measured in time and not steps, use
MAX_STEPS derived in Equation 6 and Equation 7 for
VALUE in Equation 4 and Equation 5.
If CLKIN < 60 MHz:
To adjust the current phase shift value, the PSEN enable
signal must be High to enable the PS unit. Coincidently,
PSINCDEC must be High to increment the current phase
shift amount or Low to decrement the current amount. All
VARIABLE phase shift operations are controlled by the
PSCLK input, which can be the CLKIN signal or any other
clock signal.
MAX_STEPS = [INTEGER(10 • (T
– 3))]
– 3))]
Eq 6
Eq 7
CLKIN
If CLKIN ≥ 60 MHz:
MAX_STEPS = [INTEGER(15 • (T
CLKIN
The phase adjustment might require as many as 100 CLKIN
cycles plus 3 PSCLK cycles to take effect, at which point the
DCM’s PSDONE output goes High for one PSCLK cycle.
This pulse indicates that the PS unit completed the previous
adjustment and is now ready for the next request.
Design Note
The VARIABLE phase shift feature operates differently from
the Spartan-3 DCM; use the DCM_SP primitive, not the
DCM primitive.
Asserting the Reset (RST) input returns the phase shift to
zero.
DCM_DELAY_STEP
DCM_DELAY_STEP is the finest delay resolution available
in the PS unit. Its value is provided at the bottom of
Table 105 in Module 3. For each enabled PSCLK cycle that
PSINCDEC is High, the PS unit adds one DCM_
DELAY_STEP of phase shift to all nine DCM outputs.
Similarly, for each enabled PSCLK cycle that PSINCDEC is
Low, the PS unit subtracts one DCM_ DELAY_STEP of
phase shift from all nine DCM outputs.
Because each DCM_DELAY_STEP has a minimum and
maximum value, the actual phase shift delay for the present
phase increment/decrement value (VALUE) falls within the
minimum and maximum values according to Equation 4 and
Equation 5.
T
T
(Max) = VALUE • DCM_DELAY_STEP_MAX Eq 4
PS
Eq 5
(Min) = VALUE • DCM_DELAY_STEP_MIN
PS
The maximum variable phase shift steps, MAX_STEPS, is
described in Equation 6 or Equation 7, for a given CLKIN
input period, T
, in nanoseconds. To convert this to a
CLKIN
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Spartan-3E FPGA Family: Functional Description
Status Logic
The Status Logic indicates the present state of the DCM
and a means to reset the DCM to its initial known state. The
Status Logic signals are described in Table 37.
frequency. The RST signal must be asserted for three or
more CLKIN cycles. A DCM reset does not affect attribute
values (for example, CLKFX_MULTIPLY and
CLKFX_DIVIDE). If not used, RST is tied to GND.
In general, the Reset (RST) input is only asserted upon
configuring the FPGA or when changing the CLKIN
The eight bits of the STATUS bus are described in Table 38.
Table 37: Status Logic Signals
Signal
Direction
Input
Description
RST
A High resets the entire DCM to its initial power-on state. Initializes the DLL taps for a delay of
zero. Sets the LOCKED output Low. This input is asynchronous.
STATUS[7:0]
LOCKED
Output
Output
The bit values on the STATUS bus provide information regarding the state of DLL and PS
operation
Indicates that the CLKIN and CLKFB signals are in phase by going High. The two signals are
out-of-phase when Low.
Table 38: DCM Status Bus
Bit
0
Name
Reserved
Description
-
1
CLKIN Stopped
CLKFX Stopped
Reserved
When High, indicates that the CLKIN input signal is not toggling. When Low, indicates CLKIN is toggling.
This bit functions only when the CLKFB input is connected.(1)
2
When High, indicates that the CLKFX output is not toggling. When Low, indicates the CLKFX output is
toggling. This bit functions only when the CLKFX or CLKFX180 output are connected.
3-6
-
Notes:
1. When only the DFS clock outputs but none of the DLL clock outputs are used, this bit does not go High when the CLKIN signal stops.
Stabilizing DCM Clocks Before User Mode
Spread Spectrum
The STARTUP_WAIT attribute shown in Table 39 optionally
delays the end of the FPGA’s configuration process until
after the DCM locks to its incoming clock frequency. This
option ensures that the FPGA remains in the Startup phase
of configuration until all clock outputs generated by the
DCM are stable. When all DCMs that have their
DCMs accept typical spread spectrum clocks as long as
they meet the input requirements. The DLL will track the
frequency changes created by the spread spectrum clock to
drive the global clocks to the FPGA logic. See XAPP469,
Spread-Spectrum Clocking Reception for Displays for
details.
STARTUP_WAIT attribute set to TRUE assert the LOCKED
signal, then the FPGA completes its configuration process
and proceeds to user mode. The associated bitstream
generator (BitGen) option LCK_cycle specifies one of the
six cycles in the Startup phase. The selected cycle defines
the point at which configuration stalls until all the LOCKED
outputs go High. See Start-Up, page 106 for more
information.
Table 39: STARTUP_WAIT Attribute
Attribute
Description
Values
STARTUP_WAIT
When TRUE, delays TRUE, FALSE
transition from
configuration to user
mode until DCM
locks to the input
clock.
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Spartan-3E FPGA Family: Functional Description
High or Low time of either input clock. The two clock inputs
can be asynchronous with regard to each other, and the S
input can change at any time, except for a short setup time
prior to the rising edge of the presently selected clock (I0 or
I1). This setup time is specified as TGSI in Table 101,
page 137. Violating this setup time requirement possibly
results in an undefined runt pulse output.
Clocking Infrastructure
For additional information, refer to the “Using Global Clock
Resources” chapter in UG331.
The Spartan-3E clocking infrastructure, shown in Figure 45,
provides a series of low-capacitance, low-skew interconnect
lines well-suited to carrying high-frequency signals
throughout the FPGA. The infrastructure also includes the
clock inputs and BUFGMUX clock buffers/multiplexers. The
Xilinx Place-and-Route (PAR) software automatically routes
high-fanout clock signals using these resources.
Table 40: BUFGMUX Select Mechanism
S Input
O Output
I0 Input
0
1
I1 Input
Clock Inputs
The BUFG clock buffer primitive drives a single clock signal
onto the clock network and is essentially the same element
as a BUFGMUX, just without the clock select mechanism.
Similarly, the BUFGCE primitive creates an enabled clock
buffer using the BUFGMUX select mechanism.
Clock pins accept external clock signals and connect
directly to DCMs and BUFGMUX elements. Each
Spartan-3E FPGA has:
•
•
•
16 Global Clock inputs (GCLK0 through GCLK15)
located along the top and bottom edges of the FPGA
The I0 and I1 inputs to an BUFGMUX element originate
from clock input pins, DCMs, or Double-Line interconnect,
as shown in Figure 46. As shown in Figure 45, there are 24
BUFGMUX elements distributed around the four edges of
the device. Clock signals from the four BUFGMUX elements
at the top edge and the four at the bottom edge are truly
global and connect to all clocking quadrants. The eight
left-edge BUFGMUX elements only connect to the two clock
quadrants in the left half of the device. Similarly, the eight
right-edge BUFGMUX elements only connect to the right
half of the device.
8 Right-Half Clock inputs (RHCLK0 through RHCLK7)
located along the right edge
8 Left-Half Clock inputs (LHCLK0 through LHCLK7)
located along the left edge
Clock inputs optionally connect directly to DCMs using
dedicated connections. Table 30, Table 31, and Table 32
show the clock inputs that best feed a specific DCM within a
given Spartan-3E part number. Different Spartan-3E FPGA
densities have different numbers of DCMs. The
XC3S1200E and XC3S1600E are the only two densities
with the left- and right-edge DCMs.
BUFGMUX elements are organized in pairs and share I0
and I1 connections with adjacent BUFGMUX elements from
a common clock switch matrix as shown in Figure 46. For
example, the input on I0 of one BUFGMUX is also a shared
input to I1 of the adjacent BUFGMUX.
Each clock input is also optionally a user-I/O pin and
connects to internal interconnect. Some clock pad pins are
input-only pins as indicated in Module 4, Pinout
Descriptions.
The clock switch matrix for the left- and right-edge
BUFGMUX elements receive signals from any of the three
following sources: an LHCLK or RHCLK pin as appropriate,
a Double-Line interconnect, or a DCM in the XC3S1200E
and XC3S1600E devices.
Design Note
Avoid using global clock input GCLK1 as it is always shared
with the M2 mode select pin. Global clock inputs GCLK0,
GCLK2, GCLK3, GCLK12, GCLK13, GCLK14, and
GCLK15 have shared functionality in some configuration
modes.
Clock Buffers/Multiplexers
Clock Buffers/Multiplexers either drive clock input signals
directly onto a clock line (BUFG) or optionally provide a
multiplexer to switch between two unrelated, possibly
asynchronous clock signals (BUFGMUX).
Each BUFGMUX element, shown in Figure 46, is a 2-to-1
multiplexer. The select line, S, chooses which of the two
inputs, I0 or I1, drives the BUFGMUX’s output signal, O, as
described in Table 40. The switching from one clock to the
other is glitch-less, and done in such a way that the output
High and Low times are never shorter than the shortest
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Spartan-3E FPGA Family: Functional Description
X-Ref Target - Figure 45
Global Clock Inputs
GCLK11 GCLK10
GCLK9 GCLK8
4
GCLK7 GCLK6
GCLK5
GCLK4 4
DCM
BUFGMUX
pair
DCM
Clock Line
XC3S100E (X0Y1)
XC3S250E (X1Y1)
XC3S500E (X1Y1)
XC3S1200E (X2Y3)
XC3S1600E (X2Y3)
XC3S250E (X0Y1)
XC3S500E (X0Y1)
XC3S1200E (X1Y3)
XC3S1600E (X1Y3)
X1Y10 X1Y11
X2Y10 X2Y11
in Quadrant
BUFGMUX
4
4
H
G
F
E
H
G
H
Top Right
Top Left
Quadrant (TR)
Quadrant (TL)
8
8
8
4
G
•
•
•
•
•
•
2
2
2
2
8
DCM
DCM
XC3S1200E (X0Y1)
XC3S1600E (X0Y1)
XC3S1200E (X3Y1)
XC3S1600E (X3Y1)
8
8
2
2
2
2
F
F
Note 3
Note 4
E
D
E
D
8
8
8
8
Left Spine
Right Spine
Horizontal
Spine
Note 3
Note 4
•
8
•
8
C
C
2
2
2
2
8
8
DCM
DCM
•
•
XC3S1200E (X0Y2)
XC3S1600E (X0Y2)
XC3S1200E (X3Y2)
XC3S1600E (X3Y2)
2
2
2
2
•
•
B
A
B
4
Bottom Right
Quadrant (BR)
8
8
Bottom Left
Quadrant (BL)
A
4
4
DCM
DCM
D
C
B
A
XC3S100E (X0Y0)
XC3S250E (X1Y0)
XC3S500E (X1Y0)
XC3S1200E (X2Y0)
XC3S1600E (X2Y0)
XC3S250E (X0Y0)
XC3S500E (X0Y0)
XC3S1200E (X1Y0)
XC3S1600E (X1Y0)
X1Y0 X1Y1
X2Y0 X2Y1
GCLK1 GCLK0
4
4 GCLK3
GCLK2
GCLK15 GCLK14 GCLK13 GCLK12
Global Clock Inputs
DS312-2_04_041106
Notes:
1. The diagram presents electrical connectivity. The diagram locations do not necessarily match the physical location on the
device, although the coordinate locations shown are correct.
2. Number of DCMs and locations of these DCM varies for different device densities. The left and right DCMs are only in the
XC3S1200E and XC3S1600E. The XC3S100E has only two DCMs, one on the top right and one on the bottom right of the die.
3. See Figure 47a, which shows how the eight clock lines are multiplexed on the left-hand side of the device.
4. See Figure 47b, which shows how the eight clock lines are multiplexed on the right-hand side of the device.
5. For best direct clock inputs to a particular clock buffer, not a DCM, see Table 41.
6. For best direct clock inputs to a particular DCM, not a BUFGMUX, see Table 30, Table 31, and Table 32. Direct pin inputs to a
DCM are shown in gray.
Figure 45: Spartan-3E Internal Quadrant-Based Clock Network (Electrical Connectivity View)
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Spartan-3E FPGA Family: Functional Description
By contrast, the clock switch matrixes on the top and bottom
edges receive signals from any of the five following sources:
two GCLK pins, two DCM outputs, or one Double-Line
interconnect.
The four BUFGMUX elements on the top edge are paired
together and share inputs from the eight global clock inputs
along the top edge. Each BUFGMUX pair connects to four
of the eight global clock inputs, as shown in Figure 45. This
optionally allows differential inputs to the global clock inputs
without wasting a BUFGMUX element.
Table 41 indicates permissible connections between clock
inputs and BUFGMUX elements. The I0-input provides the
best input path to a clock buffer. The I1-input provides the
secondary input for the clock multiplexer function.
Table 41: Connections from Clock Inputs to BUFGMUX Elements and Associated Quadrant Clock
Quadran
t Clock
Line(1)
Left-Half BUFGMUX
Location(2) I0 Input
I1 Input
Top or Bottom BUFGMUX
Right-Half BUFGMUX
Location(2) I0 Input
I1 Input
(2)
Location
I0 Input
I1 Input
GCLK7 or
GCLK11
GCLK6 or
GCLK10
H
G
F
X0Y9
X0Y8
X0Y7
X0Y6
X0Y5
X0Y4
X0Y3
X0Y2
LHCLK7
LHCLK6
LHCLK5
LHCLK4
LHCLK3
LHCLK2
LHCLK1
LHCLK0
LHCLK6
LHCLK7
LHCLK4
LHCLK5
LHCLK2
LHCLK3
LHCLK0
LHCLK1
X1Y10
X1Y11
X2Y10
X2Y11
X1Y0
X3Y9
X3Y8
X3Y7
X3Y6
X3Y5
X3Y4
X3Y3
X3Y2
RHCLK3
RHCLK2
RHCLK1
RHCLK0
RHCLK7
RHCLK6
RHCLK5
RHCLK4
RHCLK2
RHCLK3
RHCLK0
RHCLK1
RHCLK6
RHCLK7
RHCLK4
RHCLK5
GCLK6 or
GCLK10
GCLK7 or
GCLK11
GCLK5 or
GCLK9
GCLK4 or
GCLK8
GCLK4 or
GCLK8
GCLK5 or
GCLK9
E
D
C
B
GCLK3 or
GCLK15
GCLK2 or
GCLK14
GCLK2 or
GCLK14
GCLK3 or
GCLK15
X1Y1
GCLK1 or
GCLK13
GCLK0 or
GCLK12
X2Y0
GCLK0 or
GCLK12
GCLK1 or
GCLK13
A
X2Y1
Notes:
1. See Quadrant Clock Routing for connectivity details for the eight quadrant clocks.
2. See Figure 45 for specific BUFGMUX locations, and Figure 47 for information on how BUFGMUX elements drive onto a specific clock line
within a quadrant.
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Spartan-3E FPGA Family: Functional Description
The connections for the bottom-edge BUFGMUX elements
are similar to the top-edge connections (see Figure 46).
On the left and right edges, only two clock inputs feed each
pair of BUFGMUX elements.
X-Ref Target - Figure 46
Left-/Right-Half BUFGMUX
CLK Switch
Top/Bottom (Global) BUFGMUX
CLK Switch
Matrix
Matrix
BUFGMUX
BUFGMUX
O
S
S
I0
I0
0
1
0
1
O
O
I1
I1
I0
I1
I0
I1
0
1
0
1
O
S
S
LHCLK or
RHCLK input
1st GCLK pin
1st DCM output
Double Line
Double Line
DCM output*
*(XC3S1200E and
XC3S1600E only)
2nd DCM output
2nd GCLK pin
DS312-2_16_110706
Figure 46: Clock Switch Matrix to BUFGMUX Pair Connectivity
Quadrant Clock Routing
Table 42: QFP Package Clock Quadrant Locations
Clock Pins
GCLK[3:0]
Quadrant
BR
The clock routing within the FPGA is quadrant-based, as
shown in Figure 45. Each clock quadrant supports eight
total clock signals, labeled ‘A’ through ‘H’ in Table 41 and
Figure 47. The clock source for an individual clock line
originates either from a global BUFGMUX element along
the top and bottom edges or from a BUFGMUX element
along the associated edge, as shown in Figure 47. The
clock lines feed the synchronous resource elements (CLBs,
IOBs, block RAM, multipliers, and DCMs) within the
quadrant.
GCLK[7:4]
TR
GCLK[11:8]
GCLK[15:12]
RHCLK[3:0]
RHCLK[7:4]
LHCLK[3:0]
LHCLK[7:4]
TL
BL
BR
TR
TL
BL
The four quadrants of the device are:
•
•
•
•
Top Right (TR)
Bottom Right (BR)
Bottom Left (BL)
Top Left (TL)
In a few cases, a dedicated input is physically in one
quadrant of the device but connects to a different clock
quadrant:
•
•
•
FT256, H16 is in clock quadrant BR
FG320, K2 is in clock quadrant BL
Note that the quadrant clock notation (TR, BR, BL, TL) is
separate from that used for similar IOB placement
constraints.
FG400, L8 is in clock quadrant TL and the I/O at N11 is
in clock quadrant BL
•
FG484, M2 is in clock quadrant TL and L15 is in clock
quadrant BR
To estimate the quadrant location for a particular I/O, see
the footprint diagrams in Module 4, Pinout Descriptions. For
exact quadrant locations, use the floorplanning tool. In the
QFP packages (VQ100, TQ144 and PQ208) the quadrant
borders fall in the middle of each side of the package, at a
GND pin. The clock inputs fall on the quadrant boundaries,
as indicated in Table 42.
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Spartan-3E FPGA Family: Functional Description
X-Ref Target - Figure 47
Clock Line
BUFGMUX Output
X1Y10 (Global)
Clock Line
BUFGMUX Output
X1Y10 (Global)
H
H
X0Y9 (Left Half)
X3Y9 (Right Half)
X1Y11 (Global)
X0Y8 (Left Half)
X1Y11 (Global)
G
F
G
F
X3Y8 (Right Half)
X2Y10 (Global)
X0Y7 (Left Half)
X2Y10 (Global)
X3Y7 (Right Half)
X2Y11 (Global)
X0Y6 (Left Half)
X2Y11 (Global)
E
D
C
B
E
D
C
B
X3Y6 (Right Half)
X1Y0 (Global)
X1Y0 (Global)
X0Y5 (Left Half)
X3Y5 (Right Half)
X1Y1 (Global)
X1Y1 (Global)
X0Y4 (Left Half)
X3Y4 (Right Half)
X2Y0 (Global)
X2Y0 (Global)
X0Y3 (Left Half)
X3Y3 (Right Half)
X2Y1 (Global)
X2Y1 (Global)
A
A
X0Y2 (Left Half)
X3Y2 (Right Half)
a. Left (TL and BL Quadrants) Half of Die
b. Right (TR and BR Quadrants) Half of Die
DS312-2_17_103105
Figure 47: Clock Sources for the Eight Clock Lines within a Clock Quadrant
The outputs of the top or bottom BUFGMUX elements
connect to two vertical spines, each comprising four vertical
clock lines as shown in Figure 45. At the center of the die,
these clock signals connect to the eight-line horizontal clock
spine.
Outputs of the left and right BUFGMUX elements are routed
onto the left or right horizontal spines, each comprising
eight horizontal clock lines.
Each of the eight clock signals in a clock quadrant derives
either from a global clock signal or a half clock signal. In
other words, there are up to 24 total potential clock inputs to
the FPGA, eight of which can connect to clocked elements
in a single clock quadrant. Figure 47 shows how the clock
lines in each quadrant are selected from associated
BUFGMUX sources. For example, if quadrant clock ‘A’ in
the bottom left (BL) quadrant originates from
BUFGMUX_X2Y1, then the clock signal from
BUFGMUX_X0Y2 is unavailable in the bottom left quadrant.
However, the top left (TL) quadrant clock ‘A’ can still solely
use the output from either BUFGMUX_X2Y1 or
BUFGMUX_X0Y2 as the source.
To minimize the dynamic power dissipation of the clock
network, the Xilinx development software automatically
disables all clock segments not in use.
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Spartan-3E FPGA Family: Functional Description
exploits the rich interconnect array to deliver optimal system
performance and the fastest compile times.
Interconnect
For additional information, refer to the “Using Interconnect”
chapter in UG331.
Switch Matrix
Interconnect is the programmable network of signal
pathways between the inputs and outputs of functional
elements within the FPGA, such as IOBs, CLBs, DCMs, and
block RAM.
The switch matrix connects to the different kinds of
interconnects across the device. An interconnect tile, shown
in Figure 48, is defined as a single switch matrix connected
to a functional element, such as a CLB, IOB, or DCM. If a
functional element spans across multiple switch matrices
such as the block RAM or multipliers, then an interconnect
tile is defined by the number of switch matrices connected
to that functional element. A Spartan-3E device can be
represented as an array of interconnect tiles where
interconnect resources are for the channel between any two
adjacent interconnect tile rows or columns as shown in
Figure 49.
Overview
Interconnect, also called routing, is segmented for optimal
connectivity. Functionally, interconnect resources are
identical to that of the Spartan-3 architecture. There are four
kinds of interconnects: long lines, hex lines, double lines,
and direct lines. The Xilinx Place and Route (PAR) software
X-Ref Target - Figure 48
Switch
Matrix
Switch
Matrix
CLB
IOB
Switch
Matrix
Switch
Matrix
18Kb
Block
RAM
MULT
18 x 18
Switch
Matrix
Switch
Matrix
DCM
Switch
Matrix
DS312_08_100110
Figure 48: Four Types of Interconnect Tiles (CLBs, IOBs, DCMs, and Block RAM/Multiplier)
X-Ref Target - Figure 49
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
IOB
IOB
IOB
IOB
IOB
IOB
CLB
CLB
CLB
CLB
IOB
CLB
CLB
CLB
CLB
IOB
CLB
CLB
CLB
CLB
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
DS312_09_100110
Figure 49: Array of Interconnect Tiles in Spartan-3E FPGA
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Spartan-3E FPGA Family: Functional Description
X-Ref Target - Figure 50
Horizontal and Vertical
Long Lines
24
(horizontal channel
shown as an example)
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
6
6
6
6
6
DS312-2_10_022305
Horizontal and Vertical
Hex Lines
8
(horizontal channel
shown as an example)
CLB
CLB
CLB
CLB
CLB
CLB
CLB
DS312-2_11_020905
Horizontal and Vertical
Double Lines
8
(horizontal channel
shown as an example)
CLB
CLB
CLB
DS312-2_15_022305
Direct Connections
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
DS312-2_12_020905
Figure 50: Interconnect Types between Two Adjacent Interconnect Tiles
The four types of general-purpose interconnect available in
each channel, shown in Figure 50, are described below.
Hex Lines
Each set of eight hex lines are connected to one out of
every three tiles, both horizontally and vertically. Thirty-two
hex lines are available between any given interconnect tile.
Hex lines are only driven from one end of the route.
Long Lines
Each set of 24 long line signals spans the die both
horizontally and vertically and connects to one out of every
six interconnect tiles. At any tile, four of the long lines drive
or receive signals from a switch matrix. Because of their low
capacitance, these lines are well-suited for carrying
high-frequency signals with minimal loading effects (e.g.
skew). If all global clock lines are already committed and
additional clock signals remain to be assigned, long lines
serve as a good alternative.
Double Lines
Each set of eight double lines are connected to every other
tile, both horizontally and vertically. in all four directions.
Thirty-two double lines available between any given
interconnect tile. Double lines are more connections and
more flexibility, compared to long line and hex lines.
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Spartan-3E FPGA Family: Functional Description
Direct Connections
Direct connect lines route signals to neighboring tiles:
vertically, horizontally, and diagonally. These lines most
often drive a signal from a “source” tile to a double, hex, or
long line and conversely from the longer interconnect back
to a direct line accessing a “destination” tile.
Global Controls (STARTUP_SPARTAN3E)
In addition to the general-purpose interconnect, Spartan-3E
FPGAs have two global logic control signals, as described
in Table 43. These signals are available to the FPGA
application via the STARTUP_SPARTAN3E primitive.
Table 43: Spartan-3E Global Logic Control Signals
Global Control
Description
Input
Global Set/Reset: When High,
asynchronously places all registers and
flip-flops in their initial state (see Initialization,
page 32). Asserted automatically during the
GSR
FPGA configuration process (see Start-Up,
page 106).
Global Three-State: When High,
asynchronously forces all I/O pins to a
high-impedance state (Hi-Z, three-state).
GTS
The Global Set/Reset (GSR) signal replaces the global
reset signal included in many ASIC-style designs. Use the
GSR control instead of a separate global reset signal in the
design to free up CLB inputs, resulting in a smaller, more
efficient design. Similarly, the GSR signal is asserted
automatically during the FPGA configuration process,
guaranteeing that the FPGA starts-up in a known state.
The STARTUP_SPARTAN3E primitive also includes two
other signals used specifically during configuration. The
MBT signals are for Dynamically Loading Multiple
Configuration Images Using MultiBoot Option, page 92. The
CLK input is an alternate clock for configuration Start-Up,
page 106.
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Spartan-3E FPGA Family: Functional Description
merely borrowed and returned to the application as
general-purpose user I/Os after configuration completes.
Configuration
For additional information on configuration, refer to UG332:
Spartan-3E FPGAs offer several configuration options to
minimize the impact of configuration on the overall system
design. In some configuration modes, the FPGA generates
a clock and loads itself from an external memory source,
either serially or via a byte-wide data path. Alternatively, an
external host such as a microprocessor downloads the
FPGA’s configuration data using a simple synchronous
serial interface or via a byte-wide peripheral-style interface.
Furthermore, multiple-FPGA designs share a single
configuration memory source, creating a structure called a
daisy chain.
Spartan-3 Generation Configuration User Guide.
Differences from Spartan-3 FPGAs
In general, Spartan-3E FPGA configuration modes are a
superset to those available in Spartan-3 FPGAs. Two new
modes added in Spartan-3E FPGAs provide a glueless
configuration interface to industry-standard parallel NOR
Flash and SPI serial Flash memories.
Configuration Process
Three FPGA pins—M2, M1, and M0—select the desired
configuration mode. The mode pin settings appear in
Table 44. The mode pin values are sampled during the start
of configuration when the FPGA’s INIT_B output goes High.
After the FPGA completes configuration, the mode pins are
available as user I/Os.
The function of a Spartan-3E FPGA is defined by loading
application-specific configuration data into the FPGA’s
internal, reprogrammable CMOS configuration latches
(CCLs), similar to the way a microprocessor’s function is
defined by its application program. For FPGAs, this
configuration process uses a subset of the device pins,
some of which are dedicated to configuration; other pins are
Table 44: Spartan-3E Configuration Mode Options and Pin Settings
Master
Serial
SPI
BPI
Slave Parallel
Slave Serial
JTAG
M[2:0] mode pin
settings
<0:0:0>
<0:0:1>
<0:1:0>=Up
<0:1:1>=Down
<1:1:0>
<1:1:1>
<1:0:1>
Data width
Serial
Serial
Byte-wide
Byte-wide
Serial
Serial
Configuration memory
source
Xilinx
Platform
Flash
Industry-standard Industry-standard Any source via
Any source via
Any source via
SPI serial Flash
parallel NOR
Flash or Xilinx
microcontroller, microcontroller, microcontroller,
CPU, Xilinx CPU, Xilinx CPU, System
parallel Platform parallel Platform Platform Flash, ACE™ CF, etc.
Flash
Flash, etc.
etc.
Clock source
Internal
oscillator
Internal oscillator Internal oscillator
External clock
on CCLK pin
External clock
on CCLK pin
External clock
on TCK pin
Total I/O pins borrowed
during configuration
8
13
46
21
8
0
Configuration mode for Slave Serial
downstream daisy-
chained FPGAs
Slave Serial
Slave Parallel
Slave Parallel or
Memory
Slave Serial
JTAG
Mapped
Stand-alone FPGA
applications (no
external download
Possible using
XCFxxP
Platform Flash, Platform Flash,
which optionally which optionally
generates CCLK generates CCLK
Possible using
XCFxxP
✓
✓
✓
✓
host)
Uses low-cost,
industry-standard
Flash
✓
✓
Supports optional
MultiBoot,
multi-configuration
mode
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Spartan-3E FPGA Family: Functional Description
values applied to the M2, M1, and M0 mode select pins and
the HSWAP pin. The mode select pins determine which of
the I/O pins are borrowed during configuration and how they
function. In JTAG configuration mode, no user-I/O pins are
borrowed for configuration.
Configuration Bitstream Image Sizes
A specific Spartan-3E part type always requires a constant
number of configuration bits, regardless of design
complexity, as shown in Table 45. The configuration file size
for a multiple-FPGA daisy-chain design roughly equals the
sum of the individual file sizes.
All user-I/O pins, input-only pins, and dual-purpose pins that
are not actively involved in the currently-select configuration
mode are high impedance (floating, three-stated, Hi-Z)
during the configuration process. These pins are indicated
in Table 46 as gray shaded table entries or cells.
Table 45: Number of Bits to Program a Spartan-3E
FPGA (Uncompressed Bitstreams)
Number of
Spartan-3E FPGA
Configuration Bits
The HSWAP input controls whether all user-I/O pins,
input-only pins, and dual-purpose pins have a pull-up
resistor to the supply rail or not. When HSWAP is Low, each
pin has an internal pull-up resistor that is active throughout
configuration. After configuration, pull-up and pull-down
resistors are available in the FPGA application as described
in Pull-Up and Pull-Down Resistors.
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
581,344
1,353,728
2,270,208
3,841,184
5,969,696
The yellow-shaded table entries or cells represent pins
where the pull-up resistor is always enabled during
configuration, regardless of the HSWAP input. The
post-configuration behavior of these pins is defined by
Bitstream Generator options as defined in Table 69.
Pin Behavior During Configuration
For additional information, refer to the “Configuration Pins
and Behavior during Configuration” chapter in UG332.
Table 46 shows how various pins behave during the FPGA
configuration process. The actual behavior depends on the
Table 46: Pin Behavior during Configuration
SPI (Serial
Flash)
BPI (Parallel
NOR Flash)
Pin Name
Master Serial
JTAG
Slave Parallel Slave Serial
I/O Bank(3)
IO* (user-I/O)
IP* (input-only)
-
TDI
TMS
TDI
TMS
TCK
TDO
PROG_B
DONE
HSWAP
0
TDI
TMS
TCK
TDO
PROG_B
DONE
HSWAP
0
TDI
TMS
TCK
TDI
TMS
TCK
TDO
PROG_B
DONE
HSWAP
1
TDI
TMS
TCK
TDO
PROG_B
DONE
HSWAP
1
TDI
TMS
TCK
TDO
PROG_B
DONE
HSWAP
1
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
0
TCK
TDO
TDO
PROG_B
DONE
HSWAP
M2
PROG_B
DONE
HSWAP
0
2
M1
0
0
1
0
1
1
2
M0
0
1
0 = Up
1 = Down
1
0
1
2
CCLK
CCLK (I/O)
INIT_B
CCLK (I/O)
INIT_B
CSO_B
DOUT
CCLK (I/O)
INIT_B
CSO_B
BUSY
CSI_B
D7
CCLK (I)
INIT_B
CSO_B
BUSY
CSI_B
D7
CCLK (I)
INIT_B
2
2
2
2
2
2
2
2
2
2
2
2
INIT_B
CSO_B
DOUT/BUSY
DOUT
DOUT
MOSI/CSI_B
MOSI
D7
D6
D5
D4
D3
D2
D1
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
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Spartan-3E FPGA Family: Functional Description
Table 46: Pin Behavior during Configuration (Cont’d)
SPI (Serial
Flash)
BPI (Parallel
NOR Flash)
Pin Name
Master Serial
JTAG
Slave Parallel Slave Serial
I/O Bank(3)
D0/DIN
RDWR_B
A23
DIN
DIN
D0
D0
DIN
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RDWR_B
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
RDWR_B
A22
A21
A20
A19/VS2
A18/VS1
A17/VS0
A16
VS2
VS1
VS0
A15
A14
A13
A12
A11
A10
A9
A8
A8
A7
A7
A6
A6
A5
A5
A4
A4
A3
A3
A2
A2
A1
A1
A0
A0
LDC0
LDC1
LDC2
HDC
LDC0
LDC1
LDC2
HDC
Notes:
1. Gray shaded cells represent pins that are in a high-impedance state (Hi-Z, floating) during configuration. These pins have an optional
internal pull-up resistor to their respective VCCO supply pin that is active throughout configuration if the HSWAP input is Low.
2. Yellow shaded cells represent pins with an internal pull-up resistor to its respective voltage supply rail that is active during
configuration, regardless of the HSWAP pin.
3. Note that dual-purpose outputs are supplied by VCCO, and configuration inputs are supplied by VCCAUX
.
The HSWAP pin itself has a pull-up resistor enabled during
configuration. However, the VCCO_0 supply voltage must
be applied before the pull-up resistor becomes active. If the
VCCO_0 supply ramps after the VCCO_2 power supply, do
not let HSWAP float; tie HSWAP to the desired logic level
externally.
Table 47 shows the default I/O standard setting for the
various configuration pins during the configuration process.
The configuration interface is designed primarily for 2.5V
operation when the VCCO_2 (and VCCO_1 in BPI mode)
connects to 2.5V.
Table 47: Default I/O Standard Setting During Config-
Spartan-3E FPGAs have only six dedicated configuration
pins, including the DONE and PROG_B pins, and the four
JTAG boundary-scan pins: TDI, TDO, TMS, and TCK. All
other configuration pins are dual-purpose I/O pins and are
available to the FPGA application after the DONE pin goes
High. See Start-Up for additional information.
uration (VCCO_2 = 2.5V)
Pin(s)
I/O Standard Output Drive Slew Rate
8 mA Slow
All, including CCLK LVCMOS25
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Spartan-3E FPGA Family: Functional Description
The configuration pins also operate at other voltages by
setting VCCO_2 (and VCCO_1 in BPI mode) to either 3.3V
Design Considerations for the HSWAP,
M[2:0], and VS[2:0] Pins
or 1.8V. The change on the V
supply also changes the
CCO
I/O characteristics, including the effective IOSTANDARD.
For example, with V = 3.3V, the output characteristics
For additional information, refer to the “Configuration Pins
and Behavior during Configuration” chapter in UG332.
CCO
will be similar to those of LVCMOS33, and the current when
driving High, I , increases to approximately 12 to 16 mA,
Unlike previous Spartan FPGA families, nearly all of the
Spartan-3E dual-purpose configuration pins are available
as full-featured user I/O pins after successful configuration,
when the DONE output goes High.
OH
while the current when driving Low, I , remains 8 mA. At
OL
V
= 1.8V, the output characteristics will be similar to
CCO
those of LVCMOS18, and the current when driving High,
, decreases slightly to approximately 6 to 8 mA. Again,
I
The HSWAP pin, the mode select pins (M[2:0]), and the
variant-select pins (VS[2:0]) must have valid and stable
logic values at the start of configuration. VS[2:0] are only
used in the SPI configuration mode. The levels on the
M[2:0] pins and VS[2:0] pins are sampled when the INIT_B
pin returns High. See Figure 76 for a timing example.
OH
the current when driving Low, I , remains 8 mA. The
OL
output voltages are determined by the V
level,
CCO
LVCMOS18 for 1.8V, LVCMOS25 for 2.5V, and LVCMOS33
for 3.3V. For more details see UG332.
CCLK Design Considerations
The HSWAP pin defines whether FPGA user I/O pins have
a pull-up resistor connected to their associated V
For additional information, refer to the “Configuration Pins
and Behavior during Configuration” chapter in UG332.
CCO
supply pin during configuration or not, as shown Table 48.
HSWAP must be valid at the start of configuration and
remain constant throughout the configuration process.
The FPGA’s configuration process is controlled by the
CCLK configuration clock. Consequently, signal integrity of
CCLK is important to guarantee successful configuration.
Poor CCLK signal integrity caused by ringing or reflections
might cause double-clocking, causing the configuration
process to fail.
Table 48: HSWAP Behavior
HSWAP
Description
Value
0
Pull-up resistors connect to the associated VCCO
supply for all user-I/O or dual-purpose I/O pins
during configuration. Pull-up resistors are active until
configuration completes.
Although the CCLK frequency is relatively low, Spartan-3E
FPGA output edge rates are fast. Therefore, careful
attention must be paid to the CCLK signal integrity on the
printed circuit board. Signal integrity simulation with IBIS is
recommended. For all configuration modes except JTAG,
the signal integrity must be considered at every CCLK trace
destination, including the FPGA’s CCLK pin.
1
Pull-up resistors disabled during configuration. All
user-I/O or dual-purpose I/O pins are in a
high-impedance state.
The Configuration section provides detailed schematics for
each configuration mode. The schematics indicate the
required logic values for HSWAP, M[2:0], and VS[2:0] but do
not specify how the application provides the logic Low or
High value. The HSWAP, M[2:0], and VS[2:0] pins can be
either dedicated or reused by the FPGA application.
This analysis is especially important when the FPGA
re-uses the CCLK pin as a user-I/O after configuration. In
these cases, there might be unrelated devices attached to
CCLK, which add additional trace length and signal
destinations.
In the Master Serial, SPI, and BPI configuration modes, the
FPGA drives the CCLK pin and CCLK should be treated as
a full bidirectional I/O pin for signal integrity analysis. In BPI
mode, CCLK is only used in multi-FPGA daisy-chains.
Dedicating the HSWAP, M[2:0], and VS[2:0] Pins
If the HSWAP, M[2:0], and VS[2:0] pins are not required by
the FPGA design after configuration, simply connect these
pins directly to the V
or GND supply rail shown in the
CCO
The best signal integrity is ensured by following these basic
PCB guidelines:
appropriate configuration schematic.
Reusing HSWAP, M[2:0], and VS[2:0] After Config-
uration
•
•
•
•
Route the CCLK signal as a 50 Ω
controlled-impedance transmission line.
To reuse the HSWAP, M[2:0], and VS[2:0] pin after
configuration, use pull-up or pull-down resistors to define
the logic values shown in the appropriate configuration
schematic.
Route the CCLK signal without any branching. Do not
use a “star” topology.
Keep stubs, if required, shorter than 10 mm (0.4
inches).
Terminate the end of the CCLK transmission line.
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Spartan-3E FPGA Family: Functional Description
Table 49: Pull-up or Pull-down Values for HSWAP, M[2:0], and VS[2:0]
Required Resistor Value to Define Logic Level on
HSWAP, M[2:0], or VS[2:0]
I/O Pull-up Resistors
during Configuration
HSWAP Value
High
Low
0
Enabled
Pulled High via an internal pull-up
resistor to the associated VCCO
supply. No external pull-up resistor is
necessary.
Pulled Low using an appropriately sized
pull-down resistor to GND.
For a 2.5V or 3.3V interface: R ≤ 560Ω . For a
1.8V interface: R ≤ 1.1kΩ .
1
Disabled
Pulled High using a 3.3 to 4.7kΩ
resistor to the associated VCCO
supply.
Pulled Low using a 3.3 to 4.7kΩ resistor to
GND.
The logic level on HSWAP dictates how to define the logic
levels on M[2:0] and VS[2:0], as shown in Table 49. If the
application requires HSWAP to be High, the HSWAP pin is
pulled High using an external 3.3kΩ to 4.7kΩ resistor to
VCCO_0. If the application requires HSWAP to be Low
during configuration, then HSWAP is either connected to
GND or pulled Low using an appropriately sized external
pull-down resistor to GND. When HSWAP is Low, its pin has
an internal pull-up resistor to VCCO_0. The external
pull-down resistor must be strong enough to define a logic
Low on HSWAP for the I/O standard used during
configuration. For 2.5V or 3.3V I/O, the pull-down resistor is
560Ω or lower. For 1.8V I/O, the pull-down resistor is 1.1kΩ
or lower.
Once HSWAP is defined, use Table 49 to define the logic
values for M[2:0] and VS[2:0].
Use the weakest external pull-up or pull-down resistor value
allowed by the application. The resistor must be strong
enough to define a logic Low or High during configuration.
However, when driving the HSWAP, M[2:0], or VS[2:0] pins
after configuration, the output driver must be strong enough
to overcome the pull-up or pull-down resistor value and
generate the appropriate logic levels. For example, to
overcome a 560Ω pull-down resistor, a 3.3V FPGA I/O pin
must use a 6 mA or stronger driver.
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Spartan-3E FPGA Family: Functional Description
Flash PROM, as illustrated in Figure 51. The FPGA
supplies the CCLK output clock from its internal oscillator to
the attached Platform Flash PROM. In response, the
Platform Flash PROM supplies bit-serial data to the FPGA’s
DIN input, and the FPGA accepts this data on each rising
CCLK edge.
Master Serial Mode
For additional information, refer to the “Master Serial Mode”
chapter in UG332.
In Master Serial mode (M[2:0] = <0:0:0>), the Spartan-3E
FPGA configures itself from an attached Xilinx Platform
X-Ref Target - Figure 51
+1.2V
XCFxxS = +3.3V
XCFxxP = +1.8V
V
VCCINT
P
HSWAP
VCCO_0
VCCO_0
VCCINT
VCCO_2
DIN
V
D0
VCCO
V
Serial Master
Mode
CCLK
DOUT
INIT_B
CLK
‘0’
‘0’
‘0’
M2
M1
M0
OE/RESET
+2.5V
Platform Flash
Spartan-3E
XCFxx
FPGA
CE
CF
CEO
+2.5V
JTAG
VCCAUX
+2.5V
VCCJ
TDO
+2.5V
TDI
TDI
TDO
TDI
TMS
TCK
TDO
TMS
TCK
TMS
TCK
GND
PROG_B
DONE
GND
PROG_B
Recommend
open-drain
driver
DS312-2_44_082009
Figure 51: Master Serial Mode using Platform Flash PROM
All mode select pins, M[2:0], must be Low when sampled,
when the FPGA’s INIT_B output goes High. After
configuration, when the FPGA’s DONE output goes High,
the mode select pins are available as full-featured user-I/O
pins.
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Spartan-3E FPGA Family: Functional Description
P
Similarly, the FPGA’s HSWAP pin must be Low to
available as full-featured user-I/O pin and is powered by the
VCCO_0 supply.
enable pull-up resistors on all user-I/O pins during
configuration or High to disable the pull-up resistors. The
HSWAP control must remain at a constant logic level
throughout FPGA configuration. After configuration, when
the FPGA’s DONE output goes High, the HSWAP pin is
The FPGA's DOUT pin is used in daisy-chain applications,
described later. In a single-FPGA application, the FPGA’s
DOUT pin is not used but is actively driving during the
configuration process.
Table 50: Serial Master Mode Connections
FPGA
Direction
Pin Name
Description
During Configuration
After Configuration
HSWAP
Input
User I/O Pull-Up Control. When Low during Drive at valid logic level
configuration, enables pull-up resistors in all throughout configuration.
I/O pins to respective I/O bank VCCO input.
User I/O
P
0: Pull-ups during configuration
1: No pull-ups
M[2:0]
Input
Mode Select. Selects the FPGA configuration M2 = 0, M1 = 0, M0 = 0. Sampled User I/O
mode. See Design Considerations for the
HSWAP, M[2:0], and VS[2:0] Pins.
when INIT_B goes High.
DIN
Input
Serial Data Input.
Receives serial data from PROM’s User I/O
D0 output.
CCLK
Output
Configuration Clock. Generated by FPGA
internal oscillator. Frequency controlled by
ConfigRate bitstream generator option. If
CCLK PCB trace is long or has multiple
connections, terminate this output to maintain
signal integrity. See CCLK Design
Drives PROM’s CLK clock input.
User I/O
Considerations.
DOUT
INIT_B
Output
Serial Data Output.
Actively drives. Not used in
single-FPGA designs. In a
daisy-chain configuration, this pin
connects to DIN input of the next
FPGA in the chain.
User I/O
Open-drain Initialization Indicator. Active Low. Goes
bidirectional Low at start of configuration during
Connects to PROM’s OE/RESET User I/O. If unused in
input. FPGA clears PROM’s
address counter at start of
configuration, enables outputs
during configuration. PROM also
holds FPGA in Initialization state
until PROM reaches Power-On
Reset (POR) state. If CRC error
detected during configuration,
FPGA drives INIT_B Low.
the application, drive
INIT_B High.
I/O
Initialization memory clearing process.
Released at end of memory clearing, when
mode select pins are sampled. Requires
external 4.7 kΩ pull-up resistor to VCCO_2.
DONE
Open-drain FPGA Configuration Done. Low during
bidirectional configuration. Goes High when FPGA
Connects to PROM’s chip-enable Pulled High via external
(CE) input. Enables PROM during pull-up. When High,
I/O
successfully completes configuration.
Requires external 330 Ω pull-up resistor to
2.5V.
configuration. Disables PROM
after configuration.
indicates that the FPGA
successfully
configured.
PROG_B
Input
Program FPGA. Active Low. When asserted Must be High during configuration Drive PROG_B Low
Low for 500 ns or longer, forces the FPGA to to allow configuration to start.
and release to
restart its configuration process by clearing
configuration memory and resetting the
DONE and INIT_B pins once PROG_B
returns High. Recommend external 4.7 kΩ
pull-up resistor to 2.5V. Internal pull-up value
may be weaker (see Table 78). If driving
externally with a 3.3V output, use an
open-drain or open-collector driver or use a
current limiting series resistor.
Connects to PROM’s CF pin,
allowing JTAG PROM
programming algorithm to
reprogram the FPGA.
reprogram FPGA.
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Spartan-3E FPGA Family: Functional Description
Voltage Compatibility
Table 52: Maximum ConfigRate Settings for Platform
Flash
The PROM’s V
supply must be either 3.3V for the
CCINT
Maximum
serial XCFxxS Platform Flash PROMs or 1.8V for the
serial/parallel XCFxxP PROMs.
Platform Flash
Part Number
I/O Voltage
ConfigRate
(VCCO_2, VCCO
)
Setting
V
The FPGA’s VCCO_2 supply input and the Platform
XCF01S
XCF02S
XCF04S
3.3V or 2.5V
1.8V
25
12
Flash PROM’s V
supply input must be the same
CCO
voltage, ideally +2.5V. Both devices also support 1.8V and
3.3V interfaces but the FPGA’s PROG_B and DONE pins
require special attention as they are powered by the FPGA’s
XCF08P
XCF16P
XCF32P
3.3V, 2.5V, or 1.8V
25
V
supply, nominally 2.5V. See application note
CCAUX
XAPP453: The 3.3V Configuration of Spartan-3 FPGAs for
additional information.
Supported Platform Flash PROMs
Table 51 shows the smallest available Platform Flash
PROM to program one Spartan-3E FPGA. A multiple-FPGA
daisy-chain application requires a Platform Flash PROM
large enough to contain the sum of the various FPGA file
sizes.
Table 51: Number of Bits to Program a Spartan-3E
FPGA and Smallest Platform Flash PROM
Spartan-3E
FPGA
Number of
Configuration Bits
Smallest Available
Platform Flash
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
581,344
1,353,728
2,270,208
3,841,184
XCF01S
XCF02S
XCF04S
XCF04S
XCF08P
or 2 x XCF04S
XC3S1600E
5,969,696
The XC3S1600E requires an 8 Mbit PROM. Two solutions
are possible: either a single 8 Mbit XCF08P parallel/serial
PROM or two 4 Mbit XCF04S serial PROMs cascaded. The
two XCF04S PROMs use a 3.3V V
supply while the
CCINT
XCF08P requires a 1.8V V
supply. If the board does
CCINT
not already have a 1.8V supply available, the two cascaded
XCF04S PROM solution is recommended.
CCLK Frequency
In Master Serial mode, the FPGA’s internal oscillator
generates the configuration clock frequency. The FPGA
provides this clock on its CCLK output pin, driving the
PROM’s CLK input pin. The FPGA starts configuration at its
lowest frequency and increases its frequency for the
remainder of the configuration process if so specified in the
configuration bitstream. The maximum frequency is
specified using the ConfigRate bitstream generator option.
Table 52 shows the maximum ConfigRate settings,
approximately equal to MHz, for various Platform Flash
devices and I/O voltages. For the serial XCFxxS PROMs,
the maximum frequency also depends on the interface
voltage.
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73
Spartan-3E FPGA Family: Functional Description
X-Ref Target - Figure 52
CCLK
+1.2V
+1.2V
XCFxxS = +3.3V
XCFxxP = +1.8V
VCCINT
VCCINT
P
HSWAP
VCCO_0
VCCO_0
P
HSWAP
VCCO_0
VCCO_0
VCCINT
VCCO_2
DIN
V
VCCO_2
V
Slave
Serial
Mode
D0
VCCO
V
Serial Master
Mode
CCLK
DOUT
INIT_B
CLK
‘0’
‘0’
‘0’
M2
M1
M0
‘1’
‘1’
‘1’
M2
M1
M0
DOUT
INIT_B
DOUT
OE/RESET
Platform Flash
Spartan-3E
FPGA
Spartan-3E
FPGA
XCFxx
CE
CF
CEO
CCLK
DIN
+2.5V
JTAG
VCCAUX
+2.5V
VCCJ
TDO
+2.5V
VCCAUX
+2.5V
TDI
TDI
TDO
TDI
TDI
TDO
TMS
TCK
TDO
TMS
TCK
TMS
TCK
TMS
TCK
V
+2.5V
GND
PROG_B
DONE
PROG_B
DONE
GND
GND
PROG_B
PROG_B
Recommend
open-drain
driver
TCK
TMS
DONE
INIT_B
DS312-2_45_082009
Figure 52: Daisy-Chaining from Master Serial Mode
Daisy-Chaining
In-System Programming Support
If the application requires multiple FPGAs with different
configurations, then configure the FPGAs using a daisy
chain, as shown in Figure 52. Use Master Serial mode
(M[2:0] = <0:0:0>) for the FPGA connected to the Platform
Flash PROM and Slave Serial mode (M[2:0] = <1:1:1>) for
all other FPGAs in the daisy-chain. After the master
FPGA—the FPGA on the left in the diagram—finishes
loading its configuration data from the Platform Flash, the
master device supplies data using its DOUT output pin to
the next device in the daisy-chain, on the falling CCLK edge.
Both the FPGA and the Platform Flash PROM are in-system
programmable via the JTAG chain. Download support is
provided by the Xilinx iMPACT programming software and
the associated Xilinx Parallel Cable IV or Platform Cable
USB programming cables.
Storing Additional User Data in Platform Flash
After configuration, the FPGA application can continue to
use the Master Serial interface pins to communicate with
the Platform Flash PROM. If desired, use a larger Platform
Flash PROM to hold additional non-volatile application data,
such as MicroBlaze processor code, or other user data such
as serial numbers and Ethernet MAC IDs. The FPGA first
configures from Platform Flash PROM. Then using FPGA
logic after configuration, the FPGA copies MicroBlaze code
from Platform Flash into external DDR SDRAM for code
execution.
JTAG Interface
Both the Spartan-3E FPGA and the Platform Flash PROM
have a four-wire IEEE 1149.1/1532 JTAG port. Both devices
share the TCK clock input and the TMS mode select input.
The devices may connect in either order on the JTAG chain
with the TDO output of one device feeding the TDI input of
the following device in the chain. The TDO output of the last
device in the JTAG chain drives the JTAG connector.
See XAPP694: Reading User Data from Configuration
PROMs and XAPP482: MicroBlaze Platform Flash/PROM
Boot Loader and User Data Storage for specific details on
how to implement such an interface.
The JTAG interface on Spartan-3E FPGAs is powered by
the 2.5V V
supply. Consequently, the PROM’s V
CCAUX
CCJ
supply input must also be 2.5V. To create a 3.3V JTAG
interface, please refer to application note XAPP453: The
3.3V Configuration of Spartan-3 FPGAs for additional
information.
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Product Specification
74
Spartan-3E FPGA Family: Functional Description
In SPI Serial Flash mode (M[2:0] = <0:0:1>), the Spartan-3E
FPGA configures itself from an attached industry-standard
SPI serial Flash PROM, as illustrated in Figure 53 and
Figure 54. The FPGA supplies the CCLK output clock from
its internal oscillator to the clock input of the attached SPI
Flash PROM.
SPI Serial Flash Mode
For additional information, refer to the “Master SPI Mode”
chapter in UG332.
X-Ref Target - Figure 53
+1.2V
+3.3V
SPI
Serial
Flash
VCCINT
P
P
HSWAP
VCCO_0
VCCO_0
I
VCC
DATA_IN
VCCO_2
MOSI
+3.3V
SPI Mode
DIN
DATA_OUT
SELECT
‘0’
‘0’
‘1’
M2
M1
M0
CSO_B
WR_PROTECT
HOLD
W
‘1’
Spartan-3E
CLOCK
Variant Select
FPGA
GND
‘1’
S
VS2
VS1
VS0
+3.3V
‘1’
CCLK
DOUT
INIT_B
+2.5V
JTAG
TDI
+2.5V
VCCAUX
TDO
+2.5V
TDI
TMS
TCK
TDO
TMS
TCK
PROG_B
DONE
GND
PROG_B
Recommend
open-drain
driver
DS312-2_46_082009
Figure 53: SPI Flash PROM Interface for PROMs Supporting READ (0x03) and FAST_READ (0x0B) Commands
S
Although SPI is a standard four-wire interface, various
Serial Peripheral Interface (SPI) Configuration Timing in
Module 3.
available SPI Flash PROMs use different command
protocols. The FPGA’s variant select pins, VS[2:0], define
how the FPGA communicates with the SPI Flash, including
which SPI Flash command the FPGA issues to start the
read operation and the number of dummy bytes inserted
before the FPGA expects to receive valid data from the SPI
Flash. Table 53 shows the available SPI Flash PROMs
expected to operate with Spartan-3E FPGAs. Other
compatible devices might work but have not been tested for
suitability with Spartan-3E FPGAs. All other VS[2:0] values
are reserved for future use. Consult the data sheet for the
desired SPI Flash device to determine its suitability. The
basic timing requirements and waveforms are provided in
Figure 53 shows the general connection diagram for those
SPI Flash PROMs that support the 0x03 READ command
or the 0x0B FAST READ commands.
Figure 54 shows the connection diagram for Atmel
DataFlash serial PROMs, which also use an SPI-based
protocol. ‘B’-series DataFlash devices are limited to FPGA
applications operating over the commercial temperature
range. Industrial temperature range applications must use
‘C’- or ‘D’-series DataFlash devices, which have a shorter
DataFlash select setup time, because of the faster FPGA
CCLK frequency at cold temperatures.
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75
Spartan-3E FPGA Family: Functional Description
Figure 57, page 83 demonstrates how to configure multiple
FPGAs with different configurations, all stored in a single
SPI Flash. The diagram uses standard SPI Flash memories
but the same general technique applies for Atmel
DataFlash.
X-Ref Target - Figure 54
+1.2V
+3.3V
Atmel
AT45DB
VCCINT
DataFlash
P
P
HSWAP
VCCO_0
VCCO_0
I
VCC
VCCO_2
MOSI
+3.3V
SI
Power-on monitor is only required if
+3.3V (VCCO_2) supply is the last supply
SPI Mode
DIN
SO
in power-on sequence, after VCCINT
and VCCAUX. Must delay FPGA
configuration for > 20 ms after SPI
DataFlash reaches its minimum VCC.
Force FPGA INIT_B input OR PROG_B
input Low with an open-drain or open-
collector driver.
‘0’
‘0’
‘1’
M2
M1
M0
CSO_B
CS
W
WP
‘1’
RESET
RDY/BUSY
SCK
Spartan-3E
Variant Select
FPGA
‘1’
‘1’
‘0’
VS2
VS1
VS0
GND
+3.3V
+3.3V
CCLK
DOUT
INIT_B
Power-On
Monitor
INIT_B
+2.5V
JTAG
+2.5V
VCCAUX
TDO
+2.5V
TDI
TDI
TMS
TCK
TDO
TMS
TCK
or
PROG_B
DONE
+3.3V
GND
Power-On
Monitor
PROG_B
PROG_B
Recommend
open-drain
driver
DS312-2_50a_082009
Figure 54: Atmel SPI-based DataFlash Configuration Interface
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Product Specification
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Spartan-3E FPGA Family: Functional Description
iMPACT
Table 53: Variant Select Codes for Various SPI Serial Flash PROMs
Dummy
VS2 VS1 VS0 SPI Read Command
SPI Serial Flash Vendor
SPI Flash Family
Programming
Support
Bytes
M25Pxx
M25PExx/M45PExx
STMicroelectronics (ST)
Atmel
Yes
Yes
AT45DB‘D’-SeriesData
Flash
AT26 / AT25(1)
S33
Intel
Spansion (AMD, Fujitsu)
Winbond (NexFlash)
Macronix
S25FLxxxA
NX25 / W25
MX25Lxxxx
FAST READ (0x0B)
(see Figure 53)
1
1
1
1
SST25LFxxxA
SST25VFxxxA
Silicon Storage Technology
(SST)
Programmable
Microelectronics Corp.
(PMC)
Pm25LVxxx
AMIC Technology
A25L
EN25
Eon Silicon Solution, Inc.
M25Pxx
M25PExx/M45PExx
STMicroelectronics (ST)
Yes
Spansion (AMD, Fujitsu)
Winbond (NexFlash)
Macronix
S25FLxxxA
NX25 / W25
MX25Lxxxx
READ (0x03)
(see Figure 53)
1
0
1
0
SST25LFxxxA
SST25VFxxxA
SST25VFxxx
Silicon Storage Technology
(SST)
Programmable
Microelectronics Corp.
(PMC)
Pm25LVxxx
AT45DB DataFlash
READ ARRAY (0xE8)
(see Figure 54)
(use only ‘C’ or ‘D’
Series for Industrial
temperature range)
1
1
0
4
Atmel Corporation
Yes
Others
Reserved
Notes:
1. See iMPACT documentation for specific device support.
WRITER NOTE: Many of the URLs in this table are obsolete or
otherwise broken.
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Product Specification
77
Spartan-3E FPGA Family: Functional Description
W
Table 54 shows the connections between the SPI Flash
controls are not used by the FPGA during configuration.
However, the HOLD pin must be High during the
configuration process. The PROM’s write protect input must
be High in order to write or program the Flash memory.
PROM and the FPGA’s SPI configuration interface. Each
SPI Flash PROM vendor uses slightly different signal
naming. The SPI Flash PROM’s write protect and hold
Table 54: Example SPI Flash PROM Connections and Pin Naming
Silicon
Storage
Technology
Atmel
DataFlash
SPI Flash Pin
FPGA Connection
STMicro
NexFlash
DATA_IN
DATA_OUT
SELECT
CLOCK
MOSI
DIN
D
Q
S
C
DI
DO
CS
SI
SI
SO
SO
CSO_B
CCLK
CE#
SCK
CS
CLK
SCK
Not required for FPGA configuration. Must be High
to program SPI Flash. Optional connection to
FPGA user I/O after configuration.
WR_PROTECT
W
WP
WP#
WP
N/A
W
Not required for FPGA configuration but must be
High during configuration. Optional connection to
FPGA user I/O after configuration. Not applicable
to Atmel DataFlash.
HOLD
(see Figure 53)
HOLD
HOLD
HOLD#
Only applicable to Atmel DataFlash. Not required
for FPGA configuration but must be High during
configuration. Optional connection to FPGA user
I/O after configuration. Do not connect to FPGA’s
PROG_B as this will prevent direct programming of
the DataFlash.
RESET
(see Figure 54)
N/A
N/A
N/A
N/A
N/A
N/A
RESET
Only applicable to Atmel DataFlash and only
available on certain packages. Not required for
FPGA configuration. Output from DataFlash
PROM. Optional connection to FPGA user I/O after
configuration.
RDY/BUSY
(see Figure 54)
RDY/BUSY
The mode select pins, M[2:0], and the variant select pins,
VS[2:0] are sampled when the FPGA’s INIT_B output goes
High and must be at defined logic levels during this time.
After configuration, when the FPGA’s DONE output goes
High, these pins are all available as full-featured user-I/O
pins.
disable the pull-up resistors. The HSWAP control must
remain at a constant logic level throughout FPGA
configuration. After configuration, when the FPGA’s DONE
output goes High, the HSWAP pin is available as
full-featured user-I/O pin and is powered by the VCCO_0
supply.
In a single-FPGA application, the FPGA’s DOUT pin is not
used but is actively driving during the configuration process.
P
Similarly, the FPGA’s HSWAP pin must be Low to
enable pull-up resistors on all user-I/O pins or High to
Table 55: Serial Peripheral Interface (SPI) Connections
FPGA
Pin Name
Description
During Configuration
After Configuration
User I/O
Direction
HSWAP
Input
User I/O Pull-Up Control. When Low
during configuration, enables pull-up
resistors in all I/O pins to respective I/O
bank VCCO input.
Drive at valid logic level
throughout configuration.
P
0: Pull-ups during configuration
1: No pull-ups
M[2:0]
Input
Mode Select. Selects the FPGA
configuration mode. See Design
Considerations for the HSWAP, M[2:0],
and VS[2:0] Pins.
M2 = 0, M1 = 0, M0 = 1.
Sampled when INIT_B goes
High.
User I/O
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Spartan-3E FPGA Family: Functional Description
Table 55: Serial Peripheral Interface (SPI) Connections (Cont’d)
FPGA
Direction
Pin Name
Description
During Configuration
After Configuration
VS[2:0]
Input
Variant Select. Instructs the FPGA how Must be at the logic levels shown User I/O
to communicate with the attached SPI in Table 53. Sampled when
Flash PROM. SeeDesign Considerations INIT_B goes High.
for the HSWAP, M[2:0], and VS[2:0] Pins.
S
MOSI
Output
Serial Data Output.
FPGA sends SPI Flash memory User I/O
read commands and starting
address to the PROM’s serial
data input.
DIN
Input
Serial Data Input.
FPGA receives serial data from User I/O
PROM’s serial data output.
CSO_B
Output
Chip Select Output. Active Low.
Connects to the SPI Flash
PROM’s chip-select input. If
Drive CSO_B High after
configuration to disable the
HSWAP = 1, connect this signal SPI Flash and reclaim the
to a 4.7 kΩ pull-up resistor to
3.3V.
MOSI, DIN, and CCLK pins.
Optionally, re-use this pin
and MOSI, DIN, and CCLK
to continue communicating
with SPI Flash.
CCLK
Output
Output
Configuration Clock. Generated by
FPGA internal oscillator. Frequency
controlled by ConfigRate bitstream
generator option. If CCLK PCB trace is
long or has multiple connections,
terminate this output to maintain signal
integrity. See CCLK Design
Drives PROM’s clock input.
User I/O
Considerations.
DOUT
INIT_B
Serial Data Output.
Actively drives. Not used in
single-FPGA designs. In a
daisy-chain configuration, this
pin connects to DIN input of the
next FPGA in the chain.
User I/O
Open-drain Initialization Indicator. Active Low.
bidirectional Goes Low at start of configuration during SPI Flash PROM requires
Active during configuration. If
User I/O. If unused in the
application, drive INIT_B
I/O
Initialization memory clearing process.
Released at end of memory clearing,
when mode select pins are sampled. In
daisy-chain applications, this signal
requires an external 4.7 kΩ pull-up
resistor to VCCO_2.
> 2 ms to awake after powering High.
on, hold INIT_B Low until PROM
is ready. If CRC error detected
during configuration, FPGA
drives INIT_B Low.
DONE
Open-drain FPGA Configuration Done. Low during Low indicates that the FPGA is Pulled High via external
bidirectional configuration. Goes High when FPGA
not yet configured.
pull-up. When High,
I/O
successfully completes configuration.
Requires external 330 Ω pull-up resistor
to 2.5V.
indicates that the FPGA
successfully configured.
PROG_B
Input
Program FPGA. Active Low. When
Must be High to allow
Drive PROG_B Low and
release to reprogram FPGA.
Hold PROG_B to force
FPGA I/O pins into Hi-Z,
allowing direct programming
access to SPI Flash PROM
pins.
asserted Low for 500 ns or longer, forces configuration to start.
the FPGA to restart its configuration
process by clearing configuration
memory and resetting the DONE and
INIT_B pins once PROG_B returns High.
Recommend external 4.7 kΩ pull-up
resistor to 2.5V. Internal pull-up value
may be weaker (see Table 78). If driving
externally with a 3.3V output, use an
open-drain or open-collector driver or use
a current limiting series resistor.
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Product Specification
79
Spartan-3E FPGA Family: Functional Description
for its three power supplies — V
, V
, and V
CCAUX CCO
Voltage Compatibility
CCINT
to I/O Bank 2 (VCCO_2) — to reach their respective
Available SPI Flash PROMs use a single 3.3V supply
voltage. All of the FPGA’s SPI Flash interface signals are
within I/O Bank 2. Consequently, the FPGA’s VCCO_2
supply voltage must also be 3.3V to match the SPI Flash
PROM.
power-on thresholds before beginning the configuration
process.
The SPI Flash PROM is powered by the same voltage
supply feeding the FPGA's VCCO_2 voltage input, typically
3.3V. SPI Flash PROMs specify that they cannot be
Power-On Precautions if 3.3V Supply is Last in
Sequence
accessed until their V supply reaches its minimum data
CC
sheet voltage, followed by an additional delay. For some
devices, this additional delay is as little as 10 µs as shown in
Table 56. For other vendors, this delay is as much as 20 ms.
Spartan-3E FPGAs have a built-in power-on reset (POR)
circuit, as shown in Figure 66, page 103. The FPGA waits
Table 56: Example Minimum Power-On to Select Times for Various SPI Flash PROMs
Data Sheet Minimum Time from VCC min to Select = Low
SPI Flash PROM
Part Number
Vendor
Symbol
TVSL
Value
10
Units
μs
STMicroelectronics
Spansion
M25Pxx
S25FLxxxA
NX25xx
tPU
10
ms
μs
NexFlash
TVSL
10
Macronix
MX25Lxxxx
SST25LFxx
tVSL
10
μs
Silicon Storage Technology
TPU-READ
10
μs
Programmable Microelectronics
Corporation
Pm25LVxxx
TVCS
tVCSL
50
μs
Atmel Corporation
AT45DBxxxD
AT45DBxxxB
30
20
μs
ms
In many systems, the 3.3V supply feeding the FPGA's
VCCO_2 input is valid before the FPGA's other V
supply is last in the sequence, a potential race occurs
between the FPGA and the SPI Flash PROM, as shown in
Figure 55.
and
CCINT
V
supplies, and consequently, there is no issue.
CCAUX
However, if the 3.3V supply feeding the FPGA's VCCO_2
X-Ref Target - Figure 55
3.3V Supply
SPI Flash cannot be selected
SPI Flash PROM
minimum voltage
SPI Flash available for
read operations
SPI Flash
PROM CS
SPI Flash PROM must
be ready for FPGA
access, otherwise delay
FPGA configuration
FPGA VCCO_2 minimum
Power On Reset Voltage
(t
)
delay
VSL
(VCCO2T
)
FPGA accesses
SPI Flash PROM
FPGA initializes configuration
(V
, V
CCINT CCAUX
memory (TPOR
)
already valid)
Time
DS312-2_50b_110206
Figure 55: SPI Flash PROM/FPGA Power-On Timing if 3.3V Supply is Last in Power-On Sequence
If the FPGA's V
valid, then the FPGA waits for VCCO_2 to reach its
minimum threshold voltage before starting configuration.
and V
supplies are already
CCAUX
respective Power On Reset (POR) thresholds, the FPGA
starts the configuration process and begins initializing its
internal configuration memory. Initialization requires
CCINT
This threshold voltage is labeled as V
in Table 74 of
approximately 1 ms (T
, minimum in Table 111 of
CCO2T
POR
Module 3 and ranges from approximately 0.4V to 1.0V,
substantially lower than the SPI Flash PROM's minimum
voltage. Once all three FPGA supplies reach their
Module 3, after which the FPGA de-asserts INIT_B, selects
the SPI Flash PROM, and starts sending the appropriate
read command. The SPI Flash PROM must be ready for
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Spartan-3E FPGA Family: Functional Description
read operations at this time. Spartan-3E FPGAs issue the
read command just once. If the SPI Flash is not ready, then
the FPGA does not properly configure.
such PROMs support up to ConfigRate = 25 and beyond
but require careful data sheet analysis. See Serial
Peripheral Interface (SPI) Configuration Timing for more
detailed timing analysis.
If the 3.3V supply is last in the sequence and does not ramp
fast enough, or if the SPI Flash PROM cannot be ready
when required by the FPGA, delay the FPGA configuration
process by holding either the FPGA's PROG_B input or
INIT_B input Low, as highlighted in Figure 54. Release the
FPGA when the SPI Flash PROM is ready. For example, a
simple R-C delay circuit attached to the INIT_B pin forces
the FPGA to wait for a preselected amount of time.
Alternately, a Power Good signal from the 3.3V supply or a
system reset signal accomplishes the same purpose. Use
an open-drain or open-collector output when driving
PROG_B or INIT_B.
Using the SPI Flash Interface after Configuration
After the FPGA successfully completes configuration, all of
the pins connected to the SPI Flash PROM are available as
user-I/O pins.
If not using the SPI Flash PROM after configuration, drive
CSO_B High to disable the PROM. The MOSI, DIN, and
CCLK pins are then available to the FPGA application.
Because all the interface pins are user I/O after
configuration, the FPGA application can continue to use the
SPI Flash interface pins to communicate with the SPI Flash
PROM, as shown in Figure 56. SPI Flash PROMs offer
random-accessible, byte-addressable, read/write,
non-volatile storage to the FPGA application.
SPI Flash PROM Density Requirements
Table 57 shows the smallest usable SPI Flash PROM to
program a single Spartan-3E FPGA. Commercially
available SPI Flash PROMs range in density from 1 Mbit to
128 Mbits. A multiple-FPGA daisy-chained application
requires a SPI Flash PROM large enough to contain the
sum of the FPGA file sizes. An application can also use a
larger-density SPI Flash PROM to hold additional data
beyond just FPGA configuration data. For example, the SPI
Flash PROM can also store application code for a
MicroBlaze™ RISC processor core integrated in the
Spartan-3E FPGA. See Using the SPI Flash Interface after
Configuration.
SPI Flash PROMs are available in densities ranging from
1 Mbit up to 128 Mbits. However, a single Spartan-3E
FPGA requires less than 6 Mbits. If desired, use a larger
SPI Flash PROM to contain additional non-volatile
application data, such as MicroBlaze processor code, or
other user data such as serial numbers and Ethernet MAC
IDs. In the example shown in Figure 56, the FPGA
configures from SPI Flash PROM. Then using FPGA logic
after configuration, the FPGA copies MicroBlaze code from
SPI Flash into external DDR SDRAM for code execution.
Similarly, the FPGA application can store non-volatile
application data within the SPI Flash PROM.
Table 57: Number of Bits to Program a Spartan-3E
FPGA and Smallest SPI Flash PROM
The FPGA configuration data is stored starting at location 0.
Store any additional data beginning in the next available SPI
Flash PROM sector or page. Do not mix configuration data
and user data in the same sector or page.
Number of
Smallest Usable SPI
Flash PROM
Device
Configuration Bits
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
581,344
1,353,728
2,270,208
3,841,184
5,969,696
1 Mbit
2 Mbit
4 Mbit
4 Mbit
8 Mbit
Similarly, the SPI bus can be expanded to additional SPI
peripherals. Because SPI is a common industry-standard
interface, various SPI-based peripherals are available, such
as analog-to-digital (A/D) converters, digital-to-analog (D/A)
converters, CAN controllers, and temperature sensors.
However, if sufficient I/O pins are available in the
application, Xilinx recommends creating a separate SPI bus
to control peripherals. Creating a second port reduces the
loading on the CCLK and DIN pins, which are crucial for
configuration.
CCLK Frequency
In SPI Flash mode, the FPGA’s internal oscillator generates
the configuration clock frequency. The FPGA provides this
clock on its CCLK output pin, driving the PROM’s clock input
pin. The FPGA starts configuration at its lowest frequency
and increases its frequency for the remainder of the
configuration process if so specified in the configuration
bitstream. The maximum frequency is specified using the
ConfigRate bitstream generator option. The maximum
frequency supported by the FPGA configuration logic
depends on the timing for the SPI Flash device. Without
examining the timing for a specific SPI Flash PROM, use
ConfigRate = 12 or lower. SPI Flash PROMs that support
the FAST READ command support higher data rates. Some
The MOSI, DIN, and CCLK pins are common to all SPI
peripherals. Connect the select input on each additional SPI
peripheral to one of the FPGA user I/O pins. If HSWAP = 0
during configuration, the FPGA holds the select line High. If
HSWAP = 1, connect the select line to +3.3V via an external
4.7 kΩ pull-up resistor to avoid spurious read or write
operations. After configuration, drive the select line Low to
select the desired SPI peripheral.
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Spartan-3E FPGA Family: Functional Description
During the configuration process, CCLK is controlled by the
FPGA and limited to the frequencies generated by the
FPGA. After configuration, the FPGA application can use
other clock signals to drive the CCLK pin and can further
optimize SPI-based communication.
Refer to the individual SPI peripheral data sheet for specific
interface and communication protocol requirements.
X-Ref Target - Figure 56
Spartan-3E FPGA
SPI Serial Flash PROM
FFFFF
User Data
MOSI
DIN
DATA_IN
FPGA-based
SPI Master
MicroBlaze
DATA_OUT
Code
CCLK
CLOCK
FPGA
Configuration
CSO_B
SELECT
+3.3V
0
User I/O
SPI Peripherals
- A/D Converter
DATA_IN
DATA_OUT
CLOCK
- D/A Converter
- CAN Controller
- Displays
- Temperature Sensor
- ASSP
SELECT
DS312-2_47_082009
To other SPI slave peripherals
Figure 56: Using the SPI Flash Interface After Configuration
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Spartan-3E FPGA Family: Functional Description
Daisy-Chaining
If the application requires multiple FPGAs with different
configurations, then configure the FPGAs using a daisy
chain, as shown in Figure 57. Daisy-chaining from a single
SPI serial Flash PROM is supported in Stepping 1 devices.
It is not supported in Stepping 0 devices. Use SPI Flash
mode (M[2:0] = <0:0:1>) for the FPGA connected to the
Platform Flash PROM and Slave Serial mode
diagram—finishes loading its configuration data from the
SPI Flash PROM, the master device uses its DOUT output
pin to supply data to the next device in the daisy-chain, on
the falling CCLK edge.
Design Note
SPI mode daisy chains are supported only in Stepping 1
silicon versions.
(M[2:0] = <1:1:1>) for all other FPGAs in the daisy-chain.
After the master FPGA—the FPGA on the left in the
X-Ref Target - Figure 57
SPI-based daisy-chaining is
only supported in Stepping 1.
!
CCLK
+1.2V
+1.2V
+3.3V
SPI
Serial
VCCINT
Flash
VCCINT
P
P
HSWAP
VCCO_0
VCCO_0
P
HSWAP
VCCO_0
VCCO_2
VCCO_0
I
VCC
DATA_IN
VCCO_2
MOSI
+3.3V
+3.3V
Slave
Serial
Mode
SPI Mode
DIN
DATA_OUT
SELECT
‘0’
‘0’
‘1’
M2
M1
M0
CSO_B
‘1’
‘1’
‘1’
M2
M1
M0
W
WR_PROTECT
HOLD
‘1’
Spartan-3E
FPGA
CLOCK
Spartan-3E
FPGA
Variant Select
GND
‘1’
S
VS2
VS1
VS0
‘1’
CCLK
DOUT
INIT_B
CCLK
DIN
DOUT
INIT_B
DOUT
+2.5V
JTAG
TDI
VCCAUX
TDO
+2.5V
VCCAUX
TDO
+2.5V
TDI
TDI
TMS
TCK
TDO
TMS
TCK
TMS
TCK
+2.5V
+3.3V
PROG_B
DONE
PROG_B
DONE
GND
GND
PROG_B
PROG_B
Recommend
open-drain
driver
TCK
TMS
DONE
INIT_B
DS312-2_48_082009
Figure 57: Daisy-Chaining from SPI Flash Mode (Stepping 1)
In-system programming support is available from some
third-party PROM programmers using a socket adapter with
attached wires. To gain access to the SPI Flash signals,
drive the FPGA’s PROG_B input Low with an open-drain
driver. This action places all FPGA I/O pins, including those
attached to the SPI Flash, in high-impedance (Hi-Z). If the
HSWAP input is Low, the I/Os have pull-up resistors to the
Programming Support
For successful daisy-chaining, the DONE_cycle
configuration option must be set to cycle 5 or sooner. The
default cycle is 4. See Table 69 and the Start-Up section for
additional information.
I
In production applications, the SPI Flash PROM is
V
input on their respective I/O bank. The external
usually pre-programmed before it is mounted on the printed
circuit board. The Xilinx ISE development software
produces industry-standard programming files that can be
used with third-party gang programmers. Consult your
specific SPI Flash vendor for recommended production
programming solutions.
CCO
programming hardware then has direct access to the SPI
Flash pins. The programming access points are highlighted
in the gray box in Figure 53, Figure 54, and Figure 57.
Beginning with the Xilinx ISE 8.2i software release, the
iMPACT programming utility provides direct, in-system
prototype programming support for STMicro M25P-series
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83
Spartan-3E FPGA Family: Functional Description
SPI serial Flash PROMs and the Atmel AT45DB-series
Data Flash PROMs using the Platform Cable USB, Xilinx
Parallel IV, or other compatible programming cable.
Byte-Wide Peripheral Interface (BPI) Parallel
Flash Mode
For additional information, refer to the “Master BPI Mode”
chapter in UG332.
In Byte-wide Peripheral Interface (BPI) mode
(M[2:0] = <0:1:0> or <0:1:1>), a Spartan-3E FPGA
configures itself from an industry-standard parallel NOR
Flash PROM, as illustrated in Figure 58. The FPGA
generates up to a 24-bit address lines to access an
attached parallel Flash. Only 20 address lines are
generated for Spartan-3E FPGAs in the TQ144 package.
Similarly, the XC3S100E FPGA in the CP132 package only
has 20 address lines while the XC3S250E and XC3S500E
FPGAs in the same package have 24 address lines. When
using the VQ100 package, the BPI mode is not available
when using parallel NOR Flash, but is supported using
parallel Platform Flash (XCFxxP).
The BPI configuration interface is primarily designed for
standard parallel NOR Flash PROMs and supports both
byte-wide (x8) and byte-wide/halfword (x8/x16) PROMs.
The interface functions with halfword-only (x16) PROMs,
but the upper byte in a portion of the PROM remains
unused. For configuration, the BPI interface does not
require any specific Flash PROM features, such as boot
block or a specific sector size.
The BPI interface also functions with Xilinx parallel Platform
Flash PROMs (XCFxxP), although the FPGA’s address
lines are left unconnected.
The BPI interface also works equally wells with other
asynchronous memories that use a similar SRAM-style
interface such as SRAM, NVRAM, EEPROM, EPROM, or
masked ROM.
NAND Flash memory is commonly used in memory cards
for digital cameras. Spartan-3E FPGAs do not configure
directly from NAND Flash memories.
The FPGA’s internal oscillator controls the interface timing
and the FPGA supplies the clock on the CCLK output pin.
However, the CCLK signal is not used in single FPGA
applications. Similarly, the FPGA drives three pins Low
during configuration (LDC[2:0]) and one pin High during
configuration (HDC) to the PROM’s control inputs.
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Spartan-3E FPGA Family: Functional Description
X-Ref Target - Figure 58
+1.2V
V
VCCINT
HSWAP
VCCO_0
VCCO_0
P
I
VCCO
VCCO_1
LDC0
V
x8 or
x8/x16
Flash
PROM
CE#
LDC1
OE#
HDC
WE#
BYTE#
LDC2
Not available
in VQ100
D
A[16:0]
package
DQ[15:7]
BPI Mode
VCCO_2
D[7:0]
V
‘0’
‘1’
A
M2
M1
M0
DQ[7:0]
A[n:0]
A[23:17]
GND
V
Spartan-3E
BUSY
CCLK
FPGA
‘0’
‘0’
CSI_B
CSO_B
INIT_B
RDWR_B
+2.5V
JTAG
+2.5V
VCCAUX
TDO
+2.5V
TDI
TDI
TMS
TCK
TDO
TMS
TCK
PROG_B
DONE
GND
PROG_B
Recommend
open-drain
driver
DS312-2_49_082009
Figure 58: Byte-wide Peripheral Interface (BPI) Mode Configured from Parallel NOR Flash PROMs
A
During configuration, the value of the M0 mode pin
determines how the FPGA generates addresses, as shown
Table 58. When M0 = 0, the FPGA generates addresses
starting at 0 and increments the address on every falling
CCLK edge. Conversely, when M0 = 1, the FPGA
generates addresses starting at 0xFF_FFFF(all ones) and
decrements the address on every falling CCLK edge.
Table 58: BPI Addressing Control
M2
M1
M0
0
Start Address
0
Addressing
Incrementing
Decrementing
0
1
1
0xFF_FFFF
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Spartan-3E FPGA Family: Functional Description
This addressing flexibility allows the FPGA to share the
parallel Flash PROM with an external or embedded
processor. Depending on the specific processor
architecture, the processor boots either from the top or
bottom of memory. The FPGA is flexible and boots from the
opposite end of memory from the processor. Only the
processor or the FPGA can boot at any given time. The
FPGA can configure first, holding the processor in reset or
the processor can boot first, asserting the FPGA’s PROG_B
pin.
full-featured user-I/O pin and is powered by the VCCO_0
supply.
The RDWR_B and CSI_B must be Low throughout the
configuration process. After configuration, these pins also
become user I/O.
In a single-FPGA application, the FPGA’s CSO_B and
CCLK pins are not used but are actively driving during the
configuration process. The BUSY pin is not used but also
actively drives during configuration and is available as a
user I/O after configuration.
The mode select pins, M[2:0], are sampled when the
FPGA’s INIT_B output goes High and must be at defined
logic levels during this time. After configuration, when the
FPGA’s DONE output goes High, the mode pins are
available as full-featured user-I/O pins.
After configuration, all of the interface pins except DONE
and PROG_B are available as user I/Os. Furthermore, the
bidirectional SelectMAP configuration peripheral interface
(see Slave Parallel Mode) is available after configuration. To
continue using SelectMAP mode, set the Persist bitstream
generator option to Yes. An external host can then read and
verify configuration data.
P
Similarly, the FPGA’s HSWAP pin must be Low to
enable pull-up resistors on all user-I/O pins or High to
disable the pull-up resistors. The HSWAP control must
remain at a constant logic level throughout FPGA
configuration. After configuration, when the FPGA’s DONE
output goes High, the HSWAP pin is available as
The Persist option will maintain A20-A23 as configuration
pins although they are not used in SelectMAP mode.
Table 59: Byte-Wide Peripheral Interface (BPI) Connections
Pin Name
FPGA Direction
Description
During Configuration
After Configuration
HSWAP
P
Input
User I/O Pull-Up Control. When
Low during configuration, enables configuration.
pull-up resistors in all I/O pins to
Drive at valid logic level throughout User I/O
respective I/O bank VCCO input.
0: Pull-ups during configuration
1: No pull-ups
M[2:0]
Input
Mode Select. Selects the FPGA
configuration mode. See Design
Considerations for the HSWAP,
M[2:0], and VS[2:0] Pins.
M2 = 0, M1 = 1. Set M0 = 0 to start User I/O
at address 0, increment
addresses. Set M0 = 1 to start at
address 0xFFFFFF and
A
decrement addresses. Sampled
when INIT_B goes High.
CSI_B
Input
Input
Chip Select Input. Active Low.
Must be Low throughout
configuration.
User I/O. If bitstream option
Persist=Yes, becomes
part of SelectMap parallel
peripheral interface.
RDWR_B
Read/Write Control. Active Low
write enable. Read functionality
typically only used after
configuration, if bitstream option
Persist=Yes.
Must be Low throughout
configuration.
User I/O. If bitstream option
Persist=Yes, becomes
part of SelectMap parallel
peripheral interface.
LDC0
LDC1
Output
Output
PROM Chip Enable
Connect to PROM chip-select
input (CE#). FPGA drives this
signal Low throughout
configuration.
User I/O. If the FPGA does
not access the PROM after
configuration, drive this pin
High to deselect the
PROM. A[23:0], D[7:0],
LDC[2:1], and HDC then
become available as user
I/O.
PROM Output Enable
Connect to the PROM
User I/O
output-enable input (OE#). The
FPGA drives this signal Low
throughout configuration.
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Spartan-3E FPGA Family: Functional Description
Table 59: Byte-Wide Peripheral Interface (BPI) Connections (Cont’d)
Pin Name
HDC
FPGA Direction
Description
PROM Write Enable
During Configuration
After Configuration
User I/O
Output
Connect to PROM write-enable
input (WE#). FPGA drives this
signal High throughout
configuration.
LDC2
Output
Output
PROM Byte Mode
This signal is not used for x8
PROMs. For PROMs with a x8/x16 after configuration to use a
data width control, connect to
PROM byte-mode input (BYTE#).
See Precautions Using x8/x16
Flash PROMs. FPGA drives this
signal Low throughout
User I/O. Drive this pin High
D
x8/x16 PROM in x16 mode.
configuration.
A[23:0]
Address
Connect to PROM address inputs. User I/O
High-order address lines may not
be available in all packages and
not all may be required. Number of
address lines required depends on
the size of the attached Flash
PROM. FPGA address generation
controlled by M0 mode pin.
Addresses presented on falling
CCLK edge.
Only 20 address lines are available
in TQ144 package.
D[7:0]
Input
Data Input
FPGA receives byte-wide data on User I/O. If bitstream option
these pins in response the address Persist=Yes, becomes
presented on A[23:0]. Data
part of SelectMap parallel
captured by FPGA on rising edge peripheral interface.
of CCLK.
CSO_B
Output
Chip Select Output. Active Low.
Not used in single FPGA
User I/O
applications. In a daisy-chain
configuration, this pin connects to
the CSI_B pin of the next FPGA in
the chain. If HSWAP = 1 in a
multi-FPGA daisy-chain
application, connect this signal to a
4.7 kΩ pull-up resistor to VCCO_2.
Actively drives Low when selecting
a downstream device in the chain.
BUSY
CCLK
Output
Output
Busy Indicator. Typically only used Not used during configuration but User I/O. If bitstream option
after configuration, if bitstream
actively drives.
Persist=Yes, becomes
part of SelectMap parallel
peripheral interface.
option Persist=Yes.
Configuration Clock. Generated Not used in single FPGA
User I/O. If bitstream option
applications but actively drives. In Persist=Yes, becomes
by FPGA internal oscillator.
Frequency controlled by
a daisy-chain configuration, drives part of SelectMap parallel
ConfigRate bitstream generator
the CCLK inputs of all other
peripheral interface.
option. If CCLK PCB trace is long or FPGAs in the daisy-chain.
has multiple connections, terminate
this output to maintain signal
integrity. See CCLK Design
Considerations.
INIT_B
Open-drain
Initialization Indicator. Active Low. Active during configuration. If CRC User I/O. If unused in the
application, drive INIT_B
configuration, FPGA drives INIT_B High.
bidirectional I/O Goes Low at start of configuration error detected during
during the Initialization memory
clearing process. Released at the Low.
end of memory clearing, when the
mode select pins are sampled. In
daisy-chain applications, this signal
requires an external 4.7 kΩ pull-up
resistor to VCCO_2.
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Spartan-3E FPGA Family: Functional Description
Table 59: Byte-Wide Peripheral Interface (BPI) Connections (Cont’d)
Pin Name
DONE
FPGA Direction
Description
During Configuration
After Configuration
Open-drain
FPGA Configuration Done. Low
Low indicates that the FPGA is not Pulled High via external
yet configured.
bidirectional I/O during configuration. Goes High
whenFPGAsuccessfullycompletes
configuration. Requires external
pull-up. When High,
indicates that the FPGA is
successfully configured.
330 Ω pull-up resistor to 2.5V.
PROG_B
Input
Program FPGA. Active Low. When Must be High to allow configuration Drive PROG_B Low and
asserted Low for 500 ns or longer, to start.
forces the FPGA to restart its
configuration process by clearing
configuration memory and resetting
the DONE and INIT_B pins once
PROG_B returns High.
release to reprogram
FPGA. Hold PROG_B to
force FPGA I/O pins into
Hi-Z, allowing direct
programming access to
Flash PROM pins.
Recommend external 4.7 kΩ
pull-up resistor to 2.5V. Internal
pull-up value may be weaker (see
Table 78). If driving externally with a
3.3V output, use an open-drain or
open-collector driver or use a
current limiting series resistor.
Power-On Precautions if 3.3V Supply is Last in Sequence
for a similar description of the issue for SPI Flash PROMs.
Voltage Compatibility
V
The FPGA’s parallel Flash interface signals are within
I/O Banks 1 and 2. The majority of parallel Flash PROMs
use a single 3.3V supply voltage. Consequently, in most
cases, the FPGA’s VCCO_1 and VCCO_2 supply voltages
must also be 3.3V to match the parallel Flash PROM. There
are some 1.8V parallel Flash PROMs available and the
FPGA interfaces with these devices if the VCCO_1 and
VCCO_2 supplies are also 1.8V.
Supported Parallel NOR Flash PROM Densities
Table 60 indicates the smallest usable parallel Flash PROM
to program a single Spartan-3E FPGA. Parallel Flash
density is specified in bits but addressed as bytes. The
FPGA presents up to 24 address lines during configuration
but not all are required for single FPGA applications.
Table 60 shows the minimum required number of address
lines between the FPGA and parallel Flash PROM. The
actual number of address line required depends on the
density of the attached parallel Flash PROM.
Power-On Precautions if PROM Supply is Last in
Sequence
Like SPI Flash PROMs, parallel Flash PROMs typically
require some amount of internal initialization time when the
supply voltage reaches its minimum value.
A multiple-FPGA daisy-chained application requires a
parallel Flash PROM large enough to contain the sum of the
FPGA file sizes. An application can also use a larger-density
parallel Flash PROM to hold additional data beyond just
FPGA configuration data. For example, the parallel Flash
PROM can also contain the application code for a MicroBlaze
RISC processor core implemented within the Spartan-3E
FPGA. After configuration, the MicroBlaze processor can
execute directly from external Flash or can copy the code to
other, faster system memory before executing the code.
The PROM supply voltage also connects to the FPGA’s
VCCO_2 supply input. In many systems, the PROM supply
feeding the FPGA’s VCCO_2 input is valid before the
FPGA’s other V
and V
supplies, and
CCINT
CCAUX
consequently, there is no issue. However, if the PROM
supply is last in the sequence, a potential race occurs
between the FPGA and the parallel Flash PROM. See
Table 60: Number of Bits to Program a Spartan-3E FPGA and Smallest Parallel Flash PROM
Uncompressed
File Sizes (bits)
Smallest Usable
Parallel Flash PROM
Minimum Required
Address Lines
Spartan-3E FPGA
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
581,344
1,353,728
2,270,208
3,841,184
5,969,696
1 Mbit
2 Mbit
4 Mbit
4 Mbit
8 Mbit
A[16:0]
A[17:0]
A[18:0]
A[18:0]
A[19:0]
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Spartan-3E FPGA Family: Functional Description
Because all the interface pins are user I/Os after
Compatible Flash Families
configuration, the FPGA application can continue to use the
interface pins to communicate with the parallel Flash
PROM. Parallel Flash PROMs are available in densities
ranging from 1 Mbit up to 128 Mbits and beyond. However,
a single Spartan-3E FPGA requires less than 6 Mbits for
configuration. If desired, use a larger parallel Flash PROM
to contain additional non-volatile application data, such as
MicroBlaze processor code, or other user data, such as
serial numbers and Ethernet MAC IDs. In such an example,
the FPGA configures from parallel Flash PROM. Then using
FPGA logic after configuration, a MicroBlaze processor
embedded within the FPGA can either execute code directly
from parallel Flash PROM or copy the code to external DDR
SDRAM and execute from DDR SDRAM. Similarly, the
FPGA application can store non-volatile application data
within the parallel Flash PROM.
The Spartan-3E BPI configuration interface operates with a
wide variety of x8 or x8/x16 parallel NOR Flash devices.
Table 61 provides a few Flash memory families that operate
with the Spartan-3E BPI interface. Consult the data sheet
for the desired parallel NOR Flash to determine its suitability
The basic timing requirements and waveforms are provided
in Byte Peripheral Interface (BPI) Configuration Timing
(Module 3).
Table 61: Compatible Parallel NOR Flash Families
Flash Vendor
Numonyx
Flash Memory Family
M29W, J3D StrataFlash
AT29 / AT49
Atmel
Spansion
Macronix
S29
MX29
The FPGA configuration data is stored starting at either at
location 0 or the top of memory (addresses all ones) or at
both locations for MultiBoot mode. Store any additional data
beginning in other available parallel Flash PROM sectors.
Do not mix configuration data and user data in the same
sector.
CCLK Frequency
In BPI mode, the FPGA’s internal oscillator generates the
configuration clock frequency that controls all the interface
timing. The FPGA starts configuration at its lowest
frequency and increases its frequency for the remainder of
the configuration process if so specified in the configuration
bitstream. The maximum frequency is specified using the
ConfigRate bitstream generator option.
Similarly, the parallel Flash PROM interface can be
expanded to additional parallel peripherals.
The address, data, and LDC1 (OE#) and HDC (WE#)
control signals are common to all parallel peripherals.
Connect the chip-select input on each additional peripheral
to one of the FPGA user I/O pins. If HSWAP = 0 during
configuration, the FPGA holds the chip-select line High via
an internal pull-up resistor. If HSWAP = 1, connect the
select line to +3.3V via an external 4.7 kΩ pull-up resistor to
avoid spurious read or write operations. After configuration,
drive the select line Low to select the desired peripheral.
Refer to the individual peripheral data sheet for specific
interface and communication protocol requirements.
Table 62: Maximum ConfigRate Settings for Parallel
Flash PROMs (Commercial Temperature Range)
Maximum ConfigRate
Flash Read Access Time
Setting
250 ns
115 ns
45 ns
3
6
12
Table 62 shows the maximum ConfigRate settings for
various typical PROM read access times over the
Commercial temperature operating range. See Byte
Peripheral Interface (BPI) Configuration Timing (Module 3)
and UG332 for more detailed information. Despite using
slower ConfigRate settings, BPI mode is equally fast as the
other configuration modes. In BPI mode, data is accessed
at the ConfigRate frequency and internally serialized with
an 8X clock frequency.
The FPGA optionally supports a 16-bit peripheral interface
by driving the LDC2 (BYTE#) control pin High after
configuration. See Precautions Using x8/x16 Flash PROMs
for additional information.
The FPGA provides up to 24 address lines during
configuration, addressing up to 128 Mbits (16 Mbytes). If
using a larger parallel PROM, connect the upper address
lines to FPGA user I/O. During configuration, the upper
address lines will be pulled High if HSWAP = 0. Otherwise,
use external pull-up or pull-down resistors on these address
lines to define their values during configuration.
Using the BPI Interface after Configuration
After the FPGA successfully completes configuration, all
pins connected to the parallel Flash PROM are available as
user I/Os.
Precautions Using x8/x16 Flash PROMs
D
Most low- to mid-density PROMs are byte-wide (x8)
If not using the parallel Flash PROM after configuration,
drive LDC0 High to disable the PROM’s chip-select input.
The remainder of the BPI pins then become available to the
FPGA application, including all 24 address lines, the eight
data lines, and the LDC2, LDC1, and HDC control pins.
only. Many higher-density Flash PROMs support both
byte-wide (x8) and halfword-wide (x16) data paths and
include a mode input called BYTE# that switches between
x8 or x16. During configuration, Spartan-3E FPGAs only
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Spartan-3E FPGA Family: Functional Description
support byte-wide data. However, after configuration, the
FPGA supports either x8 or x16 modes. In x16 mode, up to
eight additional user I/O pins are required for the upper data
bits, D[15:8].
Other vendors (AMD, Atmel, Silicon Storage Technology,
some STMicroelectronics devices) use a pin-efficient
interface but change the function of one pin, called
IO15/A-1, depending if the PROM is in x8 or x16 mode. In
x8 mode, BYTE# = 0, this pin is the least-significant
address line. The A0 address line selects the halfword
location. The A-1 address line selects the byte location.
When in x16 mode, BYTE# = 1, the IO15/A-1 pin becomes
the most-significant data bit, D15 because byte addressing
is not required in this mode. Check to see if the Flash
PROM has a pin named “IO15/A-1” or “DQ15/A-1”. If so, be
careful to connect x8/x16 Flash PROMs correctly, as shown
in Table 63. Also, remember that the D[14:8] data
Connecting a Spartan-3E FPGA to a x8/x16 Flash PROM is
simple, but does require a precaution. Various Flash PROM
vendors use slightly different interfaces to support both x8
and x16 modes. Some vendors (Intel, Micron, some
STMicroelectronics devices) use a straightforward interface
with pin naming that matches the FPGA connections.
However, the PROM’s A0 pin is wasted in x16 applications
and a separate FPGA user-I/O pin is required for the D15
data line. Fortunately, the FPGA A0 pin is still available as a
user I/O after configuration, even though it connects to the
Flash PROM.
connections require FPGA user I/O pins but that the D15
data is already connected for the FPGA’s A0 pin.
Table 63: FPGA Connections to Flash PROM with IO15/A-1 Pin
Connection to Flash PROM with
IO15/A-1 Pin
x8 Flash PROM Interface After
x16 Flash PROM Interface After
FPGA Configuration
FPGA Pin
FPGA Configuration
LDC2
BYTE#
Drive LDC2 Low or leave
unconnected and tie PROM BYTE#
input to GND
Drive LCD2 High
LDC1
LDC0
OE#
CS#
Active-Low Flash PROM
output-enable control
Active-Low Flash PROM
output-enable control
Active-Low Flash PROM chip-select Active-Low Flash PROM chip-select
control
control
HDC
A[23:1]
A0
WE#
Flash PROM write-enable control
A[n:0]
Flash PROM write-enable control
A[n:0]
A[n:0]
IO15/A-1
IO15/A-1 is the least-significant
address input
IO15/A-1 is the most-significant data
line, IO15
D[7:0]
IO[7:0]
IO[7:0]
IO[7:0]
User I/O
Upper data lines IO[14:8] not required
unless used as x16 Flash interface after required
configuration
Upper data lines IO[14:8] not
IO[14:8]
Some x8/x16 Flash PROMs have a long setup time
requirement on the BYTE# signal. For the FPGA to
configure correctly, the PROM must be in x8 mode with
BYTE# = 0 at power-on or when the FPGA’s PROG_B pin is
pulsed Low. If required, extend the BYTE# setup time for a
3.3V PROM using an external 680 Ω pull-down resistor on
the FPGA’s LDC2 pin or by delaying assertion of the CSI_B
select input to the FPGA.
chain between the first and last FPGAs must from either the
Spartan-3E or Virtex®-5 FPGA families.
After the master FPGA—the FPGA on the left in the
diagram—finishes loading its configuration data from the
parallel Flash PROM, the master device continues
generating addresses to the Flash PROM and asserts its
CSO_B output Low, enabling the next FPGA in the
daisy-chain. The next FPGA then receives parallel
configuration data from the Flash PROM. The master
FPGA’s CCLK output synchronizes data capture.
Daisy-Chaining
If the application requires multiple FPGAs with different
configurations, then configure the FPGAs using a daisy
chain, as shown in Figure 59. Use BPI mode
(M[2:0] = <0:1:0> or <0:1:1>) for the FPGA connected to
the parallel NOR Flash PROM and Slave Parallel mode
(M[2:0] = <1:1:0>) for all downstream FPGAs in the
daisy-chain. If there are more than two FPGAs in the chain,
then last FPGA in the chain can be from any Xilinx FPGA
family. However, all intermediate FPGAs located in the
If HSWAP = 1, an external 4.7kΩ pull-up resistor must be
added on the CSO_B pin. If HSWAP = 0, no external pull-up
is necessary.
Design Note
BPI mode daisy chain software support is available starting
in ISE 8.2i.
http://www.xilinx.com/support/answers/23061.htm
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90
Spartan-3E FPGA Family: Functional Description
Also, in a multi-FPGA daisy-chain configuration of more
than two devices, all intermediate FPGAs between the first
and last devices must be Spartan-3E or Virtex-5 FPGAs.
The last FPGA in the chain can be from any Xilinx FPGA
family.
BPI Mode Interaction with Right and Bottom Edge
Global Clock Inputs
Some of the BPI mode configuration pins are shared with
global clock inputs along the right and bottom edges of the
device (Bank 1 and Bank 2, respectively). These pins are
not easily reclaimable for clock inputs after configuration,
especially if the FPGA application access the parallel NOR
Flash after configuration. Table 64 summarizes the shared
pins.
Table 64: Shared BPI Configuration Mode and Global
Buffer Input Pins
Device
Edge
Global Buffer
Input Pin
BPI Mode
Configuration Pin
GCLK0
GCLK2
RDWR_B
D2
GCLK3
D1
Bottom
GCLK12
GCLK13
GCLK14
GCLK15
RHCLK0
RHCLK1
RHCLK2
RHCLK3
RHCLK4
RHCLK5
RHCLK6
RHCLK7
D7
D6
D4
D3
A10
A9
A8
A7
Right
A6
A5
A4
A3
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Spartan-3E FPGA Family: Functional Description
configuration file, then subsequent reconfigurations using
the JTAG port will fail. Potential workarounds include setting
the mode pins for JTAG configuration (M[2:0] = <1:0:1>) or
offsetting the initial memory location in Flash by 0x2000.
Stepping 0 Limitations when Reprogramming via
JTAG if FPGA Set for BPI Configuration
The FPGA can always be reprogrammed via the JTAG port,
regardless of the mode pin (M[2:0]) settings. However,
Stepping 0 devices have a minor limitation. If a Stepping 0
FPGA is set to configure in BPI mode and the FPGA is
attached to a parallel memory containing a valid FPGA
Stepping 1 devices fully support JTAG configuration even
when the FPGA mode pins are set for BPI mode.
X-Ref Target - Figure 59
CCLK
D[7:0]
+1.2V
+1.2V
V
VCCINT
VCCINT
P
HSWAP
VCCO_0
VCCO_0
P
HSWAP
VCCO_0
VCCO_0
VCCO_1
I
VCC
VCCO_1
LDC0
V
VCCO_1
CE#
x8 or
x8/x16
Flash
LDC1
OE#
HDC
WE#
BYTE#
PROM
LDC2
Not available
in VQ100
package
D
A[16:0]
Slave
Parallel
Mode
DQ[15:7]
BPI Mode
VCCO_2
D[7:0]
VCCO_2
D[7:0]
V
V
‘0’
‘1’
A
M2
M1
M0
DQ[7:0]
A[n:0]
‘1’
‘1’
‘0’
M2
M1
M0
A[23:17]
GND
Spartan-3E
FPGA
Spartan-3E
FPGA
BUSY
CCLK
BUSY
CCLK
‘0’
‘0’
CSI_B
CSO_B
INIT_B
CSI_B
CSO_B
CSO_B
RDWR_B
‘0’
RDWR_B
INIT_B
2.5V
JTAG
VCCAUX
TDO
+2.5V
VCCAUX
TDO
+2.5V
TDI
TDI
TDI
TMS
TCK
TDO
TMS
TCK
TMS
TCK
V
+2.5V
PROG_B
DONE
PROG_B
DONE
GND
GND
PROG_B
PROG_B
Recommend
open-drain
driver
TCK
TMS
DONE
INIT_B
DS312-2_50_082009
Figure 59: Daisy-Chaining from BPI Flash Mode
highlighted in the gray boxes in Figure 58 and Figure 59.
In-System Programming Support
I
The FPGA itself can also be used as a parallel Flash PROM
programmer during development and test phases. Initially,
an FPGA-based programmer is downloaded into the FPGA
via JTAG. Then the FPGA performs the Flash PROM
programming algorithms and receives programming data
from the host via the FPGA’s JTAG interface. See the
Embedded System Tools Reference Manual.
In a production application, the parallel Flash PROM is
usually preprogrammed before it is mounted on the printed
circuit board. In-system programming support is available
from third-party boundary-scan tool vendors and from some
third-party PROM programmers using a socket adapter with
attached wires. To gain access to the parallel Flash signals,
drive the FPGA’s PROG_B input Low with an open-drain
driver. This action places all FPGA I/O pins, including those
attached to the parallel Flash, in high-impedance (Hi-Z). If
the HSWAP input is Low, the I/Os have pull-up resistors to
Dynamically Loading Multiple Configuration
Images Using MultiBoot Option
the V
input on their respective I/O bank. The external
CCO
For additional information, refer to the “Reconfiguration and
MultiBoot” chapter in UG332.
programming hardware then has direct access to the
parallel Flash pins. The programming access points are
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Spartan-3E FPGA Family: Functional Description
After the FPGA configures itself using BPI mode from one
end of the parallel Flash PROM, then the FPGA can trigger
a MultiBoot event and reconfigure itself from the opposite
end of the parallel Flash PROM. MultiBoot is only available
when using BPI mode and only for applications with a single
Spartan-3E FPGA.
Figure 60 shows an example usage. At power up, the FPGA
loads itself from the attached parallel Flash PROM. In this
example, the M0 mode pin is Low so the FPGA starts at
address 0 and increments through the Flash PROM
memory locations. After the FPGA completes configuration,
the application initially loaded into the FPGA performs a
board-level or system test using FPGA logic. If the test is
successful, the FPGA then triggers a MultiBoot event,
causing the FPGA to reconfigure from the opposite end of
the Flash PROM memory. This second configuration
contains the FPGA application for normal operation.
By default, MultiBoot mode is disabled. To trigger a
MultiBoot event, assert a Low pulse lasting at least 300 ns
on the MultiBoot Trigger (MBT) input to the
STARTUP_SPARTAN3E library primitive. When the MBT
signal returns High after the 300 ns or longer pulse, the
FPGA automatically reconfigures from the opposite end of
the parallel Flash memory.
Similarly, the general FPGA application could trigger
another MultiBoot event at any time to reload the
diagnostics design, and so on.
X-Ref Target - Figure 60
Parallel Flash PROM
Parallel Flash PROM
FFFFFF
FFFFFF
General
FPGA
General
FPGA
Application
Application
STARTUP_SPARTAN3E
GSR
User Area
GTS
MBT
User Area
> 300 ns
CLK
Diagnostics
FPGA
Application
Diagnostics
FPGA
Application
Reconfigure
0
0
First Configuration
Second Configuration
DS312-2_51_103105
Figure 60: Use MultiBoot to Load Alternate Configuration Images
In another potential application, the initial design loaded into
the FPGA image contains a “golden” or “fail-safe”
configuration image, which then communicates with the
outside world and checks for a newer image. If there is a
new configuration revision and the new image verifies as
good, the “golden” configuration triggers a MultiBoot event
to load the new image.
When a MultiBoot event is triggered, the FPGA then again
drives its configuration pins as described in Table 59.
However, the FPGA does not assert the PROG_B pin. The
system design must ensure that no other device drives on
these same pins during the reconfiguration process. The
FPGA’s DONE, LDC[2:0], or HDC pins can temporarily
disable any conflicting drivers during reconfiguration.
Asserting the PROG_B pin Low overrides the MultiBoot
feature and forces the FPGA to reconfigure starting from the
end of memory defined by the mode pins, shown in
Table 58.
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Spartan-3E FPGA Family: Functional Description
X-Ref Target - Figure 61
+1.2V
VCCINT
P
HSWAP
VCCO_0
VCCO_0
Slave
Parallel
Mode
VCCO_2
V
V
‘1’
‘1’
‘0’
M2
M1
M0
Intelligent
Download Host
V
Spartan-3E
FPGA
VCC
D[7:0]
D[7:0]
Configuration
Memory
BUSY
SELECT
BUSY
Source
CSI_B
RDWR_B
CCLK
CSO_B
READ/WRITE
CLOCK
INIT_B
- Internal memory
- Disk drive
- Over network
- Over RF link
PROG_B
DONE
VCCAUX
TDO
+2.5V
INIT_B
TDI
TMS
TCK
GND
+2.5V
- Microcontroller
- Processor
- Tester
PROG_B
DONE
GND
- Computer
PROG_B
Recommend
+2.5V
JTAG
open-drain
driver
TDI
TMS
TCK
TDO
DS312-2_52_082009
Figure 61: Slave Parallel Configuration Mode
Slave Parallel Mode
For additional information, refer to the “Slave Parallel
(SelectMAP) Mode” chapter in UG332.
The FPGA captures data on the rising CCLK edge. If the
CCLK frequency exceeds 50 MHz, then the host must also
monitor the FPGA’s BUSY output. If the FPGA asserts
BUSY High, the host must hold the data for an additional
clock cycle, until BUSY returns Low. If the CCLK frequency
is 50 MHz or below, the BUSY pin may be ignored but
actively drives during configuration.
In Slave Parallel mode (M[2:0] = <1:1:0>), an external host,
such as a microprocessor or microcontroller, writes
byte-wide configuration data into the FPGA, using a typical
peripheral interface as shown in Figure 61.
The external download host starts the configuration process
by pulsing PROG_B and monitoring that the INIT_B pin
goes High, indicating that the FPGA is ready to receive its
first data. The host asserts the active-Low chip-select signal
(CSI_B) and the active-Low Write signal (RDWR_B). The
host then continues supplying data and clock signals until
either the FPGA’s DONE pin goes High, indicating a
successful configuration, or until the FPGA’s INIT_B pin
goes Low, indicating a configuration error.
The configuration process requires more clock cycles than
indicated from the configuration file size. Additional clocks
are required during the FPGA’s start-up sequence,
especially if the FPGA is programmed to wait for selected
Digital Clock Managers (DCMs) to lock to their respective
clock inputs (see Start-Up, page 106).
If the Slave Parallel interface is only used to configure the
FPGA, never to read data back, then the RDWR_B signal
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Spartan-3E FPGA Family: Functional Description
can also be eliminated from the interface. However,
RDWR_B must remain Low during configuration.
The Persist option will maintain A20-A23 as configuration
pins although they are not used in SelectMAP mode.
After configuration, all of the interface pins except DONE
and PROG_B are available as user I/Os. Alternatively, the
bidirectional SelectMAP configuration interface is available
after configuration. To continue using SelectMAP mode, set
the Persist bitstream generator option to Yes. The external
host can then read and verify configuration data.
The Slave Parallel mode is also used with BPI mode to
create multi-FPGA daisy-chains. The lead FPGA is set for
BPI mode configuration; all the downstream daisy-chain
FPGAs are set for Slave Parallel configuration, as
highlighted in Figure 59.
Table 65: Slave Parallel Mode Connections
Pin Name
FPGA Direction
Description
During Configuration
After Configuration
User I/O
HSWAP
Input
User I/O Pull-Up Control. When
Low during configuration, enables
pull-up resistors in all I/O pins to
respective I/O bank VCCO input.
Drive at valid logic level
throughout configuration.
0: Pull-ups during configuration
1: No pull-ups
M[2:0]
D[7:0]
Input
Input
Mode Select. Selects the FPGA
configuration mode. See Design
Considerations for the HSWAP,
M[2:0], and VS[2:0] Pins.
M2 = 1, M1 = 1, M0 = 0 Sampled User I/O
when INIT_B goes High.
Data Input.
Byte-wide data provided by host. User I/O. If bitstream
FPGA captures data on rising
CCLK edge.
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
BUSY
Output
Busy Indicator.
If CCLK frequency is < 50 MHz,
User I/O. If bitstream
option Persist=Yes,
this pin may be ignored. When
High, indicates that the FPGA is becomes part of
not ready to receive additional
SelectMap parallel
configuration data. Host must hold peripheral interface.
data an additional clock cycle.
CSI_B
Input
Input
Chip Select Input. Active Low.
Must be Low throughout
configuration.
User I/O. If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
RDWR_B
CCLK
Read/Write Control. Active Low
write enable.
Must be Low throughout
configuration.
User I/O. If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
Input
Configuration Clock. If CCLK PCB External clock.
trace is long or has multiple
connections, terminate this output to
maintain signal integrity. See CCLK
Design Considerations.
User I/O If bitstream option
Persist=Yes, becomes
part of SelectMap parallel
peripheral interface.
CSO_B
Output
Chip Select Output. Active Low.
Not used in single FPGA
User I/O
applications. In a daisy-chain
configuration, this pin connects to
the CSI_B pin of the next FPGA in
the chain. Actively drives.
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Table 65: Slave Parallel Mode Connections (Cont’d)
Pin Name
FPGA Direction
Description
During Configuration
After Configuration
INIT_B
Open-drain
bidirectional I/O Goes Low at the start of
Initialization Indicator. Active Low. Active during configuration. If
User I/O. If unused in the
application, drive INIT_B
High.
CRC error detected during
configuration during the Initialization configuration, FPGA drives
memory clearing process. Released INIT_B Low.
at the end of memory clearing, when
mode select pins are sampled. In
daisy-chain applications, this signal
requires an external 4.7 kΩ pull-up
resistor to VCCO_2.
DONE
Open-drain
FPGA Configuration Done. Low
Low indicates that the FPGA is not Pulled High via external
bidirectional I/O during configuration. Goes High
when FPGA successfully completes
configuration. Requires external 330
Ω pull-up resistor to 2.5V.
yet configured.
pull-up. When High,
indicates that the FPGA
successfully configured.
PROG_B
Input
Program FPGA. Active Low. When Must be High to allow
Drive PROG_B Low and
release to reprogram
FPGA.
asserted Low for 500 ns or longer,
forces the FPGA to restart its
configuration process by clearing
configuration memory and resetting
the DONE and INIT_B pins once
PROG_B returns High. Recommend
external 4.7 kΩ pull-up resistor to
2.5V. Internal pull-up value may be
weaker (see Table 78). If driving
externally with a 3.3V output, use an
open-drain or open-collector driver
or use a current limiting series
resistor.
configuration to start.
Voltage Compatibility
V
Most Slave Parallel interface signals are within the
FPGA’s I/O Bank 2, supplied by the VCCO_2 supply input.
The VCCO_2 voltage can be 1.8V, 2.5V, or 3.3V to match
the requirements of the external host, ideally 2.5V. Using
1.8V or 3.3V requires additional design considerations as
the DONE and PROG_B pins are powered by the FPGA’s
2.5V V
supply. See XAPP453: The 3.3V
CCAUX
Configuration of Spartan-3 FPGAs for additional
information.
Daisy-Chaining
If the application requires multiple FPGAs with different
configurations, then configure the FPGAs using a daisy
chain. Use Slave Parallel mode (M[2:0] = <1:1:0>) for all
FPGAs in the daisy-chain. The schematic in Figure 62 is
optimized for FPGA downloading and does not support the
SelectMAP read interface. The FPGA’s RDWR_B pin must
be Low during configuration.
After the lead FPGA is filled with its configuration data, the
lead FPGA enables the next FPGA in the daisy-chain by
asserting is chip-select output, CSO_B.
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Spartan-3E FPGA Family: Functional Description
X-Ref Target - Figure 62
D[7:0]
CCLK
+1.2V
+1.2V
VCCINT
VCCINT
P
HSWAP
VCCO_0
VCCO_0
VCCO_1
P
HSWAP
VCCO_0
VCCO_0
VCCO_1
VCCO_1
LDC0
LDC1
HDC
VCCO_1
LDC0
LDC1
HDC
Slave
Parallel
Mode
Slave
Parallel
Mode
LDC2
LDC2
VCCO_2
VCCO_2
V
V
V
V
‘1’
‘1’
‘0’
M2
M1
M0
‘1’
‘1’
‘0’
M2
M1
M0
Intelligent
Download Host
Spartan-3E
Spartan-3E
FPGA
VCC
DATA[7:0]
BUSY
FPGA
D[7:0]
BUSY
CSI_B
D[7:0]
Configuration
Memory
BUSY
Source
SELECT
READ/WRITE
CLOCK
CSO_B
CSI_B
RDWR_B
CCLK
CSO_B
CSO_B
‘0’
RDWR_B
CCLK
INIT_B
‘0’
INIT_B
•Internal memory
•Disk drive
PROG_B
DONE
•Over network
•Over RF link
VCCAUX
TDO
+2.5V
VCCAUX
TDO
+2.5V
INIT_B
TDI
TDI
TMS
TCK
TMS
TCK
GND
+2.5V
•Microcontroller
•Processor
•Tester
PROG_B
DONE
PROG_B
DONE
GND
GND
PROG_B
PROG_B
DONE
Recommend
open-drain
driver
2.5V
JTAG
INIT_B
TDI
TMS
TCK
TDO
TMS
TCK
DS312-2_53_082009
Figure 62: Daisy-Chaining using Slave Parallel Mode
Slave Serial Mode
For additional information, refer to the “Slave Serial Mode”
chapter in UG332.
The intelligent host starts the configuration process by
pulsing PROG_B and monitoring that the INIT_B pin goes
High, indicating that the FPGA is ready to receive its first
data. The host then continues supplying data and clock
signals until either the DONE pin goes High, indicating a
successful configuration, or until the INIT_B pin goes Low,
indicating a configuration error. The configuration process
requires more clock cycles than indicated from the
configuration file size. Additional clocks are required during
the FPGA’s start-up sequence, especially if the FPGA is
programmed to wait for selected Digital Clock Managers
(DCMs) to lock to their respective clock inputs (see
Start-Up, page 106).
In Slave Serial mode (M[2:0] = <1:1:1>), an external host
such as a microprocessor or microcontroller writes serial
configuration data into the FPGA, using the synchronous
serial interface shown in Figure 63. The serial configuration
data is presented on the FPGA’s DIN input pin with
sufficient setup time before each rising edge of the
externally generated CCLK clock input.
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Spartan-3E FPGA Family: Functional Description
X-Ref Target - Figure 63
+1.2V
VCCINT
P
HSWAP
VCCO_0
VCCO_0
VCCO_2
V
Slave
Serial
Mode
V
‘1’
‘1’
‘1’
M2
M1
M0
Intelligent
V
Download Host
Spartan-3E
FPGA
VCC
Configuration
CLOCK
CCLK
DIN
Memory
Source
SERIAL_OUT
PROG_B
DONE
DOUT
INIT_B
• Internal memory
• Disk drive
VCCAUX
TDO
+2.5V
INIT_B
TDI
• Over network
• Over RF link
GND
TMS
TCK
+2.5V
• Microcontroller
• Processor
• Tester
PROG_B
DONE
GND
• Computer
PROG_B
Recommend
open-drain
driver
+2.5V
JTAG
TDI
TMS
TCK
TDO
DS312-2_54_082009
Figure 63: Slave Serial Configuration
The mode select pins, M[2:0], are sampled when the
FPGA’s INIT_B output goes High and must be at defined
logic levels during this time. After configuration, when the
FPGA’s DONE output goes High, the mode pins are
available as full-featured user-I/O pins.
Voltage Compatibility
V
Most Slave Serial interface signals are within the
FPGA’s I/O Bank 2, supplied by the VCCO_2 supply input.
The VCCO_2 voltage can be 3.3V, 2.5V, or 1.8V to match
the requirements of the external host, ideally 2.5V. Using
3.3V or 1.8V requires additional design considerations as
the DONE and PROG_B pins are powered by the FPGA’s
P
Similarly, the FPGA’s HSWAP pin must be Low to
enable pull-up resistors on all user-I/O pins or High to
disable the pull-up resistors. The HSWAP control must
remain at a constant logic level throughout FPGA
configuration. After configuration, when the FPGA’s DONE
output goes High, the HSWAP pin is available as
full-featured user-I/O pin and is powered by the VCCO_0
supply.
2.5V V
supply. See XAPP453: The 3.3V
CCAUX
Configuration of Spartan-3 FPGAs for additional
information.
Daisy-Chaining
If the application requires multiple FPGAs with different
configurations, then configure the FPGAs using a daisy
chain, as shown in Figure 64. Use Slave Serial mode
(M[2:0] = <1:1:1>) for all FPGAs in the daisy-chain. After
the lead FPGA is filled with its configuration data, the lead
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Spartan-3E FPGA Family: Functional Description
FPGA passes configuration data via its DOUT output pin to
the next FPGA on the falling CCLK edge.
Table 66: Slave Serial Mode Connections
Pin Name
FPGA Direction
Description
During Configuration
After Configuration
User I/O
HSWAP
Input
User I/O Pull-Up Control. When Drive at valid logic level
Low during configuration, enables throughout configuration.
pull-up resistors in all I/O pins to
respective I/O bank V
input.
CCO
0: Pull-up during configuration
1: No pull-ups
M[2:0]
Input
Mode Select. Selects the FPGA
configuration mode. See Design
Considerations for the HSWAP,
M[2:0], and VS[2:0] Pins.
M2 = 1, M1 = 1, M0 = 1 Sampled User I/O
when INIT_B goes High.
DIN
Input
Input
Data Input.
Serial data provided by host.
FPGA captures data on rising
CCLK edge.
User I/O
User I/O
CCLK
Configuration Clock. If CCLK
PCB trace is long or has multiple
connections, terminate this output
to maintain signal integrity. See
CCLK Design Considerations.
External clock.
INIT_B
Open-drain
Initialization Indicator. Active
Active during configuration. If
CRC error detected during
configuration, FPGA drives
INIT_B Low.
User I/O. If unused in the
application, drive INIT_B
High.
bidirectional I/O Low. Goes Low at start of
configuration during Initialization
memory clearing process.
Released at end of memory
clearing, when mode select pins
are sampled. In daisy-chain
applications, this signal requires
an external 4.7 kΩ pull-up resistor
to VCCO_2.
DONE
Open-drain
FPGA Configuration Done. Low Low indicates that the FPGA is not Pulled High via external
bidirectional I/O during configuration. Goes High
when FPGA successfully
yet configured.
pull-up. When High,
indicates that the FPGA
successfully configured.
completes configuration. Requires
external 330 Ω pull-up resistor to
2.5V.
PROG_B
Input
Program FPGA. Active Low.
Must be High to allow
Drive PROG_B Low and
release to reprogram
FPGA.
When asserted Low for 500 ns or configuration to start.
longer, forces the FPGA to restart
its configuration process by
clearingconfigurationmemoryand
resetting the DONE and INIT_B
pins once PROG_B returns High.
Recommend external 4.7 kΩ
pull-up resistor to 2.5V. Internal
pull-up value may be weaker (see
Table 78). If driving externally with
a 3.3V output, use an open-drain
or open-collector driver or use a
current limiting series resistor.
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Spartan-3E FPGA Family: Functional Description
X-Ref Target - Figure 64
CCLK
+1.2V
+1.2V
VCCINT
VCCINT
P
HSWAP
VCCO_0
VCCO_0
P
HSWAP
VCCO_0
VCCO_0
VCCO_2
VCCO_2
V
VCCO_2
Slave
Serial
Mode
Slave
Serial
Mode
V
‘1’
‘1’
‘1’
M2
M1
M0
‘1’
‘1’
‘1’
M2
M1
M0
Intelligent
V
Download Host
Spartan-3E
FPGA
Spartan-3E
FPGA
VCC
Configuration
Memory
Source
CLOCK
CCLK
DIN
CCLK
DIN
SERIAL_OUT
PROG_B
DONE
DOUT
DOUT
INIT_B
DOUT
INIT_B
•Internal memory
•Disk drive
VCCAUX
TDO
+2.5V
VCCAUX
TDO
+2.5V
INIT_B
TDI
TDI
•Over network
•Over RF link
GND
TMS
TCK
TMS
TCK
+2.5V
•Microcontroller
•Processor
•Tester
PROG_B
DONE
PROG_B
DONE
GND
GND
•Computer
PROG_B
PROG_B
DONE
Recommend
open-drain
driver
INIT_B
+2.5V
JTAG
TDI
TMS
TCK
TDO
TMS
TCK
DS312-2_55_082009
Figure 64: Daisy-Chaining using Slave Serial Mode
JTAG Mode
For additional information, refer to the “JTAG Configuration
Mode and Boundary-Scan” chapter in UG332.
The FPGA bitstream may be corrupted and the DONE pin
may go High. The following Answer Record contains
additional information.
The Spartan-3E FPGA has a dedicated four-wire IEEE
1149.1/1532 JTAG port that is always available any time the
FPGA is powered and regardless of the mode pin settings.
However, when the FPGA mode pins are set for JTAG mode
(M[2:0] = <1:0:1>), the FPGA waits to be configured via the
JTAG port after a power-on event or when PROG_B is
asserted. Selecting the JTAG mode simply disables the
other configuration modes. No other pins are required as
part of the configuration interface.
http://www.xilinx.com/support/answers/22255.htm
Figure 65 illustrates a JTAG-only configuration interface.
The JTAG interface is easily cascaded to any number of
FPGAs by connecting the TDO output of one device to the
TDI input of the next device in the chain. The TDO output of
the last device in the chain loops back to the port connector.
Design Note
If using software versions prior to ISE 9.1.01i, avoid
configuring the FPGA using JTAG if...
•
•
the mode pins are set for a Master mode
the attached Master mode PROM contains a valid
FPGA configuration bitstream.
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Spartan-3E FPGA Family: Functional Description
X-Ref Target - Figure 65
+1.2V
+1.2V
VCCINT
VCCINT
P
HSWAP
VCCO_0
VCCO_0
VCCO_2
HSWAP
VCCO_0
VCCO_0
VCCO_2
P
VCCO_2
VCCO_2
JTAG
Mode
JTAG
Mode
Spartan-3E
Spartan-3E
FPGA
‘1’
‘0’
‘1’
M2
M1
M0
‘1’
‘0’
‘1’
M2
M1
M0
FPGA
VCCAUX
+2.5V
VCCAUX
TDO
+2.5V
TDI
TDO
TDI
TMS
TCK
TMS
TCK
PROG_B
DONE
PROG_B
DONE
GND
GND
+2.5V
JTAG
TDI
TMS
TCK
TDO
TMS
TCK
DS312-2_56_082009
Figure 65: JTAG Configuration Mode
Voltage Compatibility
JTAG Device ID
The 2.5V V
supply powers the JTAG interface. All of
Each Spartan-3E FPGA array type has a 32-bit
CCAUX
the user I/Os are separately powered by their respective
VCCO_# supplies.
device-specific JTAG device identifier as shown in Table 67.
The lower 28 bits represent the device vendor (Xilinx) and
device identifer. The upper four bits, ignored by most tools,
represent the revision level of the silicon mounted on the
printed circuit board. Table 67 associates the revision code
with a specific stepping level.
When connecting the Spartan-3E JTAG port to a 3.3V
interface, the JTAG input pins must be current-limited to
10 mA or less using series resistors. Similarly, the TDO pin
is a CMOS output powered from +2.5V. The TDO output can
directly drive a 3.3V input but with reduced noise immunity.
See XAPP453: The 3.3V Configuration of Spartan-3
FPGAs for additional information.
JTAG User ID
The Spartan-3E JTAG interface also provides the option to
store a 32-bit User ID, loaded during configuration. The
User ID value is specified via the UserID configuration
bitstream option, shown in Table 69, page 108.
Table 67: Spartan-3E JTAG Device Identifiers
4-Bit Revision Code
28-Bit
Vendor/Device
Identifier
Spartan-3E
FPGA
Using JTAG Interface to Communicate to a
Configured FPGA Design
Step 0
Step 1
XC3S100E
XC3S250E
0x0
0x0
0x1
0x1
0x1C 10 093
0x1C 1A 093
After the FPGA is configured, using any of the available
modes, the JTAG interface offers a possible
communications channel to internal FPGA logic. The
BSCAN_SPARTAN3 design primitive provides two private
JTAG instructions to create an internal boundary scan
chain.
0x0
0x2
XC3S500E
XC3S1200E
XC3S1600E
0x4
0x2
0x2
0x1C 22 093
0x1C 2E 093
0x1C 3A 093
0x0
0x1
0x0
0x1
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Spartan-3E FPGA Family: Functional Description
The FPGA configuration sequence can also be initiated by
asserting PROG_B. Once released, the FPGA begins
clearing its internal configuration memory, and progresses
through the remainder of the configuration process.
Maximum Bitstream Size for Daisy-Chains
The maximum bitstream length supported by Spartan-3E
FPGAs in serial daisy-chains is 4,294,967,264 bits
(4 Gbits), roughly equivalent to a daisy-chain with 720
XC3S1600E FPGAs. This is a limit only for serial
daisy-chains where configuration data is passed via the
FPGA’s DOUT pin. There is no such limit for JTAG chains.
Configuration Sequence
For additional information including I/O behavior before and
during configuration, refer to the “Sequence of Events”
chapter in UG332.
The Spartan-3E configuration process is three-stage
process that begins after the FPGA powers on (a POR
event) or after the PROG_B input is asserted. Power-On
Reset (POR) occurs after the V
, V
, and the
CCINT CCAUX
V
Bank 2 supplies reach their respective input threshold
CCO
levels. After either a POR or PROG_B event, the
three-stage configuration process begins.
1. The FPGA clears (initializes) the internal configuration
memory.
2. Configuration data is loaded into the internal memory.
3. The user-application is activated by a start-up process.
Figure 66 is a generalized block diagram of the Spartan-3E
configuration logic, showing the interaction of different
device inputs and Bitstream Generator (BitGen) options. A
flow diagram for the configuration sequence of the Serial
and Parallel modes appears in Figure 66. Figure 67 shows
the Boundary-Scan or JTAG configuration sequence.
Initialization
Configuration automatically begins after power-on or after
asserting the FPGA PROG_B pin, unless delayed using the
FPGA’s INIT_B pin. The FPGA holds the open-drain INIT_B
signal Low while it clears its internal configuration memory.
Externally holding the INIT_B pin Low forces the
configuration sequencer to wait until INIT_B again goes
High.
The FPGA signals when the memory-clearing phase is
complete by releasing the open-drain INIT_B pin, allowing
the pin to go High via the external pull-up resistor to
VCCO_2.
Loading Configuration Data
After initialization, configuration data is written to the
FPGA’s internal memory. The FPGA holds the Global
Set/Reset (GSR) signal active throughout configuration,
holding all FPGA flip-flops in a reset state. The FPGA
signals when the entire configuration process completes by
releasing the DONE pin, allowing it to go High.
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Spartan-3E FPGA Family: Functional Description
X-Ref Target - Figure 66
DS312-2_57_102605
Figure 66: Generalized Spartan-3E FPGA Configuration Logic Block Diagram
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Spartan-3E FPGA Family: Functional Description
Set PROG_B Low
after Power-On
Power-On
VCCINT >1V
and VCCAUX > 2V
No
and VCCO Bank 2 > 1V
Yes
Yes
Clear configuration
PROG_B = Low
No
memory
No
INIT_ B = High?
Yes
M[2:0] and VS[2:0]
pins are sampled on
INIT_B rising edge
Sample mode pins
Load configuration
data frames
No
INIT_B goes Low.
Abort Start-Up
CRC
correct?
Yes
DONE pin goes High,
signaling end of
configuration
Start-Up
sequence
User mode
No
Yes
Reconfigure?
DS312-2_58_051706
Figure 66: General Configuration Process
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Spartan-3E FPGA Family: Functional Description
X-Ref Target - Figure 67
Set PROG_B Low
after Power-On
Power-On
VCCINT >1V
and VCCAUX > 2V
No
and VCCO Bank 2 > 1V
Load
JPROG
instruction
Yes
Clear
configuration
memory
Yes
PROG_B = Low
No
No
INIT_B = High?
Yes
Sample
mode pins
(JTAG port becomes
available)
Load CFG_IN
instruction
Load configuration
data frames
No
CRC
correct?
INIT_B goes Low.
Abort Start-Up
Yes
Synchronous
TAP reset
(Clock five 1's
on TMS)
Load JSTART
instruction
Start-Up
sequence
User mode
No
Yes
Reconfigure?
DS312-2_59_051706
Figure 67: Boundary-Scan Configuration Flow Diagram
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Spartan-3E FPGA Family: Functional Description
become user I/Os. Like all user-I/O pins, GTS controls when
the dual-purpose pins can drive out.
Start-Up
At the end of configuration, the FPGA automatically pulses
the Global Set/Reset (GSR) signal, placing all flip-flops in a
known state. After configuration completes, the FPGA
switches over to the user application loaded into the FPGA.
The sequence and timing of how the FPGA switches over is
programmable as is the clock source controlling the
sequence.
The relative timing of configuration events is programmed
via the Bitstream Generator (BitGen) options in the Xilinx
development software. For example, the GTS and GWE
events can be programmed to wait for all the DONE pins to
High on all the devices in a multiple-FPGA daisy-chain,
forcing the FPGAs to start synchronously. Similarly, the
start-up sequence can be paused at any stage, waiting for
selected DCMs to lock to their respective input clock
signals. See also Stabilizing DCM Clocks Before User
Mode.
The default start-up sequence appears in Figure 68, where
the Global Three-State signal (GTS) is released one clock
cycle after DONE goes High. This sequence allows the
DONE signal to enable or disable any external logic used
during configuration before the user application in the FPGA
starts driving output signals. One clock cycle later, the
Global Write Enable (GWE) signal is released. This allows
signals to propagate within the FPGA before any clocked
storage elements such as flip-flops and block ROM are
enabled.
By default, the start-up sequence is synchronized to CCLK.
Alternatively, the start-up sequence can be synchronized to
a user-specified clock from within the FPGA application
using the STARTUP_SPARTAN3E library primitive and by
setting the StartupClk bitstream generator option. The
FPGA application can optionally assert the GSR and GTS
signals via the STARTUP_SPARTAN3E primitive. For JTAG
configuration, the start-up sequence can be synchronized
to the TCK clock input.
X-Ref Target - Figure 68
Default Cycles
Start-Up Clock
Phase
0
1
2
3
4
5
6 7
DONE
GTS
GWE
Sync-to-DONE
Start-Up Clock
Phase
0
1
2
3
4
5
6 7
DONE High
DONE
GTS
GWE
DS312-2_60_022305
Figure 68: Default Start-Up Sequence
The function of the dual-purpose I/O pins, such as M[2:0],
VS[2:0], HSWAP, and A[23:0], also changes when the
DONE pin goes High. When DONE is High, these pins
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Spartan-3E FPGA Family: Functional Description
Readback
FPGA configuration data can be read back using either the
Slave Parallel or JTAG mode. This function is disabled if the
Bitstream Generator Security option is set to either Level1
or Level2.
Table 68: Readback Support in Spartan-3E FPGAs
Temperature Range
Speed Grade
Commercial
Industrial
-4
-4
-5
Block RAM Readback
All Spartan-3E FPGAs
Along with the configuration data, it is possible to read back
the contents of all registers and distributed RAM.
No
Yes
Yes
General Readback (registers, distributed RAM)
To synchronously control when register values are captured
for readback, use the CAPTURE_SPARTAN3 library
primitive, which applies for both Spartan-3 and Spartan-3E
FPGA families.
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
The Readback feature is available in most Spartan-3E
FPGA product options, as indicated in Table 68. The
Readback feature is not available in the XC3S1200E and
XC3S1600E FPGAs when using the -4 speed grade in the
Commercial temperature grade. Similarly, block RAM
Readback support is not available in the -4 speed grade,
Commercial temperature devices. If Readback is required in
an XC3S1200E or XC3S1600E FPGA, or if block RAM
Readback is required on any Spartan-3E FPGA, upgrade to
either the Industrial temperature grade version or the -5
speed grade.
No
The Xilinx iMPACT programming software uses the
Readback feature for its optional Verify and Readback
operations. The Xilinx ChipScope™ software presently
does not use Readback but may in future updates.
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Spartan-3E FPGA Family: Functional Description
Bitstream Generator (BitGen) Options
For additional information, refer to the “Configuration
Bitstream Generator (BitGen) Settings” chapter in UG332.
values are specified when creating the bitstream image with
the Bitstream Generator (BitGen) software.
Various Spartan-3E FPGA functions are controlled by
specific bits in the configuration bitstream image. These
Table 69 provides a list of all BitGen options for Spartan-3E
FPGAs.
Table 69: Spartan-3E FPGA Bitstream Generator (BitGen) Options
Pins/Function
Affected
Values
(default)
Option Name
Description
ConfigRate
CCLK,
Configuration
1, 3, 6,
Sets the approximate frequency, in MHz, of the internal oscillator using for Master
12, 25, 50 Serial, SPI, and BPI configuration modes. The internal oscillator powers up at its lowest
frequency, and the new setting is loaded as part of the configuration bitstream. The
software default value is 1 (~1.5 MHz) starting with ISE 8.1, Service Pack 1.
StartupClk
Configuration,
Startup
Cclk
Default. The CCLK signal (internally or externally generated) controls the startup
sequence when the FPGA transitions from configuration mode to the user mode. See
Start-Up.
UserClk A clock signal from within the FPGA application controls the startup sequence when the
FPGA transitions from configuration mode to the user mode. See Start-Up. The FPGA
application supplies the user clock on the CLK pin on the STARTUP_SPARTAN3E
primitive.
Jtag
The JTAG TCK input controls the startup sequence when the FPGA transitions from the
configuration mode to the user mode. See Start-Up.
UnusedPin
Unused I/O
Pins
Pulldown Default. All unused I/O pins and input-only pins have a pull-down resistor to GND.
Pullup
All unused I/O pins and input-only pins have a pull-up resistor to the VCCO_# supply
for its associated I/O bank.
Pullnone All unused I/O pins and input-only pins are left floating (Hi-Z, high-impedance,
three-state). Use external pull-up or pull-down resistors or logic to apply a valid signal
level.
DONE_cycle
GWE_cycle
DONE pin,
Configuration
Startup
1, 2, 3, 4, Selects the Configuration Startup phase that activates the FPGA’s DONE pin. See
5, 6
Start-Up.
All flip-flops,
LUTRAMs,and
SRL16 shift
registers, Block
RAM,
Configuration
Startup
1, 2, 3, 4, Selects the Configuration Startup phase that asserts the internal write-enable signal to
5, 6
all flip-flops, LUT RAMs and shift registers (SRL16). It also enables block RAM read and
write operations. See Start-Up.
Done
Waits for the DONE pin input to go High before asserting the internal write-enable signal
to all flip-flops, LUT RAMs and shift registers (SRL16). Block RAM read and write
operations are enabled at this time.
Keep
Retains the current GWE_cycle setting for partial reconfiguration applications.
GTS_cycle
All I/O pins,
Configuration
1, 2, 3, 4, Selects the Configuration Startup phase that releases the internal three-state control,
5, 6
holding all I/O buffers in high-impedance (Hi-Z). Output buffers actively drive, if so
configured, after this point. See Start-Up.
Done
Waits for the DONE pin input to go High before releasing the internal three-state control,
holding all I/O buffers in high-impedance (Hi-Z). Output buffers actively drive, if so
configured, after this point.
Keep
Retains the current GTS_cycle setting for partial reconfiguration applications.
The FPGA does not wait for selected DCMs to lock before completing configuration.
LCK_cycle
DonePin
DCMs,
Configuration
Startup
NoWait
0, 1, 2, 3, If one or more DCMs in the design have the STARTUP_WAIT attribute set to TRUE, the
4, 5, 6
FPGA waits for such DCMs to acquire their respective input clock and assert their
LOCKED output. This setting selects the Configuration Startup phase where the FPGA
waits for the DCMs to lock.
DONE pin
Pullup
Internally connects a pull-up resistor between DONE pin and VCCAUX. An external
330 Ω pull-up resistor to VCCAUX is still recommended.
Pullnone No internal pull-up resistor on DONE pin. An external 330 Ω pull-up resistor to VCCAUX
is required.
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Spartan-3E FPGA Family: Functional Description
Description
Table 69: Spartan-3E FPGA Bitstream Generator (BitGen) Options (Cont’d)
Pins/Function
Affected
Values
(default)
Option Name
DriveDone
DONE pin
No
When configuration completes, the DONE pin stops driving Low and relies on an
external 330 Ω pull-up resistor to VCCAUX for a valid logic High.
Yes
When configuration completes, the DONE pin actively drives High. When using this
option, an external pull-up resistor is no longer required. Only one device in an FPGA
daisy-chain should use this setting.
DonePipe
ProgPin
DONE pin
No
The input path from DONE pin input back to the Startup sequencer is not pipelined.
Yes
This option adds a pipeline register stage between the DONE pin input and the Startup
sequencer. Used for high-speed daisy-chain configurations when DONE cannot rise in
a single CCLK cycle. Releases GWE and GTS signals on the first rising edge of
StartupClk after the DONE pin input goes High.
PROG_B pin
Pullup
Internally connects a pull-up resistor or between PROG_B pin and VCCAUX. An external
4.7 kΩ pull-up resistor to VCCAUX is still recommended since the internal pull-up value
may be weaker (see Table 78).
Pullnone No internal pull-up resistor on PROG_B pin. An external 4.7 kΩ pull-up resistor to
VCCAUX is required.
TckPin
TdiPin
TdoPin
TmsPin
JTAG TCK pin
JTAG TDI pin
JTAG TDO pin
JTAG TMS pin
Pullup
Internally connects a pull-up resistor between JTAG TCK pin and VCCAUX.
Pulldown Internally connects a pull-down resistor between JTAG TCK pin and GND.
Pullnone No internal pull-up resistor on JTAG TCK pin.
Pullup
Internally connects a pull-up resistor between JTAG TDI pin and VCCAUX.
Pulldown Internally connects a pull-down resistor between JTAG TDI pin and GND.
Pullnone No internal pull-up resistor on JTAG TDI pin.
Pullup
Internally connects a pull-up resistor between JTAG TDO pin and VCCAUX.
Pulldown Internally connects a pull-down resistor between JTAG TDO pin and GND.
Pullnone No internal pull-up resistor on JTAG TDO pin.
Pullup
Internally connects a pull-up resistor between JTAG TMS pin and VCCAUX.
Pulldown Internally connects a pull-down resistor between JTAG TMS pin and GND.
Pullnone No internal pull-up resistor on JTAG TMS pin.
UserID
JTAG User ID User string The 32-bit JTAG User ID register value is loaded during configuration. The default value
register
is all ones, 0xFFFF_FFFFhexadecimal. To specify another value, enter an 8-character
hexadecimal value.
Security
JTAG,
SelectMAP,
Readback,
Partial
None
Readback and limited partial reconfiguration are available via the JTAG port or via the
SelectMAP interface, if the Persist option is set to Yes.
Level1
Readback function is disabled. Limited partial reconfiguration is still available via the
JTAG port or via the SelectMAP interface, if the Persist option is set to Yes.
reconfiguration
Level2
Readback function is disabled. Limited partial reconfiguration is disabled.
CRC
Configuration
Enable
Default. Enable CRC checking on the FPGA bitstream. If error detected, FPGA asserts
INIT_B Low and DONE pin stays Low.
Disable
No
Turn off CRC checking.
Persist
SelectMAP
interface pins,
BPI mode,
Slave mode,
Configuration
All BPI and Slave mode configuration pins are available as user-I/O after configuration.
Yes
This option is required for Readback and partial reconfiguration using the SelectMAP
interface. The SelectMAP interface pins (see Slave Parallel Mode) are reserved after
configuration and are not available as user-I/O.
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Spartan-3E FPGA Family: Functional Description
supply inputs for internal logic functions, V
and
CCINT
Powering Spartan-3E FPGAs
For additional information, refer to the “Powering Spartan-3
Generation FPGAs” chapter in UG331.
V
. Each of the four I/O banks has a separate V
CCAUX
CCO
supply input that powers the output buffers within the
associated I/O bank. All of the V connections to a
CCO
specific I/O bank must be connected and must connect to
the same voltage.
Voltage Supplies
Like Spartan-3 FPGAs, Spartan-3E FPGAs have multiple
voltage supply inputs, as shown in Table 70. There are two
Table 70: Spartan-3E Voltage Supplies
Supply Input
Description
Nominal Supply Voltage
VCCINT
Internal core supply voltage. Supplies all internal logic functions, such as CLBs, block
RAM, and multipliers. Input to Power-On Reset (POR) circuit.
1.2V
VCCAUX
VCCO_0
VCCO_1
Auxiliary supply voltage. Supplies Digital Clock Managers (DCMs), differential drivers,
dedicated configuration pins, JTAG interface. Input to Power-On Reset (POR) circuit.
2.5V
Supplies the output buffers in I/O Bank 0, the bank along the top edge of the FPGA.
Selectable, 3.3V, 2.5V, 1.8,
1.5V, or 1.2V
Supplies the output buffers in I/O Bank 1, the bank along the right edge of the FPGA. In Selectable, 3.3V, 2.5V, 1.8,
Byte-Wide Peripheral Interface (BPI) Parallel Flash Mode, connects to the same voltage
as the Flash PROM.
1.5V, or 1.2V
VCCO_2
VCCO_3
Supplies the output buffers in I/O Bank 2, the bank along the bottom edge of the FPGA. Selectable, 3.3V, 2.5V, 1.8,
Connects to the same voltage as the FPGA configuration source. Input to Power-On
Reset (POR) circuit.
1.5V, or 1.2V
Supplies the output buffers in I/O Bank 3, the bank along the left edge of the FPGA.
Selectable, 3.3V, 2.5V, 1.8,
1.5V, or 1.2V
In a 3.3V-only application, all four V
supplies connect to
CCO
3.3V. However, Spartan-3E FPGAs provide the ability to
bridge between different I/O voltages and standards by
applying different voltages to the V
inputs of different
CCO
banks. Refer to I/O Banking Rules for which I/O standards
can be intermixed within a single I/O bank.
Each I/O bank also has an separate, optional input voltage
reference supply, called V . If the I/O bank includes an I/O
REF
standard that requires a voltage reference such as HSTL or
SSTL, then all V
pins within the I/O bank must be
REF
connected to the same voltage.
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110
Spartan-3E FPGA Family: Functional Description
do not require Power-On Surge (POS) current to
successfully configure.
Voltage Regulators
Various power supply manufacturers offer complete power
solutions for Xilinx FPGAs including some with integrated
three-rail regulators specifically designed for Spartan-3 and
Spartan-3E FPGAs. The Xilinx Power Corner website
provides links to vendor solution guides and Xilinx power
estimation and analysis tools.
Surplus ICCINT if VCCINT Applied before VCCAUX
If the V
supply is applied before the V
supply,
CCINT
CCAUX
the FPGA might draw a surplus I
current in addition to
CCINT
the I
quiescent current levels specified in Table 79,
CCINT
page 119. The momentary additional I
surplus current
CCINT
might be a few hundred milliamperes under nominal
conditions, significantly less than the instantaneous current
consumed by the bypass capacitors at power-on. However,
the surplus current immediately disappears when the
Power Distribution System (PDS) Design
and Decoupling/Bypass Capacitors
Good power distribution system (PDS) design is important
for all FPGA designs, but especially so for high performance
applications, greater than 100 MHz. Proper design results
in better overall performance, lower clock and DCM jitter,
and a generally more robust system. Before designing the
printed circuit board (PCB) for the FPGA design, please
review XAPP623: Power Distribution System (PDS) Design:
Using Bypass/Decoupling Capacitors.
V
supply is applied, and, in response, the FPGA’s
CCAUX
I
quiescent current demand drops to the levels
CCINT
specified in Table 79. The FPGA does not use or require the
surplus current to successfully power-on and configure. If
applying V
before V
, ensure that the regulator
CCINT
CCAUX
does not have a foldback feature that could inadvertently
shut down in the presence of the surplus current.
Configuration Data Retention, Brown-Out
Power-On Behavior
The FPGA’s configuration data is stored in robust CMOS
configuration latches. The data in these latches is retained
even when the voltages drop to the minimum levels
necessary to preserve RAM contents, as specified in
Table 76.
For additional power-on behavior information, including I/O
behavior before and during configuration, refer to the
“Sequence of Events” chapter in UG332.
Spartan-3E FPGAs have a built-in Power-On Reset (POR)
circuit that monitors the three power rails required to
successfully configure the FPGA. At power-up, the POR
If, after configuration, the V
or V
supply drops
CCINT
CCAUX
below its data retention voltage, the current device
configuration must be cleared using one of the following
methods:
circuit holds the FPGA in a reset state until the V
,
CCINT
V
, and V
Bank 2 supplies reach their respective
CCAUX
CCO
input threshold levels (see Table 74 in Module 3). After all
three supplies reach their respective thresholds, the POR
reset is released and the FPGA begins its configuration
process.
•
Force the V
or V
supply voltage below the
CCINT
CCAUX
minimum Power On Reset (POR) voltage threshold
(Table 74).
•
Assert PROG_B Low.
Supply Sequencing
The POR circuit does not monitor the VCCO_2 supply after
configuration. Consequently, dropping the VCCO_2 voltage
does not reset the device by triggering a Power-On Reset
(POR) event.
Because the three FPGA supply inputs must be valid to
release the POR reset and can be supplied in any order,
there are no FPGA-specific voltage sequencing
requirements. Applying the FPGA’s V
supply before
CCAUX
the V
supply uses the least I
current.
CCINT
CCINT
No Internal Charge Pumps or Free-Running
Oscillators
Although the FPGA has no specific voltage sequence
requirements, be sure to consider any potential sequencing
requirement of the configuration device attached to the
FPGA, such as an SPI serial Flash PROM, a parallel NOR
Flash PROM, or a microcontroller. For example, Flash
PROMs have a minimum time requirement before the
PROM can be selected and this must be considered if the
3.3V supply is the last in the sequence. See Power-On
Precautions if 3.3V Supply is Last in Sequence for more
details.
Some system applications are sensitive to sources of
analog noise. Spartan-3E FPGA circuitry is fully static and
does not employ internal charge pumps.
The CCLK configuration clock is active during the FPGA
configuration process. After configuration completes, the
CCLK oscillator is automatically disabled unless the
Bitstream Generator (BitGen) option Persist=Yes.
When all three supplies are valid, the minimum current
required to power-on the FPGA equals the worst-case
quiescent current, specified in Table 79. Spartan-3E FPGAs
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111
Spartan-3E FPGA Family: Functional Description
Production Stepping
The Spartan-3E FPGA family uses production stepping to
indicate improved capabilities or enhanced features.
Designs operating on the Stepping 0 devices perform
similarly on a Stepping 1 device.
Stepping 1 is, by definition, a functional superset of
Stepping 0. Furthermore, configuration bitstreams
generated for Stepping 0 are compatible with Stepping 1.
Differences Between Steppings
Table 71 summarizes the feature and performance
differences between Stepping 0 devices and Stepping 1
devices.
Table 71: Differences between Spartan-3E Production Stepping Levels
Stepping 0
Stepping 1
Production status
Production starting
March 2006
Production from 2005 to 2007
Speed grade and operating conditions
JTAG ID code
-4C only
-4C, -4I, -5C
Different revision fields. See Table 67.
DCM DLL maximum input frequency
90 MHz
(200 MHz for XC3S1200E)
240 MHz (-4 speed grade)
275 MHz (-5 speed grade)
DCM DFS output frequency range(s)
Split ranges at 5 – 90 MHz and
220 – 307 MHz
(single range 5 – 307 MHz for XC3S1200E)
Continuous range:
5 – 311 MHz (-4)
5 – 333 MHz (-5)
Supports multi-FPGA daisy-chain configurations from
SPI Flash
No, single FPGA only
No(1)
Yes
JTAG configuration supported when FPGA in BPI
mode with a valid image in the attached parallel NOR
Flash PROM
Yes
JTAG EXTEST, INTEST, SAMPLE support
Yes: XC3S100E, XC3S250E, XC3S500E
No(2): XC3S1200E, XC3S1600E
Yes
All Devices
Power sequencing when using HSWAP Pull-Up
PCI compliance
Requires VCCINT before VCCAUX
No
Any sequence
Yes
Notes:
1. Workarounds exist. See Stepping 0 Limitations when Reprogramming via JTAG if FPGA Set for BPI Configuration.
2. JTAG BYPASS and JTAG configuration are supported
Ordering a Later Stepping
Software Version Requirements
-5C and -4I devices, and -4C devices (with date codes 0901
(2009) and later) always support the Stepping 1 feature set
independent of the stepping code. Optionally, to order only
Stepping 1 for the -4C devices, append an “S1” suffix to the
standard ordering code, where ‘1’ is the stepping number,
as indicated in Table 72.
Production Spartan-3E applications must be processed
using the Xilinx ISE 8.1i, Service Pack 3 or later
development software, using the v1.21 or later speed files.
The ISE 8.1i software implements critical bitstream
generator updates.
For additional information on Spartan-3E development
software and known issues, see the following Answer
Record:
Table 72: Spartan-3E Optional Stepping Ordering
Stepping
Number
Suffix Code
Status
•
Xilinx Answer #22253
http://www.xilinx.com/support/answers/22253.htm
0
1
None
S1
Production
Production
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112
Spartan-3E FPGA Family: Functional Description
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revision
03/01/2005
03/21/2005
11/23/2005
Initial Xilinx release.
1.1
Updated Figure 45. Modified title on Table 39 and Table 45.
2.0
Updated values of On-Chip Differential Termination resistors. Updated Table 7. Updated configuration
bitstream sizes for XC3S250E through XC3S1600E in Table 45, Table 51, Table 57, and Table 60.
Added DLL Performance Differences Between Steppings. Added Stepping 0 Limitations when
Reprogramming via JTAG if FPGA Set for BPI Configuration. Added Stepping 0 limitations when
Daisy-Chaining in SPI configuration mode. Added Multiplier/Block RAM Interaction section. Updated
Digital Clock Managers (DCMs) section, especially Phase Shifter (PS) portion. Corrected and
enhanced the clock infrastructure diagram in Figure 45 and Table 41. Added CCLK Design
Considerations section. Added Design Considerations for the HSWAP, M[2:0], and VS[2:0] Pins
section. Added Spansion, Winbond, and Macronix to list of SPI Flash vendors in Table 53 and Table 56.
Clarified that SPI mode configuration supports Atmel ‘C’- and ‘D’-series DataFlash. Updated the
Programming Support section for SPI Flash PROMs. Added Power-On Precautions if PROM Supply is
Last in Sequence, Compatible Flash Families, and BPI Mode Interaction with Right and Bottom Edge
Global Clock Inputs sections to BPI configuration mode topic. Updated and amplified Powering
Spartan-3E FPGAs section. Added Production Stepping section.
03/22/2006
3.0
Upgraded data sheet status to Preliminary. Updated Input Delay Functions and Figure 6. Added
clarification that Input-only pins also have Pull-Up and Pull-Down Resistors. Added design note about
address setup and hold requirements to Block RAM. Added warning message about software
differences between ISE 8.1i, Service Pack 3 and earlier software to FIXED Phase Shift Mode and
VARIABLE Phase Shift Mode. Added message about using GCLK1 in DLL Clock Input Connections
and Clock Inputs. Updated Figure 45. Added additional information on HSWAP behavior to Pin
Behavior During Configuration. Highlighted which pins have configuration pull-up resistors unaffected
by HSWAP in Table 46. Updated bitstream image sizes for the XC3S1200E and XC3S1600E in
Table 45, Table 51, Table 57, and Table 60. Clarified that ‘B’-series Atmel DataFlash SPI PROMs can
be used in Commercial temperature range applications in Table 53 and Figure 54. Updated Figure 56.
Updated Dynamically Loading Multiple Configuration Images Using MultiBoot Option section. Added
design note about BPI daisy-chaining software support to BPI Daisy-Chaining section. Updated JTAG
revision codes in Table 67. Added No Internal Charge Pumps or Free-Running Oscillators. Updated
information on production stepping differences in Table 71. Updated Software Version Requirements.
04/10/2006
05/19/2006
3.1
3.2
Updated JTAG User ID information. Clarified Note 1, Figure 5. Clarified that Figure 45 shows electrical
connectivity and corrected left- and right-edge DCM coordinates. Updated Table 30, Table 31, and
Table 32 to show the specific clock line driven by the associated BUFGMUX primitive. Corrected the
coordinate locations for the associated BUFGMUX primitives in Table 31 and Table 32. Updated
Table 41 to show that the I0-input is the preferred connection to a BUFGMUX.
Made further clarifying changes to Figure 46, showing both direct inputs to BUFGMUX primitives and
to DCMs. Added Atmel AT45DBxxxD-series DataFlash serial PROMs to Table 53. Added details that
intermediate FPGAs in a BPI-mode, multi-FPGA configuration daisy-chain must be from either the
Spartan-3E or the Virtex-5 FPGA families (see BPI Daisy-Chaining). Added Using JTAG Interface to
Communicate to a Configured FPGA Design. Minor updates to Figure 66 and Figure 67. Clarified
which Spartan-3E FPGA product options support the Readback feature, shown in Table 68.
05/30/2006
10/02/2006
3.2.1
3.3
Corrected various typos and incorrect links.
Clarified that the block RAM Readback feature is available either on the -5 speed grade or the Industrial
temperature range.
11/09/2006
3.4
Updated the description of the Input Delay Functions. The ODDR2 flip-flop with C0 or C1 Alignment is
no longer supported. Updated Figure 5. Updated Table 6 for improved PCI input voltage tolerance.
Replaced missing text in Clock Buffers/Multiplexers. Updated SPI Flash devices in Table 53. Updated
parallel NOR Flash devices in Table 61. Direct, SPI Flash in-system Programming Support was added
beginning with ISE 8.1i iMPACT software for STMicro and Atmel SPI PROMs. Updated Table 71 and
Table 72 as Stepping 1 is in full production. Freshened various hyper links. Promoted Module 2 to
Production status.
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Spartan-3E FPGA Family: Functional Description
Revision
Date
Version
03/16/2007
3.5
Added information about new Spartan-3 Generation user guides (Design Documentation Available).
Added cross-references to UG331: Spartan-3 Generation FPGA User Guide and to UG332: Spartan-3
Generation Configuration User Guide. Added note about possible JTAG configuration issues when the
FPGA mode pins are set for Master mode and using software prior to ISE 9.1.01i (JTAG Mode).
Removed a few lingering references to “weak” pull-up resistors, including in Figure 12. Removed
vestigial references regarding the LDC[2:0] and HDC pins during Slave Parallel Mode configuration.
These pins are not used in this configuration mode.
05/29/2007
04/18/2008
08/26/2009
3.6
3.7
3.8
Added information about HSWAP and PCI differences between steppings to Table 71. Removed
“Performance Differences between Global Buffers” to match improved specs in Module 3. Updated
PROG_B pulse width descriptions to match specification in Module 3.
Corrected Figure 6 to show six taps and updated associated text. Added note for recommended pull-up
on DONE in Table 55 and elsewhere. Added a caution regarding Persist of pins A20-A23. Updated
Stepping description in Table 71 to note that only Stepping 1 is in production today. Updated links.
Added a frequency limitation to Equation 6. Added a new Equation 7 with a frequency limitation. Added
a Spread Spectrum, page 57 paragraph. Added Table 42, page 61. Updated a Flash vendor name in
Table 61, page 89. Removed the < symbol from the flash read access times in Table 62, page 89.
Revised the first paragraph in Configuration Sequence, page 102. Revised the first paragraph in
Power-On Behavior, page 111. Revised the second paragraph in Production Stepping, page 112.
Revised the first paragraph in Ordering a Later Stepping, page 112.
10/29/2012
07/19/2013
4.0
4.1
Added Notice of Disclaimer. This product is not recommended for new designs.
Updated the design note section in VARIABLE Phase Shift Mode. Added the VQ100 to the Quadrant
Clock Routing section.
Removed banner. This product IS recommended for new designs.
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED
WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE
SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
CRITICAL APPLICATIONS DISCLAIMER
XILINX PRODUCTS (INCLUDING HARDWARE, SOFTWARE AND/OR IP CORES) ARE NOT DESIGNED OR INTENDED TO BE
FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS IN LIFE-SUPPORT OR
SAFETY DEVICES OR SYSTEMS, CLASS III MEDICAL DEVICES, NUCLEAR FACILITIES, APPLICATIONS RELATED TO THE
DEPLOYMENT OF AIRBAGS, OR ANY OTHER APPLICATIONS THAT COULD LEAD TO DEATH, PERSONAL INJURY OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE (INDIVIDUALLY AND COLLECTIVELY, “CRITICAL APPLICATIONS”). FURTHERMORE,
XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN ANY APPLICATIONS THAT AFFECT CONTROL OF A
VEHICLE OR AIRCRAFT, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF
SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE
OPERATOR. CUSTOMER AGREES, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE XILINX
PRODUCTS, TO THOROUGHLY TEST THE SAME FOR SAFETY PURPOSES. TO THE MAXIMUM EXTENT PERMITTED BY
APPLICABLE LAW, CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN CRITICAL
APPLICATIONS.
AUTOMOTIVE APPLICATIONS DISCLAIMER
XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING
FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A
VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN
THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III)
USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY
USE OF XILINX PRODUCTS IN SUCH APPLICATIONS.
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156
Spartan-3E FPGA Family:
DC and Switching Characteristics
DS312 (v4.1) July 19, 2013
Product Specification
DC Electrical Characteristics
In this section, specifications may be designated as
Advance, Preliminary, or Production. These terms are
defined as follows:
All parameter limits are representative of worst-case supply
voltage and junction temperature conditions. Unless
otherwise noted, the published parameter values apply
to all Spartan®-3E devices. AC and DC characteristics
are specified using the same numbers for both
commercial and industrial grades.
Advance: Initial estimates are based on simulation, early
characterization, and/or extrapolation from the
characteristics of other families. Values are subject to
change. Use as estimates, not for production.
Absolute Maximum Ratings
Preliminary: Based on characterization. Further changes
Stresses beyond those listed under Table 73, Absolute
Maximum Ratings may cause permanent damage to the
device. These are stress ratings only; functional operation
of the device at these or any other conditions beyond those
listed under the Recommended Operating Conditions is not
implied. Exposure to absolute maximum conditions for
extended periods of time adversely affects device reliability.
are not expected.
Production: These specifications are approved once the
silicon has been characterized over numerous production
lots. Parameter values are considered stable with no future
changes expected.
Table 73: Absolute Maximum Ratings
Symbol
VCCINT
VCCAUX
VCCO
Description
Internal supply voltage
Conditions
Min
–0.5
–0.5
–0.5
–0.5
–0.95
–0.85
–0.5
–
Max
1.32
Units
V
Auxiliary supply voltage
Output driver supply voltage
Input reference voltage
3.00
V
3.75
VCCO +0.5(1)
V
VREF
V
(1,2,3,4)
VIN
Voltage applied to all User I/O pins and
Dual-Purpose pins
Driver in a
Commercial
Industrial
4.4
V
high-impedance
state
4.3
V
Voltage applied to all Dedicated pins
Input clamp current per I/O pin
Electrostatic Discharge Voltage
All temp. ranges
V
CCAUX+0.5(3)
V
IIK
–0.5 V < VIN < (VCCO + 0.5 V)
Human body model
100
mA
V
VESD
–
2000
500
Charged device model
Machine model
–
V
–
200
V
TJ
Junction temperature
Storage temperature
–
125
°C
°C
TSTG
–65
150
Notes:
1. Each of the User I/O and Dual-Purpose pins is associated with one of the four banks’ V
rails. Keeping V within 500 mV of the
CCO
IN
associated V
rails or ground rail ensures that the internal diode junctions do not turn on. Table 77 specifies the V
range used to
CCO
CCO
evaluate the maximum V voltage.
IN
2. Input voltages outside the -0.5V to V
+ 0.5V (or V
+ 0.5V) voltage range are require the I input diode clamp diode rating is met
CCAUX IK
CCO
and no more than 100 pins exceed the range simultaneously. Prolonged exposure to such current may compromise device reliability. A
sustained current of 10 mA will not compromise device reliability. See XAPP459: Eliminating I/O Coupling Effects when Interfacing
Large-Swing Single-Ended Signals to User I/O Pins on Spartan-3 Families for more details.
3. All Dedicated pins (PROG_B, DONE, TCK, TDI, TDO, and TMS) draw power from the V
rail (2.5V). Meeting the V max limit ensures
CCAUX
IN
that the internal diode junctions that exist between each of these pins and the V
rail do not turn on. Table 77 specifies the V
CCAUX
CCAUX
range used to evaluate the maximum V voltage. As long as the V max specification is met, oxide stress is not possible.
IN
IN
4. See XAPP459: Eliminating I/O Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins on Spartan-3
Families.
5. For soldering guidelines, see UG112: Device Packaging and Thermal Characteristics and XAPP427: Implementation and Solder Reflow
Guidelines for Pb-Free Packages.
© Copyright 2005–2013 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, Artix, Kintex, Zynq, Vivado, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
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Product Specification
115
Spartan-3E FPGA Family: DC and Switching Characteristics
Power Supply Specifications
Table 74: Supply Voltage Thresholds for Power-On Reset
Symbol
VCCINTT
VCCAUXT
VCCO2T
Description
Threshold for the VCCINT supply
Min
0.4
0.8
0.4
Max
1.0
Units
V
V
V
Threshold for the VCCAUX supply
2.0
Threshold for the VCCO Bank 2 supply
1.0
Notes:
1.
V
, V
, and V
supplies to the FPGA can be applied in any order. However, the FPGA’s configuration source (Platform Flash,
CCO
CCINT CCAUX
SPI Flash, parallel NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration
source. In Step 0 devices using the HSWAP internal pull-up, V must be applied before V
.
CCAUX
CCINT
2. To ensure successful power-on, V
no dips at any point.
, V
Bank 2, and V
supplies must rise through their respective threshold-voltage ranges with
CCAUX
CCINT CCO
Table 75: Supply Voltage Ramp Rate
Symbol
Description
Min
0.2
0.2
0.2
Max
50
Units
ms
VCCINTR
VCCAUXR
VCCO2R
Ramp rate from GND to valid VCCINT supply level
Ramp rate from GND to valid VCCAUX supply level
Ramp rate from GND to valid VCCO Bank 2 supply level
50
ms
50
ms
Notes:
1.
V
, V
, and V
supplies to the FPGA can be applied in any order. However, the FPGA’s configuration source (Platform Flash,
CCO
CCINT CCAUX
SPI Flash, parallel NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration
source. In Step 0 devices using the HSWAP internal pull-up, V must be applied before V
.
CCAUX
CCINT
2. To ensure successful power-on, V
no dips at any point.
, V
Bank 2, and V
supplies must rise through their respective threshold-voltage ranges with
CCAUX
CCINT CCO
Table 76: Supply Voltage Levels Necessary for Preserving RAM Contents
Symbol
VDRINT
VDRAUX
Description
VCCINT level required to retain RAM data
VCCAUX level required to retain RAM data
Min
1.0
2.0
Units
V
V
Notes:
1. RAM contents include configuration data.
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Spartan-3E FPGA Family: DC and Switching Characteristics
General Recommended Operating Conditions
Table 77: General Recommended Operating Conditions
Symbol
Description
Commercial
Min
0
Nominal
Max
85
Units
°C
°C
V
TJ
Junction temperature
–
Industrial
–40
1.140
1.100
2.375
–0.5
–0.5
–0.5
–
–
100
VCCINT
Internal supply voltage
1.200
1.260
(1)
VCCO
Output driver supply voltage
Auxiliary supply voltage
-
3.465
V
VCCAUX
2.500
2.625
V
(2,3)
VIN
Input voltage extremes to avoid
I/O, Input-only, and
IP or IO_#
IO_Lxxy_#(5)
–
–
–
–
VCCO + 0.5
VCCO + 0.5
VCCAUX + 0.5
500
V
turning on I/O protection diodes Dual-Purpose pins (4)
V
Dedicated pins(6)
V
TIN
Notes:
1. This V
Input signal transition time(7)
ns
range spans the lowest and highest operating voltages for all supported I/O standards. Table 80 lists the recommended V
CCO
CCO
range specific to each of the single-ended I/O standards, and Table 82 lists that specific to the differential standards.
2. Input voltages outside the recommended range require the I input clamp diode rating is met and no more than 100 pins exceed the range
IK
simultaneously. Refer to Table 73.
3. See XAPP459: Eliminating I/O Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins on Spartan-3 Families.
4. Each of the User I/O and Dual-Purpose pins is associated with one of the four banks’ V
rails. Meeting the V limit ensures that the
CCO
IN
internal diode junctions that exist between these pins and their associated V
is provided in Table 73.
and GND rails do not turn on. The absolute maximum rating
CCO
5. For single-ended signals that are placed on a differential-capable I/O, V of –0.2V to –0.5V is supported but can cause increased leakage
IN
between the two pins. See Parasitic Leakage in UG331, Spartan-3 Generation FPGA User Guide.
6. All Dedicated pins (PROG_B, DONE, TCK, TDI, TDO, and TMS) draw power from the V
rail (2.5V). Meeting the V max limit ensures
CCAUX
IN
that the internal diode junctions that exist between each of these pins and the V
and GND rails do not turn on.
CCAUX
7. Measured between 10% and 90% V
. Follow Signal Integrity recommendations.
CCO
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117
Spartan-3E FPGA Family: DC and Switching Characteristics
General DC Characteristics for I/O Pins
Table 78: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins
Symbol
Description
Test Conditions
Min
Typ
Max
Units
(3)
IL
Leakage current at User I/O, Input-only,
Dual-Purpose, and Dedicated pins
Driver is in a high-impedance state, VIN
0V or VCCO max, sample-tested
=
–10
–
+10
μA
(2)
IRPU
Current through pull-up resistor at User I/O,
Dual-Purpose, Input-only, and Dedicated
pins
V
IN = 0V, VCCO = 3.3V
–0.36
–0.22
–0.10
–0.06
–0.04
2.4
–
–
–
–
–
–
–
–
–
–
–
–1.24
–0.80
–0.42
–0.27
–0.22
10.8
mA
mA
mA
mA
mA
kΩ
kΩ
kΩ
kΩ
kΩ
mA
VIN = 0V, VCCO = 2.5V
VIN = 0V, VCCO = 1.8V
VIN = 0V, VCCO = 1.5V
VIN = 0V, VCCO = 1.2V
(2)
RPU
Equivalent pull-up resistor value at User
I/O, Dual-Purpose, Input-only, and
Dedicated pins (based on IRPU per Note 2)
VIN = 0V, VCCO = 3.0V to 3.465V
VIN = 0V, VCCO = 2.3V to 2.7V
2.7
11.8
V
IN = 0V, VCCO = 1.7V to 1.9V
IN = 0V, VCCO =1.4V to 1.6V
VIN = 0V, VCCO = 1.14V to 1.26V
IN = VCCO
4.3
20.2
V
5.0
25.9
5.5
32.0
(2)
IRPD
Current through pull-down resistor at User
I/O, Dual-Purpose, Input-only, and
Dedicated pins
V
0.10
0.75
(2)
RPD
Equivalent pull-down resistor value at User
I/O, Dual-Purpose, Input-only, and
Dedicated pins (based on IRPD per Note 2)
V
IN = VCCO = 3.0V to 3.465V
IN = VCCO = 2.3V to 2.7V
VIN = VCCO = 1.7V to 1.9V
IN = VCCO = 1.4V to 1.6V
4.0
3.0
2.3
1.8
1.5
–10
–
–
–
34.5
27.0
19.0
16.0
12.6
+10
10
kΩ
kΩ
kΩ
kΩ
kΩ
μA
pF
Ω
V
–
V
–
VIN = VCCO = 1.14V to 1.26V
–
IREF
CIN
VREF current per pin
Input capacitance
All VCCO levels
–
–
–
RDT
Resistance of optional differential
termination circuit within a differential I/O
pair. Not available on Input-only pairs.
VOCM Min ≤ VICM ≤ VOCM Max
OD Min ≤ VID ≤ VOD Max
VCCO = 2.5V
–
120
–
V
Notes:
1. The numbers in this table are based on the conditions set forth in Table 77.
2. This parameter is based on characterization. The pull-up resistance R = V
/ I
. The pull-down resistance R = V / I
.
PU
CCO RPU
PD
IN RPD
3. For single-ended signals that are placed on a differential-capable I/O, V of –0.2V to –0.5V is supported but can cause increased leakage
IN
between the two pins. See Parasitic Leakage in UG331, Spartan-3 Generation FPGA User Guide.
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118
Spartan-3E FPGA Family: DC and Switching Characteristics
Quiescent Current Requirements
Table 79: Quiescent Supply Current Characteristics
Commercial
Maximum(1)
Industrial
Symbol
Description
Device
Typical
Units
Maximum(1)
ICCINTQ
Quiescent VCCINT supply current
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
8
27
78
36
104
145
324
457
1.5
1.5
1.5
2.5
2.5
13
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
15
25
50
65
0.8
0.8
0.8
1.5
1.5
8
106
259
366
1.0
1.0
1.0
2.0
2.0
12
ICCOQ
Quiescent VCCO supply current
ICCAUXQ Quiescent VCCAUX supply current
12
18
35
45
22
26
31
34
52
59
76
86
Notes:
1. The maximum numbers in this table indicate the minimum current each power rail requires in order for the FPGA to power-on successfully.
2. The numbers in this table are based on the conditions set forth in Table 77.
3. Quiescent supply current is measured with all I/O drivers in a high-impedance state and with all pull-up/pull-down resistors at the I/O pads
disabled. Typical values are characterized using typical devices at room temperature (T of 25°C at V
= 1.2 V, V
= 3.3V, and V
J
CCINT
CCO CCAUX
= 2.5V). The maximum limits are tested for each device at the respective maximum specified junction temperature and at maximum voltage
limits with V = 1.26V, V = 3.465V, and V = 2.625V. The FPGA is programmed with a “blank” configuration data file (i.e., a
CCINT
CCO
CCAUX
design with no functional elements instantiated). For conditions other than those described above, (e.g., a design including functional
elements), measured quiescent current levels may be different than the values in the table. For more accurate estimates for a specific design,
use the Xilinx® XPower tools.
4. There are two recommended ways to estimate the total power consumption (quiescent plus dynamic) for a specific design: a) The
Spartan-3E XPower Estimator provides quick, approximate, typical estimates, and does not require a netlist of the design. b) XPower
Analyzer uses a netlist as input to provide maximum estimates as well as more accurate typical estimates.
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119
Spartan-3E FPGA Family: DC and Switching Characteristics
Single-Ended I/O Standards
Table 80: Recommended Operating Conditions for User I/Os Using Single-Ended Standards
(3)
V
CCO for Drivers(2)
VREF
VIL
Max (V)
0.8
VIH
IOSTANDARD
Attribute
Min (V)
3.0
Nom (V)
3.3
Max (V)
Min (V)
Nom (V)
Max (V)
Min (V)
2.0
LVTTL
LVCMOS33
3.465
3.465
2.7
(4)
3.0
3.3
0.8
2.0
LVCMOS25(4,5)
LVCMOS18
LVCMOS15
LVCMOS12
2.3
2.5
0.7
1.7
1.65
1.4
1.8
1.95
1.6
0.4
0.8
VREF is not used for
these I/O standards
1.5
0.4
0.8
1.1
1.2
1.3
0.4
0.7
(6)
PCI33_3
3.0
3.3
3.465
3.465
1.9
0.3 • VCCO
0.3 • VCCO
VREF - 0.1
0.5 • VCCO
0.5 • VCCO
VREF + 0.1
VREF + 0.1
VREF + 0.125
VREF + 0.125
(6)
PCI66_3
3.0
3.3
HSTL_I_18
HSTL_III_18
SSTL18_I
SSTL2_I
1.7
1.8
0.8
-
0.9
1.1
1.1
-
1.7
1.8
1.9
VREF - 0.1
1.7
1.8
1.9
0.833
1.15
0.900
1.25
0.969
1.35
V
V
REF - 0.125
REF - 0.125
2.3
2.5
2.7
Notes:
1. Descriptions of the symbols used in this table are as follows:
V
V
V
V
– the supply voltage for output drivers
CCO
REF
IL
– the reference voltage for setting the input switching threshold
– the input voltage that indicates a Low logic level
– the input voltage that indicates a High logic level
IH
2. The V
rails supply only output drivers, not input circuits.
CCO
3. For device operation, the maximum signal voltage (V max) may be as high as V max. See Table 73.
IH
IN
4. There is approximately 100 mV of hysteresis on inputs using LVCMOS33 and LVCMOS25 I/O standards.
5. All Dedicated pins (PROG_B, DONE, TCK, TDI, TDO, and TMS) use the LVCMOS25 standard and draw power from the V
rail (2.5V).
CCAUX
The Dual-Purpose configuration pins use the LVCMOS standard before the User mode. When using these pins as part of a standard 2.5V
configuration interface, apply 2.5V to the V lines of Banks 0, 1, and 2 at power-on as well as throughout configuration.
CCO
6. For information on PCI IP solutions, see www.xilinx.com/pci. The PCIX IOSTANDARD is available and has equivalent characteristics but no
PCI-X IP is supported.
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120
Spartan-3E FPGA Family: DC and Switching Characteristics
Table 81: DC Characteristics of User I/Os Using
Single-Ended Standards (Cont’d)
Table 81: DC Characteristics of User I/Os Using
Single-Ended Standards
Test
Logic Level
Test
Logic Level
Conditions
Characteristics
Conditions
Characteristics
IOSTANDARD
Attribute
IOSTANDARD
Attribute
IOL
IOH
VOL
VOH
Min (V)
IOL
IOH
VOL
VOH
Min (V)
(mA) (mA)
Max (V)
(mA) (mA)
Max (V)
LVTTL(3)
2
4
6
8
2
4
–2
–4
0.4
2.4
SSTL2_I
Notes:
8.1
–8.1 VTT – 0.61
VTT + 0.61
1. The numbers in this table are based on the conditions set forth in
Table 77 and Table 80.
2. Descriptions of the symbols used in this table are as follows:
6
–6
8
–8
I
I
V
V
V
V
– the output current condition under which VOL is tested
– the output current condition under which VOH is tested
OL
OH
12
16
2
12
16
2
–12
–16
–2
– the output voltage that indicates a Low logic level
– the output voltage that indicates a High logic level
OL
OH
LVCMOS33(3)
0.4
VCCO – 0.4
– the supply voltage for output drivers
CCO
– the voltage applied to a resistor termination
TT
4
4
–4
3. For the LVCMOS and LVTTL standards: the same V and V
OL
OH
limits apply for both the Fast and Slow slew attributes.
6
6
–6
4. Tested according to the relevant PCI specifications. For
information on PCI IP solutions, see www.xilinx.com/pci. The
PCIX IOSTANDARD is available and has equivalent
characteristics but no PCI-X IP is supported.
8
8
–8
12
16
2
12
16
2
–12
–16
–2
LVCMOS25(3)
0.4
0.4
VCCO – 0.4
4
4
–4
6
6
–6
8
8
–8
12
2
12
2
–12
–2
LVCMOS18(3)
LVCMOS15(3)
VCCO – 0.4
4
4
–4
6
6
–6
8
8
–8
2
2
–2
0.4
0.4
VCCO – 0.4
4
4
–4
6
6
–6
LVCMOS12(3)
PCI33_3(4)
PCI66_3(4)
HSTL_I_18
HSTL_III_18
SSTL18_I
2
2
–2
VCCO – 0.4
90% VCCO
90% VCCO
VCCO – 0.4
1.5
1.5
8
–0.5 10% VCCO
–0.5 10% VCCO
–8
–8
0.4
0.4
24
6.7
VCCO – 0.4
–6.7
VTT – 0.475 VTT + 0.475
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121
Spartan-3E FPGA Family: DC and Switching Characteristics
Differential I/O Standards
X-Ref Target - Figure 69
VINP
Differential
I/O Pair Pins
P
N
Internal
Logic
VINN
VINN
VID
50%
VINP
VICM
GND level
VINP + VINN
V
ICM = Input common mode voltage =
2
V
VINP - VINN
ID = Differential input voltage =
DS099-3_01_012304
Figure 69: Differential Input Voltages
Table 82: Recommended Operating Conditions for User I/Os Using Differential Signal Standards
VCCO for Drivers(1)
VID
VICM
IOSTANDARD
Attribute
Min (V)
2.375
2.375
2.375
Nom (V)
2.50
Max (V)
Min (mV) Nom (mV) Max (mV)
Min (V)
0.30
0.30
0.30
0.5
Nom (V)
Max (V)
2.20
2.20
2.2
LVDS_25
2.625
2.625
2.625
100
100
200
100
100
100
100
100
100
350
600
1.25
BLVDS_25
2.50
350
600
1.25
MINI_LVDS_25
LVPECL_25(2)
RSDS_25
2.50
-
600
-
Inputs Only
2.50
800
1000
1.2
2.0
2.375
1.7
2.625
1.9
200
-
-
-
-
-
0.3
1.20
1.4
DIFF_HSTL_I_18
DIFF_HSTL_III_18
DIFF_SSTL18_I
DIFF_SSTL2_I
1.8
-
-
-
-
0.8
-
-
-
-
1.1
1.7
1.8
1.9
0.8
1.1
1.7
1.8
1.9
0.7
1.1
2.3
2.5
2.7
1.0
1.5
Notes:
1. The V
rails supply only differential output drivers, not input circuits.
CCO
2.
V
inputs are not used for any of the differential I/O standards.
REF
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122
Spartan-3E FPGA Family: DC and Switching Characteristics
X-Ref Target - Figure 70
VOUTP
Differential
I/O Pair Pins
P
N
Internal
Logic
VOUTN
VOH
VOUTN
VOD
50%
VOUTP
VOL
VOCM
GND level
VOUTP + VOUTN
V
OCM = Output common mode voltage =
2
VOUTP - VOUTN
= Output voltage indicating a High logic level
= Output voltage indicating a Low logic level
V
OD = Output differential voltage =
VOH
VOL
DS312-3_03_021505
Figure 70: Differential Output Voltages
Table 83: DC Characteristics of User I/Os Using Differential Signal Standards
VOD
ΔVOD
Min Max
(mV) (mV)
VOCM
ΔVOCM
VOH
VOL
IOSTANDARD
Attribute
Min
(mV)
Typ
(mV)
Max
(mV)
Min
(V)
Typ
(V)
Max
(V)
Min
Max
Min
(V)
Max
(V)
(mV) (mV)
LVDS_25
250
250
300
100
–
350
350
–
450
450
600
400
–
–
–
–
–
–
–
–
–
–
–
1.125
–
1.20
–
1.375
–
–
–
–
–
–
–
–
–
–
–
–
–
BLVDS_25
–
1.0
1.1
–
–
1.4
1.4
–
–
MINI_LVDS_25
RSDS_25
50
–
50
–
–
–
–
–
–
–
DIFF_HSTL_I_18
DIFF_HSTL_III_18
DIFF_SSTL18_I
DIFF_SSTL2_I
–
–
–
–
VCCO – 0.4
VCCO – 0.4
0.4
0.4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
VTT + 0.475 VTT – 0.475
VTT + 0.61 VTT – 0.61
–
–
–
–
–
–
–
–
Notes:
1. The numbers in this table are based on the conditions set forth in Table 77 and Table 82.
2. Output voltage measurements for all differential standards are made with a termination resistor (R ) of 100Ω across the N and P pins of the
T
differential signal pair. The exception is for BLVDS, shown in Figure 71.
3. At any given time, no more than two of the following differential output standards may be assigned to an I/O bank: LVDS_25, RSDS_25,
MINI_LVDS_25
X-Ref Target - Figure 71
1/4th of Bourns
Part Number
CAT16-LV4F12
1/4th of Bourns
Part Number
CAT16-PT4F4
V
CCO = 2.5V
V
CCO = 2.5V
Z
0
0
= 50Ω
= 50Ω
165Ω
FPGA
Out
FPGA
In
140Ω
100Ω
Z
165Ω
ds312-3_07_041108
Figure 71: External Termination Resistors for BLVDS Transmitter and BLVDS Receiver
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123
Spartan-3E FPGA Family: DC and Switching Characteristics
Switching Characteristics
All Spartan-3E FPGAs ship in two speed grades: -4 and the
higher performance -5. Switching characteristics in this
document may be designated as Advance, Preliminary, or
Production, as shown in Table 84. Each category is defined
as follows:
Timing parameters and their representative values are
selected for inclusion below either because they are
important as general design requirements or they indicate
fundamental device performance characteristics. The
Spartan-3E speed files (v1.27), part of the Xilinx
Development Software, are the original source for many but
not all of the values. The speed grade designations for
these files are shown in Table 84. For more complete, more
precise, and worst-case data, use the values reported by
the Xilinx static timing analyzer (TRACE in the Xilinx
development software) and back-annotated to the
simulation netlist.
Advance: These specifications are based on simulations
only and are typically available soon after establishing
FPGA specifications. Although speed grades with this
designation are considered relatively stable and
conservative, some under-reporting might still occur.
Preliminary: These specifications are based on complete
early silicon characterization. Devices and speed grades
with this designation are intended to give a better indication
of the expected performance of production silicon. The
probability of under-reporting preliminary delays is greatly
reduced compared to Advance data.
Table 84: Spartan-3E v1.27 Speed Grade Designations
Device
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
Advance
Preliminary
Production
-MIN, -4, -5
-MIN, -4, -5
-MIN, -4, -5
-MIN, -4, -5
-MIN, -4, -5
Production: These specifications are approved once
enough production silicon of a particular device family
member has been characterized to provide full correlation
between speed files and devices over numerous production
lots. There is no under-reporting of delays, and customers
receive formal notification of any subsequent changes.
Typically, the slowest speed grades transition to Production
before faster speed grades.
Table 85 provides the history of the Spartan-3E speed files
since all devices reached Production status.
Table 85: Spartan-3E Speed File Version History
Software Version Requirements
ISE
Version
Description
Added XA Automotive.
Release
9.2.03i
8.2.02i
Production-quality systems must use FPGA designs
compiled using a speed file designated as PRODUCTION
status. FPGAs designs using a less mature speed file
designation should only be used during system prototyping
or pre-production qualification. FPGA designs with speed
files designated as Advance or Preliminary should not be
used in a production-quality system.
1.27
1.26
Added -0/-MIN speed grade, which
includes minimum values.
1.25
1.23
1.21
8.2.01i
8.2i
Added XA Automotive devices to speed
file. Improved model for left and right
DCMs.
Updated input setup/hold values based
on default IFD_DELAY_VALUE
settings.
Whenever a speed file designation changes, as a device
matures toward Production status, rerun the latest Xilinx
ISE software on the FPGA design to ensure that the FPGA
design incorporates the latest timing information and
software updates.
8.1.03i
All Spartan-3E FPGAs and all speed
grades elevated to Production status.
All parameter limits are representative of worst-case supply
voltage and junction temperature conditions. Unless
otherwise noted, the published parameter values apply
to all Spartan-3E devices. AC and DC characteristics
are specified using the same numbers for both
commercial and industrial grades.
Create a Xilinx user account and sign up to receive
automatic e-mail notification whenever this data sheet or
the associated user guides are updated.
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124
Spartan-3E FPGA Family: DC and Switching Characteristics
I/O Timing
Table 86: Pin-to-Pin Clock-to-Output Times for the IOB Output Path
Speed Grade
Symbol
Description
Conditions
Device
-5
-4
Units
Max(2)
Max(2)
Clock-to-Output Times
TICKOFDCM
When reading from the Output Flip-Flop
LVCMOS25(3), 12 mA
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
2.66
3.00
3.01
3.01
3.00
5.60
4.91
4.98
5.36
5.45
2.79
3.45
3.46
3.46
3.45
5.92
5.43
5.51
5.94
6.05
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(OFF), the time from the active transition output drive, Fast slew
on the Global Clock pin to data appearing rate, with DCM(4)
at the Output pin. The DCM is used.
TICKOF
When reading from OFF, the time from the LVCMOS25(3), 12 mA
active transition on the Global Clock pin to output drive, Fast slew
data appearing at the Output pin. The
DCM is not used.
rate, without DCM
Notes:
1. The numbers in this table are tested using the methodology presented in Table 95 and are based on the operating conditions set forth in
Table 77 and Table 80.
2. For minimums, use the values reported by the Xilinx timing analyzer.
3. This clock-to-output time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or a
standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. If the former is true, add the appropriate
Input adjustment from Table 91. If the latter is true, add the appropriate Output adjustment from Table 94.
4. DCM output jitter is included in all measurements.
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125
Spartan-3E FPGA Family: DC and Switching Characteristics
Table 87: Pin-to-Pin Setup and Hold Times for the IOB Input Path (System Synchronous)
Speed Grade
IFD_
DELAY_
VALUE=
Symbol
Description
Conditions
Device
-5
-4
Units
Min
Min
Setup Times
TPSDCM
When writing to the Input
LVCMOS25(2)
,
0
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
2.65
2.25
2.25
2.25
2.25
3.16
3.44
4.00
2.60
3.33
2.98
2.59
2.59
2.58
2.59
3.58
3.91
4.73
3.31
3.77
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Flip-Flop (IFF), the time from the IFD_DELAY_VALUE = 0,
setup of data at the Input pin to with DCM(3)
the active transition at a Global
Clock pin. The DCM is used. No
Input Delay is programmed.
TPSFD
When writing to IFF, the time
from the setup of data at the
Input pin to an active transition at default software setting
the Global Clock pin. The DCM is
not used. The Input Delay is
LVCMOS25(2)
IFD_DELAY_VALUE =
,
2
3
3
3
3
programmed.
Hold Times
TPHDCM
When writing to IFF, the time
from the active transition at the
Global Clock pin to the point
when data must be held at the
Input pin. The DCM is used. No
Input Delay is programmed.
LVCMOS25(4)
,
0
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
–0.54
0.06
–0.52
0.14
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IFD_DELAY_VALUE = 0,
with DCM(3)
0.07
0.14
0.07
0.15
0.06
0.14
TPHFD
When writing to IFF, the time
from the active transition at the
Global Clock pin to the point
when data must be held at the
Input pin. The DCM is not used.
The Input Delay is programmed.
LVCMOS25(4)
IFD_DELAY_VALUE =
default software setting
,
2
3
3
3
3
–0.31
–0.32
–0.77
0.13
–0.24
–0.32
–0.77
0.16
–0.05
–0.03
Notes:
1. The numbers in this table are tested using the methodology presented in Table 95 and are based on the operating conditions set forth in
Table 77 and Table 80.
2. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from Table 91. If this is true of the data Input, add the
appropriate Input adjustment from the same table.
3. DCM output jitter is included in all measurements.
4. This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from Table 91. If this is true of the data Input, subtract the
appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
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126
Spartan-3E FPGA Family: DC and Switching Characteristics
Table 88: Setup and Hold Times for the IOB Input Path
Speed Grade
IFD_
Symbol
Description
Conditions
DELAY_
VALUE=
Device
-5
-4
Units
Min
Min
Setup Times
TIOPICK
Time from the setup of data at
the Input pin to the active
LVCMOS25(2)
IFD_DELAY_VALUE = 0
,
0
All
1.84
2.12
ns
transition at the ICLK input of the
Input Flip-Flop (IFF). No Input
Delay is programmed.
TIOPICKD
Time from the setup of data at
the Input pin to the active
transition at the IFF’s ICLK input. default software setting
The Input Delay is programmed.
LVCMOS25(2)
IFD_DELAY_VALUE =
,
2
3
XC3S100E
All Others
6.12
6.76
7.01
7.72
ns
Hold Times
TIOICKP
Time from the active transition at LVCMOS25(3)
the IFF’s ICLK input to the point IFD_DELAY_VALUE = 0
where data must be held at the
Input pin. No Input Delay is
,
0
All
–0.76
–0.76
ns
ns
programmed.
TIOICKPD
Time from the active transition at LVCMOS25(3)
the IFF’s ICLK input to the point IFD_DELAY_VALUE =
,
2
3
XC3S100E
All Others
–3.93
–3.50
–3.93
–3.50
where data must be held at the
Input pin. The Input Delay is
programmed.
default software setting
Set/Reset Pulse Width
TRPW_IOB Minimum pulse width to SR
control input on IOB
All
1.57
1.80
ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 95 and are based on the operating conditions set forth in
Table 77 and Table 80.
2. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the
appropriate Input adjustment from Table 91.
3. These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract
the appropriate Input adjustment from Table 91. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
Table 89: Sample Window (Source Synchronous)
Symbol
Description
Max
Units
TSAMP
Setup and hold capture window of an The input capture sample window value is highly specific to a particular
ps
IOB input flip-flop
application, device, package, I/O standard, I/O placement, DCM usage,
and clock buffer. Please consult the appropriate Xilinx application note
for application-specific values.
•
XAPP485: 1:7 Deserialization in Spartan-3E FPGAs at Speeds Up to
666 Mbps
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127
Spartan-3E FPGA Family: DC and Switching Characteristics
Table 90: Propagation Times for the IOB Input Path
Speed Grade
IFD_
Symbol
Description
Conditions
DELAY_
VALUE=
Device
-5
-4
Units
Min
Min
Propagation Times
TIOPLI
The time it takes for data to travel LVCMOS25(2)
,
0
All
1.96
2.25
ns
ns
from the Input pin through the
IFF latch to the I output with no
input delay programmed
IFD_DELAY_VALUE = 0
TIOPLID
The time it takes for data to travel LVCMOS25(2)
from the Input pin through the IFD_DELAY_VALUE =
IFF latch to the I output with the default software setting
input delay programmed
,
2
3
XC3S100E
All Others
5.40
6.30
5.97
7.20
Notes:
1. The numbers in this table are tested using the methodology presented in Table 95 and are based on the operating conditions set forth in
Table 77 and Table 80.
2. This propagation time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. When this is
true, add the appropriate Input adjustment from Table 91.
Table 91: Input Timing Adjustments by IOSTANDARD (Cont’d)
Table 91: Input Timing Adjustments by IOSTANDARD
Add the
Add the
Convert Input Time from
Adjustment Below
Convert Input Time from
Adjustment Below
LVCMOS25 to the
Units
LVCMOS25 to the
Units
Following Signal Standard
(IOSTANDARD)
Speed Grade
Following Signal Standard
(IOSTANDARD)
Speed Grade
-5
-4
-5
-4
Differential Standards
LVDS_25
Single-Ended Standards
LVTTL
0.48
0.39
0.48
0.27
0.48
0.48
0.48
0.30
0.32
0.49
0.39
0.49
0.27
0.49
0.49
0.49
0.30
0.32
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.42
0.42
0
0.43
0.43
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
BLVDS_25
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI33_3
MINI_LVDS_25
LVPECL_25
0.96
0.62
0.26
0.41
0.41
0.12
0.17
0.30
0.15
0.98
0.63
0.27
0.42
0.42
0.12
0.17
0.30
0.15
RSDS_25
DIFF_HSTL_I_18
DIFF_HSTL_III_18
DIFF_SSTL18_I
DIFF_SSTL2_I
PCI66_3
HSTL_I_18
HSTL_III_18
SSTL18_I
Notes:
1. The numbers in this table are tested using the methodology
presented in Table 95 and are based on the operating conditions
set forth in Table 77, Table 80, and Table 82.
SSTL2_I
2. These adjustments are used to convert input path times originally
specified for the LVCMOS25 standard to times that correspond to
other signal standards.
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Spartan-3E FPGA Family: DC and Switching Characteristics
Speed Grade
Table 92: Timing for the IOB Output Path
Symbol
Description
Conditions
Device
-5
-4
Units
Min
Min
Clock-to-Output Times
TIOCKP
When reading from the Output Flip-Flop (OFF), the LVCMOS25(2)
time from the active transition at the OCLK input to 12 mA output drive,
data appearing at the Output pin Fast slew rate
,
All
2.18
2.50
ns
Propagation Times
TIOOP
The time it takes for data to travel from the IOB’s O LVCMOS25(2)
,
All
All
2.24
2.32
2.58
2.67
ns
ns
input to the Output pin
12 mA output drive,
Fast slew rate
TIOOLP
The time it takes for data to travel from the O input
through the OFF latch to the Output pin
Set/Reset Times
TIOSRP
Time from asserting the OFF’s SR input to
setting/resetting data at the Output pin
LVCMOS25(2)
12 mA output drive,
Fast slew rate
,
3.27
8.40
3.76
9.65
ns
ns
TIOGSRQ
Time from asserting the Global Set Reset (GSR)
input on the STARTUP_SPARTAN3E primitive to
setting/resetting data at the Output pin
Notes:
1. The numbers in this table are tested using the methodology presented in Table 95 and are based on the operating conditions set forth in
Table 77 and Table 80.
2. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data
Output. When this is true, add the appropriate Output adjustment from Table 94.
3. For minimum delays use the values reported by the Timing Analyzer.
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Spartan-3E FPGA Family: DC and Switching Characteristics
Speed Grade
Table 93: Timing for the IOB Three-State Path
Symbol
Description
Conditions
Device
-5
-4
Units
Max
Max
Synchronous Output Enable/Disable Times
TIOCKHZ Time from the active transition at the OTCLK input LVCMOS25, 12 mA
All
All
1.49
2.70
1.71
3.10
ns
ns
of the Three-state Flip-Flop (TFF) to when the
Output pin enters the high-impedance state
output drive, Fast
slew rate
(2)
TIOCKON
Time from the active transition at TFF’s OTCLK
input to when the Output pin drives valid data
Asynchronous Output Enable/Disable Times
TGTS
Time from asserting the Global Three State (GTS) LVCMOS25, 12 mA
All
8.52
9.79
ns
input on the STARTUP_SPARTAN3E primitive to
when the Output pin enters the high-impedance
state
output drive, Fast
slew rate
Set/Reset Times
TIOSRHZ
Time from asserting TFF’s SR input to when the
Output pin enters a high-impedance state
LVCMOS25, 12 mA
output drive, Fast
slew rate
All
All
2.11
3.32
2.43
3.82
ns
ns
(2)
TIOSRON
Time from asserting TFF’s SR input at TFF to when
the Output pin drives valid data
Notes:
1. The numbers in this table are tested using the methodology presented in Table 95 and are based on the operating conditions set forth in
Table 77 and Table 80.
2. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data
Output. When this is true, add the appropriate Output adjustment from Table 94.
3. For minimum delays use the values reported by the Timing Analyzer.
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Spartan-3E FPGA Family: DC and Switching Characteristics
Table 94: Output Timing Adjustments for IOB (Cont’d)
Table 94: Output Timing Adjustments for IOB
Add the
Adjustment
Below
Add the
Adjustment
Below
Convert Output Time from
LVCMOS25 with 12mA Drive and
Fast Slew Rate to the Following
Signal Standard (IOSTANDARD)
Convert Output Time from
LVCMOS25 with 12mA Drive and
Fast Slew Rate to the Following
Signal Standard (IOSTANDARD)
Units
Units
Speed Grade
Speed Grade
-5
-4
-5
-4
LVCMOS18
Slow
2 mA
4 mA
6 mA
8 mA
2 mA
4 mA
6 mA
8 mA
2 mA
4 mA
6 mA
2 mA
4 mA
6 mA
2 mA
2 mA
5.03
3.08
2.39
1.83
3.98
2.04
1.09
0.72
4.49
3.81
2.99
3.25
2.59
1.47
6.36
4.26
0.33
0.53
0.44
0.44
0.24
–0.20
5.24
3.21
2.49
1.90
4.15
2.13
1.14
0.75
4.68
3.97
3.11
3.38
2.70
1.53
6.63
4.44
0.34
0.55
0.46
0.46
0.25
–0.20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Single-Ended Standards
LVTTL
Slow
Fast
Slow
Fast
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
2 mA
4 mA
6 mA
8 mA
12 mA
2 mA
4 mA
6 mA
8 mA
12 mA
5.20
2.32
1.83
0.64
0.68
0.41
4.80
1.88
1.39
0.32
0.28
0.28
5.08
1.82
1.00
0.66
0.40
0.41
4.68
1.46
0.38
0.33
0.28
0.28
4.04
2.17
1.46
1.04
0.65
3.53
1.65
0.44
0.20
0
5.41
2.41
1.90
0.67
0.70
0.43
5.00
1.96
1.45
0.34
0.30
0.30
5.29
1.89
1.04
0.69
0.42
0.43
4.87
1.52
0.39
0.34
0.30
0.30
4.21
2.26
1.52
1.08
0.68
3.67
1.72
0.46
0.21
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Fast
LVCMOS15
LVCMOS12
Slow
Fast
LVCMOS33
Slow
Fast
HSTL_I_18
HSTL_III_18
PCI33_3
PCI66_3
SSTL18_I
SSTL2_I
Differential Standards
LVDS_25
–0.55
0.04
–0.55
0.04
ns
ns
ns
ns
ns
ns
ns
ns
ns
BLVDS_25
MINI_LVDS_25
LVPECL_25
–0.56
–0.56
LVCMOS25
Slow
Fast
Input Only
RSDS_25
–0.48
0.42
0.53
0.40
0.44
–0.48
0.42
0.55
0.40
0.44
DIFF_HSTL_I_18
DIFF_HSTL_III_18
DIFF_SSTL18_I
DIFF_SSTL2_I
Notes:
1. The numbers in this table are tested using the methodology
presented in Table 95 and are based on the operating conditions
set forth in Table 77, Table 80, and Table 82.
2. These adjustments are used to convert output- and
three-state-path times originally specified for the LVCMOS25
standard with 12 mA drive and Fast slew rate to times that
correspond to other signal standards. Do not adjust times that
measure when outputs go into a high-impedance state.
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131
Spartan-3E FPGA Family: DC and Switching Characteristics
Timing Measurement Methodology
When measuring timing parameters at the programmable
I/Os, different signal standards call for different test
conditions. Table 95 lists the conditions to use for each
standard.
LVCMOS, LVTTL), then R is set to 1MΩ to indicate an open
T
connection, and V is set to zero. The same measurement
T
point (V ) that was used at the Input is also used at the
M
Output.
X-Ref Target - Figure 72
The method for measuring Input timing is as follows: A
V (V
)
signal that swings between a Low logic level of V and a
L
T
REF
High logic level of V is applied to the Input under test.
Some standards also require the application of a bias
H
FPGA Output
R (R
T
)
REF
voltage to the V
pins of a given bank to properly set the
REF
input-switching threshold. The measurement point of the
V
(V
)
M
MEAS
Input signal (V ) is commonly located halfway between V
M
L
and V .
C (C
)
H
L
REF
The Output test setup is shown in Figure 72. A termination
voltage V is applied to the termination resistor R , the other
ds312-3_04_090105
T
T
Notes:
end of which is connected to the Output. For each standard,
R and V generally take on the standard values
1. The names shown in parentheses are
used in the IBIS file.
T
T
recommended for minimizing signal reflections. If the
standard does not ordinarily use terminations (e.g.,
Figure 72: Output Test Setup
Table 95: Test Methods for Timing Measurement at I/Os
Inputs and
Inputs
Outputs
Signal Standard
(IOSTANDARD)
Outputs
VREF (V)
VL (V)
VH (V)
RT (Ω)
VT (V)
VM (V)
Single-Ended
LVTTL
-
-
-
-
-
-
-
0
3.3
3.3
1M
1M
1M
1M
1M
1M
25
0
0
1.4
1.65
1.25
0.9
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI33_3
0
0
2.5
0
0
1.8
0
0
0
1.5
0
0.75
0.6
1.2
0
Rising
Falling
Rising
Falling
Note 3
Note 3
0
0.94
2.03
0.94
2.03
VREF
VREF
VREF
VREF
25
3.3
0
PCI66_3
-
Note 3
Note 3
25
25
3.3
0.9
1.8
0.9
1.25
HSTL_I_18
HSTL_III_18
SSTL18_I
SSTL2_I
0.9
1.1
V
REF – 0.5
VREF + 0.5
VREF + 0.5
VREF + 0.5
VREF + 0.75
50
VREF – 0.5
VREF – 0.5
VREF – 0.75
50
0.9
50
1.25
50
Differential
LVDS_25
-
-
-
-
-
VICM – 0.125
VICM – 0.125
VICM – 0.125
VICM – 0.3
VICM + 0.125
VICM + 0.125
VICM + 0.125
VICM + 0.3
50
1M
50
1.2
0
VICM
VICM
VICM
VICM
VICM
BLVDS_25
MINI_LVDS_25
LVPECL_25
RSDS_25
1.2
0
1M
50
VICM – 0.1
VICM + 0.1
1.2
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132
Spartan-3E FPGA Family: DC and Switching Characteristics
Table 95: Test Methods for Timing Measurement at I/Os (Cont’d)
Inputs and
Outputs
Inputs
Outputs
Signal Standard
(IOSTANDARD)
VREF (V)
VL (V)
VH (V)
RT (Ω)
50
VT (V)
0.9
VM (V)
VICM
VICM
VICM
VICM
DIFF_HSTL_I_18
-
-
-
-
VREF – 0.5
VREF – 0.5
VREF – 0.5
VREF – 0.5
VREF + 0.5
VREF + 0.5
VREF + 0.5
VREF + 0.5
DIFF_HSTL_III_18
DIFF_SSTL18_I
DIFF_SSTL2_I
50
1.8
50
0.9
50
1.25
Notes:
1. Descriptions of the relevant symbols are as follows:
V
V
V
– The reference voltage for setting the input switching threshold
– The common mode input voltage
– Voltage of measurement point on signal transition
REF
ICM
M
V – Low-level test voltage at Input pin
L
V
– High-level test voltage at Input pin
H
R – Effective termination resistance, which takes on a value of 1MΩ when no parallel termination is required
T
V – Termination voltage
T
2. The load capacitance (C ) at the Output pin is 0 pF for all signal standards.
L
3. According to the PCI specification.
The capacitive load (C ) is connected between the output
and GND. The Output timing for all standards, as published
Delays for a given application are simulated according to its
specific load conditions as follows:
L
in the speed files and the data sheet, is always based on a
1. Simulate the desired signal standard with the output
driver connected to the test setup shown in Figure 72.
C value of zero. High-impedance probes (less than 1 pF)
L
are used for all measurements. Any delay that the test
fixture might contribute to test measurements is subtracted
from those measurements to produce the final timing
numbers as published in the speed files and data sheet.
Use parameter values V , R , and V from Table 95.
T
T
M
C
is zero.
REF
2. Record the time to V .
M
3. Simulate the same signal standard with the output
driver connected to the PCB trace with load. Use the
Using IBIS Models to Simulate Load
Conditions in Application
appropriate IBIS model (including V , R , C
,
REF REF REF
and V
load.
values) or capacitive value to represent the
MEAS
IBIS models permit the most accurate prediction of timing
delays for a given application. The parameters found in the
4. Record the time to V
.
MEAS
IBIS model (V
, R
, and V
) correspond directly
REF
REF
MEAS
5. Compare the results of steps 2 and 4. Add (or subtract)
the increase (or decrease) in delay to (or from) the
appropriate Output standard adjustment (Table 94) to
yield the worst-case delay of the PCB trace.
with the parameters used in Table 95 (V , R , and V ). Do
T
T
M
not confuse V
(the termination voltage) from the IBIS
REF
model with V
(the input-switching threshold) from the
REF
table. A fourth parameter, C , is always zero. The four
REF
parameters describe all relevant output test conditions. IBIS
models are found in the Xilinx development software as well
as at the following link:
http://www.xilinx.com/support/download/index.htm
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133
Spartan-3E FPGA Family: DC and Switching Characteristics
Simultaneously Switching Output Guidelines
This section provides guidelines for the recommended
maximum allowable number of Simultaneous Switching
Outputs (SSOs). These guidelines describe the maximum
number of user I/O pins of a given output signal standard
that should simultaneously switch in the same direction,
while maintaining a safe level of switching noise. Meeting
these guidelines for the stated test conditions ensures that
the FPGA operates free from the adverse effects of ground
and power bounce.
equivalent number of pairs is based on characterization and
might not match the physical number of pairs. For each
output signal standard and drive strength, Table 97
recommends the maximum number of SSOs, switching in
the same direction, allowed per V
/GND pair within an
CCO
I/O bank. The guidelines in Table 97 are categorized by
package style. Multiply the appropriate numbers from
Table 96 and Table 97 to calculate the maximum number of
SSOs allowed within an I/O bank. Exceeding these SSO
guidelines might result in increased power or ground
bounce, degraded signal integrity, or increased system jitter.
Ground or power bounce occurs when a large number of
outputs simultaneously switch in the same direction. The
output drive transistors all conduct current to a common
SSO
/IO Bank = Table 96 x Table 97
MAX
voltage rail. Low-to-High transitions conduct to the V
CCO
The recommended maximum SSO values assumes that the
FPGA is soldered on the printed circuit board and that the
board uses sound design practices. The SSO values do not
apply for FPGAs mounted in sockets, due to the lead
inductance introduced by the socket.
rail; High-to-Low transitions conduct to the GND rail. The
resulting cumulative current transient induces a voltage
difference across the inductance that exists between the die
pad and the power supply or ground return. The inductance
is associated with bonding wires, the package lead frame,
and any other signal routing inside the package. Other
variables contribute to SSO noise levels, including stray
inductance on the PCB as well as capacitive loading at
receivers. Any SSO-induced voltage consequently affects
internal switching noise margins and ultimately signal
quality.
The number of SSOs allowed for quad-flat packages (VQ,
TQ, PQ) is lower than for ball grid array packages (FG) due
to the larger lead inductance of the quad-flat packages. The
results for chip-scale packaging (CP132) are better than
quad-flat packaging but not as high as for ball grid array
packaging. Ball grid array packages are recommended for
applications with a large number of simultaneously
switching outputs.
Table 96 and Table 97 provide the essential SSO
guidelines. For each device/package combination, Table 96
provides the number of equivalent V
/GND pairs. The
CCO
Table 96: Equivalent V
/GND Pairs per Bank
CCO
Package Style (including Pb-free)
Device
VQ100
CP132
TQ144
PQ208
FT256
FG320
FG400
FG484
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
2
2
2
2
-
2
2
-
-
3
3
-
-
4
4
4
-
-
-
-
-
-
2
2
-
-
5
5
5
-
-
-
6
6
-
-
-
-
-
7
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Product Specification
134
Spartan-3E FPGA Family: DC and Switching Characteristics
Table 97: Recommended Number of Simultaneously
Table 97: Recommended Number of Simultaneously
Switching Outputs per V
/GND Pair (Cont’d)
Switching Outputs per V
/GND Pair
CCO
CCO
Package Type
Package Type
FT256
FG320
FG400
FG484
FT256
FG320
FG400
FG484
Signal Standard
(IOSTANDARD)
Signal Standard
(IOSTANDARD)
VQ
100
TQ
144
PQ
208
CP
132
VQ
100
TQ
144
PQ
208
CP
132
LVCMOS15 Slow
2
4
6
2
4
6
2
2
16
8
10
7
10
7
19
9
55
31
18
25
16
13
55
31
16
13
11
17
16
15
18
Single-Ended Standards
LVTTL
Slow
2
4
34
20
10
10
6
19
10
7
52
26
26
13
13
6
60
41
29
22
13
11
34
20
15
12
10
9
6
5
5
9
17
17
8
Fast
9
9
9
13
7
6
7
7
7
8
6
5
5
5
5
12
16
2
8
6
5
LVCMOS12 Slow
Fast
17
10
8
11
10
8
11
10
8
16
10
16
13
11
16
16
15
18
5
5
5
Fast
17
9
17
9
17
9
26
13
13
6
PCI33_3
4
PCI66_3
8
8
8
6
7
7
7
PCIX
7
7
7
8
6
6
6
HSTL_I_18
HSTL_III_18
SSTL18_I
SSTL2_I
10
10
9
10
10
9
10
10
9
12
16
2
5
5
5
6
5
5
5
5
LVCMOS33 Slow
34
17
17
8
20
10
10
6
20
10
7
52
26
26
13
13
6
76
46
27
20
13
10
44
26
16
12
10
8
12
12
12
4
Differential Standards (Number of I/O Pairs or Channels)
6
LVDS_25
6
4
6
6
4
6
6
4
6
12
4
20
4
8
6
BLVDS_25
12
16
2
8
6
5
MINI_LVDS_25
LVPECL_25
12
20
5
5
5
Input Only
Fast
17
8
17
8
17
8
26
13
13
6
RSDS_25
6
5
5
4
6
6
5
5
4
6
6
5
5
4
6
12
20
8
4
DIFF_HSTL_I_18
DIFF_HSTL_IIII_18
DIFF_SSTL18_I
DIFF_SSTL2_I
8
8
7
9
6
8
6
6
8
8
6
6
6
7
12
16
2
5
5
5
6
8
8
8
5
5
LVCMOS25 Slow
28
13
13
6
16
10
7
16
10
7
42
19
19
9
76
46
33
24
18
42
20
15
13
11
64
34
22
18
36
21
13
10
Notes:
4
1. The numbers in this table are recommendations that assume
sound board layout practice. This table assumes the following
parasitic factors: combined PCB trace and land inductance per
VCCO and GND pin of 1.0 nH, receiver capacitive load of 15 pF.
Test limits are the VIL/VIH voltage limits for the respective I/O
standard.
2. The PQ208 results are based on physical measurements of a
PQ208 package soldered to a typical printed circuit board. All
other results are based on worst-case simulation and an
interpolation of the PQ208 physical results.
6
8
6
6
12
2
6
6
6
9
Fast
17
9
16
9
16
9
26
13
13
6
4
6
9
7
7
3. If more than one signal standard is assigned to the I/Os of a given
bank, refer to XAPP689: Managing Ground Bounce in Large
FPGAs for information on how to perform weighted average SSO
calculations.
8
6
6
6
12
2
5
5
5
6
LVCMOS18 Slow
19
13
6
11
7
8
29
19
9
4
6
6
5
5
8
6
4
4
9
Fast
2
13
8
8
8
19
13
6
4
5
5
6
4
4
4
8
4
4
4
6
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Spartan-3E FPGA Family: DC and Switching Characteristics
Configurable Logic Block (CLB) Timing
Table 98: CLB (SLICEM) Timing
Speed Grade
Symbol
Description
-5
-4
Units
Min
Max
Min
Max
Clock-to-Output Times
TCKO
When reading from the FFX (FFY) Flip-Flop, the time
from the active transition at the CLK input to data
appearing at the XQ (YQ) output
-
0.52
-
0.60
ns
Setup Times
TAS
Time from the setup of data at the F or G input to the
active transition at the CLK input of the CLB
0.46
1.58
-
-
0.52
1.81
-
-
ns
ns
TDICK
Time from the setup of data at the BX or BY input to
the active transition at the CLK input of the CLB
Hold Times
TAH
Time from the active transition at the CLK input to the
point where data is last held at the F or G input
0
0
-
-
0
0
-
-
ns
ns
TCKDI
Time from the active transition at the CLK input to the
point where data is last held at the BX or BY input
Clock Timing
TCH
The High pulse width of the CLB’s CLK signal
The Low pulse width of the CLK signal
Toggle frequency (for export control)
0.70
0.70
0
-
-
0.80
0.80
0
-
-
ns
ns
TCL
FTOG
657
572
MHz
Propagation Times
TILO
The time it takes for data to travel from the CLB’s F
(G) input to the X (Y) output
-
0.66
-
-
0.76
-
ns
ns
Set/Reset Pulse Width
TRPW_CLB
The minimum allowable pulse width, High or Low, to
the CLB’s SR input
1.57
1.80
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 77.
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Spartan-3E FPGA Family: DC and Switching Characteristics
Table 99: CLB Distributed RAM Switching Characteristics
-5
-4
Symbol
Description
Units
Min
Max
Min
Max
Clock-to-Output Times
TSHCKO
Time from the active edge at the CLK input to data appearing on
the distributed RAM output
-
2.05
-
2.35
ns
Setup Times
TDS
Setup time of data at the BX or BY input before the active
transition at the CLK input of the distributed RAM
0.40
0.46
0.34
-
-
-
0.46
0.52
0.40
-
-
-
ns
ns
ns
TAS
Setup time of the F/G address inputs before the active transition
at the CLK input of the distributed RAM
TWS
Setup time of the write enable input before the active transition at
the CLK input of the distributed RAM
Hold Times
TDH
Hold time of the BX, BY data inputs after the active transition at
the CLK input of the distributed RAM
0.13
0
-
-
0.15
0
-
-
ns
ns
T
AH, TWH
Hold time of the F/G address inputs or the write enable input after
the active transition at the CLK input of the distributed RAM
Clock Pulse Width
TWPH, TWPL
Minimum High or Low pulse width at CLK input
0.88
-
1.01
-
ns
Table 100: CLB Shift Register Switching Characteristics
-5
-4
Symbol
Description
Units
Min
Max
Min
Max
Clock-to-Output Times
TREG
Time from the active edge at the CLK input to data appearing on
the shift register output
-
3.62
-
4.16
ns
ns
Setup Times
TSRLDS
Setup time of data at the BX or BY input before the active
transition at the CLK input of the shift register
0.41
-
0.46
-
Hold Times
TSRLDH
Hold time of the BX or BY data input after the active transition at
the CLK input of the shift register
0.14
0.88
-
-
0.16
1.01
-
-
ns
ns
Clock Pulse Width
TWPH, TWPL
Minimum High or Low pulse width at CLK input
Clock Buffer/Multiplexer Switching Characteristics
Table 101: Clock Distribution Switching Characteristics
Maximum
Speed Grade
Description
Symbol
Units
-5
-4
Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to O-output delay
TGIO
TGSI
1.46
1.46
0.63
311
ns
ns
Global clock multiplexer (BUFGMUX) select S-input setup to I0 and I1 inputs. Same
as BUFGCE enable CE-input
0.55
333
Frequency of signals distributed on global buffers (all sides)
FBUFG
MHz
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Spartan-3E FPGA Family: DC and Switching Characteristics
18 x 18 Embedded Multiplier Timing
Table 102: 18 x 18 Embedded Multiplier Timing
Speed Grade
Symbol
Description
-5
-4
Units
Min
Max
Min
Max
Combinatorial Delay
TMULT
Combinatorial multiplier propagation delay from the A and B inputs
to the P outputs, assuming 18-bit inputs and a 36-bit product
(AREG, BREG, and PREG registers unused)
-
4.34(1)
-
4.88(1)
ns
Clock-to-Output Times
TMSCKP_P
Clock-to-output delay from the active transition of the CLK input to
valid data appearing on the P outputs when using the PREG
-
-
0.98
4.42
-
-
1.10
4.97
ns
ns
register(2)
TMSCKP_A
TMSCKP_B
Clock-to-output delay from the active transition of the CLK input to
valid data appearing on the P outputs when using either the AREG
or BREG register(3)
Setup Times
TMSDCK_P
Data setup time at the A or B input before the active transition at the
CLK when using only the PREG output register (AREG, BREG
registers unused)(2)
3.54
-
3.98
-
ns
TMSDCK_A
TMSDCK_B
Data setup time at the A input before the active transition at the
CLK when using the AREG input register(3)
0.20
0.35
-
-
0.23
0.39
-
-
ns
ns
Data setup time at the B input before the active transition at the
CLK when using the BREG input register(3)
Hold Times
TMSCKD_P
Data hold time at the A or B input after the active transition at the
CLK when using only the PREG output register (AREG, BREG
registers unused)(2)
–0.97
-
–0.97
-
ns
TMSCKD_A
TMSCKD_B
Clock Frequency
Data hold time at the A input after the active transition at the CLK
0.03
0.04
-
-
0.04
0.05
-
-
ns
ns
when using the AREG input register(3)
Data hold time at the B input after the active transition at the CLK
when using the BREG input register(3)
FMULT
Internal operating frequency for a two-stage 18x18 multiplier using
the AREG and BREG input registers and the PREG output
0
270
0
240
MHz
register(1)
Notes:
1. Combinatorial delay is less and pipelined performance is higher when multiplying input data with less than 18 bits.
2. The PREG register is typically used in both single-stage and two-stage pipelined multiplier implementations.
3. Input registers AREG or BREG are typically used when inferring a two-stage multiplier.
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Spartan-3E FPGA Family: DC and Switching Characteristics
Block RAM Timing
Table 103: Block RAM Timing
Speed Grade
Symbol
Description
-5
-4
Units
Min
Max
Min
Max
Clock-to-Output Times
TBCKO
When reading from block RAM, the delay from the active
transition at the CLK input to data appearing at the DOUT
output
-
2.45
-
2.82
ns
Setup Times
TBACK
Setup time for the ADDR inputs before the active transition at
the CLK input of the block RAM
0.33
0.23
0.67
1.09
-
-
-
-
0.38
0.23
0.77
1.26
-
-
-
-
ns
ns
ns
ns
TBDCK
TBECK
TBWCK
Setup time for data at the DIN inputs before the active
transition at the CLK input of the block RAM
Setup time for the EN input before the active transition at the
CLK input of the block RAM
Setup time for the WE input before the active transition at the
CLK input of the block RAM
Hold Times
TBCKA
Hold time on the ADDR inputs after the active transition at the
CLK input
0.12
0.12
0
-
-
-
-
0.14
0.13
0
-
-
-
-
ns
ns
ns
ns
TBCKD
TBCKE
TBCKW
Hold time on the DIN inputs after the active transition at the
CLK input
Hold time on the EN input after the active transition at the CLK
input
Hold time on the WE input after the active transition at the CLK
input
0
0
Clock Timing
TBPWH
High pulse width of the CLK signal
Low pulse width of the CLK signal
1.39
1.39
-
-
1.59
1.59
-
-
ns
ns
TBPWL
Clock Frequency
FBRAM
Block RAM clock frequency. RAM read output value written
back into RAM, for shift-registers and circular buffers.
Write-only or read-only performance is faster.
0
270
0
230
MHz
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 77.
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Product Specification
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Spartan-3E FPGA Family: DC and Switching Characteristics
Digital Clock Manager (DCM) Timing
For specification purposes, the DCM consists of three key
components: the Delay-Locked Loop (DLL), the Digital
Frequency Synthesizer (DFS), and the Phase Shifter (PS).
Period jitter is the worst-case deviation from the ideal clock
period over a collection of millions of samples. In a
histogram of period jitter, the mean value is the clock period.
Aspects of DLL operation play a role in all DCM
Cycle-cycle jitter is the worst-case difference in clock period
between adjacent clock cycles in the collection of clock
periods sampled. In a histogram of cycle-cycle jitter, the
mean value is zero.
applications. All such applications inevitably use the CLKIN
and the CLKFB inputs connected to either the CLK0 or the
CLK2X feedback, respectively. Thus, specifications in the
DLL tables (Table 104 and Table 105) apply to any
application that only employs the DLL component. When
the DFS and/or the PS components are used together with
the DLL, then the specifications listed in the DFS and PS
tables (Table 106 through Table 109) supersede any
corresponding ones in the DLL tables. DLL specifications
that do not change with the addition of DFS or PS functions
are presented in Table 104 and Table 105.
Spread Spectrum
DCMs accept typical spread spectrum clocks as long as
they meet the input requirements. The DLL will track the
frequency changes created by the spread spectrum clock to
drive the global clocks to the FPGA logic. See XAPP469,
Spread-Spectrum Clocking Reception for Displays for
details.
Period jitter and cycle-cycle jitter are two of many different
ways of specifying clock jitter. Both specifications describe
statistical variation from a mean value.
Delay-Locked Loop (DLL)
Table 104: Recommended Operating Conditions for the DLL
Speed Grade
Symbol
Description
-5
-4
Units
Min
Max
Min
Max
Input Frequency Ranges
FCLKIN CLKIN_FREQ_DLL Frequency of the CLKIN
clock input
Stepping 0
Stepping 1
XC3S100E
XC3S250E
XC3S500E
XC3S1600E
N/A
N/A
5(2)
90(3)
MHz
XC3S1200E(3)
All
200(3)
240(3)
MHz
MHz
5(2)
275(3)
Input Pulse Requirements
CLKIN_PULSE
CLKIN pulse width as a
percentage of the CLKIN
period
FCLKIN ≤ 150 MHz
40%
45%
60%
55%
40%
45%
60%
55%
-
-
FCLKIN > 150 MHz
Input Clock Jitter Tolerance and Delay Path Variation(4)
CLKIN_CYC_JITT_DLL_LF
CLKIN_CYC_JITT_DLL_HF
CLKIN_PER_JITT_DLL
Cycle-to-cycle jitter at the
CLKIN input
FCLKIN ≤ 150 MHz
FCLKIN > 150 MHz
-
-
-
-
300
150
1
-
-
-
-
300
150
1
ps
ps
ns
ns
Period jitter at the CLKIN input
CLKFB_DELAY_VAR_EXT
Allowable variation of off-chip feedback delay from the DCM
output to the CLKFB input
1
1
Notes:
1. DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.
2. The DFS, when operating independently of the DLL, supports lower FCLKIN frequencies. See Table 106.
3. To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming
clock frequency by two as it enters the DCM. The CLK2X output reproduces the clock frequency provided on the CLKIN input.
4. CLKIN input jitter beyond these limits might cause the DCM to lose lock.
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Spartan-3E FPGA Family: DC and Switching Characteristics
Speed Grade
Table 105: Switching Characteristics for the DLL
Symbol
Description
Device
-5
-4
Units
Min
Max
Min
Max
Output Frequency Ranges
CLKOUT_FREQ_CLK0
Frequency for the CLK0 and
CLK180 outputs
Stepping 0
XC3S100E
XC3S250E
XC3S500E
XC3S1600E
N/A
N/A
5
90
MHz
XC3S1200E
All
200
240
90
MHz
MHz
MHz
Stepping 1
Stepping 0
5
275
N/A
CLKOUT_FREQ_CLK90
CLKOUT_FREQ_2X
CLKOUT_FREQ_DV
Frequency for the CLK90 and
CLK270 outputs
XC3S100E
XC3S250E
XC3S500E
XC3S1600E
N/A
5
XC3S1200E
All
167
200
180
MHz
MHz
MHz
Stepping 1
Stepping 0
5
200
N/A
Frequency for the CLK2X and
CLK2X180 outputs
XC3S100E
XC3S250E
XC3S500E
XC3S1600E
N/A
10
XC3S1200E
All
311
311
60
MHz
MHz
MHz
Stepping 1
Stepping 0
10
333
N/A
Frequency for the CLKDV
output
XC3S100E
XC3S250E
XC3S500E
XC3S1600E
N/A
0.3125
XC3S1200E
All
133
160
MHz
MHz
Stepping 1
0.3125
183
Output Clock Jitter(2,3,4)
CLKOUT_PER_JITT_0
CLKOUT_PER_JITT_90
CLKOUT_PER_JITT_180
CLKOUT_PER_JITT_270
CLKOUT_PER_JITT_2X
Period jitter at the CLK0 output
Period jitter at the CLK90 output
Period jitter at the CLK180 output
Period jitter at the CLK270 output
All
-
-
-
-
-
100
150
150
150
-
-
-
-
-
100
150
150
150
ps
ps
ps
ps
ps
Period jitter at the CLK2X and CLK2X180 outputs
[1% of
CLKIN
period
+ 150]
[1% of
CLKIN
period
+ 150]
CLKOUT_PER_JITT_DV1
CLKOUT_PER_JITT_DV2
Period jitter at the CLKDV output when
performing integer division
-
-
150
-
-
150
ps
ps
Period jitter at the CLKDV output when
performing non-integer division
[1% of
CLKIN
period
+ 200]
[1% of
CLKIN
period
+ 200]
Duty Cycle(4)
CLKOUT_DUTY_CYCLE_DLL Duty cycle variation for the CLK0, CLK90,
CLK180, CLK270, CLK2X, CLK2X180, and
All
-
[1% of
CLKIN
period
+ 400]
-
[1% of
CLKIN
period
+ 400]
ps
CLKDV outputs, including the BUFGMUX and
clock tree duty-cycle distortion
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Spartan-3E FPGA Family: DC and Switching Characteristics
Table 105: Switching Characteristics for the DLL (Cont’d)
Speed Grade
Symbol
Description
Device
-5
-4
Units
Min
Max
Min
Max
Phase Alignment(4)
CLKIN_CLKFB_PHASE
Phase offset between the CLKIN and CLKFB
inputs
All
-
-
200
-
-
200
ps
ps
CLKOUT_PHASE_DLL
Phase offset between DLL
outputs
CLK0 to CLK2X
(not CLK2X180)
[1% of
CLKIN
period
+ 100]
[1% of
CLKIN
period
+ 100]
All others
-
[1% of
CLKIN
period
+ 200]
-
[1% of
CLKIN
period
+ 200]
ps
Lock Time
(3)
LOCK_DLL
When using the DLL alone:
The time from deassertion at ≤ 15 MHz
the DCM’s Reset input to the
5 MHz ≤ F
All
-
-
5
-
-
5
ms
CLKIN
F
> 15 MHz
600
600
μs
CLKIN
rising transition at its
LOCKED output. When the
DCM is locked, the CLKIN and
CLKFB signals are in phase
Delay Lines
DCM_DELAY_STEP
Finest delay resolution
All
20
40
20
40
ps
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 77 and Table 104.
2. Indicates the maximum amount of output jitter that the DCM adds to the jitter on the CLKIN input.
3. For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
4. Some jitter and duty-cycle specifications include 1% of input clock period or 0.01 UI.
Example: The data sheet specifies a maximum jitter of [1% of CLKIN period + 150]. Assume the CLKIN frequency is 100 MHz. The
equivalent CLKIN period is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is [100 ps + 150 ps]
=
250 ps.
Digital Frequency Synthesizer (DFS)
Table 106: Recommended Operating Conditions for the DFS
Speed Grade
Symbol
Description
-5
-4
Units
Min
Max
Min
Max
Input Frequency Ranges(2)
(4)
(4)
FCLKIN
CLKIN_FREQ_FX
Frequency for the CLKIN input
0.200
333
0.200
333
MHz
Input Clock Jitter Tolerance(3)
CLKIN_CYC_JITT_FX_LF
CLKIN_CYC_JITT_FX_HF
Cycle-to-cycle jitter at the
CLKIN input, based on CLKFX
output frequency
FCLKFX ≤ 150 MHz
FCLKFX > 150 MHz
-
-
300
150
-
-
300
150
ps
ps
CLKIN_PER_JITT_FX
Period jitter at the CLKIN input
-
1
-
1
ns
Notes:
1. DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) are used.
2. If both DFS and DLL outputs are used on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in Table 104.
3. CLKIN input jitter beyond these limits may cause the DCM to lose lock.
4. To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming
clock frequency by two as it enters the DCM.
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Spartan-3E FPGA Family: DC and Switching Characteristics
Table 107: Switching Characteristics for the DFS
Speed Grade
Symbol
Description
Device
-5
-4
Units
Min
Max
Min
Max
Output Frequency Ranges
CLKOUT_FREQ_FX_LF
Frequency for the CLKFX and
CLKFX180 outputs, low
frequencies
Stepping 0
XC3S100E
XC3S250E
XC3S500E
XC3S1600E
N/A
N/A
5
90
MHz
MHz
CLKOUT_FREQ_FX_HF
CLKOUT_FREQ_FX
Frequency for the CLKFX and
CLKFX180 outputs, high
frequencies
220
5
307
Frequency for the CLKFX and
CLKFX180 outputs
Stepping 0
Stepping 1
XC3S1200E
All
307
311
MHz
MHz
5
333
Output Clock Jitter(2,3)
CLKOUT_PER_JITT_FX
Period jitter at the CLKFX and
CLKFX180 outputs.
All
All
Typ
Max
Typ
Max
CLKIN ≤ 20 MHz
CLKIN > 20 MHz
Note 6
ps
ps
[1% of [1% of [1%of [1%of
CLKFX CLKFX CLKFX CLKFX
period period period period
+ 100] + 200] + 100] + 200]
Duty Cycle(4,5)
CLKOUT_DUTY_CYCLE_FX Duty cycle precision for the CLKFX and CLKFX180
outputs, including the BUFGMUX and clock tree
duty-cycle distortion
-
[1% of
CLKFX
period
+ 400]
-
[1%of
CLKFX
period
+ 400]
ps
Phase Alignment(5)
CLKOUT_PHASE_FX
Phase offset between the DFS CLKFX output and the
DLL CLK0 output when both the DFS and DLL are
used
All
All
-
-
200
-
-
200
ps
ps
CLKOUT_PHASE_FX180
Phase offset between the DFS CLKFX180 output and
the DLL CLK0 output when both the DFS and DLL are
used
[1% of
CLKFX
period
+ 300]
[1%of
CLKFX
period
+ 300]
Lock Time
(2)
LOCK_FX
The time from deassertion at the
DCM’s Reset input to the rising
transition at its LOCKED output.
The DFS asserts LOCKED when
the CLKFX and CLKFX180
signals are valid. If using both
the DLL and the DFS, use the
longer locking time.
5 MHz ≤ F
All
-
-
5
-
-
5
ms
CLKIN
≤ 15 MHz
F
> 15 MHz
450
450
μs
CLKIN
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 77 and Table 106.
2. For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
3. Maximum output jitter is characterized within a reasonable noise environment (150 ps input period jitter, 40 SSOs and 25% CLB switching).
Output jitter strongly depends on the environment, including the number of SSOs, the output drive strength, CLB utilization, CLB switching
activities, switching frequency, power supply and PCB design. The actual maximum output jitter depends on the system application.
4. The CLKFX and CLKFX180 outputs always have an approximate 50% duty cycle.
5. Some duty-cycle and alignment specifications include 1% of the CLKFX output period or 0.01 UI.
Example: The data sheet specifies a maximum jitter of [1% of CLKFX period + 300]. Assume the CLKFX output frequency is 100 MHz. The
equivalent CLKFX period is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is [100 ps + 300 ps]
=
400 ps.
6. Use the Spartan-3A Jitter Calculator (www.xilinx.com/support/documentation/data_sheets/s3a_jitter_calc.zip) to estimate DFS output jitter.
Use the Clocking Wizard to determine jitter for a specific design.
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Spartan-3E FPGA Family: DC and Switching Characteristics
Phase Shifter (PS)
Table 108: Recommended Operating Conditions for the PS in Variable Phase Mode
Speed Grade
Symbol
Description
-5
-4
Units
Min
Max
Min
Max
Operating Frequency Ranges
PSCLK_FREQ
(FPSCLK
Frequency for the PSCLK input
1
167
1
167
MHz
-
)
Input Pulse Requirements
PSCLK_PULSE PSCLK pulse width as a percentage of the PSCLK period
40%
60%
40%
60%
Table 109: Switching Characteristics for the PS in Variable Phase Mode
Symbol
Phase Shifting Range
MAX_STEPS(2)
Description
Equation
Units
Maximum allowed number of DCM_DELAY_STEP steps CLKIN < 60 MHz
for a given CLKIN clock period, where T = CLKIN clock
[INTEGER(10 • steps
(TCLKIN – 3 ns))]
period in ns. If using CLKIN_DIVIDE_BY_2 = TRUE,
double the effective clock period.(3)
CLKIN ≥ 60 MHz
[INTEGER(15 • steps
(TCLKIN – 3 ns))]
FINE_SHIFT_RANGE_MIN
Minimum guaranteed delay for variable phase shifting
[MAX_STEPS •
DCM_DELAY_STEP_MIN]
ns
ns
FINE_SHIFT_RANGE_MAX Maximum guaranteed delay for variable phase shifting
[MAX_STEPS •
DCM_DELAY_STEP_MAX]
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 77 and Table 108.
2. The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM is has no initial fixed phase shifting, i.e., the
PHASE_SHIFT attribute is set to 0.
3. The DCM_DELAY_STEP values are provided at the bottom of Table 105.
Miscellaneous DCM Timing
Table 110: Miscellaneous DCM Timing
Symbol
Description
Min
Max
Units
DCM_RST_PW_MIN(1)
Minimum duration of a RST pulse width
3
-
CLKIN
cycles
DCM_RST_PW_MAX(2)
Maximum duration of a RST pulse width
N/A
N/A
N/A
N/A
seconds
minutes
DCM_CONFIG_LAG_TIME(3)
Maximum duration from VCCINT applied to FPGA configuration
successfully completed (DONE pin goes High) and clocks
applied to DCM DLL
Notes:
1. This limit only applies to applications that use the DCM DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV).
The DCM DFS outputs (CLKFX, CLKFX180) are unaffected.
2. This specification is equivalent to the Virtex-4 DCM_RESET specfication.This specification does not apply for Spartan-3E FPGAs.
3. This specification is equivalent to the Virtex-4 TCONFIG specification. This specification does not apply for Spartan-3E FPGAs.
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Spartan-3E FPGA Family: DC and Switching Characteristics
Configuration and JTAG Timing
General Configuration Power-On/Reconfigure Timing
X-Ref Target - Figure 73
1.2V
2.5V
V
CCINT
1.0V
2.0V
1.0V
(Supply)
V
CCAUX
(Supply)
V
Bank 2
(Supply)
CCO
TPOR
PROG_B
(Input)
TPL
TPROG
INIT_B
(Open-Drain)
TICCK
CCLK
(Output)
DS312-3_01_103105
Notes:
1. The V
, V
, and V
supplies may be applied in any order.
CCO
CCINT CCAUX
2. The Low-going pulse on PROG_B is optional after power-on but necessary for reconfiguration without a power cycle.
3. The rising edge of INIT_B samples the voltage levels applied to the mode pins (M0 - M2).
Figure 73: Waveforms for Power-On and the Beginning of Configuration
Table 111: Power-On Timing and the Beginning of Configuration
All Speed Grades
Symbol
Description
Device
Units
Min
Max
5
(2)
TPOR
The time from the application of VCCINT, VCCAUX, and VCCO
Bank 2 supply voltage ramps (whichever occurs last) to the
rising transition of the INIT_B pin
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
All
-
ms
ms
ms
ms
ms
μs
-
5
-
5
-
5
-
7
TPROG
The width of the low-going pulse on the PROG_B pin
0.5
-
(2)
TPL
The time from the rising edge of the PROG_B pin to the
rising transition on the INIT_B pin
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
All
-
0.5
0.5
1
ms
ms
ms
ms
ms
ns
-
-
-
2
-
2
TINIT
Minimum Low pulse width on INIT_B output
250
0.5
-
(3)
TICCK
The time from the rising edge of the INIT_B pin to the
generation of the configuration clock signal at the CCLK
output pin
All
4.0
μs
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 77. This means power must be applied to all V
, V
,
CCINT CCO
and V
lines.
CCAUX
2. Power-on reset and the clearing of configuration memory occurs during this period.
3. This specification applies only to the Master Serial, SPI, BPI-Up, and BPI-Down modes.
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Spartan-3E FPGA Family: DC and Switching Characteristics
Configuration Clock (CCLK) Characteristics
Table 112: Master Mode CCLK Output Period by ConfigRate Option Setting
ConfigRate
Setting
Temperature
Range
Symbol
Description
Minimum
Maximum
Units
CCLK clock period by
ConfigRate setting
1
Commercial
570
ns
TCCLK1
(power-onvalueand
default value)
1,250
Industrial
Commercial
Industrial
485
285
242
142
121
71.2
60.6
35.5
30.3
17.8
15.1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCCLK3
TCCLK6
TCCLK12
TCCLK25
3
625
313
157
78.2
39.1
Commercial
Industrial
6
Commercial
Industrial
12
25
50
Commercial
Industrial
Commercial
Industrial
TCCLK50
Notes:
1. Set the ConfigRate option value when generating a configuration bitstream. See Bitstream Generator (BitGen) Options in Module 2.
Table 113: Master Mode CCLK Output Frequency by ConfigRate Option Setting
ConfigRate
Setting
Temperature
Range
Symbol
Description
Minimum
Maximum
Units
Equivalent CCLK clock frequency
by ConfigRate setting
1
Commercial
1.8
MHz
FCCLK1
(power-onvalueand
default value)
0.8
Industrial
Commercial
Industrial
2.1
3.6
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
FCCLK3
FCCLK6
FCCLK12
FCCLK25
FCCLK50
3
1.6
3.2
4.2
Commercial
Industrial
7.1
6
8.3
Commercial
Industrial
14.1
16.5
28.1
33.0
56.2
66.0
12
25
50
6.4
Commercial
Industrial
12.8
25.6
Commercial
Industrial
Table 114: Master Mode CCLK Output Minimum Low and High Time
ConfigRate Setting
Symbol
Description
Units
1
3
6
12
25
50
TMCCL,
TMCCH
Master mode CCLK minimum
Low and High time
Commercial
Industrial
276
235
138
117
69
58
34.5
29.3
17.1
14.5
8.5
7.3
ns
ns
Table 115: Slave Mode CCLK Input Low and High Time
Symbol
Description
Min
Max
Units
TSCCL,
TSCCH
CCLK Low and High time
5
∞
ns
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Spartan-3E FPGA Family: DC and Switching Characteristics
Master Serial and Slave Serial Mode Timing
X-Ref Target - Figure 74
PROG_B
(Input)
INIT_B
(Open-Drain)
TMCCH
TSCCH
TMCCL
TSCCL
CCLK
(Input/Output)
TDCC
1/FCCSER
TCCD
DIN
(Input)
Bit n+1
TCCO
Bit n
Bit 0
Bit 1
DOUT
(Output)
Bit n-63
Bit n-64
DS312-3_05_103105
Figure 74: Waveforms for Master Serial and Slave Serial Configuration
Table 116: Timing for the Master Serial and Slave Serial Configuration Modes
All Speed Grades
Slave/
Master
Symbol
Description
Units
Min
Max
Clock-to-Output Times
TCCO
The time from the falling transition on the CCLK pin to data appearing at the
DOUT pin
Both
Both
Both
1.5
10.0
ns
Setup Times
TDCC
The time from the setup of data at the DIN pin to the active edge of the
CCLK pin
11.0
0
-
-
ns
ns
Hold Times
TCCD
The time from the active edge of the CCLK pin to the point when data is last
held at the DIN pin
Clock Timing
TCCH
High pulse width at the CCLK input pin
Master
Slave
Master
Slave
Slave
See Table 114
See Table 115
See Table 114
See Table 115
66(2)
TCCL
Low pulse width at the CCLK input pin
FCCSER
Frequency of the clock signal at the
CCLK input pin
No bitstream compression
With bitstream compression
0
0
MHz
MHz
20
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 77.
2. For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz.
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Spartan-3E FPGA Family: DC and Switching Characteristics
Slave Parallel Mode Timing
X-Ref Target
-
Figure 75
PROG_B
(Input)
INIT_B
(Open-Drain)
TSMCSCC
TSMCCCS
CSI_B
(Input)
TSMCCW
TSMWCC
RDWR_B
(Input)
TMCCH
TSCCH
TMCCL
TSCCL
CCLK
(Input)
1/FCCPAR
Byte n
TSMDCC
TSMCCD
D0 - D7
(Inputs)
Byte 0
Byte 1
Byte n+1
TSMCKBY
TSMCKBY
High-Z
High-Z
BUSY
(Output)
BUSY
DS312-3_02_103105
Notes:
1. It is possible to abort configuration by pulling CSI_B Low in a given CCLK cycle, then switching RDWR_B Low or High in any subsequent
cycle for which CSI_B remains Low. The RDWR_B pin asynchronously controls the driver impedance of the D0 - D7 bus. When RDWR_B
switches High, be careful to avoid contention on the D0 - D7 bus.
Figure 75: Waveforms for Slave Parallel Configuration
Table 117: Timing for the Slave Parallel Configuration Mode
All Speed Grades
Symbol
Description
Units
Min
Max
Clock-to-Output Times
TSMCKBY
The time from the rising transition on the CCLK pin to a signal transition at the BUSY pin
-
12.0
ns
Setup Times
TSMDCC
The time from the setup of data at the D0-D7 pins to the active edge the CCLK pin
Setup time on the CSI_B pin before the active edge of the CCLK pin
Setup time on the RDWR_B pin before active edge of the CCLK pin
11.0
10.0
23.0
-
-
-
ns
ns
ns
TSMCSCC
(2)
TSMCCW
Hold Times
TSMCCD
The time from the active edge of the CCLK pin to the point when data is last held at the
D0-D7 pins
1.0
0
-
-
-
ns
ns
ns
TSMCCCS
TSMWCC
The time from the active edge of the CCLK pin to the point when a logic level is last held
at the CSO_B pin
The time from the active edge of the CCLK pin to the point when a logic level is last held
at the RDWR_B pin
0
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Spartan-3E FPGA Family: DC and Switching Characteristics
Table 117: Timing for the Slave Parallel Configuration Mode (Cont’d)
All Speed Grades
Symbol
Description
Units
Min
Max
Clock Timing
TCCH
The High pulse width at the CCLK input pin
5
5
0
0
0
-
ns
TCCL
The Low pulse width at the CCLK input pin
-
ns
FCCPAR
Frequency of the clock signal No bitstream
Not using the BUSY pin(2)
Using the BUSY pin
50
66
20
MHz
MHz
MHz
at the CCLK input pin
compression
With bitstream compression
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 77.
2. In the Slave Parallel mode, it is necessary to use the BUSY pin when the CCLK frequency exceeds this maximum specification.
3. Some Xilinx documents refer to Parallel modes as “SelectMAP” modes.
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Spartan-3E FPGA Family: DC and Switching Characteristics
Serial Peripheral Interface (SPI) Configuration Timing
X-Ref Target - Figure 76
PROG_B
(Input)
HSWAP
(Input)
HSWAP must be stable before INIT_B goes High and constant throughout the configuration process.
VS[2:0]
(Input)
<1:1:1>
Mode input pins M[2:0] and variant select input pins VS[2:0] are sampled when INIT_B
goes High. After this point, input values do not matter until DONE goes High, at which
point these pins become user-I/O pins.
M[2:0]
(Input)
<0:0:1>
TMINIT
TINITM
INIT_B
(Open-Drain)
New ConfigRate active
TCCLK
TMCCH
T
n
MCCL
n
TMCCL1 TMCCH1
T
TCCLK1
CCLK1
n
CCLK
TV
DIN
(Input)
Data
Data
TDCC
Data
Data
TCSS
TCCD
CSO_B
MOSI
TCCO
Command Command
(msb) (msb-1)
TDSU
TDH
Pin initially pulled High by internal pull-up resistor if HSWAP input is Low.
Pin initially high-impedance (Hi-Z) if HSWAP input is High. External pull-up resistor required on CSO_B.
ds312-3_06_110206
Shaded values indicate specifications on attached SPI Flash PROM.
Figure 76: Waveforms for Serial Peripheral Interface (SPI) Configuration
Table 118: Timing for Serial Peripheral Interface (SPI) Configuration Mode
Symbol Description
TCCLK1
Minimum
See Table 112
See Table 112
50
Maximum
Units
Initial CCLK clock period
TCCLKn
TMINIT
TINITM
TCCO
CCLK clock period after FPGA loads ConfigRate setting
Setup time on VS[2:0] and M[2:0] mode pins before the rising edge of INIT_B
Hold time on VS[2:0] and M[2:0]mode pins after the rising edge of INIT_B
MOSI output valid after CCLK edge
-
-
ns
ns
0
See Table 116
See Table 116
See Table 116
TDCC
Setup time on DIN data input before CCLK edge
TCCD
Hold time on DIN data input after CCLK edge
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Spartan-3E FPGA Family: DC and Switching Characteristics
Table 119: Configuration Timing Requirements for Attached SPI Serial Flash
Symbol Description
TCCS SPI serial Flash PROM chip-select time
Requirement
Units
ns
TCCS ≤ TMCCL1 – TCCO
TDSU
TDH
SPI serial Flash PROM data input setup time
SPI serial Flash PROM data input hold time
SPI serial Flash PROM data clock-to-output time
ns
ns
TDSU ≤ TMCCL1 – TCCO
TDH ≤ TMCCH 1
TV
ns
TV ≤ TMCCLn – TDCC
fC or fR
Maximum SPI serial Flash PROM clock frequency (also depends on
specific read command used)
MHz
1
fC ≥ ------------------------------
TCCLKn(min)
Notes:
1. These requirements are for successful FPGA configuration in SPI mode, where the FPGA provides the CCLK frequency. The post
configuration timing can be different to support the specific needs of the application loaded into the FPGA and the resulting clock source.
2. Subtract additional printed circuit board routing delay as required by the application.
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Spartan-3E FPGA Family: DC and Switching Characteristics
Byte Peripheral Interface (BPI) Configuration Timing
X-Ref Target - Figure 77
PROG_B
(Input)
HSWAP
HSWAP must be stable before INIT_B goes High and constant throughout the configuration process.
Mode input pins M[2:0] are sampled when INIT_B goes High. After this point,
(Input)
M[2:0]
(Input)
<0:1:0>
input values do not matter until DONE goes High, at which point the mode pins
become user-I/O pins.
TMINIT
TINITM
INIT_B
(Open-Drain)
Pin initially pulled High by internal pull-up resistor if HSWAP input is Low.
Pin initially high-impedance (Hi-Z) if HSWAP input is High.
LDC[2:0]
HDC
CSO_B
New ConfigRate active
TCCLK1
TCCLKn
TINITADDR
TCCLK1
CCLK
TCCO
000_0000
Address
Address Address
TCCD
A[23:0]
000_0001
T
TDCC
Data
AVQV
D[7:0]
(Input)
Byte 0
Data
Data
Data
Byte 1
Shaded values indicate specifications on attached parallel NOR Flash PROM.
DS312-3_08_032409
Figure 77: Waveforms for Byte-wide Peripheral Interface (BPI) Configuration (BPI-DN mode shown)
Table 120: Timing for Byte-wide Peripheral Interface (BPI) Configuration Mode
Symbol
TCCLK1
TCCLKn
TMINIT
Description
Minimum
Maximum
See Table 112
See Table 112
-
Units
Initial CCLK clock period
CCLK clock period after FPGA loads ConfigRate setting
Setup time on CSI_B, RDWR_B, and M[2:0] mode pins before the rising edge of
INIT_B
50
0
ns
ns
TINITM
Hold time on CSI_B, RDWR_B, and M[2:0] mode pins after the rising edge of
INIT_B
-
TINITADDR
Minimum period of initial A[23:0] address cycle; LDC[2:0]
and HDC are asserted and valid
BPI-UP:
(M[2:0] = <0:1:0>)
5
5
2
TCCLK1
cycles
BPI-DN:
2
(M[2:0] = <0:1:1>)
TCCO
TDCC
TCCD
Address A[23:0] outputs valid after CCLK falling edge
Setup time on D[7:0] data inputs before CCLK rising edge
Hold time on D[7:0] data inputs after CCLK rising edge
See Table 116
See Table 116
See Table 116
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Spartan-3E FPGA Family: DC and Switching Characteristics
Table 121: Configuration Timing Requirements for Attached Parallel NOR Flash
Symbol
TCE (tELQV
Description
Requirement
Units
)
Parallel NOR Flash PROM chip-select
time
ns
TCE ≤ TINITADDR
TOE (tGLQV
ACC (tAVQV
TBYTE (tFLQV, FHQV
)
Parallel NOR Flash PROM
output-enable time
ns
ns
ns
TOE ≤ TINITADDR
TACC ≤ 0.5TCCLKn(min) – TCCO – TDCC – PCB
TBYTE ≤ TINITADDR
T
)
Parallel NOR Flash PROM read
access time
t
) For x8/x16 PROMs only: BYTE# to
output valid time(3)
Notes:
1. These requirements are for successful FPGA configuration in BPI mode, where the FPGA provides the CCLK frequency. The post
configuration timing can be different to support the specific needs of the application loaded int o the FPGA and the resulting clock source.
2. Subtract additional printed circuit board routing delay as required by the application.
3. The initial BYTE# timing can be extended using an external, appropriately sized pull-down resistor on the FPGA’s LDC2 pin. The resistor
value also depends on whether the FPGA’s HSWAP pin is High or Low.
Table 122: MultiBoot Trigger (MBT) Timing
Symbol
Description
Minimum
Maximum
Units
TMBT
MultiBoot Trigger (MBT) Low pulse width required to initiate MultiBoot
reconfiguration
300
∞
ns
Notes:
1. MultiBoot re-configuration starts on the rising edge after MBT is Low for at least the prescribed minimum period.
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Spartan-3E FPGA Family: DC and Switching Characteristics
IEEE 1149.1/1532 JTAG Test Access Port Timing
X-Ref Target - Figure 78
TCCH
TCCL
TCK
(Input)
1/FTCK
TTCKTMS
TTMSTCK
TMS
(Input)
TTDITCK
TTCKTDI
TDI
(Input)
TTCKTDO
TDO
(Output)
DS312-3_79_032409
Figure 78: JTAG Waveforms
Table 123: Timing for the JTAG Test Access Port
All Speed Grades
Min Max
Symbol
Description
Units
Clock-to-Output Times
TTCKTDO
The time from the falling transition on the TCK pin to
data appearing at the TDO pin
1.0
11.0
ns
Setup Times
TTDITCK
The time from the setup of data at the TDI pin to the
rising transition at the TCK pin
7.0
7.0
-
-
ns
ns
TTMSTCK
The time from the setup of a logic level at the TMS pin
to the rising transition at the TCK pin
Hold Times
TTCKTDI
The time from the rising transition at the TCK pin to the
point when data is last held at the TDI pin
0
0
-
-
ns
ns
TTCKTMS
The time from the rising transition at the TCK pin to the
point when a logic level is last held at the TMS pin
Clock Timing
TCCH
The High pulse width at the TCK pin
The Low pulse width at the TCK pin
Frequency of the TCK signal
5
5
-
-
-
ns
ns
TCCL
FTCK
30
MHz
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 77.
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Spartan-3E FPGA Family: DC and Switching Characteristics
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revision
03/01/2005
11/23/2005
03/22/2006
Initial Xilinx release.
2.0
Added AC timing information and additional DC specifications.
3.0
Upgraded data sheet status to Preliminary. Finalized production timing parameters. All speed grades
for all Spartan-3E FPGAs are now Production status using the v1.21 speed files, as shown in Table 84.
Expanded description in Note 2, Table 78. Updated pin-to-pin and clock-to-output timing based on final
characterization, shown in Table 86. Updated system-synchronous input setup and hold times based
on final characterization, shown in Table 87 and Table 88. Updated other I/O timing in Table 90.
Provided input and output adjustments for LVPECL_25, DIFF_SSTL and DIFF_HSTL I/O standards
that supersede the v1.21 speed file values, in Table 91 and Table 94. Reduced I/O three-state and
set/reset delays in Table 93. Added XC3S100E FPGA in CP132 package to Table 96. Increased TAS
slice flip-flop timing by 100 ps in Table 98. Updated distributed RAM timing in Table 99 and SRL16
timing in Table 100. Updated global clock timing, removed left/right clock buffer limits in Table 101.
Updated block RAM timing in Table 103. Added DCM parameters for remainder of Step 0 device;
added improved Step 1 DCM performance to Table 104, Table 105, Table 106, and Table 107. Added
minimum INIT_B pulse width specification, TINIT, in Table 111. Increased data hold time for Slave
Parallel mode to 1.0 ns (TSMCCD) in Table 117. Improved the DCM performance for the XC3S1200E,
Stepping 0 in Table 104, Table 105, Table 106, and Table 107. Corrected links in Table 118 and
Table 120. Added MultiBoot timing specifications to Table 122.
04/07/2006
05/19/2006
3.1
3.2
Improved SSO limits for LVDS_25, MINI_LVDS_25, and RSDS_25 I/O standards in the QFP packages
(Table 97). Removed potentially confusing Note 2 from Table 78.
Clarified that 100 mV of hysteresis applies to LVCMOS33 and LVCMOS25 I/O standards (Note 4,
Table 80). Other minor edits.
05/30/2006
11/09/2006
3.2.1
3.4
Corrected various typos and incorrect links.
Improved absolute maximum voltage specifications in Table 73, providing additional overshoot
allowance. Widened the recommended voltage range for PCI and PCI-X standards in Table 80.
Clarified Note 2, Table 83. Improved various timing specifications for v1.26 speed file. Added Table 85
to summarize the history of speed file releases after which time all devices became Production status.
Added absolute minimum values for Table 86, Table 92, and Table 93. Updated pin-to-pin setup and
hold timing based on default IFD_DELAY_VALUE settings in Table 87, Table 88, and Table 90. Added
Table 89 about source-synchronous input capture sample window. Promoted Module 3 to Production
status. Synchronized all modules to v3.4.
03/16/2007
05/29/2007
3.5
3.6
Based on extensive 90 nm production data, improved (reduced) the maximum quiescent current limits
for the ICCINTQ, ICCAUXQ, and ICCOQ specifications in Table 79 by an average of 50%.
Added note to Table 74 and Table 75 regarding HSWAP in step 0 devices. Updated tRPW_CLB in
Table 98 to match value in speed file. Improved CLKOUT_FREQ_CLK90 to 200 MHz for Stepping 1 in
Table 105.
04/18/2008
3.7
Clarified that Stepping 0 was offered only for -4C and removed Stepping 0 -5 specifications. Added
reference to XAPP459 in Table 73 and Table 77. Improved recommended max VCCO to 3.465V (3.3V
+ 5%) in Table 77. Removed minimum input capacitance from Table 78. Updated Recommended
Operating Conditions for LVCMOS and PCI I/O standards in Table 80. Removed Absolute Minimums
from Table 86, Table 92 and Table 93 and added footnote recommending use of Timing Analyzer for
minimum values. Updated TPSFD and TPHFD in Table 87 to match current speed file. Update TRPW_IOB
in Table 88 to match current speed file and CLB equivalent spec. Added XC3S500E VQG100 to
Table 96. Replaced TMULCKID with TMSCKD for A, B, and P registers in Table 102. Updated
CLKOUT_PER_JITT_FX in Table 107. Updated MAX_STEPS equation in Table 109. Updated
Figure 77 and Table 120 to correct CCLK active edge. Updated links.
08/26/2009
3.8
Added reference to XAPP459 in Table 73 note 2. Updated BPI timing in Figure 77, Table 119, and
Table 120. Removed VREF requirements for differential HSTL and differential SSTL in Table 95. Added
Spread Spectrum paragraph. Revised hold times for TIOICKPD in Table 88 and setup times for TDICK in
Table 98. Added note 4 to Table 106 and note 3 to Table 107, and updated note 6 for Table 107 to add
input jitter.
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Spartan-3E FPGA Family: DC and Switching Characteristics
Revision
Date
Version
10/29/2012
4.0
Added Notice of Disclaimer. This product is not recommended for new designs.
Revised note 2 in Table 73. Revised note 2 and VIN description in Table 77, and added note 5. Added
note 3 to Table 78.
07/19/2013
4.1
Removed banner. This product IS recommended for new designs.
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED
WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE
SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
CRITICAL APPLICATIONS DISCLAIMER
XILINX PRODUCTS (INCLUDING HARDWARE, SOFTWARE AND/OR IP CORES) ARE NOT DESIGNED OR INTENDED TO BE
FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS IN LIFE-SUPPORT OR
SAFETY DEVICES OR SYSTEMS, CLASS III MEDICAL DEVICES, NUCLEAR FACILITIES, APPLICATIONS RELATED TO THE
DEPLOYMENT OF AIRBAGS, OR ANY OTHER APPLICATIONS THAT COULD LEAD TO DEATH, PERSONAL INJURY OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE (INDIVIDUALLY AND COLLECTIVELY, “CRITICAL APPLICATIONS”). FURTHERMORE,
XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN ANY APPLICATIONS THAT AFFECT CONTROL OF A
VEHICLE OR AIRCRAFT, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF
SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE
OPERATOR. CUSTOMER AGREES, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE XILINX
PRODUCTS, TO THOROUGHLY TEST THE SAME FOR SAFETY PURPOSES. TO THE MAXIMUM EXTENT PERMITTED BY
APPLICABLE LAW, CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN CRITICAL
APPLICATIONS.
AUTOMOTIVE APPLICATIONS DISCLAIMER
XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING
FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A
VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN
THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III)
USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY
USE OF XILINX PRODUCTS IN SUCH APPLICATIONS.
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227
Spartan-3E FPGA Family:
Pinout Descriptions
DS312 (v4.1) July 19, 2013
Product Specification
Introduction
Pin Types
This section describes the various pins on a Spartan®-3E
FPGA and how they connect within the supported
component packages.
Most pins on a Spartan-3E FPGA are general-purpose,
user-defined I/O pins. There are, however, up to 11 different
functional types of pins on Spartan-3E packages, as
outlined in Table 124. In the package footprint drawings that
follow, the individual pins are color-coded according to pin
type as in the table.
Table 124: Types of Pins on Spartan-3E FPGAs
Type / Color
Description
Code
Pin Name(s) in Type(1)
I/O
Unrestricted, general-purpose user-I/O pin. Most pins can be paired together to form IO
differential I/Os.
IO_Lxxy_#
INPUT
DUAL
Unrestricted, general-purpose input-only pin. This pin does not have an output
structure, differential termination resistor, or PCI clamp diode.
IP
IP_Lxxy_#
Dual-purpose pin used in some configuration modes during the configuration
process and then usually available as a user I/O after configuration. If the pin is not HSWAP
M[2:0]
used during configuration, this pin behaves as an I/O-type pin. Some of the
dual-purpose pins are also shared with bottom-edge global (GCLK) or right-half
(RHCLK) clock inputs. See the Configuration section in Module 2 for additional
information on these signals.
CCLK
MOSI/CSI_B
D[7:1]
D0/DIN
CSO_B
RDWR_B
BUSY/DOUT
INIT_B
A[23:20]
A19/VS2
A18/VS1
A17/VS0
A[16:0]
LDC[2:0]
HDC
VREF
CLK
Dual-purpose pin that is either a user-I/O pin or Input-only pin, or, along with all other IP/VREF_#
VREF pins in the same bank, provides a reference voltage input for certain I/O
standards. If used for a reference voltage within a bank, all VREF pins within the
bank must be connected.
IP_Lxxy_#/VREF_#
IO/VREF_#
IO_Lxxy_#/VREF_#
Either a user-I/O pin or Input-only pin, or an input to a specific clock buffer driver.
IO_Lxxy_#/GCLK[15:10, 7:2]
Every package has 16 global clock inputs that optionally clock the entire device. The IP_Lxxy_#/GCLK[9:8, 1:0]
RHCLK inputs optionally clock the right-half of the device. The LHCLK inputs IO_Lxxy_#/LHCLK[7:0]
optionally clock the left-half of the device. Some of the clock pins are shared with the IO_Lxxy_#/RHCLK[7:0]
dual-purpose configuration pins and are considered DUAL-type. See the Clocking
Infrastructure section in Module 2 for additional information on these signals.
CONFIG
Dedicated configuration pin. Not available as a user-I/O pin. Every package has two DONE, PROG_B
dedicated configuration pins. These pins are powered by VCCAUX. See the
Configuration section in Module 2 for details.
JTAG
GND
Dedicated JTAG pin. Not available as a user-I/O pin. Every package has four
dedicated JTAG pins. These pins are powered by VCCAUX.
TDI, TMS, TCK, TDO
Dedicated ground pin. The number of GND pins depends on the package used. All GND
must be connected.
© Copyright 2005–2013 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, Artix, Kintex, Zynq, Vivado, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
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Spartan-3E FPGA Family: Pinout Descriptions
Pin Name(s) in Type(1)
Table 124: Types of Pins on Spartan-3E FPGAs (Cont’d)
Type / Color
Description
Code
VCCAUX
VCCINT
VCCO
N.C.
Dedicated auxiliary power supply pin. The number of VCCAUX pins depends on the VCCAUX
package used. All must be connected to +2.5V. See the Powering Spartan-3E
FPGAs section in Module 2 for details.
Dedicated internal core logic power supply pin. The number of VCCINT pins
depends on the package used. All must be connected to +1.2V. See the Powering
Spartan-3E FPGAs section in Module 2 for details.
VCCINT
Along with all the other VCCO pins in the same bank, this pin supplies power to the VCCO_#
output buffers within the I/O bank and sets the input threshold voltage for some I/O
standards. See the Powering Spartan-3E FPGAs section in Module 2 for details.
This package pin is not connected in this specific device/package combination but N.C.
may be connected in larger devices in the same package.
Notes:
1. # = I/O bank number, an integer between 0 and 3.
2. IRDY/TRDY designations are for PCI designs; refer to PCI documentation for details.
‘L’ indicates that the pin is part of a differential pair.
Differential Pair Labeling
‘xx’ is a two-digit integer, unique for each bank, that
identifies a differential pin-pair.
I/Os with Lxxy_# are part of a differential pair. ‘L’ indicates
differential capability. The ‘xx’ field is a two-digit integer,
unique to each bank that identifies a differential pin-pair.
The ‘y’ field is either ‘P’ for the true signal or ‘N’ for the
inverted signal in the differential pair. The ‘#’ field is the I/O
bank number.
‘y’ is replaced by ‘P’ for the true signal or ‘N’ for the
inverted. These two pins form one differential pin-pair.
‘#’ is an integer, 0 through 3, indicating the associated
I/O bank.
The pin name suffix has the following significance.
Figure 79 provides a specific example showing a differential
input to and a differential output from Bank 1.
X-Ref Target - Figure 79
Pair Number
Bank Number
IO_L38P_1
Bank 0
IO_L38N_1
True Receiver
IO_L39P_1
Positive Polarity
Spartan-3E
FPGA
IO_L39N_1
Negative Polarity
Inverted Receiver
Bank 2
DS312-4_00_032409
Figure 79: Differential Pair Labeling
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Spartan-3E FPGA Family: Pinout Descriptions
packages are similar, as shown in the mechanical drawings
provided in Table 127.
Package Overview
Table 125 shows the eight low-cost, space-saving
production package styles for the Spartan-3E family. Each
package style is available as a standard and an
environmentally friendly lead-free (Pb-free) option. The
Pb-free packages include an extra ‘G’ in the package style
name. For example, the standard “VQ100” package
becomes “VQG100” when ordered as the Pb-free option.
The mechanical dimensions of the standard and Pb-free
Not all Spartan-3E densities are available in all packages.
For a specific package, however, there is a common
footprint that supports all the devices available in that
package. See the footprint diagrams that follow.
For additional package information, see UG112: Device
Package User Guide.
Table 125: Spartan-3E Family Package Options
Lead
Pitch
(mm)
Maximum
I/O
Footprint
Area (mm)
Height
(mm)
Mass(1)
(g)
Package
Leads
Type
VQ100 / VQG100
CP132 / CPG132
TQ144 / TQG144
PQ208 / PQG208
FT256 / FTG256
FG320 / FGG320
FG400 / FGG400
FG484 / FGG484
100
132
144
208
256
320
400
484
Very-thin Quad Flat Pack (VQFP)
Chip-Scale Package (CSP)
66
0.5
0.5
0.5
0.5
1.0
1.0
1.0
1.0
16 x 16
8.1 x 8.1
22 x 22
1.20
1.10
1.60
4.10
1.55
2.00
2.43
2.60
0.6
0.1
1.4
5.3
0.9
1.4
2.2
2.2
92
Thin Quad Flat Pack (TQFP)
108
158
190
250
304
376
Plastic Quad Flat Pack (PQFP)
Fine-pitch, Thin Ball Grid Array (FBGA)
Fine-pitch Ball Grid Array (FBGA)
Fine-pitch Ball Grid Array (FBGA)
Fine-pitch Ball Grid Array (FBGA)
30.6 x 30.6
17 x 17
19 x 19
21 x 21
23 x 23
Notes:
1. Package mass is 10%.
packages are superior in almost every other aspect, as
summarized in Table 126. Consequently, Xilinx
recommends using BGA packaging whenever possible.
Selecting the Right Package Option
Spartan-3E FPGAs are available in both quad-flat pack
(QFP) and ball grid array (BGA) packaging options. While
QFP packaging offers the lowest absolute cost, the BGA
Table 126: QFP and BGA Comparison
Characteristic
Quad Flat Pack (QFP)
Ball Grid Array (BGA)
Maximum User I/O
158
Good
Fair
376
Better
Better
Better
Better
4-6
Packing Density (Logic/Area)
Signal Integrity
Simultaneous Switching Output (SSO) Support
Thermal Dissipation
Fair
Fair
Minimum Printed Circuit Board (PCB) Layers
Hand Assembly/Rework
4
Possible
Difficult
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Spartan-3E FPGA Family: Pinout Descriptions
Material Declaration Data Sheets (MDDS) are also
available on the Xilinx web site for each package.
Mechanical Drawings
Detailed mechanical drawings for each package type are
available from the Xilinx® web site at the specified location
in Table 127.
Table 127: Xilinx Package Mechanical Drawings and Material Declaration Data Sheets
Package Package Drawing
Package Drawing
MDDS
VQ100
PK173_VQ100
PK130_VQG100
PK147_CP132
PK101_CPG132
PK169_TQ144
PK126_TQG144
PK166_PQ208
PK123_PQG208
PK158_FT256
PK115_FTG256
PK152_FG320
PK106_FGG320
PK182_FG400
PK108_FGG400
PK183_FG484
PK110_FGG484
VQG100
CP132
Package Drawing
Package Drawing
Package Drawing
Package Drawing
Package Drawing
Package Drawing
Package Drawing
CPG132
TQ144
TQG144
PQ208
PQG208
FT256
FTG256
FG320
FGG320
FG400
FGG400
FG484
FGG484
CLK-type pins are used as general-purpose I/O. Likewise,
the table shows the maximum number of differential
pin-pairs available on the package. Finally, the table shows
how the total maximum user-I/Os are distributed by pin type,
including the number of unconnected—i.e., N.C.—pins on
the device.
Package Pins by Type
Each package has three separate voltage supply
inputs—VCCINT, VCCAUX, and VCCO—and a common
ground return, GND. The numbers of pins dedicated to
these functions vary by package, as shown in Table 128.
Table 128: Power and Ground Supply Pins by Package
Package
VQ100
CP132
TQ144
PQ208
FT256
VCCINT
VCCAUX
VCCO
8
GND
12
4
6
4
4
8
16
4
4
9
13
4
8
12
16
20
24
28
20
8
8
28
FG320
FG400
FG484
8
8
28
16
16
8
42
10
48
A majority of package pins are user-defined I/O or input
pins. However, the numbers and characteristics of these I/O
depend on the device type and the package in which it is
available, as shown in Table 129. The table shows the
maximum number of single-ended I/O pins available,
assuming that all I/O-, INPUT-, DUAL-, VREF-, and
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Spartan-3E FPGA Family: Pinout Descriptions
Table 129: Maximum User I/O by Package
Maximum
All Possible I/Os by Type
(2)
Maximum
Input-
Only
Maximum
Differential
Pairs
User I/Os
and
Device
Package
VQ100
CP132
I/O
INPUT
DUAL VREF(1)
N.C.
CLK
Input-Only
XC3S100E
XC3S250E
XC3S500E
XC3S100E
XC3S250E
XC3S500E
XC3S100E
XC3S250E
XC3S250E
XC3S500E
XC3S250E
XC3S500E
XC3S1200E
XC3S500E
XC3S1200E
XC3S1600E
XC3S1200E
XC3S1600E
XC3S1600E
66
66
7
30
30
30
35
41
41
40
40
65
65
68
77
77
92
99
99
124
124
156
16
16
1
21
21
21
42
46
46
42
42
46
46
46
46
46
46
46
46
46
46
46
4
4
24
24
24
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
0
0
7
1
66
7
16
1
4
0
83
11
7
16
2
7
9
92
22
0
8
0
92
7
22
0
8
0
108
108
158
158
172
190
190
232
250
250
304
304
376
28
28
32
32
40
41
40
56
56
56
72
72
82
22
19
21
25
25
33
33
31
48
47
47
62
62
72
9
0
TQ144
PQ208
20
9
0
58
13
13
15
19
19
20
21
21
24
24
28
0
58
0
62
18
0
FT256
FG320
76
78
0
102
120
120
156
156
214
18
0
0
0
FG400
FG484
0
0
Notes:
1. Some VREF pins are on INPUT pins. See pinout tables for details.
2. All devices have 24 possible global clock and right- and left-half side clock inputs. The right-half and bottom-edge clock pins have shared
functionality in some FPGA configuration modes. Consequently, some clock pins are counted in the DUAL column. 4 GCLK pins, including
2 DUAL pins, are on INPUT pins.
Electronic versions of the package pinout tables and foot-
prints are available for download from the Xilinx website.
Download the files from the following location:
http://www.xilinx.com/support/documentation/data_sheets
/s3e_pin.zip
Using a spreadsheet program, the data can be sorted and
reformatted according to any specific needs. Similarly, the
ASCII-text file is easily parsed by most scripting programs.
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Spartan-3E FPGA Family: Pinout Descriptions
package body (case) and the die junction temperature per
Package Thermal Characteristics
watt of power consumption. The junction-to-board (θ )
JB
The power dissipated by an FPGA application has
implications on package selection and system design. The
power consumed by a Spartan-3E FPGA is reported using
either the XPower Estimator or the XPower Analyzer
calculator integrated in the Xilinx ISE® development
software. Table 130 provides the thermal characteristics for
the various Spartan-3E package offerings.
value similarly reports the difference between the board and
junction temperature. The junction-to-ambient (θ ) value
JA
reports the temperature difference per watt between the
ambient environment and the junction temperature. The θ
JA
value is reported at different air velocities, measured in
linear feet per minute (LFM). The Still Air (0 LFM) column
shows the θ value in a system without a fan. The thermal
JA
resistance drops with increasing air flow.
The junction-to-case thermal resistance (θ ) indicates the
JC
difference between the temperature measured on the
Table 130: Spartan-3E Package Thermal Characteristics
Junction-to-Ambient (θJA
)
at Different Air Flows
Junction-to-Case Junction-to-Board
Device
Package
Units
(θJC
)
(θJB)
Still Air
(0 LFM)
250 LFM
500 LFM
750 LFM
XC3S100E
XC3S250E
XC3S500E
XC3S100E
XC3S250E
XC3S500E
XC3S100E
XC3S250E
XC3S250E
XC3S500E
XC3S250E
XC3S500E
XC3S1200E
XC3S500E
XC3S1200E
XC3S1600E
XC3S1200E
XC3S1600E
XC3S1600E
13.0
11.0
9.8
30.9
25.9
49.0
43.3
40.0
62.1
48.3
41.5
52.1
37.6
37.0
36.1
35.8
31.1
26.2
26.1
23.0
21.1
22.3
20.3
18.8
40.7
36.0
33.3
55.3
41.8
35.2
40.5
29.2
27.3
26.6
29.3
25.0
20.5
20.6
17.7
15.9
17.2
15.2
12.5
37.9
33.6
31.0
52.8
39.5
32.9
34.6
25.0
24.1
23.6
28.4
24.0
19.3
19.4
16.4
14.6
16.0
14.0
11.3
37.0
32.7
30.2
51.2
38.0
31.5
32.5
23.4
22.4
21.8
28.1
23.6
18.9
18.6
15.7
13.8
15.3
13.3
10.8
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
VQ100
CP132
19.3
11.8
8.5
42.0
28.1
21.3
31.9
25.7
29.0
26.8
27.7
22.2
16.4
15.6
12.5
10.6
12.4
10.4
9.4
8.2
TQ144
PQ208
7.2
9.8
8.5
12.4
9.6
FT256
FG320
6.5
9.8
8.2
7.1
7.5
FG400
FG484
6.0
5.7
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162
Spartan-3E FPGA Family: Pinout Descriptions
VQ100: 100-lead Very-thin Quad Flat Package
The XC3S100E, XC3S250E, and the XC3S500E devices
are available in the 100-lead very-thin quad flat package,
VQ100. All devices share a common footprint for this
package as shown in Table 131 and Figure 80.
Table 131: VQ100 Package Pinout (Cont’d)
XC3S100E
VQ100
XC3S250E
XC3S500E
Pin Name
Bank
Pin
Number
Type
Table 131 lists all the package pins. They are sorted by
bank number and then by pin name. Pins that form a
differential I/O pair appear together in the table. The table
also shows the pin number for each pin and the pin type, as
defined earlier.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO_L02P_1
P57
P61
P60
P63
P62
P66
P65
P68
P67
P71
P70
P69
P55
P73
P34
P42
P25
P24
P27
P26
P33
P32
P36
P35
P41
P40
P44
P43
P48
P47
P50
P49
P30
P39
P38
I/O
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
I/O
IO_L03N_1/RHCLK1
IO_L03P_1/RHCLK0
IO_L04N_1/RHCLK3
IO_L04P_1/RHCLK2
IO_L05N_1/RHCLK5
IO_L05P_1/RHCLK4
IO_L06N_1/RHCLK7
IO_L06P_1/RHCLK6
IO_L07N_1
The VQ100 package does not support the Byte-wide
Peripheral Interface (BPI) configuration mode.
Consequently, the VQ100 footprint has fewer DUAL-type
pins than other packages.
An electronic version of this package pinout table and
footprint diagram is available for download from the Xilinx
web site at:
IO_L07P_1
I/O
http://www.xilinx.com/support/documentation/data_sheets
/s3e_pin.zip
IP/VREF_1
VREF
VCCO_1
VCCO
VCCO_1
VCCO
Pinout Table
IO/D5
DUAL
Table 131 shows the pinout for production Spartan-3E
FPGAs in the VQ100 package.
IO/M1
DUAL
IO_L01N_2/INIT_B
IO_L01P_2/CSO_B
IO_L02N_2/MOSI/CSI_B
IO_L02P_2/DOUT/BUSY
IO_L03N_2/D6/GCLK13
IO_L03P_2/D7/GCLK12
IO_L04N_2/D3/GCLK15
IO_L04P_2/D4/GCLK14
IO_L06N_2/D1/GCLK3
IO_L06P_2/D2/GCLK2
IO_L07N_2/DIN/D0
IO_L07P_2/M0
DUAL
Table 131: VQ100 Package Pinout
DUAL
XC3S100E
VQ100
DUAL
XC3S250E
DUAL
Bank
Pin
Type
XC3S500E
Pin Name
Number
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
IO
P92
P79
P78
P84
P83
P86
P85
P91
P90
P95
P94
P99
P98
P89
P88
P82
P97
P54
P53
P58
I/O
I/O
IO_L01N_0
IO_L01P_0
I/O
IO_L02N_0/GCLK5
IO_L02P_0/GCLK4
IO_L03N_0/GCLK7
IO_L03P_0/GCLK6
IO_L05N_0/GCLK11
IO_L05P_0/GCLK10
IO_L06N_0/VREF_0
IO_L06P_0
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
VREF
I/O
DUAL
IO_L08N_2/VS1
DUAL
IO_L08P_2/VS2
DUAL
IO_L09N_2/CCLK
IO_L09P_2/VS0
DUAL
DUAL
IP/VREF_2
VREF
IO_L07N_0/HSWAP
IO_L07P_0
DUAL
I/O
IP_L05N_2/M2/GCLK1
DUAL/GCLK
DUAL/GCLK
IP_L05P_2/RDWR_B/
GCLK0
IP_L04N_0/GCLK9
IP_L04P_0/GCLK8
VCCO_0
GCLK
GCLK
VCCO
VCCO
I/O
2
2
3
3
3
VCCO_2
P31
P45
P3
VCCO
VCCO
I/O
VCCO_2
VCCO_0
IO_L01N_3
IO_L01P_3
IO_L02N_3/VREF_3
IO_L01N_1
P2
I/O
IO_L01P_1
I/O
P5
VREF
IO_L02N_1
I/O
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163
Spartan-3E FPGA Family: Pinout Descriptions
Table 131: VQ100 Package Pinout (Cont’d)
XC3S100E
VQ100
XC3S250E
Bank
Pin
Type
XC3S500E
Pin Name
Number
3
3
IO_L02P_3
P4
P10
P9
I/O
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
I/O
IO_L03N_3/LHCLK1
3
IO_L03P_3/LHCLK0
3
IO_L04N_3/LHCLK3
P12
P11
P16
P15
P18
P17
P23
P22
P13
P8
3
IO_L04P_3/LHCLK2
3
IO_L05N_3/LHCLK5
3
IO_L05P_3/LHCLK4
3
IO_L06N_3/LHCLK7
3
IO_L06P_3/LHCLK6
IO_L07N_3
IO_L07P_3
IP
3
3
I/O
3
INPUT
VCCO
VCCO
GND
3
VCCO_3
VCCO_3
GND
3
P20
P7
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
P14
P19
P29
P37
P52
P59
P64
P72
P81
P87
P93
P51
P1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCCAUX DONE
VCCAUX PROG_B
VCCAUX TCK
CONFIG
CONFIG
JTAG
P77
P100
P76
P75
P21
P46
P74
P96
P6
VCCAUX TDI
JTAG
VCCAUX TDO
JTAG
VCCAUX TMS
JTAG
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
P28
P56
P80
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164
Spartan-3E FPGA Family: Pinout Descriptions
User I/Os by Bank
Table 132 indicates how the 66 available user-I/O pins are
distributed between the four I/O banks on the VQ100
package.
Table 132: User I/Os Per Bank for XC3S100E, XC3S250E, and XC3S500E in the VQ100 Package
All Possible I/O Pins by Type
Package
Edge
Maximum
I/O
I/O Bank
(2)
I/O
5
INPUT
DUAL
VREF(1)
CLK
Top
0
1
2
3
15
15
19
17
66
0
0
0
1
1
1
0
1
1
1
1
4
8
8
Right
6
Bottom
Left
0
18
2
0(2)
8
5
TOTAL
16
21
24
Notes:
1. Some VREF and CLK pins are on INPUT pins.
2. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
Footprint Migration Differences
The production XC3S100E, XC3S250E, and XC3S500E
FPGAs have identical footprints in the VQ100 package.
Designs can migrate between the devices without further
consideration.
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165
Spartan-3E FPGA Family: Pinout Descriptions
VQ100 Footprint
In Figure 80, note pin 1 indicator in top-left corner and logo
orientation.
X-Ref Target - Figure 80
PROG_B
IO_L01P_3
1
2
75 TMS
74 VCCAUX
Bank 0
IO_L01N_3
IO_L02P_3
3
4
5
6
7
8
9
73 VCCO_1
72 GND
IO_L02N_3/VREF_3
VCCINT
71 IO_L07N_1
70 IO_L07P_1
GND
69 IP/VREF_1
VCCO_3
68 IO_L06N_1/RHCLK7
67 IO_L06P_1/RHCLK6
66 IO_L05N_1/RHCLK5
65 IO_L05P_1/RHCLK4
64 GND
IO_L03P_3/LHCLK0
IO_L03N_3/LHCLK1 10
IO_L04P_3/LHCLK2 11
IO_L04N_3/LHCLK3 12
IP 13
63 IO_L04N_1/RHCLK3
62 IO_L04P_1/RHCLK2
61 IO_L03N_1/RHCLK1
60 IO_L03P_1/RHCLK0
59 GND
GND 14
IO_L05P_3/LHCLK4 15
IO_L05N_3/LHCLK5 16
IO_L06P_3/LHCLK6 17
IO_L06N_3/LHCLK7 18
GND 19
58 IO_L02N_1
57 IO_L02P_1
VCCO_3 20
56 VCCINT
VCCAUX 21
55 VCCO_1
IO_L07P_3 22
IO_L07N_3 23
54 IO_L01N_1
53 IO_L01P_1
IO_L01P_2/CSO_B 24
IO_L01N_2/INIT_B 25
52 GND
51 DONE
Bank 2
DS312-4_02_082009
Figure 80: VQ100 Package Footprint (top view)
I/O: Unrestricted, general-purpose
DUAL: Configuration pin, then
VREF: User I/O or input voltage
16
1
21
24
4
4
8
4
4
user I/O
possible user-I/O
reference for bank
INPUT: Unrestricted,
general-purpose input pin
CLK: User I/O, input, or global
buffer input
VCCO: Output voltage supply for
bank
CONFIG: Dedicated configuration
pins
JTAG: Dedicated JTAG port pins
GND: Ground
VCCINT: Internal core supply
voltage (+1.2V)
2
N.C.: Not connected
VCCAUX: Auxiliary supply voltage
(+2.5V)
0
12
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Spartan-3E FPGA Family: Pinout Descriptions
CP132: 132-ball Chip-scale Package
The XC3S100E, XC3S250E and the XC3S500E FPGAs
are available in the 132-ball chip-scale package, CP132.
The devices share a common footprint for this package as
shown in Table 133 and Figure 81.
Similarly, the A4, C1, and P10 balls on the XC3S100E
FPGA are not connected but should be connected to GND
to maintain density migration compatibility.
The XC3S100E FPGA has four fewer BPI address pins,
A[19:0], whereas the XC3S250E and XC3S500E support
A[23:0].
Table 133 lists all the CP132 package pins. They are sorted
by bank number and then by pin name. Pins that form a
differential I/O pair appear together in the table. The table
also shows the pin number for each pin and the pin type, as
defined earlier.
An electronic version of this package pinout table and
footprint diagram is available for download from the Xilinx
web site at:
Physically, the D14 and K2 balls on the XC3S100E and
XC3S250E FPGAs are not connected but should be
connected to VCCINT to maintain density migration
compatibility.
http://www.xilinx.com/support/documentation/data_sheets
/s3e_pin.zip
Pinout Table
Table 133: CP132 Package Pinout
XC3S250E
XC3S500E
Pin Name
XC3S100E
Pin Name
Bank
CP132 Ball
Type
0
0
0
IO_L01N_0
IO_L01P_0
N.C. ()
IO_L01N_0
IO_L01P_0
IO_L02N_0
C12
A13
A12
I/O
I/O
100E: N.C.
Others: I/O
0
0
0
N.C. ()
N.C. ()
IP
IO_L02P_0
B12
B11
C11
100E: N.C.
Others: I/O
IO_L03N_0/VREF_0
IO_L03P_0
100E: N.C.
Others: VREF (I/O)
100E: INPUT
Others: I/O
0
0
0
0
0
0
0
0
0
0
0
IO_L04N_0/GCLK5
IO_L04P_0/GCLK4
IO_L05N_0/GCLK7
IO_L05P_0/GCLK6
IO_L07N_0/GCLK11
IO_L07P_0/GCLK10
IO_L08N_0/VREF_0
IO_L08P_0
IO_L04N_0/GCLK5
IO_L04P_0/GCLK4
IO_L05N_0/GCLK7
IO_L05P_0/GCLK6
IO_L07N_0/GCLK11
IO_L07P_0/GCLK10
IO_L08N_0/VREF_0
IO_L08P_0
C9
A10
A9
B9
B7
A7
C6
B6
C5
B5
C4
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
VREF
I/O
IO_L09N_0
IO_L09N_0
I/O
IO_L09P_0
IO_L09P_0
I/O
N.C. ()
IO_L10N_0
100E: N.C.
Others: I/O
0
IP
IO_L10P_0
B4
100E: INPUT
Others: I/O
0
0
0
0
0
IO_L11N_0/HSWAP
IO_L11P_0
IO_L11N_0/HSWAP
IO_L11P_0
B3
A3
C8
B8
A6
DUAL
I/O
IP_L06N_0/GCLK9
IP_L06P_0/GCLK8
VCCO_0
IP_L06N_0/GCLK9
IP_L06P_0/GCLK8
VCCO_0
GCLK
GCLK
VCCO
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Spartan-3E FPGA Family: Pinout Descriptions
Table 133: CP132 Package Pinout (Cont’d)
XC3S250E
XC3S500E
Pin Name
XC3S100E
Pin Name
Bank
CP132 Ball
Type
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
VCCO_0
VCCO_0
IO/A0
B10
F12
K13
N14
N13
M13
M12
L14
L13
J12
K14
J14
J13
H12
H13
G13
G14
F13
F14
D12
D13
C13
C14
G12
E13
M14
P4
VCCO
DUAL
IO/A0
IO/VREF_1
IO/VREF_1
VREF
IO_L01N_1/A15
IO_L01P_1/A16
IO_L02N_1/A13
IO_L02P_1/A14
IO_L03N_1/A11
IO_L03P_1/A12
IO_L04N_1/A9/RHCLK1
IO_L04P_1/A10/RHCLK0
IO_L05N_1/A7/RHCLK3/TRDY1
IO_L05P_1/A8/RHCLK2
IO_L06N_1/A5/RHCLK5
IO_L06P_1/A6/RHCLK4/IRDY1
IO_L07N_1/A3/RHCLK7
IO_L07P_1/A4/RHCLK6
IO_L08N_1/A1
IO_L01N_1/A15
IO_L01P_1/A16
DUAL
DUAL
IO_L02N_1/A13
IO_L02P_1/A14
DUAL
DUAL
IO_L03N_1/A11
IO_L03P_1/A12
DUAL
DUAL
IO_L04N_1/A9/RHCLK1
IO_L04P_1/A10/RHCLK0
IO_L05N_1/A7/RHCLK3/TRDY1
IO_L05P_1/A8/RHCLK2
IO_L06N_1/A5/RHCLK5
IO_L06P_1/A6/RHCLK4/IRDY1
IO_L07N_1/A3/RHCLK7
IO_L07P_1/A4/RHCLK6
IO_L08N_1/A1
RHCLK/DUAL
RHCLK/DUAL
RHCLK/DUAL
RHCLK/DUAL
RHCLK/DUAL
RHCLK/DUAL
RHCLK/DUAL
RHCLK/DUAL
DUAL
IO_L08P_1/A2
IO_L08P_1/A2
DUAL
IO_L09N_1/LDC0
IO_L09P_1/HDC
IO_L10N_1/LDC2
IO_L10P_1/LDC1
IP/VREF_1
IO_L09N_1/LDC0
IO_L09P_1/HDC
IO_L10N_1/LDC2
IO_L10P_1/LDC1
IP/VREF_1
DUAL
DUAL
DUAL
DUAL
VREF
VCCO_1
VCCO_1
VCCO
VCCO_1
VCCO_1
VCCO
IO/D5
IO/D5
DUAL
IO/M1
IO/M1
N7
DUAL
IP/VREF_2
IO/VREF_2
P11
100E: VREF(INPUT)
Others: VREF(I/O)
2
2
2
2
2
2
2
2
2
2
2
2
2
IO_L01N_2/INIT_B
IO_L01N_2/INIT_B
N1
M2
N2
P1
N4
M4
N5
M5
P7
P6
N8
P8
M9
DUAL
DUAL
IO_L01P_2/CSO_B
IO_L02N_2/MOSI/CSI_B
IO_L02P_2/DOUT/BUSY
IO_L03N_2/D6/GCLK13
IO_L03P_2/D7/GCLK12
IO_L04N_2/D3/GCLK15
IO_L04P_2/D4/GCLK14
IO_L06N_2/D1/GCLK3
IO_L06P_2/D2/GCLK2
IO_L07N_2/DIN/D0
IO_L07P_2/M0
IO_L01P_2/CSO_B
IO_L02N_2/MOSI/CSI_B
IO_L02P_2/DOUT/BUSY
IO_L03N_2/D6/GCLK13
IO_L03P_2/D7/GCLK12
IO_L04N_2/D3/GCLK15
IO_L04P_2/D4/GCLK14
IO_L06N_2/D1/GCLK3
IO_L06P_2/D2/GCLK2
IO_L07N_2/DIN/D0
DUAL
DUAL
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL
IO_L07P_2/M0
DUAL
N.C. ()
IO_L08N_2/A22
100E: N.C.
Others: DUAL
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Spartan-3E FPGA Family: Pinout Descriptions
Table 133: CP132 Package Pinout (Cont’d)
XC3S250E
XC3S500E
Pin Name
XC3S100E
Pin Name
Bank
CP132 Ball
Type
2
2
2
N.C. ()
N.C. ()
N.C. ()
IO_L08P_2/A23
N9
100E: N.C.
Others: DUAL
IO_L09N_2/A20
IO_L09P_2/A21
M10
N10
100E: N.C.
Others: DUAL
100E: N.C.
Others: DUAL
2
2
2
2
2
2
2
2
2
3
3
IO_L10N_2/VS1/A18
IO_L10P_2/VS2/A19
IO_L11N_2/CCLK
IO_L11P_2/VS0/A17
IP/VREF_2
IO_L10N_2/VS1/A18
IO_L10P_2/VS2/A19
IO_L11N_2/CCLK
IO_L11P_2/VS0/A17
IP/VREF_2
M11
N11
N12
P12
N3
DUAL
DUAL
DUAL
DUAL
VREF
IP_L05N_2/M2/GCLK1
IP_L05P_2/RDWR_B/GCLK0
VCCO_2
IP_L05N_2/M2/GCLK1
IP_L05P_2/RDWR_B/GCLK0
VCCO_2
N6
DUAL/GCLK
DUAL/GCLK
VCCO
M6
M8
P3
VCCO_2
VCCO_2
VCCO
IO
IO
J3
I/O
IP/VREF_3
IO/VREF_3
K3
100E: VREF(INPUT)
Others: VREF(I/O)
3
3
3
3
3
IO_L01N_3
IO_L01P_3
IO_L02N_3
IO_L02P_3
N.C. ()
IO_L01N_3
IO_L01P_3
IO_L02N_3
IO_L02P_3
IO_L03N_3
B1
B2
C2
C3
D1
I/O
I/O
I/O
I/O
100E: N.C.
Others: I/O
3
IO
IO_L03P_3
D2
F2
F3
G1
F1
H1
G3
H3
H2
L2
I/O
3
IO_L04N_3/LHCLK1
IO_L04P_3/LHCLK0
IO_L05N_3/LHCLK3/IRDY2
IO_L05P_3/LHCLK2
IO_L06N_3/LHCLK5
IO_L06P_3/LHCLK4/TRDY2
IO_L07N_3/LHCLK7
IO_L07P_3/LHCLK6
IO_L08N_3
IO_L04N_3/LHCLK1
IO_L04P_3/LHCLK0
IO_L05N_3/LHCLK3/IRDY2
IO_L05P_3/LHCLK2
IO_L06N_3/LHCLK5
IO_L06P_3/LHCLK4/TRDY2
IO_L07N_3/LHCLK7
IO_L07P_3/LHCLK6
IO_L08N_3
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
I/O
3
3
3
3
3
3
3
3
3
IO_L08P_3
IO_L08P_3
L1
I/O
3
IO_L09N_3
IO_L09N_3
M1
L3
I/O
3
IO_L09P_3
IO_L09P_3
I/O
3
IP/VREF_3
IP/VREF_3
E2
E1
J2
VREF
VCCO
VCCO
GND
3
VCCO_3
VCCO_3
3
VCCO_3
VCCO_3
GND
GND
GND
GND
N.C. (GND)
GND
A4
A8
C1
C7
GND
GND
GND
N.C. (GND)
GND
GND
GND
GND
GND
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Spartan-3E FPGA Family: Pinout Descriptions
Table 133: CP132 Package Pinout (Cont’d)
XC3S250E
XC3S500E
Pin Name
XC3S100E
Pin Name
Bank
CP132 Ball
Type
GND
GND
GND
GND
C10
E3
GND
GND
GND
GND
GND
GND
GND
E14
G2
GND
GND
GND
GND
GND
GND
GND
GND
H14
J1
GND
GND
GND
GND
GND
GND
GND
GND
K12
M3
M7
P5
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
N.C. (GND)
GND
GND
P10
P14
P13
A1
GND
GND
GND
GND
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
DONE
PROG_B
TCK
DONE
PROG_B
TCK
CONFIG
CONFIG
JTAG
B13
A2
TDI
TDI
JTAG
TDO
TDO
A14
B14
A5
JTAG
TMS
TMS
JTAG
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
N.C. (VCCINT)
N.C. (VCCINT)
VCCINT
VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
E12
K1
P9
A11
D3
D14
K2
L12
P2
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170
Spartan-3E FPGA Family: Pinout Descriptions
User I/Os by Bank
Table 134 shows how the 83 available user-I/O pins are
distributed on the XC3S100E FPGA packaged in the CP132
package. Table 135 indicates how the 92 available user-I/O
pins are distributed on the XC3S250E and the XC3S500E
FPGAs in the CP132 package.
Table 134: User I/Os Per Bank for the XC3S100E in the CP132 Package
All Possible I/O Pins by Type
Package
Edge
I/O Bank
Maximum I/O
(2)
I/O
6
INPUT
DUAL
1
VREF(1)
CLK
Top
0
1
2
3
18
23
22
20
83
2
0
0
0
2
1
2
2
2
7
8
(2)
Right
0
21
20
0
0
0
(2)
Bottom
Left
0
10
16
8
TOTAL
42
16
Notes:
1. Some VREF and CLK pins are on INPUT pins.
2. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
Table 135: User I/Os Per Bank for the XC3S250E and XC3S500E in the CP132 Package
All Possible I/O Pins by Type
Package
I/O Bank
Maximum I/O
Edge
(2)
I/O
11
0
INPUT
DUAL
VREF(1)
CLK
Top
0
1
2
3
22
23
26
21
92
0
0
0
0
0
1
2
2
2
2
8
8
Right
21
24
0
0(2)
0(2)
8
Bottom
Left
0
11
22
TOTAL
46
16
Notes:
1. Some VREF and CLK pins are on INPUT pins.
2. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
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171
Spartan-3E FPGA Family: Pinout Descriptions
Footprint Migration Differences
Table 136 summarizes any footprint and functionality
differences between the XC3S100E, the XC3S250E, and
the XC3S500E FPGAs that may affect easy migration
between devices in the CP132 package. There are 14 such
balls. All other pins not listed in Table 136 unconditionally
migrate between Spartan-3E devices available in the
CP132 package.
the two pins have identical functionality. A left-facing arrow
() indicates that the pin on the device on the right
unconditionally migrates to the pin on the device on the left.
It may be possible to migrate the opposite direction
depending on the I/O configuration. For example, an I/O pin
(Type = I/O) can migrate to an input-only pin
(Type = INPUT) if the I/O pin is configured as an input.
The XC3S100E is duplicated on both the left and right sides
of the table to show migrations to and from the XC3S250E
and the XC3S500E. The arrows indicate the direction for
easy migration. A double-ended arrow () indicates that
The XC3S100E FPGA in the CP132 package has four fewer
BPI-mode address lines than the XC3S250E and
XC3S500E.
Table 136: CP132 Footprint Migration Differences
CP132
Ball
XC3S100E
Type
XC3S250E
Type
XC3S500E
Type
XC3S100E
Type
Bank
Migration
Migration
Migration
A12
B4
0
0
0
0
0
0
3
3
3
2
2
2
2
2
N.C.
14
I/O
I/O
0
I/O
I/O
14
N.C.
INPUT
N.C.
INPUT
N.C.
B11
B12
C4
I/O
I/O
N.C.
I/O
I/O
N.C.
N.C.
I/O
I/O
N.C.
C11
D1
INPUT
N.C.
I/O
I/O
INPUT
N.C.
I/O
I/O
D2
I/O
I/O (Diff)
VREF(I/O)
DUAL
DUAL
DUAL
DUAL
VREF(I/O)
I/O (Diff)
VREF(I/O)
DUAL
DUAL
DUAL
DUAL
VREF(I/O)
I/O
K3
VREF(INPUT)
N.C.
VREF(INPUT)
N.C.
M9
M10
N9
N.C.
N.C.
N.C.
N.C.
N10
P11
N.C.
N.C.
VREF(INPUT)
VREF(INPUT)
DIFFERENCES
Legend:
This pin is identical on the device on the left and the right.
This pin can unconditionally migrate from the device on the left to the device on the right. Migration in the other direction may be
possible depending on how the pin is configured for the device on the right.
This pin can unconditionally migrate from the device on the right to the device on the left. Migration in the other direction may be
possible depending on how the pin is configured for the device on the left.
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Product Specification
172
Spartan-3E FPGA Family: Pinout Descriptions
CP132 Footprint
X-Ref Target - Figure 81
Bank 0
8
1
2
3
4
5
6
7
I/O
9
I/O
L05N_0
GCLK7
10
I/O
L04P_0
GCLK4
11
12
I/O
13
14
I/O
L11P_0
I/O
L01P_0
VCCAUX
PROG_B
GND
GND
TDI
VCCINT L02N_0
TDO
VCCO_0 L07P_0
GCLK10
A
B
C
D
E
F
I/O
I/O
L11N_0
HSWAP
I/O
L10P_0
I/O
I/O
L08P_0
INPUT
L06P_0
GCLK8
I/O
L05P_0
GCLK6
I/O
L02P_0
I/O
L01N_3
I/O
L01P_3
I/O
L09P_0
L03N_0
VREF_0
VCCO_0
TCK
TMS
L07N_0
GCLK11
I/O
L10N_0
I/O
I/O
L04N_0
GCLK5
I/O
I/O
L10N_1
LDC2
I/O
L10P_1
LDC1
INPUT
L06N_0
GCLK9
I/O
I/O
I/O
L09N_0
I/O
L08N_0
L03P_0
GND
GND
GND
L02N_3
L02P_3
L01N_0
VREF_0
I/O
L09N_1
LDC0
I/O
I/O
L03N_3
I/O
L03P_3 VCCINT
L09P_1 VCCINT
HDC
INPUT
GND
VCCO_3
VCCAUX
GND
VCCO_1
VREF_3
I/O
L05P_3
I/O
L04N_3
LHCLK2 LHCLK1 LHCLK0
I/O
L04P_3
I/O
L08N_1
A1
I/O
L08P_1
A2
I/O
A0
I/O
L05N_3
LHCLK3
IRDY2
I/O
L06P_3
LHCLK4
TRDY2
I/O
I/O
INPUT
VREF_1
L07N_1
A3
L07P_1
A4
G
H
J
GND
RHCLK7 RHCLK6
I/O
I/O
I/O
I/O
I/O
L06P_1
L06N_1
A5
L06N_3
L07P_3
L07N_3
A6
GND
I/O
RHCLK4
IRDY1
LHCLK5 LHCLK6 LHCLK7
RHCLK5
I/O
L04N_1
A9
I/O
L05P_1
A8
L05N_1
A7
VCCO_3
I/O
GND
RHCLK3
TRDY1
RHCLK1 RHCLK2
I/O
I/O
I/O
GND
L04P_1
A10
VCCINT
VCCAUX
K
L
VREF_3
VREF_1
RHCLK0
I/O
L03P_1
A12
I/O
L03N_1
A11
I/O
L08P_3
I/O
L08N_3
I/O
L09P_3
VCCINT
I/O
L08N_2
A22
I/O
L09N_2
A20
I/O
I/O
INPUT
I/O
I/O
L01P_2
CSO_B
I/O
L02P_1
A14
I/O
L02N_1
A13
I/O
L03P_2
D7
L04P_2
D4
L05P_2
L10N_2
VS1
GND
M
N
P
GND
VCCO_2
VCCO_1
L09N_3
RDWR_B
GCLK0
GCLK12 GCLK14
A18
I/O
L08P_2
A23
I/O
L09P_2
A21
I/O
I/O
L03N_2
D6
I/O
L04N_2
D3
INPUT
I/O
I/O
I/O
L01N_2
INIT_B
I/O
L11N_2
CCLK
I/O
L01P_1
A16
I/O
L01N_1
A15
I/O
M1
INPUT
VREF_2
L02N_2
MOSI
L05N_2
L07N_2
DIN
L10P_2
VS2
M2
CSI_B
GCLK13 GCLK15
GCLK1
D0
A19
I/O
L02P_2
DOUT
BUSY
I/O
I/O
I/O
I/O
L07P_2
M0
I/O
VREF_2
I/O
L06P_2
D2
L06N_2
D1
L11P_2
VS0
VCCO_2
GND
D5
VCCAUX
GND
GND
VCCINT
DONE
GCLK2
GCLK3
A17
Bank 2
DS312-4_07_030206
Figure 81: CP132 Package Footprint (top view)
I/O: Unrestricted, general-purpose
user I/O
DUAL: Configuration pin, then
possible user I/O
VREF: User I/O or input voltage
reference for bank
16-
22
42-
46
7-8
INPUT: Unrestricted,
CLK: User I/O, input, or global
VCCO: Output voltage supply for
0-2
2
16
4
8
6
4
general-purpose input pin
buffer input
bank
CONFIG: Dedicated configuration
pins
JTAG: Dedicated JTAG port pins
GND: Ground
VCCINT: Internal core supply
voltage (+1.2V)
N.C.: Unconnected balls on the
XC3S100E FPGA ()
VCCAUX: Auxiliary supply voltage
(+2.5V)
9
16
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173
Spartan-3E FPGA Family: Pinout Descriptions
TQ144: 144-lead Thin Quad Flat Package
The XC3S100E and the XC3S250E FPGAs are available in
the 144-lead thin quad flat package, TQ144. Both devices
share a common footprint for this package as shown in
Table 137 and Figure 82.
The TQ144 package only supports 20 address output pins
in the Byte-wide Peripheral Interface (BPI) configuration
mode. In larger packages, there are 24 BPI address
outputs.
Table 137 lists all the package pins. They are sorted by
bank number and then by pin name of the largest device.
Pins that form a differential I/O pair appear together in the
table. The table also shows the pin number for each pin and
the pin type, as defined earlier.
An electronic version of this package pinout table and
footprint diagram is available for download from the Xilinx
web site at:
http://www.xilinx.com/support/documentation/data_sheets
/s3e_pin.zip
Pinout Table
Table 137: TQ144 Package Pinout
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
XC3S100E Pin Name
XC3S250E Pin Name
TQ144 Pin
P132
P124
P113
P112
P117
P116
P123
P122
P126
P125
P131
P130
P135
P134
P140
P139
P143
P142
P111
P114
P136
P141
P120
P119
P129
P128
P121
P138
P98
Type
I/O
IO
IO
IO/VREF_0
IO/VREF_0
VREF
I/O
IO_L01N_0
IO_L01N_0
IO_L01P_0
IO_L01P_0
I/O
IO_L02N_0
IO_L02N_0
I/O
IO_L02P_0
IO_L02P_0
I/O
IO_L04N_0/GCLK5
IO_L04P_0/GCLK4
IO_L05N_0/GCLK7
IO_L05P_0/GCLK6
IO_L07N_0/GCLK11
IO_L07P_0/GCLK10
IO_L08N_0/VREF_0
IO_L08P_0
IO_L04N_0/GCLK5
IO_L04P_0/GCLK4
IO_L05N_0/GCLK7
IO_L05P_0/GCLK6
IO_L07N_0/GCLK11
IO_L07P_0/GCLK10
IO_L08N_0/VREF_0
IO_L08P_0
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
VREF
I/O
IO_L09N_0
IO_L09N_0
I/O
IO_L09P_0
IO_L09P_0
I/O
IO_L10N_0/HSWAP
IO_L10P_0
IO_L10N_0/HSWAP
IO_L10P_0
DUAL
I/O
IP
IP
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
GCLK
GCLK
VCCO
VCCO
DUAL
VREF
DUAL
DUAL
DUAL
IP
IP
IP
IP
IP
IP
IP_L03N_0
IP_L03N_0
IP_L03P_0
IP_L03P_0
IP_L06N_0/GCLK9
IP_L06P_0/GCLK8
VCCO_0
IP_L06N_0/GCLK9
IP_L06P_0/GCLK8
VCCO_0
VCCO_0
VCCO_0
IO/A0
IO/A0
IO/VREF_1
IO/VREF_1
P83
IO_L01N_1/A15
IO_L01P_1/A16
IO_L02N_1/A13
IO_L01N_1/A15
IO_L01P_1/A16
IO_L02N_1/A13
P75
P74
P77
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Product Specification
174
Spartan-3E FPGA Family: Pinout Descriptions
Table 137: TQ144 Package Pinout (Cont’d)
Bank
1
XC3S100E Pin Name
IO_L02P_1/A14
XC3S250E Pin Name
IO_L02P_1/A14
TQ144 Pin
P76
Type
DUAL
1
IO_L03N_1/A11
IO_L03P_1/A12
IO_L04N_1/A9/RHCLK1
IO_L04P_1/A10/RHCLK0
IO_L05N_1/A7/RHCLK3/TRDY1
IO_L05P_1/A8/RHCLK2
IO_L06N_1/A5/RHCLK5
IO_L06P_1/A6/RHCLK4/IRDY1
IO_L07N_1/A3/RHCLK7
IO_L07P_1/A4/RHCLK6
IO_L08N_1/A1
IO_L08P_1/A2
IO_L09N_1/LDC0
IO_L09P_1/HDC
IO_L10N_1/LDC2
IO_L10P_1/LDC1
IP
IO_L03N_1/A11
IO_L03P_1/A12
IO_L04N_1/A9/RHCLK1
IO_L04P_1/A10/RHCLK0
IO_L05N_1/A7/RHCLK3
IO_L05P_1/A8/RHCLK2
IO_L06N_1/A5/RHCLK5
IO_L06P_1/A6/RHCLK4
IO_L07N_1/A3/RHCLK7
IO_L07P_1/A4/RHCLK6
IO_L08N_1/A1
IO_L08P_1/A2
IO_L09N_1/LDC0
IO_L09P_1/HDC
IO_L10N_1/LDC2
IO_L10P_1/LDC1
IP
P82
DUAL
1
P81
DUAL
1
P86
RHCLK/DUAL
RHCLK/DUAL
RHCLK/DUAL
RHCLK/DUAL
RHCLK/DUAL
RHCLK/DUAL
RHCLK/DUAL
RHCLK/DUAL
DUAL
1
P85
1
P88
1
P87
1
P92
1
P91
1
P94
1
P93
1
P97
1
P96
DUAL
1
P104
P103
P106
P105
P78
DUAL
1
DUAL
1
DUAL
1
DUAL
1
INPUT
1
IP
IP
P84
INPUT
1
IP
IP
P89
INPUT
1
IP
IP
P101
P107
P95
INPUT
1
IP
IP
INPUT
1
IP/VREF_1
IP/VREF_1
VREF
1
VCCO_1
VCCO_1
P79
VCCO
1
VCCO_1
VCCO_1
P100
P52
VCCO
2
IO/D5
IO/D5
DUAL
2
IO/M1
IO/M1
P60
DUAL
2
IP/VREF_2
IO/VREF_2
P66
100E: VREF(INPUT)
250E: VREF(I/O)
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO_L01N_2/INIT_B
IO_L01N_2/INIT_B
P40
P39
P44
P43
P51
P50
P54
P53
P59
P58
P63
P62
P68
P67
P71
P70
DUAL
DUAL
IO_L01P_2/CSO_B
IO_L01P_2/CSO_B
IO_L02N_2/MOSI/CSI_B
IO_L02P_2/DOUT/BUSY
IO_L04N_2/D6/GCLK13
IO_L04P_2/D7/GCLK12
IO_L05N_2/D3/GCLK15
IO_L05P_2/D4/GCLK14
IO_L07N_2/D1/GCLK3
IO_L07P_2/D2/GCLK2
IO_L08N_2/DIN/D0
IO_L02N_2/MOSI/CSI_B
IO_L02P_2/DOUT/BUSY
IO_L04N_2/D6/GCLK13
IO_L04P_2/D7/GCLK12
IO_L05N_2/D3/GCLK15
IO_L05P_2/D4/GCLK14
IO_L07N_2/D1/GCLK3
IO_L07P_2/D2/GCLK2
IO_L08N_2/DIN/D0
DUAL
DUAL
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL
IO_L08P_2/M0
IO_L08P_2/M0
DUAL
IO_L09N_2/VS1/A18
IO_L09P_2/VS2/A19
IO_L10N_2/CCLK
IO_L09N_2/VS1/A18
IO_L09P_2/VS2/A19
IO_L10N_2/CCLK
DUAL
DUAL
DUAL
IO_L10P_2/VS0/A17
IO_L10P_2/VS0/A17
DUAL
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Spartan-3E FPGA Family: Pinout Descriptions
Table 137: TQ144 Package Pinout (Cont’d)
Bank
XC3S100E Pin Name
XC3S250E Pin Name
TQ144 Pin
P38
Type
INPUT
2
2
2
2
2
2
2
2
2
2
3
IP
IP
IP
IP
IP
IP
P41
INPUT
P69
INPUT
IP_L03N_2/VREF_2
IP_L03P_2
IP_L03N_2/VREF_2
IP_L03P_2
P48
VREF
P47
INPUT
IP_L06N_2/M2/GCLK1
IP_L06P_2/RDWR_B/GCLK0
VCCO_2
IP_L06N_2/M2/GCLK1
IP_L06P_2/RDWR_B/GCLK0
VCCO_2
P57
DUAL/GCLK
DUAL/GCLK
VCCO
P56
P42
VCCO_2
VCCO_2
P49
VCCO
VCCO_2
VCCO_2
P64
VCCO
IP/VREF_3
IO/VREF_3
P31
100E: VREF(INPUT)
250E: VREF(I/O)
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO_L01N_3
IO_L01N_3
P3
P2
I/O
I/O
IO_L01P_3
IO_L01P_3
IO_L02N_3/VREF_3
IO_L02P_3
IO_L02N_3/VREF_3
IO_L02P_3
P5
VREF
I/O
P4
IO_L03N_3
IO_L03N_3
P8
I/O
IO_L03P_3
IO_L03P_3
P7
I/O
IO_L04N_3/LHCLK1
IO_L04P_3/LHCLK0
IO_L05N_3/LHCLK3/IRDY2
IO_L05P_3/LHCLK2
IO_L06N_3/LHCLK5
IO_L06P_3/LHCLK4/TRDY2
IO_L07N_3/LHCLK7
IO_L07P_3/LHCLK6
IO_L08N_3
IO_L04N_3/LHCLK1
IO_L04P_3/LHCLK0
IO_L05N_3/LHCLK3
IO_L05P_3/LHCLK2
IO_L06N_3/LHCLK5
IO_L06P_3/LHCLK4
IO_L07N_3/LHCLK7
IO_L07P_3/LHCLK6
IO_L08N_3
P15
P14
P17
P16
P21
P20
P23
P22
P26
P25
P33
P32
P35
P34
P6
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
I/O
IO_L08P_3
IO_L08P_3
I/O
IO_L09N_3
IO_L09N_3
I/O
IO_L09P_3
IO_L09P_3
I/O
IO_L10N_3
IO_L10N_3
I/O
IO_L10P_3
IO_L10P_3
I/O
IP
IP
INPUT
IO
IP
P10
100E: I/O
250E: INPUT
3
3
3
IP
IP
IO
IP
IP
IP
P18
P24
P29
INPUT
INPUT
100E: I/O
250E: INPUT
3
3
IP
IP
P36
P12
P13
P28
P11
P19
INPUT
VREF
VCCO
VCCO
GND
IP/VREF_3
VCCO_3
VCCO_3
GND
IP/VREF_3
VCCO_3
VCCO_3
GND
3
3
GND
GND
GND
GND
GND
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Spartan-3E FPGA Family: Pinout Descriptions
Table 137: TQ144 Package Pinout (Cont’d)
Bank
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
XC3S100E Pin Name
XC3S250E Pin Name
TQ144 Pin
P27
Type
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DONE
P37
GND
P46
GND
P55
GND
P61
GND
P73
GND
P90
GND
P99
GND
P118
P127
P133
P72
GND
GND
GND
VCCAUX DONE
VCCAUX PROG_B
VCCAUX TCK
CONFIG
CONFIG
JTAG
PROG_B
TCK
P1
P110
P144
P109
P108
P30
VCCAUX TDI
TDI
JTAG
VCCAUX TDO
TDO
JTAG
VCCAUX TMS
TMS
JTAG
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
P65
P102
P137
P9
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
P45
P80
P115
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Spartan-3E FPGA Family: Pinout Descriptions
User I/Os by Bank
Table 138 and Table 139 indicate how the 108 available
user-I/O pins are distributed between the four I/O banks on
the TQ144 package.
Table 138: User I/Os Per Bank for the XC3S100E in the TQ144 Package
All Possible I/O Pins by Type
Package
Edge
I/O Bank
Maximum I/O
(2)
I/O
9
INPUT
DUAL
1
VREF(1)
CLK
Top
0
1
2
3
26
28
6
5
2
2
2
3
9
8
Right
0
21
20
0
0(2)
0(2)
8
Bottom
Left
26
0
4
28
13
22
4
TOTAL
108
19
42
16
Notes:
1. Some VREF and CLK pins are on INPUT pins.
2. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
Table 139: User I/Os Per Bank for the XC3S250E in TQ144 Package
All Possible I/O Pins by Type
Package
Edge
I/O Bank
Maximum I/O
(2)
I/O
9
INPUT
DUAL
1
VREF(1)
CLK
Top
0
1
2
3
26
28
6
5
2
2
2
3
9
8
Right
0
21
20
0
0(2)
0(2)
8
Bottom
Left
26
0
4
28
11
20
6
TOTAL
108
21
42
16
Notes:
1. Some VREF and CLK pins are on INPUT pins.
2. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
The arrows indicate the direction for easy migration. For
example, a left-facing arrow indicates that the pin on the
XC3S250E unconditionally migrates to the pin on the
XC3S100E. It may be possible to migrate the opposite
direction depending on the I/O configuration. For example,
an I/O pin (Type = I/O) can migrate to an input-only pin
(Type = INPUT) if the I/O pin is configured as an input.
Footprint Migration Differences
Table 140 summarizes any footprint and functionality
differences between the XC3S100E and the XC3S250E
FPGAs that may affect easy migration between devices.
There are four such pins. All other pins not listed in
Table 140 unconditionally migrate between Spartan-3E
devices available in the TQ144 package.
Table 140: TQ144 Footprint Migration Differences
TQ144 Pin
P10
Bank
XC3S100E Type
Migration
XC3S250E Type
INPUT
3
3
3
2
I/O
I/O
4
P29
INPUT
P31
VREF(INPUT)
VREF(INPUT)
VREF(I/O)
VREF(I/O)
P66
DIFFERENCES
Legend:
This pin can unconditionally migrate from the device on the left to the device on the right. Migration in the other direction may
be possible depending on how the pin is configured for the device on the right.
This pin can unconditionally migrate from the device on the right to the device on the left. Migration in the other direction may
be possible depending on how the pin is configured for the device on the left.
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178
Spartan-3E FPGA Family: Pinout Descriptions
TQ144 Footprint
Note pin 1 indicator in top-left corner and logo orientation.
Double arrows () indicates a pinout migration difference
between the XC3S100E and XC3S250E.
X-Ref Target - Figure 82
PROG_B
IO_L01P_3
1
2
108 TMS
107 IP
Bank 0
IO_L01N_3
IO_L02P_3
IO_L02N_3/VREF_3
IP
3
4
106 IO_L10N_1/LDC2
105 IO_L10P_1/LDC1
104 IO_L09N_1/LDC0
103 IO_L09P_1/HDC
102 VCCAUX
5
6
IO_L03P_3
IO_L03N_3
VCCINT
7
8
101 IP
9
100 VCCO_1
(ꢀꢁ) IP
10
99 GND
GND 11
IP/VREF_3 12
98 IO/A0
97 IO_L08N_1/A1
96 IO_L08P_1/A2
95 IP/VREF_1
VCCO_3 13
IO_L04P_3/LHCLK0 14
IO_L04N_3/LHCLK1 15
IO_L05P_3/LHCLK2 16
IO_L05N_3/LHCLK3 17
IP 18
94 IO_L07N_1/A3/RHCLK7
93 IO_L07P_1/A4/RHCLK6
92 IO_L06N_1/A5/RHCLK5
91 IO_L06P_1/A6/RHCLK4
90 GND
GND 19
IO_L06P_3/LHCLK4 20
IO_L06N_3/LHCLK5 21
IO_L07P_3/LHCLK6 22
IO_L07N_3/LHCLK7 23
IP 24
89 IP
88 IO_L05N_1/A7/RHCLK3
87 IO_L05P_1/A8/RHCLK2
86 IO_L04N_1/A9/RHCLK1
85 IO_L04P_1/A10/RHCLK0
84 IP
IO_L08P_3 25
IO_L08N_3 26
83 IO/VREF_1
GND 27
82 IO_L03N_1/A11
81 IO_L03P_1/A12
80 VCCINT
VCCO_3 28
(ꢀꢁ) IP
VCCAUX 30
29
79 VCCO_1
(ꢀꢁ) IO/VREF_3
31
IO_L09P_3 32
IO_L09N_3 33
IO_L10P_3 34
IO_L10N_3 35
IP 36
78 IP
77 IO_L02N_1/A13
76 IO_L02P_1/A14
75 IO_L01N_1/A15
74
73
IO_L01P_1/A16
GND
Bank 2
DS312-4_01_082009
Figure 82: TQ144 Package Footprint (top view)
I/O: Unrestricted, general-purpose
DUAL: Configuration pin, then
VREF: User I/O or input voltage
20
21
2
42
16
4
9
9
4
4
user I/O
possible user I/O
reference for bank
INPUT: Unrestricted,
general-purpose input pin
CLK: User I/O, input, or global
buffer input
VCCO: Output voltage supply for
bank
CONFIG: Dedicated configuration
pins
JTAG: Dedicated JTAG port pins
GND: Ground
VCCINT: Internal core supply
voltage (+1.2V)
N.C.: Not connected
VCCAUX: Auxiliary supply voltage
(+2.5V)
0
13
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179
Spartan-3E FPGA Family: Pinout Descriptions
PQ208: 208-pin Plastic Quad Flat Package
The 208-pin plastic quad flat package, PQ208, supports two
different Spartan-3E FPGAs, including the XC3S250E and
the XC3S500E.
Table 141: PQ208 Package Pinout (Cont’d)
XC3S250E
XC3S500E
Pin Name
PQ208
Pin
Bank
Type
Table 141 lists all the PQ208 package pins. They are sorted
by bank number and then by pin name. Pairs of pins that
form a differential I/O pair appear together in the table. The
table also shows the pin number for each pin and the pin
type, as defined earlier.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IO_L15P_0
P202
P206
P205
P159
P169
P194
P204
P175
P174
P184
P183
P176
P191
P201
P107
P106
P109
P108
P113
P112
P116
P115
P120
P119
P123
P122
I/O
IO_L16N_0/HSWAP
IO_L16P_0
DUAL
I/O
IP
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
GCLK
GCLK
VCCO
VCCO
VCCO
DUAL
DUAL
DUAL
DUAL
VREF
I/O
An electronic version of this package pinout table and
footprint diagram is available for download from the Xilinx
website at:
IP
IP
IP
http://www.xilinx.com/support/documentation/data_sheets
/s3e_pin.zip
IP_L06N_0
IP_L06P_0
IP_L09N_0/GCLK9
IP_L09P_0/GCLK8
VCCO_0
Pinout Table
Table 141: PQ208 Package Pinout
XC3S250E
XC3S500E
Pin Name
VCCO_0
PQ208
Pin
Bank
Type
VCCO_0
IO_L01N_1/A15
IO_L01P_1/A16
IO_L02N_1/A13
IO_L02P_1/A14
IO_L03N_1/VREF_1
IO_L03P_1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO
P187
P179
P161
P160
P163
P162
P165
P164
P168
P167
P172
P171
P178
P177
P181
P180
P186
P185
P190
P189
P193
P192
P197
P196
P200
P199
P203
I/O
VREF
I/O
IO/VREF_0
IO_L01N_0
IO_L01P_0
I/O
IO_L02N_0/VREF_0
IO_L02P_0
VREF
I/O
IO_L04N_1
I/O
IO_L03N_0
I/O
IO_L04P_1
I/O
IO_L03P_0
I/O
IO_L05N_1/A11
IO_L05P_1/A12
IO_L06N_1/VREF_1
IO_L06P_1
DUAL
DUAL
VREF
I/O
IO_L04N_0/VREF_0
IO_L04P_0
VREF
I/O
IO_L05N_0
I/O
IO_L05P_0
I/O
IO_L07N_1/A9/RHCLK1
P127 RHCLK/DUAL
IO_L07N_0/GCLK5
IO_L07P_0/GCLK4
IO_L08N_0/GCLK7
IO_L08P_0/GCLK6
IO_L10N_0/GCLK11
IO_L10P_0/GCLK10
IO_L11N_0
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
I/O
IO_L07P_1/A10/RHCLK0 P126 RHCLK/DUAL
IO_L08N_1/A7/RHCLK3
IO_L08P_1/A8/RHCLK2
IO_L09N_1/A5/RHCLK5
IO_L09P_1/A6/RHCLK4
IO_L10N_1/A3/RHCLK7
IO_L10P_1/A4/RHCLK6
IO_L11N_1/A1
P129 RHCLK/DUAL
P128 RHCLK/DUAL
P133 RHCLK/DUAL
P132 RHCLK/DUAL
P135 RHCLK/DUAL
P134 RHCLK/DUAL
IO_L11P_0
I/O
P138
P137
P140
P139
P145
P144
P147
P146
DUAL
DUAL
DUAL
I/O
IO_L12N_0/VREF_0
IO_L12P_0
VREF
I/O
IO_L11P_1/A2
IO_L12N_1/A0
IO_L13N_0
I/O
IO_L12P_1
IO_L13P_0
I/O
IO_L13N_1
I/O
IO_L14N_0/VREF_0
IO_L14P_0
VREF
I/O
IO_L13P_1
I/O
IO_L14N_1
I/O
IO_L15N_0
I/O
IO_L14P_1
I/O
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Spartan-3E FPGA Family: Pinout Descriptions
Table 141: PQ208 Package Pinout (Cont’d)
Table 141: PQ208 Package Pinout (Cont’d)
XC3S250E
XC3S500E
Pin Name
XC3S250E
XC3S500E
Pin Name
PQ208
Pin
PQ208
Pin
Bank
Type
Bank
Type
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO_L15N_1/LDC0
IO_L15P_1/HDC
IO_L16N_1/LDC2
IO_L16P_1/LDC1
IP
P151
P150
P153
P152
P110
P118
P124
P130
P142
P148
P154
P136
P114
P125
P143
P76
DUAL
DUAL
2
2
2
2
2
2
2
2
2
2
2
2
IO_L16P_2/VS2/A19
IO_L17N_2/CCLK
IO_L17P_2/VS0/A17
IP
P99
P103
P102
P54
P91
P101
P58
P57
P72
P71
P81
P80
DUAL
DUAL
DUAL
DUAL
DUAL
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VREF
VCCO
VCCO
VCCO
DUAL
IP
INPUT
IP
IP
INPUT
IP
IP_L02N_2
INPUT
IP
IP_L02P_2
INPUT
IP
IP_L07N_2/VREF_2
IP_L07P_2
VREF
IP
INPUT
IP
IP_L10N_2/M2/GCLK1
DUAL/GCLK
DUAL/GCLK
IP/VREF_1
IP_L10P_2/RDWR_B/
GCLK0
VCCO_1
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
VCCO_2
P59
P73
P88
P45
P3
VCCO
VCCO
VCCO
VREF
I/O
VCCO_1
VCCO_2
VCCO_1
VCCO_2
IO/D5
IO/VREF_3
IO/M1
P84
DUAL
IO_L01N_3
IO/VREF_2
P98
VREF
DUAL
IO_L01P_3
P2
I/O
IO_L01N_2/INIT_B
IO_L01P_2/CSO_B
IO_L03N_2/MOSI/CSI_B
IO_L03P_2/DOUT/BUSY
IO_L04N_2
P56
IO_L02N_3/VREF_3
IO_L02P_3
P5
VREF
I/O
P55
DUAL
P4
P61
DUAL
IO_L03N_3
P9
I/O
P60
DUAL
IO_L03P_3
P8
I/O
P63
I/O
IO_L04N_3
P12
P11
P16
P15
P19
P18
P23
P22
P25
P24
P29
P28
P31
P30
P34
P33
P36
P35
P40
P39
P42
I/O
IO_L04P_2
P62
I/O
IO_L04P_3
I/O
IO_L05N_2
P65
I/O
IO_L05N_3
I/O
IO_L05P_2
P64
I/O
IO_L05P_3
I/O
IO_L06N_2
P69
I/O
IO_L06N_3
I/O
IO_L06P_2
P68
I/O
IO_L06P_3
I/O
IO_L08N_2/D6/GCLK13
IO_L08P_2/D7/GCLK12
IO_L09N_2/D3/GCLK15
IO_L09P_2/D4/GCLK14
IO_L11N_2/D1/GCLK3
IO_L11P_2/D2/GCLK2
IO_L12N_2/DIN/D0
IO_L12P_2/M0
IO_L13N_2
P75
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL
IO_L07N_3/LHCLK1
IO_L07P_3/LHCLK0
IO_L08N_3/LHCLK3
IO_L08P_3/LHCLK2
IO_L09N_3/LHCLK5
IO_L09P_3/LHCLK4
IO_L10N_3/LHCLK7
IO_L10P_3/LHCLK6
IO_L11N_3
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
I/O
P74
P78
P77
P83
P82
P87
P86
DUAL
P90
I/O
IO_L13P_2
P89
I/O
IO_L11P_3
I/O
IO_L14N_2/A22
IO_L14P_2/A23
IO_L15N_2/A20
IO_L15P_2/A21
IO_L16N_2/VS1/A18
P94
DUAL
IO_L12N_3
I/O
P93
DUAL
IO_L12P_3
I/O
P97
DUAL
IO_L13N_3
I/O
P96
DUAL
IO_L13P_3
I/O
P100
DUAL
IO_L14N_3
I/O
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181
Spartan-3E FPGA Family: Pinout Descriptions
Table 141: PQ208 Package Pinout (Cont’d)
Table 141: PQ208 Package Pinout (Cont’d)
XC3S250E
XC3S500E
Pin Name
XC3S250E
XC3S500E
Pin Name
PQ208
Pin
PQ208
Pin
Bank
Type
Bank
Type
3
IO_L14P_3
P41
P48
P47
P50
P49
P6
I/O
I/O
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
P66
P92
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
3
IO_L15N_3
IO_L15P_3
IO_L16N_3
IO_L16P_3
IP
3
I/O
P111
P149
P166
P195
P13
3
I/O
3
I/O
3
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VREF
VCCO
VCCO
VCCO
GND
3
IP
P14
P26
P32
P43
P51
P20
P21
P38
P46
P10
P17
P27
P37
P52
P53
P70
P79
P85
P95
P105
P121
P131
P141
P156
P173
P182
P188
P198
P208
P104
P1
3
IP
P67
3
IP
P117
P170
3
IP
3
IP
3
IP/VREF_3
VCCO_3
VCCO_3
VCCO_3
GND
3
3
3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCCAUX DONE
VCCAUX PROG_B
VCCAUX TCK
CONFIG
CONFIG
JTAG
JTAG
JTAG
JTAG
VCCAUX
VCCAUX
P158
P207
P157
P155
P7
VCCAUX TDI
VCCAUX TDO
VCCAUX TMS
VCCAUX VCCAUX
VCCAUX VCCAUX
P44
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182
Spartan-3E FPGA Family: Pinout Descriptions
User I/Os by Bank
Footprint Migration Differences
Table 142 indicates how the 158 available user-I/O pins are
distributed between the four I/O banks on the PQ208
package.
The XC3S250E and XC3S500E FPGAs have identical
footprints in the PQ208 package. Designs can migrate
between the XC3S250E and XC3S500E without further
consideration.
Table 142: User I/Os Per Bank for the XC3S250E and XC3S500E in the PQ208 Package
All Possible I/O Pins by Type
Package
I/O Bank
Maximum I/O
Edge
(2)
I/O
18
9
INPUT
DUAL
VREF(1)
CLK
Top
0
1
2
3
38
40
6
7
1
5
3
8
(2)
Right
21
24
0
0
0
(2)
Bottom
Left
40
8
6
2
40
23
58
6
3
8
TOTAL
158
25
46
13
16
Notes:
1. Some VREF and CLK pins are on INPUT pins.
2. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
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183
Spartan-3E FPGA Family: Pinout Descriptions
PQ208 Footprint (Left)
X-Ref Target - Figure 83
PROG_B
IO_L01P_3
1
2
Bank 0
IO_L01N_3
IO_L02P_3
IO_L02N_3/VREF_3
IP
3
4
5
6
7
8
9
VCCAUX
IO_L03P_3
IO_L03N_3
GND 10
IO_L04P_3 11
IO_L04N_3 12
VCCINT 13
IP 14
IO_L05P_3 15
IO_L05N_3 16
GND 17
IO_L06P_3 18
IO_L06N_3 19
IP/VREF_3 20
VCCO_3 21
IO_L07P_3/LHCLK0 22
IO_L07N_3/LHCLK1 23
IO_L08P_3/LHCLK2 24
IO_L08N_3/LHCLK3 25
IP 26
GND 27
IO_L09P_3/LHCLK4 28
IO_L09N_3/LHCLK5 29
IO_L10P_3/LHCLK6 30
IO_L10N_3/LHCLK7 31
IP 32
IO_L11P_3 33
IO_L11N_3 34
IO_L12P_3 35
IO_L12N_3 36
GND 37
VCCO_3 38
IO_L13P_3 39
IO_L13N_3 40
IO_L14P_3 41
IO_L14N_3 42
IP 43
VCCAUX 44
IO/VREF_3 45
VCCO_3 46
IO_L15P_3 47
IO_L15N_3 48
IO_L16P_3 49
IO_L16N_3 50
IP 51
Bank 2
GND 52
DS312-4_03_030705
Figure 83: PQ208 Footprint (Left)
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Product Specification
184
Spartan-3E FPGA Family: Pinout Descriptions
PQ208 Footprint (Right)
X-Ref Target - Figure 84
156 GND
155 TMS
Bank 0
154 IP
153 IO_L16N_1/LDC2
152 IO_L16P_1/LDC1
151 IO_L15N_1/LDC0
150 IO_L15P_1/HDC
149 VCCAUX
148 IP
147 IO_L14N_1
146 IO_L14P_1
145 IO_L13N_1
144 IO_L13P_1
143 VCCO_1
142 IP
141 GND
140 IO_L12N_1/A0
139 IO_L12P_1
138 IO_L11N_1/A1
137 IO_L11P_1/A2
136 IP/VREF_1
135 IO_L10N_1/A3/RHCLK7
134 IO_L10P_1/A4/RHCLK6
133 IO_L09N_1/A5/RHCLK5
132 IO_L09P_1/A6/RHCLK4
131 GND
130 IP
129 IO_L08N_1/A7/RHCLK3
128 IO_L08P_1/A8/RHCLK2
127 IO_L07N_1/A9/RHCLK1
126 IO_L07P_1/A10/RHCLK
125 VCCO_1
124 IP
123 IO_L06N_1/VREF_1
122 IO_L06P_1
121 GND
120 IO_L05N_1/A11
119 IO_L05P_1/A12
118 IP
117 VCCINT
116 IO_L04N_1
115 IO_L04P_1
114 VCCO_1
113 IO_L03N_1/VREF_1
112 IO_L03P_1
111 VCCAUX
110 IP
109 IO_L02N_1/A13
108 IO_L02P_1/A14
107 IO_L01N_1/A15
106 IO_L01P_1/A16
105 GND
Bank 2
DS312-4_04_082009
Figure 84: PQ208 Footprint (Right)
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Product Specification
185
Spartan-3E FPGA Family: Pinout Descriptions
FT256: 256-ball Fine-pitch, Thin Ball Grid Array
The 256-ball fine-pitch, thin ball grid array package, FT256,
supports three different Spartan-3E FPGAs, including the
XC3S250E, the XC3S500E, and the XC3S1200E.
to a VREF pin on the XC3S500E and XC3S1200E FPGA. If
the FPGA application uses an I/O standard that requires a
VREF voltage reference, connect the highlighted pin to the
VREF voltage supply, even though this does not actually
connect to the XC3S250E FPGA. This VREF connection on
the board allows future migration to the larger devices
without modifying the printed-circuit board.
Table 143 lists all the package pins. They are sorted by
bank number and then by pin name of the largest device.
Pins that form a differential I/O pair appear together in the
table. The table also shows the pin number for each pin and
the pin type, as defined earlier.
All other balls have nearly identical functionality on all three
devices. Table 147 summarizes the Spartan-3E footprint
migration differences for the FT256 package.
The highlighted rows indicate pinout differences between
the XC3S250E, the XC3S500E, and the XC3S1200E
FPGAs. The XC3S250E has 18 unconnected balls,
indicated as N.C. (No Connection) in Table 143 and with the
black diamond character () in Table 143 and Figure 83.
An electronic version of this package pinout table and
footprint diagram is available for download from the Xilinx
web site at:
If the table row is highlighted in tan, then this is an instance
where an unconnected pin on the XC3S250E FPGA maps
http://www.xilinx.com/support/documentation/data_sheets
/s3e_pin.zip
Pinout Table
Table 143: FT256 Package Pinout
FT256
Ball
Bank
XC3S250E Pin Name
XC3S500E Pin Name
XC3S1200E Pin Name
Type
0
0
0
0
IO
IO
IO
IP
IO
IO
IO
IP
IO
IO
IO
IO
A7
I/O
I/O
I/O
A12
B4
B6
250E: INPUT
500E: INPUT
1200E: I/O
0
IP
IP
IO
B10
250E: INPUT
500E: INPUT
1200E: I/O
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO/VREF_0
IO/VREF_0
IO/VREF_0
D9
A14
B14
A13
B13
E11
D11
B11
C11
E10
D10
F9
VREF
I/O
IO_L01N_0
IO_L01N_0
IO_L01N_0
IO_L01P_0
IO_L01P_0
IO_L01P_0
I/O
IO_L03N_0/VREF_0
IO_L03P_0
IO_L03N_0/VREF_0
IO_L03P_0
IO_L03N_0/VREF_0
IO_L03P_0
VREF
I/O
IO_L04N_0
IO_L04N_0
IO_L04N_0
I/O
IO_L04P_0
IO_L04P_0
IO_L04P_0
I/O
IO_L05N_0/VREF_0
IO_L05P_0
IO_L05N_0/VREF_0
IO_L05P_0
IO_L05N_0/VREF_0
IO_L05P_0
VREF
I/O
IO_L06N_0
IO_L06N_0
IO_L06N_0
I/O
IO_L06P_0
IO_L06P_0
IO_L06P_0
I/O
IO_L08N_0/GCLK5
IO_L08P_0/GCLK4
IO_L09N_0/GCLK7
IO_L09P_0/GCLK6
IO_L11N_0/GCLK11
IO_L11P_0/GCLK10
IO_L12N_0
IO_L08N_0/GCLK5
IO_L08P_0/GCLK4
IO_L09N_0/GCLK7
IO_L09P_0/GCLK6
IO_L11N_0/GCLK11
IO_L11P_0/GCLK10
IO_L12N_0
IO_L08N_0/GCLK5
IO_L08P_0/GCLK4
IO_L09N_0/GCLK7
IO_L09P_0/GCLK6
IO_L11N_0/GCLK11
IO_L11P_0/GCLK10
IO_L12N_0
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
I/O
E9
A9
A10
D8
C8
F8
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186
Spartan-3E FPGA Family: Pinout Descriptions
FT256
Table 143: FT256 Package Pinout (Cont’d)
Bank
XC3S250E Pin Name
XC3S500E Pin Name
XC3S1200E Pin Name
Type
Ball
0
0
IO_L12P_0
IO_L12P_0
IO_L12P_0
IO_L13N_0
E8
I/O
N.C. ()
N.C. ()
IO_L13N_0
IO_L13P_0
C7
250E: N.C.
500E: I/O
1200E: I/O
0
IO_L13P_0
B7
250E: N.C.
500E: I/O
1200E: I/O
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
IO_L14N_0/VREF_0
IO_L14P_0
IO_L15N_0
IO_L15P_0
IO_L17N_0/VREF_0
IO_L17P_0
IO_L18N_0
IO_L18P_0
IO_L19N_0/HSWAP
IO_L19P_0
IP
IO_L14N_0/VREF_0
IO_L14P_0
IO_L14N_0/VREF_0
IO_L14P_0
D7
E7
VREF
I/O
IO_L15N_0
IO_L15N_0
D6
I/O
IO_L15P_0
IO_L15P_0
C6
I/O
IO_L17N_0/VREF_0
IO_L17P_0
IO_L17N_0/VREF_0
IO_L17P_0
A4
VREF
I/O
A5
IO_L18N_0
IO_L18N_0
C4
I/O
IO_L18P_0
IO_L18P_0
C5
I/O
IO_L19N_0/HSWAP
IO_L19P_0
IO_L19N_0/HSWAP
IO_L19P_0
B3
DUAL
I/O
C3
IP
IP
A3
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
GCLK
GCLK
INPUT
INPUT
VCCO
VCCO
VCCO
VCCO
DUAL
DUAL
DUAL
DUAL
IP
IP
IP
C13
C12
D12
C9
IP_L02N_0
IP_L02N_0
IP_L02N_0
IP_L02P_0
IP_L02P_0
IP_L02P_0
IP_L07N_0
IP_L07N_0
IP_L07N_0
IP_L07P_0
IP_L07P_0
IP_L07P_0
C10
B8
IP_L10N_0/GCLK9
IP_L10P_0/GCLK8
IP_L16N_0
IP_L10N_0/GCLK9
IP_L10P_0/GCLK8
IP_L16N_0
IP_L10N_0/GCLK9
IP_L10P_0/GCLK8
IP_L16N_0
A8
E6
IP_L16P_0
IP_L16P_0
IP_L16P_0
D5
VCCO_0
VCCO_0
VCCO_0
B5
VCCO_0
VCCO_0
VCCO_0
B12
F7
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
F10
R15
R16
P15
P16
N15
IO_L01N_1/A15
IO_L01P_1/A16
IO_L02N_1/A13
IO_L02P_1/A14
N.C. ()
IO_L01N_1/A15
IO_L01P_1/A16
IO_L02N_1/A13
IO_L02P_1/A14
IO_L03N_1/VREF_1
IO_L01N_1/A15
IO_L01P_1/A16
IO_L02N_1/A13
IO_L02P_1/A14
IO_L03N_1/VREF_1
250E: N.C.
500E: VREF
1200E: VREF
1
N.C. ()
IO_L03P_1
IO_L03P_1
N14
250E: N.C.
500E: I/O
1200E: I/O
1
1
1
IO_L04N_1/VREF_1
IO_L04P_1
IO_L04N_1/VREF_1
IO_L04P_1
IO_L04N_1/VREF_1
IO_L04P_1
M16
N16
L13
VREF
I/O
N.C. ()
IO_L05N_1
IO_L05N_1
250E: N.C.
500E: I/O
1200E: I/O
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187
Spartan-3E FPGA Family: Pinout Descriptions
FT256
Table 143: FT256 Package Pinout (Cont’d)
Bank
XC3S250E Pin Name
N.C. ()
XC3S500E Pin Name
IO_L05P_1
XC3S1200E Pin Name
Type
Ball
1
IO_L05P_1
L12
250E: N.C.
500E: I/O
1200E: I/O
1
1
1
1
1
1
1
1
1
IO_L06N_1
IO_L06N_1
IO_L06N_1
L15
L14
K12
K13
K14
K15
J16
K16
J13
I/O
I/O
IO_L06P_1
IO_L06P_1
IO_L06P_1
IO_L07N_1/A11
IO_L07P_1/A12
IO_L08N_1/VREF_1
IO_L08P_1
IO_L07N_1/A11
IO_L07P_1/A12
IO_L08N_1/VREF_1
IO_L08P_1
IO_L07N_1/A11
IO_L07P_1/A12
IO_L08N_1/VREF_1
IO_L08P_1
DUAL
DUAL
VREF
I/O
IO_L09N_1/A9/RHCLK1
IO_L09P_1/A10/RHCLK0
IO_L09N_1/A9/RHCLK1
IO_L09P_1/A10/RHCLK0
IO_L09N_1/A9/RHCLK1
IO_L09P_1/A10/RHCLK0
RHCLK/DUAL
RHCLK/DUAL
RHCLK/DUAL
IO_L10N_1/A7/RHCLK3/
TRDY1
IO_L10N_1/A7/RHCLK3/
TRDY1
IO_L10N_1/A7/RHCLK3/
TRDY1
1
1
1
IO_L10P_1/A8/RHCLK2
IO_L11N_1/A5/RHCLK5
IO_L10P_1/A8/RHCLK2
IO_L11N_1/A5/RHCLK5
IO_L10P_1/A8/RHCLK2
IO_L11N_1/A5/RHCLK5
J14
H14
H15
RHCLK/DUAL
RHCLK/DUAL
RHCLK/DUAL
IO_L11P_1/A6/RHCLK4/
IRDY1
IO_L11P_1/A6/RHCLK4/
IRDY1
IO_L11P_1/A6/RHCLK4/
IRDY1
1
1
1
1
1
1
1
1
1
1
1
IO_L12N_1/A3/RHCLK7
IO_L12P_1/A4/RHCLK6
IO_L13N_1/A1
IO_L13P_1/A2
IO_L14N_1/A0
IO_L14P_1
IO_L12N_1/A3/RHCLK7
IO_L12P_1/A4/RHCLK6
IO_L13N_1/A1
IO_L13P_1/A2
IO_L14N_1/A0
IO_L14P_1
IO_L12N_1/A3/RHCLK7
IO_L12P_1/A4/RHCLK6
IO_L13N_1/A1
IO_L13P_1/A2
IO_L14N_1/A0
IO_L14P_1
H11
H12
G16
G15
G14
G13
F15
F14
F12
F13
E16
RHCLK/DUAL
RHCLK/DUAL
DUAL
DUAL
DUAL
I/O
IO_L15N_1
IO_L15N_1
IO_L15N_1
I/O
IO_L15P_1
IO_L15P_1
IO_L15P_1
I/O
IO_L16N_1
IO_L16N_1
IO_L16N_1
I/O
IO_L16P_1
IO_L16P_1
IO_L16P_1
I/O
N.C. ()
IO_L17N_1
IO_L17N_1
250E: N.C.
500E: I/O
1200E: I/O
1
N.C. ().
IO_L17P_1
IO_L17P_1
E13
250E: N.C.
500E: I/O
1200E: I/O
1
1
1
1
1
1
1
1
1
1
1
IO_L18N_1/LDC0
IO_L18N_1/LDC0
IO_L18N_1/LDC0
D14
D15
C15
C16
B16
E14
G12
H16
J11
DUAL
DUAL
DUAL
DUAL
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
IO_L18P_1/HDC
IO_L18P_1/HDC
IO_L18P_1/HDC
IO_L19N_1/LDC2
IO_L19N_1/LDC2
IO_L19N_1/LDC2
IO_L19P_1/LDC1
IO_L19P_1/LDC1
IO_L19P_1/LDC1
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
J12
M13
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188
Spartan-3E FPGA Family: Pinout Descriptions
FT256
Table 143: FT256 Package Pinout (Cont’d)
Bank
XC3S250E Pin Name
XC3S500E Pin Name
XC3S1200E Pin Name
Type
Ball
1
IO
IO
IP
M14
250E: I/O
500E: I/O
1200E: INPUT
1
IO/VREF_1
IP/VREF_1
IP/VREF_1
D16
250E: VREF(I/O)
500E:
VREF(INPUT)
1200E:
VREF(INPUT)
1
1
1
1
1
2
IP/VREF_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
IP
IP/VREF_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
IP
IP/VREF_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
IO
H13
E15
G11
K11
M15
M7
VREF
VCCO
VCCO
VCCO
VCCO
250E: INPUT
500E: INPUT
1200E: I/O
2
IP
IP
IO
T12
250E: INPUT
500E: INPUT
1200E: I/O
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO/D5
IO/D5
IO/D5
T8
T10
P13
R4
P4
P3
N5
P5
T5
DUAL
DUAL
VREF
VREF
DUAL
DUAL
DUAL
DUAL
I/O
IO/M1
IO/M1
IO/M1
IO/VREF_2
IO/VREF_2
IO/VREF_2
IO/VREF_2
IO/VREF_2
IO/VREF_2
IO_L01N_2/INIT_B
IO_L01P_2/CSO_B
IO_L03N_2/MOSI/CSI_B
IO_L03P_2/DOUT/BUSY
IO_L04N_2
IO_L01N_2/INIT_B
IO_L01P_2/CSO_B
IO_L03N_2/MOSI/CSI_B
IO_L03P_2/DOUT/BUSY
IO_L04N_2
IO_L01N_2/INIT_B
IO_L01P_2/CSO_B
IO_L03N_2/MOSI/CSI_B
IO_L03P_2/DOUT/BUSY
IO_L04N_2
IO_L04P_2
IO_L04P_2
IO_L04P_2
T4
I/O
IO_L05N_2
IO_L05N_2
IO_L05N_2
N6
M6
P6
R6
P7
I/O
IO_L05P_2
IO_L05P_2
IO_L05P_2
I/O
IO_L06N_2
IO_L06N_2
IO_L06N_2
I/O
IO_L06P_2
IO_L06P_2
IO_L06P_2
I/O
N.C. ()
IO_L07N_2
IO_L07N_2
250E: N.C.
500E: I/O
1200E: I/O
2
N.C. ()
IO_L07P_2
IO_L07P_2
N7
250E: N.C.
500E: I/O
1200E: I/O
2
2
2
2
2
2
2
2
IO_L09N_2/D6/GCLK13
IO_L09P_2/D7/GCLK12
IO_L10N_2/D3/GCLK15
IO_L10P_2/D4/GCLK14
IO_L12N_2/D1/GCLK3
IO_L12P_2/D2/GCLK2
IO_L13N_2/DIN/D0
IO_L09N_2/D6/GCLK13
IO_L09P_2/D7/GCLK12
IO_L10N_2/D3/GCLK15
IO_L10P_2/D4/GCLK14
IO_L12N_2/D1/GCLK3
IO_L12P_2/D2/GCLK2
IO_L13N_2/DIN/D0
IO_L09N_2/D6/GCLK13
IO_L09P_2/D7/GCLK12
IO_L10N_2/D3/GCLK15
IO_L10P_2/D4/GCLK14
IO_L12N_2/D1/GCLK3
IO_L12P_2/D2/GCLK2
IO_L13N_2/DIN/D0
L8
M8
P8
N8
N9
P9
M9
L9
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL
IO_L13P_2/M0
IO_L13P_2/M0
IO_L13P_2/M0
DUAL
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189
Spartan-3E FPGA Family: Pinout Descriptions
FT256
Table 143: FT256 Package Pinout (Cont’d)
Bank
XC3S250E Pin Name
N.C. ()
XC3S500E Pin Name
XC3S1200E Pin Name
Type
Ball
2
IO_L14N_2/VREF_2
IO_L14N_2/VREF_2
R10
250E: N.C.
500E: VREF
1200E: VREF
2
N.C. ()
IO_L14P_2
IO_L14P_2
P10
250E: N.C.
500E: I/O
1200E: I/O
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO_L15N_2
IO_L15N_2
IO_L15N_2
M10
N10
P11
R11
N12
P12
R13
T13
R14
P14
T2
I/O
I/O
IO_L15P_2
IO_L15P_2
IO_L15P_2
IO_L16N_2/A22
IO_L16P_2/A23
IO_L18N_2/A20
IO_L18P_2/A21
IO_L19N_2/VS1/A18
IO_L19P_2/VS2/A19
IO_L20N_2/CCLK
IO_L20P_2/VS0/A17
IP
IO_L16N_2/A22
IO_L16P_2/A23
IO_L18N_2/A20
IO_L18P_2/A21
IO_L19N_2/VS1/A18
IO_L19P_2/VS2/A19
IO_L20N_2/CCLK
IO_L20P_2/VS0/A17
IP
IO_L16N_2/A22
IO_L16P_2/A23
IO_L18N_2/A20
IO_L18P_2/A21
IO_L19N_2/VS1/A18
IO_L19P_2/VS2/A19
IO_L20N_2/CCLK
IO_L20P_2/VS0/A17
IP
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
INPUT
INPUT
INPUT
INPUT
VREF
IP
IP
IP
T14
R3
IP_L02N_2
IP_L02N_2
IP_L02N_2
IP_L02P_2
IP_L02P_2
IP_L02P_2
T3
IP_L08N_2/VREF_2
IP_L08P_2
IP_L08N_2/VREF_2
IP_L08P_2
IP_L08N_2/VREF_2
IP_L08P_2
T7
R7
INPUT
DUAL/GCLK
DUAL/GCLK
IP_L11N_2/M2/GCLK1
IP_L11N_2/M2/GCLK1
IP_L11N_2/M2/GCLK1
R9
IP_L11P_2/RDWR_B/
GCLK0
IP_L11P_2/RDWR_B/
GCLK0
IP_L11P_2/RDWR_B/
GCLK0
T9
2
2
2
2
2
2
3
3
3
3
3
3
3
IP_L17N_2
IP_L17P_2
VCCO_2
IP_L17N_2
IP_L17P_2
VCCO_2
IP_L17N_2
IP_L17P_2
VCCO_2
M11
N11
L7
INPUT
INPUT
VCCO
VCCO
VCCO
VCCO
I/O
VCCO_2
VCCO_2
VCCO_2
L10
R5
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
R12
B2
IO_L01N_3
IO_L01P_3
IO_L02N_3/VREF_3
IO_L02P_3
IO_L03N_3
IO_L03P_3
N.C. ()
IO_L01N_3
IO_L01P_3
IO_L02N_3/VREF_3
IO_L02P_3
IO_L03N_3
IO_L03P_3
IO_L04N_3/VREF_3
IO_L01N_3
IO_L01P_3
IO_L02N_3/VREF_3
IO_L02P_3
IO_L03N_3
IO_L03P_3
IO_L04N_3/VREF_3
B1
I/O
C2
VREF
I/O
C1
E4
I/O
E3
I/O
F4
250E: N.C.
500E: VREF
1200E: VREF
3
N.C. ()
IO_L04P_3
IO_L04P_3
F3
250E: N.C.
500E: I/O
1200E: I/O
3
3
3
IO_L05N_3
IO_L05P_3
IO_L06N_3
IO_L05N_3
IO_L05P_3
IO_L06N_3
IO_L05N_3
IO_L05P_3
IO_L06N_3
E1
D1
G4
I/O
I/O
I/O
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190
Spartan-3E FPGA Family: Pinout Descriptions
FT256
Table 143: FT256 Package Pinout (Cont’d)
Bank
XC3S250E Pin Name
XC3S500E Pin Name
XC3S1200E Pin Name
Type
Ball
G5
G2
G3
H6
H5
H4
3
3
3
3
3
3
IO_L06P_3
IO_L06P_3
IO_L06P_3
I/O
I/O
IO_L07N_3
IO_L07N_3
IO_L07N_3
IO_L07P_3
IO_L07P_3
IO_L07P_3
I/O
IO_L08N_3/LHCLK1
IO_L08P_3/LHCLK0
IO_L08N_3/LHCLK1
IO_L08P_3/LHCLK0
IO_L08N_3/LHCLK1
IO_L08P_3/LHCLK0
LHCLK
LHCLK
LHCLK
IO_L09N_3/LHCLK3/
IRDY2
IO_L09N_3/LHCLK3/
IRDY2
IO_L09N_3/LHCLK3/
IRDY2
3
3
3
IO_L09P_3/LHCLK2
IO_L10N_3/LHCLK5
IO_L09P_3/LHCLK2
IO_L10N_3/LHCLK5
IO_L09P_3/LHCLK2
IO_L10N_3/LHCLK5
H3
J3
J2
LHCLK
LHCLK
LHCLK
IO_L10P_3/LHCLK4/
TRDY2
IO_L10P_3/LHCLK4/
TRDY2
IO_L10P_3/LHCLK4/
TRDY2
3
3
3
3
3
3
3
IO_L11N_3/LHCLK7
IO_L11P_3/LHCLK6
IO_L12N_3
IO_L11N_3/LHCLK7
IO_L11P_3/LHCLK6
IO_L12N_3
IO_L11N_3/LHCLK7
IO_L11P_3/LHCLK6
IO_L12N_3
J4
J5
K1
J1
K3
K2
L2
LHCLK
LHCLK
I/O
IO_L12P_3
IO_L12P_3
IO_L12P_3
I/O
IO_L13N_3
IO_L13N_3
IO_L13N_3
I/O
IO_L13P_3
IO_L13P_3
IO_L13P_3
I/O
N.C. ()
IO_L14N_3/VREF_3
IO_L14N_3/VREF_3
250E: N.C.
500E: VREF
1200E: VREF
3
N.C. ()
IO_L14P_3
IO_L14P_3
L3
250E: N.C.
500E: I/O
1200E: I/O
3
3
3
3
3
IO_L15N_3
IO_L15P_3
IO_L16N_3
IO_L16P_3
N.C. ()
IO_L15N_3
IO_L15P_3
IO_L16N_3
IO_L16P_3
IO_L17N_3
IO_L15N_3
IO_L15P_3
IO_L16N_3
IO_L16P_3
IO_L17N_3
L5
K5
N1
M1
L4
I/O
I/O
I/O
I/O
250E: N.C.
500E: I/O
1200E: I/O
3
N.C. ()
IO_L17P_3
IO_L17P_3
M4
250E: N.C.
500E: I/O
1200E: I/O
3
3
3
3
3
3
3
IO_L18N_3
IO_L18P_3
IO_L19N_3
IO_L19P_3
IP
IO_L18N_3
IO_L18P_3
IO_L19N_3
IO_L19P_3
IP
IO_L18N_3
IO_L18P_3
IO_L19N_3
IO_L19P_3
IP
P1
P2
R1
R2
D2
F2
F5
I/O
I/O
I/O
I/O
INPUT
INPUT
IP
IP
IP
IO
IO
IP
250E: I/O
500E: I/O
1200E: INPUT
3
3
3
3
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
H1
J6
INPUT
INPUT
INPUT
INPUT
K4
M3
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191
Spartan-3E FPGA Family: Pinout Descriptions
FT256
Table 143: FT256 Package Pinout (Cont’d)
Bank
XC3S250E Pin Name
XC3S500E Pin Name
XC3S1200E Pin Name
Type
Ball
3
3
3
IP
IP
IP
N3
INPUT
VREF
IP/VREF_3
IO/VREF_3
IP/VREF_3
IO/VREF_3
IP/VREF_3
IP/VREF_3
G1
N2
250E: VREF(I/O)
500E: VREF(I/O)
1200E:
VREF(INPUT)
3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCCO_3
VCCO_3
VCCO_3
VCCO_3
GND
VCCO_3
VCCO_3
VCCO_3
VCCO_3
GND
E2
G6
K6
VCCO
VCCO
VCCO
VCCO
GND
3
3
3
M2
A1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A16
B9
GND
GND
GND
GND
GND
GND
F6
GND
GND
GND
F11
G7
G8
G9
G10
H2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
H7
GND
GND
GND
H8
GND
GND
GND
H9
GND
GND
GND
H10
J7
GND
GND
GND
GND
GND
GND
J8
GND
GND
GND
J9
GND
GND
GND
J10
J15
K7
GND
GND
GND
GND
GND
GND
GND
GND
GND
K8
GND
GND
GND
K9
GND
GND
GND
K10
L6
GND
GND
GND
GND
GND
GND
L11
R8
GND
GND
GND
GND
GND
GND
T1
GND
GND
GND
T16
T15
D3
GND
VCCAUX DONE
VCCAUX PROG_B
VCCAUX TCK
VCCAUX TDI
DONE
PROG_B
TCK
DONE
PROG_B
TCK
CONFIG
CONFIG
JTAG
JTAG
JTAG
JTAG
VCCAUX
A15
A2
TDI
TDI
VCCAUX TDO
VCCAUX TMS
VCCAUX VCCAUX
TDO
TDO
C14
B15
A6
TMS
TMS
VCCAUX
VCCAUX
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192
Spartan-3E FPGA Family: Pinout Descriptions
FT256
Table 143: FT256 Package Pinout (Cont’d)
Bank XC3S250E Pin Name XC3S500E Pin Name
VCCAUX
XC3S1200E Pin Name
Type
Ball
A11
F1
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
F16
L1
L16
T6
T11
D4
D13
E5
E12
M5
M12
N4
N13
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193
Spartan-3E FPGA Family: Pinout Descriptions
The XC3S250E FPGA in the FT256 package has 18
unconnected balls, labeled with an “N.C.” type. These pins
are also indicated with the black diamond () symbol in
Figure 85.
User I/Os by Bank
Table 144, Table 145, and Table 146 indicate how the
available user-I/O pins are distributed between the four I/O
banks on the FT256 package.
Table 144: User I/Os Per Bank on XC3S250E in the FT256 Package
All Possible I/O Pins by Type
Package
I/O Bank
Maximum I/O
Edge
(2)
I/O
20
10
8
INPUT
DUAL
1
VREF(1)
CLK
Top
0
1
2
3
44
42
10
7
5
4
8
Right
21
24
0
0(2)
0(2)
8
Bottom
Left
44
9
3
42
24
62
7
3
TOTAL
172
33
46
15
16
Notes:
1. Some VREF and CLK pins are on INPUT pins.
2. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
Table 145: User I/Os Per Bank on XC3S500E in the FT256 Package
All Possible I/O Pins by Type
Package
I/O Bank
Maximum I/O
Edge
(2)
I/O
22
15
11
28
76
INPUT
DUAL
VREF(1)
CLK
8
Top
0
1
2
3
46
48
10
7
1
5
5
Right
21
24
0
0(2)
0(2)
8
Bottom
Left
48
9
4
48
7
5
TOTAL
190
33
46
19
16
Notes:
1. Some VREF and CLK pins are on INPUT pins.
2. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
.
Table 146: User I/Os Per Bank on XC3S1200E in the FT256 Package
All Possible I/O Pins by Type
Package
Edge
I/O Bank
Maximum I/O
(2)
I/O
24
14
13
27
78
INPUT
DUAL
1
VREF(1)
CLK
8
Top
0
1
2
3
46
48
8
8
5
5
Right
21
24
0
0(2)
0(2)
8
Bottom
Left
48
7
4
48
8
5
TOTAL
190
31
46
19
16
Notes:
1. Some VREF and CLK pins are on INPUT pins.
2. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
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Spartan-3E FPGA Family: Pinout Descriptions
Footprint Migration Differences
Table 147 summarizes any footprint and functionality
differences between the XC3S250E, the XC3S500E, and
the XC3S1200E FPGAs that may affect easy migration
between devices in the FG256 package. There are 26 such
balls. All other pins not listed in Table 147 unconditionally
migrate between Spartan-3E devices available in the FT256
package.
and the XC3S1200E. The arrows indicate the direction for
easy migration. A double-ended arrow () indicates that
the two pins have identical functionality. A left-facing arrow
() indicates that the pin on the device on the right
unconditionally migrates to the pin on the device on the left.
It may be possible to migrate the opposite direction
depending on the I/O configuration. For example, an I/O pin
(Type = I/O) can migrate to an input-only pin
The XC3S250E is duplicated on both the left and right sides
of the table to show migrations to and from the XC3S500E
(Type = INPUT) if the I/O pin is configured as an input.
Table 147: FT256 Footprint Migration Differences
FT256
Ball
XC3S250E
Type
XC3S250E
Migration XC3S1200E Type Migration
Type
Bank
Migration
XC3S500E Type
B6
B7
0
0
0
0
1
1
1
3
3
3
3
3
3
1
1
3
2
1
3
2
1
1
2
2
2
2
INPUT
N.C.
INPUT
I/O
I/O
26
INPUT
N.C.
I/O
B10
C7
INPUT
N.C.
INPUT
I/O
I/O
INPUT
N.C.
I/O
D16
E13
E16
F3
VREF(I/O)
N.C.
VREF(INPUT)
I/O
VREF(INPUT)
VREF(I/O)
N.C.
I/O
N.C.
I/O
I/O
N.C.
N.C.
I/O
I/O
N.C.
F4
N.C.
VREF
I/O
VREF
INPUT
VREF
I/O
N.C.
F5
I/O
I/O
L2
N.C.
VREF
I/O
N.C.
L3
N.C.
N.C.
L4
N.C.
I/O
I/O
N.C.
L12
L13
M4
M7
M14
N2
N.C.
I/O
I/O
N.C.
N.C.
I/O
I/O
N.C.
N.C.
I/O
I/O
N.C.
INPUT
I/O
INPUT
I/O
I/O
INPUT
I/O
INPUT
VREF(INPUT)
I/O
VREF(I/O)
N.C.
VREF(I/O)
I/O
VREF(I/O)
N.C.
N7
N14
N15
P7
N.C.
I/O
I/O
N.C.
N.C.
VREF
I/O
VREF
I/O
N.C.
N.C.
N.C.
P10
R10
T12
N.C.
I/O
I/O
N.C.
N.C.
VREF
INPUT
VREF
I/O
N.C.
INPUT
19
INPUT
DIFFERENCES
7
Legend:
This pin is identical on the device on the left and the right.
This pin can unconditionally migrate from the device on the left to the device on the right. Migration in the other direction may be
possible depending on how the pin is configured for the device on the right.
This pin can unconditionally migrate from the device on the right to the device on the left. Migration in the other direction may be
possible depending on how the pin is configured for the device on the left.
DS312 (v4.1) July 19, 2013
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Product Specification
195
Spartan-3E FPGA Family: Pinout Descriptions
FT256 Footprint
X-Ref Target
-
Figure 85
Bank 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
I/O
L17N_0
VREF_0
INPUT
L10P_0
GCLK8
I/O
L09N_0
GCLK7
I/O
L09P_0
GCLK6
I/O
L03N_0
VREF_0
I/O
L17P_0
I/O
L01N_0
VCCAUX
VCCAUX
GND
TDI
INPUT
I/O
I/O
TCK
GND
A
B
C
D
E
F
I/O
L13P_0
I/O
L19N_0
HSWAP
INPUT
L10N_0
GCLK9
I/O
L05N_0
VREF_0
INPUT
INPUT
I/O
L01P_3
I/O
L01N_3
I/O
L03P_0
I/O
L01P_0
VCCO_0
VCCO_0
I/O
GND
TMS
INPUT
I/O
L13N_0
I/O
L02N_3
VREF_3
I/O
L11P_0
GCLK10
I/O
L19N_1
LDC2
I/O
L19P_1
LDC1
I/O
L02P_3
I/O
L19P_0
I/O
L18N_0
I/O
L18P_0
I/O
L15P_0
INPUT INPUT
I/O
L05P_0
INPUT
L02N_0
INPUT
TDO
L07N_0
L07P_0
INPUT
VREF_1
I/O
L14N_0
VREF_0 GCLK11
I/O
L11N_0
I/O
L18N_1
LDC0
I/O
L18P_1
HDC
I/O
L05P_3
INPUT
L16P_0
I/O
L15N_0
I/O
VREF_0
I/O
L06P_0
I/O
L04P_0
INPUT
L02P_0
PROG_B
INPUT
VCCINT
VCCINT
I/O
L17P_1
I/O
L17N_1
I/O
L08P_0
GCLK4
I/O
L05N_3
I/O
L03P_3
I/O
L03N_3
INPUT
L16N_0
I/O
L14P_0
I/O
L12P_0
I/O
L06N_0
I/O
L04N_0
VCCO_3
VCCO_1
VCCINT
VCCINT
INPUT
I/O
L04N_3
VREF_3
I/O
L04P_3
I/O
L08N_0
GCLK5
INPUT
I/O
L12N_0
I/O
L16N_1
I/O
L16P_1
I/O
L15P_1
I/O
L15N_1
VCCAUX
VCCO_0
GND
VCCO_0
GND
VCCAUX
INPUT
I/O
GND
GND
I/O
L14N_1
A0
I/O
L13P_1
A2
I/O
L13N_1
A1
INPUT
VREF_3 L07N_3
I/O
L07P_3
I/O
L06N_3
I/O
L06P_3
I/O
L14P_1
VCCO_3
VCCO_1
GND
GND
GND
GND
GND
GND
GND
INPUT
I/O
L12P_1
A4
G
H
J
I/O
L11P_1
A6
I/O
L09N_3
LHCLK3
IRDY2
I/O
I/O
I/O
L09P_3
LHCLK2
I/O
L08P_3
I/O
L08N_3
LHCLK0 LHCLK1
INPUT
VREF_1
L12N_1
A3
L11N_1
A5
INPUT
GND
I/O
L10P_3
LHCLK4
TRDY2
GND
GND
INPUT
I/O
L09N_1
A9
RHCLK1
RHCLK4
IRDY1
RHCLK7 RHCLK6
RHCLK5
I/O
I/O
I/O
L10N_3
I/O
L11N_3
I/O
L11P_3
L10N_1
I/O
L12P_3
L10P_1
A8
INPUT
VCCO_3
GND
GND
GND
INPUT INPUT
GND
A7
RHCLK3
LHCLK5 LHCLK7 LHCLK6
RHCLK2
TRDY1
I/O
I/O
I/O
L07P_1
A12
I/O
L08N_1
VREF_1
I/O
L12N_3
I/O
L13P_3
I/O
L13N_3
I/O
L15P_3
I/O
L08P_1
L09P_1
A10
VCCO_1
L07N_1
INPUT
GND
GND
I/O
L09N_2
D6
GCLK13
GND
K
L
A11
RHCLK0
I/O
L14N_3
VREF_3
I/O
L14P_3
I/O
L17N_3
I/O
L05P_1
I/O
L05N_1
I/O
L13P_2
M0
I/O
L15N_3
I/O
L06P_1
I/O
L06N_1
VCCAUX
VCCO_2
VCCO_2
VCCAUX
GND
I/O
I/O
I/O
I/O
L04N_1
VREF_1
INPUT
INPUT
I/O
L16P_3
I/O
L05P_2
I/O
L15N_2
INPUT
L17N_2
L09P_2
D7
L13N_2
DIN
VCCO_3
VCCO_1
INPUT L17P_3 VCCINT
VCCINT INPUT
M
N
P
R
T
GCLK12
D0
I/O
INPUT
VREF_3
I/O
L07P_2
I/O
L03P_1
I/O
I/O
I/O
I/O
L18N_2
A20
I/O
L16N_3
I/O
L05N_2
I/O
L15P_2
INPUT
L17P_2
I/O
L04P_1
L03N_1
VREF_1
L03N_2
L10P_2
D4
L12N_2
D1
INPUT VCCINT
VCCINT
MOSI
CSI_B
GCLK14
GCLK3
I/O
L07N_2
I/O
L14P_2
I/O
L03P_2
DOUT
BUSY
I/O
I/O
I/O
I/O
L01P_2
I/O
L01N_2
I/O
L16N_2
A22
I/O
L18P_2
A21
I/O
L02N_1
A13
I/O
L02P_1
A14
I/O
L18N_3
I/O
L18P_3
I/O
L06N_2
I/O
VREF_2
L10N_2
D3
L12P_2
D2
L20P_2
VS0
CSO_B
INIT_B
GCLK15
GCLK2
A17
I/O
L14N_2
VREF_2
INPUT
I/O
I/O
L16P_2
A23
I/O
L20N_2
CCLK
I/O
L01N_1
A15
I/O
L01P_1
A16
I/O
L19N_3
I/O
L19P_3
INPUT
I/O
I/O
L06P_2
INPUT
L08P_2
L11N_2
M2
L19N_2
VS1
VCCO_2
VCCO_2
GND
L02N_2 VREF_2
GCLK1
A18
INPUT
L11P_2
RDWR_B
GCLK0
I/O
INPUT
L08N_2
VREF_2
INPUT
INPUT
L02P_2
I/O
L04P_2
I/O
L04N_2
I/O
D5
I/O
M1
L19P_2
VS2
VCCAUX
VCCAUX
GND
INPUT
INPUT DONE
GND
A19
Bank 2
DS312-4_05_101805
Figure 85: FT256 Package Footprint (top view)
CONFIG: Dedicated configuration
JTAG: Dedicated JTAG port pins
VCCINT: Internal core supply
2
4
8
8
pins
voltage (+1.2V)
GND: Ground
VCCO: Output voltage supply for
bank
VCCAUX: Auxiliary supply voltage
(+2.5V)
28
6
16
Migration Difference: For flexible
package migration, use these pins
as inputs.
Unconnected pins on XC3S250E
18
()
DS312 (v4.1) July 19, 2013
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Product Specification
196
Spartan-3E FPGA Family: Pinout Descriptions
FG320: 320-ball Fine-pitch Ball Grid Array
The 320-ball fine-pitch ball grid array package, FG320,
supports three different Spartan-3E FPGAs, including the
XC3S500E, the XC3S1200E, and the XC3S1600E, as
shown in Table 148 and Figure 86.
If the table row is highlighted in tan, then this is an instance
where an unconnected pin on the XC3S500E FPGA maps
to a VREF pin on the XC3S1200E and XC3S1600E FPGA.
If the FPGA application uses an I/O standard that requires a
VREF voltage reference, connect the highlighted pin to the
VREF voltage supply, even though this does not actually
connect to the XC3S500E FPGA. This VREF connection on
the board allows future migration to the larger devices
without modifying the printed-circuit board.
The FG320 package is an 18 x 18 array of solder balls
minus the four center balls.
Table 148 lists all the package pins. They are sorted by
bank number and then by pin name of the largest device.
Pins that form a differential I/O pair appear together in the
table. The table also shows the pin number for each pin and
the pin type, as defined earlier.
All other balls have nearly identical functionality on all three
devices. Table 147 summarizes the Spartan-3E footprint
migration differences for the FG320 package.
The highlighted rows indicate pinout differences between
the XC3S500E, the XC3S1200E, and the XC3S1600E
FPGAs. The XC3S500E has 18 unconnected balls,
indicated as N.C. (No Connection) in Table 148 and with the
black diamond character () in Table 148 and Figure 86.
An electronic version of this package pinout table and
footprint diagram is available for download from the Xilinx
web site at:
http://www.xilinx.com/support/documentation/data_sheets
/s3e_pin.zip
Pinout Table
Table 148: FG320 Package Pinout
FG320
Ball
Bank
XC3S500E Pin Name
XC3S1200E Pin Name
XC3S1600E Pin Name
Type
0
IP
IO
IO
A7
500E: INPUT
1200E: I/O
1600E: I/O
0
0
0
IO
IO
IO
IO
IO
IO
IO
IO
A8
I/O
I/O
A11
A12
N.C. ()
500E: N.C.
1200E: I/O
1600E: I/O
0
0
IO
IP
IO
IO
IO
IO
C4
I/O
D13
500E: INPUT
1200E: I/O
1600E: I/O
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO
IO
IO
IO
IO
E13
G9
I/O
I/O
IO
IO/VREF_0
IO_L01N_0
IO_L01P_0
IO_L03N_0/VREF_0
IO_L03P_0
IO_L04N_0
IO_L04P_0
IO_L05N_0/VREF_0
IO_L05P_0
IO_L06N_0
IO_L06P_0
IO_L08N_0
IO/VREF_0
IO/VREF_0
B11
A16
B16
C14
D14
A14
B14
B13
A13
E12
F12
F11
VREF
I/O
IO_L01N_0
IO_L01N_0
IO_L01P_0
IO_L01P_0
I/O
IO_L03N_0/VREF_0
IO_L03P_0
IO_L03N_0/VREF_0
IO_L03P_0
VREF
I/O
IO_L04N_0
IO_L04N_0
I/O
IO_L04P_0
IO_L04P_0
I/O
IO_L05N_0/VREF_0
IO_L05P_0
IO_L05N_0/VREF_0
IO_L05P_0
VREF
I/O
IO_L06N_0
IO_L06N_0
I/O
IO_L06P_0
IO_L06P_0
I/O
IO_L08N_0
IO_L08N_0
I/O
DS312 (v4.1) July 19, 2013
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Product Specification
197
Spartan-3E FPGA Family: Pinout Descriptions
FG320
Table 148: FG320 Package Pinout (Cont’d)
Bank
XC3S500E Pin Name
IO_L08P_0
XC3S1200E Pin Name
XC3S1600E Pin Name
Type
Ball
E11
D11
C11
E10
D10
A10
B10
D9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO_L08P_0
IO_L08P_0
I/O
I/O
IO_L09N_0
IO_L09N_0
IO_L09N_0
IO_L09P_0
IO_L09P_0
IO_L09P_0
I/O
IO_L11N_0/GCLK5
IO_L11P_0/GCLK4
IO_L12N_0/GCLK7
IO_L12P_0/GCLK6
IO_L14N_0/GCLK11
IO_L14P_0/GCLK10
IO_L15N_0
IO_L11N_0/GCLK5
IO_L11P_0/GCLK4
IO_L12N_0/GCLK7
IO_L12P_0/GCLK6
IO_L14N_0/GCLK11
IO_L14P_0/GCLK10
IO_L15N_0
IO_L11N_0/GCLK5
IO_L11P_0/GCLK4
IO_L12N_0/GCLK7
IO_L12P_0/GCLK6
IO_L14N_0/GCLK11
IO_L14P_0/GCLK10
IO_L15N_0
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
I/O
C9
F9
IO_L15P_0
IO_L15P_0
IO_L15P_0
E9
I/O
IO_L17N_0
IO_L17N_0
IO_L17N_0
F8
I/O
IO_L17P_0
IO_L17P_0
IO_L17P_0
E8
I/O
IO_L18N_0/VREF_0
IO_L18P_0
IO_L18N_0/VREF_0
IO_L18P_0
IO_L18N_0/VREF_0
IO_L18P_0
D7
VREF
I/O
C7
IO_L19N_0/VREF_0
IO_L19P_0
IO_L19N_0/VREF_0
IO_L19P_0
IO_L19N_0/VREF_0
IO_L19P_0
E7
VREF
I/O
F7
IO_L20N_0
IO_L20N_0
IO_L20N_0
A6
I/O
IO_L20P_0
IO_L20P_0
IO_L20P_0
B6
I/O
N.C. ()
IO_L21N_0
IO_L21N_0
E6
500E: N.C.
1200E: I/O
1600E: I/O
0
N.C. ()
IO_L21P_0
IO_L21P_0
D6
500E: N.C.
1200E: I/O
1600E: I/O
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO_L23N_0/VREF_0
IO_L23P_0
IO_L24N_0
IO_L24P_0
IO_L25N_0/HSWAP
IO_L25P_0
IP
IO_L23N_0/VREF_0
IO_L23P_0
IO_L24N_0
IO_L24P_0
IO_L25N_0/HSWAP
IO_L25P_0
IP
IO_L23N_0/VREF_0
IO_L23P_0
IO_L24N_0
IO_L24P_0
IO_L25N_0/HSWAP
IO_L25P_0
IP
D5
C5
VREF
I/O
B4
I/O
A4
I/O
B3
DUAL
I/O
C3
A3
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
GCLK
GCLK
INPUT
INPUT
INPUT
INPUT
IP
IP
IP
C15
A15
B15
D12
C12
G10
F10
B9
IP_L02N_0
IP_L02P_0
IP_L07N_0
IP_L07P_0
IP_L10N_0
IP_L10P_0
IP_L13N_0/GCLK9
IP_L13P_0/GCLK8
IP_L16N_0
IP_L16P_0
IP_L22N_0
IP_L22P_0
IP_L02N_0
IP_L02P_0
IP_L07N_0
IP_L07P_0
IP_L10N_0
IP_L10P_0
IP_L13N_0/GCLK9
IP_L13P_0/GCLK8
IP_L16N_0
IP_L16P_0
IP_L22N_0
IP_L22P_0
IP_L02N_0
IP_L02P_0
IP_L07N_0
IP_L07P_0
IP_L10N_0
IP_L10P_0
IP_L13N_0/GCLK9
IP_L13P_0/GCLK8
IP_L16N_0
IP_L16P_0
IP_L22N_0
IP_L22P_0
B8
D8
C8
B5
A5
DS312 (v4.1) July 19, 2013
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Product Specification
198
Spartan-3E FPGA Family: Pinout Descriptions
FG320
Table 148: FG320 Package Pinout (Cont’d)
Bank
XC3S500E Pin Name
VCCO_0
XC3S1200E Pin Name
VCCO_0
XC3S1600E Pin Name
Type
Ball
0
0
0
0
0
1
VCCO_0
A9
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO_0
VCCO_0
VCCO_0
VCCO_0
N.C. ()
VCCO_0
VCCO_0
VCCO_0
VCCO_0
IO
VCCO_0
VCCO_0
VCCO_0
VCCO_0
IO
C6
C13
G8
G11
P16
500E: N.C.
1200E: I/O
1600E: I/O
1
1
1
1
1
1
1
IO_L01N_1/A15
IO_L01P_1/A16
IO_L02N_1/A13
IO_L02P_1/A14
IO_L03N_1/VREF_1
IO_L03P_1
IO_L01N_1/A15
IO_L01P_1/A16
IO_L02N_1/A13
IO_L02P_1/A14
IO_L03N_1/VREF_1
IO_L03P_1
IO_L01N_1/A15
IO_L01P_1/A16
IO_L02N_1/A13
IO_L02P_1/A14
IO_L03N_1/VREF_1
IO_L03P_1
T17
U18
T18
R18
R16
R15
N14
DUAL
DUAL
DUAL
DUAL
VREF
I/O
N.C. ()
IO_L04N_1
IO_L04N_1
500E: N.C.
1200E: I/O
1600E: I/O
1
N.C. ()
IO_L04P_1
IO_L04P_1
N15
500E: N.C.
1200E: I/O
1600E: I/O
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IO_L05N_1/VREF_1
IO_L05P_1
IO_L05N_1/VREF_1
IO_L05P_1
IO_L05N_1/VREF_1
IO_L05P_1
M13
M14
P18
P17
M16
M15
M18
N18
L15
L16
L17
L18
K12
K13
K14
VREF
I/O
IO_L06N_1
IO_L06N_1
IO_L06N_1
I/O
IO_L06P_1
IO_L06P_1
IO_L06P_1
I/O
I/O
IO_L07N_1
IO_L07N_1
IO_L07N_1
IO_L07P_1
IO_L07P_1
IO_L07P_1
I/O
IO_L08N_1
IO_L08N_1
IO_L08N_1
I/O
IO_L08P_1
IO_L08P_1
IO_L08P_1
I/O
IO_L09N_1/A11
IO_L09P_1/A12
IO_L10N_1/VREF_1
IO_L10P_1
IO_L09N_1/A11
IO_L09P_1/A12
IO_L10N_1/VREF_1
IO_L10P_1
IO_L09N_1/A11
IO_L09P_1/A12
IO_L10N_1/VREF_1
IO_L10P_1
DUAL
DUAL
VREF
I/O
IO_L11N_1/A9/RHCLK1
IO_L11P_1/A10/RHCLK0
IO_L11N_1/A9/RHCLK1
IO_L11P_1/A10/RHCLK0
IO_L11N_1/A9/RHCLK1
IO_L11P_1/A10/RHCLK0
RHCLK/DUAL
RHCLK/DUAL
RHCLK/DUAL
IO_L12N_1/A7/RHCLK3/
TRDY1
IO_L12N_1/A7/RHCLK3/
TRDY1
IO_L12N_1/A7/RHCLK3/
TRDY1
1
1
1
IO_L12P_1/A8/RHCLK2
IO_L13N_1/A5/RHCLK5
IO_L12P_1/A8/RHCLK2
IO_L13N_1/A5/RHCLK5
IO_L12P_1/A8/RHCLK2
IO_L13N_1/A5/RHCLK5
K15
J16
J17
RHCLK/DUAL
RHCLK/DUAL
RHCLK/DUAL
IO_L13P_1/A6/RHCLK4/
IRDY1
IO_L13P_1/A6/RHCLK4/
IRDY1
IO_L13P_1/A6/RHCLK4/
IRDY1
1
1
1
1
1
1
IO_L14N_1/A3/RHCLK7
IO_L14P_1/A4/RHCLK6
IO_L15N_1/A1
IO_L14N_1/A3/RHCLK7
IO_L14P_1/A4/RHCLK6
IO_L15N_1/A1
IO_L14N_1/A3/RHCLK7
IO_L14P_1/A4/RHCLK6
IO_L15N_1/A1
J14
J15
J13
J12
H17
H16
RHCLK/DUAL
RHCLK/DUAL
DUAL
IO_L15P_1/A2
IO_L15P_1/A2
IO_L15P_1/A2
DUAL
IO_L16N_1/A0
IO_L16N_1/A0
IO_L16N_1/A0
DUAL
IO_L16P_1
IO_L16P_1
IO_L16P_1
I/O
DS312 (v4.1) July 19, 2013
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Product Specification
199
Spartan-3E FPGA Family: Pinout Descriptions
FG320
Table 148: FG320 Package Pinout (Cont’d)
Bank
XC3S500E Pin Name
IO_L17N_1
XC3S1200E Pin Name
XC3S1600E Pin Name
Type
Ball
H15
H14
G16
G15
F17
F18
G13
G14
F14
F15
E16
1
1
1
1
1
1
1
1
1
1
1
IO_L17N_1
IO_L17P_1
IO_L18N_1
IO_L18P_1
IO_L19N_1
IO_L19P_1
IO_L20N_1
IO_L20P_1
IO_L21N_1
IO_L21P_1
IO_L22N_1
IO_L17N_1
IO_L17P_1
IO_L18N_1
IO_L18P_1
IO_L19N_1
IO_L19P_1
IO_L20N_1
IO_L20P_1
IO_L21N_1
IO_L21P_1
IO_L22N_1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IO_L17P_1
IO_L18N_1
IO_L18P_1
IO_L19N_1
IO_L19P_1
IO_L20N_1
IO_L20P_1
IO_L21N_1
IO_L21P_1
N.C. ()
500E: N.C.
1200E: I/O
1600E: I/O
1
N.C. ()
IO_L22P_1
IO_L22P_1
E15
500E: N.C.
1200E: I/O
1600E: I/O
1
1
1
1
1
1
IO_L23N_1/LDC0
IO_L23P_1/HDC
IO_L24N_1/LDC2
IO_L24P_1/LDC1
IP
IO_L23N_1/LDC0
IO_L23P_1/HDC
IO_L24N_1/LDC2
IO_L24P_1/LDC1
IP
IO_L23N_1/LDC0
IO_L23P_1/HDC
IO_L24N_1/LDC2
IO_L24P_1/LDC1
IP
D16
D17
C17
C18
B18
E17
DUAL
DUAL
DUAL
DUAL
INPUT
IO
IP
IP
500E: I/O
1200E: INPUT
1600E: INPUT
1
1
1
1
1
1
1
1
1
IP
IP
IP
IP
IP
IP
IP
IP
IO
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
E18
G18
H13
K17
K18
L13
L14
N17
P15
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
500E: I/O
1200E: INPUT
1600E: INPUT
1
1
1
1
1
1
1
1
2
2
IP
IP
IP
R17
D18
H18
F16
H12
J18
L12
N16
P9
INPUT
VREF
VREF
VCCO
VCCO
VCCO
VCCO
VCCO
I/O
IP/VREF_1
IP/VREF_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
IO
IP/VREF_1
IP/VREF_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
IO
IP/VREF_1
IP/VREF_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
IO
IO
IO
IO
R11
I/O
DS312 (v4.1) July 19, 2013
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Product Specification
200
Spartan-3E FPGA Family: Pinout Descriptions
FG320
Table 148: FG320 Package Pinout (Cont’d)
Bank
XC3S500E Pin Name
XC3S1200E Pin Name
XC3S1600E Pin Name
Type
Ball
2
IP
IP
IO
IO
IO
IO
IO
IO
U6
500E: INPUT
1200E: I/O
1600E: I/O
2
2
U13
V7
500E: INPUT
1200E: I/O
1600E: I/O
N.C. ()
500E: N.C.
1200E: I/O
1600E: I/O
2
2
2
2
2
2
2
2
2
2
2
2
2
IO/D5
IO/D5
IO/D5
R9
V11
T15
U5
T3
DUAL
DUAL
VREF
VREF
DUAL
DUAL
DUAL
DUAL
I/O
IO/M1
IO/M1
IO/M1
IO/VREF_2
IO/VREF_2
IO/VREF_2
IO/VREF_2
IO/VREF_2
IO/VREF_2
IO_L01N_2/INIT_B
IO_L01P_2/CSO_B
IO_L03N_2/MOSI/CSI_B
IO_L03P_2/DOUT/BUSY
IO_L04N_2
IO_L01N_2/INIT_B
IO_L01P_2/CSO_B
IO_L03N_2/MOSI/CSI_B
IO_L03P_2/DOUT/BUSY
IO_L04N_2
IO_L01N_2/INIT_B
IO_L01P_2/CSO_B
IO_L03N_2/MOSI/CSI_B
IO_L03P_2/DOUT/BUSY
IO_L04N_2
U3
T4
U4
T5
IO_L04P_2
IO_L04P_2
IO_L04P_2
R5
P6
R6
V6
I/O
IO_L05N_2
IO_L05N_2
IO_L05N_2
I/O
IO_L05P_2
IO_L05P_2
IO_L05P_2
I/O
N.C. ()
IO_L06N_2/VREF_2
IO_L06N_2/VREF_2
500E: N.C.
1200E: VREF
1600E: VREF
2
N.C. ()
IO_L06P_2
IO_L06P_2
V5
500E: N.C.
1200E: I/O
1600E: I/O
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO_L07N_2
IO_L07N_2
IO_L07N_2
P7
N7
I/O
I/O
IO_L07P_2
IO_L07P_2
IO_L07P_2
IO_L09N_2
IO_L09N_2
IO_L09N_2
N8
I/O
IO_L09P_2
IO_L09P_2
IO_L09P_2
P8
I/O
IO_L10N_2
IO_L10N_2
IO_L10N_2
T8
I/O
IO_L10P_2
IO_L10P_2
IO_L10P_2
R8
I/O
IO_L12N_2/D6/GCLK13
IO_L12P_2/D7/GCLK12
IO_L13N_2/D3/GCLK15
IO_L13P_2/D4/GCLK14
IO_L15N_2/D1/GCLK3
IO_L15P_2/D2/GCLK2
IO_L16N_2/DIN/D0
IO_L16P_2/M0
IO_L18N_2
IO_L12N_2/D6/GCLK13
IO_L12P_2/D7/GCLK12
IO_L13N_2/D3/GCLK15
IO_L13P_2/D4/GCLK14
IO_L15N_2/D1/GCLK3
IO_L15P_2/D2/GCLK2
IO_L16N_2/DIN/D0
IO_L16P_2/M0
IO_L18N_2
IO_L12N_2/D6/GCLK13
IO_L12P_2/D7/GCLK12
IO_L13N_2/D3/GCLK15
IO_L13P_2/D4/GCLK14
IO_L15N_2/D1/GCLK3
IO_L15P_2/D2/GCLK2
IO_L16N_2/DIN/D0
IO_L16P_2/M0
IO_L18N_2
M9
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL
N9
V9
U9
P10
R10
N10
M10
N11
P11
V13
V12
R12
DUAL
I/O
IO_L18P_2
IO_L18P_2
IO_L18P_2
I/O
IO_L19N_2/VREF_2
IO_L19P_2
IO_L19N_2/VREF_2
IO_L19P_2
IO_L19N_2/VREF_2
IO_L19P_2
VREF
I/O
IO_L20N_2
IO_L20N_2
IO_L20N_2
I/O
DS312 (v4.1) July 19, 2013
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Product Specification
201
Spartan-3E FPGA Family: Pinout Descriptions
FG320
Table 148: FG320 Package Pinout (Cont’d)
Bank
XC3S500E Pin Name
IO_L20P_2
XC3S1200E Pin Name
XC3S1600E Pin Name
Type
Ball
T12
P12
2
2
IO_L20P_2
IO_L21N_2
IO_L20P_2
IO_L21N_2
I/O
N.C. ()
500E: N.C.
1200E: I/O
1600E: I/O
2
N.C. ()
IO_L21P_2
IO_L21P_2
N12
500E: N.C.
1200E: I/O
1600E: I/O
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO_L22N_2/A22
IO_L22P_2/A23
IO_L24N_2/A20
IO_L24P_2/A21
IO_L25N_2/VS1/A18
IO_L25P_2/VS2/A19
IO_L26N_2/CCLK
IO_L26P_2/VS0/A17
IP
IO_L22N_2/A22
IO_L22P_2/A23
IO_L24N_2/A20
IO_L24P_2/A21
IO_L25N_2/VS1/A18
IO_L25P_2/VS2/A19
IO_L26N_2/CCLK
IO_L26P_2/VS0/A17
IP
IO_L22N_2/A22
IO_L22P_2/A23
IO_L24N_2/A20
IO_L24P_2/A21
IO_L25N_2/VS1/A18
IO_L25P_2/VS2/A19
IO_L26N_2/CCLK
IO_L26P_2/VS0/A17
IP
R13
P13
R14
T14
U15
V15
U16
T16
V2
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VREF
IP
IP
IP
V16
V3
IP_L02N_2
IP_L02N_2
IP_L02N_2
IP_L02P_2
IP_L02P_2
IP_L02P_2
V4
IP_L08N_2
IP_L08N_2
IP_L08N_2
R7
IP_L08P_2
IP_L08P_2
IP_L08P_2
T7
IP_L11N_2/VREF_2
IP_L11P_2
IP_L11N_2/VREF_2
IP_L11P_2
IP_L11N_2/VREF_2
IP_L11P_2
V8
U8
INPUT
DUAL/GCLK
DUAL/GCLK
IP_L14N_2/M2/GCLK1
IP_L14N_2/M2/GCLK1
IP_L14N_2/M2/GCLK1
T10
U10
IP_L14P_2/RDWR_B/
GCLK0
IP_L14P_2/RDWR_B/
GCLK0
IP_L14P_2/RDWR_B/
GCLK0
2
2
2
2
2
2
2
2
2
3
IP_L17N_2
IP_L17P_2
IP_L23N_2
IP_L23P_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
N.C. ()
IP_L17N_2
IP_L17P_2
IP_L23N_2
IP_L23P_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
IO
IP_L17N_2
IP_L17P_2
IP_L23N_2
IP_L23P_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
IO
U11
T11
U14
V14
M8
INPUT
INPUT
INPUT
INPUT
VCCO
VCCO
VCCO
VCCO
VCCO
M11
T6
T13
V10
D4
500E: N.C.
1200E: I/O
1600E: I/O
3
3
3
3
3
3
IO_L01N_3
IO_L01N_3
IO_L01N_3
C2
C1
D2
D1
E1
E2
I/O
I/O
IO_L01P_3
IO_L01P_3
IO_L01P_3
IO_L02N_3/VREF_3
IO_L02P_3
IO_L02N_3/VREF_3
IO_L02P_3
IO_L02N_3/VREF_3
IO_L02P_3
VREF
I/O
IO_L03N_3
IO_L03N_3
IO_L03N_3
I/O
IO_L03P_3
IO_L03P_3
IO_L03P_3
I/O
DS312 (v4.1) July 19, 2013
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Product Specification
202
Spartan-3E FPGA Family: Pinout Descriptions
FG320
Table 148: FG320 Package Pinout (Cont’d)
Bank
XC3S500E Pin Name
N.C. ()
XC3S1200E Pin Name
XC3S1600E Pin Name
Type
Ball
3
IO_L04N_3
IO_L04N_3
E3
500E: N.C.
1200E: I/O
1600E: I/O
3
N.C. ()
IO_L04P_3
IO_L04P_3
E4
500E: N.C.
1200E: I/O
1600E: I/O
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO_L05N_3
IO_L05N_3
IO_L05N_3
F2
F1
G4
G3
G5
G6
H5
H6
H3
H4
H1
H2
J4
I/O
I/O
IO_L05P_3
IO_L05P_3
IO_L05P_3
IO_L06N_3/VREF_3
IO_L06P_3
IO_L06N_3/VREF_3
IO_L06P_3
IO_L06N_3/VREF_3
IO_L06P_3
VREF
I/O
IO_L07N_3
IO_L07N_3
IO_L07N_3
I/O
IO_L07P_3
IO_L07P_3
IO_L07P_3
I/O
IO_L08N_3
IO_L08N_3
IO_L08N_3
I/O
IO_L08P_3
IO_L08P_3
IO_L08P_3
I/O
IO_L09N_3
IO_L09N_3
IO_L09N_3
I/O
IO_L09P_3
IO_L09P_3
IO_L09P_3
I/O
IO_L10N_3
IO_L10N_3
IO_L10N_3
I/O
IO_L10P_3
IO_L10P_3
IO_L10P_3
I/O
IO_L11N_3/LHCLK1
IO_L11P_3/LHCLK0
IO_L11N_3/LHCLK1
IO_L11P_3/LHCLK0
IO_L11N_3/LHCLK1
IO_L11P_3/LHCLK0
LHCLK
LHCLK
LHCLK
J5
IO_L12N_3/LHCLK3/
IRDY2
IO_L12N_3/LHCLK3/
IRDY2
IO_L12N_3/LHCLK3/
IRDY2
J2
3
3
3
IO_L12P_3/LHCLK2
IO_L13N_3/LHCLK5
IO_L12P_3/LHCLK2
IO_L13N_3/LHCLK5
IO_L12P_3/LHCLK2
IO_L13N_3/LHCLK5
J1
K4
K3
LHCLK
LHCLK
LHCLK
IO_L13P_3/LHCLK4/
TRDY2
IO_L13P_3/LHCLK4/
TRDY2
IO_L13P_3/LHCLK4/
TRDY2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO_L14N_3/LHCLK7
IO_L14P_3/LHCLK6
IO_L15N_3
IO_L14N_3/LHCLK7
IO_L14P_3/LHCLK6
IO_L15N_3
IO_L14N_3/LHCLK7
IO_L14P_3/LHCLK6
IO_L15N_3
K5
K6
L2
LHCLK
LHCLK
I/O
IO_L15P_3
IO_L15P_3
IO_L15P_3
L1
I/O
IO_L16N_3
IO_L16N_3
IO_L16N_3
L4
I/O
IO_L16P_3
IO_L16P_3
IO_L16P_3
L3
I/O
IO_L17N_3/VREF_3
IO_L17P_3
IO_L17N_3/VREF_3
IO_L17P_3
IO_L17N_3/VREF_3
IO_L17P_3
L5
VREF
I/O
L6
IO_L18N_3
IO_L18N_3
IO_L18N_3
M3
M4
M6
M5
N5
N4
P1
P2
P4
I/O
IO_L18P_3
IO_L18P_3
IO_L18P_3
I/O
IO_L19N_3
IO_L19N_3
IO_L19N_3
I/O
IO_L19P_3
IO_L19P_3
IO_L19P_3
I/O
IO_L20N_3
IO_L20N_3
IO_L20N_3
I/O
IO_L20P_3
IO_L20P_3
IO_L20P_3
I/O
IO_L21N_3
IO_L21N_3
IO_L21N_3
I/O
IO_L21P_3
IO_L21P_3
IO_L21P_3
I/O
N.C. ()
IO_L22N_3
IO_L22N_3
500E: N.C.
1200E: I/O
1600E: I/O
DS312 (v4.1) July 19, 2013
www.xilinx.com
Product Specification
203
Spartan-3E FPGA Family: Pinout Descriptions
FG320
Table 148: FG320 Package Pinout (Cont’d)
Bank
XC3S500E Pin Name
N.C. ()
XC3S1200E Pin Name
XC3S1600E Pin Name
Type
Ball
3
IO_L22P_3
IO_L22P_3
P3
500E: N.C.
1200E: I/O
1600E: I/O
3
3
3
3
3
3
IO_L23N_3
IO_L23P_3
IO_L24N_3
IO_L24P_3
IP
IO_L23N_3
IO_L23P_3
IO_L24N_3
IO_L24P_3
IP
IO_L23N_3
IO_L23P_3
IO_L24N_3
IO_L24P_3
IP
R2
R3
T1
T2
D3
F4
I/O
I/O
I/O
I/O
INPUT
IO
IP
IP
500E: I/O
1200E: INPUT
1600E: INPUT
3
3
3
3
3
3
3
3
3
3
3
3
IP
IP
IP
F5
G1
J7
INPUT
INPUT
IP
IP
IP
IP
IP
IP
INPUT
IP
IP
IP
K2
K7
M1
N1
N2
R1
U1
J6
INPUT
IP
IP
IP
INPUT
IP
IP
IP
INPUT
IP
IP
IP
INPUT
IP
IP
IP
INPUT
IP
IP
IP
INPUT
IP
IP
IP
INPUT
IP/VREF_3
IO/VREF_3
IP/VREF_3
IP/VREF_3
IP/VREF_3
IP/VREF_3
VREF
R4
500E: VREF(I/O)
1200E:
VREF(INPUT)
1600E:
VREF(INPUT)
3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
GND
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
GND
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
GND
F3
H7
VCCO
VCCO
VCCO
VCCO
VCCO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
3
3
K1
3
L7
3
N3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A1
GND
GND
GND
A18
B2
GND
GND
GND
GND
GND
GND
B17
C10
G7
G12
H8
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
H9
GND
GND
GND
H10
H11
J3
GND
GND
GND
GND
GND
GND
GND
GND
GND
J8
GND
GND
GND
J11
DS312 (v4.1) July 19, 2013
www.xilinx.com
Product Specification
204
Spartan-3E FPGA Family: Pinout Descriptions
FG320
Table 148: FG320 Package Pinout (Cont’d)
Bank
XC3S500E Pin Name
GND
XC3S1200E Pin Name
GND
XC3S1600E Pin Name
Type
Ball
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
K8
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
K11
K16
L8
GND
GND
GND
GND
GND
GND
GND
GND
L9
GND
GND
GND
L10
L11
M7
GND
GND
GND
GND
GND
GND
GND
GND
GND
M12
T9
GND
GND
GND
GND
GND
GND
U2
GND
GND
GND
U17
V1
GND
GND
GND
GND
GND
GND
V18
V17
B1
GND
VCCAUX DONE
VCCAUX PROG_B
VCCAUX TCK
DONE
PROG_B
TCK
DONE
PROG_B
TCK
CONFIG
CONFIG
JTAG
A17
A2
VCCAUX TDI
TDI
TDI
JTAG
VCCAUX TDO
TDO
TDO
C16
D15
B7
JTAG
VCCAUX TMS
TMS
TMS
JTAG
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
B12
G2
G17
M2
M17
U7
U12
E5
E14
F6
F13
N6
N13
P5
P14
DS312 (v4.1) July 19, 2013
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Product Specification
205
Spartan-3E FPGA Family: Pinout Descriptions
User I/Os by Bank
Table 149 and Table 150 indicate how the available user-I/O
pins are distributed between the four I/O banks on the
FG320 package.
Table 149: User I/Os Per Bank for XC3S500E in the FG320 Package
All Possible I/O Pins by Type
Package
I/O Bank
Maximum I/O
Edge
(2)
I/O
29
INPUT
14
DUAL
1
VREF(1)
CLK
8
Top
0
1
2
3
58
58
6
5
Right
22
10
21
24
0
0(2)
0(2)
8
Bottom
Left
58
17
13
4
58
34
11
5
TOTAL
232
102
48
46
20
16
Notes:
1. Some VREF and CLK pins are on INPUT pins.
2. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
Table 150: User I/Os Per Bank for XC3S1200E and XC3S1600E in the FG320 Package
All Possible I/O Pins by Type
Package
I/O Bank
Maximum I/O
Edge
(2)
I/O
INPUT
DUAL
VREF(1)
CLK
8
Top
0
1
2
3
61
63
34
12
1
6
5
Right
25
12
21
24
0
0(2)
0(2)
8
Bottom
Left
63
23
11
5
63
38
12
5
TOTAL
250
120
47
46
21
16
Notes:
1. Some VREF and CLK pins are on INPUT pins.
2. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
DS312 (v4.1) July 19, 2013
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Product Specification
206
Spartan-3E FPGA Family: Pinout Descriptions
Footprint Migration Differences
Table 151 summarizes any footprint and functionality
differences between the XC3S500E, the XC3S1200E, and
the XC3S1600E FPGAs that may affect easy migration
between devices available in the FG320 package. There are
26 such balls. All other pins not listed in Table 151
unconditionally migrate between Spartan-3E devices
available in the FG320 package.
and the XC3S1600E. The arrows indicate the direction for
easy migration. A double-ended arrow () indicates that
the two pins have identical functionality. A left-facing arrow
() indicates that the pin on the device on the right
unconditionally migrates to the pin on the device on the left.
It may be possible to migrate the opposite direction
depending on the I/O configuration. For example, an I/O pin
(Type = I/O) can migrate to an input-only pin
The XC3S500E is duplicated on both the left and right sides
of the table to show migrations to and from the XC3S1200E
(Type = INPUT) if the I/O pin is configured as an input.
Table 151: FG320 Footprint Migration Differences
Pin
A7
Bank
0
XC3S500E
INPUT
N.C.
Migration
XC3S1200E
I/O
Migration
0
XC3S1600E
I/O
Migration
XC3S500E
INPUT
A12
D4
0
I/O
I/O
N.C.
N.C.
N.C.
INPUT
N.C.
N.C.
N.C.
N.C.
N.C.
I/O
3
N.C.
I/O
I/O
D6
0
N.C.
I/O
I/O
D13
E3
0
INPUT
N.C.
I/O
I/O
3
I/O
I/O
E4
3
N.C.
I/O
I/O
E6
0
N.C.
I/O
I/O
E15
E16
E17
F4
1
N.C.
I/O
I/O
1
N.C.
I/O
I/O
1
I/O
INPUT
INPUT
I/O
INPUT
INPUT
I/O
3
I/O
I/O
N12
N14
N15
P3
2
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
I/O
1
N.C.
I/O
I/O
1
N.C.
I/O
I/O
3
N.C.
I/O
I/O
P4
3
N.C.
I/O
I/O
P12
P15
P16
R4
2
N.C.
I/O
I/O
1
I/O
INPUT
I/O
INPUT
I/O
1
N.C.
N.C.
VREF(I/O)
INPUT
INPUT
N.C.
N.C.
N.C.
3
VREF(I/O)
INPUT
INPUT
N.C.
VREF(INPUT)
I/O
VREF(INPUT)
I/O
U6
2
U13
V5
2
I/O
I/O
2
I/O
I/O
V6
2
N.C.
VREF
I/O
VREF
I/O
V7
2
N.C.
DIFFERENCES
26
26
Legend:
This pin is identical on the device on the left and the right.
This pin can unconditionally migrate from the device on the left to the device on the right. Migration in the other direction may be
possible depending on how the pin is configured for the device on the right.
This pin can unconditionally migrate from the device on the right to the device on the left. Migration in the other direction may be
possible depending on how the pin is configured for the device on the left.
DS312 (v4.1) July 19, 2013
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Product Specification
207
Spartan-3E FPGA Family: Pinout Descriptions
FG320 Footprint
X-Ref Target - Figure 86
Bank 0
1
2
3
4
5
6
7
8
9
10
11
I/O
12
13
14
15
16
17
18
I/O
L12N_0
GCLK7
I/O
INPUT
I/O
L24P_0
INPUT
L22P_0
I/O
L20N_0
I/O
L05P_0
I/O
L04N_0
INPUT
L02N_0
I/O
L01N_0
VCCO_0
GND
TDI
INPUT
I/O
TCK
GND
A
B
C
D
E
F
I/O
L25N_0
HSWAP
INPUT INPUT
I/O
L12P_0
GCLK6
I/O
L05N_0
VREF_0
I/O
INPUT
I/O
I/O
I/O
INPUT
I/O
PROG_B
VCCAUX
VCCAUX
GND
GND
INPUT
L13P_0
GCLK8
L13N_0
GCLK9
L24N_0
L22N_0
L20P_0
VREF_0
L04P_0
L02P_0
L01P_0
I/O
L14P_0
GCLK10
I/O
L03N_0
VREF_0
I/O
L24N_1
LDC2
I/O
L24P_1
LDC1
I/O
L01P_3
I/O
L01N_3
I/O
L25P_0
I/O
L23P_0
I/O
L18P_0
INPUT
L16P_0
I/O
L09P_0
INPUT
L07P_0
VCCO_0
VCCO_0
I/O
GND
INPUT
TMS
TDO
I/O
L21P_0
I/O
L02N_3
VREF_3
I/O
L23N_0
VREF_0
I/O
L18N_0
VREF_0
I/O
L14N_0
GCLK11
I/O
L11P_0
GCLK4
I/O
L23N_1
LDC0
I/O
L23P_1
HDC
INPUT
I/O
I/O
L02P_3
INPUT
L16N_0
I/O
L09N_0
INPUT
L07N_0
I/O
L03P_0
INPUT
VREF_1
INPUT
I/O
L04N_3
I/O
L04P_3
I/O
L21N_0
I/O
L22P_1
I/O
L22N_1
I/O
L19N_0
VREF_0
I/O
L11N_0
GCLK5
INPUT
I/O
L03N_3
I/O
L03P_3
I/O
L17P_0
I/O
L15P_0
I/O
L08P_0
I/O
L06N_0
VCCINT
I/O
VCCINT
INPUT
INPUT
I/O
L05P_3
I/O
L05N_3
I/O
L19P_0
I/O
L17N_0
I/O
L15N_0
INPUT
L10P_0
I/O
L08N_0
I/O
L06P_0
I/O
L21N_1
I/O
L21P_1
I/O
L19N_1
I/O
L19P_1
VCCO_3
VCCO_1
INPUT VCCINT
VCCINT
I/O
L06N_3
VREF_3
I/O
I/O
I/O
INPUT
I/O
I/O
I/O
I/O
VCCAUX
VCCO_0
VCCO_0
VCCAUX
INPUT
GND
I/O
GND
INPUT
G
H
J
L06P_3
L07N_3
L07P_3
L10N_0
L20N_1
L20P_1
L18P_1
L18N_1
I/O
L16N_1
A0
I/O
L10N_3
I/O
L10P_3
I/O
L09N_3
I/O
L09P_3
I/O
L08N_3
I/O
L08P_3
I/O
L17P_1
I/O
L17N_1
I/O
L16P_1
INPUT
VREF_1
VCCO_3
VCCO_1
GND
GND
GND
GND
GND
GND
INPUT
I/O
L13P_1
A6
RHCLK4
IRDY1
I/O
L12N_3
LHCLK3
IRDY2
I/O
I/O
I/O
I/O
L12P_3
LHCLK2
I/O
L11N_3
LHCLK1 LHCLK0
I/O
L11P_3
I/O
L15P_1
A2
I/O
L15N_1
A1
INPUT
VREF_3
L14N_1
A3
L14P_1
A4
L13N_1
A5
VCCO_1
GND
I/O
L13P_3
LHCLK4
TRDY2
INPUT
INPUT
VCCO_3
GND
RHCLK7 RHCLK6 RHCLK5
I/O
I/O
I/O
I/O
I/O
L13N_3
I/O
L14N_3
I/O
L14P_3
L12N_1
L11N_1
A9
L11P_1
A10
L12P_1
VCCO_3
INPUT
GND
GND
A7
GND
INPUT INPUT
K
L
A8
RHCLK3
TRDY1
LHCLK5 LHCLK7 LHCLK6
RHCLK1 RHCLK0
RHCLK2
I/O
L17N_3
VREF_3
I/O
L09N_1
A11
I/O
L09P_1
A12
I/O
I/O
L15P_3
I/O
L15N_3
I/O
L16P_3
I/O
L16N_3
I/O
L17P_3
I/O
VCCO_1
GND
GND
I/O
GND
GND
INPUT INPUT
L10N_1
L10P_1
VREF_1
I/O
L16P_2
M0
I/O
I/O
L18N_3
I/O
L18P_3
I/O
L19P_3
I/O
L19N_3
I/O
I/O
L07P_1
I/O
L07N_1
I/O
L08N_1
L12N_2
D6
VCCAUX
VCCO_2
VCCO_2
VCCAUX
INPUT
GND
L05N_1
L05P_1
VREF_1
M
N
P
R
T
GCLK13
I/O
L21P_2
I/O
L04N_1
I/O
L04P_1
I/O
I/O
I/O
L20P_3
I/O
L20N_3
I/O
L07P_2
I/O
L09N_2
I/O
L18N_2
I/O
INPUT
L12P_2
D7
L16N_2
DIN
VCCO_3
VCCO_1
INPUT INPUT
VCCINT
VCCINT
L08P_1
GCLK12
D0
I/O
L22P_3
I/O
L22N_3
I/O
L21N_2
I/O
I/O
L22P_2
A23
INPUT
I/O
I/O
L21N_3
I/O
L21P_3
I/O
L05N_2
I/O
L07N_2
I/O
L09P_2
I/O
L18P_2
I/O
L06P_1
I/O
L06N_1
L15N_2
D1
VCCINT
I/O
VCCINT
GCLK3
INPUT
VREF_3
I/O
I/O
L22N_2
A22
I/O
L24N_2
A20
I/O
L03N_1
VREF_1
I/O
L02P_1
A14
I/O
L23N_3
I/O
L23P_3
I/O
L04P_2
I/O
L05P_2
INPUT
L08N_2
I/O
L10P_2
I/O
D5
I/O
L20N_2
I/O
L03P_1
L15P_2
D2
INPUT
I/O
INPUT
GCLK2
INPUT
I/O
I/O
I/O
L01N_2
INIT_B
I/O
L24P_2
A21
I/O
L01N_1
A15
I/O
L02N_1
A13
I/O
L24N_3
I/O
L24P_3
I/O
L04N_2
INPUT
L08P_2
I/O
L10N_2
INPUT
L17P_2
I/O
L20P_2
I/O
VREF_2
L03N_2
MOSI
L14N_2
L26P_2
VS0
VCCO_2
VCCO_2
GND
I/O
M2
CSI_B
GCLK1
A17
I/O
INPUT
I/O
I/O
L01P_2
CSO_B
I/O
L26N_2
CCLK
I/O
L01P_1
A16
INPUT
INPUT
I/O
VREF_2
INPUT
L11P_2
INPUT
INPUT
L23N_2
L03P_2
DOUT
BUSY
L13P_2
L14P_2
L25N_2
VS1
VCCAUX
VCCAUX
INPUT
GND
GND
GND
U
V
D4
RDWR_B L17N_2
GCLK0
GCLK14
A18
I/O
I/O
L06P_2
I/O
I/O
INPUT
L11N_2
VREF_2
I/O
L19N_2
VREF_2
I/O
INPUT INPUT
L02N_2 L02P_2
I/O
M1
I/O
L19P_2
INPUT
L23P_2
L06N_2
L13N_2
D3
L25P_2
VS2
VCCO_2
INPUT
INPUT DONE
GND
VREF_2
GCLK15
A19
Bank 2
DS312-4_06_022106
Figure 86: FG320 Package Footprint (top view)
I/O: Unrestricted, general-purpose
DUAL: Configuration pin, then
VREF: User I/O or input voltage
102-
120
20-
21
46
16
user I/O
possible user-I/O
reference for bank
INPUT: Unrestricted,
general-purpose input pin
CLK: User I/O, input, or global
buffer input
VCCO: Output voltage supply for
bank
47-
48
20
CONFIG: Dedicated configuration
JTAG: Dedicated JTAG port pins
GND: Ground
VCCINT: Internal core supply
2
4
8
8
pins
voltage (+1.2V)
N.C.: Not connected. Only the
XC3S500E has these pins ().
VCCAUX: Auxiliary supply voltage
(+2.5V)
18
28
DS312 (v4.1) July 19, 2013
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Product Specification
208
Spartan-3E FPGA Family: Pinout Descriptions
FG400: 400-ball Fine-pitch Ball Grid Array
The 400-ball fine-pitch ball grid array, FG400, supports two
different Spartan-3E FPGAs, including the XC3S1200E and
the XC3S1600E. Both devices share a common footprint for
this package as shown in Table 152 and Figure 87.
Table 152: FG400 Package Pinout (Cont’d)
XC3S1200E
FG400
Bank
XC3S1600E
Pin Name
Type
Ball
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO_L12P_0
D12
E12
F12
G11
F11
E10
E11
A9
I/O
I/O
Table 152 lists all the FG400 package pins. They are sorted
by bank number and then by pin name. Pairs of pins that
form a differential I/O pair appear together in the table. The
table also shows the pin number for each pin and the pin
type, as defined earlier.
IO_L13N_0
IO_L13P_0
I/O
IO_L15N_0/GCLK5
IO_L15P_0/GCLK4
IO_L16N_0/GCLK7
IO_L16P_0/GCLK6
IO_L18N_0/GCLK11
IO_L18P_0/GCLK10
IO_L19N_0
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
I/O
An electronic version of this package pinout table and
footprint diagram is available for download from the Xilinx
website at:
http://www.xilinx.com/support/documentation/data_sheets
/s3e_pin.zip
A10
F9
IO_L19P_0
E9
I/O
Pinout Table
IO_L21N_0
C9
I/O
Table 152: FG400 Package Pinout
IO_L21P_0
D9
I/O
XC3S1200E
XC3S1600E
Pin Name
IO_L22N_0/VREF_0
IO_L22P_0
B8
VREF
I/O
FG400
Ball
Bank
Type
B9
IO_L24N_0/VREF_0
IO_L24P_0
F7
VREF
I/O
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
A3
I/O
I/O
F8
A8
IO_L25N_0
A6
I/O
A12
C7
I/O
IO_L25P_0
A7
I/O
I/O
IO_L27N_0
B5
I/O
C10
E8
I/O
IO_L27P_0
B6
I/O
I/O
IO_L28N_0
D6
I/O
E13
E16
F13
F14
G7
I/O
IO_L28P_0
C6
I/O
I/O
IO_L30N_0/VREF_0
IO_L30P_0
C5
VREF
I/O
I/O
D5
I/O
IO_L31N_0
A2
I/O
I/O
IO_L31P_0
B2
I/O
IO/VREF_0
IO_L01N_0
IO_L01P_0
C11
B17
C17
A18
A19
A17
A16
A15
B15
C14
D14
A13
A14
B13
C13
C12
VREF
I/O
IO_L32N_0/HSWAP
IO_L32P_0
D4
DUAL
I/O
C4
I/O
IP
B18
E5
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
GCLK
IO_L03N_0/VREF_0
IO_L03P_0
VREF
I/O
IP
IP_L02N_0
C16
D16
D15
C15
E14
E15
G14
G13
B11
B12
G10
IO_L04N_0
IO_L04P_0
I/O
IP_L02P_0
I/O
IP_L05N_0
IO_L06N_0
IO_L06P_0
I/O
IP_L05P_0
I/O
IP_L08N_0
IO_L07N_0
IO_L07P_0
I/O
IP_L08P_0
I/O
IP_L11N_0
IO_L09N_0/VREF_0
IO_L09P_0
VREF
I/O
IP_L11P_0
IP_L14N_0
IO_L10N_0
IO_L10P_0
I/O
IP_L14P_0
I/O
IP_L17N_0/GCLK9
IO_L12N_0
I/O
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209
Spartan-3E FPGA Family: Pinout Descriptions
Table 152: FG400 Package Pinout (Cont’d)
Table 152: FG400 Package Pinout (Cont’d)
XC3S1200E
XC3S1600E
Pin Name
XC3S1200E
XC3S1600E
Pin Name
FG400
Ball
FG400
Ball
Bank
Type
Bank
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IP_L17P_0/GCLK8
IP_L20N_0
H10
G9
GCLK
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
DUAL
DUAL
DUAL
DUAL
VREF
I/O
1
1
1
1
1
1
1
IO_L14P_1/A10/RHCLK0
M16
RHCLK/
DUAL
IO_L15N_1/A7/RHCLK3/
TRDY1
L14
L15
K14
K13
J20
K20
RHCLK/
DUAL
IP_L20P_0
G8
IP_L23N_0
C8
IO_L15P_1/A8/RHCLK2
RHCLK/
DUAL
IP_L23P_0
D8
IP_L26N_0
E6
IO_L16N_1/A5/RHCLK5
RHCLK/
DUAL
IP_L26P_0
E7
IO_L16P_1/A6/RHCLK4/
IRDY1
RHCLK/
DUAL
IP_L29N_0
A4
IP_L29P_0
A5
IO_L17N_1/A3/RHCLK7
RHCLK/
DUAL
VCCO_0
B4
VCCO_0
B10
B16
D7
IO_L17P_1/A4/RHCLK6
RHCLK/
DUAL
VCCO_0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IO_L18N_1/A1
IO_L18P_1/A2
IO_L19N_1/A0
IO_L19P_1
IO_L20N_1
IO_L20P_1
IO_L21N_1
IO_L21P_1
IO_L22N_1
IO_L22P_1
IO_L23N_1
IO_L23P_1
IO_L24N_1/VREF_1
IO_L24P_1
IO_L25N_1
IO_L25P_1
IO_L26N_1
IO_L26P_1
IO_L27N_1
IO_L27P_1
IO_L28N_1
IO_L28P_1
IO_L29N_1/LDC0
IO_L29P_1/HDC
IO_L30N_1/LDC2
IO_L30P_1/LDC1
IP
K16
J16
J13
J14
J17
J18
H19
J19
H15
H16
H18
H17
H20
G20
G16
F16
F19
F20
F18
F17
D20
E20
D18
E18
C19
C20
B20
G15
G18
H14
J15
DUAL
DUAL
DUAL
I/O
VCCO_0
VCCO_0
D13
F10
U18
U17
T18
T17
V19
U19
W20
V20
R18
R17
T20
U20
P18
P17
P20
R20
P16
N16
N19
N18
N15
M15
M18
M17
L19
M19
L16
VCCO_0
IO_L01N_1/A15
IO_L01P_1/A16
IO_L02N_1/A13
IO_L02P_1/A14
IO_L03N_1/VREF_1
IO_L03P_1
I/O
I/O
I/O
I/O
I/O
I/O
IO_L04N_1
I/O
I/O
IO_L04P_1
I/O
I/O
IO_L05N_1
I/O
VREF
I/O
IO_L05P_1
I/O
IO_L06N_1
I/O
I/O
IO_L06P_1
I/O
I/O
IO_L07N_1
I/O
I/O
IO_L07P_1
I/O
I/O
IO_L08N_1/VREF_1
IO_L08P_1
VREF
I/O
I/O
I/O
IO_L09N_1
I/O
I/O
IO_L09P_1
I/O
I/O
IO_L10N_1
I/O
DUAL
DUAL
DUAL
DUAL
INPUT
INPUT
INPUT
INPUT
INPUT
IO_L10P_1
I/O
IO_L11N_1
I/O
IO_L11P_1
I/O
IO_L12N_1/A11
IO_L12P_1/A12
IO_L13N_1/VREF_1
IO_L13P_1
DUAL
DUAL
VREF
I/O
IP
IP
IP
IO_L14N_1/A9/RHCLK1
RHCLK/
DUAL
IP
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Product Specification
210
Spartan-3E FPGA Family: Pinout Descriptions
Table 152: FG400 Package Pinout (Cont’d)
Table 152: FG400 Package Pinout (Cont’d)
XC3S1200E
XC3S1600E
Pin Name
XC3S1200E
XC3S1600E
Pin Name
FG400
Ball
FG400
Ball
Bank
Type
Bank
Type
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IP
IP
IP
IP
IP
IP
IP
L18
M20
N14
N20
P15
R16
R19
E19
K18
D19
G17
K15
K19
N17
T19
P8
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VREF
VREF
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
I/O
2
2
2
IO_L13N_2
Y8
Y9
I/O
I/O
IO_L13P_2
IO_L15N_2/D6/GCLK13
W10
DUAL/
GCLK
2
2
2
2
2
IO_L15P_2/D7/GCLK12
IO_L16N_2/D3/GCLK15
IO_L16P_2/D4/GCLK14
IO_L18N_2/D1/GCLK3
IO_L18P_2/D2/GCLK2
W9
P10
R10
V11
V10
DUAL/
GCLK
DUAL/
GCLK
IP/VREF_1
IP/VREF_1
VCCO_1
DUAL/
GCLK
DUAL/
GCLK
VCCO_1
DUAL/
GCLK
VCCO_1
VCCO_1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO_L19N_2/DIN/D0
IO_L19P_2/M0
IO_L21N_2
Y12
Y11
U12
V12
W12
W13
U13
V13
P14
R14
Y14
Y15
T15
U15
V16
U16
Y18
W18
W19
Y19
T16
W3
DUAL
DUAL
I/O
VCCO_1
VCCO_1
IO
IO_L21P_2
I/O
IO
P13
R9
I/O
IO_L22N_2/VREF_2
IO_L22P_2
VREF
I/O
IO
I/O
IO
R13
W15
Y5
I/O
IO_L24N_2
I/O
IO
I/O
IO_L24P_2
I/O
IO
I/O
IO_L25N_2
I/O
IO
Y7
I/O
IO_L25P_2
I/O
IO
Y13
N11
T11
Y3
I/O
IO_L27N_2/A22
IO_L27P_2/A23
IO_L28N_2
DUAL
DUAL
I/O
IO/D5
DUAL
DUAL
VREF
VREF
DUAL
DUAL
DUAL
DUAL
I/O
IO/M1
IO/VREF_2
IO/VREF_2
IO_L01N_2/INIT_B
IO_L01P_2/CSO_B
IO_L03N_2/MOSI/CSI_B
IO_L03P_2/DOUT/BUSY
IO_L04N_2
IO_L04P_2
IO_L06N_2
IO_L06P_2
IO_L07N_2
IO_L07P_2
IO_L09N_2/VREF_2
IO_L09P_2
IO_L10N_2
IO_L10P_2
IO_L12N_2
IO_L12P_2
IO_L28P_2
I/O
Y17
V4
IO_L30N_2/A20
IO_L30P_2/A21
IO_L31N_2/VS1/A18
IO_L31P_2/VS2/A19
IO_L32N_2/CCLK
IO_L32P_2/VS0/A17
IP
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VREF
U4
V5
U5
Y4
W4
T6
I/O
I/O
IP
T5
I/O
IP_L02N_2
Y2
U7
I/O
IP_L02P_2
W2
V7
I/O
IP_L05N_2
V6
R7
VREF
I/O
IP_L05P_2
U6
T7
IP_L08N_2
Y6
V8
I/O
IP_L08P_2
W6
W8
U9
I/O
IP_L11N_2
R8
I/O
IP_L11P_2
T8
V9
I/O
IP_L14N_2/VREF_2
T10
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Product Specification
211
Spartan-3E FPGA Family: Pinout Descriptions
Table 152: FG400 Package Pinout (Cont’d)
Table 152: FG400 Package Pinout (Cont’d)
XC3S1200E
XC3S1600E
Pin Name
XC3S1200E
XC3S1600E
Pin Name
FG400
Ball
FG400
Ball
Bank
Type
Bank
Type
2
2
IP_L14P_2
T9
INPUT
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO_L13P_3
K6
K2
K3
L7
I/O
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
I/O
IP_L17N_2/M2/GCLK1
P12
DUAL/
GCLK
IO_L14N_3/LHCLK1
IO_L14P_3/LHCLK0
IO_L15N_3/LHCLK3/IRDY2
IO_L15P_3/LHCLK2
IO_L16N_3/LHCLK5
IO_L16P_3/LHCLK4/TRDY2
IO_L17N_3/LHCLK7
IO_L17P_3/LHCLK6
IO_L18N_3
IO_L18P_3
IO_L19N_3
IO_L19P_3
IO_L20N_3/VREF_3
IO_L20P_3
IO_L21N_3
IO_L21P_3
IO_L22N_3
IO_L22P_3
IO_L23N_3
IO_L23P_3
IO_L24N_3
IO_L24P_3
IO_L25N_3
IO_L25P_3
IO_L26N_3
IO_L26P_3
IO_L27N_3
IO_L27P_3
IO_L28N_3/VREF_3
IO_L28P_3
IO_L29N_3
IO_L29P_3
IO_L30N_3
IO_L30P_3
IP
2
IP_L17P_2/RDWR_B/
GCLK0
P11
DUAL/
GCLK
K7
L1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IP_L20N_2
IP_L20P_2
IP_L23N_2/VREF_2
IP_L23P_2
IP_L26N_2
IP_L26P_2
IP_L29N_2
IP_L29P_2
VCCO_2
T12
R12
T13
T14
V14
V15
W16
Y16
R11
U8
INPUT
INPUT
VREF
INPUT
INPUT
INPUT
INPUT
INPUT
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
I/O
M1
L3
M3
M7
M8
M4
M5
N6
M6
N2
N1
P7
N7
N4
N3
R1
P1
R5
P5
T2
R2
R4
R3
T1
U1
T3
U3
V1
V2
F5
G1
G6
H1
J5
I/O
I/O
I/O
VREF
I/O
VCCO_2
VCCO_2
U14
W5
W11
W17
D2
I/O
VCCO_2
I/O
VCCO_2
I/O
VCCO_2
I/O
IO_L01N_3
IO_L01P_3
IO_L02N_3/VREF_3
IO_L02P_3
IO_L03N_3
IO_L03P_3
IO_L04N_3
IO_L04P_3
IO_L05N_3
IO_L05P_3
IO_L06N_3
IO_L06P_3
IO_L07N_3
IO_L07P_3
IO_L08N_3
IO_L08P_3
IO_L09N_3/VREF_3
IO_L09P_3
IO_L10N_3
IO_L10P_3
IO_L11N_3
IO_L11P_3
IO_L12N_3
IO_L12P_3
IO_L13N_3
I/O
D3
I/O
I/O
E3
VREF
I/O
I/O
E4
I/O
C1
I/O
I/O
B1
I/O
I/O
E1
I/O
I/O
D1
I/O
I/O
F3
I/O
I/O
F4
I/O
I/O
F1
I/O
VREF
I/O
F2
I/O
G4
G3
G5
H5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
H3
VREF
I/O
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
H2
IP
H7
I/O
IP
H6
I/O
IP
J4
I/O
IP
J3
I/O
IP
L5
J1
I/O
IP
L8
J2
I/O
IP
M2
J6
I/O
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Product Specification
212
Spartan-3E FPGA Family: Pinout Descriptions
Table 152: FG400 Package Pinout (Cont’d)
Table 152: FG400 Package Pinout (Cont’d)
XC3S1200E
XC3S1600E
Pin Name
XC3S1200E
XC3S1600E
Pin Name
FG400
Ball
FG400
Ball
Bank
Type
Bank
Type
3
IP
IP
IP
IP
N5
P3
INPUT
INPUT
INPUT
INPUT
VREF
VREF
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
P19
R6
GND
GND
3
3
T4
R15
U11
V3
GND
3
W1
K5
GND
3
IP/VREF_3
IP/VREF_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
GND
GND
3
P6
V18
W7
W14
Y1
GND
3
E2
GND
3
H4
GND
3
L2
GND
3
L6
Y10
Y20
V17
C2
GND
3
P4
GND
3
U2
VCCAUX DONE
CONFIG
CONFIG
JTAG
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A1
VCCAUX PROG_B
VCCAUX TCK
GND
A11
A20
B7
D17
B3
GND
VCCAUX TDI
JTAG
GND
VCCAUX TDO
B19
E17
D11
H12
J7
JTAG
GND
B14
C3
VCCAUX TMS
JTAG
GND
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
GND
C18
D10
F6
GND
GND
K4
GND
F15
G2
L17
M14
N9
GND
GND
G12
G19
H8
GND
U10
H9
GND
GND
J9
H11
H13
J8
GND
J11
K1
GND
GND
K8
J10
J12
K9
GND
K10
K12
K17
L4
GND
GND
K11
L10
L12
M9
GND
GND
L9
GND
L11
L13
L20
M10
M12
N13
P2
GND
M11
M13
N8
GND
GND
GND
N10
N12
GND
GND
GND
P9
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Product Specification
213
Spartan-3E FPGA Family: Pinout Descriptions
User I/Os by Bank
Table 153 indicates how the 304 available user-I/O pins are
distributed between the four I/O banks on the FG400
package.
Table 153: User I/Os Per Bank for the XC3S1200E and XC3S1600E in the FG400 Package
All Possible I/O Pins by Type
Package
I/O Bank
Maximum I/O
Edge
(2)
I/O
INPUT
DUAL
VREF(1)
CLK
Top
0
1
2
3
78
74
43
20
1
6
6
8
Right
35
12
21
24
0
0(2)
0(2)
8
Bottom
Left
78
30
18
6
74
48
12
6
TOTAL
304
156
62
46
24
16
Notes:
1. Some VREF and CLK pins are on INPUT pins.
2. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
Footprint Migration Differences
The XC3S1200E and XC3S1600E FPGAs have identical
footprints in the FG400 package. Designs can migrate
between the XC3S1200E and XC3S1600E FPGAs without
further consideration.
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Product Specification
214
Spartan-3E FPGA Family: Pinout Descriptions
Bank 0
X-Ref Target - Figure 87
FG400 Footprint
1
2
3
4
5
6
7
8
10
9
Left Half of Package
(top view)
I/O
L18N_0
GCLK11
I/O
L18P_0
GCLK10
I/O
L31N_0
INPUT
L29N_0
INPUT
L29P_0
I/O
L25N_0
I/O
L25P_0
GND
I/O
I/O
A
B
C
D
E
F
I/O
L22N_0
VREF_0
I/O
L03P_3
I/O
L31P_0
I/O
I/O
I/O
VCCO_0
VCCO_0
I/O
TDI
GND
I/O
I/O: Unrestricted,
156
L27N_0
L27P_0
L22P_0
general-purpose user I/O
I/O
L30N_0
VREF_0
I/O
L03N_3
I/O
L32P_0
I/O
L28P_0
INPUT
L23N_0
I/O
L21N_0
PROG_B
GND
INPUT: Unrestricted,
62
general-purpose input pin
I/O
L32N_0
HSWAP
I/O
L04P_3
I/O
L01N_3
I/O
L01P_3
I/O
L30P_0
I/O
L28N_0
INPUT
L23P_0
I/O
L21P_0
VCCO_0
GND
DUAL: Configuration pin,
46
then possible user I/O
I/O
L02N_3
VREF_3
I/O
L16N_0
GCLK7
I/O
L04N_3
I/O
INPUT
INPUT
I/O
VCCO_3
INPUT
INPUT
I/O
VREF: User I/O or input
24
L02P_3
L26N_0
L26P_0
L19P_0
voltage reference for bank
I/O
L24N_0
VREF_0
I/O
L06N_3
I/O
L06P_3
I/O
L05N_3
I/O
L05P_3
I/O
L24P_0
I/O
L19N_0
VCCO_0
GND
CLK: User I/O, input, or
clock buffer input
16
INPUT
L17N_0
GCLK9
I/O
I/O
I/O
INPUT
INPUT
INPUT
INPUT
GND
INPUT
I/O
CONFIG: Dedicated
G
H
J
L07P_3
L07N_3
L08N_3
L20P_0
L20N_0
2
configuration pins
I/O
L09N_3
VREF_3
INPUT
L17P_0
GCLK8
I/O
L09P_3
I/O
L08P_3
I/O
L10P_3
I/O
L10N_3
VCCO_3
JTAG: Dedicated JTAG
port pins
GND
VCCINT
GND
VCCINT
GND
4
I/O
L12N_3
I/O
L12P_3
I/O
L11P_3
I/O
L11N_3
I/O
L13N_3
GND: Ground
VCCAUX
INPUT
VCCINT
GND
42
I/O
L14N_3
LHCLK1
I/O
L14P_3
LHCLK0
I/O
L15P_3
LHCLK2
INPUT
VREF_3
I/O
L13P_3
VCCO: Output voltage
supply for bank
VCCAUX
GND
VCCINT
GND
K
L
24
I/O
L15N_3
LHCLK3
IRDY2
I/O
L16N_3
LHCLK5
I/O
L17N_3
LHCLK7
VCCINT: Internal core
16
VCCO_3
VCCO_3
GND
INPUT
INPUT
VCCINT
GND
supply voltage (+1.2V)
I/O
L16P_3
LHCLK4
TRDY2
I/O
L17P_3
LHCLK6
I/O
L19N_3
I/O
L19P_3
I/O
L20P_3
I/O
L18N_3
I/O
L18P_3
VCCAUX: Auxiliary supply
voltage (+2.5V)
INPUT
VCCINT
VCCAUX
GND
M
N
P
R
T
8
I/O
L20N_3
VREF_3
I/O
L21P_3
I/O
L21N_3
I/O
L23P_3
I/O
L23N_3
I/O
L22P_3
N.C.: Not connected
INPUT
VCCINT
I/O
VCCINT
I/O
L16N_2
D3
GCLK15
0
I/O
L24P_3
I/O
L25P_3
INPUT
VREF_3
I/O
L22N_3
VCCO_3
GND
INPUT
I/O
I/O
L09N_2
VREF_2
I/O
L24N_3
I/O
L26P_3
I/O
L27P_3
I/O
L27N_3
I/O
L25N_3
INPUT
L11N_2
L16P_2
D4
GND
I/O
GCLK14
I/O
L28N_3
VREF_3
INPUT
L14N_2
VREF_2
I/O
L26N_3
I/O
L29N_3
I/O
L06P_2
I/O
L06N_2
I/O
L09P_2
INPUT
L11P_2
INPUT
L14P_2
INPUT
I/O
L03P_2
DOUT
BUSY
I/O
L01P_2
CSO_B
I/O
L28P_3
I/O
L29P_3
INPUT
L05P_2
I/O
L07N_2
I/O
L12N_2
VCCO_3
VCCO_2
VCCAUX
U
V
W
Y
I/O
I/O
I/O
L01N_2
INIT_B
I/O
I/O
INPUT
I/O
I/O
I/O
L03N_2
MOSI
L18P_2
D2
GND
L30N_3
L30P_3
L05N_2
L07P_2
L10N_2
L12P_2
CSI_B
GCLK2
I/O
I/O
INPUT
L02P_2
I/O
L04P_2
INPUT
L08P_2
I/O
L10P_2
L15P_2
D7
L15N_2
D6
VCCO_2
INPUT
GND
INPUT
GND
I/O
GCLK12
GCLK13
INPUT
L02N_2
I/O
VREF_2
I/O
L04N_2
INPUT
L08N_2
I/O
L13N_2
I/O
L13P_2
I/O
GND
Bank 2
DS312-4_08_101905
Figure 87: FG400 Package Footprint (top view)
DS312 (v4.1) July 19, 2013
www.xilinx.com
Product Specification
215
Spartan-3E FPGA Family: Pinout Descriptions
FG400 Footprint
Bank 0
11
12
I/O
13
14
15
16
17
18
19
20
Right Half of Package
(top view)
I/O
L09N_0
VREF_0
I/O
L03N_0
VREF_0
I/O
L09P_0
I/O
L06N_0
I/O
L04P_0
I/O
L04N_0
I/O
L03P_0
GND
GND
A
INPUT
INPUT
I/O
I/O
I/O
VCCO_0
GND
INPUT
GND
TDO
INPUT
B
C
D
E
F
L14N_0
L14P_0
L10N_0
L06P_0
L01N_0
I/O
L30N_1
LDC2
I/O
L30P_1
LDC1
I/O
VREF_0
I/O
L12N_0
I/O
L10P_0
I/O
L07N_0
INPUT
L05P_0
INPUT
L02N_0
I/O
L01P_0
I/O
L29N_1
LDC0
I/O
L12P_0
I/O
L07P_0
INPUT
L05N_0
INPUT
L02P_0
I/O
L28N_1
VCCAUX
VCCO_0
I/O
VCCO_1
TCK
TMS
I/O
L16P_0
GCLK6
I/O
L29P_1
HDC
I/O
L13N_0
INPUT
L08N_0
INPUT
L08P_0
INPUT
VREF_1
I/O
L28P_1
I/O
I/O
L15P_0
GCLK4
I/O
L13P_0
I/O
L25P_1
I/O
L27P_1
I/O
L27N_1
I/O
L26N_1
I/O
L26P_1
I/O
I/O
GND
I/O
L15N_0
GCLK5
INPUT
INPUT
I/O
I/O
VCCO_1
GND
VCCAUX
VCCINT
GND
INPUT
INPUT
GND
G
H
J
L11P_0
L11N_0
L25N_1
L24P_1
I/O
L24N_1
VREF_1
I/O
L22N_1
I/O
L22P_1
I/O
L23P_1
I/O
L23N_1
I/O
L21N_1
VCCINT
GND
VCCINT INPUT
I/O
I/O
I/O
I/O
L18P_1
A2
I/O
L20N_1
I/O
L20P_1
I/O
L21P_1
L17N_1
A3
INPUT
L19N_1
L19P_1
A0
RHCLK7
I/O
L16P_1
A6
RHCLK4
IRDY1
I/O
I/O
I/O
L18N_1
A1
INPUT
VREF_1
L16N_1
A5
L17P_1
A4
VCCO_1
VCCO_1
VCCINT
GND
GND
K
L
RHCLK5
RHCLK6
I/O
L15N_1
A7
RHCLK3
TRDY1
I/O
I/O
I/O
L13N_1
VREF_1
L15P_1
A8
L14N_1
A9
VCCAUX
VCCINT
GND
GND
VCCINT
GND
I/O
INPUT
GND
RHCLK2
RHCLK1
I/O
I/O
L12P_1
A12
I/O
L12N_1
A11
I/O
L11P_1
I/O
L13P_1
L14P_1
A10
VCCAUX
VCCINT
INPUT
INPUT
M
N
P
R
T
RHCLK0
I/O
D5
I/O
L11N_1
I/O
L09P_1
I/O
L10P_1
I/O
L10N_1
VCCO_1
VCCINT
INPUT
L17N_2
M2
GCLK1
INPUT
INPUT
L17P_2
RDWR_B
GCLK0
I/O
L08N_1
VREF_1
I/O
L25N_2
I/O
L09N_1
I/O
L07P_1
I/O
L07N_1
INPUT
GND
GND
INPUT
VCCO_1
INPUT
L20P_2
I/O
L25P_2
I/O
L05P_1
I/O
L05N_1
I/O
L08P_1
VCCO_2
I/O
INPUT
INPUT
INPUT
L23N_2
VREF_2
I/O
L02P_1
A14
I/O
L02N_1
A13
I/O
M1
INPUT
L20N_2
INPUT
L23P_2
I/O
L28N_2
I/O
L06N_1
I/O
L30P_2
A21
I/O
L01P_1
A16
I/O
L01N_1
A15
I/O
I/O
I/O
I/O
I/O
VCCO_2
GND
I/O
U
V
W
Y
L21N_2
L24N_2
L28P_2
L03P_1
L06P_1
I/O
L30N_2
A20
I/O
L03N_1
VREF_1
I/O
L21P_2
I/O
L24P_2
INPUT
L26N_2
INPUT
L26P_2
I/O
L04P_1
L18N_2
D1
DONE
GND
I/O
L31P_2
VS2
A19
GCLK3
I/O
L22N_2
VREF_2
I/O
L32N_2
CCLK
I/O
L22P_2
INPUT
L29N_2
I/O
L04N_1
VCCO_2
VCCO_2
GND
I/O
I/O
I/O
I/O
I/O
L19P_2
M0
I/O
L27N_2
A22
I/O
L27P_2
A23
INPUT
L29P_2
I/O
VREF_2
L19N_2
DIN
L31N_2
VS1
L32P_2
VS0
I/O
GND
D0
A18
A17
Bank 2
DS312-4_09_101905
DS312 (v4.1) July 19, 2013
www.xilinx.com
Product Specification
216
Spartan-3E FPGA Family: Pinout Descriptions
FG484: 484-ball Fine-pitch Ball Grid Array
The 484-ball fine-pitch ball grid array, FG484, supports the
XC3S1600E FPGA.
Table 154: FG484 Package Pinout (Cont’d)
XC3S1600E
Pin Name
FG484
Ball
Bank
Type
Table 154 lists all the FG484 package pins. They are sorted
by bank number and then by pin name. Pairs of pins that
form a differential I/O pair appear together in the table. The
table also shows the pin number for each pin and the pin
type, as defined earlier.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO_L12P_0
IO_L13N_0
A15
H14
G14
G13
F13
J13
H13
E12
F12
C12
B12
B11
C11
D11
E11
A9
I/O
I/O
IO_L13P_0
I/O
IO_L15N_0
I/O
An electronic version of this package pinout table and
footprint diagram is available for download from the Xilinx
website at:
IO_L15P_0
I/O
IO_L16N_0
I/O
IO_L16P_0
I/O
http://www.xilinx.com/support/documentation/data_sheets
/s3e_pin.zip
IO_L18N_0/GCLK5
IO_L18P_0/GCLK4
IO_L19N_0/GCLK7
IO_L19P_0/GCLK6
IO_L21N_0/GCLK11
IO_L21P_0/GCLK10
IO_L22N_0
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
I/O
Pinout Table
Table 154: FG484 Package Pinout
XC3S1600E
Pin Name
FG484
Ball
Bank
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO
IO
B6
I/O
I/O
IO_L22P_0
I/O
B13
C5
IO_L24N_0
I/O
IO
I/O
IO_L24P_0
A10
D10
C10
H8
I/O
IO
C14
E16
F9
I/O
IO_L25N_0/VREF_0
IO_L25P_0
VREF
I/O
IO
I/O
IO
I/O
IO_L27N_0
I/O
IO
F16
G8
I/O
IO_L27P_0
H9
I/O
IO
I/O
IO_L28N_0
C9
I/O
IO
H10
H15
J11
G12
C18
C19
A20
A21
A19
A18
C16
D16
A16
A17
B15
C15
G15
F15
D14
E14
A14
I/O
IO_L28P_0
B9
I/O
IO
I/O
IO_L29N_0
E9
I/O
IO
I/O
IO_L29P_0
D9
I/O
IO/VREF_0
IO_L01N_0
IO_L01P_0
IO_L03N_0/VREF_0
IO_L03P_0
IO_L04N_0
IO_L04P_0
IO_L06N_0
IO_L06P_0
IO_L07N_0
IO_L07P_0
IO_L09N_0/VREF_0
IO_L09P_0
IO_L10N_0
IO_L10P_0
IO_L11N_0
IO_L11P_0
IO_L12N_0/VREF_0
VREF
I/O
IO_L30N_0
B8
I/O
IO_L30P_0
A8
I/O
I/O
IO_L32N_0/VREF_0
IO_L32P_0
F7
VREF
I/O
VREF
I/O
F8
IO_L33N_0
A6
I/O
I/O
IO_L33P_0
A7
I/O
I/O
IO_L35N_0
A4
I/O
I/O
IO_L35P_0
A5
I/O
I/O
IO_L36N_0
E7
I/O
I/O
IO_L36P_0
D7
I/O
I/O
IO_L38N_0/VREF_0
IO_L38P_0
D6
VREF
I/O
VREF
I/O
D5
IO_L39N_0
B4
I/O
I/O
IO_L39P_0
B3
I/O
I/O
IO_L40N_0/HSWAP
IO_L40P_0
D4
DUAL
I/O
I/O
C4
I/O
IP
B19
INPUT
VREF
DS312 (v4.1) July 19, 2013
www.xilinx.com
Product Specification
217
Spartan-3E FPGA Family: Pinout Descriptions
Table 154: FG484 Package Pinout (Cont’d)
Table 154: FG484 Package Pinout (Cont’d)
XC3S1600E
Pin Name
FG484
Ball
XC3S1600E
Pin Name
FG484
Ball
Bank
Type
Bank
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IP
IP_L02N_0
IP_L02P_0
IP_L05N_0
IP_L05P_0
IP_L08N_0
IP_L08P_0
IP_L14N_0
IP_L14P_0
IP_L17N_0
IP_L17P_0
IP_L20N_0/GCLK9
IP_L20P_0/GCLK8
IP_L23N_0
IP_L23P_0
IP_L26N_0
IP_L26P_0
IP_L31N_0
IP_L31P_0
IP_L34N_0
IP_L34P_0
IP_L37N_0
IP_L37P_0
VCCO_0
E6
D17
D18
C17
B17
E15
D15
D13
C13
A12
A13
H11
H12
F10
F11
G9
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
GCLK
GCLK
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
DUAL
DUAL
DUAL
DUAL
VREF
I/O
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IO_L08N_1
IO_L08P_1
T22
U22
R19
R18
R16
T16
R21
R20
P18
P17
P22
R22
P15
P16
N18
N19
N16
N17
M20
N20
M22
I/O
I/O
IO_L09N_1
I/O
IO_L09P_1
I/O
IO_L10N_1
I/O
IO_L10P_1
I/O
IO_L11N_1
I/O
IO_L11P_1
I/O
IO_L12N_1/VREF_1
IO_L12P_1
VREF
I/O
IO_L13N_1
I/O
IO_L13P_1
I/O
IO_L14N_1
I/O
IO_L14P_1
I/O
IO_L15N_1
I/O
IO_L15P_1
I/O
G10
C8
IO_L16N_1/A11
IO_L16P_1/A12
IO_L17N_1/VREF_1
IO_L17P_1
DUAL
DUAL
VREF
I/O
D8
C7
C6
IO_L18N_1/A9/RHCLK1
RHCLK/
DUAL
A3
1
1
1
1
1
1
1
IO_L18P_1/A10/RHCLK0
N22
M16
M15
L21
L20
L19
L18
RHCLK/
DUAL
A2
B5
IO_L19N_1/A7/RHCLK3/
TRDY1
RHCLK/
DUAL
VCCO_0
B10
B14
B18
E8
VCCO_0
IO_L19P_1/A8/RHCLK2
RHCLK/
DUAL
VCCO_0
IO_L20N_1/A5/RHCLK5
RHCLK/
DUAL
VCCO_0
VCCO_0
F14
G11
Y22
AA22
W21
Y21
W20
V20
U19
V19
V22
W22
T19
T18
U20
U21
IO_L20P_1/A6/RHCLK4/
IRDY1
RHCLK/
DUAL
VCCO_0
IO_L01N_1/A15
IO_L01P_1/A16
IO_L02N_1/A13
IO_L02P_1/A14
IO_L03N_1/VREF_1
IO_L03P_1
IO_L04N_1
IO_L04P_1
IO_L05N_1
IO_L05P_1
IO_L06N_1
IO_L06P_1
IO_L07N_1/VREF_1
IO_L07P_1
IO_L21N_1/A3/RHCLK7
RHCLK/
DUAL
IO_L21P_1/A4/RHCLK6
RHCLK/
DUAL
1
1
1
1
1
1
1
1
1
1
IO_L22N_1/A1
IO_L22P_1/A2
IO_L23N_1/A0
IO_L23P_1
IO_L24N_1
IO_L24P_1
IO_L25N_1
IO_L25P_1
IO_L26N_1
IO_L26P_1
K22
L22
K17
K16
K19
K18
K15
J15
J20
J21
DUAL
DUAL
DUAL
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
DS312 (v4.1) July 19, 2013
www.xilinx.com
Product Specification
218
Spartan-3E FPGA Family: Pinout Descriptions
Table 154: FG484 Package Pinout (Cont’d)
Table 154: FG484 Package Pinout (Cont’d)
XC3S1600E
Pin Name
FG484
Ball
XC3S1600E
Pin Name
FG484
Ball
Bank
Type
Bank
Type
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IO_L27N_1
IO_L27P_1
IO_L28N_1/VREF_1
IO_L28P_1
IO_L29N_1
IO_L29P_1
IO_L30N_1
IO_L30P_1
IO_L31N_1
IO_L31P_1
IO_L32N_1
IO_L32P_1
IO_L33N_1
IO_L33P_1
IO_L34N_1
IO_L34P_1
IO_L35N_1
IO_L35P_1
IO_L36N_1
IO_L36P_1
IO_L37N_1/LDC0
IO_L37P_1/HDC
IO_L38N_1/LDC2
IO_L38P_1/LDC1
IP
J17
J18
I/O
I/O
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
VCCO_1
VCCO_1
K21
L16
P21
R17
V21
Y8
VCCO
VCCO
VCCO
VCCO
VCCO
I/O
H21
H22
H20
H19
H17
G17
F22
G22
F20
G20
G18
G19
D22
E22
F19
F18
E20
E19
C21
C22
B21
B22
D20
F21
G16
H16
J16
VREF
I/O
VCCO_1
VCCO_1
I/O
VCCO_1
I/O
IO
I/O
IO
Y9
I/O
I/O
IO
AA10
AB5
AB13
AB14
AB16
AB18
AB11
AA12
AB4
AB21
AB3
AA3
Y5
I/O
I/O
IO
I/O
I/O
IO
I/O
I/O
IO
I/O
I/O
IO
I/O
I/O
IO
I/O
I/O
IO/D5
DUAL
DUAL
VREF
VREF
DUAL
DUAL
DUAL
DUAL
I/O
I/O
IO/M1
I/O
IO/VREF_2
IO/VREF_2
IO_L01N_2/INIT_B
IO_L01P_2/CSO_B
IO_L03N_2/MOSI/CSI_B
IO_L03P_2/DOUT/BUSY
IO_L04N_2
IO_L04P_2
IO_L06N_2
IO_L06P_2
IO_L07N_2
IO_L07P_2
IO_L09N_2/VREF_2
IO_L09P_2
IO_L10N_2
IO_L10P_2
IO_L11N_2
IO_L11P_2
IO_L12N_2
IO_L12P_2
IO_L13N_2/VREF_2
IO_L13P_2
IO_L14N_2
IO_L14P_2
IO_L16N_2
IO_L16P_2
IO_L17N_2
IO_L17P_2
I/O
I/O
I/O
I/O
DUAL
DUAL
DUAL
DUAL
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VREF
VREF
VCCO
VCCO
W5
W6
V6
I/O
W7
I/O
Y7
I/O
IP
U7
I/O
IP
V7
I/O
IP
V8
VREF
I/O
IP
W8
IP
J22
T8
I/O
IP
K20
L15
M18
N15
N21
P20
R15
T17
T20
U18
D21
L17
E21
H18
U8
I/O
IP
AB8
AA8
W9
I/O
IP
I/O
IP
I/O
IP
V9
I/O
IP
R9
VREF
I/O
IP
T9
IP
AB9
AB10
U10
T10
R10
P10
I/O
IP
I/O
IP
I/O
IP/VREF_1
IP/VREF_1
VCCO_1
VCCO_1
I/O
I/O
I/O
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Product Specification
219
Spartan-3E FPGA Family: Pinout Descriptions
Table 154: FG484 Package Pinout (Cont’d)
Table 154: FG484 Package Pinout (Cont’d)
XC3S1600E
Pin Name
FG484
Ball
XC3S1600E
Pin Name
FG484
Ball
Bank
Type
Bank
Type
2
IO_L19N_2/D6/GCLK13
IO_L19P_2/D7/GCLK12
IO_L20N_2/D3/GCLK15
IO_L20P_2/D4/GCLK14
IO_L22N_2/D1/GCLK3
IO_L22P_2/D2/GCLK2
U11
V11
T11
R11
W12
Y12
DUAL/
GCLK
2
2
2
2
2
2
2
IP_L08N_2
IP_L08P_2
AB7
AB6
Y10
INPUT
INPUT
INPUT
INPUT
VREF
2
2
2
2
2
DUAL/
GCLK
IP_L15N_2
IP_L15P_2
W10
AA11
Y11
DUAL/
GCLK
IP_L18N_2/VREF_2
IP_L18P_2
INPUT
DUAL/
GCLK
IP_L21N_2/M2/GCLK1
P12
DUAL/
GCLK
DUAL/
GCLK
2
IP_L21P_2/RDWR_B/ GCLK0
R12
DUAL/
GCLK
DUAL/
GCLK
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IP_L24N_2
IP_L24P_2
IP_L31N_2/VREF_2
IP_L31P_2
IP_L34N_2
IP_L34P_2
IP_L37N_2
IP_L37P_2
VCCO_2
R13
T13
T15
U15
Y16
W16
AA19
AB19
T12
U9
INPUT
INPUT
VREF
INPUT
INPUT
INPUT
INPUT
INPUT
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
I/O
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO_L23N_2/DIN/D0
IO_L23P_2/M0
IO_L25N_2
U12
V12
DUAL
DUAL
I/O
Y13
IO_L25P_2
W13
U14
U13
T14
I/O
IO_L26N_2/VREF_2
IO_L26P_2
VREF
I/O
IO_L27N_2
I/O
IO_L27P_2
R14
Y14
I/O
IO_L28N_2
I/O
VCCO_2
IO_L28P_2
AA14
W14
V14
I/O
VCCO_2
V15
AA5
AA9
AA13
AA18
C1
IO_L29N_2
I/O
VCCO_2
IO_L29P_2
I/O
VCCO_2
IO_L30N_2
AB15
AA15
W15
Y15
I/O
VCCO_2
IO_L30P_2
I/O
VCCO_2
IO_L32N_2
I/O
IO_L01N_3
IO_L01P_3
IO_L02N_3/VREF_3
IO_L02P_3
IO_L03N_3
IO_L03P_3
IO_L04N_3
IO_L04P_3
IO_L05N_3
IO_L05P_3
IO_L06N_3
IO_L06P_3
IO_L07N_3
IO_L07P_3
IO_L08N_3/VREF_3
IO_L08P_3
IO_L09N_3
IO_L09P_3
IO_L10N_3
IO_L10P_3
IO_L32P_2
I/O
C2
I/O
IO_L33N_2
U16
V16
I/O
D2
VREF
I/O
IO_L33P_2
I/O
D3
IO_L35N_2/A22
IO_L35P_2/A23
IO_L36N_2
AB17
AA17
W17
Y17
DUAL
DUAL
I/O
E3
I/O
E4
I/O
E1
I/O
IO_L36P_2
I/O
D1
I/O
IO_L38N_2/A20
IO_L38P_2/A21
IO_L39N_2/VS1/A18
IO_L39P_2/VS2/A19
IO_L40N_2/CCLK
IO_L40P_2/VS0/A17
IP
Y18
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
F4
I/O
W18
AA20
AB20
W19
Y19
F3
I/O
G5
I/O
G4
I/O
F1
I/O
G1
I/O
V17
G6
VREF
I/O
IP
AB2
AA4
Y4
G7
IP_L02N_2
H4
I/O
IP_L02P_2
H5
I/O
IP_L05N_2
Y6
H2
I/O
IP_L05P_2
AA6
H3
I/O
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Product Specification
220
Spartan-3E FPGA Family: Pinout Descriptions
Table 154: FG484 Package Pinout (Cont’d)
Table 154: FG484 Package Pinout (Cont’d)
XC3S1600E
Pin Name
FG484
Ball
XC3S1600E
Pin Name
FG484
Ball
Bank
Type
Bank
Type
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO_L11N_3
IO_L11P_3
H1
J1
I/O
I/O
3
IO_L33N_3
W1
V1
U4
U3
V4
V3
W3
W2
Y2
Y1
AA1
AA2
F2
I/O
3
IO_L33P_3
I/O
IO_L12N_3
J6
I/O
3
IO_L34N_3
I/O
IO_L12P_3
J5
I/O
3
IO_L34P_3
I/O
IO_L13N_3/VREF_3
IO_L13P_3
J3
VREF
I/O
3
IO_L35N_3
I/O
K3
J8
3
IO_L35P_3
I/O
IO_L14N_3
I/O
3
IO_L36N_3/VREF_3
VREF
I/O
IO_L14P_3
K8
K4
K5
K1
L1
I/O
3
IO_L36P_3
IO_L37N_3
IO_L37P_3
IO_L38N_3
IO_L38P_3
IP
IO_L15N_3
I/O
3
I/O
IO_L15P_3
I/O
3
I/O
IO_L16N_3
I/O
3
I/O
IO_L16P_3
I/O
3
I/O
IO_L17N_3
L7
I/O
3
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VREF
VREF
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
GND
GND
GND
GND
GND
GND
GND
IO_L17P_3
K7
L5
I/O
3
IP
F5
IO_L18N_3/LHCLK1
IO_L18P_3/LHCLK0
IO_L19N_3/LHCLK3/IRDY2
IO_L19P_3/LHCLK2
IO_L20N_3/LHCLK5
IO_L20P_3/LHCLK4/TRDY2
IO_L21N_3/LHCLK7
IO_L21P_3/LHCLK6
IO_L22N_3
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
I/O
3
IP
G3
H7
J7
M5
M8
L8
3
IP
3
IP
3
IP
K2
K6
M2
M6
N3
P3
R8
T1
N1
M1
M4
M3
N6
N7
P8
N8
N4
N5
P2
P1
R7
P7
P6
P5
R2
R1
R3
R4
T6
R6
U2
U1
T4
T5
3
IP
3
IP
3
IP
3
IP
3
IP
IO_L22P_3
I/O
3
IP
IO_L23N_3
I/O
3
IP
IO_L23P_3
I/O
3
IP
T7
IO_L24N_3/VREF_3
IO_L24P_3
VREF
I/O
3
3
IP
U5
W4
L3
IP
IO_L25N_3
I/O
3
IP/VREF_3
IP/VREF_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
GND
IO_L25P_3
I/O
3
T3
IO_L26N_3
I/O
3
E2
H6
J2
IO_L26P_3
I/O
3
IO_L27N_3
I/O
3
IO_L27P_3
I/O
3
M7
N2
R5
V2
A1
A11
A22
B7
B16
C3
C20
IO_L28N_3
I/O
3
IO_L28P_3
I/O
3
IO_L29N_3
I/O
3
IO_L29P_3
I/O
GND
GND
GND
GND
GND
GND
GND
IO_L30N_3
I/O
GND
IO_L30P_3
I/O
GND
IO_L31N_3
I/O
GND
IO_L31P_3
I/O
GND
IO_L32N_3
I/O
GND
IO_L32P_3
I/O
GND
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Product Specification
221
Spartan-3E FPGA Family: Pinout Descriptions
Table 154: FG484 Package Pinout (Cont’d)
Table 154: FG484 Package Pinout (Cont’d)
XC3S1600E
Pin Name
FG484
Ball
XC3S1600E
Pin Name
FG484
Ball
Bank
Type
Bank
Type
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
E10
E13
F6
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AB1
AB12
AB22
AA21
B1
GND
GND
GND
GND
GND
GND
GND
F17
G2
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
DONE
CONFIG
CONFIG
JTAG
PROG_B
TCK
G21
J4
E17
B2
TDI
JTAG
J9
TDO
B20
D19
D12
E5
JTAG
J12
J14
J19
K10
K12
L2
TMS
JTAG
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
E18
K14
L4
L6
M19
N9
L9
L13
M10
M14
M17
M21
N11
N13
P4
V5
V18
W11
J10
K9
K11
K13
L10
L11
L12
L14
M9
P9
P11
P14
P19
T2
M11
M12
M13
N10
N12
N14
P13
T21
U6
U17
V10
V13
Y3
Y20
AA7
AA16
User I/Os by Bank
Table 155 indicates how the 304 available user-I/O pins are
distributed between the four I/O banks on the FG484
package.
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Product Specification
222
Spartan-3E FPGA Family: Pinout Descriptions
Table 155: User I/Os Per Bank for the XC3S1600E in the FG484 Package
All Possible I/O Pins by Type
Package
Edge
I/O Bank
Maximum I/O
(2)
I/O
56
INPUT
DUAL
1
VREF(1)
CLK
Top
0
1
2
3
94
94
22
16
18
16
72
7
7
8
Right
50
21
24
0
0(2)
0(2)
8
Bottom
Left
94
45
7
94
63
7
TOTAL
376
214
46
28
16
Notes:
1. Some VREF and CLK pins are on INPUT pins.
2. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
Footprint Migration Differences
The XC3S1600E FPGA is the only Spartan-3E device
offered in the FG484 package.
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Product Specification
223
Spartan-3E FPGA Family: Pinout Descriptions
Bank 0
X-Ref Target - Figure 88
FG484 Footprint
1
2
3
4
5
6
7
8
9
10
11
Left Half of Package
(top view)
INPUT INPUT
L37P_0
I/O
L35N_0
I/O
L35P_0
I/O
L33N_0
I/O
L33P_0
I/O
L30P_0
I/O
L24N_0
I/O
L24P_0
GND
GND
A
B
C
D
E
F
L37N_0
I/O
I/O
L39P_0
I/O
L39N_0
I/O
L30N_0
I/O
L28P_0
PROG_B
VCCO_0
VCCO_0
TDI
I/O
GND
L21N_0
GCLK11
I/O: Unrestricted,
214
I/O
general-purpose user I/O
I/O
L01N_3
I/O
L01P_3
I/O
L40P_0
INPUT INPUT INPUT
I/O
L28N_0
I/O
L25P_0
GND
I/O
L21P_0
L34P_0
L34N_0
L31N_0
GCLK10
INPUT: User I/O or
reference resistor input for
bank
I/O
L02N_3
VREF_3
I/O
I/O
I/O
72
I/O
L04P_3
I/O
L02P_3
I/O
L38P_0
I/O
L36P_0
INPUT
L31P_0
I/O
L29P_0
I/O
L22N_0
L40N_0
L38N_0
L25N_0
HSWAP
VREF_0
VREF_0
I/O
L04N_3
I/O
L03N_3
I/O
I/O
I/O
I/O
DUAL: Configuration pin,
VCCO_3
INPUT
GND
VCCAUX
VCCO_0
INPUT
GND
GND
46
28
16
2
L03P_3
L36N_0
L29N_0
L22P_0
then possible user I/O
I/O
L32N_0
VREF_0
I/O
L07N_3
I/O
L05P_3
I/O
L05N_3
I/O
L32P_0
INPUT INPUT
VREF: User I/O or input
voltage reference for bank
INPUT
I/O
L23N_0
L23P_0
I/O
I/O
L07P_3
I/O
L06P_3
I/O
L06N_3
I/O
L08P_3
INPUT INPUT
VCCO_0
INPUT
I/O
L08N_3
G
H
J
CLK: User I/O, input, or
clock buffer input
L26N_0
L26P_0
VREF_3
INPUT
L20N_0
GCLK9
I/O
L11N_3
I/O
L10N_3
I/O
L10P_3
I/O
I/O
I/O
I/O
VCCO_3
INPUT
INPUT
I/O
CONFIG: Dedicated
configuration pins
L09N_3
L09P_3
L27N_0
L27P_0
I/O
L13N_3
VREF_3
I/O
L11P_3
I/O
L12P_3
I/O
L12N_3
I/O
L14N_3
VCCO_3
INPUT
GND
GND
GND VCCINT
I/O
JTAG: Dedicated JTAG
port pins
4
I/O
L16N_3
I/O
L13P_3
I/O
I/O
I/O
I/O
INPUT
GND
VCCINT GND VCCINT
GND VCCINT VCCINT
VCCINT GND VCCINT
K
L
L15N_3
L15P_3
L17P_3
L14P_3
GND: Ground
48
28
16
10
0
I/O
L18N_3
LHCLK1
I/O
L19P_3
LHCLK2
I/O
L16P_3
INPUT
VREF_3
I/O
L17N_3
VCCAUX
VCCO: Output voltage
supply for bank
I/O
L20P_3
LHCLK4
TRDY2
I/O
L19N_3
LHCLK3
IRDY2
I/O
L21P_3
I/O
L21N_3
I/O
L18P_3
VCCO_3
INPUT
VCCO_3
INPUT
M
N
P
R
T
LHCLK6 LHCLK7 LHCLK0
VCCINT: Internal core
supply voltage (+1.2V)
I/O
L20N_3
LHCLK5
I/O
I/O
I/O
L22N_3
I/O
L22P_3
I/O
L23P_3
VCCAUX
INPUT
INPUT
VCCINT GND
L24N_3
VREF_3
L24P_3
VCCAUX: Auxiliary supply
voltage (+2.5V)
I/O
L25P_3
I/O
L25N_3
I/O
L27P_3
I/O
L27N_3
I/O
L26P_3
I/O
L23N_3
I/O
GND
GND
GND
L17P_2
N.C.: Not connected
I/O
I/O
I/O
L28P_3
I/O
L28N_3
I/O
L29N_3
I/O
L29P_3
I/O
L30P_3
I/O
L26N_3
I/O
L17N_2
L20P_2
VCCO_3
INPUT
L13N_2
D4
GCLK14
VREF_2
I/O
INPUT
VREF_3
I/O
L32N_3
I/O
L32P_3
I/O
L30N_3
I/O
L10N_2
I/O
L13P_2
I/O
L16P_2
L20N_2
D3
INPUT
GND
INPUT
GCLK15
I/O
I/O
L31P_3
I/O
L31N_3
I/O
L34P_3
I/O
L34N_3
I/O
L07N_2
I/O
L10P_2
I/O
L16N_2
L19N_2
D6
VCCO_2
INPUT
GND
U
V
W
Y
GCLK13
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L19P_2
D7
VCCO_3
VCCAUX
GND
L09N_2
L33P_3
L35P_3
L35N_3
L04P_2
L07P_2
L12P_2
VREF_2
GCLK12
I/O
L03P_2
DOUT
BUSY
I/O
L36N_3
VREF_3
I/O
L33N_3
I/O
L36P_3
I/O
L04N_2
I/O
L06N_2
I/O
L09P_2
I/O
L12N_2
INPUT
L15P_2
VCCAUX
INPUT
I/O
I/O
L37P_3
I/O
L37N_3
INPUT
L02P_2
INPUT
L05N_2
I/O
L06P_2
INPUT INPUT
L03N_2
MOSI
GND
I/O
I/O
L15N_2
L18P_2
CSI_B
I/O
INPUT
L18N_2
VREF_2
A
A
I/O
L38N_3
I/O
L38P_3
INPUT
L02N_2
INPUT
L05P_2
I/O
L11P_2
VCCO_2
VCCO_2
GND
I/O
L01P_2
CSO_B
I/O
A
B
I/O
VREF_2
INPUT INPUT
I/O
L11N_2
I/O
L14N_2
I/O
L14P_2
I/O
D5
GND
INPUT
I/O
L01N_2
L08P_2
L08N_2
INIT_B
Bank 2
DS312_10_101905
Figure 88: FG484 Package Footprint (top view)
DS312 (v4.1) July 19, 2013
www.xilinx.com
Product Specification
224
Spartan-3E FPGA Family: Pinout Descriptions
FG484 Footprint
Bank 0
12
13
14
15
16
17
18
19
20
21
22
Right Half of Package
(top view)
I/O
L12N_0
VREF_0
I/O
L03N_0
VREF_0
INPUT INPUT
L17N_0
I/O
L12P_0
I/O
L07N_0
I/O
L07P_0
I/O
L04P_0
I/O
L04N_0
I/O
L03P_0
GND
A
B
C
D
E
F
L17P_0
I/O
L19P_0
GCLK6
I/O
L09N_0
VREF_0
I/O
L38N_1
LDC2
I/O
L38P_1
LDC1
INPUT
L05P_0
VCCO_0
VCCO_0
I/O
GND
INPUT
TDO
GND
I/O
L19N_0
GCLK7
I/O
L37N_1
LDC0
I/O
L37P_1
HDC
INPUT
L14P_0
I/O
L09P_0
I/O
L06N_0
INPUT
L05N_0
I/O
L01N_0
I/O
L01P_0
I/O
INPUT
L14N_0
I/O
L11N_0
INPUT
L08P_0
I/O
L06P_0
INPUT INPUT
L02N_0
INPUT
VREF_1
I/O
L34N_1
VCCAUX
TMS
INPUT
L02P_0
I/O
L18N_0
GCLK5
I/O
L11P_0
INPUT
L08N_0
I/O
L36P_1
I/O
L36N_1
I/O
L34P_1
VCCAUX
VCCO_1
INPUT
GND
GND
I/O
TCK
I/O
L18P_0
GCLK4
I/O
L15P_0
I/O
L10P_0
I/O
L35P_1
I/O
L35N_1
I/O
L32N_1
I/O
L31N_1
VCCO_0
I/O
GND
I/O
VREF_0
I/O
L15N_0
I/O
L13P_0
I/O
L10N_0
I/O
L30P_1
I/O
L33N_1
I/O
L33P_1
I/O
L32P_1
I/O
L31P_1
INPUT
INPUT
INPUT
G
H
J
INPUT
L20P_0
GCLK8
I/O
L28N_1
VREF_1
I/O
L16P_0
I/O
L13N_0
I/O
L30N_1
I/O
L29P_1
I/O
L29N_1
I/O
L28P_1
VCCO_1
I/O
I/O
L16N_0
I/O
L25P_1
I/O
L27N_1
I/O
L27P_1
I/O
L26N_1
I/O
L26P_1
GND
GND
GND
INPUT
I/O
L23N_1
A0
I/O
L22N_1
A1
I/O
I/O
I/O
I/O
VCCAUX
VCCO_1
GND VCCINT
INPUT
K
L
L25N_1
L23P_1
L24P_1
L24N_1
I/O
L20P_1
A6
I/O
I/O
L21N_1
A3
I/O
I/O
L22P_1
A2
INPUT
VREF_1
L21P_1
A4
L20N_1
A5
VCCO_1
VCCINT GND VCCINT INPUT
I/O
RHCLK4
RHCLK6 RHCLK7
RHCLK5
IRDY1
I/O
I/O
I/O
L17N_1
VREF_1
L19N_1
L19P_1
L18N_1
A9
VCCAUX
VCCINT VCCINT GND
GND
INPUT
GND
INPUT
VCCO_1
A7
M
N
P
R
T
A8
RHCLK3
RHCLK2
RHCLK1
TRDY1
I/O
I/O
L16N_1
A11
I/O
L16P_1
A12
I/O
L15N_1
I/O
L15P_1
I/O
L17P_1
L18P_1
A10
VCCINT GND VCCINT INPUT
INPUT
RHCLK0
I/O
L12N_1
VREF_1
I/O
L21N_2
I/O
L14P_1
I/O
L12P_1
I/O
L13N_1
VCCINT GND
GND
INPUT
M2
GCLK1
L14N_1
INPUT
INPUT
I/O
L27P_2
I/O
L10N_1
I/O
L09P_1
I/O
L09N_1
I/O
L11P_1
I/O
L11N_1
I/O
L13P_1
L21P_2
VCCO_1
INPUT
GND
INPUT
RDWR_B L24N_2
GCLK0
INPUT
L31N_2
VREF_2
INPUT
VCCO_2
I/O
L27N_2
I/O
L10P_1
I/O
L06P_1
I/O
L06N_1
I/O
L08N_1
INPUT
GND
L24P_2
I/O
I/O
L26N_2
VREF_2
I/O
L07N_1
VREF_1
I/O
L26P_2
INPUT
L31P_2
I/O
L33N_2
I/O
L04N_1
I/O
L07P_1
I/O
L08P_1
L23N_2
INPUT
U
V
W
Y
DIN
D0
I/O
L23P_2
M0
I/O
L29P_2
I/O
L33P_2
I/O
L04P_1
I/O
L03P_1
I/O
L05N_1
VCCO_2
VCCAUX
VCCO_1
GND
INPUT
I/O
I/O
L38P_2
A21
I/O
L40N_2
CCLK
I/O
L03N_1
VREF_1
I/O
L02N_1
A13
I/O
L25P_2
I/O
L29N_2
I/O
L32N_2
INPUT
L34P_2
I/O
L36N_2
I/O
L05P_1
L22N_2
D1
GCLK3
I/O
I/O
I/O
L38N_2
A20
I/O
L02P_1
A14
I/O
L01N_1
A15
I/O
L25N_2
I/O
L28N_2
I/O
L32P_2
INPUT
L34N_2
I/O
L36P_2
L22P_2
D2
L40P_2
VS0
GND
I/O
L39N_2
VS1
A18
GCLK2
A17
I/O
L35P_2
A23
I/O
L01P_1
A16
A
A
I/O
M1
I/O
L28P_2
I/O
L30P_2
INPUT
L37N_2
VCCO_2
VCCO_2
GND
I/O
DONE
I/O
I/O
L35N_2
A22
A
B
I/O
L30N_2
INPUT
L37P_2
I/O
VREF_2
L39P_2
VS2
GND
I/O
I/O
I/O
GND
A19
Bank 2
DS312_11_101905
DS312 (v4.1) July 19, 2013
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Product Specification
225
Spartan-3E FPGA Family: Pinout Descriptions
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revision
03/01/2005
03/21/2005
Initial Xilinx release.
1.1
Added XC3S250E in the CP132 package to Table 129. Corrected number of differential I/O pairs on
CP132. Added pinout and footprint information for the CP132, FG400, and FG484 packages. Removed
IRDY and TRDY pins from the VQ100, TQ144, and PQ208 packages.
11/23/2005
03/22/2006
2.0
3.0
Corrected title of Table 153. Updated differential pair numbering for some pins in Bank 0 of the FG400
package, affecting Table 152 and Figure 87. Pin functionality and ball assignment were not affected.
Added Package Thermal Characteristics section. Added package mass values to Table 125.
Included I/O pins, not just input-only pins under the VREF description in Table 124. Clarified that some
global clock inputs are Input-only pins in Table 124. Added information on the XC3S100E in the CP132
package, affecting Table 129, Table 130, Table 133, Table 134, Table 136, and Figure 81. Ball A12 on
the XC3S1600E in the FG320 package a full I/O pin, not an Input-only pin. Corrected the I/O counts
for the XC3S1600E in the FG320 package, affecting Table 129, Table 150, Table 151, and Figure 86.
Corrected pin type for XC3S1600E balls N14 and N15 in Table 148.
05/19/2006
11/09/2006
3.1
3.4
Minor text edits.
Added package thermal data for the XC3S100E in the CP132 package to Table 130. Corrected pin
migration arrows for balls E17 and F4 between the XC3S500E and XC3S1600E in Table 151.
Promoted Module 4 to Production status. Synchronized all modules to v3.4.
03/16/2007
05/29/2007
3.5
3.6
Minor formatting changes.
Corrected ‘Lxx’ to ‘Lxxy’ in Table 124. Noted that some GCLK and VREF pins are on INPUT pins in
Table 124 and Table 129. Added link before Table 127 to Material Declaration Data Sheets.
04/18/2008
3.7
Added XC3S500E VQG100 package. Added Material Declaration Data Sheet links in Table 127.
Updated Thermal Characteristics in Table 130. Updated links.
08/26/2009
10/29/2012
3.8
4.0
Minor typographical updates.
Added Notice of Disclaimer. This product is not recommended for new designs.
Updated the XC3S250E-FT256 in Table 129.
07/19/2013
4.1
Removed banner. This product IS recommended for new designs.
DS312 (v4.1) July 19, 2013
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Product Specification
226
Spartan-3E FPGA Family: Pinout Descriptions
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED
WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE
SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
CRITICAL APPLICATIONS DISCLAIMER
XILINX PRODUCTS (INCLUDING HARDWARE, SOFTWARE AND/OR IP CORES) ARE NOT DESIGNED OR INTENDED TO BE
FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS IN LIFE-SUPPORT OR
SAFETY DEVICES OR SYSTEMS, CLASS III MEDICAL DEVICES, NUCLEAR FACILITIES, APPLICATIONS RELATED TO THE
DEPLOYMENT OF AIRBAGS, OR ANY OTHER APPLICATIONS THAT COULD LEAD TO DEATH, PERSONAL INJURY OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE (INDIVIDUALLY AND COLLECTIVELY, “CRITICAL APPLICATIONS”). FURTHERMORE,
XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN ANY APPLICATIONS THAT AFFECT CONTROL OF A
VEHICLE OR AIRCRAFT, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF
SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE
OPERATOR. CUSTOMER AGREES, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE XILINX
PRODUCTS, TO THOROUGHLY TEST THE SAME FOR SAFETY PURPOSES. TO THE MAXIMUM EXTENT PERMITTED BY
APPLICABLE LAW, CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN CRITICAL
APPLICATIONS.
AUTOMOTIVE APPLICATIONS DISCLAIMER
XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING
FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A
VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN
THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III)
USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY
USE OF XILINX PRODUCTS IN SUCH APPLICATIONS.
DS312 (v4.1) July 19, 2013
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Product Specification
227
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