XC3S400AN-4FTG256I [XILINX]
Field Programmable Gate Array, 896 CLBs, 400000 Gates, 667MHz, 8064-Cell, CMOS, PBGA256, ROHS COMPLIANT, FTBGA-256;型号: | XC3S400AN-4FTG256I |
厂家: | XILINX, INC |
描述: | Field Programmable Gate Array, 896 CLBs, 400000 Gates, 667MHz, 8064-Cell, CMOS, PBGA256, ROHS COMPLIANT, FTBGA-256 时钟 栅 可编程逻辑 |
文件: | 总123页 (文件大小:3574K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
1
Spartan-3AN FPGA Family Data Sheet
DS557 June 12, 2014
Product Specification
Module 1:
Introduction and Ordering Information
Module 3:
DC and Switching Characteristics
DS557 (v4.2) June 12, 2014
DS557 (v4.2) June 12, 2014
•
•
•
•
•
•
•
•
Introduction
Features
•
DC Electrical Characteristics
•
•
•
Absolute Maximum Ratings
Supply Voltage Specifications
Recommended Operating Conditions
Architectural Overview
Configuration Overview
In-system Flash Memory Overview
General I/O Capabilities
Supported Packages and Package Marking
Ordering Information
•
Switching Characteristics
•
•
•
•
•
•
•
•
I/O Timing
Configurable Logic Block (CLB) Timing
Multiplier Timing
Block RAM Timing
Module 2:
Functional Description
DS557 (v4.2) June 12, 2014
Digital Clock Manager (DCM) Timing
Suspend Mode Timing
Device DNA Timing
Configuration and JTAG Timing
The functionality of the Spartan®-3AN FPGA family is
described in the following documents:
Module 4:
Pinout Descriptions
•
UG331: Spartan-3 Generation FPGA User Guide
•
•
•
•
Clocking Resources
Digital Clock Managers (DCMs)
Block RAM
DS557 (v4.2) June 12, 2014
•
•
•
•
Pin Descriptions
Package Overview
Pinout Tables
Configurable Logic Blocks (CLBs)
-
-
-
Distributed RAM
SRL16 Shift Registers
Carry and Arithmetic Logic
Footprint Diagrams
Table 1: Production Status of Spartan-3AN FPGAs
•
•
•
•
•
•
•
•
•
I/O Resources
Spartan-3AN FPGA
XC3S50AN
Status
Embedded Multiplier Blocks
Programmable Interconnect
ISE® Design Tools and IP Cores
Embedded Processing and Control Solutions
Pin Types and Package Overview
Package Drawings
Production
Production
Production
Production
Production
XC3S200AN
XC3S400AN
XC3S700AN
Powering FPGAs
Power Management
XC3S1400AN
•
UG332: Spartan-3 Generation Configuration User Guide
Additional information on the Spartan-3AN family can be
found at:
http://www.xilinx.com/support/index.html/content/xilinx/en/s
upportNav/silicon_devices/fpga/spartan-3an.html.
•
•
•
•
Configuration Overview
Configuration Pins and Behavior
Bitstream Sizes
Detailed Descriptions by Mode
-
-
-
-
-
-
-
Self-contained In-System Flash mode
Master Serial Mode using Platform Flash PROM
Master SPI Mode using Commodity Serial Flash
Master BPI Mode using Commodity Parallel Flash
Slave Parallel (SelectMAP) using a Processor
Slave Serial using a Processor
JTAG Mode
•
•
•
ISE iMPACT Programming Examples
MultiBoot Reconfiguration
Design Authentication using Device DNA
•
•
UG333: Spartan-3AN In-System Flash User Guide
UG334: Spartan-3AN Starter Kit User Guide
© Copyright 2007–2014 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
DS557 June 12, 2014
www.xilinx.com
Product Specification
1
9
Spartan-3AN FPGA Family:
Introduction and Ordering Information
DS557 (v4.2) June 12, 2014
Product Specification
Introduction
The Spartan®-3AN FPGA family combines the best attributes of a
leading edge, low cost FPGA with nonvolatile technology across a
broad range of densities. The family combines all the features of
the Spartan-3A FPGA family plus leading technology in-system
Flash memory for configuration and nonvolatile data storage.
•
•
Buried configuration interface
Unique Device DNA serial number in each device for
design Authentication to prevent unauthorized copying
•
Flash memory sector protection and lockdown
•
•
Configuration watchdog timer automatically recovers from
configuration errors
Suspend mode reduces system power consumption
•
•
Full hot-swap compliance
Multi-voltage, multi-standard SelectIO™ interface pins
•
•
The Spartan-3AN FPGAs are part of the Extended Spartan-3A
family, which also includes the Spartan-3A FPGAs and the higher
density Spartan-3A DSP FPGAs. The Spartan-3AN FPGA family
is excellent for space-constrained applications such as blade
servers, medical devices, automotive infotainment, telematics,
GPS, and other small consumer products. Combining FPGA and
Flash technology minimizes chip count, PCB traces and overall
size while increasing system reliability.
The Spartan-3AN FPGA internal configuration interface is
completely self-contained, increasing design security. The family
maintains full support for external configuration. The Spartan-3AN
FPGA is the world’s first nonvolatile FPGA with MultiBoot,
supporting two or more configuration files in one device, allowing
alternative configurations for field upgrades, test modes, or
multiple system configurations.
Retains all design state and FPGA configuration data
Fast response time, typically less than 100 μs
•
•
Up to 502 I/O pins or 227 differential signal pairs
LVCMOS, LVTTL, HSTL, and SSTL single-ended signal
standards
3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
Up to 24 mA output drive
3.3V 10% compatibility and hot swap compliance
622+ Mb/s data transfer rate per I/O
DDR/DDR2 SDRAM support up to 400 Mb/s
•
•
•
•
•
•
Features
LVDS, RSDS, mini-LVDS, PPDS, and HSTL/SSTL
differential I/O
•
•
The new standard for low cost nonvolatile FPGA solutions
Eliminates traditional nonvolatile FPGA limitations with the
advanced 90 nm Spartan-3A device feature set
•
•
Abundant, flexible logic resources
•
•
•
Densities up to 25,344 logic cells
Optional shift register or distributed RAM support
Enhanced 18 x 18 multipliers with optional pipeline
•
Memory, multipliers, DCMs, SelectIO, hot swap, power
management, etc.
•
•
Integrated robust configuration memory
Hierarchical SelectRAM™ memory architecture
•
•
Up to eight Digital Clock Managers (DCMs)
Eight global clocks and eight additional clocks per each half
of device, plus abundant low-skew routing
•
•
•
•
Saves board space
Improves ease-of-use
Simplifies design
Up to 576 Kbits of dedicated block RAM
Up to 176 Kbits of efficient distributed RAM
•
•
Reduces support issues
Plentiful amounts of nonvolatile memory available to the user
•
Complete Xilinx® ISE® and WebPACK™ software
development system support
MicroBlaze™ and PicoBlaze embedded processor cores
Fully compliant 32-/64-bit 33 MHz PCI™ technology support
Low-cost QFP and BGA Pb-free (RoHS) packaging options
•
•
•
•
Up to 11+ Mb available
MultiBoot support
Embedded processing and code shadowing
Scratchpad memory
•
•
•
•
•
•
Robust 100K Flash memory program/erase cycles
20 years Flash memory data retention
Security features provide bitstream anti-cloning protection
•
Pin-compatible with the same packages in the
Spartan-3A FPGA family
Table 2: Summary of Spartan-3AN FPGA Attributes
System Equivalent
Distributed BlockRAM Dedicated
Maximum Max Differential Bitstream In-System
Device
Gates Logic Cells CLBs Slices RAM Bits(1)
Bits(1)
Multipliers DCMs User I/O
I/O Pairs
Size(1) Flash Bits
XC3S50AN
XC3S200AN
XC3S400AN
XC3S700AN
50K
1,584
4,032
8,064
13,248
25,344
176
448
896
1,472 5,888
2,816 11,264
704
1,792
3,584
11K
28K
56K
92K
176K
54K
3
2
4
4
8
8
108
195
311
372
502
50
90
142
165
227
427K
1M(2)
4M
4M
8M
200K
400K
700K
288K
360K
360K
576K
16
20
20
32
1,168K
1,842K
2,669K
4,644K
XC3S1400AN 1400K
16M
Notes:
1. By convention, one Kb is equivalent to 1,024 bits and one Mb is equivalent to 1,024 Kb.
2. Maximum supported by Xilinx tools. See the customer notice XCN14003: Flash Wafer Fabrication Change and Gold (Au) To Copper (Cu) Transition
for Spartan-3AN FPGA Devices.
© Copyright 2007–2014 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
DS557 (v4.2) June 12, 2014
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Product Specification
2
Spartan-3AN FPGA Family: Introduction and Ordering Information
Architectural Overview
The Spartan-3AN FPGA architecture is compatible with that
of the Spartan-3A FPGA. The architecture consists of five
fundamental programmable functional elements:
•
Digital Clock Manager (DCM) Blocks provide
self-calibrating, fully digital solutions for distributing,
delaying, multiplying, dividing, and phase-shifting clock
signals.
•
Configurable Logic Blocks (CLBs) contain flexible
Look-Up Tables (LUTs) that implement logic plus
storage elements used as flip-flops or latches.
These elements are organized as shown in Figure 1. A dual
ring of staggered IOBs surrounds a regular array of CLBs.
Each device has two columns of block RAM except for the
XC3S50AN, which has one column. Each RAM column
consists of several 18-Kbit RAM blocks. Each block RAM is
associated with a dedicated multiplier. The DCMs are
positioned in the center with two at the top and two at the
bottom of the device. The XC3S50AN has DCMs only at the
top, while the XC3S700AN and XC3S1400AN add two
DCMs in the middle of the two columns of block RAM and
multipliers.
•
Input/Output Blocks (IOBs) control the flow of data
between the I/O pins and the internal logic of the
device. IOBs support bidirectional data flow plus
3-state operation. They support a variety of signal
standards, including several high-performance
differential standards. Double Data-Rate (DDR)
registers are included.
•
•
Block RAM provides data storage in the form of
18-Kbit dual-port blocks.
The Spartan-3AN FPGA features a rich network of traces
that interconnect all five functional elements, transmitting
signals among them. Each functional element has an
associated switch matrix that permits multiple connections
to the routing.
Multiplier Blocks accept two 18-bit binary numbers as
inputs and calculate the product.
X-Ref Target - Figure 1
IOBs
CLB
DCM
IOBs
DCM
CLBs
DCM
IOBs
DS557-1_01_122006
Notes:
1. The XC3S700AN and XC3S1400AN have two additional DCMs on both the left and right sides as indicated by the
dashed lines. The XC3S50AN has only two DCMs at the top and only one Block RAM/Multiplier column.
Figure 1: Spartan-3AN Family Architecture
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Product Specification
3
Spartan-3AN FPGA Family: Introduction and Ordering Information
X-Ref Target - Figure 2
Spartan-3AN FPGA
‘0’
‘1’
‘1’
M2
M1
M0
VCCAUX
INIT_B
DONE
3.3V
Configure
from internal
flash memory
Indicates when
configuration is
finished
DS557-1_06_082810
Figure 2: Spartan-3AN FPGA Configuration Interface from Internal SPI Flash Memory
Configuration
In-System Flash Memory
Spartan-3AN FPGAs are programmed by loading
configuration data into robust, reprogrammable, static
CMOS configuration latches (CCLs) that collectively control
all functional elements and routing resources. The FPGA’s
configuration data is stored on-chip in nonvolatile Flash
memory, or externally in a PROM or some other nonvolatile
medium, either on or off the board. After applying power, the
configuration data is written to the FPGA using any of seven
different modes:
Each Spartan-3AN FPGA contains abundant integrated SPI
serial Flash memory, shown in Table 3, used primarily to
store the FPGA’s configuration bitstream. However, the
Flash memory array is large enough to store at least two
MultiBoot FPGA configuration bitstreams or nonvolatile
data required by the FPGA application, such as
code-shadowed MicroBlaze processor applications.
Table 3: Spartan-3AN Device In-System Flash Memory
Additional
•
Configure from internal SPI Flash memory (Figure 2)
Total Flash
Memory
(Bits)
FPGA
Bitstream
(Bits)
Flash
Memory
(Bits)(1)
Part Number
•
•
•
Completely self-contained
Reduced board space
Easy-to-use configuration interface
XC3S50AN
1,081,344(2)
4,325,376
4,325,376
8,650,752
17,301,504
437,312
1,196,128
1,886,560
2,732,640
4,755,296
642,048
3,127,872
2,437,248
5,917,824
12,545,280
XC3S200AN
XC3S400AN
XC3S700AN
XC3S1400AN
•
•
Master Serial from a Xilinx Platform Flash PROM
Serial Peripheral Interface (SPI) from an external
industry-standard SPI serial Flash
•
Byte Peripheral Interface (BPI) Up from an
industry-standard x8 or x8/x16 parallel NOR Flash
Notes:
•
•
•
Slave Serial, typically downloaded from a processor
Slave Parallel, typically downloaded from a processor
1. Aligned to next available page location.
2. Maximum supported by Xilinx tools.
Boundary-Scan (JTAG), typically downloaded from a
processor or system tester
After configuration, the FPGA design has full access to the
in-system Flash memory via an internal SPI interface; the
control logic is implemented with FPGA logic. Additionally,
the FPGA application itself can store nonvolatile data or
provide live, in-system Flash updates.
The MultiBoot feature stores multiple configuration files in
the on-chip Flash, providing extended life with field
upgrades. MultiBoot also supports multiple system
solutions with a single board to minimize inventory and
simplify the addition of new features, even in the field.
Flexibility is maintained to do additional MultiBoot
configurations via the external configuration method.
The Spartan-3AN device in-system Flash memory supports
leading-edge serial Flash features.
•
Small page size (264 or 528 bytes) simplifies
nonvolatile data storage
The Spartan-3AN device authentication protocol prevents
cloning. Design cloning, unauthorized overbuilding, and
complete reverse engineering have driven device security
requirements to higher and higher levels. Authentication
moves the security from bitstream protection to the next
generation of design-level security protecting both the
design and embedded microcode. The authentication
algorithm is entirely user defined, implemented using FPGA
logic. Every product, generation, or design can have a
different algorithm and functionality to enhance security.
•
•
•
Randomly accessible, byte addressable
Up to 66 MHz serial data transfers
SRAM page buffers
•
Read Flash data while programming another Flash
page
•
•
EEPROM-like byte write functionality
Two buffers in most devices, one in XC3S50AN
•
Page, Block, and Sector Erase
DS557 (v4.2) June 12, 2014
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Product Specification
4
Spartan-3AN FPGA Family: Introduction and Ordering Information
•
•
Sector-based data protection and security features
I/O Capabilities
•
Sector Protect: Write- and erase-protect a sector
(changeable)
The Spartan-3AN FPGA SelectIO interface supports many
popular single-ended and differential standards. Table 4
shows the number of user I/Os as well as the number of
differential I/O pairs available for each device/package
combination. Some of the user I/Os are unidirectional,
input-only pins as indicated in Table 4.
•
Sector Lockdown: Sector data is unchangeable
(permanent)
128-byte Security Register
•
•
•
Separate from FPGA’s unique Device DNA
identifier
64-byte factory-programmed identifier unique to
the in-system Flash memory
64-byte one-time programmable,
user-programmable field
Spartan-3AN FPGAs support the following single-ended
standards:
•
•
3.3V low-voltage TTL (LVTTL)
Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V,
1.5V, or 1.2V
•
•
•
100,000 Program/Erase cycles
20-year data retention
•
•
3.3V PCI at 33 MHz or 66 MHz
HSTL I, II, and III at 1.5V and 1.8V, commonly used in
memory applications
Comprehensive programming support
•
In-system prototype programming via JTAG using
Xilinx Platform Cable USB and iMPACT software
•
SSTL I and II at 1.8V, 2.5V, and 3.3V, commonly used
for memory applications
•
Product programming support using BPM
Microsystems programmers with appropriate
programming adapter
Spartan-3AN FPGAs support the following differential
standards:
•
Design examples demonstrating in-system
programming from a Spartan-3AN FPGA
application
•
LVDS, mini-LVDS, RSDS, and PPDS I/O at 2.5V or
3.3V
•
•
•
•
Bus LVDS I/O at 2.5V
TMDS I/O at 3.3V
Differential HSTL and SSTL I/O
LVPECL inputs at 2.5V or 3.3V
Table 4: Available User I/Os and Differential (Diff) I/O Pairs
TQ144
TQG144
FT256
FTG256
FG400
FGG400
FG484
FGG484
FG676
FGG676
Package(1)
Body Size (mm)
20 x 20(2)
17 x 17
21 x 21
23 x 23
27 x 27
Device(3)
User
Diff
User
Diff
User
Diff
User
Diff
User
Diff
108(4)
50
144(5)
64(5)
XC3S50AN
XC3S200AN
XC3S400AN
XC3S700AN
–
–
–
–
–
–
–
–
–
–
–
–
(7)
(24)
(32)
(32)
195
(35)
90
(50)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
195
(35)
90
(50)
311
(63)
142
(78)
372
(84)
165
(93)
–
–
–
–
–
–
–
–
375(5)
(87)
165(5)
(93)
502
(94)
227
(131)
XC3S1400AN
Notes:
1. See Pb and Pb-Free Packaging, page 7 for details on Pb and Pb-free packaging options.
2. The footprint for the TQ(G)144 (22 mm x 22 mm) package is larger than the package body.
3. Each Spartan-3AN FPGA has a pin-compatible Spartan-3A FPGA equivalent, although Spartan-3A FPGAs do not have internal SPI flash
and offer more part/package combinations.
4. The number shown in bold indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the number
of input-only pins. The differential (Diff) input-only pin count includes both differential pairs on input-only pins and differential pairs on I/O pins
within I/O banks that are restricted to differential inputs.
5. Xilinx has issued a discontinuation notice for these highlighted devices/packages. For more information see XCN13016: Product
Discontinuation Notice For Selected Spartan-3AN FPGA Products.
DS557 (v4.2) June 12, 2014
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Product Specification
5
Spartan-3AN FPGA Family: Introduction and Ordering Information
Package Marking
Figure 3 provides a top marking example for Spartan-3AN
FPGAs in the quad-flat packages. Figure 4 shows the top
marking for Spartan-3AN FPGAs in BGA packages. The
markings for the BGA packages are nearly identical to those
for the quad-flat packages, except that the marking is
rotated with respect to the ball A1 indicator.
The “5C” and “4I” Speed Grade/Temperature Range part
combinations may be dual marked as “5C/4I”. Devices
with the dual mark can be used as either -5C or -4I devices.
Devices with a single mark are only guaranteed for the
marked speed grade and temperature range.
X-Ref Target - Figure 3
Mask Revision Code
Fabrication Code
R
R
Process Technology
SPARTAN
XC3S50ANTM
Device Type
Date Code
Package
TQG144AGQ0725
D1234567A
Speed Grade
4C
Lot Code
Temperature Range
Pin P1
DS557-1_02_080107
Figure 3: Spartan-3AN FPGA QFP Package Marking Example
X-Ref Target - Figure 4
Mask Revision Code
R
BGA Ball A1
Fabrication Code
Process Code
R
SPARTAN
Device Type
XC3S200ANTM
FTG256 AGQ0725
D1234567A
Date Code
Lot Code
Package
4C
Speed Grade
Temperature Range
DS557-1_03_080107
Figure 4: Spartan-3AN FPGA BGA Package Marking Example
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Product Specification
6
Spartan-3AN FPGA Family: Introduction and Ordering Information
Pb and Pb-Free Packaging
Spartan-3AN FPGAs are available in both leaded (Pb) and Pb-free packaging options (see Table 5). The Pb-free packages
are available for all devices and include a ‘G’ character in the ordering code. Leaded (non-Pb-free) packages are available
for selected devices. The ordering code for the leaded devices does not have an extra ‘G’. Leaded and Pb-free devices have
the same pin-out.
Table 5: Pb and Pb-Free Package Options
Pins
Type
144
256
400
484
676
TQFP
FTBGA
FBGA
FBGA
FBGA
Material
Pb-Free
Pb
Pb-Free
Pb
Pb-Free
Pb
Pb-Free
Pb
Pb-Free
Pb
Device
Speed Range TQG144 TQ144 FTG256 FT256 FGG400 FG400 FGG484 FG484 FGG676 FG676
(1)
SCD4100
XC3S50AN
-4
-5
-4
-5
-4
-5
-4
-5
-4
-5
C, I
C
✔
✔
Note 3 Note 3
Note 3 Note 3
Note 2
XC3S200AN
XC3S400AN
XC3S700AN
XC3S1400AN
C, I
C
✔
✔
✔
✔
✔
✔
✔
✔
C, I
C
✔
✔
✔
Note 2
C, I
C
✔
✔
✔
Note 2
C, I
C
Note 3 Note 3
Note 3 Note 3
✔
✔
✔
Note 2
Notes:
1. To order a Pb package for the XC3S50AN -4 option, append SCD4100 to the part number (XC3S50AN-4TQ144C4100).
2. For Pb packaging for these options, contact your Xilinx sales representative.
3. Xilinx has issued a discontinuation notice for these highlighted devices/packages. For more information see XCN13016: Product
Discontinuation Notice For Selected Spartan-3AN FPGA Products.
DS557 (v4.2) June 12, 2014
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Product Specification
7
Spartan-3AN FPGA Family: Introduction and Ordering Information
Ordering Information
X-Ref Target - Figure 5
TQG144
Example: XC3S50AN -4
C
Device Type
Temperature Range:
C = Commercial (TJ = 0oC to 85oC)
I = Industrial (TJ = -40oC to 100oC)
Speed Grade
Package Type/Number of Pins
DS557-1_05_101109
Figure 5: Device Numbering Format
Device
XC3S50AN
Speed Grade
Package Type / Number of Pins
Temperature Range (TJ)
-4 Standard Performance TQ144/ 144-pin Thin Quad Flat Pack (TQFP)
TQG144
C Commercial (0°C to 85°C)
XC3S200AN -5 High Performance(1) FT256/ 256-ball Fine-Pitch Thin Ball Grid Array (FTBGA)
FTG256
I
Industrial (–40°C to 100°C)
XC3S400AN
XC3S700AN
XC3S1400AN
FG400/ 400-ball Fine-Pitch Ball Grid Array (FBGA)
FGG400
FG484/ 484-ball Fine-Pitch Ball Grid Array (FBGA)
FGG484
FG676/ 676-ball Fine-Pitch Ball Grid Array (FBGA)
FGG676
Notes:
1. The -5 speed grade is exclusively available in the Commercial temperature range.
2. See Table 4 and Table 5 for available package combinations.
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Product Specification
8
Spartan-3AN FPGA Family: Introduction and Ordering Information
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revision
02/26/2007
08/16/2007
09/12/2007
12/12/2007
Initial release.
2.0
Updated for Production release of initial device.
2.0.1
3.0
Noted that only dual-mark devices are guaranteed for both -4I and -5C.
Updated to Production status with Production release of final family member, XC3S50AN. Noted that
non-Pb-free packages may be available for selected devices.
06/02/2008
11/19/2009
3.1
3.2
Minor updates.
Updated document throughout to reflect availability of Pb package options. Added references to the
Extended Spartan-3A family. Removed table note 2 from Table 2. In Table 4, added Pb packages,
added table note 4, and updated table note 2. Added Table 5.
12/02/2010
04/01/2011
4.0
4.1
Updated Notice of Disclaimer.
In Table 2, revised the Maximum Differential I/O Pairs and Maximum User I/O values for the
XC3S50AN. In Table 4, added packages to the XC3S50AN, XC3S400AN, and XC3S1400AN. Updated
Pb and Pb-Free Packaging section and Table 5 to include the new device/package combinations for
the XC3S50AN, XC3S400AN, and XC3S1400AN.
06/11/2014
4.2
In Table 2, revised the XC3S50AN values in Maximum User I/O and Max Differential I/O Pairs columns,
and added Note 2 to the In-System Flash Bits column. In Table 3, added the same Note 2. Descriptions
of these changes and further links to the product changes are outlined in the customer notice
XCN14003: Flash Wafer Fabrication Change and Gold (Au) To Copper (Cu) Transition for Spartan-3AN
FPGA Devices.
Xilinx has issued a discontinuation notice for the XC3S50AN in the FT(G)256 package and the
XC3S1400AN in the FG(G)484 package. See XCN13016: Product Discontinuation Notice For
Selected Spartan-3AN FPGA Products. This customer notice is highlighted in Table 4 and Table 5.
Updated Notice of Disclaimer.
Notice of Disclaimer
The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the
maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL
WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
(whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related
to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special,
incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of
any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility
of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to
product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain
products are subject to the terms and conditions of Xilinx’s limited warranty, please refer to Xilinx’s Terms of Sale which can be viewed at
www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx
products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and
liability for use of Xilinx products in such critical applications, please refer to Xilinx’s Terms of Sale which can be viewed at
www.xilinx.com/legal.htm#tos.
AUTOMOTIVE APPLICATIONS DISCLAIMER
XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING
FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A
VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN
THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III)
USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY
USE OF XILINX PRODUCTS IN SUCH APPLICATIONS.
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9
11
Spartan-3AN FPGA Family:
Functional Description
DS557 (v4.2) June 12, 2014
Product Specification
Spartan-3AN FPGA Design Documentation
The functionality of the Spartan®-3AN FPGA family is
described in the following documents. The topics covered in
each guide are listed below:
•
UG333: Spartan-3AN FPGA In-System Flash User
Guide
•
For FPGA applications that write to or read from
the In-System Flash memory after configuration
•
•
DS706: Extended Spartan-3A Family Overview
UG331: Spartan-3 Generation FPGA User Guide
•
•
•
•
•
•
SPI_ACCESS interface
•
•
•
•
Clocking Resources
Digital Clock Managers (DCMs)
Block RAM
In-System Flash memory architecture
Read, program, and erase commands
Status registers
Configurable Logic Blocks (CLBs)
Sector Protection and Sector Lockdown features
Security Register with Unique Identifier
-
-
-
Distributed RAM
SRL16 Shift Registers
Carry and Arithmetic Logic
Create a Xilinx user account and sign up to receive
automatic e-mail notification whenever this data sheet or
the associated user guides are updated.
•
•
•
•
•
•
•
•
•
•
I/O Resources
Embedded Multiplier Blocks
Programmable Interconnect
ISE Design Tools
•
Sign Up for Alerts on Xilinx.com
https://secure.xilinx.com/webreg/register.do?group=my
profile&languageID=1
®
IP Cores
Embedded Processing and Control Solutions
Pin Types and Package Overview
Package Drawings
Powering FPGAs
Power Management
Spartan-3AN FPGA Starter Kit
For specific hardware examples, please see the
Spartan-3AN FPGA Starter Kit board web page, which has
links to various design examples and the user guide.
•
Spartan-3AN FPGA Starter Kit Board Page
http://www.xilinx.com/s3anstarter
•
UG332: Spartan-3 Generation Configuration
User Guide
•
UG334: Spartan-3AN FPGA Starter Kit User Guide
•
Configuration Overview
-
-
Configuration Pins and Behavior
Bitstream Sizes
•
Detailed Descriptions by Mode
-
Master Serial Mode using Xilinx® Platform
Flash
-
Master SPI Mode using SPI Serial Flash
PROM
-
-
-
-
-
Internal Master SPI Mode
Master BPI Mode using Parallel NOR Flash
Slave Parallel (SelectMAP) using a Processor
Slave Serial using a Processor
JTAG Mode
•
•
•
ISE iMPACT Programming Examples
MultiBoot Reconfiguration
Design Authentication using Device DNA
© Copyright 2007–2014 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
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Product Specification
10
Spartan-3AN FPGA Family: Functional Description
Related Product Families
The Spartan-3AN FPGA family is generally compatible with the Spartan-3A FPGA family.
•
DS529: Spartan-3A FPGA Family Data Sheet
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revision
02/26/2007
08/16/2007
09/12/2007
09/24/2007
12/12/2007
Initial release.
2.0
Updated for Production release of initial device.
2.0.1
2.1
Minor updates to text.
Added note that In-System Flash commands were not supported by simulation until ISE 10.1 software.
3.0
Updated to Production status with Production release of final family member, XC3S50AN. Noted that
SPI_ACCESS simulation is supported in ISE 10.1 software. Updated links.
06/02/2008
11/19/2009
3.1
3.2
Minor updates.
In the Spartan-3AN FPGA Design Documentation section, added link to DS706, Extended Spartan-3A
Family Overview and removed references to older software versions.
12/02/2010
04/01/2011
4.0
4.1
Updated link to sign up for Alerts and updated Notice of Disclaimer.
Added the FT(G)256 package selection for the XC3S50AN and XC3S400AN devices and the
FG(G)484 package selection for the XC3S1400AN device throughout this data sheet.
06/11/2014
4.2
Xilinx has issued a discontinuation notice for the XC3S50AN in the FT(G)256 package and the
XC3S1400AN in the FG(G)484 package. See XCN13016: Product Discontinuation Notice For
Selected Spartan-3AN FPGA Products. Updated Notice of Disclaimer.
Notice of Disclaimer
The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the
maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL
WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
(whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related
to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special,
incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of
any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility
of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to
product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain
products are subject to the terms and conditions of Xilinx’s limited warranty, please refer to Xilinx’s Terms of Sale which can be viewed at
www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx
products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and
liability for use of Xilinx products in such critical applications, please refer to Xilinx’s Terms of Sale which can be viewed at
www.xilinx.com/legal.htm#tos.
AUTOMOTIVE APPLICATIONS DISCLAIMER
XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING
FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A
VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN
THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III)
USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY
USE OF XILINX PRODUCTS IN SUCH APPLICATIONS.
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11
70
Spartan-3AN FPGA Family:
DC and Switching Characteristics
DS557 (v4.2) June 12, 2014
Product Specification
DC Electrical Characteristics
In this section, specifications can be designated as
Advance, Preliminary, or Production. These terms are
defined as follows:
All parameter limits are representative of worst-case supply
voltage and junction temperature conditions. Unless
otherwise noted, the published parameter values apply
to all Spartan®-3AN devices. AC and DC characteristics
are specified using the same numbers for both
commercial and industrial grades.
Advance: Initial estimates are based on simulation, early
characterization, and/or extrapolation from the
characteristics of other families. Values are subject to
change. Use as estimates, not for production.
Absolute Maximum Ratings
Preliminary: Based on characterization. Further changes
Stresses beyond those listed under Table 6: Absolute
Maximum Ratings might cause permanent damage to the
device. These are stress ratings only; functional operation
of the device at these or any other conditions beyond those
listed under the Recommended Operating Conditions is not
implied. Exposure to absolute maximum conditions for
extended periods of time adversely affects device reliability.
are not expected.
Production: These specifications are approved once the
silicon has been characterized over numerous production
lots. Parameter values are considered stable with no future
changes expected.
Table 6: Absolute Maximum Ratings
Symbol
Description
Internal supply voltage
Conditions
Min
–0.5
–0.5
–0.5
–0.5
–0.95
Max
1.32
Units
VCCINT
V
V
V
V
V
VCCAUX Auxiliary supply voltage
3.75
VCCO
VREF
Output driver supply voltage
Input reference voltage
3.75
VCCO +0.5
4.6
Voltage applied to all User I/O pins and
dual-purpose pins
Driver in a high-impedance state
VIN
Voltage applied to all Dedicated pins
Input clamp current per I/O pin
Electrostatic Discharge Voltage
–0.5
–
4.6
V
mA
V
IIK
–0.5V < VIN < (VCCO + 0.5V)(1)
Human body model
100
2000
500
200
125
150
–
VESD
Charged device model
Machine model
–
V
–
V
TJ
Junction temperature
Storage temperature
–
°C
°C
TSTG
–65
Notes:
1. Upper clamp applies only when using PCI IOSTANDARDs.
1. For soldering guidelines, see UG112: Device Package User Guide and XAPP427: Implementation and Solder Reflow Guidelines for Pb-Free
Packages.
© Copyright 2007–2014 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
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Product Specification
12
Spartan-3AN FPGA Family: DC and Switching Characteristics
Power Supply Specifications
Table 7: Supply Voltage Thresholds for Power-On Reset
Symbol
VCCINTT
VCCAUXT
VCCO2T
Description
Threshold for the VCCINT supply
Min
0.4
1.0
1.0
Max
1.0
Units
V
V
V
Threshold for the VCCAUX supply
2.0
Threshold for the VCCO Bank 2 supply
2.0
Notes:
1. When configuring from the In-System Flash, V
must be in the recommended operating range; on power-up make sure V
CCAUX
CCAUX
reaches at least 3.0V before INIT_B goes High to indicate the start of configuration. V
, V
, and V
supplies to the FPGA can
CCINT CCAUX
CCO
be applied in any order if this requirement is met. However, an external configuration source might have specific requirements. Check the
data sheet for the attached configuration source. Apply V last for lowest overall power consumption (see the chapter called “Powering
Spartan-3 Generation FPGAs” in UG331 for more information).
CCINT
2. To ensure successful power-on, V
no dips at any point.
, V
Bank 2, and V
supplies must rise through their respective threshold-voltage ranges with
CCAUX
CCINT CCO
Table 8: Supply Voltage Ramp Rate
Symbol
Description
Min
0.2
0.2
0.2
Max
100
100
100
Units
ms
VCCINTR
VCCAUXR
VCCO2R
Ramp rate from GND to valid VCCINT supply level
Ramp rate from GND to valid VCCAUX supply level
Ramp rate from GND to valid VCCO Bank 2 supply level
ms
ms
Notes:
1. When configuring from the In-System Flash, V
must be in the recommended operating range; on power-up make sure V
CCAUX
CCAUX
reaches at least 3.0V before INIT_B goes High to indicate the start of configuration. V
, V
, and V
supplies to the FPGA can
CCINT CCAUX
CCO
be applied in any order if this requirement is met. However, an external configuration source might have specific requirements. Check the
data sheet for the attached configuration source. Apply V last for lowest overall power consumption (see the chapter called “Powering
Spartan-3 Generation FPGAs” in UG331 for more information).
CCINT
2. To ensure successful power-on, V
no dips at any point.
, V
Bank 2, and V
supplies must rise through their respective threshold-voltage ranges with
CCINT CCO
CCAUX
Table 9: Supply Voltage Levels Necessary for Preserving CMOS Configuration Latch (CCL) Contents and RAM Data
Symbol
VDRINT
VDRAUX
Description
Min
1.0
2.0
Units
VCCINT level required to retain CMOS Configuration Latch (CCL) and RAM data
VCCAUX level required to retain CMOS Configuration Latch (CCL) and RAM data
V
V
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13
Spartan-3AN FPGA Family: DC and Switching Characteristics
General Recommended Operating Conditions
Table 10: General Recommended Operating Conditions
Symbol
Description
Commercial
Industrial
Min
0
Nominal
Max
85
Units
°C
°C
V
TJ
Junction temperature
–
–
–40
1.14
1.10
3.00
–0.5
–0.5
–0.5
–
100
VCCINT
Internal supply voltage
Output driver supply voltage
Auxiliary supply voltage
Input voltage
1.20
–
1.26
(1)
VCCO
3.60
V
VCCAUX
VCCAUX = 3.3V
3.30
–
3.60
V
(2)
VIN
PCI IOSTANDARD
VCCO + 0.5
4.10
V
All other
IOSTANDARDs
IP or IO_#
–
V
IO_Lxxy_#(3)
–
4.10
V
TIN
Input signal transition time(4)
–
500
ns
Notes:
1. This V
range spans the lowest and highest operating voltages for all supported I/O standards. Table 13 lists the recommended V
CCO
CCO
range specific to each of the single-ended I/O standards, and Table 15 lists that specific to the differential standards.
2. See XAPP459, Eliminating I/O Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins on Spartan-3 Families.
3. For single-ended signals that are placed on a differential-capable I/O, V of –0.2V to –0.5V is supported but can cause increased leakage
IN
between the two pins. See Parasitic Leakage in UG331, Spartan-3 Generation FPGA User Guide.
4. Measured between 10% and 90% V
. Follow Signal Integrity recommendations.
CCO
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Product Specification
14
Spartan-3AN FPGA Family: DC and Switching Characteristics
General DC Characteristics for I/O Pins
Table 11: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins
Symbol
Description
Test Conditions
Min
Typ
Max Units
(2)
IL
Leakage current at User I/O,
Input-only, Dual-Purpose, and
Dedicated pins, FPGA powered
Driver is in a high-impedance state,
–10
–
+10
µA
VIN = 0V or VCCO max, sample-tested
IHS
Leakage current on pins during
hot socketing, FPGA unpowered pins when PUDC_B = 1.
All pins except INIT_B, PROG_B, DONE, and JTAG
–10
–
+10
µA
µA
µA
INIT_B, PROG_B, DONE, and JTAG pins or other
Add IHS + IRPU
pins when PUDC_B = 0.
VIN = GND
(3)
IRPU
Current through pull-up resistor
at User I/O, Dual-Purpose,
VCCO or VCCAUX
3.0V to 3.6V
=
–151
–315
–710
Input-only, and Dedicated pins.
VCCO = 2.3V to 2.7V
VCCO = 1.7V to 1.9V
VCCO = 1.4V to 1.6V
–82
–36
–22
–11
5.1
–182
–88
–437
–226
–148
–83
µA
µA
µA
µA
kΩ
kΩ
kΩ
kΩ
kΩ
µA
Dedicated pins are powered by
(4)
VCCAUX
.
–56
V
CCO = 1.14V to 1.26V
VCCO = 3.0V to 3.6V
VCCO = 2.3V to 2.7V
–31
(3)
RPU
Equivalent pull-up resistor value
at User I/O, Dual-Purpose,
Input-only, and Dedicated pins
(based on IRPU per Note 3)
VIN = GND
11.4
14.8
21.6
28.4
41.1
346
23.9
33.1
52.6
74.0
119.4
659
6.2
V
CCO = 1.7V to 1.9V
CCO = 1.4V to 1.6V
8.4
V
10.8
15.3
167
VCCO = 1.14V to 1.26V
VCCAUX = 3.0V to 3.6V
(3)
IRPD
Current through pull-down
resistor at User I/O,
VIN = VCCO
Dual-Purpose, Input-only, and
Dedicated pins
(3)
RPD
Equivalent pull-down resistor
value at User I/O, Dual-Purpose,
Input-only, and Dedicated pins
(based on IRPD per Note 3)
VCCAUX = 3.0V to 3.6V
VIN = 3.0V to 3.6V
VIN = 2.3V to 2.7V
5.5
4.1
3.0
2.7
2.4
–10
–
10.4
7.8
5.7
5.1
4.5
–
20.8
15.7
11.1
9.6
kΩ
kΩ
kΩ
kΩ
kΩ
µA
pF
Ω
V
IN = 1.7V to 1.9V
IN = 1.4V to 1.6V
V
VIN = 1.14V to 1.26V
All VCCO levels
8.1
IREF
CIN
VREF current per pin
Input capacitance
+10
10
–
–
RDT
Resistance of optional differential
termination circuit within a
differential I/O pair. Not available
on Input-only pairs.
VCCO = 3.3V 10%
LVDS_33,
MINI_LVDS_33,
RSDS_33
90
100
115
VCCO = 2.5V 10%
LVDS_25,
MINI_LVDS_25,
RSDS_25
90
110
–
Ω
Notes:
1. The numbers in this table are based on the conditions set forth in Table 10.
2. For single-ended signals that are placed on a differential-capable I/O, V of –0.2V to –0.5V is supported but can cause increased leakage
IN
between the two pins. See Parasitic Leakage in UG331, Spartan-3 Generation FPGA User Guide.
3. This parameter is based on characterization. The pull-up resistance R = V
/ I
. The pull-down resistance R = V / I
.
PU
CCO RPU
PD
IN RPD
4.
V
must be 3.3V on Spartan-3AN FPGAs. V
for Spartan-3A FPGAs can be either 3.3V or 2.5V.
CCAUX
CCAUX
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15
Spartan-3AN FPGA Family: DC and Switching Characteristics
Quiescent Current Requirements
Table 12: Spartan-3AN FPGA Quiescent Supply Current Characteristics
Commercial
Maximum(2)
Industrial
Symbol
Description
Device
Typical(2)
Units
Maximum(2)
ICCINTQ
Quiescent VCCINT supply current
XC3S50AN
2
7
20
50
30
70
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
XC3S200AN
XC3S400AN
XC3S700AN
XC3S1400AN
XC3S50AN
10
85
125
185
310
3
13
120
220
2
24
ICCOQ
Quiescent VCCO supply current
0.2
0.2
0.3
0.3
0.3
3.1
5.1
5.1
6.1
10.1
XC3S200AN
XC3S400AN
XC3S700AN
XC3S1400AN
XC3S50AN
2
3
3
4
3
4
3
4
ICCAUXQ
Quiescent VCCAUX supply current
8.1
12.1
18.1
28.1
50.1
10.1
15.1
24.1
34.1
58.1
XC3S200AN
XC3S400AN
XC3S700AN
XC3S1400AN
Notes:
1. The numbers in this table are based on the conditions set forth in Table 10.
2. Quiescent supply current is measured with all I/O drivers in a high-impedance state and with all pull-up/pull-down resistors at the I/O pads
disabled. The internal SPI Flash is deselected (CSB = High); the internal SPI Flash current is consumed on the V supply rail. Typical
CCAUX
values are characterized using typical devices at room temperature (T of 25°C at V
= 1.2V, V
= 3.3V, and V
= 3.3V). The
J
CCINT
CCO
CCAUX
maximum limits are tested for each device at the respective maximum specified junction temperature and at maximum voltage limits with
= 1.26V, V = 3.6V, and V = 3.6V. The FPGA is programmed with a “blank” configuration data file (that is, a design with no
V
CCINT
CCO
CCAUX
functional elements instantiated). For conditions other than those described above (for example, a design including functional elements),
measured quiescent current levels will be different than the values in the table.
3. There are two recommended ways to estimate the total power consumption (quiescent plus dynamic) for a specific design:
•
•
The Spartan-3AN FPGA Xilinx Power Estimator provides quick, approximate, typical estimates, and does not require a netlist of the design.
Xilinx Power Analyzer uses a netlist as input to provide maximum estimates as well as more accurate typical estimates. For more
information on power for the In-System Flash memory, see the Power Management chapter of UG333.
4. The maximum numbers in this table indicate the minimum current each power rail requires in order for the FPGA to power-on successfully.
5. For information on the power-saving Suspend mode, see XAPP480: Using Suspend Mode in Spartan-3 Generation FPGAs. Suspend mode
typically saves 40% total power consumption compared to quiescent current.
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16
Spartan-3AN FPGA Family: DC and Switching Characteristics
Single-Ended I/O Standards
Table 13: Recommended Operating Conditions for User I/Os Using Single-Ended Standards
(3)
VCCO for Drivers(2)
VREF
VIL
Max (V)
0.8
VIH
IOSTANDARD
Attribute
Min (V) Max (V)
Nom (V)
3.3
3.3
2.5
1.8
1.5
1.2
3.3
3.3
1.5
1.5
1.8
1.8
1.8
1.8
1.8
2.5
2.5
3.3
3.3
Min (V)
Nom (V)
Max (V)
Min (V)
2.0
LVTTL
3.0
3.0
2.3
1.65
1.4
1.1
3.0
3.0
1.4
1.4
1.7
1.7
1.7
1.7
1.7
2.3
2.3
3.0
3.0
3.6
3.6
2.7
1.95
1.6
1.3
3.6
3.6
1.6
1.6
1.9
1.9
1.9
1.9
1.9
2.7
2.7
3.6
3.6
LVCMOS33(4)
LVCMOS25(4)(5)
LVCMOS18
LVCMOS15
LVCMOS12
PCI33_3(6)
PCI66_3(6)
HSTL_I
0.8
2.0
0.7
1.7
0.4
0.8
VREF is not used for
these I/O standards
0.4
0.8
0.4
0.7
0.3 • VCCO
0.3 • VCCO
VREF – 0.1
0.5 • VCCO
0.5 • VCCO
VREF + 0.1
VREF + 0.1
VREF + 0.1
VREF + 0.1
VREF + 0.1
VREF + 0.125
VREF + 0.125
VREF + 0.150
VREF + 0.150
VREF + 0.2
VREF + 0.2
0.68
–
0.75
0.9
0.9
–
HSTL_III
VREF – 0.1
VREF – 0.1
VREF – 0.1
VREF – 0.1
HSTL_I_18
HSTL_II_18
HSTL_III_18
SSTL18_I
SSTL18_II
SSTL2_I
0.8
0.9
1.1
–
–
0.9
–
1.1
–
0.833
0.833
1.13
1.13
1.3
0.900
0.900
1.25
1.25
1.5
0.969
0.969
1.38
1.38
1.7
1.7
VREF – 0.125
V
V
REF – 0.125
REF – 0.150
SSTL2_II
VREF – 0.150
SSTL3_I
V
REF – 0.2
REF – 0.2
SSTL3_II
1.3
1.5
V
Notes:
1. Descriptions of the symbols used in this table are as follows:
V
V
V
V
– the supply voltage for output drivers
– the reference voltage for setting the input switching threshold
– the input voltage that indicates a Low logic level
– the input voltage that indicates a High logic level
CCO
REF
IL
IH
2. In general, the V
rails supply only output drivers, not input circuits. The exceptions are for LVCMOS25 inputs and for PCI™ I/O standards.
CCO
3. For device operation, the maximum signal voltage (V max) can be as high as V max. See Table 6.
IH
IN
4. There is approximately 100 mV of hysteresis on inputs using LVCMOS33 and LVCMOS25 I/O standards.
5. All Dedicated pins (PROG_B, DONE, SUSPEND, TCK, TDI, TDO, and TMS) draw power from the V
rail and use the LVCMOS33
CCAUX
standard. The Dual-Purpose configuration pins use the LVCMOS standard before the User mode. When using these pins as part of a
standard 2.5V configuration interface, apply 2.5V to the V lines of Banks 0, 1, and 2 at power-on as well as throughout configuration.
CCO
6. For information on PCI IP solutions, see www.xilinx.com/pci. The PCI IOSTANDARD is not supported on input-only pins. The PCIX
IOSTANDARD is available and has equivalent characteristics but no PCI-X IP is supported.
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Product Specification
17
Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 14: DC Characteristics of User I/Os Using
Single-Ended Standards (Cont’d)
Table 14: DC Characteristics of User I/Os Using
Single-Ended Standards
Test
Logic Level
Test
Logic Level
Conditions
Characteristics
Conditions
Characteristics
IOSTANDARD
Attribute
IOSTANDARD
Attribute
IOL
IOH
VOL
VOH
Min (V)
IOL
IOH
VOL
VOH
Min (V)
(mA) (mA)
Max (V)
(mA) (mA)
Max (V)
HSTL_I(5)
8
24
8
–8
–8
0.4
0.4
0.4
0.4
0.4
VCCO - 0.4
VCCO - 0.4
VCCO - 0.4
VCCO - 0.4
VCCO - 0.4
LVTTL(3)
2
4
6
8
2
4
–2
–4
0.4
0.4
0.4
0.4
2.4
HSTL_III(5)
HSTL_I_18
HSTL_II_18(5)
HSTL_III_18
SSTL18_I
–8
6
–6
16
24
6.7
–16
–8
8
–8
12
16
24
2
12
16
24
2
–12
–16
–24
–2
VTT – 0.475 VTT + 0.475
VTT – 0.603 VTT + 0.603
–6.7
SSTL18_II(5)
SSTL2_I
13.4 –13.4
8.1 –8.1
16.2 –16.2 VTT – 0.81
LVCMOS33(3)
LVCMOS25(3)
LVCMOS18(3)
VCCO – 0.4
VCCO – 0.4
VCCO – 0.4
V
TT – 0.61
VTT + 0.61
VTT + 0.81
VTT + 0.6
VTT + 0.8
SSTL2_II(5)
SSTL3_I
4
4
–4
8
–8
V
TT – 0.6
6
6
–6
SSTL3_II
16
–16
VTT – 0.8
8
8
–8
12
16
24(5)
2
12
16
24
2
–12
–16
–24
–2
Notes:
1. The numbers in this table are based on the conditions set forth in
Table 10 and Table 13.
2. Descriptions of the symbols used in this table are as follows:
IOL – the output current condition under which VOL is tested
IOH – the output current condition under which VOH is tested
VOL – the output voltage that indicates a Low logic level
VOH – the output voltage that indicates a High logic level
VCCO – the supply voltage for output drivers
4
4
–4
6
6
–6
VTT – the voltage applied to a resistor termination
8
8
–8
3. For the LVCMOS and LVTTL standards: the same V and V
OL
OH
limits apply for the Fast, Slow and QUIETIO slew attributes.
4. Tested according to the relevant PCI specifications. For
12
16(5)
24(5)
2
12
16
24
2
–12
–16
–24
–2
information on PCI IP solutions, see www.xilinx.com/products/
design_resources/conn_central/protocols/pci_pcix.htm. The
PCIX IOSTANDARD is available and has equivalent
characteristics but no PCI-X IP is supported.
5. These higher-drive output standards are supported only on
FPGA banks 1 and 3. Inputs are unrestricted. See the chapter
“Using I/O Resources” in UG331.
4
4
–4
6
6
–6
8
8
–8
12(5)
16(5)
2
12
16
2
–12
–16
–2
LVCMOS15(3)
0.4
0.4
VCCO – 0.4
4
4
–4
6
6
–6
8(5)
12(5)
2
8
–8
12
2
–12
–2
LVCMOS12(3)
VCCO – 0.4
4(5)
6(5)
4
–4
6
–6
PCI33_3(4)
PCI66_3(4)
1.5
1.5
–0.5 10% VCCO
–0.5 10% VCCO
90% VCCO
90% VCCO
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18
Spartan-3AN FPGA Family: DC and Switching Characteristics
Differential I/O Standards
Differential Input Pairs
X-Ref Target - Figure 6
VINP
Differential
I/O Pair Pins
P
N
Internal
Logic
VINN
VINN
V
50%
ID
VINP
V
ICM
GND level
V
INP + VINN
V
ICM = Input common mode voltage =
2
INP - VINN
Figure 6: Differential Input Voltages
V
V
ID = Differential input voltage =
DS529-3_10_012907
Table 15: Recommended Operating Conditions for User I/Os Using Differential Signal Standards
(2)
VCCO for Drivers(1)
VID
Max (V) Min (mV) Nom (mV) Max (mV) Min (V)
VICM
IOSTANDARD Attribute
Min (V)
2.25
3.0
Nom (V)
2.5
Nom (V)
1.25
1.25
1.3
1.2
1.2
1.2
1.2
1.2
1.2
–
Max (V)
2.35
2.35
2.35
1.95
1.95
1.95
2.8(6)
1.5
LVDS_25(3)
2.75
3.6
100
100
100
200
200
100
100
100
100
150
100
100
100
100
100
100
100
100
100
100
100
100
350
350
300
–
600
600
–
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
2.7
0.2
0.2
0.8
0.8
0.8
0.68
–
LVDS_33(3)
3.3
BLVDS_25(4)
2.25
2.25
3.0
2.5
2.75
2.75
3.6
MINI_LVDS_25(3)
MINI_LVDS_33(3)
LVPECL_25(5)
2.5
600
600
1000
1000
–
3.3
–
Inputs Only
Inputs Only
2.5
800
800
200
200
–
LVPECL_33(5)
RSDS_25(3)
2.25
3.0
3.14
2.25
3.0
1.7
1.7
1.7
1.4
1.4
1.7
1.7
2.3
2.3
3.0
2.75
3.6
3.47
2.75
3.6
1.9
1.9
1.9
1.6
1.6
1.9
1.9
2.7
2.7
3.6
RSDS_33(3)
3.3
–
1.5
TMDS_33(3,4,7)
PPDS_25(3)
3.3
1200
400
400
–
3.23
2.3
2.5
–
–
PPDS_33(3)
3.3
–
–
2.3
DIFF_HSTL_I_18(8)
DIFF_HSTL_II_18(8,9)
DIFF_HSTL_III_18(8)
DIFF_HSTL_I(8)
DIFF_HSTL_III(8)
DIFF_SSTL18_I(8)
DIFF_SSTL18_II(8,9)
DIFF_SSTL2_I(8)
DIFF_SSTL2_II(8,9)
DIFF_SSTL3_I(8)
1.8
–
–
1.1
1.8
–
–
–
1.1
1.8
–
–
–
1.1
1.5
–
–
0.9
1.5
–
–
0.9
–
–
1.8
–
–
0.7
0.7
1.0
1.0
1.1
1.1
1.8
–
–
–
1.1
2.5
–
–
–
1.5
2.5
–
–
–
1.5
3.3
–
–
–
1.9
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Product Specification
19
Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 15: Recommended Operating Conditions for User I/Os Using Differential Signal Standards (Cont’d)
(2)
VCCO for Drivers(1)
VID
Max (V) Min (mV) Nom (mV) Max (mV) Min (V)
3.6 100 1.1
VICM
Nom (V)
–
IOSTANDARD Attribute
Min (V)
Nom (V)
Max (V)
DIFF_SSTL3_II(8)
3.0
3.3
–
–
1.9
Notes:
1. The V
rails supply only differential output drivers, not input circuits.
CCO
2.
V
must be less than V
.
ICM
CCAUX
3. These true differential output standards are supported only on FPGA banks 0 and 2. Inputs are unrestricted. See the “Using I/O Resources”
chapter in UG331.
4. See External Termination Requirements for Differential I/O, page 22.
5. LVPECL is supported on inputs only, not outputs. Requires V
= 3.3V 10%.
CCAUX
6. LVPECL_33 maximum V
= V
– (V / 2)
ICM
CCAUX ID
7. Requires V
= 3.3V 10% for inputs. (V
– 300 mV) ≤ V
≤ (V
– 37 mV)
CCAUX
CCAUX
CCAUX
ICM
8.
V
inputs are used for the DIFF_SSTL and DIFF_HSTL standards. The V
settings are the same as for the single-ended versions in
REF
REF
Table 13. Other differential standards do not use V
.
REF
9. These higher-drive output standards are supported only on FPGA banks 1 and 3. Inputs are unrestricted. See the “Using I/O Resources”
chapter in UG331.
Differential Output Pairs
X-Ref Target - Figure 7
VOUTP
VOUTN
Differential
I/O Pair Pins
P
N
Internal
Logic
VOH
VOUTN
VOD
50%
VOUTP
VOL
VOCM
GND level
V
OUTP + VOUTN
V
OCM = Output common mode voltage =
2
V
OUTP - VOUTN
V
OD = Output differential voltage =
VOH
VOL
= Output voltage indicating a High logic level
= Output voltage indicating a Low logic level
DS529-3_11_082810
Figure 7: Differential Output Voltages
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Product Specification
20
Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 16: DC Characteristics of User I/Os Using Differential Signal Standards
VOD
VOCM
VOH
VOL
IOSTANDARD Attribute
Min (mV) Typ (mV) Max (mV)
Min (V)
Typ (V)
Max (V)
Min (V)
Max (V)
LVDS_25
247
247
240
300
300
100
100
400
100
100
–
350
350
350
–
454
454
460
600
600
400
400
800
400
400
–
1.125
–
–
1.375
–
–
–
LVDS_33
1.125
1.375
–
BLVDS_25
–
1.30
–
–
–
–
MINI_LVDS_25
MINI_LVDS_33
RSDS_25
1.0
1.4
–
–
–
1.0
–
1.4
–
–
–
1.0
–
1.4
–
–
RSDS_33
–
1.0
–
1.4
–
–
TMDS_33
–
VCCO – 0.405
–
VCCO – 0.190
–
–
PPDS_25
–
0.5
0.5
–
0.8
0.8
–
1.4
1.4
–
–
–
PPDS_33
–
–
–
DIFF_HSTL_I_18
DIFF_HSTL_II_18
DIFF_HSTL_III_18
DIFF_HSTL_I
DIFF_HSTL_III
DIFF_SSTL18_I
DIFF_SSTL18_II
DIFF_SSTL2_I
DIFF_SSTL2_II
DIFF_SSTL3_I
DIFF_SSTL3_II
–
VCCO – 0.4
VCCO – 0.4
VCCO – 0.4
VCCO – 0.4
VCCO – 0.4
0.4
0.4
0.4
0.4
0.4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
VTT + 0.475 VTT – 0.475
VTT + 0.475 VTT – 0.475
–
–
–
–
–
–
–
–
–
–
–
–
VTT + 0.61
VTT + 0.81
VTT + 0.6
VTT + 0.8
VTT – 0.61
VTT – 0.81
VTT – 0.6
VTT – 0.8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Notes:
1. The numbers in this table are based on the conditions set forth in Table 10 and Table 15.
2. See External Termination Requirements for Differential I/O, page 22.
3. Output voltage measurements for all differential standards are made with a termination resistor (R ) of 100Ω across the N and P pins of the
T
differential signal pair.
4. At any given time, no more than two of the following differential output standards can be assigned to an I/O bank: LVDS_25, RSDS_25,
MINI_LVDS_25, PPDS_25 when V
=2.5V, or LVDS_33, RSDS_33, MINI_LVDS_33, TMDS_33, PPDS_33 when V
= 3.3V
CCO
CCO
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Product Specification
21
Spartan-3AN FPGA Family: DC and Switching Characteristics
External Termination Requirements for Differential I/O
LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards
X-Ref Target - Figure 8
Bank 0 and 2
Any Bank
Bank 0
Bank 0
No VCCO Restrictions
LVDS_33, LVDS_25,
MINI_LVDS_33,
MINI_LVDS_25,
1/4th of Bourns
Part Number
CAT16-PT4F4
Bank 2
Bank 2
Z
Z
= 50Ω
= 50Ω
0
0
RSDS_33, RSDS_25,
PPDS_33, PPDS_25
VCCO = 3.3V VCCO = 2.5V
LVDS_33,
LVDS_25,
100Ω
MINI_LVDS_33,
RSDS_33,
PPDS_33
MINI_LVDS_25,
RSDS_25,
PPDS_25
DIFF_TERM=No
a) Input-only Differential Pairs or Pairs not Using DIFF_TERM=Yes Constraint
VCCO = 3.3V VCCO = 2.5V
Z
= 50Ω
0
LVDS_33,
LVDS_25,
MINI_LVDS_33,
RSDS_33,
PPDS_33
MINI_LVDS_25,
RSDS_25,
PPDS_25
VCCO = 3.3V VCCO = 2.5V
LVDS_33,
LVDS_25,
RDT
MINI_LVDS_33,
RSDS_33,
PPDS_33
MINI_LVDS_25,
RSDS_25,
PPDS_25
Z
= 50Ω
0
DIFF_TERM=Yes
b) Differential Pairs Using DIFF_TERM=Yes Constraint
DS529-3_09_080307
Figure 8: External Input Termination for LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards
BLVDS_25 I/O Standard
X-Ref Target - Figure 9
Any Bank
Bank 0
Any Bank
Bank 0
1/4th of Bourns
Part Number
CAT16-LV4F12
1/4th of Bourns
Part Number
CAT16-PT4F4
Bank 2
Bank 2
Z
Z
= 50Ω
= 50Ω
VCCO = 2.5V
0
No VCCO Requirement
165Ω
140Ω
100Ω BLVDS_25
BLVDS_25
0
165Ω
DS529-3_07_080307
Figure 9: External Output and Input Termination Resistors for BLVDS_25 I/O Standard
TMDS_33 I/O Standard
X-Ref Target - Figure 10
Any Bank
Bank 0
Bank 0 and 2
Bank 0
3.3V
Bank 2
Bank 2
50Ω
50Ω
VCCAUX = 3.3V
VCCO = 3.3V
TMDS_33
TMDS_33
DVI/HDMI cable
DS529-3_08_020107
Figure 10: External Input Resistors Required for TMDS_33 I/O Standard
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Product Specification
22
Spartan-3AN FPGA Family: DC and Switching Characteristics
Device DNA Read Endurance
Table 17: Device DNA Identifier Memory Characteristics
Symbol
Description
Minimum
Units
Number of READ operations or JTAG ISC_DNA read operations. Unaffected by
HOLD or SHIFT operations
Read
cycles
DNA_CYCLES
30,000,000
In-System Flash Memory Data Retention, Program/Write Endurance
Table 18: In-System Flash (ISF) Memory Characteristics
Symbol
Description
Minimum(1)
Units
ISF_RETENTION
Data retention
20
Years
Time that the ISF memory is selected and active. SPI_ACCESS design primitive
pins CSB = Low, CLK toggling
ISF_ACTIVE
2
Years
Cycles
Cycles
Cycles
Cycle
ISF_PAGE_CYCLES Number of program/erase cycles, per ISF memory page
100,000
10,000
10,000
1
Number of cumulative random (non-sequential) page erase/program operations
within a sector before pages must be rewritten
ISF_PAGE_REWRITE
ISF_SPR_CYCLES
ISF_SEC_CYCLES
Number of program/erase cycles for Sector Protection Register
Number of program cycles for Sector Lockdown Register per sector,
user-programmable field in Security Register, and Power-of-2 Page Size
Notes:
1. Minimum value at which functionality is still guaranteed. Do not exceed these values.
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Product Specification
23
Spartan-3AN FPGA Family: DC and Switching Characteristics
Switching Characteristics
All Spartan-3AN FPGAs ship in two speed grades: -4 and
the higher performance -5. Switching characteristics in this
document are designated as Preview, Advance,
Preliminary, or Production, as shown in Table 19. Each
category is defined as follows:
Create a Xilinx user account and sign up to receive
automatic e-mail notification whenever this data sheet or
the associated user guides are updated.
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le&languageID=1
Preview: These specifications are based on estimates only
and should not be used for timing analysis.
Timing parameters and their representative values are
selected for inclusion either because they are important as
general design requirements or they indicate fundamental
device performance characteristics. The Spartan-3AN
speed files (v1.41), part of the Xilinx Development Software,
are the original source for many but not all of the values.
The speed grade designations for these files are shown in
Table 19. For more complete, more precise, and worst-case
data, use the values reported by the Xilinx static timing
analyzer (TRACE in the Xilinx development software) and
back-annotated to the simulation netlist.
Advance: These specifications are based on simulations
only and are typically available soon after establishing
FPGA specifications. Although speed grades with this
designation are considered relatively stable and
conservative, some under-reporting might still occur.
Preliminary: These specifications are based on complete
early silicon characterization. Devices and speed grades
with this designation are intended to give a better indication
of the expected performance of production silicon. The
probability of under-reporting preliminary delays is greatly
reduced compared to Advance data.
Table 19: Spartan-3AN Family v1.41 Speed Grade
Designations
Production: These specifications are approved once
enough production silicon of a particular device family
member has been characterized to provide full correlation
between speed files and devices over numerous production
lots. There is no under-reporting of delays, and customers
receive formal notification of any subsequent changes.
Typically, the slowest speed grades transition to Production
before faster speed grades.
Device
Preview
Advance Preliminary
Production
-4, -5
XC3S50AN
XC3S200AN
XC3S400AN
XC3S700AN
XC3S1400AN
-4, -5
-4, -5
-4, -5
Software Version Requirements
-4, -5
Production-quality systems must use FPGA designs
compiled using a speed file designated as PRODUCTION
status. FPGA designs using a less mature speed file
designation should only be used during system prototyping
or pre-production qualification. FPGA designs with speed
files designated as Preview, Advance, or Preliminary should
not be used in a production-quality system.
Table 20 provides the recent history of the Spartan-3AN
speed files.
Table 20: Spartan-3AN Speed File Version History
ISE
Version
1.41
Description
Release
Updated for Spartan-3A family. No
change to data for Spartan-3AN family.
ISE 10.1.03
Whenever a speed file designation changes, as a device
matures toward Production status, rerun the latest Xilinx®
ISE® software on the FPGA design to ensure that the
FPGA design incorporates the latest timing information and
software updates.
Updated for Spartan-3A family. No
change to data for Spartan-3AN family.
1.40
ISE 10.1.02
ISE 10.1
Updated for Spartan-3A family. No
change to data for Spartan-3AN family.
1.39
In some cases, a particular family member (and speed
grade) is released to Production at a different time than
when the speed file is released with the Production label.
Any labeling discrepancies are corrected in subsequent
speed file releases. See Table 19 for devices that can be
considered to have the Production label.
Updated to Production. No change to
data.
1.38
ISE 9.2.03i
Updated pin-to-pin setup and hold
times, TMDS output adjustment,
multiplier setup/hold times, and block
RAM clock width.
1.37
1.36
ISE 9.2.01i
ISE 9.2i
Added -5 speed grade, updated to
Advance.
All parameter limits are representative of worst-case supply
voltage and junction temperature conditions. Unless
otherwise noted, the published parameter values apply
to all Spartan-3AN devices. AC and DC characteristics
are specified using the same numbers for both
commercial and industrial grades.
1.34
1.32
ISE 9.1.03i Updated pin-to-pin timing.
ISE 9.1.01i Preview speed files for -4 speed grade.
DS557 (v4.2) June 12, 2014
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Product Specification
24
Spartan-3AN FPGA Family: DC and Switching Characteristics
I/O Timing
Pin-to-Pin Clock-to-Output Times
Table 21: Pin-to-Pin Clock-to-Output Times for the IOB Output Path
Speed Grade
Symbol
Description
Conditions
Device
-5
-4
Units
Max
Max
Clock-to-Output Times
TICKOFDCM
When reading from the Output
Flip-Flop (OFF), the time from the output drive, Fast slew
active transition on the Global
Clock pin to data appearing at the
Output pin. The DCM is in use.
LVCMOS25(2), 12 mA
XC3S50AN
3.18
3.21
2.97
3.39
3.51
4.59
4.88
4.68
4.97
5.06
3.42
3.27
3.33
3.50
3.99
5.02
5.24
5.12
5.34
5.69
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XC3S200AN
XC3S400AN
XC3S700AN
XC3S1400AN
XC3S50AN
rate, with DCM(3)
TICKOF
When reading from OFF, the time LVCMOS25(2), 12 mA
from the active transition on the output drive, Fast slew
Global Clock pin to data appearing rate, without DCM
at the Output pin. The DCM is not
in use.
XC3S200AN
XC3S400AN
XC3S700AN
XC3S1400AN
Notes:
1. The numbers in this table are tested using the methodology presented in Table 30 and are based on the operating conditions set forth in
Table 10 and Table 13.
2. This clock-to-output time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or a
standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. If the former is true, add the appropriate
Input adjustment from Table 26. If the latter is true, add the appropriate Output adjustment from Table 29.
3. DCM output jitter is included in all measurements.
DS557 (v4.2) June 12, 2014
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Product Specification
25
Spartan-3AN FPGA Family: DC and Switching Characteristics
Pin-to-Pin Setup and Hold Times
Table 22: Pin-to-Pin Setup and Hold Times for the IOB Input Path (System Synchronous)
Speed Grade
Symbol
Description
Conditions
Device
-5
-4
Units
Min
Min
Setup Times
TPSDCM
When writing to the Input
Flip-Flop (IFF), the time from the IFD_DELAY_VALUE = 0,
setup of data at the Input pin to
the active transition at a Global
Clock pin. The DCM is in use. No
Input Delay is programmed.
LVCMOS25(2)
,
XC3S50AN
2.45
2.59
2.38
2.38
1.91
2.55
2.32
2.21
2.28
2.33
2.68
2.84
2.68
2.57
2.17
2.76
2.76
2.60
2.63
2.41
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XC3S200AN
XC3S400AN
XC3S700AN
XC3S1400AN
XC3S50AN
with DCM(4)
TPSFD
When writing to IFF, the time from LVCMOS25(2)
the setup of data at the Input pin IFD_DELAY_VALUE = 5,
to an active transition at the
Global Clock pin. The DCM is not
in use. The Input Delay is
programmed.
,
XC3S200AN
XC3S400AN
XC3S700AN
XC3S1400AN
without DCM
Hold Times
TPHDCM
When writing to IFF, the time from LVCMOS25(3)
the active transition at the Global IFD_DELAY_VALUE = 0,
Clock pin to the point when data with DCM(4)
must be held at the Input pin. The
DCM is in use. No Input Delay is
programmed.
,
XC3S50AN
–0.36
–0.52
–0.33
–0.17
–0.07
–0.63
–0.56
–0.42
–0.80
–0.69
–0.36
–0.52
–0.29
–0.12
0.00
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XC3S200AN
XC3S400AN
XC3S700AN
XC3S1400AN
XC3S50AN
TPHFD
When writing to IFF, the time from LVCMOS25(3)
the active transition at the Global IFD_DELAY_VALUE = 5,
Clock pin to the point when data without DCM
must be held at the Input pin. The
DCM is not in use. The Input
Delay is programmed.
,
–0.58
–0.56
–0.42
–0.75
–0.69
XC3S200AN
XC3S400AN
XC3S700AN
XC3S1400AN
Notes:
1. The numbers in this table are tested using the methodology presented in Table 30 and are based on the operating conditions set forth in
Table 10 and Table 13.
2. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from Table 26. If this is true of the data Input, add the
appropriate Input adjustment from the same table.
3. This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from Table 26. If this is true of the data Input, subtract the
appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
4. DCM output jitter is included in all measurements.
DS557 (v4.2) June 12, 2014
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Product Specification
26
Spartan-3AN FPGA Family: DC and Switching Characteristics
Input Setup and Hold Times
Table 23: Setup and Hold Times for the IOB Input Path
Speed Grade
IFD_
Symbol
Description
Conditions
DELAY_
VALUE
Device
-5
-4
Units
Min
Min
Setup Times
TIOPICK
Time from the setup of data at the
Input pin to the active transition at the
ICLK input of the Input Flip-Flop (IFF).
No Input Delay is programmed.
LVCMOS25(2)
0
XC3S50AN
XC3S200AN
XC3S400AN
XC3S700AN
XC3S1400AN
XC3S50AN
1.56
1.71
1.30
1.34
1.36
2.16
3.10
3.51
4.04
3.88
4.72
5.47
5.97
2.05
2.72
3.38
3.88
3.69
4.56
5.34
5.85
1.79
2.43
3.02
3.49
3.41
4.20
4.96
5.44
1.58
1.81
1.51
1.51
1.74
2.18
3.12
3.76
4.32
4.24
5.09
5.94
6.52
2.20
2.93
3.78
4.37
4.20
5.23
6.11
6.71
2.02
2.67
3.43
3.96
3.95
4.81
5.66
6.19
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIOPICKD
Time from the setup of data at the
Input pin to the active transition at the
ICLK input of the Input Flip-Flop (IFF).
The Input Delay is programmed.
LVCMOS25(2)
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
XC3S200AN
XC3S400AN
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Product Specification
27
Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 23: Setup and Hold Times for the IOB Input Path (Cont’d)
Speed Grade
IFD_
DELAY_
VALUE
Symbol
Description
Conditions
Device
-5
-4
Units
Min
1.82
2.62
3.32
3.83
3.69
4.60
5.39
5.92
1.79
2.55
3.38
3.75
3.81
4.39
5.16
5.69
Min
1.95
2.83
3.72
4.31
4.14
5.19
6.10
6.73
2.17
2.92
3.76
4.32
4.19
5.09
5.98
6.57
TIOPICKD
Time from the setup of data at the
Input pin to the active transition at the
ICLK input of the Input Flip-Flop (IFF).
The Input Delay is programmed.
LVCMOS25(2)
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
XC3S700AN
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XC3S1400AN
Hold Times
TIOICKP
Time from the active transition at the LVCMOS25(3)
ICLK input of the Input Flip-Flop (IFF)
to the point where data must be held
at the Input pin. No Input Delay is
programmed.
XC3S50AN
XC3S200AN
XC3S400AN
XC3S700AN
XC3S1400AN
XC3S50AN
–0.66
–0.85
–0.42
–0.81
–0.71
–0.88
–1.33
–2.05
–2.43
–2.34
–2.81
–3.03
–3.83
–1.51
–2.09
–2.40
–2.68
–2.56
–2.99
–3.29
–3.61
–0.64
–0.65
–0.42
–0.67
–0.71
–0.88
–1.33
–2.05
–2.43
–2.34
–2.81
–3.03
–3.57
–1.51
–2.09
–2.40
–2.68
–2.56
–2.99
–3.29
–3.61
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
TIOICKPD
Time from the active transition at the LVCMOS25(3)
ICLK input of the Input Flip-Flop (IFF)
to the point where data must be held
at the Input pin. The Input Delay is
programmed.
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
XC3S200AN
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Product Specification
28
Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 23: Setup and Hold Times for the IOB Input Path (Cont’d)
Speed Grade
IFD_
DELAY_
VALUE
Symbol
Description
Conditions
Device
-5
-4
Units
Min
Min
TIOICKPD
Time from the active transition at the LVCMOS25(3)
ICLK input of the Input Flip-Flop (IFF)
to the point where data must be held
at the Input pin. The Input Delay is
programmed.
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
XC3S400AN
–1.12
–1.70
–2.08
–2.38
–2.23
–2.69
–3.08
–3.35
–1.67
–2.27
–2.59
–2.92
–2.89
–3.22
–3.52
–3.81
–1.60
–2.06
–2.46
–2.86
–2.88
–3.24
–3.55
–3.89
–1.12
–1.70
–2.08
–2.38
–2.23
–2.69
–3.08
–3.35
–1.67
–2.27
–2.59
–2.92
–2.89
–3.22
–3.52
–3.81
–1.60
–2.06
–2.46
–2.86
–2.88
–3.24
–3.55
–3.89
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XC3S700AN
XC3S1400AN
Set/Reset Pulse Width
TRPW_IOB
Minimum pulse width to SR control
input on IOB
–
–
All
1.33
1.61
ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 30 and are based on the operating conditions set forth in
Table 10 and Table 13.
2. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the
appropriate Input adjustment from Table 26.
3. These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract
the appropriate Input adjustment from Table 26. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
Table 24: Sample Window (Source Synchronous)
Symbol
Description
Maximum
Units
TSAMP
Setup and hold capture
The input capture sample window value is highly specific to a particular application, device,
ps
window of an IOB flip-flop. package, I/O standard, I/O placement, DCM usage, and clock buffer.
DS557 (v4.2) June 12, 2014
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Product Specification
29
Spartan-3AN FPGA Family: DC and Switching Characteristics
Input Propagation Times
Table 25: Propagation Times for the IOB Input Path
Speed
Grade
Symbol
Description
Conditions
DELAY_VALUE
Device
Units
-5
-4
Max Max
Propagation Times
TIOPI
The time it takes for data to travel LVCMOS25(2)
from the Input pin to the I output
with no input delay programmed
IBUF_DELAY_VALUE=0 XC3S50AN
XC3S200AN
1.04
0.87
0.65
0.92
1.12
0.87
0.72
0.92
1.21
2.07
2.46
2.71
3.21
3.46
3.84
4.19
4.47
4.11
4.50
4.67
5.20
5.44
5.95
6.28
6.57
1.65
1.97
2.33
2.96
3.19
3.60
4.02
4.26
3.86
4.25
4.55
5.24
5.53
5.94
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XC3S400AN
XC3S700AN
XC3S1400AN 0.96
TIOPID
The time it takes for data to travel LVCMOS25(2)
from the Input pin to the I output
with the input delay programmed
1
2
XC3S50AN
1.79
2.13
2.36
2.88
3.11
3.45
3.75
4.00
3.61
3.95
4.18
4.75
4.98
5.31
5.62
5.86
1.57
1.87
2.16
2.68
2.87
3.20
3.57
3.79
3.42
3.79
4.02
4.62
4.86
5.18
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
XC3S200AN
2
3
4
5
6
7
8
9
10
11
12
13
14
DS557 (v4.2) June 12, 2014
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Product Specification
30
Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 25: Propagation Times for the IOB Input Path (Cont’d)
Speed
Grade
Symbol
Description
Conditions
DELAY_VALUE
Device
Units
-5
-4
Max Max
TIOPID
The time it takes for data to travel LVCMOS25(2)
from the Input pin to the I output
with the input delay programmed
15
16
1
XC3S200AN
XC3S400AN
5.43
5.75
1.32
1.67
1.90
2.33
2.60
2.94
3.23
3.50
3.18
3.53
3.76
4.26
4.51
4.85
5.14
5.40
1.84
2.20
2.46
2.93
3.21
3.54
3.86
4.13
3.82
4.17
4.43
4.95
5.22
5.57
5.89
6.16
6.24
6.59
1.43
1.83
2.07
2.52
2.91
3.20
3.51
3.85
3.55
3.95
4.20
4.67
4.97
5.32
5.64
5.95
1.87
2.27
2.60
3.15
3.45
3.80
4.16
4.48
4.19
4.58
4.89
5.49
5.83
6.21
6.55
6.89
2.18
2.59
2.84
3.30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
XC3S700AN
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
XC3S1400AN 1.95
2
2.29
2.54
2.96
3
4
DS557 (v4.2) June 12, 2014
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Product Specification
31
Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 25: Propagation Times for the IOB Input Path (Cont’d)
Speed
Grade
Symbol
Description
Conditions
DELAY_VALUE
Device
Units
-5
-4
Max Max
TIOPID
The time it takes for data to travel LVCMOS25(2)
from the Input pin to the I output
with the input delay programmed
5
6
XC3S1400AN 3.17
3.52
3.92
4.18
4.57
4.31
4.79
5.06
5.51
5.73
6.08
6.33
6.77
1.81
2.04
1.74
1.74
1.97
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3.52
3.82
4.10
3.84
4.20
4.46
4.87
5.07
5.43
5.73
6.01
7
8
9
10
11
12
13
14
15
16
TIOPLI
The time it takes for data to travel LVCMOS25(2)
from the Input pin through the IFF
latch to the I output with no input
delay programmed
IFD_DELAY_VALUE=0 XC3S50AN
XC3S200AN
1.70
1.85
1.44
1.48
XC3S400AN
XC3S700AN
XC3S1400AN 1.50
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Product Specification
32
Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 25: Propagation Times for the IOB Input Path (Cont’d)
Speed
Grade
Symbol
Description
Conditions
DELAY_VALUE
Device
Units
-5
-4
Max Max
TIOPLID
The time it takes for data to travel LVCMOS25(2)
from the Input pin through the IFF
latch to the I output with the input
delay programmed
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
XC3S50AN
2.30
3.24
3.65
4.18
4.02
4.86
5.61
6.11
2.19
2.86
3.52
4.02
3.83
4.70
5.48
5.99
1.93
2.57
3.16
3.63
3.55
4.34
5.09
5.58
1.96
2.76
3.45
3.97
3.83
4.74
5.53
6.06
2.41
3.35
3.98
4.55
4.47
5.32
6.17
6.75
2.43
3.16
4.01
4.60
4.43
5.46
6.33
6.94
2.25
2.90
3.66
4.19
4.18
5.03
5.88
6.42
2.18
3.06
3.95
4.54
4.37
5.42
6.33
6.96
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XC3S200AN
XC3S400AN
XC3S700AN
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Product Specification
33
Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 25: Propagation Times for the IOB Input Path (Cont’d)
Speed
Grade
Symbol
Description
Conditions
DELAY_VALUE
Device
Units
-5
-4
Max Max
TIOPLID
The time it takes for data to travel LVCMOS25(2)
from the Input pin through the IFF
latch to the I output with the input
delay programmed
1
2
3
4
5
6
7
8
XC3S1400AN 1.93
2.40
3.15
3.99
4.55
4.42
5.32
6.21
6.80
ns
ns
ns
ns
ns
ns
ns
ns
2.69
3.52
3.89
3.95
4.53
5.30
5.83
Notes:
1. The numbers in this table are tested using the methodology presented in Table 30 and are based on the operating conditions set forth in
Table 10 and Table 13.
2. This propagation time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. When this is
true, add the appropriate Input adjustment from Table 26.
DS557 (v4.2) June 12, 2014
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Product Specification
34
Spartan-3AN FPGA Family: DC and Switching Characteristics
Input Timing Adjustments
Table 26: Input Timing Adjustments by IOSTANDARD
Add the
Table 26: Input Timing Adjustments by IOSTANDARD
Add the
Convert Input Time from
Adjustment Below
Convert Input Time from
Adjustment Below
LVCMOS25 to the
Following Signal Standard
(IOSTANDARD)
LVCMOS25 to the
Units
Units
Speed Grade
Following Signal Standard
(IOSTANDARD)
Speed Grade
-5
-4
-5
-4
Differential Standards
LVDS_25
Single-Ended Standards
LVTTL
0.76
0.79
0.79
0.78
0.79
0.78
0.79
0.79
0.77
0.79
0.79
0.79
0.74
0.72
1.05
0.72
1.05
0.71
0.71
0.74
0.75
1.06
1.06
0.76
0.79
0.79
0.78
0.79
0.78
0.79
0.79
0.77
0.79
0.79
0.79
0.74
0.72
1.05
0.72
1.05
0.71
0.71
0.74
0.75
1.06
1.06
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.62
0.54
0
0.62
0.54
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVDS_33
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI33_3
BLVDS_25
MINI_LVDS_25
MINI_LVDS_33
LVPECL_25
0.83
0.60
0.31
0.41
0.41
0.72
0.77
0.69
0.69
0.79
0.71
0.71
0.68
0.68
0.78
0.78
0.83
0.60
0.31
0.41
0.41
0.72
0.77
0.69
0.69
0.79
0.71
0.71
0.68
0.68
0.78
0.78
LVPECL_33
RSDS_25
PCI66_3
RSDS_33
HSTL_I
TMDS_33
HSTL_III
PPDS_25
HSTL_I_18
HSTL_II_18
HSTL_III_18
SSTL18_I
SSTL18_II
SSTL2_I
PPDS_33
DIFF_HSTL_I_18
DIFF_HSTL_II_18
DIFF_HSTL_III_18
DIFF_HSTL_I
DIFF_HSTL_III
DIFF_SSTL18_I
DIFF_SSTL18_II
DIFF_SSTL2_I
DIFF_SSTL2_II
DIFF_SSTL3_I
DIFF_SSTL3_II
SSTL2_II
SSTL3_I
SSTL3_II
Notes:
1. The numbers in this table are tested using the methodology
presented in Table 30 and are based on the operating conditions
set forth in Table 10, Table 13, and Table 15.
2. These adjustments are used to convert input path times originally
specified for the LVCMOS25 standard to times that correspond to
other signal standards.
DS557 (v4.2) June 12, 2014
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Product Specification
35
Spartan-3AN FPGA Family: DC and Switching Characteristics
Output Propagation Times
Table 27: Timing for the IOB Output Path
Speed Grade
Symbol
Description
Conditions
Device
-5
-4
Units
Max
Max
Clock-to-Output Times
TIOCKP
When reading from the Output
Flip-Flop (OFF), the time from the
active transition at the OCLK input to
data appearing at the Output pin
LVCMOS25(2), 12 mA output
drive, Fast slew rate
All
2.87
2.78
3.13
2.91
ns
Propagation Times
TIOOP
The time it takes for data to travel from LVCMOS25(2), 12 mA output
the IOB’s O input to the Output pin
All
All
ns
drive, Fast slew rate
Set/Reset Times
TIOSRP
Time from asserting the OFF’s SR
input to setting/resetting data at the
Output pin
LVCMOS25(2), 12 mA output
drive, Fast slew rate
3.63
8.62
3.89
9.65
ns
ns
TIOGSRQ
Time from asserting the Global Set
Reset (GSR) input on the
STARTUP_SPARTAN3A primitive to
setting/resetting data at the Output pin
Notes:
1. The numbers in this table are tested using the methodology presented in Table 30 and are based on the operating conditions set forth in
Table 10 and Table 13.
2. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data
Output. When this is true, add the appropriate Output adjustment from Table 29.
DS557 (v4.2) June 12, 2014
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Product Specification
36
Spartan-3AN FPGA Family: DC and Switching Characteristics
Three-State Output Propagation Times
Table 28: Timing for the IOB Three-State Path
Speed Grade
Symbol
Description
Conditions
Device
-5
-4
Units
Max
Max
Synchronous Output Enable/Disable Times
TIOCKHZ
Time from the active transition at the OTCLK
LVCMOS25, 12 mA
input of the Three-state Flip-Flop (TFF) to when output drive, Fast slew
the Output pin enters the high-impedance state rate
All
All
0.63
2.80
0.76
3.06
ns
ns
(2)
TIOCKON
Time from the active transition at TFF’s OTCLK
input to when the Output pin drives valid data
Asynchronous Output Enable/Disable Times
TGTS Time from asserting the Global Three State
LVCMOS25, 12 mA
output drive, Fast slew
rate
All
9.47
10.36
ns
(GTS) input on the STARTUP_SPARTAN3A
primitive to when the Output pin enters the
high-impedance state
Set/Reset Times
TIOSRHZ Time from asserting TFF’s SR input to when the LVCMOS25, 12 mA
All
All
1.61
3.57
1.86
3.82
ns
ns
Output pin enters a high-impedance state
output drive, Fast slew
rate
(2)
TIOSRON
Time from asserting TFF’s SR input at TFF to
when the Output pin drives valid data
Notes:
1. The numbers in this table are tested using the methodology presented in Table 30 and are based on the operating conditions set forth in
Table 10 and Table 13.
2. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the
data Output. When this is true, add the appropriate Output adjustment from Table 29.
DS557 (v4.2) June 12, 2014
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Product Specification
37
Spartan-3AN FPGA Family: DC and Switching Characteristics
Output Timing Adjustments
Table 29: Output Timing Adjustments for IOB (Cont’d)
Table 29: Output Timing Adjustments for IOB
Add the
Convert Output Time from
LVCMOS25 with 12 mA Drive
and Fast Slew Rate to the
Following Signal Standard
(IOSTANDARD)
Add the
Convert Output Time from
LVCMOS25 with 12 mA Drive
and Fast Slew Rate to the
Following Signal Standard
(IOSTANDARD)
Adjustment Below
Adjustment Below
Units
Units
Speed Grade
Speed Grade
-5
-4
-5
-4
LVCMOS33
Slow
2 mA
4 mA
5.58
5.58
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Single-Ended Standards
3.17
3.17
LVTTL
Slow
2 mA
4 mA
5.58
3.16
5.58
3.16
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6 mA
3.17
3.17
8 mA
2.09
2.09
6 mA
3.17
3.17
12 mA
16 mA
24 mA
2 mA
1.24
1.24
8 mA
2.09
2.09
1.15
1.15
12 mA
16 mA
24 mA
2 mA
1.62
1.62
2.55(3)
3.02
2.55(3)
3.02
1.24
1.24
2.74(3)
3.03
2.74(3)
3.03
Fast
4 mA
1.71
1.71
Fast
6 mA
1.72
1.72
4 mA
1.71
1.71
8 mA
0.53
0.53
6 mA
1.71
1.71
12 mA
16 mA
24 mA
0.59
0.59
8 mA
0.53
0.53
0.59
0.59
12 mA
16 mA
24 mA
0.53
0.53
0.51
0.51
0.59
0.59
QuietIO 2 mA
4 mA
27.67
27.67
27.67
16.71
16.29
16.18
12.11
27.67
27.67
27.67
16.71
16.29
16.18
12.11
0.60
0.60
QuietIO 2 mA
4 mA
27.67
27.67
27.67
16.71
16.67
16.22
12.11
27.67
27.67
27.67
16.71
16.67
16.22
12.11
6 mA
8 mA
6 mA
12 mA
8 mA
16 mA
12 mA
24 mA
16 mA
24 mA
DS557 (v4.2) June 12, 2014
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Product Specification
38
Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 29: Output Timing Adjustments for IOB (Cont’d)
Table 29: Output Timing Adjustments for IOB (Cont’d)
Add the
Add the
Convert Output Time from
LVCMOS25 with 12 mA Drive
and Fast Slew Rate to the
Following Signal Standard
(IOSTANDARD)
Convert Output Time from
LVCMOS25 with 12 mA Drive
and Fast Slew Rate to the
Following Signal Standard
(IOSTANDARD)
Adjustment Below
Adjustment Below
Units
Units
Speed Grade
Speed Grade
-5
-4
-5
-4
LVCMOS25
Slow
2 mA
4 mA
5.33
2.81
2.82
1.14
1.10
0.83
2.26(3)
4.36
1.76
1.25
0.38
0
5.33
2.81
2.82
1.14
1.10
0.83
2.26(3)
4.36
1.76
1.25
0.38
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVCMOS18
Slow
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
4.48
3.69
2.91
1.99
1.57
1.19
3.96
2.57
1.90
1.06
0.83
0.63
24.97
24.97
24.08
16.43
14.52
13.41
5.82
3.97
3.21
2.53
2.06
5.23
3.05
1.95
1.60
1.30
34.11
25.66
24.64
22.06
20.64
4.48
3.69
2.91
1.99
1.57
1.19
3.96
2.57
1.90
1.06
0.83
0.63
24.97
24.97
24.08
16.43
14.52
13.41
5.82
3.97
3.21
2.53
2.06
5.23
3.05
1.95
1.60
1.30
34.11
25.66
24.64
22.06
20.64
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6 mA
8 mA
12 mA
16 mA
24 mA
2 mA
Fast
Fast
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
0.01
0.01
25.92
25.92
25.92
15.57
15.59
14.27
11.37
0.01
0.01
25.92
25.92
25.92
15.57
15.59
14.27
11.37
QuietIO 2 mA
4 mA
QuietIO 2 mA
4 mA
6 mA
8 mA
6 mA
12 mA
8 mA
16 mA
12 mA
LVCMOS15
Slow
Fast
2 mA
4 mA
6 mA
8 mA
12 mA
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
QuietIO 2 mA
4 mA
6 mA
8 mA
12 mA
DS557 (v4.2) June 12, 2014
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Product Specification
39
Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 29: Output Timing Adjustments for IOB (Cont’d)
Table 29: Output Timing Adjustments for IOB (Cont’d)
Add the
Add the
Convert Output Time from
LVCMOS25 with 12 mA Drive
and Fast Slew Rate to the
Following Signal Standard
(IOSTANDARD)
Convert Output Time from
LVCMOS25 with 12 mA Drive
and Fast Slew Rate to the
Following Signal Standard
(IOSTANDARD)
Adjustment Below
Adjustment Below
Units
Units
Speed Grade
Speed Grade
-5
-4
-5
-4
LVCMOS12
Slow
2 mA
4 mA
6 mA
2 mA
4 mA
6 mA
7.14
4.87
5.67
6.77
5.02
4.09
50.76
43.17
37.31
0.34
0.34
0.78
1.16
0.35
0.30
0.47
0.40
0.30
0
7.14
4.87
5.67
6.77
5.02
4.09
50.76
43.17
37.31
0.34
0.34
0.78
1.16
0.35
0.30
0.47
0.40
0.30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Differential Standards
LVDS_25
1.16
0.46
0.11
0.75
0.40
1.16
0.46
0.11
0.75
0.40
ns
ns
ns
ns
ns
LVDS_33
Fast
BLVDS_25
MINI_LVDS_25
MINI_LVDS_33
LVPECL_25
QuietIO 2 mA
4 mA
Input Only
LVPECL_33
6 mA
RSDS_25
1.42
0.58
0.46
1.07
0.63
0.43
0.41
0.36
1.01
0.54
0.49
0.41
0.82
0.09
1.16
0.28
1.42
0.58
0.46
1.07
0.63
0.43
0.41
0.36
1.01
0.54
0.49
0.41
0.82
0.09
1.16
0.28
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PCI33_3
RSDS_33
PCI66_3
TMDS_33
HSTL_I
PPDS_25
HSTL_III
HSTL_I_18
HSTL_II_18
HSTL_III_18
SSTL18_I
SSTL18_II
SSTL2_I
PPDS_33
DIFF_HSTL_I_18
DIFF_HSTL_II_18
DIFF_HSTL_III_18
DIFF_HSTL_I
DIFF_HSTL_III
DIFF_SSTL18_I
DIFF_SSTL18_II
DIFF_SSTL2_I
DIFF_SSTL2_II
DIFF_SSTL3_I
DIFF_SSTL3_II
SSTL2_II
SSTL3_I
–0.05
0
–0.05
0
SSTL3_II
0.17
0.17
Notes:
1. The numbers in this table are tested using the methodology
presented in Table 30 and are based on the operating conditions
set forth in Table 10, Table 13, and Table 15.
2. These adjustments are used to convert output- and
three-state-path times originally specified for the LVCMOS25
standard with 12 mA drive and Fast slew rate to times that
correspond to other signal standards. Do not adjust times that
measure when outputs go into a high-impedance state.
3. Note that 16 mA drive is faster than 24 mA drive for the Slow slew
rate.
DS557 (v4.2) June 12, 2014
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Product Specification
40
Spartan-3AN FPGA Family: DC and Switching Characteristics
Timing Measurement Methodology
When measuring timing parameters at the programmable
I/Os, different signal standards call for different test
conditions. Table 30 lists the conditions to use for each
standard.
LVCMOS, LVTTL), then R is set to 1MΩ to indicate an
T
open connection, and V is set to zero. The same
T
measurement point (V ) that was used at the Input is also
M
used at the Output.
X-Ref Target - Figure 11
The method for measuring Input timing is as follows: A
signal that swings between a Low logic level of V and a
V (V
)
L
T
REF
High logic level of V is applied to the Input under test.
H
Some standards also require the application of a bias
FPGA Output
R (R
T
)
REF
voltage to the V
pins of a given bank to properly set the
REF
input-switching threshold. The measurement point of the
Input signal (V ) is commonly located halfway between V
V
(V
)
M
MEAS
M
L
and V .
H
C (C
)
L
REF
The Output test setup is shown in Figure 11. A termination
voltage V is applied to the termination resistor R , the other
DS312-3_04_102406
T
T
Notes:
end of which is connected to the Output. For each standard,
R and V generally take on the standard values
recommended for minimizing signal reflections. If the
1. The names shown in parentheses are
used in the IBIS file.
T
T
standard does not ordinarily use terminations (for example,
Figure 11: Output Test Setup
Table 30: Test Methods for Timing Measurement at I/Os
Inputs and
Inputs
Outputs(2)
VT (V)
Signal Standard
(IOSTANDARD)
Outputs
VREF (V)
VL (V)
VH (V)
RT (Ω)
VM (V)
Single-Ended
LVTTL
–
–
–
–
–
–
0
0
0
0
0
0
3.3
3.3
2.5
1.8
1.5
1.2
1M
1M
1M
1M
1M
1M
25
25
25
25
50
50
50
25
50
50
25
50
25
50
25
0
0
1.4
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI33_3
1.65
1.25
0.9
0
0
0
0.75
0.6
0
Rising
Falling
Rising
Falling
0
0.94
2.03
0.94
2.03
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
–
–
Note 3
Note 3
Note 3
Note 3
3.3
0
PCI66_3
3.3
0.75
1.5
0.9
0.9
1.8
0.9
0.9
1.25
1.25
1.5
1.5
HSTL_I
0.75
0.9
VREF – 0.5
VREF – 0.5
VREF – 0.5
VREF – 0.5
VREF – 0.5
VREF – 0.5
VREF – 0.5
VREF – 0.75
VREF – 0.75
VREF – 0.75
VREF – 0.75
VREF + 0.5
VREF + 0.5
VREF + 0.5
VREF + 0.5
VREF + 0.5
VREF + 0.5
VREF + 0.5
VREF + 0.75
VREF + 0.75
VREF + 0.75
VREF + 0.75
HSTL_III
HSTL_I_18
HSTL_II_18
HSTL_III_18
SSTL18_I
SSTL18_II
SSTL2_I
0.9
0.9
1.1
0.9
0.9
1.25
1.25
1.5
SSTL2_II
SSTL3_I
SSTL3_II
1.5
DS557 (v4.2) June 12, 2014
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Product Specification
41
Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 30: Test Methods for Timing Measurement at I/Os (Cont’d)
Inputs and
Outputs
Inputs
VL (V)
Outputs(2)
VT (V)
Signal Standard
(IOSTANDARD)
VREF (V)
VH (V)
RT (Ω)
VM (V)
Differential
LVDS_25
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
VICM – 0.125
VICM – 0.125
VICM – 0.125
VICM – 0.125
VICM – 0.125
VICM – 0.3
VICM – 0.3
VICM – 0.1
VICM – 0.1
VICM – 0.1
VICM – 0.1
VICM – 0.1
VICM – 0.5
VICM – 0.5
VICM – 0.5
VICM – 0.5
VICM – 0.5
VICM – 0.5
VICM – 0.5
VICM – 0.5
VICM – 0.5
VICM – 0.5
VICM – 0.5
VICM + 0.125
VICM + 0.125
VICM + 0.125
VICM + 0.125
VICM + 0.125
VICM + 0.3
VICM + 0.3
VICM + 0.1
VICM + 0.1
VICM + 0.1
VICM + 0.1
VICM + 0.1
VICM + 0.5
VICM + 0.5
VICM + 0.5
VICM + 0.5
VICM + 0.5
VICM + 0.5
VICM + 0.5
VICM + 0.5
VICM + 0.5
VICM + 0.5
VICM + 0.5
50
50
1M
50
50
N/A
N/A
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
1.2
1.2
0
VICM
VICM
VICM
VICM
VICM
VICM
VICM
VICM
VICM
VICM
VICM
VICM
VICM
VICM
VICM
VICM
VICM
VICM
VICM
VICM
VICM
VICM
VICM
LVDS_33
BLVDS_25
MINI_LVDS_25
MINI_LVDS_33
LVPECL_25
1.2
1.2
N/A
N/A
1.2
1.2
3.3
0.8
0.8
0.75
1.5
0.9
0.9
1.8
0.9
0.9
1.25
1.25
1.5
1.5
LVPECL_33
RSDS_25
RSDS_33
TMDS_33
PPDS_25
PPDS_33
DIFF_HSTL_I
DIFF_HSTL_III
DIFF_HSTL_I_18
DIFF_HSTL_II_18
DIFF_HSTL_III_18
DIFF_SSTL18_I
DIFF_SSTL18_II
DIFF_SSTL2_I
DIFF_SSTL2_II
DIFF_SSTL3_I
DIFF_SSTL3_II
Notes:
1. Descriptions of the relevant symbols are as follows:
V
V
V
– The reference voltage for setting the input switching threshold
REF
ICM
M
– The common mode input voltage
– Voltage of measurement point on signal transition
V – Low-level test voltage at Input pin
L
H
V
– High-level test voltage at Input pin
R – Effective termination resistance, which takes on a value of 1 MΩ when no parallel termination is required
T
V – Termination voltage
T
2. The load capacitance (C ) at the Output pin is 0 pF for all signal standards.
L
3. According to the PCI specification. For information on PCI IP solutions, see
www.xilinx.com/products/design_resources/conn_central/protocols/pci_pcix.htm. The PCIX IOSTANDARD is available and has equivalent
characteristics but no PCI-X IP is supported.
The capacitive load (C ) is connected between the output
L
and GND. The Output timing for all standards, as published
in the speed files and the data sheet, is always based on a
C value of zero. High-impedance probes (less than 1 pF)
L
are used for all measurements. Any delay that the test
fixture might contribute to test measurements is subtracted
from those measurements to produce the final timing
numbers as published in the speed files and data sheet.
DS557 (v4.2) June 12, 2014
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Product Specification
42
Spartan-3AN FPGA Family: DC and Switching Characteristics
and any other signal routing inside the package. Other
variables contribute to SSO noise levels, including stray
inductance on the PCB as well as capacitive loading at
receivers. Any SSO-induced voltage consequently affects
internal switching noise margins and ultimately signal
quality.
Using IBIS Models to Simulate Load
Conditions in Application
IBIS models permit the most accurate prediction of timing
delays for a given application. The parameters found in the
IBIS model (V , R , and V
) correspond directly
REF REF
MEAS
with the parameters used in Table 30 (V , R , and V ). Do
T
T
M
Table 31 and Table 32 provide the essential SSO
guidelines. For each device/package combination, Table 31
not confuse V
(the termination voltage) from the IBIS
REF
model with V
(the input-switching threshold) from the
REF
provides the number of equivalent V
/GND pairs. The
CCO
table. A fourth parameter, C , is always zero. The four
REF
equivalent number of pairs is based on characterization and
may not match the physical number of pairs. For each
output signal standard and drive strength, Table 32
recommends the maximum number of SSOs, switching in
parameters describe all relevant output test conditions. IBIS
models are found in the Xilinx development software as well
as at the following link:
the same direction, allowed per V
/GND pair within an
www.xilinx.com/support/download/index.htm
CCO
I/O bank. The guidelines in Table 32 are categorized by
package style, slew rate, and output drive current.
Furthermore, the number of SSOs is specified by I/O bank.
Generally, the left and right I/O banks (Banks 1 and 3)
support higher output drive current.
Delays for a given application are simulated according to its
specific load conditions as follows:
1. Simulate the desired signal standard with the output
driver connected to the test setup shown in Figure 11.
Use parameter values V , R , and V from Table 30.
T
T
M
Multiply the appropriate numbers from Table 31 and
Table 32 to calculate the maximum number of SSOs
allowed within an I/O bank. Exceeding these SSO
guidelines might result in increased power or ground
bounce, degraded signal integrity, or increased system jitter.
C
is zero.
REF
2. Record the time to V .
M
3. Simulate the same signal standard with the output
driver connected to the PCB trace with load. Use the
appropriate IBIS model (including V , R , C
,
REF REF REF
SSO
/IO Bank = Table 31 x Table 32
MAX
and V
load.
values) or capacitive value to represent the
MEAS
The recommended maximum SSO values assumes that the
FPGA is soldered on the printed circuit board and that the
board uses sound design practices. The SSO values do not
apply for FPGAs mounted in sockets, due to the lead
inductance introduced by the socket.
4. Record the time to V
.
MEAS
5. Compare the results of steps 2 and 4. Add (or subtract)
the increase (or decrease) in delay to (or from) the
appropriate Output standard adjustment (Table 29) to
yield the worst-case delay of the PCB trace.
The number of SSOs allowed for quad-flat packages (TQ) is
lower than for ball grid array packages (FG) due to the
larger lead inductance of the quad-flat packages. Ball grid
array packages are recommended for applications with a
large number of simultaneously switching outputs.
Simultaneously Switching Output
Guidelines
This section provides guidelines for the recommended
maximum allowable number of Simultaneous Switching
Outputs (SSOs). These guidelines describe the maximum
number of user I/O pins of a given output signal standard
that should simultaneously switch in the same direction,
while maintaining a safe level of switching noise. Meeting
these guidelines for the stated test conditions ensures that
the FPGA operates free from the adverse effects of ground
and power bounce.
Table 31: Equivalent V
/GND Pairs per Bank
Package Style
CCO
Device
TQG144 FTG256 FGG400 FGG484 FGG676
XC3S50AN
2
–
–
–
–
3
4
4
–
–
–
–
5
–
–
–
–
–
5
6
–
–
–
–
9
XC3S200AN
XC3S400AN
XC3S700AN
XC3S1400AN
Ground or power bounce occurs when a large number of
outputs simultaneously switch in the same direction. The
output drive transistors all conduct current to a common
voltage rail. Low-to-High transitions conduct to the V
CCO
rail; High-to-Low transitions conduct to the GND rail. The
resulting cumulative current transient induces a voltage
difference across the inductance that exists between the die
pad and the power supply or ground return. The inductance
is associated with bonding wires, the package lead frame,
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Product Specification
43
Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 32: Recommended Number of Simultaneously
Table 32: Recommended Number of Simultaneously
Switching Outputs per V
-GND Pair (Cont’d)
Switching Outputs per V
-GND Pair
CCO
CCO
Package Type
Package Type
FTG256,
FTG256,
FGG400,
FGG484,
FGG676
FGG400,
FGG484,
FGG676
TQG144
TQG144
Signal Standard
(IOSTANDARD)
Signal Standard
(IOSTANDARD)
Top,
Bottom Right
Banks 0,2 Banks 1,3 Banks 0,2 Banks 1,3
Left,
Top,
Bottom
Left,
Right
Top,
Bottom Right
Banks 0,2 Banks 1,3 Banks 0,2 Banks 1,3
Left,
Top,
Bottom
Left,
Right
LVCMOS33 Slow
2
4
24
14
11
10
9
24
14
11
10
9
76
46
27
20
13
10
–
76
46
27
20
13
10
9
Single-Ended Standards
LVTTL
Slow
2
4
20
10
10
6
20
10
10
6
60
41
29
22
13
11
9
60
41
29
22
13
11
9
6
8
6
12
16
24
2
8
8
8
12
16
24
2
6
6
–
8
5
5
Fast
10
8
10
8
10
8
10
8
4
4
4
Fast
10
6
10
6
10
6
10
6
6
5
5
5
5
4
8
4
4
4
4
6
5
5
5
5
12
16
24
2
4
4
4
4
8
3
3
3
3
2
2
2
2
12
16
24
2
3
3
3
3
–
2
–
2
3
3
3
3
QuietIO
36
32
24
16
16
12
–
36
32
24
16
16
12
10
76
46
32
26
18
14
–
76
46
32
26
18
14
10
2
2
2
2
4
QuietIO
40
24
20
16
12
9
40
24
20
16
12
9
80
48
36
27
16
13
12
80
48
36
27
16
13
12
6
4
8
6
12
16
24
8
12
16
24
9
9
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44
Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 32: Recommended Number of Simultaneously
Table 32: Recommended Number of Simultaneously
Switching Outputs per V
-GND Pair (Cont’d)
Switching Outputs per V
-GND Pair (Cont’d)
CCO
CCO
Package Type
Package Type
FTG256,
FTG256,
FGG400,
FGG484,
FGG676
FGG400,
FGG484,
FGG676
TQG144
TQG144
Signal Standard
(IOSTANDARD)
Signal Standard
(IOSTANDARD)
Top,
Bottom Right
Left,
Top,
Bottom
Left,
Right
Top,
Bottom Right
Left,
Top,
Bottom
Left,
Right
Banks 0,2 Banks 1,3 Banks 0,2 Banks 1,3
Banks 0,2 Banks 1,3 Banks 0,2 Banks 1,3
LVCMOS25 Slow
2
4
16
10
8
16
10
8
76
46
33
24
18
–
76
46
33
24
18
11
7
LVCMOS18 Slow
2
4
13
8
13
8
64
34
22
18
–
64
34
22
18
13
10
18
9
6
6
8
8
8
7
7
8
7
7
12
16
24
2
6
6
12
16
2
–
5
–
6
–
5
–
–
5
–
Fast
13
8
13
8
18
9
Fast
12
10
8
12
10
8
18
14
6
18
14
6
4
4
6
7
7
7
7
6
8
4
4
4
4
8
6
6
6
6
12
16
2
–
4
–
4
12
16
24
2
3
3
3
3
–
3
–
3
–
3
–
3
QuietIO
30
24
20
16
–
30
24
20
16
12
12
12
7
64
64
48
36
–
64
64
48
36
36
24
55
31
18
15
10
25
10
6
–
2
–
2
4
QuietIO
36
30
24
20
12
–
36
30
24
20
12
12
8
76
60
48
36
36
–
76
60
48
36
36
36
8
6
4
8
6
12
16
2
8
–
–
12
16
24
LVCMOS15 Slow
12
7
55
31
18
–
4
–
–
6
7
7
8
–
6
12
2
–
5
–
Fast
10
7
10
7
25
10
6
4
6
6
6
8
–
4
–
4
12
2
–
3
–
3
QuietIO
30
21
18
–
30
21
18
12
12
70
40
31
–
70
40
31
31
20
4
6
8
12
–
–
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Product Specification
45
Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 32: Recommended Number of Simultaneously
Table 32: Recommended Number of Simultaneously
Switching Outputs per V
-GND Pair (Cont’d)
Switching Outputs per V
-GND Pair (Cont’d)
CCO
CCO
Package Type
Package Type
FTG256,
FTG256,
FGG400,
FGG484,
FGG676
FGG400,
FGG484,
FGG676
TQG144
TQG144
Signal Standard
(IOSTANDARD)
Signal Standard
(IOSTANDARD)
Top,
Bottom Right
Left,
Top,
Bottom
Left,
Right
Top,
Bottom Right
Left,
Top,
Bottom
Left,
Right
Banks 0,2 Banks 1,3 Banks 0,2 Banks 1,3
Banks 0,2 Banks 1,3 Banks 0,2 Banks 1,3
LVCMOS12 Slow
2
4
6
2
4
6
2
4
6
17
–
17
13
10
9
40
–
40
25
18
31
13
9
PPDS_33
8
–
–
6
–
4
3
–
5
–
3
2
–
5
3
6
2
4
6
4
5
3
4
3
27
–
–
8
–
5
3
–
9
–
4
3
–
10
4
DIFF_HSTL_I
–
–
DIFF_HSTL_III
DIFF_HSTL_I_18
DIFF_HSTL_II_18
DIFF_HSTL_III_18
DIFF_SSTL18_I
DIFF_SSTL18_II
DIFF_SSTL2_I
DIFF_SSTL2_II
DIFF_SSTL3_I
DIFF_SSTL3_II
Fast
12
–
31
–
8
9
2
–
9
–
4
QuietIO
36
–
36
33
27
9
55
–
55
36
36
16
13
20
8
7
4
–
–
9
PCI33_3
9
16
–
4
PCI66_3
–
9
5
HSTL_I
–
11
7
–
3
HSTL_III
HSTL_I_18
HSTL_II_18
HSTL_III_18
SSTL18_I
SSTL18_II
SSTL2_I
–
–
Notes:
1. Not all I/O standards are supported on all I/O banks. The left and
right banks (I/O banks 1 and 3) support higher output drive
current than the top and bottom banks (I/O banks 0 and 2).
Similarly, true differential output standards, such as LVDS, RSDS,
PPDS, miniLVDS, and TMDS, are only supported in top or bottom
banks (I/O banks 0 and 2). Refer to UG331: Spartan-3
13
–
13
5
17
–
17
5
8
8
10
7
8
7
13
9
15
9
Generation FPGA User Guide for additional information.
–
–
2. The numbers in this table are recommendations that assume
sound board lay out practice. Test limits are the V /V voltage
IL IH
10
–
10
6
18
–
18
9
limits for the respective I/O standard.
3. If more than one signal standard is assigned to the I/Os of a given
bank, refer to XAPP689: Managing Ground Bounce in Large
FPGAs for information on how to perform weighted average SSO
calculations.
SSTL2_II
SSTL3_I
7
8
8
10
7
SSTL3_II
5
6
6
Differential Standards (Number of I/O Pairs or Channels)
LVDS_25
8
8
1
8
8
–
–
1
–
–
22
27
4
–
–
4
–
–
LVDS_33
BLVDS_25
MINI_LVDS_25
MINI_LVDS_33
LVPECL_25
LVPECL_33
RSDS_25
22
27
Input Only
Input Only
8
8
8
8
–
22
27
27
22
–
–
–
–
RSDS_33
–
–
–
TMDS_33
PPDS_25
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Configurable Logic Block (CLB) Timing
Table 33: CLB (SLICEM) Timing
Speed Grade
Symbol
Description
-5
-4
Units
Min
Max
Min
Max
Clock-to-Output Times
TCKO
When reading from the FFX (FFY) Flip-Flop, the time
from the active transition at the CLK input to data
appearing at the XQ (YQ) output
–
0.60
–
0.68
ns
Setup Times
TAS
Time from the setup of data at the F or G input to the
active transition at the CLK input of the CLB
0.18
1.58
–
–
0.36
1.88
–
–
ns
ns
TDICK
Time from the setup of data at the BX or BY input to
the active transition at the CLK input of the CLB
Hold Times
TAH
Time from the active transition at the CLK input to the
point where data is last held at the F or G input
0
0
–
–
0
0
–
–
ns
ns
TCKDI
Time from the active transition at the CLK input to the
point where data is last held at the BX or BY input
Clock Timing
TCH
The High pulse width of the CLB’s CLK signal
The Low pulse width of the CLK signal
Toggle frequency (for export control)
0.63
0.63
0
–
–
0.75
0.75
0
–
–
ns
ns
TCL
FTOG
770
667
MHz
Propagation Times
TILO
The time it takes for data to travel from the CLB’s F
(G) input to the X (Y) output
–
0.62
–
–
0.71
–
ns
ns
Set/Reset Pulse Width
TRPW_CLB
The minimum allowable pulse width, High or Low, to
the CLB’s SR input
1.33
1.61
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 10.
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 34: CLB Distributed RAM Switching Characteristics
Speed Grade
Symbol
Description
-5
-4
Units
Min
Max
Min
Max
Clock-to-Output Times
TSHCKO
Time from the active edge at the CLK input to data appearing on
the distributed RAM output
–
1.69
–
2.01
ns
Setup Times
TDS
Setup time of data at the BX or BY input before the active
transition at the CLK input of the distributed RAM
–0.07
0.18
0.30
–
–
–
–0.02
0.36
0.59
–
–
–
ns
ns
ns
TAS
Setup time of the F/G address inputs before the active transition
at the CLK input of the distributed RAM
TWS
Setup time of the write enable input before the active transition at
the CLK input of the distributed RAM
Hold Times
TDH
Hold time of the BX and BY data inputs after the active transition
at the CLK input of the distributed RAM
0.13
0.01
–
–
0.13
0.01
–
–
ns
ns
T
AH, TWH
Hold time of the F/G address inputs or the write enable input after
the active transition at the CLK input of the distributed RAM
Clock Pulse Width
TWPH, TWPL
Minimum High or Low pulse width at CLK input
0.88
–
1.01
–
ns
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 10.
Table 35: CLB Shift Register Switching Characteristics
Speed Grade
Symbol
Description
-5
-4
Units
Min
Max
Min
Max
Clock-to-Output Times
TREG
Time from the active edge at the CLK input to data appearing on
the shift register output
–
4.11
–
4.82
ns
ns
Setup Times
TSRLDS
Setup time of data at the BX or BY input before the active
transition at the CLK input of the shift register
0.13
–
0.18
–
Hold Times
TSRLDH
Hold time of the BX or BY data input after the active transition at
the CLK input of the shift register
0.16
0.90
–
–
0.16
1.01
–
–
ns
ns
Clock Pulse Width
TWPH, TWPL
Minimum High or Low pulse width at CLK input
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 10.
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Clock Buffer/Multiplexer Switching Characteristics
Table 36: Clock Distribution Switching Characteristics
Maximum
Description
Symbol
Minimum
Speed Grade
Units
-5
-4
Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to
O-output delay
TGIO
–
0.22
0.23
ns
Global clock multiplexer (BUFGMUX) select S-input setup to I0 and
I1 inputs. Same as BUFGCE enable CE-input
TGSI
–
0
0.56
350
0.63
334
ns
Frequency of signals distributed on global buffers (all sides)
FBUFG
MHz
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 10.
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Spartan-3AN FPGA Family: DC and Switching Characteristics
18 x 18 Embedded Multiplier Timing
Table 37: 18 x 18 Embedded Multiplier Timing
Speed Grade
Symbol
Description
-5
-4
Units
Min
Max
Min
Max
Combinatorial Delay
TMULT
Combinational multiplier propagation delay from the A and B inputs
to the P outputs, assuming 18-bit inputs and a 36-bit product
(AREG, BREG, and PREG registers unused)
–
4.36
–
4.88
ns
Clock-to-Output Times
TMSCKP_P
Clock-to-output delay from the active transition of the CLK input to
valid data appearing on the P outputs when using the PREG
–
–
0.84
4.44
–
–
1.30
4.97
ns
ns
register(2,3)
TMSCKP_A
TMSCKP_B
Clock-to-output delay from the active transition of the CLK input to
valid data appearing on the P outputs when using either the AREG
or BREG register(2,4)
Setup Times
TMSDCK_P
Data setup time at the A or B input before the active transition at the
CLK when using only the PREG output register (AREG, BREG
registers unused)(3)
3.56
–
3.98
–
ns
TMSDCK_A
TMSDCK_B
Data setup time at the A input before the active transition at the CLK
when using the AREG input register(4)
0.00
0.00
–
–
0.00
0.00
–
–
ns
ns
Data setup time at the B input before the active transition at the CLK
when using the BREG input register(4)
Hold Times
TMSCKD_P
Data hold time at the A or B input after the active transition at the
CLK when using only the PREG output register (AREG, BREG
registers unused)(3)
0.00
–
0.00
–
ns
TMSCKD_A
TMSCKD_B
Clock Frequency
Data hold time at the A input after the active transition at the CLK
0.35
0.35
–
–
0.45
0.45
–
–
ns
ns
when using the AREG input register(4)
Data hold time at the B input after the active transition at the CLK
when using the BREG input register(4)
FMULT
Internal operating frequency for a two-stage 18x18 multiplier using
the AREG and BREG input registers and the PREG output
0
280
0
250
MHz
register(5)
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 10.
2. The PREG register is typically used in both single-stage and two-stage pipelined multiplier implementations.
3. The PREG register is typically used when inferring a single-stage multiplier.
4. Input registers AREG or BREG are typically used when inferring a two-stage multiplier.
5. Combinational delay is less and pipelined performance is higher when multiplying input data with less than 18 bits.
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50
Spartan-3AN FPGA Family: DC and Switching Characteristics
Block RAM Timing
Table 38: Block RAM Timing
Speed Grade
Symbol
Description
-5
-4
Units
Min
Max
Min
Max
Clock-to-Output Times
TRCKO
When reading from block RAM, the delay from the active
transition at the CLK input to data appearing at the DOUT
output
–
2.06
–
2.49
ns
Setup Times
TRCCK_ADDR Setup time for the ADDR inputs before the active transition at
the CLK input of the block RAM
0.32
0.28
0.69
1.12
–
–
–
–
0.36
0.31
0.77
1.26
–
–
–
–
ns
ns
ns
ns
TRDCK_DIB
Setup time for data at the DIN inputs before the active
transition at the CLK input of the block RAM
TRCCK_ENB Setup time for the EN input before the active transition at the
CLK input of the block RAM
TRCCK_WEB Setup time for the WE input before the active transition at the
CLK input of the block RAM
Hold Times
TRCKC_ADDR Hold time on the ADDR inputs after the active transition at the
CLK input
0
0
0
0
–
–
–
–
0
0
0
0
–
–
–
–
ns
ns
ns
ns
TRCKD_DIB
Hold time on the DIN inputs after the active transition at the
CLK input
TRCKC_ENB Hold time on the EN input after the active transition at the CLK
input
TRCKC_WEB Hold time on the WE input after the active transition at the CLK
input
Clock Timing
TBPWH
TBPWL
Clock Frequency
High pulse width of the CLK signal
1.56
1.56
–
–
1.79
1.79
–
–
ns
ns
Low pulse width of the CLK signal
FBRAM
Block RAM clock frequency
0
320
0
280
MHz
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 10.
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Digital Clock Manager (DCM) Timing
For specification purposes, the DCM consists of three key
components: the Delay-Locked Loop (DLL), the Digital
Frequency Synthesizer (DFS), and the Phase Shifter (PS).
Period jitter is the worst-case deviation from the ideal clock
period over a collection of millions of samples. In a
histogram of period jitter, the mean value is the clock period.
Aspects of DLL operation play a role in all DCM
Cycle-cycle jitter is the worst-case difference in clock period
between adjacent clock cycles in the collection of clock
periods sampled. In a histogram of cycle-cycle jitter, the
mean value is zero.
applications. All such applications inevitably use the CLKIN
and the CLKFB inputs connected to either the CLK0 or the
CLK2X feedback, respectively. Thus, specifications in the
DLL tables (Table 39 and Table 40) apply to any application
that only employs the DLL component. When the DFS
and/or the PS components are used together with the DLL,
then the specifications listed in the DFS and PS tables
(Table 41 through Table 44) supersede any corresponding
ones in the DLL tables. DLL specifications that do not
change with the addition of DFS or PS functions are
presented in Table 39 and Table 40.
Spread Spectrum
DCMs accept typical spread spectrum clocks as long as
they meet the input requirements. The DLL will track the
frequency changes created by the spread spectrum clock to
drive the global clocks to the FPGA logic. See XAPP469:
Spread-Spectrum Clocking Reception for Displays for
details.
Period jitter and cycle-cycle jitter are two of many different
ways of specifying clock jitter. Both specifications describe
statistical variation from a mean value.
Delay-Locked Loop (DLL)
Table 39: Recommended Operating Conditions for the DLL
Speed Grade
Symbol
Description
-5
-4
Units
Min
Max
Min
Max
Input Frequency Ranges
FCLKIN
CLKIN_FREQ_DLL
Frequency of the CLKIN clock input
5(2)
280(3)
5(2)
250(3) MHz
Input Pulse Requirements
CLKIN_PULSE
CLKIN pulse width as a
percentage of the CLKIN
period
FCLKIN < 150 MHz
40%
45%
60%
55%
40%
45%
60%
55%
%
%
FCLKIN > 150 MHz
Input Clock Jitter Tolerance and Delay Path Variation(4)
CLKIN_CYC_JITT_DLL_LF
CLKIN_CYC_JITT_DLL_HF
CLKIN_PER_JITT_DLL
Cycle-to-cycle jitter at the
CLKIN input
FCLKIN < 150 MHz
FCLKIN > 150 MHz
–
–
–
–
300
150
1
–
–
–
–
300
150
1
ps
ps
ns
ns
Period jitter at the CLKIN input
CLKFB_DELAY_VAR_EXT
Allowable variation of off-chip feedback delay
from the DCM output to the CLKFB input
1
1
Notes:
1. DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.
2. The DFS, when operating independently of the DLL, supports lower FCLKIN frequencies. See Table 41.
3. The CLKIN_DIVIDE_BY_2 attribute can be used to increase the effective input frequency range up to F
CLKIN_DIVIDE_BY_2 divides the incoming clock frequency by two as it enters the DCM.
. When set to TRUE,
BUFG
4. CLKIN input jitter beyond these limits might cause the DCM to lose lock.
5. The DCM specifications are guaranteed when both adjacent DCMs are locked.
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Speed Grade
Table 40: Switching Characteristics for the DLL
Symbol
Description
Device
-5
-4
Units
Min
Max
Min
Max
Output Frequency Ranges
CLKOUT_FREQ_CLK0
CLKOUT_FREQ_CLK90
CLKOUT_FREQ_2X
Frequency for the CLK0 and CLK180 outputs
Frequency for the CLK90 and CLK270 outputs
Frequency for the CLK2X and CLK2X180 outputs
Frequency for the CLKDV output
All
5
5
280
200
334
186
5
5
250
200
334
166
MHz
MHz
MHz
MHz
10
10
CLKOUT_FREQ_DV
0.3125
0.3125
Output Clock Jitter(2,3,4)
CLKOUT_PER_JITT_0
CLKOUT_PER_JITT_90
Period jitter at the CLK0 output
Period jitter at the CLK90 output
All
–
–
–
–
–
100
150
150
150
–
–
–
–
–
100
150
150
150
ps
ps
ps
ps
CLKOUT_PER_JITT_180 Period jitter at the CLK180 output
CLKOUT_PER_JITT_270 Period jitter at the CLK270 output
CLKOUT_PER_JITT_2X
Period jitter at the CLK2X and CLK2X180 outputs
[0.5%
of
[0.5% ps
of
CLKIN
period
+ 100]
CLKIN
period
+ 100]
CLKOUT_PER_JITT_DV1 Period jitter at the CLKDV output when performing
integer division
–
–
150
–
–
150
ps
CLKOUT_PER_JITT_DV2 Period jitter at the CLKDV output when performing
non-integer division
[0.5%
of
[0.5% ps
of
CLKIN
period
+ 100]
CLKIN
period
+ 100]
Duty Cycle(4)
CLKOUT_DUTY_CYCLE_DLL
Duty cycle variation for the CLK0, CLK90, CLK180,
CLK270, CLK2X, CLK2X180, and CLKDV outputs,
including the BUFGMUX and clock tree duty-cycle
distortion
All
All
–
[1%of
CLKIN
period
+ 350]
–
[1%of ps
CLKIN
period
+ 350]
Phase Alignment(4)
CLKIN_CLKFB_PHASE
CLKOUT_PHASE_DLL
Phase offset between the CLKIN and CLKFB inputs
–
–
150
–
–
150
ps
Phase offset between DLL
outputs
CLK0 to CLK2X
(not CLK2X180)
[1%of
CLKIN
period
+ 100]
[1%of ps
CLKIN
period
+ 100]
All others
–
[1%of
CLKIN
period
+ 150]
–
[1%of ps
CLKIN
period
+ 150]
Lock Time
LOCK_DLL(3)
When using the DLL alone:
The time from deassertion at
the DCM’s Reset input to the
rising transition at its LOCKED
output. When the DCM is
locked, the CLKIN and CLKFB
signals are in phase
5 MHz < FCLKIN
15 MHz
<
All
–
–
5
–
–
5
ms
µs
FCLKIN > 15 MHz
600
600
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53
Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 40: Switching Characteristics for the DLL (Cont’d)
Speed Grade
Symbol
Description
Device
-5
-4
Units
Min
Max
Min
Max
Delay Lines
DCM_DELAY_STEP(5)
Finest delay resolution, average over all taps
All
15
35
15
35
ps
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 10 and Table 39.
2. Indicates the maximum amount of output jitter that the DCM adds to the jitter on the CLKIN input.
3. For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
4. Some jitter and duty-cycle specifications include 1% of input clock period or 0.01 UI. For example, the data sheet specifies a maximum jitter
of “ [1% of CLKIN period + 150]”. Assume the CLKIN frequency is 100 MHz. The equivalent CLKIN period is 10 ns and 1% of 10 ns is 0.1 ns
or 100 ps. According to the data sheet, the maximum jitter is [100 ps + 150 ps] = 250 ps.
5. The typical delay step size is 23 ps.
Digital Frequency Synthesizer (DFS)
Table 41: Recommended Operating Conditions for the DFS
Speed Grade
Symbol
Description
-5
-4
Units
Min
Max
Min
Max
Input Frequency Ranges(2)
FCLKIN
CLKIN_FREQ_FX
Frequency for the CLKIN input
0.200
333(3)
0.200
333(3)
MHz
Input Clock Jitter Tolerance(4)
CLKIN_CYC_JITT_FX_LF
CLKIN_CYC_JITT_FX_HF
Cycle-to-cycle jitter at the
CLKIN input, based on CLKFX
output frequency
FCLKFX < 150 MHz
CLKFX > 150 MHz
–
–
300
150
–
–
300
150
ps
ps
F
CLKIN_PER_JITT_FX
Period jitter at the CLKIN input
–
1
–
1
ns
Notes:
1. DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) are used.
2. If both DFS and DLL outputs are used on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in Table 39.
3. To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming
clock frequency by two as it enters the DCM.
4. CLKIN input jitter beyond these limits may cause the DCM to lose lock.
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54
Spartan-3AN FPGA Family: DC and Switching Characteristics
Speed Grade
Table 42: Switching Characteristics for the DFS
Symbol
Description
Device
-5
-4
Units
MHz
ps
Min
5
Max
350
Min
5
Max
320
Output Frequency Ranges
CLKOUT_FREQ_FX
Frequency for the CLKFX and CLKFX180 outputs
All
All
Output Clock Jitter (2)(3)
CLKOUT_PER_JITT_FX Period jitter at the CLKFX and
CLKFX180 outputs.
CLKIN
≤ 20 MHz
Typ
Max
Typ
Max
Use the Spartan-3A Jitter
Calculator:
www.xilinx.com/support/documenta
tion/data_sheets/s3a_jitter_calc.zip
CLKIN
> 20 MHz
[1% of [1% of [1% of [1% of ps
CLKFX CLKFX CLKFX CLKFX
period period period period
+ 100] + 200] + 100] + 200]
Duty Cycle(4)(5)
CLKOUT_DUTY_CYCLE_FX
Duty cycle precision for the CLKFX and CLKFX180
outputs, including the BUFGMUX and clock tree
duty-cycle distortion
All
–
[1%of
CLKFX
period
+ 350]
–
[1% of ps
CLKFX
period
+ 350]
Phase Alignment(5)
CLKOUT_PHASE_FX
Phase offset between the DFS CLKFX
output and the DLL CLK0 output when
both the DFS and DLL are used
All
All
–
–
200
–
–
200
ps
CLKOUT_PHASE_FX180 Phase offset between the DFS
CLKFX180 output and the DLL CLK0
output when both the DFS and DLL
are used
[1% of
CLKFX
period
+ 200]
[1% of ps
CLKFX
period
+ 200]
Lock Time
LOCK_FX(2)
The time from deassertion at the
DCM’s Reset input to the rising
transition at its LOCKED output. The
DFS asserts LOCKED when the
CLKFX and CLKFX180 signals are
valid. If using both the DLL and the
DFS, use the longer locking time.
5MHz<FCLKIN
< 15 MHz
All
–
–
5
–
–
5
ms
µs
FCLKIN
>
450
450
15 MHz
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 10 and Table 41.
2. For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
3. Maximum output jitter is characterized within a reasonable noise environment (40 SSOs and 25% CLB switching) on an XC3S1400A FPGA.
Output jitter strongly depends on the environment, including the number of SSOs, the output drive strength, CLB utilization, CLB switching
activities, switching frequency, power supply and PCB design. The actual maximum output jitter depends on the system application.
4. The CLKFX and CLKFX180 outputs always have an approximate 50% duty cycle.
5. Some duty-cycle and alignment specifications include a percentage of the CLKFX output period. For example, the data sheet specifies a
maximum CLKFX jitter of “ [1% of CLKFX period + 200]”. Assume the CLKFX output frequency is 100 MHz. The equivalent CLKFX period
is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is [100 ps + 200 ps] = 300 ps.
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55
Spartan-3AN FPGA Family: DC and Switching Characteristics
Phase Shifter (PS)
Table 43: Recommended Operating Conditions for the PS in Variable Phase Mode
Speed Grade
Symbol
Description
-5
-4
Units
Min
1
Max
167
Min
1
Max
167
Operating Frequency Ranges
PSCLK_FREQ (FPSCLK) Frequency for the PSCLK input
MHz
%
Input Pulse Requirements
PSCLK_PULSE
PSCLK pulse width as a percentage of the PSCLK period
40%
60%
40%
60%
Table 44: Switching Characteristics for the PS in Variable Phase Mode
Symbol
Phase Shifting Range
MAX_STEPS(2,3)
Description
Phase Shift Amount
Units
Maximum allowed number of
CLKIN < 60 MHz
[INTEGER(10 • (TCLKIN – 3 ns))] steps
DCM_DELAY_STEP steps for a given
CLKIN clock period, where T = CLKIN
clock period in ns. If using
CLKIN ≥ 60 MHz [INTEGER(15 • (TCLKIN – 3 ns))]
CLKIN_DIVIDE_BY_2 = TRUE, double
the clock effective clock period.
FINE_SHIFT_RANGE_MIN
Minimum guaranteed delay for variable phase shifting
[MAX_STEPS •
ns
ns
DCM_DELAY_STEP_MIN]
FINE_SHIFT_RANGE_MAX Maximum guaranteed delay for variable phase shifting
[MAX_STEPS •
DCM_DELAY_STEP_MAX]
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 10 and Table 43.
2. The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM is has no initial fixed phase shifting, that is, the
PHASE_SHIFT attribute is set to 0.
3. The DCM_DELAY_STEP values are provided at the bottom of Table 40.
Miscellaneous DCM Timing
Table 45: Miscellaneous DCM Timing
Symbol
Description
Min
Max
Units
DCM_RST_PW_MIN
Minimum duration of a RST pulse width
3
–
CLKIN
cycles
DCM_RST_PW_MAX(2)
Maximum duration of a RST pulse width
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
seconds
seconds
minutes
minutes
DCM_CONFIG_LAG_TIME(3)
Maximum duration from VCCINT applied to FPGA configuration
successfully completed (DONE pin goes High) and clocks
applied to DCM DLL
Notes:
1. This limit only applies to applications that use the DCM DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV).
The DCM DFS outputs (CLKFX, CLKFX180) are unaffected.
2. This specification is equivalent to the Virtex™-4 FPGA DCM_RESET specification. This specification does not apply for Spartan-3AN
FPGAs.
3. This specification is equivalent to the Virtex-4 FPGA T
specification. This specification does not apply for Spartan-3AN FPGAs.
CONFIG
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Spartan-3AN FPGA Family: DC and Switching Characteristics
DNA Port Timing
Table 46: DNA_PORT Interface Timing
Symbol
Description
Min
1.0
0.5
1.0
0.5
5.0
0
Max
Units
ns
TDNASSU
TDNASH
TDNADSU
TDNADH
TDNARSU
TDNARH
Setup time on SHIFT before the rising edge of CLK
Hold time on SHIFT after the rising edge of CLK
Setup time on DIN before the rising edge of CLK
Hold time on DIN after the rising edge of CLK
Setup time on READ before the rising edge of CLK
Hold time on READ after the rising edge of CLK
Clock-to-output delay on DOUT after rising edge of CLK
CLK frequency
–
–
ns
–
–
ns
ns
10,000
–
ns
ns
TDNADCKO
TDNACLKF
TDNACLKH
TDNACLKL
0.5
0
1.5
100
∞
ns
MHz
ns
CLK High time
1.0
1.0
CLK Low time
∞
ns
Notes:
1. The minimum READ pulse width is 5 ns, the maximum READ pulse width is 10 µs.
Internal SPI Access Port Timing
Table 47: SPI_ACCESS Interface Timing
Speed Grade
Symbol
Description
-5
-4
Units
Min
4.47
4.03
50
Max
–
Min
5.0
4.5
50
8.0
8.0
–
Max
TSPICCK_MOSI
TSPICKC_MOSI
TCSB
Setup time on MOSI before the active edge of CLK
Hold time on MOSI after the active edge of CLK
CSB High time
–
–
ns
ns
–
–
–
ns
TSPICCK_CSB
TSPICCK_CSB
TSPICKO_MISO
FSPICLK
Setup time on CSB before the active edge of CLK
Hold time on CSB after the active edge of CLK
Clock-to-output delay on MISO after active edge of CLK
CLK frequency
7.15
7.15
–
–
–
ns
–
–
ns
14.3
50
50
33
16.0
50
50
33
ns
–
–
MHz
MHz
MHz
FSPICAR1
CLK frequency for Continuous Array Read command
–
–
FSPICAR1
CLK frequency for Continuous Array Read command,
reduced initial latency
–
–
TSPICLKL
TSPICLKH
Notes:
1. For details on using SPI_ACCESS and the In-System Flash memory, see UG333 Spartan-3AN FPGA In-System Flash User Guide.
CLK High time
–
∞
–
∞
ns
ns
CLK Low time
6.8
∞
6.8
∞
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Spartan-3AN FPGA Family: DC and Switching Characteristics
In-System Flash (ISF) Memory Timing
Table 48: In-System Flash (ISF) Memory Operations
Symbol
TXFER
TCOMP
TPP
Description
Page to Buffer transfer time
Device
All
Typical(1)
Max
400
400
4
Units
µs
–
–
2
Page to Buffer compare time
Page Programming time
All
µs
XC3S50AN
XC3S200AN
XC3S400AN
ms
XC3S700AN
XC3S1400AN
3
6
ms
ms
TPE
TPEP
TBE
Page Erase time
XC3S50AN
XC3S200AN
XC3S400AN
13
32
XC3S700AN(2)
XC3S1400AN
15
14
35
35
ms
ms
Page Erase and Programming time
XC3S50AN
XC3S200AN
XC3S400AN
XC3S700AN(3)
XC3S1400AN
XC3S50AN
17
15
30
40
35
75
ms
ms
ms
Block Erase time
XC3S200AN
XC3S400AN
XC3S700AN
XC3S1400AN
45
100
ms
TSE
Sector Erase time
XC3S50AN
0.8
1.6
2.5
5
s
s
XC3S200AN
XC3S400AN
XC3S700AN
XC3S1400AN
Notes:
1. Typical values can vary with process and other conditions.
2. XC3S700AN T maximum is 50 ms for Flash devices manufactured using the UMC process. For more information, see the Xilinx customer
PE
notice XCN14003: Flash Wafer Fabrication Change and Gold (Au) To Copper (Cu) Transition for Spartan-3AN FPGA Devices.
3. XC3S700AN T
maximum is 55 ms for Flash devices manufactured using the UMC process. For more information, see the Xilinx
PEP
customer notice XCN14003: Flash Wafer Fabrication Change and Gold (Au) To Copper (Cu) Transition for Spartan-3AN FPGA
Devices.
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58
Spartan-3AN FPGA Family: DC and Switching Characteristics
Suspend Mode Timing
X-Ref Target - Figure 12
Entering Suspend Mode
SUSPEND Input
Exiting Suspend Mode
sw_gwe_cycle
sw_gts_cycle
tSUSPENDHIGH_AWAKE
tSUSPENDLOW_AWAKE
AWAKE Output
tAWAKE_GWE
tSUSPEND_GWE
Flip-Flops, Block RAM,
Distributed RAM
Write Protected
tAWAKE_GTS
tSUSPEND_GTS
FPGA Outputs
Defined by SUSPEND constraint
tSUSPEND_DISABLE tSUSPEND_ENABLE
FPGA Inputs,
Interconnect
Blocked
DS610-3_08_061207
Figure 12: Suspend Mode Timing
Table 49: Suspend Mode Timing Parameters
Symbol
Description
Min
Typ
Max Units
Entering Suspend Mode
TSUSPENDHIGH_AWAKE Rising edge of SUSPEND pin to falling edge of AWAKE pin without glitch filter
–
7
–
+600
–
ns
ns
ns
ns
ns
(suspend_filter:No)
TSUSPENDFILTER
Adjustment to SUSPEND pin rising edge parameters when glitch filter enabled +160
(suspend_filter:Yes)
+300
10
TSUSPEND_GTS
Rising edge of SUSPEND pin until FPGA output pins drive their defined
SUSPEND constraint behavior
–
–
–
TSUSPEND_GWE
Rising edge of SUSPEND pin to write-protect lock on all writable clocked
elements
< 5
–
TSUSPEND_DISABLE
Rising edge of the SUSPEND pin to FPGA input pins and interconnect
disabled
340
–
Exiting Suspend Mode
TSUSPENDLOW_AWAKE Falling edge of the SUSPEND pin to rising edge of the AWAKE pin
Does not include DCM lock time
–
–
–
–
–
–
4 to 108
–
–
–
–
–
–
µs
µs
ns
µs
ns
µs
TSUSPEND_ENABLE
TAWAKE_GWE1
TAWAKE_GWE512
TAWAKE_GTS1
Falling edge of the SUSPEND pin to FPGA input pins and interconnect
re-enabled
3.7 to 109
Rising edge of the AWAKE pin until write-protect lock released on all writable
clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:1
67
14
57
14
Rising edge of the AWAKE pin until write-protect lock released on all writable
clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:512
Rising edge of the AWAKE pin until outputs return to the behavior described
in the FPGA application, using sw_clk:InternalClock and sw_gts_cycle:1
TAWAKE_GTS512
Rising edge of the AWAKE pin until outputs return to the behavior described
in the FPGA application, using sw_clk:InternalClock and sw_gts_cycle:512
Notes:
1. These parameters based on characterization.
2. For information on using the Spartan-3AN Suspend feature, see XAPP480: Using Suspend Mode in Spartan-3 Generation FPGAs.
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Configuration and JTAG Timing
General Configuration Power-On/Reconfigure Timing
X-Ref Target - Figure 13
1.2V
3.3V
V
CCINT
1.0V
2.0V
2.0V
(Supply)
V
CCAUX
(Supply)
2.5V
or
3.3V
V
Bank 2
(Supply)
CCO
TPOR
PROG_B
(Input)
TPL
TPROG
INIT_B
(Open-Drain)
TICCK
CCLK
(Output)
DS557-3_01_052908
Notes:
1. When configuring from the In-System Flash, V
must be in the recommended operating range; on power-up make
CCAUX
sure V
reaches at least 3.0V before INIT_B goes High to indicate the start of configuration. V
, V
, and
CCAUX
CCINT CCAUX
V
supplies to the FPGA can be applied in any order if this requirement is met.
CCO
2. The Low-going pulse on PROG_B is optional after power-on but necessary for reconfiguration without a power cycle.
3. The rising edge of INIT_B samples the voltage levels applied to the mode pins (M0 - M2).
Figure 13: Waveforms for Power-On and the Beginning of Configuration
Table 50: Power-On Timing and the Beginning of Configuration
All Speed Grades
Symbol
Description
Device
Units
Min
Max
(2)
TPOR
The time from the application of VCCINT, VCCAUX, and VCCO All
Bank 2 supply voltage ramps (whichever occurs last) to the
rising transition of the INIT_B pin
–
18
ms
TPROG
The width of the low-going pulse on the PROG_B pin
All
0.5
–
–
0.5
0.5
1
µs
ms
ms
ms
ms
ms
ns
(2)
TPL
The time from the rising edge of the PROG_B pin to the
rising transition on the INIT_B pin
XC3S50AN
XC3S200AN
XC3S400AN
XC3S700AN
XC3S1400AN
All
–
–
–
2
–
2
TINIT
Minimum Low pulse width on INIT_B output
250
0.5
–
(3)
TICCK
The time from the rising edge of the INIT_B pin to the
generation of the configuration clock signal at the CCLK
output pin
All
4
µs
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 10. This means power must be applied to all V
, V
,
CCINT CCO
and V
lines.
CCAUX
2. Power-on reset and the clearing of configuration memory occurs during this period.
3. This specification applies only to the Master Serial, SPI, and BPI modes.
4. For details on configuration, see UG332 Spartan-3 Generation Configuration User Guide.
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Configuration Clock (CCLK) Characteristics
Table 51: Master Mode CCLK Output Period by ConfigRate Option Setting
ConfigRate
Temperature
Range
Symbol
TCCLK1
Description
Minimum
Maximum
Units
Setting(1)
CCLK clock period by
ConfigRate setting
Commercial
Industrial
1,254
1,180
413
390
207
195
178
168
156
147
123
116
103
97
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
2,500
(power-on value)
Commercial
Industrial
TCCLK3
3
833
417
357
313
250
208
192
147
114
100
93
Commercial
Industrial
6
TCCLK6
(default)
Commercial
Industrial
TCCLK7
7
8
Commercial
Industrial
TCCLK8
Commercial
Industrial
TCCLK10
TCCLK12
TCCLK13
TCCLK17
TCCLK22
TCCLK25
TCCLK27
TCCLK33
TCCLK44
TCCLK50
10
12
13
17
22
25
27
33
44
50
100
Commercial
Industrial
Commercial
Industrial
93
88
Commercial
Industrial
72
68
Commercial
Industrial
54
51
Commercial
Industrial
47
45
Commercial
Industrial
44
42
Commercial
Industrial
36
76
34
Commercial
Industrial
26
57
25
Commercial
Industrial
22
50
21
Commercial
Industrial
11.2
10.6
TCCLK100
25
Notes:
1. Set the ConfigRate option value when generating a configuration bitstream.
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 52: Master Mode CCLK Output Frequency by ConfigRate Option Setting
ConfigRate
Temperature
Range
Symbol
FCCLK1
Description
Minimum
Maximum
Units
Setting
Equivalent CCLK clock frequency
by ConfigRate setting
Commercial
Industrial
0.797
0.847
2.42
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
1
0.400
(power-on value)
Commercial
Industrial
FCCLK3
3
1.20
2.40
2.57
Commercial
Industrial
4.83
6
FCCLK6
(default)
5.13
Commercial
Industrial
5.61
FCCLK7
7
8
2.80
5.96
Commercial
Industrial
6.41
FCCLK8
3.20
6.81
Commercial
Industrial
8.12
FCCLK10
FCCLK12
FCCLK13
FCCLK17
FCCLK22
FCCLK25
FCCLK27
FCCLK33
FCCLK44
FCCLK50
FCCLK100
10
12
13
17
22
25
27
33
44
50
100
4.00
8.63
Commercial
Industrial
9.70
4.80
10.31
10.69
11.37
13.74
14.61
18.44
19.61
20.90
22.23
22.39
23.81
27.48
29.23
37.60
40.00
44.80
47.66
88.68
94.34
Commercial
Industrial
5.20
Commercial
Industrial
6.80
Commercial
Industrial
8.80
Commercial
Industrial
10.00
10.80
13.20
17.60
20.00
40.00
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Table 53: Master Mode CCLK Output Minimum Low and High Time
ConfigRate Setting
12 13 17 22
Commercial 595 196 98.3 84.5 74.1 58.4 48.9 44.1 34.2 25.6 22.3 20.9 17.1 12.3 10.4 5.3
Symbol
Description
Units
1
3
6
7
8
10
25
27
33
44
50 100
TMCCL,
TMCCH
Master Mode
CCLK
Minimum
ns
ns
LowandHigh Industrial 560 185 92.6 79.8 69.8 55.0 46.0 41.8 32.3 24.2 21.4 20.0 16.2 11.9 10.0 5.0
Time
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 54: Slave Mode CCLK Input Low and High Time
Symbol
Description
Min
Max
Units
TSCCL,
TSCCH
CCLK Low and High time
5
ns
∞
Master Serial and Slave Serial Mode Timing
X-Ref Target - Figure 14
PROG_B
(Input)
INIT_B
(Open-Drain)
TMCCH
TSCCH
TMCCL
TSCCL
CCLK
(Input/Output)
TDCC
1/FCCSER
TCCD
DIN
(Input)
Bit n+1
TCCO
Bit n
Bit 0
Bit 1
DOUT
(Output)
Bit n-63
Bit n-64
DS312-3_05_103105
Figure 14: Waveforms for Master Serial and Slave Serial Configuration
Table 55: Timing for the Master Serial and Slave Serial Configuration Modes
All Speed Grades
Slave/
Master
Symbol
Description
Units
Min
Max
Clock-to-Output Times
TCCO
The time from the falling transition on the CCLK pin to data appearing at the
DOUT pin
Both
Both
1.5
10
ns
Setup Times
TDCC
The time from the setup of data at the DIN pin to the rising transition at the
CCLK pin
7
–
–
ns
ns
Hold Times
TCCD
The time from the rising transition at the CCLK pin to the point when data is
last held at the DIN pin
Master
Slave
0
1.0
Clock Timing
TCCH
High pulse width at the CCLK input pin
Master
Slave
Master
Slave
Slave
See Table 53
See Table 54
See Table 53
See Table 54
100
TCCL
Low pulse width at the CCLK input pin
FCCSER
Frequency of the clock signal at the
CCLK input pin(2)
No bitstream compression
With bitstream compression
0
0
MHz
MHz
100
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 10.
2. For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz.
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Slave Parallel Mode Timing
X-Ref Target - Figure 15
PROG_B
(Input)
INIT_B
(Open-Drain)
TSMCSCC
TSMCCCS
CSI_B
(Input)
TSMCCW
TSMWCC
RDWR_B
(Input)
TMCCH
TSCCH
TMCCL
TSCCL
CCLK
(Input)
1/FCCPAR
TSMDCC
TSMCCD
D0 - D7
(Inputs)
Byte 0
Byte 1
Byte n
Byte n+1
DS529-3_02_051607
Notes:
1. It is possible to abort configuration by pulling CSI_B Low in a given CCLK cycle, then switching RDWR_B Low or High in any subsequent
cycle for which CSI_B remains Low. The RDWR_B pin asynchronously controls the driver impedance of the D0–D7 bus. When RDWR_B
switches High, be careful to avoid contention on the D0–D7 bus.
2. To pause configuration, pause CCLK instead of de-asserting CSI_B. See UG332, Chapter 7, section “Non-Continuous SelectMAP Data
Loading” for more details.
Figure 15: Waveforms for Slave Parallel Configuration
Table 56: Timing for the Slave Parallel Configuration Mode
All Speed Grades
Symbol
Description
Units
Min
Max
Setup Times
TSMDCC
The time from the setup of data at the D0-D7 pins to the rising transition at the CCLK pin
Setup time on the CSI_B pin before the rising transition at the CCLK pin
Setup time on the RDWR_B pin before the rising transition at the CCLK pin
7
7
–
–
–
ns
ns
ns
TSMCSCC
(2)
TSMCCW
15
Hold Times
TSMCCD
The time from the rising transition at the CCLK pin to the point when data is last held at
the D0-D7 pins
1.0
0
–
–
–
ns
ns
ns
TSMCCCS
TSMWCC
The time from the rising transition at the CCLK pin to the point when a logic level is last
held at the CSO_B pin
The time from the rising transition at the CCLK pin to the point when a logic level is last
held at the RDWR_B pin
0
Clock Timing
TCCH
The High pulse width at the CCLK input pin
5
5
0
0
–
–
ns
ns
TCCL
The Low pulse width at the CCLK input pin
FCCPAR
Frequency of the clock signal No bitstream compression
80
80
MHz
MHz
at the CCLK input pin
With bitstream compression
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 10.
2. Some Xilinx documents refer to Parallel modes as SelectMAP modes.
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Spartan-3AN FPGA Family: DC and Switching Characteristics
External Serial Peripheral Interface (SPI) Configuration Timing
X-Ref Target - Figure 16
PROG_B
(Input)
PUDC_B
PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process.
(Input)
VS[2:0]
(Input)
<1:1:1>
Mode input pins M[2:0] and variant select input pins VS[2:0] are sampled when INIT_B
goes High. After this point, input values do not matter until DONE goes High, at which
point these pins become user-I/O pins.
<0:0:1>
M[2:0]
(Input)
TMINIT
TINITM
INIT_B
(Open-Drain)
New ConfigRate active
TCCLK
TMCCH
T
n
MCCL
n
TMCCL1 TMCCH1
T
TCCLK1
CCLK1
n
CCLK
TV
DIN
Data
Data
TDCC
Data
Data
(Input)
TCSS
TCCD
CSO_B
MOSI
TCCO
Command Command
(msb) (msb-1)
TDSU
TDH
Pin initially pulled High by internal pull-up resistor if PUDC_B input is Low.
Pin initially high-impedance (Hi-Z) if PUDC_B input is High. External pull-up resistor required on CSO_B.
DS529-3_06_102506
Shaded values indicate specifications on attached SPI Flash PROM.
Figure 16: Waveforms for External Serial Peripheral Interface (SPI) Configuration
Table 57: Timing for External Serial Peripheral Interface (SPI) Configuration Mode
Symbol
TCCLK1
TCCLKn
TMINIT
Description
Minimum
Maximum
See Table 51
See Table 51
–
Units
Initial CCLK clock period
CCLK clock period after FPGA loads ConfigRate bitstream option setting
Setup time on VS[2:0] variant-select pins and M[2:0] mode pins before the
rising edge of INIT_B
50
0
ns
ns
TINITM
Hold time on VS[2:0] variant-select pins and M[2:0] mode pins after the
rising edge of INIT_B
–
TCCO
TDCC
TCCD
MOSI output valid delay after CCLK falling clock edge
See Table 55
See Table 55
See Table 55
Setup time on the DIN data input before CCLK rising clock edge
Hold time on the DIN data input after CCLK rising clock edge
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 58: Configuration Timing Requirements for Attached SPI Serial Flash
Symbol Description
TCCS SPI serial Flash PROM chip-select time
Requirement
Units
ns
T
T
≤ T
≤ T
– T
CCS
MCCL1
MCCL1
CCO
CCO
TDSU
TDH
SPI serial Flash PROM data input setup time
SPI serial Flash PROM data input hold time
SPI serial Flash PROM data clock-to-output time
ns
ns
– T
DSU
T
≤ T
DH
MCCH1
TV
ns
T
≤ T
– T
MCCLn DCC
V
fC or fR
Maximum SPI serial Flash PROM clock frequency (also depends on
specific read command used)
MHz
1
f
≥ ---------------------------------
C
T
CCLKn(min)
Notes:
1. These requirements are for successful FPGA configuration in SPI mode, where the FPGA generates the CCLK signal. The
post-configuration timing can be different to support the specific needs of the application loaded into the FPGA.
2. Subtract additional printed circuit board routing delay as required by the application.
Byte Peripheral Interface (BPI) Configuration Timing
X-Ref Target - Figure 17
PROG_B
(Input)
PUDC_B
(Input)
PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process.
Mode input pins M[2:0] are sampled when INIT_B goes High. After this point,
input values do not matter until DONE goes High, at which point the mode pins
become user-I/O pins.
M[2:0]
(Input)
<0:1:0>
TMINIT
TINITM
INIT_B
(Open-Drain)
Pin initially pulled High by internal pull-up resistor if PUDC_B input is Low.
Pin initially high-impedance (Hi-Z) if PUDC_B input is High.
LDC[2:0]
HDC
CSO_B
New ConfigRate active
TCCLK1
TCCLKn
TINITADDR
TCCLK1
CCLK
TCCO
000_0000
Byte 0
Address
Address Address
TCCD
A[25:0]
000_0001
Byte 1
T
AVQV
TDCC
Data
D[7:0]
(Input)
Data
Data
Data
Shaded values indicate specifications on attached parallel NOR Flash PROM.
DS557-3_16_032009
Figure 17: Waveforms for Byte-wide Peripheral Interface (BPI) Configuration
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 59: Timing for Byte-wide Peripheral Interface (BPI) Configuration Mode
Symbol
TCCLK1
TCCLKn
TMINIT
Description
Minimum
Maximum
Units
Initial CCLK clock period
See Table 51
CCLK clock period after FPGA loads ConfigRate setting
Setup time on M[2:0] mode pins before the rising edge of INIT_B
Hold time on M[2:0] mode pins after the rising edge of INIT_B
See Table 51
50
0
–
–
5
ns
ns
TINITM
TINITADDR
Minimum period of initial A[25:0] address cycle; LDC[2:0] and HDC are asserted
and valid
5
TCCLK1
cycles
TCCO
TDCC
TCCD
Address A[25:0] outputs valid after CCLK falling edge
Setup time on D[7:0] data inputs before CCLK rising edge
Hold time on D[7:0] data inputs after CCLK rising edge
See Table 55
See TSMDCC in Table 56
–
0
ns
Table 60: Configuration Timing Requirements for Attached Parallel NOR Flash
Symbol
TCE
(tELQV
TOE
(tGLQV
TACC
(tAVQV
TBYTE
(tFLQV, FHQV
Notes:
Description
Requirement
Units
Parallel NOR Flash PROM chip-select time
ns
T
T
≤ T
CE
INITADDR
)
Parallel NOR Flash PROM output-enable time
Parallel NOR Flash PROM read access time
For x8/x16 PROMs only: BYTE# to output valid time(3)
ns
ns
ns
≤ T
OE
INITADDR
)
T
≤ 0.5T
– T
– T
– PCB
DCC
ACC
CCLKn(min)
CCO
)
T
≤ T
INITADDR
BYTE
t
)
1. These requirements are for successful FPGA configuration in BPI mode, where the FPGA generates the CCLK signal. The
post-configuration timing can be different to support the specific needs of the application loaded into the FPGA.
2. Subtract additional printed circuit board routing delay as required by the application.
3. The initial BYTE# timing can be extended using an external, appropriately sized pull-down resistor on the FPGA’s LDC2 pin. The resistor
value also depends on whether the FPGA’s PUDC_B pin is High or Low.
IEEE 1149.1/1532 JTAG Test Access Port Timing
X-Ref Target - Figure 18
TCCH
TCCL
TCK
(Input)
1/FTCK
TTCKTMS
TTMSTCK
TMS
(Input)
TTDITCK
TTCKTDI
TDI
(Input)
TTCKTDO
TDO
(Output)
DS557_13_083110
Figure 18: JTAG Waveforms
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Spartan-3AN FPGA Family: DC and Switching Characteristics
(2)
Table 61: Timing for the JTAG Test Access Port
All Speed
Grades
Symbol
Description
Units
Min
Max
11.0
–
Clock-to-Output Times
TTCKTDO The time from the falling transition on the TCK pin to data appearing at the TDO pin
1.0
ns
ns
Setup Times
TTDITCK The time from the setup of data at the All devices and functions except those shown below
TDI pin to the rising transition at the
7.0
Boundary-Scan commands (INTEST, EXTEST,
TCK pin
11.0
SAMPLE) on XC3S700AN and XC3S1400AN FPGAs
TTMSTCK The time from the setup of a logic level at the TMS pin to the rising transition at the TCK pin
Hold Times
7.0
–
–
ns
ns
TTCKTDI The time from the rising transition at
the TCK pin to the point when data is
last held at the TDI pin
All functions except those shown below
0
Configuration commands (CFG_IN, ISC_PROGRAM)
2.0
TTCKTMS The time from the rising transition at the TCK pin to the point when a logic level is last held at the
TMS pin
0
–
ns
Clock Timing
TCCH
TCCL
The High pulse width at the TCK pin All functions except ISC_DNA command
The Low pulse width at the TCK pin
5
5
–
–
ns
ns
TCCHDNA The High pulse width at the TCK pin During ISC_DNA command
TCCLDNA The Low pulse width at the TCK pin
10
10
0
10,000
10,000
33
ns
ns
FTCK
Frequency of the TCK signal
All operations on XC3S50AN, XC3S200AN, and
XC3S400AN FPGAs and for BYPASS or HIGHZ
instructions on all FPGAs
MHz
All operations on XC3S700AN and XC3S1400AN
FPGAs, except for BYPASS or HIGHZ instructions
20
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 10.
2. For details on JTAG, see Chapter 9, “JTAG Configuration Mode and Boundary-Scan” in UG332 Spartan-3 Generation Configuration User
Guide.
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revision
02/26/2007
08/16/2007
Initial release.
2.0
Updated for Production release of initial device (XC3S200AN). Timing specifications updated for v1.38
speed files. DC specifications updated with production values. Other changes throughout.
08/31/2007
09/12/2007
09/24/2007
2.0.1
2.0.2
2.1
Updated for Production release of XC3S1400AN. Improved tPEP for XC3S700AN in Table 48.
Updated for Production release of XC3S700AN.
Updated for Production release of XC3S400AN. Updated Software Version Requirements to note that
Production speed files are available as of Service Pack 3. Removed PCIX IOSTANDARD due to limited
PCIX interface support. Added note that SPI_ACCESS (In-System Flash) is not currently supported in
simulation.
12/12/2007
06/02/2008
3.0
3.1
Updated to Production status with Production release of final family member, XC3S50AN. Noted that
SPI_ACCESS simulation is supported in ISE 10.1 software. Removed DNA_RETENTION limit of 10
years in Table 17 since number of Read cycles is the only unique limit. Updated Setup, Hold, and
Propagation Times for the IOB Input Path to show values by device in Table 23 and Table 25. Increased
SSO recommendation for SSTL18_II in Table 32. Updated Figure 17 and Table 59 to show BPI data
synchronous to CCLK rising edge. Updated links.
Improved VCCAUXT and VCCO2T POR minimum in Table 7 and updated VCCO POR levels in Figure 13.
Clarified power sequencing in Note 1 of Table 7, Table 8, and Figure 13. Added VIN to Recommended
Operating Conditions in Table 10 and added reference to XAPP459, “Eliminating I/O Coupling Effects
when Interfacing Large-Swing Single-Ended Signals to User I/O Pins.” Reduced typical ICCINTQ and
I
CCAUXQ quiescent current values by 12%-58% in Table 12. Noted latest speed file v1.39 in ISE 10.1
software in Table 19. Added reference to Sample Window in Table 24. Changed Internal SPI interface
max frequency to 50 MHz and updated other Internal SPI timing parameters to match names and
values from speed file in Table 47. Restored Units column to Table 49. Updated CCLK output maximum
period in Table 51 to match minimum frequency in Table 52. Added references to User Guides.
11/19/2009
3.2
Updated selected I/O standard DC characteristics. Changed typical quiescent current temperature
from ambient to junction. Removed references to older software versions. Updated column 3 header
of Table 17 and Table 18. Added table note to Table 18. Added TIOPI and TIOPID propagation times in
Table 25. Updated TIOCKHZ and TIOCKON synchronous output enable/disable times in Table 28.
Removed VREF requirements for differential HSTL and differential SSTL in Table 30. Improved
DIFF_SSTL18_II SSO limits in Table 32. Updated table note 3 in Table 39. Removed references to old
software versions from Table 47 and Table 48. Added description of spread spectrum in Spread
Spectrum section. Updated BPI configuration waveforms in Figure 17. Updated TACC equation in
Table 60.
12/02/2010
4.0
Added IIK to Table 6. Updated VIN in Table 10 and added a footnote to IL in Table 11 to note potential
leakage between pins of a differential pair. Added note 6 to Table 13. Corrected CLK High and Low
Time symbol in Table 46. Corrected symbols for TSUSPEND_GTS and TSUSPEND_GWE in Table 49.
Updated link to sign up for Alerts and updated Notice of Disclaimer.
04/01/2011
06/11/2014
4.1
4.2
In Table 31, added the equivalent pairs per bank for the XC3S50AN and XC3S400AN in the FT(G)256
package and the XC3S1400AN in the FG(G)484 package.
Clarified and updated the maximum description in Table 24.
Added Note 1, Note 2, and Note 3 to Table 48. These changes are outlined in the customer notice
XCN14003: Flash Wafer Fabrication Change and Gold (Au) To Copper (Cu) Transition for Spartan-3AN
FPGA Devices.
Xilinx has issued a discontinuation notice for the XC3S50AN in the FT(G)256 package and the
XC3S1400AN in the FG(G)484 package. See XCN13016: Product Discontinuation Notice For
Selected Spartan-3AN FPGA Products. Updated Notice of Disclaimer.
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Spartan-3AN FPGA Family: DC and Switching Characteristics
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VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN
THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III)
USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY
USE OF XILINX PRODUCTS IN SUCH APPLICATIONS.
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5
123
Spartan-3AN FPGA Family:
Pinout Descriptions
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Introduction
This section describes how the various pins on a Spartan®-3AN FPGA connect within the supported component packages,
and provides device-specific thermal characteristics. For general information on the pin functions and the package
characteristics, see the Packaging section of UG331:
•
UG331: Spartan-3 Generation FPGA User Guide
http://www.xilinx.com/support/documentation/user_guides/ug331.pdf
Spartan-3AN FPGAs are available in Pb-free, RoHS packages, indicated by a “G” in the middle of the package code. Leaded
(Pb) packages are available for selected devices, with the same pinout and without the “G” in the ordering code (see Table 5,
page 7). The Pb-free package code can be selected in the software for the Pb packages since the pinouts are identical.
References to the Pb-free package code in this document apply also to the Pb package.
Pin Types
Most pins on a Spartan-3AN FPGA are general-purpose, user-defined I/O pins. There are, however, up to 12 different
functional types of pins on Spartan-3AN FPGA packages, as outlined in Table 62. In the package footprint drawings that
follow, the individual pins are color-coded according to pin type as in the table.
Table 62: Types of Pins on Spartan-3AN FPGAs
Type with
Color Code
Pin Name(s) in
Type(1)
Description
Unrestricted, general-purpose user-I/O pin. Most pins can be paired together to form differential IO_#
I/O
I/Os.
IO_Lxxy_#
Unrestricted, general-purpose input-only pin. This pin does not have an output structure,
differential termination resistor, or PCI™ clamp diode.
IP_#
IP_Lxxy_#
INPUT
Dual-purpose pin used in some configuration modes during the configuration process and then M[2:0]
usually available as a user I/O after configuration. If the pin is not used during configuration, this PUDC_B
pin behaves as an I/O-type pin. See UG332: Spartan-3 Generation Configuration User Guide for CCLK
additional information on these signals.
MOSI/CSI_B
D[7:1]
D0/DIN
DOUT
DUAL
CSO_B
RDWR_B
INIT_B
A[25:0]
VS[2:0]
LDC[2:0]
HDC
Dual-purpose pin that is either a user-I/O pin or Input-only pin, or, along with all other VREF pins IP/VREF_#
in the same bank, provides a reference voltage input for certain I/O standards. If used for a
reference voltage within a bank, all VREF pins within the bank must be connected.
IP_Lxx_#/VREF_#
IO/VREF_#
IO_Lxx_#/VREF_#
VREF
CLK
Either a user-I/O pin or an input to a specific clock buffer driver. Most packages have 16 global IO_Lxx_#/GCLK[15:0],
clock inputs that optionally clock the entire device. The exceptions are all devices in the TQG144 IO_Lxx_#/LHCLK[7:0],
package and the XC3S50AN in the FTG256 package. The RHCLK inputs optionally clock the
right half of the device. The LHCLK inputs optionally clock the left half of the device. See the
Using Global Clock Resources chapter in UG331: Spartan-3 Generation FPGA User Guide for
additional information on these signals.
IO_Lxx_#/RHCLK[7:0]
© Copyright 2007–2014 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
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Spartan-3AN FPGA Family: Pinout Descriptions
Table 62: Types of Pins on Spartan-3AN FPGAs (Cont’d)
Type with
Description
Color Code
Pin Name(s) in
Type(1)
Dedicated configuration pin, two per device. Not available as a user-I/O pin. Every package has DONE, PROG_B
two dedicated configuration pins. These pins are powered by VCCAUX. See UG332: Spartan-3
Generation Configuration User Guide for additional information on the DONE and PROG_B
signals.
CONFIG
Control and status pins for the power-saving Suspend mode. SUSPEND is a dedicated pin and SUSPEND, AWAKE
is powered by VCCAUX. AWAKE is a dual-purpose pin. Unless Suspend mode is enabled in the
application, AWAKE is available as a user-I/O pin.
PWR
MGMT
Dedicated JTAG pin - 4 per device. Not available as a user-I/O pin. Every package has four
dedicated JTAG pins. These pins are powered by VCCAUX.
TDI, TMS, TCK, TDO
JTAG
GND
Dedicated ground pin. The number of GND pins depends on the package used. All must be
connected.
GND
Dedicated auxiliary power supply pin. The number of VCCAUX pins depends on the package
used. The In-System Flash memory is powered by VCCAUX. All must be connected to +3.3V.
VCCAUX
VCCAUX
VCCINT
Dedicated internal core logic power supply pin. The number of VCCINT pins depends on the
package used. All must be connected to +1.2V.
VCCINT
Along with all the other VCCO pins in the same bank, this pin supplies power to the output buffers VCCO_#
within the I/O bank and sets the input threshold voltage for some I/O standards. All must be
connected.
VCCO
N.C.
This package pin is not connected in this specific device/package combination.
N.C.
Notes:
1. # = I/O bank number, an integer between 0 and 3.
Package Pins by Type
Each package has three separate voltage supply inputs—VCCINT, VCCAUX, and VCCO—and a common ground return,
GND. The numbers of pins dedicated to these functions vary by package, as shown in Table 63.
Table 63: Power and Ground Supply Pins by Package
Package
TQG144
FTG256
FGG400
FGG484
FGG676
VCCINT
VCCAUX
VCCO
8
GND
13
4
6
4
4
16
28
9
8
22
43
15
23
10
14
24
53
36
77
A majority of package pins are user-defined I/O or input pins. However, the numbers and characteristics of these I/Os
depend on the device type and the package in which it is available, as shown in Table 64. The table shows the maximum
number of single-ended I/O pins available, assuming that all I/O-, INPUT-, DUAL-, VREF-, and CLK-type pins are used as
general-purpose I/O. AWAKE is counted here as a dual-purpose I/O pin. Likewise, the table shows the maximum number of
differential pin-pairs available on the package. Finally, the table shows how the total maximum user-I/Os are distributed by
pin type, including the number of unconnected—N.C.—pins on the device.
Not all I/O standards are supported on all I/O banks. The left and right banks (I/O banks 1 and 3) support higher output drive
current than the top and bottom banks (I/O banks 0 and 2). Similarly, true differential output standards, such as LVDS,
RSDS, PPDS, miniLVDS, and TMDS, are only supported in the top or bottom banks (I/O banks 0 and 2). Inputs are
unrestricted. For more details, see the “Using I/O Resources” chapter in UG331.
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All Possible I/Os by Type
Table 64: Maximum User I/O by Package
Maximum
Maximum Maximum
User I/Os
and
Device
Package
Input-
Only
Differential
Pairs
I/O
INPUT
DUAL VREF (1)
CLK
N.C.
Input-Only
TQG144
FTG256(2)
FTG256
108
144
195
195
311
372
375
502
7
50
64
42
53
2
26
26
52
52
52
52
52
52
8
30
30
32
32
32
32
32
32
0
51
0
XC3S50AN
32
35
35
63
84
87
94
20
21
21
46
61
62
67
15
21
21
26
33
34
38
XC3S200AN
XC3S400AN
XC3S700AN
XC3S1400AN
90
69
FTG256
90
69
0
FGG400
FGG484
FGG484(2)
FGG676
142
165
165
227
155
194
195
313
0
3
0
17
Notes:
1. Some VREFs are on INPUT pins. See pinout tables for details.
2. Xilinx has issued a discontinuation notice for these highlighted devices/packages. For more information see XCN13016: Product
Discontinuation Notice For Selected Spartan-3AN FPGA Products.
Electronic versions of the package pinout tables and foot-prints are available for download from the Xilinx website at:
http://www.xilinx.com/support/documentation/data_sheets/s3a_pin.zip
Using a spreadsheet program, the data can be sorted and reformatted according to any specific needs. Similarly, the
ASCII-text file is easily parsed by most scripting programs.
Package Overview
Table 65 shows the five low-cost, space-saving production package styles for the Spartan-3AN family.
Table 65: Spartan-3AN Family Package Options
Lead Pitch
(mm)
Body Area
(mm)
Height
(mm)
Package
Leads
Type
Maximum I/Os
TQ144/TQG144
FT256/FTG256
FG400/FGG400
FG484/FGG484
FG676/FGG676
144
256
400
484
676
Thin Quad Flat Pack (TQFP)
108
195
311
375
502
0.5
1.0
1.0
1.0
1.0
20 x 20
17 x 17
21 x 21
23 x 23
27 x 27
1.60
1.55
2.43
2.60
2.60
Fine-pitch Thin Ball Grid Array (FBGA)
Fine-pitch Ball Grid Array (FBGA)
Fine-pitch Ball Grid Array (FBGA)
Fine-pitch Ball Grid Array (FBGA)
Notes:
1. For mass, refer to the MDDS files (see Table 66).
Each package style is available in an environmentally friendly lead-free (Pb-free) option. The Pb-free packages include an
extra “G” in the package style name. For example, the standard “CS484” package becomes “CSG484” when ordered as the
Pb-free option. Leaded (Pb) packages are available for selected devices, with the same pinout and without the “G” in the
ordering code; See Table 5, page 7 for more information. The mechanical dimensions of the Pb and Pb-free packages are
similar, as shown in the mechanical drawings provided in Table 66.
For additional package information, see UG112: Device Package User Guide.
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Mechanical Drawings
Detailed mechanical drawings for each package type are available from the Xilinx website at the specified location in
Table 66. Material Declaration Data Sheets (MDDS) are also available on the Xilinx website for each package.
Table 66: Xilinx Package Documentation
Package
TQ144
Drawing
MDDS
Package Drawing
PK169_TQ144
PK461_TQG144
PK158_FT256
PK424_FTG256
PK182_FG400
PK108_FGG400
PK183_FG484
PK110_FGG484
PK155_FG676
PK394_FGG676
TQG144
FT256
Package Drawing
Package Drawing
Package Drawing
Package Drawing
FTG256
FG400
FGG400
FG484
FGG484
FG676
FGG676
Package Thermal Characteristics
The power dissipated by an FPGA application has implications on package selection and system design. The power
consumed by a Spartan-3AN FPGA is reported using either the Xilinx Power Estimator or the Xilinx Power Analyzer
calculator integrated in the Xilinx® ISE® development software. Table 67 provides the thermal characteristics for the various
Spartan-3AN FPGA packages. This information is also available using the Thermal Query tool at
http://www.xilinx.com/cgi-bin/thermal/thermal.pl.
The junction-to-case thermal resistance (θ ) indicates the difference between the temperature measured on the package
JC
body (case) and the junction temperature per watt of power consumption. The junction-to-board (θ ) value similarly reports
JB
the difference between the board and junction temperature. The junction-to-ambient (θ ) value reports the temperature
JA
difference between the ambient environment and the junction temperature. The θ value is reported at different air
JA
velocities, measured in linear feet per minute (LFM). The “Still Air (0 LFM)” column shows the θ value in a system without
JA
a fan. The thermal resistance drops with increasing air flow.
Table 67: Spartan-3AN FPGA Package Thermal Characteristics
Junction-to-Ambient (θJA
)
at Different Air Flows
Junction-to-Case Junction-to-Board
(θJC (θJB
Device
Package(1)
Units
)
)
Still Air
(0 LFM)
250 LFM 500 LFM 750 LFM
TQG144
FTG256(3)
FTG256
13.4
32.8
38.9
32.8
32.5
31.7
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
XC3S50AN
XC3S200AN
XC3S400AN
XC3S700AN
XC3S1400AN
7.4
5.9
6.2
5.3
23.3
13.6
12.9
11.5
29.0
25.9
22.5
19.4
23.8
21.7
16.7
15.0
23.0
20.2
15.6
13.9
22.3
19.3
15.0
13.4
FTG256
FGG400
FGG484
FGG484(3)
FGG676
4.3
10.9
17.7
13.7
12.6
12.1
Notes:
1. Thermal characteristics are similar for leaded (non-Pb-free) packages.
2. Use the Thermal Query tool at http://www.xilinx.com/cgi-bin/thermal/thermal.pl for specific device information.
3. Xilinx has issued a discontinuation notice for these highlighted devices/packages. For more information see XCN13016: Product
Discontinuation Notice For Selected Spartan-3AN FPGA Products.
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TQG144: 144-lead Thin Quad Flat Package
The XC3S50AN is available in the 144-lead thin quad flat package, TQG144.
Table 68 lists all the package pins. They are sorted by bank number and then by pin name. Pins that form a differential I/O
pair appear together in the table. The table also shows the pin number for each pin and the pin type (as defined in Table 62).
The XC3S50AN does not support the address output pins for the Byte-wide Peripheral Interface (BPI) configuration mode.
An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at:
www.xilinx.com/support/documentation/data_sheets/s3a_pin.zip.
Pinout Table
Table 68: Spartan-3AN TQG144 Pinout (Cont’d)
Table 68: Spartan-3AN TQG144 Pinout
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
Pin Name
IO_L02P_1/LDC1
IO_L03N_1
Pin
P75
P84
P82
P85
P83
P88
P87
P92
P90
P93
P91
P98
P96
P101
P99
P104
P102
P105
P103
P80
P97
P86
P95
P62
P38
P37
P41
P39
P44
P42
P45
P43
P48
Type
DUAL
I/O
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
Pin Name
Pin
Type
I/O
IO_0
P142
P111
P110
P113
P112
P117
P115
P116
P114
P121
P120
P126
P124
P127
P125
P131
P129
P132
P130
P135
P134
P139
P138
P143
P141
P140
P123
P119
P136
P79
IO_L01N_0
I/O
IO_L03P_1
I/O
IO_L01P_0
I/O
IO_L04N_1/RHCLK1
IO_L04P_1/RHCLK0
IO_L05N_1/TRDY1/RHCLK3
IO_L05P_1/RHCLK2
IO_L06N_1/RHCLK5
IO_L06P_1/RHCLK4
IO_L07N_1/RHCLK7
IO_L07P_1/IRDY1/RHCLK6
IO_L08N_1
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
I/O
IO_L02N_0
I/O
IO_L02P_0/VREF_0
IO_L03N_0
VREF
I/O
IO_L03P_0
I/O
IO_L04N_0
I/O
IO_L04P_0
I/O
IO_L05N_0
I/O
IO_L05P_0
I/O
IO_L06N_0/GCLK5
IO_L06P_0/GCLK4
IO_L07N_0/GCLK7
IO_L07P_0/GCLK6
IO_L08N_0/GCLK9
IO_L08P_0/GCLK8
IO_L09N_0/GCLK11
IO_L09P_0/GCLK10
IO_L10N_0
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
I/O
IO_L08P_1
I/O
IO_L09N_1
I/O
IO_L09P_1
I/O
IO_L10N_1
I/O
IO_L10P_1
I/O
IO_L11N_1
I/O
IO_L11P_1
I/O
IP_1/VREF_1
VREF
VREF
VCCO
VCCO
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
IP_1/VREF_1
IO_L10P_0
I/O
VCCO_1
IO_L11N_0
I/O
VCCO_1
IO_L11P_0
I/O
IO_2/MOSI/CSI_B
IO_L01N_2/M0
IO_L01P_2/M1
IO_L02N_2/CSO_B
IO_L02P_2/M2
IO_L03N_2/VS1
IO_L03P_2/RDWR_B
IO_L04N_2/VS0
IO_L04P_2/VS2
IO_L05N_2/D7
IO_L12N_0/PUDC_B
IO_L12P_0/VREF_0
IP_0
DUAL
VREF
INPUT
VREF
VCCO
VCCO
I/O
IP_0/VREF_0
VCCO_0
VCCO_0
IO_1
IO_L01N_1/LDC2
IO_L01P_1/HDC
IO_L02N_1/LDC0
P78
DUAL
DUAL
DUAL
P76
P77
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Table 68: Spartan-3AN TQG144 Pinout (Cont’d)
Table 68: Spartan-3AN TQG144 Pinout (Cont’d)
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Name
IO_L05P_2
Pin
P46
P49
P47
P51
P50
P55
P54
P59
P57
P60
P58
P64
Type
I/O
Bank
3
Pin Name
IO_L11N_3
Pin
P30
P28
P32
P31
P35
P33
P14
P23
P9
Type
I/O
IO_L06N_2/D6
DUAL
I/O
3
IO_L11P_3
IO_L12N_3
IO_L12P_3
IP_L13N_3/VREF_3
IP_L13P_3
VCCO_3
VCCO_3
GND
I/O
IO_L06P_2
3
I/O
IO_L07N_2/D4
DUAL
DUAL
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
DUAL
3
I/O
IO_L07P_2/D5
3
VREF
INPUT
VCCO
VCCO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
IO_L08N_2/GCLK15
IO_L08P_2/GCLK14
IO_L09N_2/GCLK1
IO_L09P_2/GCLK0
IO_L10N_2/GCLK3
IO_L10P_2/GCLK2
IO_L11N_2/DOUT
IO_L11P_2/AWAKE
IO_L12N_2/D3
3
3
3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
P17
P26
P34
P56
P65
P81
P89
P100
P106
P118
P128
P137
GND
GND
P63 PWR MGMT
GND
P68
P67
P71
P69
P72
P70
P53
P40
P61
P6
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
VREF
VCCO
VCCO
I/O
GND
IO_L12P_2/INIT_B
IO_L13N_2/D0/DIN/MISO
IO_L13P_2/D2
GND
GND
GND
IO_L14N_2/CCLK
IO_L14P_2/D1
GND
GND
IP_2/VREF_2
GND
VCCO_2
GND
VCCO_2
VCCAUX SUSPEND
VCCAUX DONE
VCCAUX PROG_B
VCCAUX TCK
P74 PWR MGMT
IO_L01N_3
P73
P144
P109
P2
CONFIG
CONFIG
JTAG
IO_L01P_3
P4
I/O
IO_L02N_3
P5
I/O
IO_L02P_3
P3
I/O
VCCAUX TDI
JTAG
IO_L03N_3
P8
I/O
VCCAUX TDO
P107
P1
JTAG
IO_L03P_3
P7
I/O
VCCAUX TMS
JTAG
IO_L04N_3/VREF_3
IO_L04P_3
P11
P10
P13
P12
P16
P15
P20
P18
P21
P19
P25
P24
P29
P27
VREF
I/O
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
P36
P66
P108
P133
P22
P52
P94
P122
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
IO_L05N_3/LHCLK1
IO_L05P_3/LHCLK0
IO_L06N_3/IRDY2/LHCLK3
IO_L06P_3/LHCLK2
IO_L07N_3/LHCLK5
IO_L07P_3/LHCLK4
IO_L08N_3/LHCLK7
IO_L08P_3/TRDY2/LHCLK6
IO_L09N_3
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
I/O
IO_L09P_3
I/O
IO_L10N_3
I/O
IO_L10P_3
I/O
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User I/Os by Bank
Table 69 indicates how the 108 available user-I/O pins are distributed between the four I/O banks on the TQG144 package.
The AWAKE pin is counted as a dual-purpose I/O.
Table 69: User I/Os Per Bank for the XC3S50AN in the TQG144 Package
All Possible I/O Pins by Type
Package
Edge
I/O Bank
Maximum I/Os
I/O
14
11
2
INPUT
DUAL
VREF
CLK
8
Top
0
1
2
3
27
25
1
0
0
1
2
1
4
3
2
1
2
8
Right
Bottom
Left
8
30
21
0
6
26
15
42
8
Total
108
26
30
Footprint Migration Differences
The XC3S50AN FPGA is the only Spartan-3AN device offered in the TQG144 package. The XC3S50AN FPGA is pin
compatible with the Spartan-3A XC3S50A FPGA in the TQ(G)144 package, although the Spartan-3A FPGA requires an
external configuration source.
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Spartan-3AN FPGA Family: Pinout Descriptions
TQG144 Footprint
Note: Pin 1 indicator in top-left corner and logo orientation.
X-Ref Target - Figure 19
TMS
TDI
1
2
108 VCCAUX
107 TDO
Bank 0
IO_L02P_3
IO_L01P_3
IO_L02N_3
IO_L01N_3
IO_L03P_3
IO_L03N_3
GND
3
4
5
6
7
8
9
106 GND
105 IO_L11N_1
104 IO_L10N_1
103 IO_L11P_1
102 IO_L10P_1
101 IO_L09N_1
100 GND
IO_L04P_3 10
IO_L04N_3/VREF_3 11
IO_L05P_3/LHCLK0 12
IO_L05N_3/LHCLK1 13
VCCO_3 14
99 IO_L09P_1
98 IO_L08N_1
97 IP_1/VREF_1
96 IO_L08P_1
95 VCCO_1
IO_L06P_3/LHCLK2 15
IO_L06N_3/LHCLK3 16
GND 17
94 VCCINT
93 IO_L07N_1/RHCLK7
92 IO_L06N_1/RHCLK5
91 IO_L07P_1/RHCLK6
90 IO_L06P_1/RHCLK4
89 GND
IO_L07P_3/LHCLK4 18
IO_L08P_3/LHCLK6 19
IO_L07N_3/LHCLK5 20
IO_L08N_3/LHCLK7 21
VCCINT 22
88 IO_L05N_1/RHCLK3
87 IO_L05P_1/RHCLK2
86 VCCO_1
VCCO_3 23
IO_L09P_3 24
85 IO_L04N_1/RHCLK1
84 IO_L03N_1
IO_L09N_3 25
GND 26
83 IO_L04P_1/RHCLK0
82 IO_L03P_1
IO_L10P_3 27
IO_L11P_3 28
81 GND
IO_L10N_3 29
80 IP_1/VREF_1
79 IO_1
IO_L11N_3 30
IO_L12P_3 31
78 IO_L01N_1/LDC2
77 IO_L02N_1/LDC0
76 IO_L01P_1/HDC
75 IO_L02P_1/LDC1
IO_L12N_3 32
IP_L13P_3 33
GND 34
IP_L13N_3/VREF_3 35
VCCAUX 36
74
73
SUSPEND
Bank 2
DONE
DS529-4_10_031207
Figure 19: XC3S50AN FPGA in TQG144 Package Footprint (Top View)
I/O: Unrestricted, general-purpose
DUAL: Configuration pins, then
VREF: User I/O or input voltage
42
2
25
30
8
8
user I/O
possible user I/O
reference for bank
INPUT: Unrestricted,
general-purpose input pin
CLK: User I/O, input, or global
buffer input
VCCO: Output voltage supply for
bank
CONFIG: Dedicated configuration
JTAG: Dedicated JTAG port pins
GND: Ground
VCCINT: Internal core supply
2
0
4
4
4
pins
voltage (+1.2V)
N.C.: Not connected
VCCAUX: Auxiliary supply voltage
13
SUSPEND: Dedicated SUSPEND
and dual-purpose AWAKE Power
Management pins
2
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Spartan-3AN FPGA Family: Pinout Descriptions
FTG256: 256-Ball Fine-Pitch, Thin Ball Grid Array
Xilinx has issued a discontinuation notice for the XC3S50AN in the FT(G)256 package. See XCN13016: Product
Discontinuation Notice For Selected Spartan-3AN FPGA Products.
The 256-ball fine-pitch, thin ball grid array package, FTG256, supports the XC3S200AN and XC3S400AN devices. Table 70
lists all the package pins for these devices including the discontinued XC3S50AN. They are sorted by bank number and then
by the pin name of the largest device. Pins that form a differential I/O pair appear together in the table. The differential I/O
pairs that have different assignments between the XC3S50AN and the XC3S200AN or XC3S400AN are highlighted in light
blue in Table 70. See Footprint Migration Differences, page 87 for additional information. The table also shows the pin
number for each pin and the pin type (as defined in Table 62).
The footprints for the XC3S200AN and XC3S400AN in the FTG256 are identical. Figure 21 shows the common footprint for
the XC3S200AN and XC3S400AN. The discontinued XC3S50AN footprint is compatible with the XC3S200AN and
XC3S400AN, however, there are 51 unconnected balls (indicated as N.C. in Table 70).
Table 73 summarizes the discontinued XC3S50AN FPGA footprint migration differences for the FTG256 package.
The XC3S50AN does not support the address output pins for the byte-wide peripheral interface (BPI) configuration mode.
An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at:
www.xilinx.com/support/documentation/data_sheets/s3a_pin.zip.
Pinout Table
Table 70: Spartan-3AN FTG256 Pinout (XC3S50AN (Discontinued), XC3S200AN, XC3S400AN)
Bank
0
XC3S50AN Pin Name (Discontinued)
IO_L01N_0
XC3S200AN/XC3S400AN Pin Name
IO_L01N_0
FTG256 Ball
C13
D13
B14
B15
D11
C12
A13
A14
A12
B12
E10
D10
A11
C11
A10
B10
D9
Type
I/O
0
IO_L01P_0
IO_L01P_0
I/O
0
IO_L02N_0
IO_L02N_0
I/O
0
IO_L02P_0/VREF_0
IO_L03N_0
IO_L02P_0/VREF_0
IO_L03N_0
VREF
I/O
0
0
IO_L03P_0
IO_L03P_0
I/O
0
IO_L04N_0
IO_L04N_0
I/O
0
IO_L04P_0
IO_L04P_0
I/O
0
N.C.
IO_L05N_0
I/O
0
IP_0
IO_L05P_0
I/O
0
N.C.
IO_L06N_0/VREF_0
IO_L06P_0
VREF
I/O
0
N.C.
0
IO_L07N_0
IO_L07N_0
I/O
0
IO_L07P_0
IO_L07P_0
I/O
0
IO_L08N_0
IO_L08N_0
I/O
0
IO_L08P_0
IO_L08P_0
I/O
0
IO_L09N_0/GCLK5
IO_L09P_0/GCLK4
IO_L10N_0/GCLK7
IO_L10P_0/GCLK6
IO_L11N_0/GCLK9
IO_L11P_0/GCLK8
IO_L12N_0/GCLK11
IO_L12P_0/GCLK10
IO_L09N_0/GCLK5
IO_L09P_0/GCLK4
IO_L10N_0/GCLK7
IO_L10P_0/GCLK6
IO_L11N_0/GCLK9
IO_L11P_0/GCLK8
IO_L12N_0/GCLK11
IO_L12P_0/GCLK10
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
0
C10
A9
0
0
C9
0
D8
0
C8
0
B8
0
A8
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Table 70: Spartan-3AN FTG256 Pinout (XC3S50AN (Discontinued), XC3S200AN, XC3S400AN) (Cont’d)
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
XC3S50AN Pin Name (Discontinued)
N.C.
XC3S200AN/XC3S400AN Pin Name
IO_L13N_0
FTG256 Ball
C7
Type
I/O
N.C.
IO_L13P_0
A7
I/O
N.C.
IO_L14N_0/VREF_0
IO_L14P_0
E7
VREF
I/O
N.C.
F8
IO_L15N_0
IO_L15P_0
IO_L16N_0
IO_L16P_0
IO_L17N_0
IO_L17P_0
IO_L18N_0
IO_L18P_0
IO_L19N_0
IO_L19P_0
IO_L20N_0/PUDC_B
IO_L20P_0/VREF_0
IP_0
IO_L15N_0
B6
I/O
IO_L15P_0
A6
I/O
IO_L16N_0
C6
I/O
IO_L16P_0
D7
I/O
IO_L17N_0
C5
I/O
IO_L17P_0
A5
I/O
IO_L18N_0
B4
I/O
IO_L18P_0
A4
I/O
IO_L19N_0
B3
I/O
IO_L19P_0
A3
I/O
IO_L20N_0/PUDC_B
IO_L20P_0/VREF_0
IP_0
D5
DUAL
VREF
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VREF
VCCO
VCCO
VCCO
VCCO
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
VREF
I/O
C4
D6
IP_0
IP_0
D12
E6
IP_0
IP_0
IP_0
IP_0
F7
IP_0
IP_0
F9
IP_0
IP_0
F10
E9
IP_0/VREF_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
IO_L01N_1/LDC2
IO_L01P_1/HDC
IO_L02N_1/LDC0
IO_L02P_1/LDC1
IO_L03N_1
IO_L03P_1
N.C.
IP_0/VREF_0
VCCO_0
B5
VCCO_0
B9
VCCO_0
B13
E8
VCCO_0
IO_L01N_1/LDC2
IO_L01P_1/HDC
IO_L02N_1/LDC0
IO_L02P_1/LDC1
IO_L03N_1/A1
IO_L03P_1/A0
IO_L05N_1/VREF_1
IO_L05P_1
N14
N13
P15
R15
N16
P16
M14
M13
K13
L13
M16
M15
L16
N.C.
N.C.
IO_L06N_1/A3
IO_L06P_1/A2
IO_L07N_1/A5
IO_L07P_1/A4
IO_L08N_1/A7
DUAL
DUAL
DUAL
DUAL
DUAL
N.C.
N.C.
N.C.
N.C.
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Spartan-3AN FPGA Family: Pinout Descriptions
Table 70: Spartan-3AN FTG256 Pinout (XC3S50AN (Discontinued), XC3S200AN, XC3S400AN) (Cont’d)
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
XC3S50AN Pin Name (Discontinued)
N.C.
XC3S200AN/XC3S400AN Pin Name
IO_L08P_1/A6
FTG256 Ball
L14
Type
DUAL
DUAL
DUAL
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
VREF
INPUT
INPUT
VREF
INPUT
INPUT
INPUT
VREF
INPUT
VREF
VCCO
VCCO
VCCO
IO_L10N_1
IO_L10P_1
IO_L11N_1/RHCLK1
IO_L11P_1/RHCLK0
IO_L12N_1/TRDY1/RHCLK3
IO_L12P_1/RHCLK2
IO_L14N_1/RHCLK5
IO_L14P_1/RHCLK4
IO_L15N_1/RHCLK7
IO_L15P_1/IRDY1/RHCLK6
N.C.
IO_L10N_1/A9
J13
IO_L10P_1/A8
J12
IO_L11N_1/RHCLK1
IO_L11P_1/RHCLK0
IO_L12N_1/TRDY1/RHCLK3
IO_L12P_1/RHCLK2
IO_L14N_1/RHCLK5
IO_L14P_1/RHCLK4
IO_L15N_1/RHCLK7
IO_L15P_1/IRDY1/RHCLK6
IO_L16N_1/A11
IO_L16P_1/A10
IO_L17N_1/A13
IO_L17P_1/A12
IO_L18N_1/A15
IO_L18P_1/A14
IO_L19N_1/A17
IO_L19P_1/A16
IO_L20N_1/A19
IO_L20P_1/A18
IO_L22N_1/A21
IO_L22P_1/A20
IO_L23N_1/A23
IO_L23P_1/A22
IO_L24N_1/A25
IO_L24P_1/A24
IP_L04N_1/VREF_1
IP_L04P_1
K14
K15
J16
K16
H14
J14
H16
H15
F16
G16
G14
H13
F15
E16
F14
G13
F13
E14
D15
D16
D14
E13
C15
C16
K12
K11
J11
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
IO_L20N_1
IO_L20P_1
IO_L22N_1
IO_L22P_1
IO_L23N_1
IO_L23P_1
IO_L24N_1
IO_L24P_1
IP_L04N_1/VREF_1
IP_L04P_1
N.C.
IP_L09N_1
N.C.
IP_L09P_1/VREF_1
IP_L13N_1
J10
IP_L13N_1
H11
H10
G11
G12
F11
F12
E15
H12
J15
IP_L13P_1
IP_L13P_1
IP_L21N_1
IP_L21N_1
IP_L21P_1/VREF_1
IP_L25N_1
IP_L21P_1/VREF_1
IP_L25N_1
IP_L25P_1/VREF_1
VCCO_1
IP_L25P_1/VREF_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
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Spartan-3AN FPGA Family: Pinout Descriptions
Table 70: Spartan-3AN FTG256 Pinout (XC3S50AN (Discontinued), XC3S200AN, XC3S400AN) (Cont’d)
Bank
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
XC3S50AN Pin Name (Discontinued)
VCCO_1
XC3S200AN/XC3S400AN Pin Name
VCCO_1
FTG256 Ball
N15
P4
Type
VCCO
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
I/O
IO_L01N_2/M0
IO_L01P_2/M1
IO_L02N_2/CSO_B
IO_L02P_2/M2
IO_L04P_2/VS2
IO_L03P_2/RDWR_B
IO_L04N_2/VS0
IO_L03N_2/VS1
IO_L06P_2
IO_L01N_2/M0
IO_L01P_2/M1
IO_L02N_2/CSO_B
IO_L02P_2/M2
IO_L03N_2/VS2
IO_L03P_2/RDWR_B
IO_L04N_2/VS0
IO_L04P_2/VS1
IO_L05N_2
N4
T2
R2
T3
R3
P5
N6
R5
IO_L05P_2
IO_L05P_2
T4
I/O
IO_L06N_2/D6
IO_L05N_2/D7
N.C.
IO_L06N_2/D6
IO_L06P_2/D7
IO_L07N_2
T6
DUAL
DUAL
I/O
T5
P6
N.C.
IO_L07P_2
N7
I/O
IO_L08N_2/D4
IO_L08P_2/D5
N.C.
IO_L08N_2/D4
IO_L08P_2/D5
IO_L09N_2/GCLK13
IO_L09P_2/GCLK12
IO_L10N_2/GCLK15
IO_L10P_2/GCLK14
IO_L11N_2/GCLK1
IO_L11P_2/GCLK0
IO_L12N_2/GCLK3
IO_L12P_2/GCLK2
IO_L13N_2
N8
DUAL
DUAL
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
I/O
P7
T7
N.C.
R7
IO_L10N_2/GCLK15
IO_L10P_2/GCLK14
IO_L11N_2/GCLK1
IO_L11P_2/GCLK0
IO_L12N_2/GCLK3
IO_L12P_2/GCLK2
N.C.
T8
P8
P9
N9
T9
R9
M10
N10
P10
T10
R11
T11
N11
P11
P12
T12
R13
T13
P13
N12
R14
N.C.
IO_L13P_2
I/O
IO_L14P_2/MOSI/CSI_B
IO_L14N_2
IO_L14N_2/MOSI/CSI_B
IO_L14P_2
DUAL
I/O
IO_L15N_2/DOUT
IO_L15P_2/AWAKE
IO_L16N_2
IO_L15N_2/DOUT
IO_L15P_2/AWAKE
IO_L16N_2
DUAL
PWR MGMT
I/O
IO_L16P_2
IO_L16P_2
I/O
IO_L17N_2/D3
IO_L17P_2/INIT_B
IO_L20P_2/D1
IO_L18P_2/D2
N.C.
IO_L17N_2/D3
IO_L17P_2/INIT_B
IO_L18N_2/D1
IO_L18P_2/D2
IO_L19N_2
DUAL
DUAL
DUAL
DUAL
I/O
N.C.
IO_L19P_2
I/O
IO_L20N_2/CCLK
IO_L20N_2/CCLK
DUAL
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Spartan-3AN FPGA Family: Pinout Descriptions
Table 70: Spartan-3AN FTG256 Pinout (XC3S50AN (Discontinued), XC3S200AN, XC3S400AN) (Cont’d)
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
XC3S50AN Pin Name (Discontinued)
IO_L18N_2/D0/DIN/MISO
IP_2
XC3S200AN/XC3S400AN Pin Name
IO_L20P_2/D0/DIN/MISO
IP_2
FTG256 Ball
T14
L7
Type
DUAL
INPUT
INPUT
VREF
VREF
VREF
VREF
VREF
VREF
VCCO
VCCO
VCCO
VCCO
I/O
IP_2
IP_2
L8
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
VCCO_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
VCCO_2
L9
L10
M7
M8
M11
N5
M9
R4
R8
R12
C1
C2
D3
D4
E1
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
IO_L01N_3
IO_L01N_3
IO_L01P_3
IO_L01P_3
I/O
IO_L02N_3
IO_L02N_3
I/O
IO_L02P_3
IO_L02P_3
I/O
IO_L03N_3
IO_L03N_3
I/O
IO_L03P_3
IO_L03P_3
D1
E2
I/O
N.C.
IO_L05N_3
I/O
N.C.
IO_L05P_3
E3
I/O
N.C.
IO_L07N_3
G4
F3
I/O
N.C.
IO_L07P_3
I/O
IO_L08N_3/VREF_3
IO_L08P_3
IO_L08N_3/VREF_3
IO_L08P_3
G1
F1
VREF
I/O
N.C.
IO_L09N_3
H4
G3
H5
H6
H1
G2
J3
I/O
N.C.
IO_L09P_3
I/O
N.C.
IO_L10N_3
I/O
N.C.
IO_L10P_3
I/O
IO_L11N_3/LHCLK1
IO_L11P_3/LHCLK0
IO_L12N_3/IRDY2/LHCLK3
IO_L12P_3/LHCLK2
IO_L14N_3/LHCLK5
IO_L14P_3/LHCLK4
IO_L15N_3/LHCLK7
IO_L15P_3/TRDY2/LHCLK6
N.C.
IO_L11N_3/LHCLK1
IO_L11P_3/LHCLK0
IO_L12N_3/IRDY2/LHCLK3
IO_L12P_3/LHCLK2
IO_L14N_3/LHCLK5
IO_L14P_3/LHCLK4
IO_L15N_3/LHCLK7
IO_L15P_3/TRDY2/LHCLK6
IO_L16N_3
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
I/O
H3
J1
J2
K1
K3
L2
N.C.
IO_L16P_3/VREF_3
IO_L17N_3
L1
VREF
I/O
N.C.
J6
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83
Spartan-3AN FPGA Family: Pinout Descriptions
Table 70: Spartan-3AN FTG256 Pinout (XC3S50AN (Discontinued), XC3S200AN, XC3S400AN) (Cont’d)
Bank
XC3S50AN Pin Name (Discontinued)
N.C.
XC3S200AN/XC3S400AN Pin Name
IO_L17P_3
IO_L18N_3
IO_L18P_3
IO_L19N_3
IO_L19P_3
IO_L20N_3
IO_L20P_3
IO_L22N_3
IO_L22P_3
IO_L23N_3
IO_L23P_3
IO_L24N_3
IO_L24P_3
IP_L04N_3/VREF_3
IP_L04P_3
IP_L06N_3/VREF_3
IP_L06P_3
IP_L13N_3
IP_L13P_3
IP_L21N_3
IP_L21P_3
IP_L25N_3/VREF_3
IP_L25P_3
VCCO_3
FTG256 Ball
J4
Type
I/O
3
3
N.C.
L3
I/O
3
N.C.
K4
I/O
3
N.C.
L4
I/O
3
N.C.
M3
N1
I/O
3
IO_L20N_3
IO_L20P_3
IO_L22N_3
IO_L22P_3
IO_L23N_3
IO_L23P_3
IO_L24N_3
IO_L24P_3
IP_L04N_3/VREF_3
IP_L04P_3
N.C.
I/O
3
M1
P1
I/O
3
I/O
3
3
N2
I/O
P2
I/O
3
R1
I/O
3
M4
N3
I/O
3
I/O
3
F4
VREF
INPUT
VREF
INPUT
INPUT
INPUT
INPUT
INPUT
VREF
INPUT
VCCO
VCCO
VCCO
VCCO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
3
E4
3
G5
G6
J7
3
N.C.
3
IP_L13N_3
IP_L13P_3
IP_L21N_3
IP_L21P_3
IP_L25N_3/VREF_3
IP_L25P_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
GND
3
H7
3
K6
3
K5
3
L6
3
L5
3
D2
3
VCCO_3
H2
3
VCCO_3
J5
3
VCCO_3
M2
A1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A16
B7
GND
GND
GND
GND
B11
C3
GND
GND
GND
GND
C14
E5
GND
GND
GND
GND
E12
F2
GND
GND
GND
GND
F6
GND
GND
G8
G10
G15
GND
GND
GND
GND
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Spartan-3AN FPGA Family: Pinout Descriptions
Table 70: Spartan-3AN FTG256 Pinout (XC3S50AN (Discontinued), XC3S200AN, XC3S400AN) (Cont’d)
Bank
GND
XC3S50AN Pin Name (Discontinued)
GND
XC3S200AN/XC3S400AN Pin Name
GND
FTG256 Ball
H9
Type
GND
GND
GND
GND
J8
GND
GND
GND
GND
K2
GND
GND
GND
GND
K7
GND
GND
GND
GND
K9
GND
GND
GND
GND
L11
L15
M5
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
M12
P3
GND
GND
GND
GND
GND
GND
GND
GND
P14
R6
GND
GND
GND
GND
GND
GND
GND
GND
R10
T1
GND
GND
GND
GND
GND
GND
GND
GND
T16
R16
T15
A2
GND
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
SUSPEND
DONE
PROG_B
TCK
SUSPEND
DONE
PROG_B
TCK
PWR MGMT
CONFIG
CONFIG
JTAG
A15
B1
TDI
TDI
JTAG
TDO
TDO
B16
B2
JTAG
TMS
TMS
JTAG
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
E11
F5
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
L12
M6
G7
G9
H8
J9
K8
K10
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Spartan-3AN FPGA Family: Pinout Descriptions
User I/Os by Bank
Table 71 and Table 72 indicate how the available user-I/O pins are distributed between the four I/O banks on the FTG256
package. The AWAKE pin is counted as a dual-purpose I/O. The XC3S50AN FPGA (which is discontinued in the FTG256
package) has 51 unconnected balls, labeled with an N.C. type. These pins are also indicated in Figure 20.
(1)
Table 71: User I/Os Per Bank on XC3S50AN in the FTG256 Package
All Possible I/O Pins by Type
Package
I/O Bank
Maximum I/Os
Edge
I/O
21
12
5
INPUT
DUAL
VREF
CLK
8
Top
0
1
2
3
40
32
7
5
1
4
3
3
Right
Bottom
Left
8
40
2
21
0
6
6
32
15
53
6
3
8
Total
144
20
26
15
30
Notes:
1. Xilinx has issued a discontinuation notice for the XC3S50AN in the FT(G)256 package. See XCN13016: Product Discontinuation Notice For
Selected Spartan-3AN FPGA Products.
Table 72: User I/Os Per Bank on XC3S200AN and XC3S400AN in the FTG256 Package
All Possible I/O Pins by Type
Package
I/O Bank
Maximum I/Os
Edge
I/O
27
1
INPUT
DUAL
VREF
CLK
8
Top
0
1
2
3
47
50
6
6
1
5
5
Right
Bottom
Left
30
21
0
8
48
11
30
69
2
6
8
50
7
5
8
195
21
52
21
32
Total
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86
Spartan-3AN FPGA Family: Pinout Descriptions
Footprint Migration Differences
Unconnected Balls on XC3S50AN (Discontinued in the FTG256 Package)
Table 73 summarizes any footprint and functionality differences between the XC3S50AN and the XC3S200AN or
XC3S400AN devices for migration between these devices in the FTG256 package. The XC3S200AN and XC3S400AN have
identical pinouts. The XC3S50AN pinout is compatible with the XC3S200AN and XC3S400AN, however, there are 51
unconnected balls and one functionally different ball. Generally, designs migrate upward from the XC3S50AN to either the
XC3S200AN or XC3S400AN. If using differential I/O, see Table 74. If using the BPI configuration mode (parallel Flash), see
Table 75.
In Table 73, the arrow (→) indicates that this pin can unconditionally migrate from the device on the left to the device on the
right. Migration in the other direction is possible depending on how the pin is configured for the device on the right.
(1)
Table 73: FTG256 XC3S50AN Footprint Migration/Differences
FTG256 Ball
A7
Bank
0
XC3S50AN
Migration
→
XC3S200AN or XC3S400AN
N.C.
N.C.
INPUT
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A12
B12
C7
0
→
0
→
0
→
D10
E2
0
→
3
→
E3
3
→
E7
0
→
I/O/VREF
E10
E16
F3
0
→
I/O/VREF
1
→
I/O
3
→
I/O
F8
0
→
I/O
F14
F15
F16
G3
1
→
I/O
1
→
I/O
1
→
I/O
3
→
I/O
G4
3
→
I/O
G5
3
→
INPUT/VREF
G6
3
→
INPUT
G13
G14
G16
H4
1
→
I/O
1
→
I/O
1
→
I/O
3
→
I/O
H5
3
→
I/O
H6
3
→
I/O
H13
J4
1
→
I/O
3
→
I/O
J6
3
→
I/O
J10
J11
K4
1
→
INPUT/VREF
INPUT
I/O
1
→
3
→
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Spartan-3AN FPGA Family: Pinout Descriptions
(1)
Table 73: FTG256 XC3S50AN Footprint Migration/Differences (Cont’d)
FTG256 Ball
K13
L1
Bank
1
XC3S50AN
Migration
→
XC3S200AN or XC3S400AN
I/O
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
3
→
I/O/VREF
I/O
L2
3
→
L3
3
→
I/O
L4
3
→
I/O
L13
L14
L16
M3
1
→
I/O
1
→
I/O
1
→
I/O
3
→
I/O
M10
M13
M14
M15
M16
N7
2
→
I/O
1
→
I/O
1
→
I/O/VREF
I/O
1
→
1
→
I/O
2
→
I/O
N10
N12
P6
2
→
I/O
2
→
I/O
2
→
I/O
P13
R7
2
→
I/O
2
→
I/O
T7
2
→
I/O
Number of Differences:
52
Notes:
1. Xilinx has issued a discontinuation notice for the XC3S50AN in the FT(G)256 package. See XCN13016: Product Discontinuation Notice For
Selected Spartan-3AN FPGA Products.
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88
Spartan-3AN FPGA Family: Pinout Descriptions
XC3S50AN Differential I/O Alignment Differences
Also, some differential I/O pairs on the discontinued XC3S50AN FPGA are aligned differently than the corresponding pairs
on the XC3S200AN or XC3S400AN FPGAs, as shown in Table 74. All the mismatched pairs are in I/O Bank 2. The N side
of each pair is shaded.
Table 74: Differential I/O Differences in FTG256
(1)
FTG256 Ball
Bank
XC3S50AN
IO_L04P_2/VS2
XC3S200AN or XC3S400AN
IO_L03N_2/VS2
IO_L04P_2/VS1
IO_L05N_2
T3
N6
IO_L03N_2/VS1
IO_L06P_2
R5
T5
IO_L05N_2/D7
IO_L14P_2/MOSI/CSI_B
IO_L14N_2
IO_L06P_2/D7
2
P10
T10
R13
T14
IO_L14N_2/MOSI/CSI_B
IO_L14P_2
IO_L20P_2
IO_L18N_2
IO_L18N_2
IO_L20P_2
Notes:
1. Xilinx has issued a discontinuation notice for the XC3S50AN in the FT(G)256 package. See XCN13016:
Product Discontinuation Notice For Selected Spartan-3AN FPGA Products.
XC3S50AN Does Not Have BPI Mode Address Outputs
The XC3S50AN FPGA does not generate the BPI-mode address pins during configuration. Table 75 summarizes these
differences.
Table 75: XC3S50AN BPI Functional Differences
(1)
FTG256 Ball
N16
Bank
XC3S50AN
IO_L03N_1
XC3S200AN or XC3S400AN
IO_L03N_1/A1
P16
IO_L03P_1
IO_L10N_1
IO_L10P_1
IO_L20N_1
IO_L20P_1
IO_L22N_1
IO_L22P_1
IO_L23N_1
IO_L23P_1
IO_L24N_1
IO_L24P_1
IO_L03P_1/A0
J13
IO_L10N_1/A9
J12
IO_L10P_1/A8
F13
IO_L20N_1/A19
IO_L20P_1/A18
IO_L22N_1/A21
IO_L22P_1/A20
IO_L23N_1/A23
IO_L23P_1/A22
IO_L24N_1/A25
IO_L24P_1/A24
E14
1
D15
D16
D14
E13
C15
C16
Notes:
1. Xilinx has issued a discontinuation notice for the XC3S50AN in the FT(G)256 package. See XCN13016:
Product Discontinuation Notice For Selected Spartan-3AN FPGA Products.
The Spartan-3AN FPGAs are pin compatible with the same density Spartan-3A FPGAs in the FT(G)256 package, although
the Spartan-3A FPGAs require an external configuration source.
FTG256 Footprint (XC3S50AN)
Xilinx has issued a discontinuation notice for the XC3S50AN in the FT(G)256 package. See XCN13016: Product
Discontinuation Notice For Selected Spartan-3AN FPGA Products.
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89
Spartan-3AN FPGA Family: Pinout Descriptions
(Differential Outputs)
(Differential Outputs)
Bank 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
N.C.
N.C.
TCK
GND
L12P_0
L10N_0
A
B
C
D
E
F
L19P_0
L18P_0
L17P_0
L15P_0
L08N_0
L07N_0
L04N_0
L04P_0
GCLK10
GCLK7
I/O
L12N_0
GCLK11
I/O
L02P_0
VREF_0
I/O
L19N_0
I/O
L18N_0
I/O
L15N_0
I/O
L08P_0
I/O
L02N_0
VCCO_0
VCCO_0
VCCO_0
TDI
TMS
GND
N.C.
GND
INPUT
TDO
I/O
L20P_0
VREF_0
I/O
L11P_0
GCLK8
I/O
L10P_0
GCLK6
I/O
L09P_0
GCLK4
I/O
L01N_3
I/O
L01P_3
I/O
L17N_0
I/O
L16N_0
I/O
L07P_0
I/O
L03P_0
I/O
L01N_0
I/O
L24N_1
I/O
L24P_1
GND
GND
I/O
L20N_0
PUDC_B
I/O
L11N_0
GCLK9
I/O
L09N_0
GCLK5
I/O
L03P_3
I/O
L02N_3
I/O
L02P_3
I/O
L16P_0
I/O
L03N_0
I/O
L01P_0
I/O
L23N_1
I/O
L22N_1
I/O
L22P_1
VCCO_3
N.C.
INPUT
INPUT
GND
N.C.
N.C.
INPUT
GND
I/O
L03N_3
INPUT
L04P_3
INPUT
VREF_0
I/O
L23P_1
I/O
L20P_1
VCCO_0
VCCAUX
VCCO_1
N.C.
N.C.
N.C.
N.C.
GND
VCCAUX
N.C.
N.C.
N.C.
N.C.
N.C.
INPUT
L04N_3
VREF_3
INPUT
L25P_1
VREF_1
I/O
L08P_3
INPUT
L25N_1
I/O
L20N_1
GND
INPUT
N.C.
INPUT INPUT
N.C.
N.C.
I/O
L08N_3
VREF_3 LHCLK0
I/O
L11P_3
INPUT
L21P_1
VREF_1
INPUT
L21N_1
N.C.
N.C.
N.C.
N.C.
N.C.
N.C. VCCINT GND VCCINT GND
N.C.
N.C.
GND
G
H
J
I/O
L15P_1
IRDY1
I/O
I/O
L12P_3
LHCLK2
I/O
L14N_1
RHCLK5
I/O
L15N_1
RHCLK7
INPUT
INPUT INPUT
L13P_1
VCCO_3
L11N_3
VCCO_1
N.C.
N.C.
N.C.
VCCINT GND
L13P_3
L13N_1
LHCLK1
RHCLK6
I/O
L12N_3
IRDY2
LHCLK3
I/O
L12N_1
TRDY1
RHCLK3
I/O
L14N_3
LHCLK5 LHCLK4
I/O
L14P_3
I/O
L14P_1
RHCLK4
INPUT
L13N_3
I/O
L10P_1
I/O
L10N_1
VCCO_3
VCCO_1
GND VCCINT N.C.
N.C.
I/O
L15P_3
TRDY2
LHCLK6
I/O
L15N_3
LHCLK7
INPUT
L04N_1
VREF_1
I/O
L11N_1
I/O
L11P_1
I/O
L12P_1
INPUT INPUT
L21P_3
INPUT
L04P_1
GND
N.C.
GND VCCINT GND VCCINT
N.C.
N.C.
N.C.
K
L
L21N_3
RHCLK1 RHCLK0 RHCLK2
INPUT
L25N_3
VREF_3
INPUT
L25P_3
INPUT INPUT
INPUT INPUT
VCCAUX
GND
N.C.
N.C.
N.C.
GND
N.C.
N.C.
GND
N.C.
N.C.
N.C.
VREF_2 VREF_2
I/O
L20P_3
I/O
L24N_3
INPUT INPUT
VREF_2 VREF_2
INPUT
VREF_2
VCCO_3
VCCAUX
VCCO_2
GND
N.C.
N.C.
M
N
P
R
T
I/O
L01P_2
M1
I/O
L03N_2
VS1
I/O
L08N_2
D4
I/O
L11P_2
GCLK0
I/O
L01P_1
HDC
I/O
L01N_1
LDC2
I/O
L20N_3
I/O
L22P_3
I/O
L24P_3
INPUT
VREF_2
I/O
L16N_2
I/O
L03N_1
VCCO_1
N.C.
N.C.
I/O
L14P_2
MOSI
I/O
L01N_2
M0
I/O
L04N_2
VS0
I/O
L08P_2
D5
I/O
L10P_2
GCLK14
I/O
L11N_2
GCLK1
I/O
L17N_2
D3
I/O
L02N_1
LDC0
I/O
L22N_3
I/O
L23N_3
I/O
L16P_2
I/O
L03P_1
GND
N.C.
N.C.
GND
CSI_B
I/O
L02P_2
M2
I/O
L03P_2
RDWR_B
I/O
L12P_2
GCLK2
I/O
L15N_2
DOUT
I/O
L20P_2
D1
I/O
L20N_2
CCLK
I/O
L02P_1
LDC1
I/O
L23P_3
I/O
L06P_2
VCCO_2
VCCO_2
VCCO_2
GND
N.C.
N.C.
GND
I/O
L18N_2
D0
I/O
L02N_2
CSO_B
I/O
L04P_2
VS2
I/O
L05N_2
D7
I/O
L06N_2
D6
I/O
L10N_2
GCLK15
I/O
L12N_2
GCLK3
I/O
L15P_2
AWAKE
I/O
L17P_2
INIT_B
I/O
L18P_2
D2
I/O
L05P_2
I/O
L14N_2
GND
DONE
GND
DIN/MISO
(Differential Outputs)
Bank 2
(Differential Outputs)
DS529-4_09_012009
Figure 20: XC3S50AN FTG256 Package Footprint (Top View)
I/O: Unrestricted,
DUAL: Configuration pins,
VREF: User I/O or input
SUSPEND: Dedicated
SUSPEND and
dual-purpose AWAKE
Power Management pins
53
20
2
25
30
4
15
16
6
2
general-purpose user I/O
then possible user I/O
voltage reference for bank
INPUT: Unrestricted,
general-purpose input pin
CLK: User I/O, input, or
global buffer input
VCCO: Output voltage
supply for bank
CONFIG: Dedicated
configuration pins
JTAG: Dedicated JTAG
port pins
VCCINT: Internal core
supply voltage (+1.2V)
N.C.: Not connected
(XC3S50AN only)
GND: Ground
VCCAUX: Auxiliary supply
voltage
51
28
4
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Product Specification
90
Spartan-3AN FPGA Family: Pinout Descriptions
FTG256 Footprint (XC3S200AN, XC3S400AN)
X-Ref Target - Figure 21
Bank 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
TCK
GND
L12P_0
L10N_0
A
B
C
D
E
F
L19P_0
L18P_0
L17P_0
L15P_0
L13P_0
L08N_0
L07N_0
L05N_0
L04N_0
L04P_0
GCLK10
GCLK7
I/O
L12N_0
GCLK11
I/O
L02P_0
VREF_0
I/O
L19N_0
I/O
L18N_0
I/O
L15N_0
I/O
L08P_0
I/O
L05P_0
I/O
L02N_0
VCCO_0
VCCO_0
VCCO_0
TDI
TMS
GND
GND
TDO
I/O
L20P_0
VREF_0
I/O
L11P_0
GCLK8
I/O
L10P_0
GCLK6
I/O
L09P_0
GCLK4
I/O
L24N_1
A25
I/O
L24P_1
A24
I/O
L01N_3
I/O
L01P_3
I/O
L17N_0
I/O
L16N_0
I/O
L13N_0
I/O
L07P_0
I/O
L03P_0
I/O
L01N_0
GND
GND
I/O
L20N_0
PUDC_B
I/O
L11N_0
GCLK9
I/O
L09N_0
GCLK5
I/O
L23N_1
A23
I/O
L22N_1
A21
I/O
L22P_1
A20
I/O
L03P_3
I/O
L02N_3
I/O
L02P_3
I/O
L16P_0
I/O
L06P_0
I/O
L03N_0
I/O
L01P_0
VCCO_3
INPUT
INPUT
GND
INPUT
GND
I/O
L14N_0
VREF_0
I/O
L06N_0
VREF_0
I/O
L23P_1
A22
I/O
L20P_1
A18
I/O
L18P_1
A14
I/O
L03N_3
I/O
L05N_3
I/O
L05P_3
INPUT
L04P_3
INPUT
VREF_0
VCCO_0
VCCAUX
VCCO_1
GND
INPUT
L04N_3
VREF_3
INPUT
L25P_1
VREF_1
I/O
L20N_1
A19
I/O
L19N_1
A17
I/O
L18N_1
A15
I/O
L16N_1
A11
I/O
L08P_3
I/O
L07P_3
I/O
L14P_0
INPUT
L25N_1
VCCAUX
GND
INPUT
INPUT INPUT
I/O
I/O
INPUT
L06N_3
VREF_3
INPUT
L21P_1
VREF_1
I/O
L19P_1
A16
I/O
L17N_1
A13
I/O
L16P_1
A10
I/O
I/O
INPUT
INPUT
VCCINT GND VCCINT GND
GND
L08N_3
L11P_3
G
H
J
L09P_3
L07N_3
L06P_3
L21N_1
VREF_3 LHCLK0
I/O
L15P_1
IRDY1
I/O
I/O
L12P_3
LHCLK2
I/O
L17P_1
A12
I/O
L14N_1
RHCLK5
I/O
L15N_1
RHCLK7
I/O
L09N_3
I/O
L10N_3
I/O
L10P_3
INPUT
INPUT INPUT
VCCO_3
L11N_3
VCCO_1
VCCINT GND
GND VCCINT
L13P_3
L13P_1
L13N_1
LHCLK1
RHCLK6
I/O
L12N_3
IRDY2
LHCLK3
I/O
L12N_1
TRDY1
RHCLK3
I/O
L14N_3
LHCLK5 LHCLK4
I/O
L14P_3
INPUT
L09P_1
VREF_1
I/O
L10P_1
A8
I/O
L10N_1
A9
I/O
L14P_1
RHCLK4
I/O
L17P_3
I/O
L17N_3
INPUT
L13N_3
INPUT
L09N_1
VCCO_3
VCCO_1
I/O
L15P_3
TRDY2
LHCLK6
I/O
INPUT
L04N_1
VREF_1
I/O
L06N_1
A3
I/O
I/O
I/O
I/O
L18P_3
INPUT INPUT
INPUT
L04P_1
GND
GND VCCINT GND VCCINT
L15N_3
L11N_1
L11P_1
L12P_1
K
L
L21P_3
L21N_3
LHCLK7
RHCLK1 RHCLK0 RHCLK2
I/O
INPUT
L25N_3
VREF_3
I/O
L06P_1
A2
I/O
L08P_1
A6
I/O
L08N_1
A7
I/O
L16N_3
I/O
L18N_3
I/O
L19N_3
INPUT
L25P_3
INPUT INPUT
INPUT INPUT
VCCAUX
GND
GND
L16P_3
VREF_2 VREF_2
VREF_3
I/O
I/O
L07P_1
A4
I/O
L07N_1
A5
I/O
I/O
I/O
INPUT INPUT
I/O
INPUT
I/O
VCCO_3
VCCAUX
VCCO_2
GND
GND
L05N_1
M
N
P
R
T
L20P_3
L19P_3
L24N_3
VREF_2 VREF_2
L13N_2 VREF_2
L05P_1
VREF_1
I/O
L01P_2
M1
I/O
L04P_2
VS1
I/O
I/O
I/O
L11P_2
GCLK0
I/O
L01P_1
HDC
I/O
L01N_1
LDC2
I/O
L03N_1
A1
I/O
L20N_3
I/O
L22P_3
I/O
L24P_3
INPUT
VREF_2
I/O
L13P_2
I/O
L16N_2
I/O
L19P_2
VCCO_1
L08N_2
L07P_2
D4
I/O
L14N_2
MOSI
I/O
L01N_2
M0
I/O
L04N_2
VS0
I/O
L08P_2
D5
I/O
I/O
L11N_2
GCLK1
I/O
L17N_2
D3
I/O
L02N_1
LDC0
I/O
L03P_1
A0
I/O
L22N_3
I/O
L23N_3
I/O
L07N_2
I/O
L16P_2
I/O
L19N_2
GND
GND
L10P_2
GCLK14
CSI_B
I/O
L02P_2
M2
I/O
L03P_2
RDWR_B
I/O
L09P_2
I/O
L12P_2
GCLK2
I/O
L15N_2
DOUT
I/O
L18N_2
D1
I/O
L20N_2
CCLK
I/O
L02P_1
LDC1
I/O
L23P_3
I/O
L05N_2
VCCO_2
VCCO_2
VCCO_2
GND
GND
GCLK12
I/O
L20P_2
D0
I/O
L02N_2
CSO_B
I/O
L03N_2
VS2
I/O
L06P_2
D7
I/O
L06N_2
D6
I/O
L09N_2
I/O
L10N_2
I/O
L12N_2
GCLK3
I/O
L15P_2
AWAKE
I/O
L17P_2
INIT_B
I/O
L18P_2
D2
I/O
L05P_2
I/O
L14P_2
GND
DONE
GND
GCLK13 GCLK15
DIN/MISO
DS529-4_06_012009
Bank 2
Figure 21: XC3S200AN and XC3S400AN FPGA in FTG256 Package Footprint (Top View)
I/O: Unrestricted,
DUAL: Configuration pins,
VREF: User I/O or input
SUSPEND: Dedicated
SUSPEND and
dual-purpose AWAKE
Power Management pins
69
21
2
51
32
4
21
16
6
2
general-purpose user I/O
then possible user I/O
voltage reference for bank
INPUT: Unrestricted,
general-purpose input pin
CLK: User I/O, input, or
global buffer input
VCCO: Output voltage
supply for bank
CONFIG: Dedicated
configuration pins
JTAG: Dedicated JTAG
port pins
VCCINT: Internal core
supply voltage (+1.2V)
N.C.: Not connected
GND: Ground
VCCAUX: Auxiliary supply
voltage
0
28
4
DS557 (v4.2) June 12, 2014
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Product Specification
91
Spartan-3AN FPGA Family: Pinout Descriptions
FGG400: 400-Ball Fine-Pitch Ball Grid Array
The 400-ball fine-pitch ball grid array, FGG400, supports the XC3S400AN FPGA as shown in Table 76 and Figure 22.
Table 76 lists all the FGG400 package pins. They are sorted by bank number and then by pin name. Pins that form a
differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type (as
defined in Table 62).
An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at:
www.xilinx.com/support/documentation/data_sheets/s3a_pin.zip.
Pinout Table
Table 76: Spartan-3AN FGG400 Pinout (Cont’d)
Table 76: Spartan-3AN FGG400 Pinout
FGG400
FGG400
Bank
0
Pin Name
IO_L16P_0/GCLK6
IO_L17N_0/GCLK9
IO_L17P_0/GCLK8
IO_L18N_0/GCLK11
IO_L18P_0/GCLK10
IO_L19N_0
Ball
A10
E10
D10
A8
A9
C9
B9
C8
B8
D8
C7
F9
Type
GCLK
GCLK
GCLK
GCLK
GCLK
I/O
Bank
0
Pin Name
IO_L01N_0
Ball
A18
B18
C17
D17
E15
D16
A17
B17
A16
C16
C15
D15
A14
C14
A15
B15
F13
E13
C13
D14
C12
B13
F12
D12
A12
B12
C11
B11
E11
D11
C10
Type
I/O
0
0
IO_L01P_0
I/O
0
0
IO_L02N_0
I/O
0
0
IO_L02P_0/VREF_0
IO_L03N_0
VREF
I/O
0
0
0
0
IO_L03P_0
I/O
0
IO_L19P_0
I/O
0
IO_L04N_0
I/O
0
IO_L20N_0
I/O
0
IO_L04P_0/VREF_0
IO_L05N_0
VREF
I/O
0
IO_L20P_0
I/O
0
0
IO_L21N_0
I/O
0
IO_L05P_0
I/O
0
IO_L21P_0
I/O
0
IO_L06N_0
I/O
0
IO_L22N_0/VREF_0
IO_L22P_0
VREF
I/O
0
IO_L06P_0
I/O
0
E9
F8
0
IO_L07N_0
I/O
0
IO_L23N_0
I/O
0
IO_L07P_0
I/O
0
IO_L23P_0
E8
A7
B7
C6
A6
B5
A5
F7
I/O
0
IO_L08N_0
I/O
0
IO_L24N_0
I/O
0
IO_L08P_0
I/O
0
IO_L24P_0
I/O
0
IO_L09N_0
I/O
0
IO_L25N_0
I/O
0
IO_L09P_0
I/O
0
IO_L25P_0
I/O
0
IO_L10N_0/VREF_0
IO_L10P_0
VREF
I/O
0
IO_L26N_0
I/O
0
0
IO_L26P_0
I/O
0
IO_L11N_0
I/O
0
IO_L27N_0
I/O
0
IO_L11P_0
I/O
0
IO_L27P_0
E7
D6
C5
C4
A4
B3
A3
F6
I/O
0
IO_L12N_0
I/O
0
IO_L28N_0
I/O
0
IO_L12P_0
I/O
0
IO_L28P_0
I/O
0
IO_L13N_0
I/O
0
IO_L29N_0
I/O
0
IO_L13P_0
I/O
0
IO_L29P_0
I/O
0
IO_L14N_0
I/O
0
IO_L30N_0
I/O
0
IO_L14P_0
I/O
0
IO_L30P_0
I/O
0
IO_L15N_0/GCLK5
IO_L15P_0/GCLK4
IO_L16N_0/GCLK7
GCLK
GCLK
GCLK
0
IO_L31N_0
I/O
0
0
IO_L31P_0
E6
I/O
0
DS557 (v4.2) June 12, 2014
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Product Specification
92
Spartan-3AN FPGA Family: Pinout Descriptions
Table 76: Spartan-3AN FGG400 Pinout (Cont’d)
Table 76: Spartan-3AN FGG400 Pinout (Cont’d)
FGG400
FGG400
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Name
IO_L32N_0/PUDC_B
IO_L32P_0/VREF_0
IP_0
Ball
Type
DUAL
VREF
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VREF
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
I/O
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Name
IO_L12P_1/A2
Ball
N15
N19
N18
M18
M17
L16
Type
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
DUAL
DUAL
I/O
B2
A2
IO_L13N_1/A5
IO_L13P_1/A4
E14
F11
F14
G8
IP_0
IO_L14N_1/A7
IO_L14P_1/A6
IP_0
IP_0
IO_L16N_1/A9
IO_L16P_1/A8
IP_0
G9
L15
IP_0
G10
G12
G13
H9
IO_L17N_1/RHCLK1
IO_L17P_1/RHCLK0
M20
M19
IP_0
IP_0
IO_L18N_1/TRDY1/RHCLK3 L18
IP_0
IO_L18P_1/RHCLK2
IO_L20N_1/RHCLK5
IO_L20P_1/RHCLK4
IO_L21N_1/RHCLK7
IO_L21P_1/IRDY1/RHCLK6
IO_L22N_1/A11
IO_L22P_1/A10
IO_L24N_1
L19
L17
K18
J20
IP_0
H10
H11
H12
G11
B4
IP_0
IP_0
IP_0/VREF_0
VCCO_0
K20
J18
VCCO_0
B10
B16
D7
J19
VCCO_0
K16
J17
VCCO_0
IO_L24P_1
I/O
VCCO_0
D13
F10
V20
W20
U18
V19
R16
T17
T20
T18
U20
U19
P17
P16
R17
R18
R20
R19
P20
P18
N17
IO_L25N_1/A13
IO_L25P_1/A12
IO_L26N_1/A15
IO_L26P_1/A14
IO_L28N_1
H18
H19
G20
H20
H17
G18
F19
F20
F18
G17
E19
E20
F17
E18
D18
D20
F16
G16
C19
C20
B19
DUAL
DUAL
DUAL
DUAL
I/O
VCCO_0
IO_L01N_1/LDC2
IO_L01P_1/HDC
IO_L02N_1/LDC0
IO_L02P_1/LDC1
IO_L03N_1/A1
IO_L03P_1/A0
IO_L05N_1
IO_L05P_1
IO_L06N_1
IO_L06P_1
IO_L07N_1
IO_L07P_1
IO_L08N_1
IO_L08P_1
IO_L09N_1
IO_L09P_1
IO_L10N_1/VREF_1
IO_L10P_1
IO_L12N_1/A3
IO_L28P_1
I/O
IO_L29N_1/A17
IO_L29P_1/A16
IO_L30N_1/A19
IO_L30P_1/A18
IO_L32N_1
DUAL
DUAL
DUAL
DUAL
I/O
I/O
I/O
I/O
IO_L32P_1
I/O
I/O
IO_L33N_1
I/O
I/O
IO_L33P_1
I/O
I/O
IO_L34N_1
I/O
I/O
IO_L34P_1
I/O
I/O
IO_L36N_1/A21
IO_L36P_1/A20
IO_L37N_1/A23
IO_L37P_1/A22
IO_L38N_1/A25
DUAL
DUAL
DUAL
DUAL
DUAL
I/O
VREF
I/O
DUAL
DS557 (v4.2) June 12, 2014
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Product Specification
93
Spartan-3AN FPGA Family: Pinout Descriptions
Table 76: Spartan-3AN FGG400 Pinout (Cont’d)
Table 76: Spartan-3AN FGG400 Pinout (Cont’d)
FGG400
FGG400
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Pin Name
IO_L38P_1/A24
Ball
B20
N14
P15
P14
M15
M16
M13
M14
L13
L14
K14
K15
J15
J16
J13
J14
H14
H15
G14
G15
D19
H16
K19
N16
T19
V4
Type
DUAL
VREF
VREF
INPUT
VREF
INPUT
INPUT
VREF
INPUT
INPUT
INPUT
VREF
INPUT
INPUT
INPUT
VREF
INPUT
INPUT
INPUT
VREF
VCCO
VCCO
VCCO
VCCO
VCCO
DUAL
DUAL
DUAL
DUAL
I/O
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Pin Name
IO_L08P_2
Ball
Type
I/O
Y4
IP_1/VREF_1
IP_L04N_1/VREF_1
IP_L04P_1
IO_L09N_2/VS0
IO_L09P_2/VS1
IO_L10N_2
W6
DUAL
DUAL
I/O
V6
Y7
IP_L11N_1/VREF_1
IP_L11P_1
IO_L10P_2
Y6
I/O
IO_L11N_2
U9
I/O
IP_L15N_1
IO_L11P_2
T9
I/O
IP_L15P_1/VREF_1
IP_L19N_1
IO_L12N_2/D6
IO_L12P_2/D7
IO_L13N_2
W8
DUAL
DUAL
I/O
V7
IP_L19P_1
V9
IP_L23N_1
IO_L13P_2
V8
I/O
IP_L23P_1/VREF_1
IP_L27N_1
IO_L14N_2/D4
IO_L14P_2/D5
IO_L15N_2/GCLK13
IO_L15P_2/GCLK12
IO_L16N_2/GCLK15
IO_L16P_2/GCLK14
IO_L17N_2/GCLK1
IO_L17P_2/GCLK0
IO_L18N_2/GCLK3
IO_L18P_2/GCLK2
IO_L19N_2
T10
U10
Y9
DUAL
DUAL
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
I/O
IP_L27P_1
IP_L31N_1
W9
IP_L31P_1/VREF_1
IP_L35N_1
W10
V10
V11
Y11
V12
U11
R12
T12
W12
Y12
W13
Y13
V13
U13
R13
T13
W14
Y14
T14
V14
V15
Y15
T15
U15
W16
IP_L35P_1
IP_L39N_1
IP_L39P_1/VREF_1
VCCO_1
VCCO_1
VCCO_1
IO_L19P_2
I/O
VCCO_1
IO_L20N_2/MOSI/CSI_B
IO_L20P_2
DUAL
I/O
VCCO_1
IO_L01N_2/M0
IO_L01P_2/M1
IO_L02N_2/CSO_B
IO_L02P_2/M2
IO_L03N_2
IO_L21N_2
I/O
U4
IO_L21P_2
I/O
Y2
IO_L22N_2/DOUT
IO_L22P_2/AWAKE
IO_L23N_2
DUAL
PWR MGMT
I/O
W3
W4
Y3
IO_L03P_2
I/O
IO_L23P_2
I/O
IO_L04N_2
R7
I/O
IO_L24N_2/D3
IO_L24P_2/INIT_B
IO_L25N_2
DUAL
DUAL
I/O
IO_L04P_2
T6
I/O
IO_L05N_2
U5
I/O
IO_L05P_2
V5
I/O
IO_L25P_2
I/O
IO_L06N_2
U6
I/O
IO_L26N_2/D1
IO_L26P_2/D2
IO_L27N_2
DUAL
DUAL
I/O
IO_L06P_2
T7
I/O
IO_L07N_2/VS2
IO_L07P_2/RDWR_B
IO_L08N_2
U7
DUAL
DUAL
I/O
T8
IO_L27P_2
I/O
Y5
IO_L28N_2
I/O
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Spartan-3AN FPGA Family: Pinout Descriptions
Table 76: Spartan-3AN FGG400 Pinout (Cont’d)
Table 76: Spartan-3AN FGG400 Pinout (Cont’d)
FGG400
FGG400
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Name
IO_L28P_2
Ball
Y16
U16
V16
Y18
Y17
U17
V17
Y19
W18
P9
Type
I/O
Bank
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Name
IO_L08P_3
Ball
H6
G4
F3
F2
E3
H2
G3
G1
F1
H3
J4
Type
I/O
IO_L29N_2
IO_L29P_2
IO_L30N_2
IO_L30P_2
IO_L31N_2
IO_L31P_2
IO_L32N_2/CCLK
IO_L32P_2/D0/DIN/MISO
IP_2
I/O
IO_L09N_3
I/O
I/O
IO_L09P_3
I/O
I/O
IO_L10N_3
I/O
I/O
IO_L10P_3
I/O
I/O
IO_L12N_3
I/O
I/O
IO_L12P_3
I/O
DUAL
DUAL
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VREF
VREF
VREF
VREF
VREF
VREF
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
I/O
IO_L13N_3/VREF_3
IO_L13P_3
VREF
I/O
IO_L14N_3
I/O
IP_2
P12
P13
R8
IO_L14P_3
I/O
IP_2
IO_L16N_3
J2
I/O
IP_2
IO_L16P_3
J3
I/O
IP_2
R10
T11
N9
IO_L17N_3/LHCLK1
IO_L17P_3/LHCLK0
IO_L18N_3/IRDY2/LHCLK3
IO_L18P_3/LHCLK2
IO_L20N_3/LHCLK5
IO_L20P_3/LHCLK4
IO_L21N_3/LHCLK7
IO_L21P_3/TRDY2/LHCLK6
IO_L22N_3
K2
J1
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
I/O
IP_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
VCCO_2
L3
N12
P8
K3
L5
P10
P11
R14
R11
U8
K4
M1
L1
M3
M2
M5
M4
N2
N1
N4
N3
R1
P1
P4
P3
R3
R2
T2
T1
R4
T3
U3
VCCO_2
IO_L22P_3/VREF_3
IO_L24N_3
VREF
I/O
VCCO_2
U14
W5
W11
W17
D3
VCCO_2
IO_L24P_3
I/O
VCCO_2
IO_L25N_3
I/O
VCCO_2
IO_L25P_3
I/O
IO_L01N_3
IO_L01P_3
IO_L02N_3
IO_L02P_3
IO_L03N_3
IO_L03P_3
IO_L05N_3
IO_L05P_3
IO_L06N_3
IO_L06P_3
IO_L07N_3
IO_L07P_3
IO_L08N_3
IO_L26N_3
I/O
D4
I/O
IO_L26P_3
I/O
C2
I/O
IO_L28N_3
I/O
B1
I/O
IO_L28P_3
I/O
D2
I/O
IO_L29N_3
I/O
C1
I/O
IO_L29P_3
I/O
E1
I/O
IO_L30N_3
I/O
D1
I/O
IO_L30P_3
I/O
G5
I/O
IO_L32N_3
I/O
F4
I/O
IO_L32P_3/VREF_3
IO_L33N_3
VREF
I/O
J5
I/O
J6
I/O
IO_L33P_3
I/O
H4
I/O
IO_L34N_3
I/O
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Spartan-3AN FPGA Family: Pinout Descriptions
Table 76: Spartan-3AN FGG400 Pinout (Cont’d)
Table 76: Spartan-3AN FGG400 Pinout (Cont’d)
FGG400
FGG400
Bank
Pin Name
IO_L34P_3
Ball
U1
T4
Type
I/O
Bank
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin Name
Ball
E12
F15
G2
Type
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PWR MGMT
CONFIG
CONFIG
JTAG
JTAG
JTAG
3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
3
IO_L36N_3
IO_L36P_3
IO_L37N_3
IO_L37P_3
IO_L38N_3
IO_L38P_3
IP_3
I/O
3
R5
V2
V1
W2
W1
H7
G6
G7
J7
I/O
3
I/O
G19
H8
3
I/O
3
I/O
H13
J9
3
I/O
3
INPUT
VREF
INPUT
VREF
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VREF
INPUT
VCCO
VCCO
VCCO
VCCO
VCCO
GND
J11
K1
3
IP_L04N_3/VREF_3
IP_L04P_3
IP_L11N_3/VREF_3
IP_L11P_3
IP_L15N_3
IP_L15P_3
IP_L19N_3
IP_L19P_3
IP_L23N_3
IP_L23P_3
IP_L27N_3
IP_L27P_3
IP_L31N_3
IP_L31P_3
IP_L35N_3
IP_L35P_3
IP_L39N_3/VREF_3
IP_L39P_3
VCCO_3
3
K10
K12
K17
L4
3
3
J8
3
K7
K8
K5
K6
L6
3
L9
3
L11
L20
M10
M12
N8
3
3
3
3
L7
M7
M8
N7
M6
N6
P5
P7
P6
E2
H5
L2
3
N11
N13
P2
3
3
3
P19
R6
3
3
R9
3
T16
U12
V3
3
3
VCCO_3
3
VCCO_3
V18
W7
W15
Y1
3
VCCO_3
N5
U2
A1
A11
A20
B6
B14
C3
C18
D9
E5
3
VCCO_3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Y10
Y20
R15
W19
D5
GND
GND
GND
GND
VCCAUX SUSPEND
VCCAUX DONE
VCCAUX PROG_B
VCCAUX TCK
GND
GND
GND
GND
GND
GND
A19
F5
GND
GND
VCCAUX TDI
GND
GND
VCCAUX TDO
E17
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96
Spartan-3AN FPGA Family: Pinout Descriptions
Table 76: Spartan-3AN FGG400 Pinout (Cont’d)
FGG400
Ball
Bank
Pin Name
Type
VCCAUX TMS
E4
JTAG
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
A13
E16
H1
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
K13
L8
N20
T5
Y8
J10
J12
K9
K11
L10
L12
M9
M11
N10
User I/Os by Bank
Table 77 indicates how the 311 available user-I/O pins are distributed between the four I/O banks on the FGG400 package.
The AWAKE pin is counted as a dual-purpose I/O.
Table 77: User I/Os Per Bank for the XC3S400AN in the FGG400 Package
All Possible I/O Pins by Type
Package
I/O Bank
Maximum I/Os
Edge
I/O
INPUT
DUAL
VREF
CLK
8
Top
0
1
2
3
77
79
50
12
1
6
8
Right
Bottom
Left
21
12
30
21
0
8
76
35
6
6
8
79
49
16
6
8
Total
311
155
46
52
26
32
Footprint Migration Differences
The XC3S400AN is the only Spartan-3AN FPGA offered in the FGG400 package.
The XC3S400AN FPGA is pin compatible with the Spartan-3A XC3S400A FPGA in the FG(G)400 package, although the
Spartan-3A FPGA requires an external configuration source.
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Spartan-3AN FPGA Family: Pinout Descriptions
X-Ref Target - Figure 22
FGG400 Footprint
Bank 0
1
2
3
4
5
6
7
8
9
10
Left Half of FGG400
Package (Top View)
I/O
L32P_0
VREF_0
I/O
L18N_0
GCLK11 GCLK10
I/O
L18P_0
I/O
L16P_0
GCLK6
I/O
L30P_0
I/O
L29P_0
I/O
L26P_0
I/O
L25P_0
I/O
L24N_0
GND
A
B
C
D
E
F
I/O
L32N_0
PUDC_B
I/O
L02P_3
I/O
L30N_0
I/O
L26N_0
I/O
L24P_0
I/O
L20P_0
I/O
L19P_0
VCCO_0
VCCO_0
GND
I/O: Unrestricted,
general-purpose user I/O
155
I/O
L16N_0
GCLK7
I/O
L03P_3
I/O
L02N_3
I/O
L29N_0
I/O
L28P_0
I/O
L25N_0
I/O
L21P_0
I/O
L20N_0
I/O
L19N_0
GND
INPUT: Unrestricted,
I/O
L17P_0
GCLK8
general-purpose input pin
I/O
L05P_3
I/O
L03N_3
I/O
L01N_3
I/O
L01P_3
I/O
L28N_0
I/O
L21N_0
46
VCCO_0
GND
PROG_B
I/O
L17N_0
GCLK9
DUAL: Configuration pins,
I/O
L05N_3
I/O
L10P_3
I/O
L31P_0
I/O
L27P_0
I/O
L23P_0
I/O
L22P_0
VCCO_3
TMS
GND
then possible user I/O
51
I/O
L22N_0
VREF_0
I/O
L13P_3
I/O
L10N_3
I/O
L09P_3
I/O
L06P_3
I/O
L31N_0
I/O
L27N_0
I/O
L23N_0
VCCO_0
TDI
VREF: User I/O or input
voltage reference for bank
26
I/O
L13N_3
VREF_3
INPUT
L04N_3
VREF_3
I/O
L12P_3
I/O
L09N_3
I/O
L06N_3
INPUT
L04P_3
GND
INPUT INPUT INPUT
G
H
J
CLK: User I/O, input, or
clock buffer input
32
I/O
L12N_3
I/O
L14N_3
I/O
L08N_3
I/O
L08P_3
VCCAUX
VCCO_3
INPUT
GND
INPUT INPUT
GND VCCINT
VCCINT GND
GND VCCINT
VCCINT GND
I/O
L17P_3
LHCLK0
INPUT
L11N_3
VREF_3
CONFIG: Dedicated
configuration pins
I/O
L16N_3
I/O
L16P_3
I/O
L14P_3
I/O
L07N_3
I/O
L07P_3
INPUT
L11P_3
2
JTAG: Dedicated JTAG
I/O
L17N_3
LHCLK1 LHCLK2 LHCLK4
I/O
L18P_3
I/O
L20P_3
INPUT INPUT INPUT INPUT
L19N_3
GND
port pins
K
L
4
L19P_3
L15N_3
L15P_3
I/O
L21P_3
TRDY2
LHCLK6
I/O
L18N_3
IRDY2
LHCLK3
I/O
L20N_3
LHCLK5
INPUT INPUT
L23N_3
VCCO_3
VCCAUX
GND
SUSPEND: Dedicated
L23P_3
SUSPEND and
dual-purpose AWAKE
2
I/O
L21N_3
LHCLK7 VREF_3
I/O
L22P_3
I/O
L22N_3
I/O
L24P_3
I/O
L24N_3
INPUT INPUT INPUT
L31P_3
Power Management pins
M
N
P
R
T
L27N_3
L27P_3
GND: Ground
I/O
L25P_3
I/O
L25N_3
I/O
L26P_3
I/O
L26N_3
INPUT INPUT
L35N_3
INPUT
VCCINT
VREF_2
43
VCCO_3
GND
L31N_3
INPUT
L39N_3
VREF_3
VCCO: Output voltage
I/O
L28P_3
I/O
L29P_3
I/O
L29N_3
INPUT INPUT
L35P_3
INPUT
VREF_2
INPUT
INPUT
GND
L39P_3
VREF_2
supply for bank
22
I/O
L28N_3
I/O
L30P_3
I/O
L30N_3
I/O
L33N_3
I/O
L36P_3
I/O
L04N_2
GND
INPUT
GND
INPUT
VCCINT: Internal core
supply voltage (+1.2V)
9
I/O
L32P_3
VREF_3
I/O
L07P_2
RDWR_B
I/O
L14N_2
D4
I/O
L32N_3
I/O
L33P_3
I/O
L36N_3
I/O
L04P_2
I/O
L06P_2
I/O
L11P_2
VCCAUX
VCCAUX: Auxiliary supply
voltage
I/O
L01P_2
M1
I/O
L07N_2
VS2
I/O
L14P_2
D5
8
I/O
I/O
I/O
I/O
I/O
VCCO_3
VCCO_2
U
V
W
Y
L34P_3
L34N_3
L05N_2
L06N_2
L11N_2
I/O
L01N_2
M0
I/O
L09P_2
VS1
I/O
L12P_2
D7
I/O
L16P_2
GCLK14
I/O
L37P_3
I/O
L37N_3
I/O
L05P_2
I/O
L13P_2
I/O
L13N_2
GND
I/O
L02P_2
M2
I/O
L09N_2
VS0
I/O
L12N_2
D6
I/O
L15P_2
I/O
L16N_2
GCLK12 GCLK15
I/O
L38P_3
I/O
L38N_3
I/O
L03N_2
VCCO_2
GND
I/O
L02N_2
CSO_B
I/O
L15N_2
GCLK13
I/O
L03P_2
I/O
L08P_2
I/O
L08N_2
I/O
L10P_2
I/O
L10N_2
VCCAUX
GND
GND
Bank 2
DS529-4_03_011608
Figure 22: FGG400 Package Footprint (Top View)
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98
Spartan-3AN FPGA Family: Pinout Descriptions
Bank 0
11
12
13
14
15
16
17
18
19
20
Right Half of FGG400
Package (Top View)
I/O
I/O
I/O
I/O
I/O
I/O
VCCAUX
GND
TCK
GND
A
B
C
D
E
F
L13N_0
L07N_0
L08N_0
L05N_0
L04N_0
L01N_0
I/O
L04P_0
VREF_0
I/O
L38N_1
A25
I/O
L38P_1
A24
I/O
L14P_0
I/O
L13P_0
I/O
L11P_0
I/O
L08P_0
I/O
L01P_0
VCCO_0
GND
I/O
L10N_0
VREF_0
I/O
L37N_1
A23
I/O
L37P_1
A22
I/O
L14N_0
I/O
L11N_0
I/O
L07P_0
I/O
L06N_0
I/O
L05P_0
I/O
L02N_0
GND
I/O
L15P_0
GCLK4
I/O
L02P_0
VREF_0
I/O
L12P_0
I/O
L10P_0
I/O
L06P_0
I/O
L03P_0
I/O
L34N_1
I/O
L34P_1
VCCO_0
VCCO_1
I/O
L15N_0
GCLK5
I/O
L09P_0
I/O
L03N_0
I/O
L33P_1
I/O
L32N_1
I/O
L32P_1
VCCAUX
GND
INPUT
INPUT
TDO
I/O
L36N_1
A21
I/O
L30N_1
A19
I/O
L29N_1
A17
I/O
L29P_1
A16
I/O
L12N_0
I/O
L09N_0
I/O
L33N_1
INPUT
GND
INPUT
L39P_1
VREF_1
I/O
L36P_1
A20
I/O
L30P_1
A18
I/O
L26N_1
A15
INPUT
INPUT
I/O
INPUT INPUT
GND
G
H
J
VREF_0
L39N_1
L28P_1
I/O
L25N_1
A13
I/O
L25P_1
A12
I/O
L26P_1
A14
INPUT INPUT
I/O
L28N_1
VCCO_1
INPUT INPUT
GND VCCINT
VCCINT GND
GND VCCINT
VCCINT GND
GND
L35N_1
L35P_1
INPUT
L31P_1
VREF_1
I/O
L22N_1
A11
I/O
L22P_1
A10
I/O
L21N_1
RHCLK7
INPUT
L31N_1
INPUT INPUT
L27N_1
I/O
L24P_1
L27P_1
I/O
L21P_1
IRDY1
INPUT
L23P_1
VREF_1
I/O
L20P_1
RHCLK4
INPUT
L23N_1
I/O
L24N_1
VCCAUX
VCCO_1
GND
K
L
RHCLK6
I/O
L18N_1
TRDY1
RHCLK3
I/O
L16P_1
A8
I/O
L16N_1
A9
I/O
L20N_1
RHCLK5
I/O
L18P_1
RHCLK2
INPUT INPUT
GND
L19N_1
L19P_1
INPUT INPUT
I/O
L14P_1
A6
I/O
L14N_1
A7
I/O
L17P_1
I/O
L17N_1
RHCLK0 RHCLK1
INPUT
L15N_1
INPUT
L11P_1
L15P_1
L11N_1
M
N
P
R
T
VREF_1 VREF_1
I/O
INPUT
L12P_1
I/O
L12N_1
A3
I/O
L13P_1
A4
I/O
L13N_1
A5
INPUT
GND
VCCO_1
VCCAUX
GND
VREF_2
VREF_1
A2
INPUT
INPUT
I/O
L10N_1
VREF_1
INPUT
VREF_2
I/O
L07P_1
I/O
L07N_1
I/O
L10P_1
INPUT INPUT
GND
L04N_1
L04P_1
VREF_1
I/O
L03N_1
A1
I/O
I/O
INPUT
L23N_2 VREF_2
I/O
L08N_1
I/O
L08P_1
I/O
L09P_1
I/O
L09N_1
VCCO_2
L19N_2
I/O
L03P_1
A0
I/O
L19P_2
I/O
L23P_2
I/O
L25N_2
I/O
L27N_2
I/O
L05P_1
I/O
L05N_1
VCCO_1
INPUT
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCO_2
GND
L18P_2
L22P_2
L02N_1
U
V
W
Y
L27P_2
L29N_2
L31N_2
L06P_1
L06N_1
GCLK2
AWAKE
LDC0
I/O
L17N_2
GCLK1
I/O
L18N_2
GCLK3
I/O
L22N_2
DOUT
I/O
L26N_2
D1
I/O
L02P_1
LDC1
I/O
L01N_1
LDC2
I/O
L25P_2
I/O
L29P_2
I/O
L31P_2
GND
I/O
L20N_2
MOSI
I/O
L32P_2
D0
I/O
L24N_2
D3
I/O
L01P_1
HDC
I/O
L21N_2
I/O
L28N_2
VCCO_2
VCCO_2
GND
DONE
CSI_B
DIN/MISO
I/O
L17P_2
GCLK0
I/O
L24P_2
INIT_B
I/O
L26P_2
D2
I/O
L32N_2
CCLK
I/O
L20P_2
I/O
L21P_2
I/O
L28P_2
I/O
L30P_2
I/O
L30N_2
GND
Bank 2
DS557_4_22_030911
Figure 22: FGG400 Package Footprint (Top View)
DS557 (v4.2) June 12, 2014
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Product Specification
99
Spartan-3AN FPGA Family: Pinout Descriptions
FGG484: 484-Ball Fine-Pitch Ball Grid Array
Xilinx has issued a discontinuation notice for the XC3S1400AN in the FG(G)484 package. See XCN13016: Product
Discontinuation Notice For Selected Spartan-3AN FPGA Products.
The 484-ball fine-pitch ball grid array, FGG484, supports the XC3S700AN and the discontinued XC3S1400AN FPGAs.
There are three pinout differences, as described in Table 81.
Table 78 lists all the FGG484 package pins. They are sorted by bank number and then by pin name. Pins that form a
differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type (as
defined in Table 62).
The shaded rows indicate pinout differences between the XC3S700AN and the XC3S1400AN FPGAs. The XC3S700AN
has three unconnected balls, indicated as N.C. and with a black diamond (◆) in Table 78 and Figure 23.
An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at:
www.xilinx.com/support/documentation/data_sheets/s3a_pin.zip.
Pinout Table
Table 78: Spartan-3AN FGG484 Pinout (Cont’d)
Table 78: Spartan-3AN FGG484 Pinout
FGG484
FGG484
Bank
0
Pin Name
IO_L14N_0
Ball
E13
F13
C13
D13
A13
B13
E12
C12
A11
A12
C11
B11
E11
D11
C10
A10
A8
Type
I/O
Bank
0
Pin Name
IO_L01N_0
Ball
D18
E17
C19
D19
A20
B20
F15
E15
A18
C18
A19
B19
C17
D17
C16
D16
E14
C14
A17
B17
C15
D15
A15
A16
A14
B15
Type
I/O
0
IO_L14P_0
I/O
0
IO_L01P_0
I/O
0
IO_L15N_0
I/O
0
IO_L02N_0
IO_L02P_0/VREF_0
IO_L03N_0
IO_L03P_0
I/O
0
IO_L15P_0
I/O
0
VREF
I/O
0
IO_L16N_0
I/O
0
0
IO_L16P_0
I/O
0
I/O
0
IO_L17N_0/GCLK5
IO_L17P_0/GCLK4
IO_L18N_0/GCLK7
IO_L18P_0/GCLK6
IO_L19N_0/GCLK9
IO_L19P_0/GCLK8
IO_L20N_0/GCLK11
IO_L20P_0/GCLK10
IO_L21N_0
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
I/O
0
IO_L04N_0
IO_L04P_0
I/O
0
0
I/O
0
0
IO_L05N_0
IO_L05P_0
I/O
0
0
I/O
0
0
IO_L06N_0
IO_L06P_0/VREF_0
IO_L07N_0
IO_L07P_0
I/O
0
0
VREF
I/O
0
0
0
0
I/O
0
0
IO_L08N_0
IO_L08P_0
I/O
0
IO_L21P_0
I/O
0
I/O
0
IO_L22N_0
I/O
0
IO_L09N_0
IO_L09P_0
I/O
0
IO_L22P_0
A9
I/O
0
I/O
0
IO_L23N_0
E10
D10
C9
I/O
0
IO_L10N_0
IO_L10P_0
I/O
0
IO_L23P_0
I/O
0
I/O
0
IO_L24N_0/VREF_0
IO_L24P_0
VREF
I/O
0
IO_L11N_0
IO_L11P_0
I/O
0
B9
0
I/O
0
IO_L25N_0
C8
I/O
0
IO_L12N_0/VREF_0
IO_L12P_0
VREF
I/O
0
IO_L25P_0
B8
I/O
0
0
IO_L26N_0
A6
I/O
0
IO_L13N_0
IO_L13P_0
I/O
0
IO_L26P_0
A7
I/O
0
I/O
0
IO_L27N_0
C7
I/O
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Product Specification
100
Spartan-3AN FPGA Family: Pinout Descriptions
Table 78: Spartan-3AN FGG484 Pinout (Cont’d)
Table 78: Spartan-3AN FGG484 Pinout (Cont’d)
FGG484
FGG484
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pin Name
IO_L27P_0
Ball
Type
I/O
Bank
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Name
Ball
B14
B18
B5
Type
VCCO
VCCO
VCCO
VCCO
VCCO
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
I/O
D7
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
IO_L28N_0
IO_L28P_0
IO_L29N_0
IO_L29P_0
IO_L30N_0
IO_L30P_0
IO_L31N_0
IO_L31P_0
IO_L32N_0
IO_L32P_0
IO_L33N_0
IO_L33P_0
IO_L34N_0
IO_L34P_0
IO_L35N_0
IO_L35P_0
IO_L36N_0/PUDC_B
IO_L36P_0/VREF_0
IP_0
A5
I/O
B6
I/O
D6
I/O
F14
F9
C6
I/O
D8
I/O
IO_L01N_1/LDC2
IO_L01P_1/HDC
IO_L02N_1/LDC0
IO_L02P_1/LDC1
IO_L03N_1/A1
IO_L03P_1/A0
IO_L05N_1
Y21
AA22
W20
W19
T18
T17
W21
Y22
V20
V19
V22
W22
U21
U22
U19
U20
T22
T20
T19
R20
R22
R21
P22
P20
P18
R19
N21
N22
N19
N20
N17
N18
L22
M22
L20
E9
I/O
B4
I/O
A4
I/O
D5
I/O
C5
I/O
B3
I/O
A3
I/O
IO_L05P_1
I/O
F8
I/O
IO_L06N_1
I/O
E7
I/O
IO_L06P_1
I/O
E6
I/O
IO_L07N_1
I/O
F7
I/O
IO_L07P_1
I/O
A2
DUAL
VREF
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VREF
VREF
VREF
VCCO
IO_L09N_1
I/O
B2
IO_L09P_1
I/O
E16
E8
IO_L10N_1
I/O
IP_0
IO_L10P_1
I/O
IP_0
F10
F12
F16
G10
G11
G12
G13
G14
G15
G16
G7
IO_L11N_1
I/O
IP_0
IO_L11P_1
I/O
IP_0
IO_L13N_1
I/O
IP_0
IO_L13P_1
I/O
IP_0
IO_L14N_1
I/O
IP_0
IO_L14P_1
I/O
IP_0
IO_L15N_1/VREF_1
IO_L15P_1
VREF
I/O
IP_0
IP_0
IO_L17N_1/A3
IO_L17P_1/A2
IO_L18N_1/A5
IO_L18P_1/A4
IO_L19N_1/A7
IO_L19P_1/A6
IO_L20N_1/A9
IO_L20P_1/A8
IO_L21N_1/RHCLK1
IO_L21P_1/RHCLK0
IO_L22N_1/TRDY1/RHCLK3
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
RHCLK
RHCLK
RHCLK
IP_0
IP_0
IP_0
G9
IP_0
H10
H13
H14
G8
IP_0
IP_0
IP_0/VREF_0
IP_0/VREF_0
IP_0/VREF_0
VCCO_0
H12
H9
B10
DS557 (v4.2) June 12, 2014
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Product Specification
101
Spartan-3AN FPGA Family: Pinout Descriptions
Table 78: Spartan-3AN FGG484 Pinout (Cont’d)
Table 78: Spartan-3AN FGG484 Pinout (Cont’d)
FGG484
FGG484
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Name
IO_L22P_1/RHCLK2
IO_L24N_1/RHCLK5
IO_L24P_1/RHCLK4
IO_L25N_1/RHCLK7
IO_L25P_1/IRDY1/RHCLK6
IO_L26N_1/A11
IO_L26P_1/A10
IO_L28N_1
Ball
L21
M20
M18
K19
K20
J22
Type
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
DUAL
DUAL
I/O
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Pin Name
IP_L08P_1
Ball
P15
R18
R17
N16
N15
M16
M17
L16
M15
K16
L15
K15
K14
H18
H17
J15
J16
H15
H16
E21
J17
K21
P17
P21
V21
W5
Type
INPUT
VREF
INPUT
VREF
INPUT
INPUT
INPUT
INPUT
VREF
INPUT
INPUT
INPUT
VREF
INPUT
INPUT
VREF
INPUT
INPUT
VREF
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
DUAL
DUAL
DUAL
DUAL
I/O
IP_L12N_1/VREF_1
IP_L12P_1
IP_L16N_1/VREF_1
IP_L16P_1
IP_L23N_1
K22
L19
L18
J20
IP_L23P_1
IP_L27N_1
IO_L28P_1
I/O
IP_L27P_1/VREF_1
IP_L31N_1
IO_L29N_1/A13
IO_L29P_1/A12
IO_L30N_1/A15
IO_L30P_1/A14
IO_L32N_1
DUAL
DUAL
DUAL
DUAL
I/O
J21
IP_L31P_1
G22
H22
K18
K17
H20
H21
F21
F22
G20
G19
H19
J18
IP_L35N_1
IP_L35P_1/VREF_1
IP_L39N_1
IO_L32P_1
I/O
IP_L39P_1
IO_L33N_1/A17
IO_L33P_1/A16
IO_L34N_1/A19
IO_L34P_1/A18
IO_L36N_1
DUAL
DUAL
DUAL
DUAL
I/O
IP_L43N_1/VREF_1
IP_L43P_1
IP_L47N_1
IP_L47P_1/VREF_1
VCCO_1
IO_L36P_1
I/O
VCCO_1
IO_L37N_1
I/O
VCCO_1
IO_L37P_1
I/O
VCCO_1
IO_L38N_1
F20
E20
F18
F19
D22
E22
D20
D21
C21
C22
B21
B22
G17
G18
R16
R15
P16
I/O
VCCO_1
IO_L38P_1
I/O
VCCO_1
IO_L40N_1
I/O
IO_L01N_2/M0
IO_L01P_2/M1
IO_L02N_2/CSO_B
IO_L02P_2/M2
IO_L03N_2
IO_L40P_1
I/O
V6
IO_L41N_1
I/O
Y4
IO_L41P_1
I/O
W4
IO_L42N_1
I/O
AA3
AB2
AA4
AB3
Y5
IO_L42P_1
I/O
IO_L03P_2
I/O
IO_L44N_1/A21
IO_L44P_1/A20
IO_L45N_1/A23
IO_L45P_1/A22
IO_L46N_1/A25
IO_L46P_1/A24
IP_L04N_1/VREF_1
IP_L04P_1
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
VREF
INPUT
INPUT
IO_L04N_2
I/O
IO_L04P_2
I/O
IO_L05N_2
I/O
IO_L05P_2
W6
I/O
IO_L06N_2
AB5
AB4
Y6
I/O
IO_L06P_2
I/O
IO_L07N_2
I/O
IO_L07P_2
W7
I/O
IP_L08N_1
IO_L08N_2
AB6
I/O
DS557 (v4.2) June 12, 2014
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Product Specification
102
Spartan-3AN FPGA Family: Pinout Descriptions
Table 78: Spartan-3AN FGG484 Pinout (Cont’d)
Table 78: Spartan-3AN FGG484 Pinout (Cont’d)
FGG484
FGG484
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Pin Name
IO_L08P_2
Ball
AA6
W9
Type
I/O
Bank
2
Pin Name
IO_L28P_2/D2
Ball
AA17
AB18
AB17
V15
Type
DUAL
I/O
IO_L09N_2/VS2
IO_L09P_2/RDWR_B
IO_L10N_2
DUAL
DUAL
I/O
2
IO_L29N_2
IO_L29P_2
IO_L30N_2
IO_L30P_2
IO_L31N_2
IO_L31P_2
IO_L32N_2
IO_L32P_2
IO_L33N_2
IO_L33P_2
IO_L34N_2
IO_L34P_2
IO_L35N_2
IO_L35P_2
IO_L36N_2/CCLK
IO_L36P_2/D0/DIN/MISO
IP_2
V9
2
I/O
AB7
Y7
2
I/O
IO_L10P_2
I/O
2
V14
I/O
IO_L11N_2/VS0
IO_L11P_2/VS1
IO_L12N_2
Y8
DUAL
DUAL
I/O
2
V16
I/O
W8
2
W16
AA19
AB19
V17
I/O
AB8
AA8
Y10
V10
AB9
Y9
2
I/O
IO_L12P_2
I/O
2
I/O
IO_L13N_2
I/O
2
I/O
IO_L13P_2
I/O
2
W18
W17
Y18
I/O
IO_L14N_2/D6
IO_L14P_2/D7
IO_L15N_2
DUAL
DUAL
I/O
2
I/O
2
I/O
AB10
AA10
AB11
Y11
V11
U11
Y12
W12
AB12
AA12
U12
V12
Y13
AB13
AB14
AA14
Y14
W13
AA15
2
AA21
AB21
AA20
AB20
P12
I/O
IO_L15P_2
I/O
2
I/O
IO_L16N_2/D4
IO_L16P_2/D5
IO_L17N_2/GCLK13
IO_L17P_2/GCLK12
IO_L18N_2/GCLK15
IO_L18P_2/GCLK14
IO_L19N_2/GCLK1
IO_L19P_2/GCLK0
IO_L20N_2/GCLK3
IO_L20P_2/GCLK2
IO_L21N_2
DUAL
DUAL
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
I/O
2
DUAL
DUAL
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
2
2
2
IP_2
R10
R11
R9
2
IP_2
2
IP_2
2
IP_2
T13
2
IP_2
T14
2
IP_2
T9
2
IP_2
U10
U15
2
IP_2
IO_L21P_2
I/O
XC3S1400AN: IP_2
2
2
U16
U7
INPUT
INPUT
XC3S700AN: N.C. ◆
IO_L22N_2/MOSI/CSI_B
IO_L22P_2
DUAL
I/O
XC3S1400AN: IP_2
XC3S700AN: N.C. ◆
IO_L23N_2
I/O
2
2
2
2
2
2
2
2
2
2
IP_2
U8
V7
INPUT
INPUT
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
IO_L23P_2
I/O
IP_2
IO_L24N_2/DOUT
IO_L24P_2/AWAKE
IO_L25N_2
DUAL
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
R12
R13
R14
T10
T11
T15
T16
T7
AB15 PWR MGMT
Y15
W15
U13
V13
I/O
I/O
IO_L25P_2
IO_L26N_2/D3
IO_L26P_2/INIT_B
IO_L27N_2
DUAL
DUAL
I/O
Y16
IO_L27P_2
AB16
Y17
I/O
IO_L28N_2/D1
DUAL
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Spartan-3AN FPGA Family: Pinout Descriptions
Table 78: Spartan-3AN FGG484 Pinout (Cont’d)
Table 78: Spartan-3AN FGG484 Pinout (Cont’d)
FGG484
FGG484
Bank
Pin Name
Ball
Type
Bank
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Name
IO_L20P_3
Ball
K3
L3
Type
I/O
XC3S1400AN: IP_2/VREF_2
2
T8
VREF
XC3S700AN: N.C. ◆
IO_L21N_3/LHCLK1
IO_L21P_3/LHCLK0
IO_L22N_3/IRDY2/LHCLK3
IO_L22P_3/LHCLK2
IO_L24N_3/LHCLK5
IO_L24P_3/LHCLK4
IO_L25N_3/LHCLK7
IO_L25P_3/TRDY2/LHCLK6
IO_L26N_3
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
I/O
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IP_2/VREF_2
VCCO_2
V8
AA13
AA18
AA5
AA9
U14
U9
D2
C1
C2
B1
VREF
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
I/O
L5
L1
VCCO_2
K1
M2
M1
M4
M3
N3
N1
P2
P1
P5
P3
N4
M5
R2
R1
R4
R3
T4
VCCO_2
VCCO_2
VCCO_2
VCCO_2
IO_L01N_3
IO_L01P_3
IO_L02N_3
IO_L02P_3
IO_L03N_3
IO_L03P_3
IO_L05N_3
IO_L05P_3
IO_L06N_3
IO_L06P_3
IO_L07N_3
IO_L07P_3
IO_L08N_3
IO_L08P_3
IO_L09N_3
IO_L09P_3
IO_L10N_3
IO_L10P_3
IO_L12N_3
IO_L12P_3
IO_L13N_3
IO_L13P_3
IO_L14N_3
IO_L14P_3
IO_L16N_3
IO_L16P_3
IO_L17N_3/VREF_3
IO_L17P_3
IO_L18N_3
IO_L18P_3
IO_L20N_3
I/O
IO_L26P_3/VREF_3
IO_L28N_3
VREF
I/O
I/O
I/O
IO_L28P_3
I/O
E4
I/O
IO_L29N_3
I/O
D3
G5
G6
E1
I/O
IO_L29P_3
I/O
I/O
IO_L30N_3
I/O
I/O
IO_L30P_3
I/O
I/O
IO_L32N_3
I/O
D1
E3
I/O
IO_L32P_3
I/O
I/O
IO_L33N_3
I/O
F4
I/O
IO_L33P_3
I/O
G4
F3
I/O
IO_L34N_3
I/O
I/O
IO_L34P_3
R5
T3
I/O
H6
H5
J5
I/O
IO_L36N_3
I/O
I/O
IO_L36P_3/VREF_3
IO_L37N_3
T1
VREF
I/O
I/O
U2
U1
V3
V1
U5
T5
K6
I/O
IO_L37P_3
I/O
F1
I/O
IO_L38N_3
I/O
F2
I/O
IO_L38P_3
I/O
G1
G3
H3
H4
H1
H2
J1
I/O
IO_L40N_3
I/O
I/O
IO_L40P_3
I/O
I/O
IO_L41N_3
U4
U3
W2
W1
W3
V4
Y2
Y1
AA2
I/O
I/O
IO_L41P_3
I/O
I/O
IO_L42N_3
I/O
I/O
IO_L42P_3
I/O
VREF
I/O
IO_L43N_3
I/O
J3
IO_L43P_3
I/O
K4
I/O
IO_L44N_3
I/O
K5
I/O
IO_L44P_3
I/O
K2
I/O
IO_L45N_3
I/O
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Spartan-3AN FPGA Family: Pinout Descriptions
Table 78: Spartan-3AN FGG484 Pinout (Cont’d)
Table 78: Spartan-3AN FGG484 Pinout (Cont’d)
FGG484
FGG484
Bank
Pin Name
IO_L45P_3
Ball
AA1
J8
Type
I/O
Bank
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin Name
Ball
Type
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
C3
3
IP_3/VREF_3
IP_3/VREF_3
IP_L04N_3/VREF_3
IP_L04P_3
IP_L11N_3
IP_L11P_3
IP_L15N_3/VREF_3
IP_L15P_3
IP_L19N_3
IP_L19P_3
IP_L23N_3
IP_L23P_3
IP_L27N_3
IP_L27P_3
IP_L31N_3
IP_L31P_3
IP_L35N_3
IP_L35P_3
IP_L39N_3
IP_L39P_3
IP_L46N_3/VREF_3
IP_L46P_3
VCCO_3
VREF
VREF
VREF
INPUT
INPUT
INPUT
VREF
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VREF
INPUT
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
GND
D14
D9
3
R6
3
H7
F11
F17
F6
3
H8
3
K8
3
J7
G2
3
L8
G21
J11
J13
J14
J19
J4
3
K7
3
M8
L7
3
3
M6
M7
N9
3
3
J9
3
N8
K10
K12
L11
L13
L17
L2
3
N5
3
N6
3
P8
3
N7
3
R8
3
P7
L6
3
T6
L9
3
R7
M10
M12
M14
M21
N11
N13
P10
P14
P19
P4
3
E2
3
VCCO_3
J2
3
VCCO_3
J6
3
VCCO_3
N2
3
VCCO_3
P6
3
VCCO_3
V2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A1
GND
A22
AA11
AA16
AA7
AB1
AB22
B12
B16
B7
GND
GND
GND
GND
GND
P9
GND
GND
T12
T2
GND
GND
GND
GND
T21
U17
U6
GND
GND
GND
GND
GND
GND
W10
W14
GND
C20
GND
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105
Spartan-3AN FPGA Family: Pinout Descriptions
Table 78: Spartan-3AN FGG484 Pinout (Cont’d)
FGG484
Bank
GND
GND
Pin Name
Ball
Y20
Y3
Type
GND
GND
GND
GND
VCCAUX SUSPEND
VCCAUX DONE
VCCAUX PROG_B
VCCAUX TCK
U18
Y19
C4
PWR MGMT
CONFIG
CONFIG
JTAG
A21
F5
VCCAUX TDI
JTAG
VCCAUX TDO
E19
D4
JTAG
VCCAUX TMS
JTAG
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
D12
E18
E5
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
H11
L4
M19
P11
V18
V5
W11
J10
J12
K11
K13
K9
L10
L12
L14
M11
M13
M9
N10
N12
N14
P13
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106
Spartan-3AN FPGA Family: Pinout Descriptions
User I/Os by Bank
Table 79 and Table 80 indicate how the user-I/O pins are distributed between the four I/O banks on the FGG484 package.
The AWAKE pin is counted as a dual-purpose I/O.
Table 79: User I/Os Per Bank for the XC3S700AN in the FGG484 Package
All Possible I/O Pins by Type
Package
I/O Bank
Maximum I/Os
Edge
I/O
INPUT
DUAL
VREF
CLK
8
Top
0
1
2
3
92
94
58
17
1
8
8
Right
Bottom
Left
33
15
30
21
0
8
92
43
11
9
8
94
61
17
8
8
Total
372
195
60
52
33
32
(1)
Table 80: User I/Os Per Bank for the Discontinued XC3S1400AN in the FGG484 Package
All Possible I/O Pins by Type
Package
Edge
I/O Bank
Maximum I/Os
I/O
58
INPUT
DUAL
1
VREF
CLK
8
Top
0
1
2
3
92
94
17
15
13
17
62
8
8
Right
Bottom
Left
33
30
21
0
8
95
43
10
8
8
94
61
8
Total
375
195
52
34
32
Notes:
1. Xilinx has issued a discontinuation notice for the XC3S1400AN in the FG(G)484 package. See XCN13016: Product Discontinuation Notice
For Selected Spartan-3AN FPGA Products.
Footprint Migration Differences
Table 81 summarizes the three footprint and functionality differences between the XC3S700AN and the XC3S1400AN
FPGAs that can affect migration between devices available in the FGG484 package. All other pins unconditionally migrate
between the Spartan-3AN devices available in the FGG484 package.
Spartan-3AN FPGAs are pin compatible with the same density Spartan-3A FPGAs in the FG(G)484 package, although the
Spartan-3A FPGAs require an external configuration source.
In Table 81, the arrow (→) indicates that this pin can unconditionally migrate from the device on the left to the device on the
right. Migration in the other direction is possible depending on how the pin is configured for the device on the right.
(1)
Table 81: FGG484 XC3S700AN to XC3S1400AN Footprint Migration/Differences
FGG484 Ball
Bank
XC3S700AN
Migration
XC3S1400AN (Discontinued)
T8
U7
2
2
2
N.C.
N.C.
N.C.
→
→
→
3
INPUT/VREF
INPUT
U16
INPUT
Number of Differences:
Notes:
1. Xilinx has issued a discontinuation notice for the XC3S1400AN in the FG(G)484 package. See XCN13016: Product Discontinuation Notice
For Selected Spartan-3AN FPGA Products.
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Product Specification
107
Spartan-3AN FPGA Family: Pinout Descriptions
Bank 0
X-Ref Target - Figure 23
FGG484 Footprint
1
2
3
4
5
6
7
8
9
10
11
Left Half of FGG484
Package (Top View)
I/O
L36N_0
PUDC_B
I/O
I/O
I/O
L31P_0
I/O
L28N_0
I/O
L26N_0
I/O
L26P_0
I/O
L22N_0
I/O
L22P_0
I/O
L21P_0
GND
A
B
C
D
E
F
L18N_0
L33P_0
GCLK7
I/O
L36P_0
VREF_0
I/O
I/O
L02P_3
I/O
I/O
L31N_0
I/O
L28P_0
I/O
L25P_0
I/O
L24P_0
VCCO_0
VCCO_0
GND
L19P_0
L33N_0
GCLK8
I/O: Unrestricted,
I/O
I/O
general-purpose user I/O
195
I/O
L01P_3
I/O
L02N_3
I/O
L32P_0
I/O
L29P_0
I/O
L27N_0
I/O
L25N_0
I/O
L21N_0
GND
L24N_0
L19N_0
VREF_0
GCLK9
I/O
I/O
L06P_3
I/O
L01N_3
I/O
I/O
L32N_0
I/O
L29N_0
I/O
L27P_0
I/O
L30N_0
I/O
L23P_0
INPUT: Unrestricted,
general-purpose input pin
TMS
GND
L20P_0
L03P_3
60-
62
GCLK10
I/O
I/O
L06N_3
I/O
I/O
L03N_3
I/O
L35N_0
I/O
L34P_0
I/O
L30P_0
I/O
L23N_0
VCCO_3
VCCAUX
INPUT
L20N_0
L07N_3
GCLK11
DUAL: Configuration pins,
then possible user I/O
51
I/O
L12N_3
I/O
L12P_3
I/O
I/O
L07P_3
I/O
L35P_0
I/O
L34N_0
VCCO_0
TDI
GND
INPUT
GND
L08P_3
I/O
I/O
I/O
I/O
I/O
INPUT
VREF: User I/O or input
GND
INPUT
INPUT INPUT INPUT
G
H
J
L13N_3
L13P_3
L08N_3
L05N_3
L05P_3
VREF_0
33-
34
voltage reference for bank
INPUT
L04N_3
VREF_3
I/O
L16N_3
I/O
L16P_3
I/O
L14N_3
I/O
L14P_3
I/O
L09P_3
I/O
L09N_3
INPUT INPUT
L04P_3 VREF_0
VCCAUX
INPUT
CLK: User I/O, input, or
clock buffer input
I/O
L17N_3
VREF_3
32
2
I/O
L17P_3
I/O
L10N_3
INPUT INPUT
L11P_3 VREF_3
VCCO_3
VCCO_3
GND
GND VCCINT GND
VCCINT GND VCCINT
GND VCCINT GND
VCCINT GND VCCINT
I/O
L22P_3
LHCLK2
I/O
L20N_3
I/O
L20P_3
I/O
L18N_3
I/O
L18P_3
I/O
L10P_3
INPUT INPUT
SUSPEND: Dedicated
SUSPEND and
dual-purpose AWAKE
Power Management pins
K
L
L15P_3
L11N_3
I/O
L22N_3
IRDY2
LHCLK3
I/O
L21N_3
LHCLK1
I/O
L21P_3
LHCLK0
INPUT
L15N_3
VREF_3
INPUT
L19P_3
VCCAUX
GND
GND
I/O
L25P_3
TRDY2
LHCLK6
CONFIG: Dedicated
configuration pins
I/O
L24P_3
LHCLK4 LHCLK5
I/O
L24N_3
I/O
L25N_3
LHCLK7
I/O
L30P_3
INPUT INPUT INPUT
L23N_3
M
N
P
R
T
2
L23P_3
L19N_3
I/O
I/O
L26N_3
I/O
L30N_3
INPUT INPUT INPUT INPUT INPUT
L31N_3
VCCO_3
L26P_3
VCCINT GND
L31P_3
L35P_3
L27P_3
L27N_3
JTAG: Dedicated JTAG
port pins
VREF_3
4
I/O
L28P_3
I/O
L28N_3
I/O
L29P_3
I/O
L29N_3
INPUT INPUT
VCCO_3
VCCAUX
GND
GND
GND
L39P_3
L35N_3
GND: Ground
I/O
L32P_3
I/O
L32N_3
I/O
L33P_3
I/O
L33N_3
I/O
INPUT INPUT INPUT
INPUT INPUT INPUT
53
24
15
10
L34P_3 VREF_3 L46P_3
L39N_3
INPUT
I/O
L36P_3
VREF_3
INPUT
L46N_3
VREF_3
I/O
L36N_3
I/O
L34N_3
I/O
L40P_3
INPUT
VREF_2
INPUT INPUT
INPUT
VREF_2
GND
VCCO: Output voltage
supply for bank
VREF_2 VREF_2
◆
I/O
INPUT
I/O
L37P_3
I/O
L37N_3
I/O
L41P_3
I/O
L41N_3
I/O
L40N_3
VCCO_2
GND
INPUT
INPUT
U
V
W
Y
L17P_2
◆
GCLK12
VCCINT: Internal core
supply voltage (+1.2V)
I/O
L01P_2
M1
I/O
I/O
I/O
L38P_3
I/O
L38N_3
I/O
L43P_3
INPUT
VREF_2
I/O
L13P_2
VCCO_3
VCCAUX
INPUT
L09P_2
L17N_2
RDWR_B
GCLK13
I/O
L02P_2
M2
I/O
L01N_2
M0
I/O
L11P_2
VS1
I/O
L09N_2
VS2
I/O
L42P_3
I/O
L42N_3
I/O
L43N_3
I/O
L05P_2
I/O
L07P_2
VCCAUX
GND
VCCAUX: Auxiliary supply
voltage (+3.3V)
I/O
L02N_2
CSO_B
I/O
L11N_2
VS0
I/O
L14P_2
D7
I/O
L16P_2
D5
I/O
L44P_3
I/O
L44N_3
I/O
L05N_2
I/O
L07N_2
I/O
L10P_2
I/O
L13N_2
GND
N.C.: Not connected
(XC3S700AN only)
3
◆
A
A
I/O
L45P_3
I/O
L45N_3
I/O
L03N_2
I/O
L04N_2
I/O
L08P_2
I/O
L12P_2
I/O
L15P_2
VCCO_2
VCCO_2
GND
GND
I/O
L14N_2
D6
I/O
L16N_2
D4
A
B
I/O
L03P_2
I/O
L04P_2
I/O
L06P_2
I/O
L06N_2
I/O
L08N_2
I/O
L10N_2
I/O
L12N_2
I/O
L15N_2
GND
Bank 2
DS557_4_23_030911
Figure 23: FGG484 Package Footprint (Top View)
DS557 (v4.2) June 12, 2014
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Product Specification
108
Spartan-3AN FPGA Family: Pinout Descriptions
Bank 0
12
13
14
15
16
17
18
19
20
21
22
Right Half of FGG484
Package (Top View)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TCK
GND
L18P_0
L12N_0
A
B
C
D
E
F
L16N_0
L13N_0
L12P_0
L10N_0
L05N_0
L06N_0
L03N_0
GCLK6
VREF_0
I/O
L06P_0
VREF_0
I/O
L45N_1
A23
I/O
L45P_1
A22
I/O
L16P_0
I/O
L13P_0
I/O
L10P_0
I/O
L03P_0
VCCO_0
VCCO_0
GND
GND
I/O
L17P_0
GCLK4
I/O
L44N_1
A21
I/O
L44P_1
A20
I/O
L15N_0
I/O
L09P_0
I/O
L11N_0
I/O
L08N_0
I/O
L07N_0
I/O
L05P_0
I/O
L02N_0
GND
I/O
L02P_0
VREF_0
I/O
L15P_0
I/O
L11P_0
I/O
L08P_0
I/O
L07P_0
I/O
L01N_0
I/O
L42N_1
I/O
L42P_1
I/O
L41N_1
VCCAUX
GND
I/O
L17N_0
GCLK5
I/O
L14N_0
I/O
L09N_0
I/O
L04P_0
I/O
L01P_0
I/O
L38P_1
I/O
L41P_1
VCCAUX
VCCO_1
INPUT
INPUT
TDO
I/O
L34N_1
A19
I/O
L34P_1
A18
I/O
L14P_0
I/O
L04N_0
I/O
L40N_1
I/O
L40P_1
I/O
L38N_1
VCCO_0
INPUT
GND
I/O
L46N_1
A25
I/O
L46P_1
A24
I/O
L30N_1
A15
I/O
I/O
INPUT INPUT INPUT INPUT INPUT
INPUT
GND
G
H
J
L36P_1
L36N_1
I/O
L33N_1
A17
I/O
L33P_1
A16
I/O
L30P_1
A14
INPUT
INPUT
INPUT INPUT
L39P_1
I/O
L37N_1
INPUT INPUT
L47P_1
VREF_0
L47N_1
L39N_1
VREF_1
INPUT
L43N_1
VREF_1
I/O
L29N_1
A13
I/O
L29P_1
A12
I/O
L26N_1
A11
INPUT
I/O
L37P_1
VCCO_1
VCCINT GND
GND VCCINT
GND
GND
L43P_1
I/O
L25P_1
IRDY1
INPUT
L35P_1
VREF_1
I/O
L25N_1
RHCLK7
I/O
L26P_1
A10
INPUT INPUT
L35N_1
I/O
L32P_1
I/O
L32N_1
VCCO_1
K
L
L31N_1
RHCLK6
I/O
L22N_1
TRDY1
RHCLK3
I/O
L22P_1
I/O
L21N_1
RHCLK2 RHCLK1
INPUT INPUT
I/O
L28P_1
I/O
L28N_1
VCCINT GND VCCINT
GND VCCINT GND
VCCINT GND VCCINT
INPUT VCCINT GND
GND
L31P_1
L27N_1
INPUT
L27P_1
VREF_1
I/O
L24P_1
RHCLK4
I/O
L24N_1
RHCLK5
I/O
L21P_1
RHCLK0
INPUT INPUT
VCCAUX
GND
M
N
P
R
T
L23N_1
L23P_1
INPUT
L16N_1
VREF_1
I/O
L20N_1
A9
I/O
L20P_1
A8
I/O
L19N_1
A7
I/O
L19P_1
A6
I/O
L18N_1
A5
I/O
L18P_1
A4
INPUT
L16P_1
I/O
L17N_1
A3
I/O
L15N_1
VREF_1
INPUT INPUT
I/O
L15P_1
VCCO_1
VCCO_1
GND
L08P_1
L08N_1
INPUT
L04N_1
VREF_1
INPUT
L12N_1
VREF_1
I/O
L17P_1
A2
INPUT INPUT INPUT INPUT
VREF_2 VREF_2 VREF_2 L04P_1
INPUT
L12P_1
I/O
L13P_1
I/O
L14P_1
I/O
L14N_1
I/O
L03P_1
A0
I/O
L03N_1
A1
INPUT INPUT
I/O
L13N_1
I/O
L11P_1
I/O
L11N_1
GND
INPUT INPUT
I/O
GND
VREF_2 VREF_2
I/O
L20N_2
GCLK3
INPUT
I/O
L10N_1
I/O
L10P_1
I/O
L09N_1
I/O
L09P_1
VCCO_2
L26N_2
INPUT
GND
U
V
W
Y
◆
D3
I/O
I/O
I/O
I/O
L30N_2
I/O
L31N_2
I/O
L33N_2
I/O
L06P_1
I/O
L06N_1
I/O
L07N_1
VCCAUX
VCCO_1
L20P_2
L26P_2
L30P_2
INIT_B
GCLK2
I/O
I/O
L02P_1
LDC1
I/O
L02N_1
LDC0
I/O
I/O
L25P_2
I/O
L31P_2
I/O
L34N_2
I/O
L33P_2
I/O
L05N_1
I/O
L07P_1
GND
L23P_2
L18P_2
GCLK14
I/O
I/O
L28N_2
D1
I/O
L01N_1
LDC2
I/O
L21N_2
I/O
L23N_2
I/O
L25N_2
I/O
L27N_2
I/O
L34P_2
I/O
L05P_1
DONE
GND
L18N_2
GCLK15
I/O
I/O
I/O
L28P_2
D2
I/O
I/O
L01P_1
HDC
A
A
I/O
L22P_2
I/O
L32N_2
I/O
L35N_2
VCCO_2
VCCO_2
GND
L19P_2
L24N_2
L36N_2
GCLK0
DOUT
CCLK
I/O
I/O
L36P_2
D0
I/O
I/O
A
B
I/O
L21P_2
I/O
L27P_2
I/O
L29P_2
I/O
L29N_2
I/O
L32P_2
I/O
L35P_2
L22N_2
MOSI
GND
L19N_2
L24P_2
GCLK1
AWAKE
CSI_B
DIN/MISO
Bank 2
DS557_4_23_030911
Figure 23: FGG484 Package Footprint (Top View)
DS557 (v4.2) June 12, 2014
www.xilinx.com
Product Specification
109
Spartan-3AN FPGA Family: Pinout Descriptions
FGG676: 676-Ball Fine-Pitch Ball Grid Array
The 676-ball fine-pitch ball grid array, FGG676, supports the XC3S1400AN FPGA.
Table 82 lists all the FGG676 package pins. They are sorted by bank number and then by pin name. Pins that form a
differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type (as
defined in Table 62).
The XC3S1400AN has 17 unconnected balls, indicated as N.C. in Table 82 and Figure 24.
An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at:
www.xilinx.com/support/documentation/data_sheets/s3a_pin.zip.
Pinout Table
Table 82: Spartan-3AN FGG676 Pinout (Cont’d)
Table 82: Spartan-3AN FGG676 Pinout
FGG676
FGG676
Bank
0
Pin Name
IO_L18N_0
Ball
A18
B18
B17
C17
E15
F15
C16
D17
C15
D16
A15
B15
F14
E14
J14
Type
I/O
Bank
0
Pin Name
IO_L01N_0
Ball
F20
G20
F19
G19
C22
D22
C23
D23
A22
B23
G17
H17
B21
C21
D21
E21
C20
D20
K16
J16
Type
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
0
IO_L18P_0
I/O
0
IO_L01P_0
IO_L02N_0
IO_L02P_0/VREF_0
IO_L05N_0
IO_L05P_0
IO_L06N_0
IO_L06P_0
IO_L07N_0
IO_L07P_0
IO_L08N_0
IO_L08P_0
IO_L09N_0
IO_L09P_0
IO_L10N_0
IO_L10P_0
IO_L11N_0
IO_L11P_0
IO_L12N_0
IO_L12P_0
IO_L13N_0
IO_L13P_0
IO_L14N_0
IO_L14P_0/VREF_0
IO_L15N_0
IO_L15P_0
IO_L16N_0
IO_L16P_0
IO_L17N_0
IO_L17P_0
0
IO_L19N_0
I/O
0
0
IO_L19P_0
I/O
0
0
IO_L20N_0/VREF_0
IO_L20P_0
VREF
I/O
0
0
0
0
IO_L21N_0
I/O
0
0
IO_L21P_0
I/O
0
0
IO_L22N_0
I/O
0
0
IO_L22P_0
I/O
0
0
IO_L23N_0
I/O
0
0
IO_L23P_0
I/O
0
0
IO_L24N_0
I/O
0
0
IO_L24P_0
I/O
0
0
IO_L25N_0/GCLK5
IO_L25P_0/GCLK4
IO_L26N_0/GCLK7
IO_L26P_0/GCLK6
IO_L27N_0/GCLK9
IO_L27P_0/GCLK8
IO_L28N_0/GCLK11
IO_L28P_0/GCLK10
IO_L29N_0
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
I/O
0
0
K14
A14
B14
G13
F13
C13
B13
B12
A12
C12
D13
F12
E12
D11
C11
0
0
0
0
0
0
0
0
0
0
0
E17
F17
A20
B20
A19
B19
H15
G15
C18
D18
0
0
0
0
0
IO_L29P_0
I/O
0
0
IO_L30N_0
I/O
0
0
IO_L30P_0
I/O
0
0
IO_L31N_0
I/O
0
0
IO_L31P_0
I/O
0
0
IO_L32N_0/VREF_0
IO_L32P_0
VREF
I/O
0
0
0
DS557 (v4.2) June 12, 2014
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Product Specification
110
Spartan-3AN FPGA Family: Pinout Descriptions
Table 82: Spartan-3AN FGG676 Pinout (Cont’d)
Table 82: Spartan-3AN FGG676 Pinout (Cont’d)
FGG676
FGG676
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pin Name
IO_L33N_0
Ball
B10
A10
D10
C10
H12
G12
B9
Type
I/O
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
Pin Name
Ball
A23
C4
Type
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VREF
VREF
VREF
VREF
N.C.
IP_0
IP_0
IP_0
IP_0
IP_0
IP_0
IP_0
IP_0
IP_0
IP_0
IP_0
IP_0
IP_0
IP_0
IP_0
IP_0
IO_L33P_0
IO_L34N_0
IO_L34P_0
IO_L35N_0
IO_L35P_0
IO_L36N_0
IO_L36P_0
IO_L37N_0
IO_L37P_0
IO_L38N_0
IO_L38P_0
IO_L39N_0
IO_L39P_0
IO_L40N_0
IO_L40P_0
IO_L41N_0
IO_L41P_0
IO_L42N_0
IO_L42P_0
IO_L43N_0
IO_L43P_0
IO_L44N_0
IO_L44P_0
IO_L45N_0
IO_L45P_0
IO_L46N_0
IO_L46P_0
IO_L47N_0
IO_L47P_0
IO_L48N_0
IO_L48P_0
IO_L51N_0
IO_L51P_0
IO_L52N_0/PUDC_B
IO_L52P_0/VREF_0
IP_0
I/O
I/O
D12
D15
D19
E11
E18
E20
F10
G14
G16
H13
H18
J10
J13
J15
D7
I/O
I/O
I/O
I/O
A9
I/O
D9
I/O
E10
B8
I/O
I/O
A8
I/O
K12
J12
D8
I/O
I/O
I/O
C8
I/O
C6
I/O
IP_0/VREF_0
IP_0/VREF_0
IP_0/VREF_0
IP_0/VREF_0
N.C.
B6
I/O
D14
G11
J17
A24
B24
D5
C7
I/O
B7
I/O
K11
J11
D6
I/O
I/O
N.C.
N.C.
I/O
N.C.
N.C.
C5
I/O
N.C.
E9
N.C.
B4
I/O
N.C.
F18
E6
N.C.
A4
I/O
N.C.
N.C.
H10
G10
H9
I/O
N.C.
F9
N.C.
I/O
N.C.
G18
B5
N.C.
I/O
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
IO_L01N_1/LDC2
IO_L01P_1/HDC
IO_L02N_1/LDC0
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
DUAL
DUAL
DUAL
G9
E7
I/O
B11
B16
B22
E8
I/O
F7
I/O
B3
I/O
A3
I/O
E13
E19
H11
H16
Y21
Y20
AD25
G8
F8
DUAL
VREF
INPUT
INPUT
INPUT
INPUT
A5
IP_0
A7
IP_0
A13
A17
IP_0
DS557 (v4.2) June 12, 2014
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Product Specification
111
Spartan-3AN FPGA Family: Pinout Descriptions
Table 82: Spartan-3AN FGG676 Pinout (Cont’d)
Table 82: Spartan-3AN FGG676 Pinout (Cont’d)
FGG676
FGG676
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Name
IO_L02P_1/LDC1
IO_L03N_1/A1
IO_L03P_1/A0
IO_L04N_1
IO_L04P_1
IO_L05N_1
IO_L05P_1
IO_L06N_1
IO_L06P_1
IO_L07N_1/VREF_1
IO_L07P_1
IO_L08N_1
IO_L08P_1
IO_L09N_1
IO_L09P_1
IO_L10N_1
IO_L10P_1
IO_L11N_1
IO_L11P_1
IO_L12N_1
IO_L12P_1
IO_L13N_1
IO_L13P_1
IO_L14N_1
IO_L14P_1
IO_L15N_1
IO_L15P_1
IO_L17N_1
IO_L17P_1
IO_L18N_1
IO_L18P_1
IO_L19N_1
IO_L19P_1
IO_L21N_1
IO_L21P_1
IO_L22N_1
IO_L22P_1
IO_L23N_1/VREF_1
IO_L23P_1
IO_L25N_1/A3
Ball
AE26
AC24
AC23
W21
W20
AC25
AD26
AB26
AC26
AB24
AB23
V19
Type
DUAL
DUAL
DUAL
I/O
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Name
IO_L25P_1/A2
Ball
R21
T24
T23
R17
R18
R26
R25
P20
P21
P25
P26
N24
P23
N19
P18
M25
M26
N21
P22
M23
L24
N17
N18
K26
K25
M20
N20
J25
Type
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
DUAL
DUAL
I/O
IO_L26N_1/A5
IO_L26P_1/A4
IO_L27N_1/A7
IO_L27P_1/A6
IO_L29N_1/A9
IO_L29P_1/A8
IO_L30N_1/RHCLK1
IO_L30P_1/RHCLK0
IO_L31N_1/TRDY1/RHCLK3
IO_L31P_1/RHCLK2
IO_L33N_1/RHCLK5
IO_L33P_1/RHCLK4
IO_L34N_1/RHCLK7
IO_L34P_1/IRDY1/RHCLK6
IO_L35N_1/A11
IO_L35P_1/A10
IO_L37N_1
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
V18
I/O
AA23
AA22
U20
I/O
I/O
I/O
V21
I/O
AA25
AA24
U18
I/O
I/O
IO_L37P_1
I/O
I/O
IO_L38N_1/A13
IO_L38P_1/A12
IO_L39N_1/A15
IO_L39P_1/A14
IO_L41N_1
DUAL
DUAL
DUAL
DUAL
I/O
U19
I/O
Y23
I/O
Y22
I/O
T20
I/O
U21
I/O
IO_L41P_1
I/O
Y25
I/O
IO_L42N_1/A17
IO_L42P_1/A16
IO_L43N_1/A19
IO_L43P_1/A18
IO_L45N_1
DUAL
DUAL
DUAL
DUAL
I/O
Y24
I/O
T17
I/O
T18
I/O
J26
V22
I/O
M22
M21
K22
K23
M18
M19
J22
W23
V25
I/O
IO_L45P_1
I/O
I/O
IO_L46N_1
I/O
V24
I/O
IO_L46P_1
I/O
U22
I/O
IO_L47N_1
I/O
V23
I/O
IO_L47P_1
I/O
R20
I/O
IO_L49N_1
I/O
R19
I/O
IO_L49P_1
J23
I/O
U24
VREF
I/O
IO_L50N_1
K21
L22
G24
I/O
U23
IO_L50P_1
I/O
R22
DUAL
IO_L51N_1
I/O
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Product Specification
112
Spartan-3AN FPGA Family: Pinout Descriptions
Table 82: Spartan-3AN FGG676 Pinout (Cont’d)
Table 82: Spartan-3AN FGG676 Pinout (Cont’d)
FGG676
FGG676
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Name
IO_L51P_1
Ball
G23
K20
L20
F24
F25
L17
L18
F23
E24
K18
K19
G22
F22
J20
Type
I/O
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Pin Name
IP_L44P_1/VREF_1
IP_L48N_1
IP_L48P_1
IP_L52N_1/VREF_1
IP_L52P_1
IP_L65N_1
IP_L65P_1/VREF_1
VCCO_1
Ball
H26
H24
H23
G25
G26
B25
B26
AB25
E25
H22
L19
Type
VREF
INPUT
INPUT
VREF
INPUT
INPUT
VREF
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
DUAL
DUAL
DUAL
DUAL
I/O
IO_L53N_1
I/O
IO_L53P_1
I/O
IO_L54N_1
I/O
IO_L54P_1
I/O
IO_L55N_1
I/O
IO_L55P_1
I/O
IO_L56N_1
I/O
IO_L56P_1
I/O
VCCO_1
IO_L57N_1
I/O
VCCO_1
IO_L57P_1
I/O
VCCO_1
IO_L58N_1
I/O
VCCO_1
L25
IO_L58P_1/VREF_1
IO_L59N_1
VREF
I/O
VCCO_1
N22
T19
T25
W22
AD4
AC4
AA7
Y7
VCCO_1
IO_L59P_1
J19
I/O
VCCO_1
IO_L60N_1
D26
E26
D24
D25
H21
J21
I/O
VCCO_1
IO_L60P_1
I/O
IO_L01N_2/M0
IO_L01P_2/M1
IO_L02N_2/CSO_B
IO_L02P_2/M2
IO_L05N_2
IO_L05P_2
IO_L06N_2
IO_L06P_2
IO_L07N_2
IO_L07P_2
IO_L08N_2
IO_L08P_2
IO_L09N_2
IO_L09P_2
IO_L10N_2
IO_L10P_2
IO_L11N_2
IO_L11P_2
IO_L12N_2
IO_L12P_2
IO_L13N_2
IO_L13P_2
IO_L14N_2
IO_L14P_2
IO_L61N_1
I/O
IO_L61P_1
I/O
IO_L62N_1/A21
IO_L62P_1/A20
IO_L63N_1/A23
IO_L63P_1/A22
IO_L64N_1/A25
IO_L64P_1/A24
IP_L16N_1
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
INPUT
INPUT
VREF
INPUT
VREF
INPUT
INPUT
VREF
INPUT
INPUT
INPUT
VREF
INPUT
INPUT
INPUT
Y9
C25
C26
G21
H20
Y26
W25
V26
W26
U26
U25
R24
R23
N25
N26
N23
M24
L23
K24
H25
W9
I/O
AF3
AE3
AF4
AE4
AD6
AC6
W10
V10
AE6
AF5
AE7
AD7
AA10
Y10
U11
V11
AB7
AC8
I/O
I/O
I/O
I/O
IP_L16P_1
I/O
IP_L20N_1/VREF_1
IP_L20P_1
I/O
I/O
IP_L24N_1/VREF_1
IP_L24P_1
I/O
I/O
IP_L28N_1
I/O
IP_L28P_1/VREF_1
IP_L32N_1
I/O
I/O
IP_L32P_1
I/O
IP_L36N_1
I/O
IP_L36P_1/VREF_1
IP_L40N_1
I/O
I/O
IP_L40P_1
I/O
IP_L44N_1
I/O
DS557 (v4.2) June 12, 2014
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Product Specification
113
Spartan-3AN FPGA Family: Pinout Descriptions
Table 82: Spartan-3AN FGG676 Pinout (Cont’d)
Table 82: Spartan-3AN FGG676 Pinout (Cont’d)
FGG676
FGG676
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Pin Name
IO_L15N_2
Ball
Type
I/O
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Pin Name
IO_L35N_2
Ball
Type
I/O
AC9
U15
IO_L15P_2
AB9
I/O
IO_L35P_2
IO_L36N_2/D1
IO_L36P_2/D2
IO_L37N_2
IO_L37P_2
IO_L38N_2
IO_L38P_2
IO_L39N_2
IO_L39P_2
IO_L40N_2
IO_L40P_2
IO_L41N_2
IO_L41P_2
IO_L42N_2
IO_L42P_2
IO_L43N_2
IO_L43P_2
IO_L44N_2
IO_L44P_2
IO_L45N_2
IO_L45P_2
IO_L46N_2
IO_L46P_2
IO_L47N_2
IO_L47P_2
IO_L48N_2
IO_L48P_2
IO_L51N_2
IO_L51P_2
IO_L52N_2/CCLK
IO_L52P_2/D0/DIN/MISO
IP_2
V15
I/O
IO_L16N_2
W12
V12
I/O
AE18
AF18
AE19
AF19
AB16
AC16
AE20
AF20
AC19
AD19
AC20
AD20
U16
DUAL
DUAL
I/O
IO_L16P_2
I/O
IO_L17N_2/VS2
IO_L17P_2/RDWR_B
IO_L18N_2
AA12
Y12
DUAL
DUAL
I/O
I/O
AF8
I/O
IO_L18P_2
AE8
I/O
I/O
IO_L19N_2/VS0
IO_L19P_2/VS1
IO_L20N_2
AF9
DUAL
DUAL
I/O
I/O
AE9
I/O
W13
V13
I/O
IO_L20P_2
I/O
I/O
IO_L21N_2
AC12
AB12
AF10
AE10
AC11
AD11
AE12
AF12
Y13
I/O
I/O
IO_L21P_2
I/O
I/O
IO_L22N_2/D6
IO_L22P_2/D7
IO_L23N_2
DUAL
DUAL
I/O
I/O
V16
I/O
Y17
I/O
IO_L23P_2
I/O
AA17
AD21
AE21
AC21
AD22
V17
I/O
IO_L24N_2/D4
IO_L24P_2/D5
IO_L25N_2/GCLK13
IO_L25P_2/GCLK12
IO_L26N_2/GCLK15
IO_L26P_2/GCLK14
IO_L27N_2/GCLK1
IO_L27P_2/GCLK0
IO_L28N_2/GCLK3
IO_L28P_2/GCLK2
IO_L29N_2
DUAL
DUAL
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
I/O
I/O
I/O
I/O
AA13
AE13
AF13
AA14
Y14
I/O
I/O
W17
I/O
AA18
AB18
AE23
AF23
AE25
AF25
AE24
AF24
AA19
AB13
AB17
AB20
AC7
I/O
I/O
AE14
AF14
AC14
AD14
AB15
AC15
W15
V14
I/O
I/O
I/O
IO_L29P_2
I/O
I/O
IO_L30N_2/MOSI/CSI_B
IO_L30P_2
DUAL
I/O
DUAL
DUAL
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
IO_L31N_2
I/O
IO_L31P_2
I/O
IP_2
IO_L32N_2/DOUT
IO_L32P_2/AWAKE
IO_L33N_2
AE15
DUAL
IP_2
AD15 PWR MGMT
IP_2
AD17
AE17
Y15
I/O
I/O
IP_2
IO_L33P_2
IP_2
AC13
AC17
AC18
IO_L34N_2/D3
IO_L34P_2/INIT_B
DUAL
DUAL
IP_2
AA15
IP_2
DS557 (v4.2) June 12, 2014
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Product Specification
114
Spartan-3AN FPGA Family: Pinout Descriptions
Table 82: Spartan-3AN FGG676 Pinout (Cont’d)
Table 82: Spartan-3AN FGG676 Pinout (Cont’d)
FGG676
FGG676
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
Pin Name
Ball
AD9
AD10
AD16
AF2
AF7
Y11
Type
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
N.C.
Bank
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Name
IO_L05N_3
Ball
K8
K9
E4
D3
F4
E3
G4
F5
H6
J7
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
IP_2
IP_2
IP_2
IP_2
IP_2
IP_2
IO_L05P_3
IO_L06N_3
IO_L06P_3
IO_L07N_3
IO_L07P_3
IO_L09N_3
IO_L09P_3
IO_L10N_3
IO_L10P_3
IO_L11N_3
IO_L11P_3
IO_L13N_3
IO_L13P_3
IO_L14N_3
IO_L14P_3
IO_L15N_3
IO_L15P_3
IO_L17N_3
IO_L17P_3
IO_L18N_3
IO_L18P_3
IO_L19N_3
IO_L19P_3
IO_L21N_3
IO_L21P_3
IO_L22N_3
IO_L22P_3
IO_L23N_3
IO_L23P_3
IO_L25N_3
IO_L25P_3
IO_L26N_3
IO_L26P_3
IO_L27N_3
IO_L27P_3
IO_L28N_3
IO_L28P_3
IO_L29N_3/VREF_3
IO_L29P_3
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
N.C.
AA9
AA20
AB6
AB10
AC10
AD12
AF15
AF17
AF22
Y16
F2
E1
J6
K7
F3
G3
L9
AA8
AC5
AC22
AD5
Y18
N.C.
N.C.
L10
H1
H2
L7
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
Y19
N.C.
K6
J4
N.C.
AD23
W18
Y8
N.C.
N.C.
N.C.
J5
N.C.
N.C.
M9
M10
K4
K5
K2
K3
L3
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
IO_L01N_3
IO_L01P_3
IO_L02N_3
IO_L02P_3
IO_L03N_3
IO_L03P_3
AB8
AB14
AB19
AE5
AE11
AE16
AE22
W11
W16
J9
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
I/O
L4
M7
M8
M3
M4
M6
M5
M1
M2
J8
I/O
B1
I/O
B2
I/O
H7
I/O
G6
I/O
DS557 (v4.2) June 12, 2014
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Product Specification
115
Spartan-3AN FPGA Family: Pinout Descriptions
Table 82: Spartan-3AN FGG676 Pinout (Cont’d)
Table 82: Spartan-3AN FGG676 Pinout (Cont’d)
FGG676
FGG676
Bank
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Name
IO_L30N_3
Ball
N4
N5
N2
N1
N7
N6
P2
P1
P3
P4
P10
N9
R2
R1
R4
R3
T4
Type
I/O
Bank
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Name
IO_L52N_3
Ball
W4
W3
Y2
Type
I/O
IO_L30P_3
I/O
IO_L52P_3
IO_L53N_3
IO_L53P_3
IO_L55N_3
IO_L55P_3
IO_L56N_3
IO_L56P_3
IO_L57N_3
IO_L57P_3
IO_L59N_3
IO_L59P_3
IO_L60N_3
IO_L60P_3
IO_L61N_3
IO_L61P_3
IO_L63N_3
IO_L63P_3
IO_L64N_3
IO_L64P_3
IO_L65N_3
IO_L65P_3
IP_L04N_3/VREF_3
IP_L04P_3
I/O
IO_L31N_3
I/O
I/O
IO_L31P_3
I/O
Y1
I/O
IO_L32N_3/LHCLK1
IO_L32P_3/LHCLK0
IO_L33N_3/IRDY2/LHCLK3
IO_L33P_3/LHCLK2
IO_L34N_3/LHCLK5
IO_L34P_3/LHCLK4
IO_L35N_3/LHCLK7
IO_L35P_3/TRDY2/LHCLK6
IO_L36N_3
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
I/O
AA3
AA2
U8
I/O
I/O
I/O
U7
I/O
Y6
I/O
Y5
I/O
V6
I/O
V7
I/O
AC1
AB1
V8
I/O
IO_L36P_3/VREF_3
IO_L37N_3
VREF
I/O
I/O
I/O
IO_L37P_3
I/O
U9
I/O
IO_L38N_3
I/O
W6
W7
AC3
AC2
AD2
AD1
C1
I/O
IO_L38P_3
T3
I/O
I/O
IO_L39N_3
P6
P7
R6
R5
P9
P8
U4
T5
I/O
I/O
IO_L39P_3
I/O
I/O
IO_L40N_3
I/O
I/O
IO_L40P_3
I/O
I/O
IO_L41N_3
I/O
VREF
INPUT
INPUT
INPUT
VREF
INPUT
INPUT
INPUT
VREF
INPUT
INPUT
INPUT
INPUT
INPUT
VREF
INPUT
INPUT
INPUT
IO_L41P_3
I/O
C2
IO_L42N_3
I/O
IP_L08N_3
IP_L08P_3
D1
IO_L42P_3
I/O
D2
IO_L43N_3
R9
R10
U2
U1
R7
R8
V2
V1
T9
I/O
IP_L12N_3/VREF_3
IP_L12P_3
H4
IO_L43P_3/VREF_3
IO_L44N_3
VREF
I/O
G5
G1
G2
J2
IP_L16N_3
IP_L16P_3
IO_L44P_3
I/O
IO_L45N_3
I/O
IP_L20N_3/VREF_3
IP_L20P_3
IO_L45P_3
I/O
J3
IO_L47N_3
I/O
IP_L24N_3
IP_L24P_3
K1
IO_L47P_3
I/O
J1
IO_L48N_3
I/O
IP_L46N_3
IP_L46P_3
V4
IO_L48P_3
T10
V5
U5
U6
T7
I/O
U3
IO_L49N_3
I/O
IP_L50N_3/VREF_3
IP_L50P_3
W2
W1
Y4
IO_L49P_3
I/O
IO_L51N_3
I/O
IP_L54N_3
IP_L54P_3
IO_L51P_3
I/O
Y3
DS557 (v4.2) June 12, 2014
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Product Specification
116
Spartan-3AN FPGA Family: Pinout Descriptions
Table 82: Spartan-3AN FGG676 Pinout (Cont’d)
Table 82: Spartan-3AN FGG676 Pinout (Cont’d)
FGG676
FGG676
Bank
3
Pin Name
IP_L58N_3/VREF_3
IP_L58P_3
IP_L62N_3
IP_L62P_3
IP_L66N_3/VREF_3
IP_L66P_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
GND
Ball
AA5
AA4
AB4
AB3
AE2
AE1
AB2
E2
Type
VREF
INPUT
INPUT
INPUT
VREF
INPUT
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
GND
Bank
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin Name
Ball
C14
C19
C24
F1
Type
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
3
3
3
3
F6
3
F11
F16
F21
F26
H3
3
3
3
H5
3
L2
3
L8
H8
3
P5
H14
H19
J24
K10
K17
L1
3
T2
3
T8
3
W5
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A1
GND
A6
GND
GND
A11
A16
A21
A26
AA1
AA6
AA11
AA16
AA21
AA26
AD3
AD8
AD13
AD18
AD24
AF1
AF6
AF11
AF16
AF21
AF26
C3
GND
L6
GND
GND
L11
L13
L15
L21
L26
M12
M14
M16
N3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
N8
GND
GND
N11
N15
P12
P16
P19
P24
R11
R13
R15
T1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
T6
GND
C9
GND
T12
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117
Spartan-3AN FPGA Family: Pinout Descriptions
Table 82: Spartan-3AN FGG676 Pinout (Cont’d)
Table 82: Spartan-3AN FGG676 Pinout (Cont’d)
FGG676
FGG676
Bank
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin Name
Ball
T14
T16
T21
T26
U10
U13
U17
V3
Type
GND
Bank
Pin Name
Ball
M17
N12
N13
N14
N16
P11
P13
P14
P15
R12
R14
R16
T11
T13
T15
U12
Type
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
GND
GND
GND
GND
GND
GND
GND
W8
GND
W14
W19
W24
V20
AB21
A2
GND
GND
GND
VCCAUX SUSPEND
VCCAUX DONE
VCCAUX PROG_B
VCCAUX TCK
PWR MGMT
CONFIG
CONFIG
JTAG
A25
G7
VCCAUX TDI
JTAG
VCCAUX TDO
E23
D4
JTAG
VCCAUX TMS
JTAG
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
AB5
AB11
AB22
E5
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
E16
E22
J18
K13
L5
N10
P17
T22
U14
V9
K15
L12
L14
L16
M11
M13
M15
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Product Specification
118
Spartan-3AN FPGA Family: Pinout Descriptions
User I/Os by Bank
Table 83 indicates how the 502 available user-I/O pins are distributed between the four I/O banks on the FGG676 package.
The AWAKE pin is counted as a dual-purpose I/O.
Table 83: User I/Os Per Bank for the XC3S1400AN in the FGG676 Package
All Possible I/O Pins by Type
Package
I/O Bank
Maximum I/Os
Edge
I/O
INPUT
DUAL
VREF
CLK
8
Top
0
1
2
3
120
130
120
132
502
82
20
1
9
Right
Bottom
Left
67
15
30
21
0
10
10
9
8
67
14
8
97
18
8
Total
313
67
52
38
32
Footprint Migration Differences
The XC3S1400AN is the only Spartan-3AN FPGA offered in the FGG676 package. The XC3S1400AN FPGA is pin
compatible with the Spartan-3A XC3S1400A FPGA in the FG(G)676 package, although the Spartan-3A FPGA requires an
external configuration source.
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Product Specification
119
Spartan-3AN FPGA Family: Pinout Descriptions
X-Ref Target - Figure 24
FGG676 Footprint
Bank 0
1
2
3
4
5
6
7
8
9
10
11
12
13
Left Half of FGG676
Package (Top View)
I/O
I/O
I/O
I/O
I/O
I/O
GND
INPUT
GND
INPUT
GND
INPUT
A
B
C
D
E
F
L51P_0
L45P_0
L38P_0
L36P_0
L33P_0
L29P_0
PROG_B
I/O
L28P_0
GCLK10
I/O
L02N_3
I/O
L02P_3
I/O
L51N_0
I/O
L45N_0
I/O
L41P_0
I/O
L42P_0
I/O
L38N_0
I/O
L36N_0
I/O
L33N_0
I/O
L29N_0
VCCO_0
VCCO_0
INPUT
L04N_3
VREF_3
I/O
L28N_0
GCLK11
INPUT
L04P_3
I/O
L44P_0
I/O
L41N_0
I/O
L42N_0
I/O
L40P_0
I/O
L34P_0
I/O
L32P_0
I/O
L30N_0
I/O: Unrestricted,
GND
INPUT
TMS
GND
general-purpose user I/O
313
67
I/O
L32N_0
VREF_0
INPUT INPUT
L08N_3
I/O
L06P_3
I/O
INPUT
I/O
I/O
L37N_0
I/O
L34N_0
I/O
L30P_0
N.C.
INPUT
L08P_3
L44N_0 VREF_0 L40N_0
INPUT: Unrestricted,
general-purpose input pin
I/O
L11P_3
I/O
L07P_3
I/O
L06N_3
I/O
L48N_0
I/O
L37P_0
I/O
L31P_0
VCCO_3
VCCAUX
N.C.
VCCO_0
VCCO_0
N.C.
N.C.
INPUT
I/O
L52P_0
VREF_0
I/O
L27P_0
GCLK8
I/O
L11N_3
I/O
L14N_3
I/O
L07N_3
I/O
L09P_3
I/O
L48P_0
I/O
L31N_0
GND
GND
INPUT
I/O
GND
DUAL: Configuration pins,
then possible user I/O
51
I/O
L52N_0
PUDC_B
I/O
L27N_0
GCLK9
INPUT INPUT
L16N_3
I/O
L14P_3
I/O
L09N_3
INPUT
L12P_3
I/O
L03P_3
I/O
L47P_0
INPUT
I/O
L35P_0
TDI
G
H
J
L16P_3
L46P_0 VREF_0
INPUT
L12N_3
VREF_3
I/O
L17N_3
I/O
L17P_3
I/O
L10N_3
I/O
L03N_3
I/O
L47N_0
I/O
L46N_0
I/O
L35N_0
SUSPEND: Dedicated
SUSPEND and
dual-purpose AWAKE
Power Management pins
VCCO_3
VCCO_0
GND
GND
INPUT
INPUT
VCCAUX
2
INPUT
L20N_3
VREF_3
INPUT
L24P_3
INPUT
L20P_3
I/O
L19N_3
I/O
L19P_3
I/O
L13N_3
I/O
L10P_3
I/O
L01P_3
I/O
L01N_3
I/O
INPUT
I/O
L39P_0
L43P_0
INPUT
L24N_3
I/O
L23N_3
I/O
L23P_3
I/O
L22N_3
I/O
L22P_3
I/O
L18P_3
I/O
L13P_3
I/O
L05N_3
I/O
L05P_3
I/O
GND
I/O
L39N_0
VREF: User I/O or input
K
L
L43N_0
voltage reference for bank
38
32
2
I/O
L25N_3
I/O
L25P_3
I/O
L18N_3
I/O
L15N_3
I/O
L15P_3
VCCO_3
VCCAUX
VCCO_3
GND
GND
GND VCCINT GND
VCCINT GND VCCINT
GND VCCINT VCCINT
VCCINT GND VCCINT
GND VCCINT GND
VCCINT GND VCCINT
CLK: User I/O, input, or
clock buffer input
I/O
L29N_3
VREF_3
I/O
L29P_3
I/O
L27N_3
I/O
L27P_3
I/O
L28P_3
I/O
L28N_3
I/O
L26N_3
I/O
L26P_3
I/O
L21N_3
I/O
L21P_3
M
N
P
R
T
I/O
I/O
L32P_3
LHCLK0 LHCLK1
I/O
L32N_3
I/O
L31P_3
I/O
L31N_3
I/O
L30N_3
I/O
L30P_3
L35P_3
TRDY2
VCCAUX
GND
GND
CONFIG: Dedicated
configuration pins
LHCLK6
I/O
I/O
L33P_3
LHCLK2
I/O
L34N_3
LHCLK5 LHCLK4
I/O
L34P_3
I/O
L35N_3
LHCLK7
I/O
L39N_3
I/O
L39P_3
I/O
L41P_3
I/O
L41N_3
L33N_3
IRDY2
VCCO_3
LHCLK3
I/O
L36P_3
VREF_3
I/O
L43P_3
VREF_3
I/O
L36N_3
I/O
L37P_3
I/O
L37N_3
I/O
L40P_3
I/O
L40N_3
I/O
L45N_3
I/O
L45P_3
I/O
L43N_3
JTAG: Dedicated JTAG
port pins
4
I/O
L38P_3
I/O
L38N_3
I/O
L42P_3
I/O
L51P_3
I/O
L48N_3
I/O
L48P_3
VCCO_3
VCCO_3
GND
GND
GND: Ground
I/O
I/O
INPUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCCINT GND
L13N_2
77
36
23
14
17
U
V
W
Y
L44P_3
L44N_3
L46P_3
L42N_3
L49P_3
L51N_3
L56P_3
L56N_3
L61P_3
I/O
L47P_3
I/O
L47N_3
INPUT
L46N_3
I/O
L49N_3
I/O
L59N_3
I/O
L59P_3
I/O
L61N_3
I/O
L09P_2
I/O
L13P_2
I/O
L16P_2
I/O
L20P_2
VCCAUX
GND
VCCO: Output voltage
supply for bank
INPUT
L50N_3
VREF_3
INPUT
L50P_3
I/O
L52P_3
I/O
L52N_3
I/O
L63N_3
I/O
L63P_3
I/O
L05P_2
I/O
L09N_2
I/O
L16N_2
I/O
L20N_2
VCCO_3
VCCO_2
INPUT
GND
GND
I/O
L02P_2
M2
I/O
L17P_2
I/O
L25N_2
I/O
L53P_3
I/O
L53N_3
INPUT INPUT
L54P_3
I/O
L57P_3
I/O
L57N_3
I/O
L05N_2
I/O
L12P_2
VCCINT: Internal core
supply voltage (+1.2V)
N.C.
N.C.
L54N_3
RDWR_B GCLK13
INPUT
L58N_3
VREF_3
I/O
L02N_2
CSO_B
I/O
L17N_2
VS2
I/O
L25P_2
GCLK12
A
A
I/O
L55P_3
I/O
L55N_3
INPUT
L58P_3
INPUT
VREF_2 L12N_2
I/O
GND
GND
VCCAUX: Auxiliary supply
A
B
I/O
INPUT INPUT
INPUT
I/O
I/O
INPUT
I/O
voltage
VCCO_3
VCCAUX
VCCO_2
VCCAUX
INPUT
INPUT
GND
L60P_3
L62P_3
L62N_3
VREF_2 L14N_2
L15P_2 VREF_2
L21P_2
I/O
L01P_2
M1
A
C
I/O
L60N_3
I/O
L64P_3
I/O
L64N_3
I/O
I/O
L14P_2
I/O
INPUT
I/O
I/O
L21N_2
N.C.
N.C.
INPUT
L08P_2
L15N_2 VREF_2 L23N_2
N.C.: Not connected
I/O
L01N_2
M0
A
D
I/O
L65P_3
I/O
L65N_3
I/O
L08N_2
I/O
L11P_2
I/O
INPUT
L23P_2 VREF_2
GND
GND
INPUT INPUT
INPUT
L66N_3
VREF_3
I/O
L19P_2
VS1
I/O
L22P_2
D7
I/O
L24N_2
D4
I/O
L26N_2
GCLK15
A
E
INPUT
L66P_3
I/O
L06P_2
I/O
L07P_2
I/O
L10N_2
I/O
L11N_2
I/O
L18P_2
VCCO_2
VCCO_2
I/O
L19N_2
VS0
I/O
L22N_2
D6
I/O
L24P_2
D5
I/O
L26P_2
GCLK14
A
F
I/O
L06N_2
I/O
L07N_2
I/O
L10P_2
I/O
L18N_2
GND
INPUT
GND
INPUT
GND
Bank 2
DS557-4_07_032309
Figure 24: FGG676 Package Footprint (Top View)
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Product Specification
120
Spartan-3AN FPGA Family: Pinout Descriptions
Bank 0
14
15
16
17
18
19
20
21
22
23
24
25
26
Right Half of FGG676
Package (Top View)
I/O
L26N_0
GCLK7
I/O
I/O
I/O
I/O
I/O
GND
INPUT
GND
INPUT
N.C.
TCK
GND
A
B
C
D
E
F
L23N_0
L18N_0
L15N_0
L14N_0
L07N_0
I/O
L26P_0
GCLK6
I/O
L14P_0
VREF_0
INPUT
L65P_1
VREF_1
I/O
L23P_0
I/O
L19N_0
I/O
L18P_0
I/O
L15P_0
I/O
L09N_0
I/O
L07P_0
INPUT
L65N_1
VCCO_0
VCCO_0
N.C.
I/O
L63N_1
A23
I/O
L63P_1
A22
I/O
L22N_0
I/O
L21N_0
I/O
L19P_0
I/O
L17N_0
I/O
L11N_0
I/O
L09P_0
I/O
L05N_0
I/O
L06N_0
GND
GND
INPUT
VCCO_0
GND
INPUT
VREF_0
I/O
L22P_0
I/O
L21P_0
I/O
L17P_0
I/O
L11P_0
I/O
L10N_0
I/O
L05P_0
I/O
L06P_0
I/O
L61N_1
I/O
L61P_1
I/O
L60N_1
INPUT
I/O
L20N_0
VREF_0
I/O
L24P_0
I/O
L13N_0
I/O
L10P_0
I/O
L56P_1
I/O
L60P_1
VCCAUX
GND
VCCAUX
VCCO_1
INPUT
N.C.
INPUT
TDO
I/O
L58P_1
VREF_1
I/O
L24N_0
I/O
L20P_0
I/O
L13P_0
I/O
L02N_0
I/O
L01N_0
I/O
L56N_1
I/O
L54N_1
I/O
L54P_1
GND
GND
I/O
L02P_0
VREF_0
I/O
L64N_1
A25
INPUT
L52N_1
VREF_1
I/O
I/O
I/O
I/O
I/O
I/O
INPUT
INPUT
GND
INPUT
N.C.
G
H
J
L16P_0
L08N_0
L01P_0
L58N_1
L51P_1
L51N_1
L52P_1
I/O
L64P_1
A24
I/O
L62N_1
A21
INPUT
L44P_1
VREF_1
I/O
L16N_0
I/O
L08P_0
INPUT INPUT INPUT
VCCO_0
VCCO_1
INPUT
VCCAUX
GND
L48P_1
L48N_1
L44N_1
I/O
L25N_0
GCLK5
I/O
L62P_1
A20
I/O
L43N_1
A19
I/O
L43P_1
A18
I/O
INPUT
L12P_0 VREF_0
I/O
L59P_1
I/O
L59N_1
I/O
L49N_1
I/O
L49P_1
INPUT
GND
I/O
L25P_0
GCLK4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
INPUT
I/O
I/O
VCCINT
GND
L12N_0
K
L
L57N_1
L57P_1
L53N_1
L50N_1
L46N_1
L46P_1
L40P_1
L41P_1
L41N_1
I/O
L38P_1
A12
I/O
L55N_1
I/O
L55P_1
I/O
L53P_1
I/O
L50P_1
INPUT
L40N_1
VCCO_1
VCCO_1
VCCINT GND VCCINT
GND
GND
I/O
L42N_1
A17
I/O
L38N_1
A13
INPUT
L36P_1
VREF_1
I/O
L35N_1
A11
I/O
L35P_1
A10
I/O
I/O
I/O
I/O
GND VCCINT GND VCCINT
I/O
M
N
P
R
T
L47N_1
L47P_1
L45P_1
L45N_1
I/O
L39P_1
A14
I/O
L34N_1
RHCLK7
I/O
L42P_1
A16
I/O
L33N_1
RHCLK5
I/O
L37N_1
INPUT
L36N_1
INPUT INPUT
L32N_1
VCCO_1
VCCINT GND VCCINT
VCCINT VCCINT GND
VCCINT GND VCCINT
GND VCCINT GND
L39N_1
L32P_1
A15
I/O
I/O
I/O
L30N_1
RHCLK1 RHCLK0
I/O
L30P_1
I/O
L33P_1
RHCLK4
I/O
L31P_1
RHCLK2
I/O
L37P_1
L34P_1
IRDY1
L31N_1
TRDY1
RHCLK
VCCAUX
GND
GND
RHCLK6
3
I/O
L27N_1
A7
I/O
L27P_1
A6
I/O
I/O
L25N_1
A3
INPUT
L28P_1
VREF_1
I/O
L29P_1
A8
I/O
L29N_1
A9
I/O
L22P_1
I/O
L25P_1
L22N_1
A2
INPUT
L28N_1
I/O
L26P_1
A4
I/O
L26N_1
A5
I/O
L17N_1
I/O
L17P_1
I/O
VCCO_1
VCCAUX
VCCO_1
GND
L14N_1
GND
I/O
L23N_1
VREF_1
INPUT
L24N_1
VREF_1
I/O
I/O
I/O
I/O
I/O
L10N_1
I/O
I/O
I/O
INPUT
VCCAUX
GND
U
V
L35N_2
L42N_2
L12N_1
L12P_1
L14P_1
L21N_1
L23P_1
L24P_1
INPUT
L20N_1
VREF_1
I/O
L31P_2
I/O
L35P_2
I/O
L42P_2
I/O
L46N_2
I/O
L08P_1
I/O
L08N_1
I/O
L10P_1
I/O
L18N_1
I/O
L21P_1
I/O
L19P_1
I/O
L19N_1
I/O
I/O
I/O
I/O
I/O
INPUT INPUT
VCCO_2
VCCO_1
GND
GND
GND
N.C.
N.C.
W
Y
L31N_2
L46P_2
L04P_1
L04N_1
L18P_1
L16P_1
L20P_1
I/O
L27P_2
GCLK0
I/O
L34N_2
D3
I/O
L01P_1
HDC
I/O
L01N_1
LDC2
INPUT
VREF_2
I/O
L43N_2
I/O
L13P_1
I/O
L13N_1
I/O
L15P_1
I/O
INPUT
L16N_1
N.C.
L15N_1
I/O
L27N_2
GCLK1
I/O
L34P_2
INIT_B
A
A
I/O
I/O
INPUT
I/O
I/O
I/O
I/O
GND
INPUT
VCCO_2
GND
GND
L43P_2
L47N_2
VREF_2
L09P_1
L09N_1
L11P_1
L11N_1
I/O
I/O
L07N_1
VREF_1
A
B
I/O
L38N_2
I/O
L47P_2
I/O
L07P_1
I/O
L06N_1
L30N_2
MOSI
VCCO_2
VCCAUX
VCCO_1
INPUT
INPUT DONE
CSI_B
I/O
L03P_1
A0
I/O
L03N_1
A1
A
C
I/O
L29N_2
I/O
L30P_2
I/O
L38P_2
I/O
L40N_2
I/O
L41N_2
I/O
L45N_2
I/O
L05N_1
I/O
L06P_1
INPUT INPUT
N.C.
I/O
L32P_2
AWAKE
I/O
L02N_1
LDC0
A
D
I/O
I/O
I/O
I/O
I/O
I/O
I/O
INPUT
VCCO_2
GND
GND
L33N_2
GND
N.C.
L29P_2
L40P_2
L41P_2
L44N_2
L45P_2
L05P_1
I/O
L28N_2
GCLK3
I/O
L32N_2
DOUT
I/O
I/O
I/O
L52N_2
CCLK
I/O
L02P_1
LDC1
A
E
I/O
L37N_2
I/O
L39N_2
I/O
L44P_2
I/O
L48N_2
I/O
L51N_2
VCCO_2
L36N_2
L33P_2
D1
I/O
L52P_2
D0
I/O
L28P_2
GCLK2
I/O
INPUT
VREF_2
D2
A
F
INPUT
VREF_2
I/O
L37P_2
I/O
L39P_2
INPUT
VREF_2
I/O
L48P_2
I/O
L51P_2
GND
GND
L36P_2
DIN/MISO
Bank 2
DS557-4_08_030911
Figure 24: FGG676 Package Footprint (Top View)
DS557 (v4.2) June 12, 2014
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Product Specification
121
Spartan-3AN FPGA Family: Pinout Descriptions
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revision
02/26/2007
08/16/2007
09/12/2007
09/24/2007
12/12/2007
Initial release.
2.0
Updated for Production release of initial device. Noted that family is available in Pb-free packages only.
Minor updates to text.
2.0.1
2.1
Update thermal characteristics in Table 67.
3.0
Updated to Production status with Production release of final family member, XC3S50AN. Noted that
non-Pb-free packages may be available for selected devices. Updated thermal characteristics in
Table 67. Updated links.
06/02/2008
11/19/2009
3.1
3.2
Add Package Overview section. Removed VREF and INPUT designations and diamond symbols on
unconnected N.C. pins for XC3S700AN FGG484 in Table 78 and Figure 22 and for XC3S1400AN
FGG676 in Table 82 and Figure 23.
Renamed package ‘Footprint Area’ to ‘Body Area’ throughout document. Noted in Introduction that
references to Pb-free package code also apply to the Pb package. Added Pb packages to Table 65 and
Table 66. Changed Body Area of TQ144/TQG144 packages in Table 65. Corrected bank designation
for SUSPEND to VCCAUX. Noted that non-Pb-free (Pb) packages are available for selected devices.
Updated Table 79 and Figure 22 for I/O vs. Input pin counts.
12/02/2010
04/01/2011
4.0
4.1
Upgraded Notice of Disclaimer.
Updated the CLK description in Table 62. In Table 64, added device/package combinations for the
XC3S50AN and XC3S400AN in the FT(G)256 package and the XC3S1400AN in the FG(G)484
package. In Table 65, updated the maximum I/Os for the FG484/FGG484 packages, removed the
Mass column, and updated Note 1. In Table 65, changed the FTG256 link from PK115_FTG256,
FGG676 link from PK111_FGG676, and the TQG144 link from PK126_TQG144. Completely replaced
the section FTG256: 256-Ball Fine-Pitch, Thin Ball Grid Array with new information on the added
device/package combinations and new figures and tables. Revised U16, U7, and T8 in Table 78. Added
Table 80 and Table 81 and updated Figure 23.
06/11/2014
4.2
Xilinx has issued a discontinuation notice for the XC3S50AN in the FT(G)256 package and the
XC3S1400AN in the FG(G)484 package. See XCN13016: Product Discontinuation Notice For
Selected Spartan-3AN FPGA Products. This customer notice is highlighted in Table 64 with the
addition of Note 2 and Table 67 with the addition of Note 3. The FTG256: 256-Ball Fine-Pitch, Thin Ball
Grid Array, page 79 and FGG484: 484-Ball Fine-Pitch Ball Grid Array, page 100 package sections have
been updated due to this discontinuation notice including adding Note 1 to Table 71, Note 1 to
Table 73, Note 1 to Table 74, Note 1 to Table 75, and a note above FTG256 Footprint (XC3S50AN)
Figure 20. The FGG484: 484-Ball Fine-Pitch Ball Grid Array, page 100 section is also updated with
links to the customer notice including adding Note 1 to Table 80 and Note 1 to Table 81.
Also added data to Table 67 for the XC3S400AN in the FTG676 package.
Updated Notice of Disclaimer.
DS557 (v4.2) June 12, 2014
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Product Specification
122
Spartan-3AN FPGA Family: Pinout Descriptions
Notice of Disclaimer
The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the
maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL
WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
(whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related
to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special,
incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of
any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility
of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to
product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain
products are subject to the terms and conditions of Xilinx’s limited warranty, please refer to Xilinx’s Terms of Sale which can be viewed at
www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx
products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and
liability for use of Xilinx products in such critical applications, please refer to Xilinx’s Terms of Sale which can be viewed at
www.xilinx.com/legal.htm#tos.
AUTOMOTIVE APPLICATIONS DISCLAIMER
XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING
FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A
VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN
THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III)
USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY
USE OF XILINX PRODUCTS IN SUCH APPLICATIONS.
DS557 (v4.2) June 12, 2014
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Product Specification
123
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