XC3S50-4FTG256C [XILINX]
Field Programmable Gate Array, 192 CLBs, 50000 Gates, PBGA256, LEAD FREE, FTBGA-256;
| 型号： | XC3S50-4FTG256C |
| 厂家： | 
XILINX, INC |
| 描述： | Field Programmable Gate Array, 192 CLBs, 50000 Gates, PBGA256, LEAD FREE, FTBGA-256 栅 |
| 文件： | 总272页 (文件大小：5986K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1
Spartan-3 FPGA Family
Data Sheet
DS099 June 27, 2013
Product Specification
Module 1:
Introduction and Ordering Information
Module 4: Pinout Descriptions
DS099 (v3.1) June 27, 2013
DS099 (v3.1) June 27, 2013
•
Pin Descriptions
Pin Behavior During Configuration
•
•
•
•
•
•
Introduction
•
Features
•
•
Package Overview
Pinout Tables
Architectural Overview
Array Sizes and Resources
User I/O Chart
•
Footprints
Ordering Information
Module 2: Functional Description
DS099 (v3.1) June 27, 2013
•
Input/Output Blocks (IOBs)
•
•
IOB Overview
SelectIO™ Interface I/O Standards
•
•
•
•
•
•
Configurable Logic Blocks (CLBs)
Block RAM
Dedicated Multipliers
Digital Clock Manager (DCM)
Clock Network
Configuration
Module 3:
DC and Switching Characteristics
DS099 (v3.1) June 27, 2013
•
DC Electrical Characteristics
•
•
•
•
Absolute Maximum Ratings
Supply Voltage Specifications
Recommended Operating Conditions
DC Characteristics
•
Switching Characteristics
•
•
•
•
I/O Timing
Internal Logic Timing
DCM Timing
Configuration and JTAG Timing
© Copyright 2003–2013 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, Artix, Kintex, Zynq, Vivado, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
DS099 June 27, 2013
www.xilinx.com
Product Specification
1
8
Spartan-3 FPGA Family:
Introduction and Ordering Information
DS099 (v3.1) June 27, 2013
Product Specification
Introduction
Features
•
Low-cost, high-performance logic solution for high-volume,
consumer-oriented applications
The Spartan®-3 family of Field-Programmable Gate Arrays
is specifically designed to meet the needs of high volume,
cost-sensitive consumer electronic applications. The
eight-member family offers densities ranging from 50,000 to
5,000,000 system gates, as shown in Table 1.
•
Densities up to 74,880 logic cells
•
SelectIO™ interface signaling
•
•
•
•
•
•
•
•
Up to 633 I/O pins
622+ Mb/s data transfer rate per I/O
18 single-ended signal standards
8 differential I/O standards including LVDS, RSDS
Termination by Digitally Controlled Impedance
Signal swing ranging from 1.14V to 3.465V
Double Data Rate (DDR) support
The Spartan-3 family builds on the success of the earlier
Spartan-IIE family by increasing the amount of logic
resources, the capacity of internal RAM, the total number of
I/Os, and the overall level of performance as well as by
improving clock management functions. Numerous
enhancements derive from the Virtex®-II platform
technology. These Spartan-3 FPGA enhancements,
combined with advanced process technology, deliver more
functionality and bandwidth per dollar than was previously
possible, setting new standards in the programmable logic
industry.
DDR, DDR2 SDRAM support up to 333 Mb/s
•
Logic resources
•
•
•
•
•
Abundant logic cells with shift register capability
Wide, fast multiplexers
Fast look-ahead carry logic
Dedicated 18 x 18 multipliers
JTAG logic compatible with IEEE 1149.1/1532
•
•
SelectRAM™ hierarchical memory
•
•
Up to 1,872 Kbits of total block RAM
Up to 520 Kbits of total distributed RAM
Because of their exceptionally low cost, Spartan-3 FPGAs
are ideally suited to a wide range of consumer electronics
applications, including broadband access, home
networking, display/projection and digital television
equipment.
Digital Clock Manager (up to four DCMs)
•
•
•
Clock skew elimination
Frequency synthesis
High resolution phase shifting
•
•
Eight global clock lines and abundant routing
Fully supported by Xilinx ISE® and WebPACK™ software
development systems
The Spartan-3 family is a superior alternative to mask
programmed ASICs. FPGAs avoid the high initial cost, the
lengthy development cycles, and the inherent inflexibility of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary, an impossibility with ASICs.
•
MicroBlaze™ and PicoBlaze™ processor, PCI®,
PCI Express® PIPE Endpoint, and other IP cores
•
•
Pb-free packaging options
Automotive Spartan-3 XA Family variant
Table 1: Summary of Spartan-3 FPGA Attributes
CLB Array
Distributed
Block
Maximum
Differential
I/O Pairs
(One CLB = Four Slices)
System
Equivalent
Dedicated
Multipliers
Max.
User I/O
Device
RAM Bits RAM Bits
DCMs
(1)
Gates Logic Cells
Total
Rows Columns
CLBs
(K=1024)
(K=1024)
(2)
XC3S50
50K
200K
400K
1M
1,728
4,320
16
24
32
48
64
80
96
104
12
20
28
40
52
64
72
80
192
480
12K
30K
72K
216K
288K
432K
576K
720K
1,728K
1,872K
4
12
16
24
32
40
96
104
2
4
4
4
4
4
4
4
124
173
264
391
487
565
633
633
56
(2)
XC3S200
XC3S400
76
(2)
(2)
8,064
896
56K
116
175
221
270
300
300
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
17,280
29,952
46,080
62,208
74,880
1,920
3,328
5,120
6,912
8,320
120K
208K
320K
432K
520K
1.5M
2M
4M
5M
Notes:
1. Logic Cell = 4-input Look-Up Table (LUT) plus a ‘D’ flip-flop. "Equivalent Logic Cells" equals "Total CLBs" x 8 Logic Cells/CLB x 1.125 effectiveness.
2. These devices are available in Xilinx Automotive versions as described in DS314: Spartan-3 Automotive XA FPGA Family.
© Copyright 2003–2013 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, Artix, Kintex, Zynq, Vivado, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
DS099 (v3.1) June 27, 2013
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Product Specification
2
Spartan-3 FPGA Family: Introduction and Ordering Information
Architectural Overview
The Spartan-3 family architecture consists of five fundamental programmable functional elements:
•
Configurable Logic Blocks (CLBs) contain RAM-based Look-Up Tables (LUTs) to implement logic and storage
elements that can be used as flip-flops or latches. CLBs can be programmed to perform a wide variety of logical
functions as well as to store data.
•
Input/Output Blocks (IOBs) control the flow of data between the I/O pins and the internal logic of the device. Each IOB
supports bidirectional data flow plus 3-state operation. Twenty-six different signal standards, including eight
high-performance differential standards, are available as shown in Table 2. Double Data-Rate (DDR) registers are
included. The Digitally Controlled Impedance (DCI) feature provides automatic on-chip terminations, simplifying board
designs.
•
•
•
Block RAM provides data storage in the form of 18-Kbit dual-port blocks.
Multiplier blocks accept two 18-bit binary numbers as inputs and calculate the product.
Digital Clock Manager (DCM) blocks provide self-calibrating, fully digital solutions for distributing, delaying, multiplying,
dividing, and phase shifting clock signals.
These elements are organized as shown in Figure 1. A ring of IOBs surrounds a regular array of CLBs. The XC3S50 has a
single column of block RAM embedded in the array. Those devices ranging from the XC3S200 to the XC3S2000 have two
columns of block RAM. The XC3S4000 and XC3S5000 devices have four RAM columns. Each column is made up of several
18-Kbit RAM blocks; each block is associated with a dedicated multiplier. The DCMs are positioned at the ends of the outer
block RAM columns.
The Spartan-3 family features a rich network of traces and switches that interconnect all five functional elements,
transmitting signals among them. Each functional element has an associated switch matrix that permits multiple connections
to the routing.
X-Ref Target - Figure 1
DS099-1_01_032703
Notes:
1. The two additional block RAM columns of the XC3S4000 and XC3S5000 devices
are shown with dashed lines. The XC3S50 has only the block RAM column on the
far left.
Figure 1: Spartan-3 Family Architecture
Configuration
Spartan-3 FPGAs are programmed by loading configuration data into robust reprogrammable static CMOS configuration
latches (CCLs) that collectively control all functional elements and routing resources. Before powering on the FPGA,
configuration data is stored externally in a PROM or some other nonvolatile medium either on or off the board. After applying
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Product Specification
3
Spartan-3 FPGA Family: Introduction and Ordering Information
power, the configuration data is written to the FPGA using any of five different modes: Master Parallel, Slave Parallel, Master
Serial, Slave Serial, and Boundary Scan (JTAG). The Master and Slave Parallel modes use an 8-bit-wide SelectMAP port.
The recommended memory for storing the configuration data is the low-cost Xilinx Platform Flash PROM family, which
includes the XCF00S PROMs for serial configuration and the higher density XCF00P PROMs for parallel or serial
configuration.
I/O Capabilities
The SelectIO feature of Spartan-3 devices supports eighteen single-ended standards and eight differential standards as
listed in Table 2. Many standards support the DCI feature, which uses integrated terminations to eliminate unwanted signal
reflections.
Table 2: Signal Standards Supported by the Spartan-3 Family
Standard
Category
Symbol
(IOSTANDARD)
DCI
Option
Description
VCCO (V)
Class
Single-Ended
GTL
Gunning Transceiver Logic
N/A
1.5
1.8
Terminated
GTL
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Plus
GTLP
HSTL
High-Speed Transceiver Logic
I
HSTL_I
III
HSTL_III
I
HSTL_I_18
HSTL_II_18
HSTL_III_18
LVCMOS12
LVCMOS15
LVCMOS18
LVCMOS25
LVCMOS33
LVTTL
II
III
LVCMOS
Low-Voltage CMOS
1.2
1.5
1.8
2.5
3.3
3.3
3.0
1.8
N/A
N/A
Yes
Yes
Yes
Yes
No
N/A
N/A
N/A
LVTTL
PCI
Low-Voltage Transistor-Transistor Logic
Peripheral Component Interconnect
Stub Series Terminated Logic
N/A
33 MHz(1)
PCI33_3
No
SSTL
N/A ( 6.7 mA)
SSTL18_I
SSTL18_II
SSTL2_I
Yes
No
N/A ( 13.4 mA)
2.5
2.5
I
Yes
Yes
II
SSTL2_II
Differential
LDT
(ULVDS)
Lightning Data Transport (HyperTransport™)
Logic
N/A
LDT_25
No
LVDS
Low-Voltage Differential Signaling
Standard
LVDS_25
Yes
No
Bus
BLVDS_25
Extended Mode
LVDSEXT_25
LVPECL_25
RSDS_25
Yes
No
LVPECL
RSDS
HSTL
Low-Voltage Positive Emitter-Coupled Logic
Reduced-Swing Differential Signaling
Differential High-Speed Transceiver Logic
Differential Stub Series Terminated Logic
2.5
2.5
1.8
2.5
N/A
N/A
II
No
DIFF_HSTL_II_18
DIFF_SSTL2_II
Yes
Yes
SSTL
II
Notes:
1. 66 MHz PCI is not supported by the Xilinx IP core although PCI66_3 is an available I/O standard.
DS099 (v3.1) June 27, 2013
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Product Specification
4
Spartan-3 FPGA Family: Introduction and Ordering Information
Table 3 shows the number of user I/Os as well as the number of differential I/O pairs available for each device/package
combination.
Table 3: Spartan-3 Device I/O Chart
Available User I/Os and Differential (Diff) I/O Pairs by Package Type
(1)
(1)
VQ100
VQG100
CP132
TQ144
TQG144
PQ208
PQG208
FT256
FTG256
FG320
FGG320
FG456
FGG456
FG676
FGG676
FG900
FGG900
FG1156
Package
CPG132
FGG1156
Footprint
(mm)
16 x 16
8 x 8
22 x 22 30.6 x 30.6 17 x 17
19 x 19
23 x 23
27 x 27
31 x 31
35 x 35
Device
XC3S50
User Diff User Diff User Diff User Diff User Diff User Diff User Diff User Diff User Diff User
Diff
–
(1)
(1)
63
63
–
29
29
–
97
97
97
–
46
46
46
–
124
141
141
–
56
62
62
–
–
173
173
173
–
–
76
76
76
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
89
44
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
221 100 264 116
–
–
–
–
221 100 333 149 391 175
221 100 333 149 487 221
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
333 149 489 221 565 270
–
–
(1)
(1)
(1)
–
–
–
–
–
–
–
–
–
–
–
–
489 221 633 300
489 221 633 300
712
784
312
344
(1)
–
–
–
–
–
–
–
–
Notes:
1. The CP132, CPG132, FG1156, and FGG1156 packages are discontinued. See
http://www.xilinx.com/support/documentation/spartan-3_customer_notices.htm.
2. All device options listed in a given package column are pin-compatible.
3. User = Single-ended user I/O pins. Diff = Differential I/O pairs.
Package Marking
Figure 2 shows the top marking for Spartan-3 FPGAs in the quad-flat packages. Figure 3 shows the top marking for
Spartan-3 FPGAs in BGA packages except the 132-ball chip-scale package (CP132 and CPG132). The markings for the
BGA packages are nearly identical to those for the quad-flat packages, except that the marking is rotated with respect to the
ball A1 indicator. Figure 4 shows the top marking for Spartan-3 FPGAs in the CP132 and CPG132 packages.
The “5C” and “4I” part combinations may be dual marked as “5C/4I”. Devices with the dual mark can be used as either -5C
or -4I devices. Devices with a single mark are only guaranteed for the marked speed grade and temperature range. Some
specifications vary according to mask revision. Mask revision E devices are errata-free. All shipments since 2006 have been
mask revision E.
X-Ref Target - Figure 2
Mask Revision Code
Fabrication Code
R
R
Process Technology
SPARTAN
XC3S400
TM
Device Type
Date Code
Lot Code
Package
PQ208EGQ0525
D1234567A
Speed Grade
4C
Temperature Range
Pin P1
DS099-1_03_050305
Figure 2: Spartan-3 FPGA QFP Package Marking Example for Part Number XC3S400-4PQ208C
DS099 (v3.1) June 27, 2013
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Product Specification
5
Spartan-3 FPGA Family: Introduction and Ordering Information
X-Ref Target - Figure 3
Mask Revision Code
R
BGA Ball A1
Fabrication Code
Process Code
R
SPARTAN
Device Type
XC3S1000TM
Date Code
Lot Code
Package
FT256EGQ0525
D1234567A
4C
Speed Grade
Temperature Range
DS099-1_04_050305
Figure 3: Spartan-3 FPGA BGA Package Marking Example for Part Number XC3S1000-4FT256C
X-Ref Target - Figure 4
Ball A1
Device Type
3S50
F12345 -0525
PHILIPPINES
Lot Code
Date Code
Temperature Range
Package
C5 = CP132
C6 = CPG132
C5-EGQ
4C
Speed Grade
Process Code
Mask Revision Code
Fabrication Code
DS099-1_05_092712
Figure 4: Spartan-3 FPGA CP132 and CPG132 Package Marking Example for XC3S50-4CP132C
Ordering Information
Spartan-3 FPGAs are available in both standard (Figure 5) and Pb-free (Figure 6) packaging options for all device/package
combinations. The Pb-free packages include a special ‘G’ character in the ordering code.
X-Ref Target - Figure 5
Example: XC3S50 -4 PQ 208 C
Device Type
Temperature Range:
C = Commercial (Tj = 0°C to 85°C)
I = Industrial (Tj = –40°C to +100°C)
Speed Grade
Package Type
Number of Pins
DS099_1_05_020711
Figure 5: Standard Packaging
For additional information on Pb-free packaging, see XAPP427: Implementation and Solder Reflow Guidelines for Pb-Free
Packages.
X-Ref Target - Figure 6
Example: XC3S50 -4 PQ G 208 C
Device Type
Temperature Range:
C = Commercial (Tj = 0°C to 85°C)
I = Industrial (Tj = –40°C to +100°C)
Speed Grade
Package Type
Number of Pins
Pb-free
DS099_1_06_020711
Figure 6: Pb-Free Packaging
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Product Specification
6
Spartan-3 FPGA Family: Introduction and Ordering Information
Table 4: Example Ordering Information
Device
XC3S50
Speed Grade
Package Type/Number of Pins
Temperature Range (Tj)
-4 Standard Performance
VQ(G)100
100-pin Very Thin Quad Flat Pack (VQFP)
132-pin Chip-Scale Package (CSP)
C Commercial (0°C to 85°C)
(1)
(2)
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
-5 High Performance
CP(G)132
TQ(G)144
PQ(G)208
FT(G)256
FG(G)320
FG(G)456
FG(G)676
FG(G)900
I
Industrial (–40°C to 100°C)
144-pin Thin Quad Flat Pack (TQFP)
208-pin Plastic Quad Flat Pack (PQFP)
256-ball Fine-Pitch Thin Ball Grid Array (FTBGA)
320-ball Fine-Pitch Ball Grid Array (FBGA)
456-ball Fine-Pitch Ball Grid Array (FBGA)
676-ball Fine-Pitch Ball Grid Array (FBGA)
900-ball Fine-Pitch Ball Grid Array (FBGA)
1156-ball Fine-Pitch Ball Grid Array (FBGA)
(2)
FG(G)1156
Notes:
1. The -5 speed grade is exclusively available in the Commercial temperature range.
2. The CP132, CPG132, FG1156, and FGG1156 packages are discontinued. See
http://www.xilinx.com/support/documentation/spartan-3_customer_notices.htm.
Revision History
Date
Version
1.0
Description
04/11/2003
04/24/2003
12/24/2003
07/13/2004
01/17/2005
Initial Xilinx release.
1.1
Updated block RAM, DCM, and multiplier counts for the XC3S50.
Added the FG320 package.
1.2
1.3
Added information on Pb-free packaging options.
1.4
Referenced Spartan-3 XA Automotive FPGA families in Table 1. Added XC3S50CP132,
XC3S2000FG456, XC3S4000FG676 options to Table 3. Updated Package Marking to show mask
revision code, fabrication facility code, and process technology code.
08/19/2005
1.5
Added package markings for BGA packages (Figure 3) and CP132/CPG132 packages (Figure 4).
Added differential (complementary single-ended) HSTL and SSTL I/O standards.
04/03/2006
04/26/2006
05/25/2007
11/30/2007
2.0
2.1
2.2
2.3
Increased number of supported single-ended and differential I/O standards.
Updated document links.
Updated Package Marking to allow for dual-marking.
Added XC3S5000 FG(G)676 to Table 3. Noted that FG(G)1156 package is being discontinued and
updated max I/O count.
06/25/2008
12/04/2009
10/29/2012
2.4
2.5
3.0
Updated max I/O counts based on FG1156 discontinuation. Clarified dual mark in Package Marking.
Updated formatting and links.
CP132 and CPG132 packages are being discontinued. Added link to Spartan-3 FPGA customer
notices. Updated Table 3 with package footprint dimensions.
Added Notice of Disclaimer section. Per XCN07022, updated the discontinued FG1156 and FGG1156
package discussion throughout document. Per XCN08011, updated the discontinued CP132 and
CPG132 package discussion throughout document. Although the package is discontinued, updated
the marking on Figure 4. This product is not recommended for new designs.
06/27/2013
3.1
Removed banner. This product IS recommended for new designs.
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Product Specification
7
Spartan-3 FPGA Family: Introduction and Ordering Information
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED
WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE
SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
CRITICAL APPLICATIONS DISCLAIMER
XILINX PRODUCTS (INCLUDING HARDWARE, SOFTWARE AND/OR IP CORES) ARE NOT DESIGNED OR INTENDED TO BE
FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS IN LIFE-SUPPORT OR
SAFETY DEVICES OR SYSTEMS, CLASS III MEDICAL DEVICES, NUCLEAR FACILITIES, APPLICATIONS RELATED TO THE
DEPLOYMENT OF AIRBAGS, OR ANY OTHER APPLICATIONS THAT COULD LEAD TO DEATH, PERSONAL INJURY OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE (INDIVIDUALLY AND COLLECTIVELY, “CRITICAL APPLICATIONS”). FURTHERMORE,
XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN ANY APPLICATIONS THAT AFFECT CONTROL OF A
VEHICLE OR AIRCRAFT, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF
SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE
OPERATOR. CUSTOMER AGREES, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE XILINX
PRODUCTS, TO THOROUGHLY TEST THE SAME FOR SAFETY PURPOSES. TO THE MAXIMUM EXTENT PERMITTED BY
APPLICABLE LAW, CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN CRITICAL
APPLICATIONS.
AUTOMOTIVE APPLICATIONS DISCLAIMER
XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING
FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A
VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN
THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III)
USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY
USE OF XILINX PRODUCTS IN SUCH APPLICATIONS.
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Product Specification
8
57
Spartan-3 FPGA Family:
Functional Description
DS099 (v3.1) June 27, 2013
Product Specification
Spartan-3 FPGA Design Documentation
The functionality of the Spartan®-3 FPGA family is described in the following documents. The topics covered in each guide
are listed.
•
UG331: Spartan-3 Generation FPGA User Guide
Create a Xilinx user account and sign up to receive
automatic e-mail notification whenever this data sheet or
the associated user guides are updated.
•
•
•
•
Clocking Resources
Digital Clock Managers (DCMs)
Block RAM
•
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https://secure.xilinx.com/webreg/register.do
?group=myprofile&languageID=1
Configurable Logic Blocks (CLBs)
-
-
-
Distributed RAM
For specific hardware examples, see the Spartan-3 FPGA
Starter Kit board web page, which has links to various
design examples and the user guide.
SRL16 Shift Registers
Carry and Arithmetic Logic
•
Spartan-3 FPGA Starter Kit Board page
http://www.xilinx.com/s3starter
•
•
•
•
•
•
•
•
•
I/O Resources
Embedded Multiplier Blocks
Programmable Interconnect
ISE® Software Design Tools
IP Cores
•
UG130: Spartan-3 FPGA Starter Kit User Guide
Embedded Processing and Control Solutions
Pin Types and Package Overview
Package Drawings
Powering FPGAs
•
UG332: Spartan-3 Generation Configuration User
Guide
•
Configuration Overview
-
-
Configuration Pins and Behavior
Bitstream Sizes
•
Detailed Descriptions by Mode
-
Master Serial Mode using Xilinx Platform Flash
PROM
-
-
-
Slave Parallel (SelectMAP) using a Processor
Slave Serial using a Processor
JTAG Mode
•
ISE iMPACT Programming Examples
© Copyright 2003–2013 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, Artix, Kintex, Zynq, Vivado, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
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Product Specification
9
Spartan-3 FPGA Family: Functional Description
IOBs
For additional information, refer to the chapter entitled “Using I/O Resources” in UG331: Spartan-3 Generation FPGA User
Guide.
IOB Overview
The Input/Output Block (IOB) provides a programmable, bidirectional interface between an I/O pin and the FPGA’s internal
logic.
A simplified diagram of the IOB’s internal structure appears in Figure 7. There are three main signal paths within the IOB: the
output path, input path, and 3-state path. Each path has its own pair of storage elements that can act as either registers or
latches. For more information, see the Storage Element Functions section. The three main signal paths are as follows:
•
The input path carries data from the pad, which is bonded to a package pin, through an optional programmable delay
element directly to the I line. There are alternate routes through a pair of storage elements to the IQ1 and IQ2 lines.
The IOB outputs I, IQ1, and IQ2 all lead to the FPGA’s internal logic. The delay element can be set to ensure a hold
time of zero.
•
•
The output path, starting with the O1 and O2 lines, carries data from the FPGA’s internal logic through a multiplexer
and then a three-state driver to the IOB pad. In addition to this direct path, the multiplexer provides the option to insert
a pair of storage elements.
The 3-state path determines when the output driver is high impedance. The T1 and T2 lines carry data from the
FPGA’s internal logic through a multiplexer to the output driver. In addition to this direct path, the multiplexer provides
the option to insert a pair of storage elements. When the T1 or T2 lines are asserted High, the output driver is
high-impedance (floating, hi-Z). The output driver is active-Low enabled.
•
All signal paths entering the IOB, including those associated with the storage elements, have an inverter option. Any
inverter placed on these paths is automatically absorbed into the IOB.
Storage Element Functions
There are three pairs of storage elements in each IOB, one pair for each of the three paths. It is possible to configure each
of these storage elements as an edge-triggered D-type flip-flop (FD) or a level-sensitive latch (LD).
The storage-element-pair on either the Output path or the Three-State path can be used together with a special multiplexer
to produce Double-Data-Rate (DDR) transmission. This is accomplished by taking data synchronized to the clock signal’s
rising edge and converting them to bits synchronized on both the rising and the falling edge. The combination of two
registers and a multiplexer is referred to as a Double-Data-Rate D-type flip-flop (FDDR). See Double-Data-Rate
Transmission, page 12 for more information.
The signal paths associated with the storage element are described in Table 5.
Table 5: Storage Element Signal Description
Storage
Element
Signal
Description
Data input
Function
D
Data at this input is stored on the active edge of CK enabled by CE. For latch operation when the
input is enabled, data passes directly to the output Q.
Q
Data output
The data on this output reflects the state of the storage element. For operation as a latch in
transparent mode, Q will mirror the data at D.
CK
CE
SR
Clock input
A signal’s active edge on this input with CE asserted, loads data into the storage element.
When asserted, this input enables CK. If not connected, CE defaults to the asserted state.
Clock Enable input
Set/Reset
Forces storage element into the state specified by the SRHIGH/SRLOW attributes. The
SYNC/ASYNC attribute setting determines if the SR input is synchronized to the clock or not.
REV
Reverse
Used together with SR. Forces storage element into the state opposite from what SR does.
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Product Specification
10
Spartan-3 FPGA Family: Functional Description
X-Ref Target - Figure 7
T
TFF1
T1
D
Q
CE
CK
SR
REV
Q
DDR
MUX
TCE
T2
D
TFF2
CE
CK
SR
REV
Three-state Path
V
CCO
OFF1
O1
D
Q
CE
CK
Pull-Up
ESD
ESD
OTCLK1
SR
REV
Q
DDR
MUX
I/O
Pin
OCE
O2
Program-
mable
Output
Driver
Pull-
Down
D
DCI
OFF2
CE
OTCLK2
CK
SR
REV
Keeper
Latch
Output Path
I
Fixed
LVCMOS, LVTTL, PCI
Single-ended Standards
IQ1
Delay
D
Q
Fixed
Delay
IFF1
using V
REF
CE
CK
V
REF
Pin
ICLK1
ICE
SR
REV
Q
Differential Standards
IQ2
I/O Pin
from
D
Adjacent
IOB
IFF2
CE
ICLK2
CK
SR
REV
SR
REV
Input Path
Note: All IOB signals originating from the FPGA's internal logic have an optional polarity inverter.
DS099-2_01_091410
Figure 7: Simplified IOB Diagram
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Product Specification
11
Spartan-3 FPGA Family: Functional Description
According to Figure 7, the clock line OTCLK1 connects the CK inputs of the upper registers on the output and three-state
paths. Similarly, OTCLK2 connects the CK inputs for the lower registers on the output and three-state paths. The upper and
lower registers on the input path have independent clock lines: ICLK1 and ICLK2. The enable line OCE connects the CE
inputs of the upper and lower registers on the output path. Similarly, TCE connects the CE inputs for the register pair on the
three-state path and ICE does the same for the register pair on the input path. The Set/Reset (SR) line entering the IOB is
common to all six registers, as is the Reverse (REV) line.
Each storage element supports numerous options in addition to the control over signal polarity described in the IOB
Overview section. These are described in Table 6.
Table 6: Storage Element Options
Option Switch
Function
Specificity
FF/Latch
Chooses between an edge-sensitive flip-flop or a
level-sensitive latch
Independent for each storage element.
SYNC/ASYNC
Determines whether SR is synchronous or
asynchronous
Independent for each storage element.
SRHIGH/SRLOW Determines whether SR acts as a Set, which forces the Independent for each storage element, except when using
storage element to a logic “1" (SRHIGH) or a Reset,
which forces a logic “0” (SRLOW).
FDDR. In the latter case, the selection for the upper
element (OFF1 or TFF2) applies to both elements.
INIT1/INIT0
In the event of a Global Set/Reset, after configuration Independent for each storage element, except when using
or upon activation of the GSR net, this switch decides FDDR. In the latter case, selecting INIT0 for one element
whether to set or reset a storage element. By default, applies to both elements (even though INIT1 is selected
choosing SRLOW also selects INIT0; choosing
SRHIGH also selects INIT1.
for the other).
Double-Data-Rate Transmission
Double-Data-Rate (DDR) transmission describes the technique of synchronizing signals to both the rising and falling edges
of the clock signal. Spartan-3 devices use register-pairs in all three IOB paths to perform DDR operations.
The pair of storage elements on the IOB’s Output path (OFF1 and OFF2), used as registers, combine with a special
multiplexer to form a DDR D-type flip-flop (FDDR). This primitive permits DDR transmission where output data bits are
synchronized to both the rising and falling edges of a clock. It is possible to access this function by placing either an
FDDRRSE or an FDDRCPE component or symbol into the design. DDR operation requires two clock signals (50% duty
cycle), one the inverted form of the other. These signals trigger the two registers in alternating fashion, as shown in Figure 8.
Commonly, the Digital Clock Manager (DCM) generates the two clock signals by mirroring an incoming signal, then shifting
it 180 degrees. This approach ensures minimal skew between the two signals.
The storage-element-pair on the Three-State path (TFF1 and TFF2) can also be combined with a local multiplexer to form
an FDDR primitive. This permits synchronizing the output enable to both the rising and falling edges of a clock. This DDR
operation is realized in the same way as for the output path.
The storage-element-pair on the input path (IFF1 and IFF2) allows an I/O to receive a DDR signal. An incoming DDR clock
signal triggers one register and the inverted clock signal triggers the other register. In this way, the registers take turns
capturing bits of the incoming DDR data signal.
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Product Specification
12
Spartan-3 FPGA Family: Functional Description
X-Ref Target - Figure 8
DCM
180˚ 0˚
FDDR
D1
Q1
CLK1
DDR MUX
Q
D2
Q2
CLK2
DS099-2_02_070303
Figure 8: Clocking the DDR Register
Aside from high bandwidth data transfers, DDR can also be used to reproduce, or “mirror”, a clock signal on the output. This
approach is used to transmit clock and data signals together. A similar approach is used to reproduce a clock signal at
multiple outputs. The advantage for both approaches is that skew across the outputs will be minimal.
Some adjacent I/O blocks (IOBs) share common routing connecting the ICLK1, ICLK2, OTCLK1, and OTCLK2 clock inputs
of both IOBs. These IOB pairs are identified by their differential pair names IO_LxxN_# and IO_LxxP_#, where "xx" is an I/O
pair number and ‘#’ is an I/O bank number. Two adjacent IOBs containing DDR registers must share common clock inputs,
otherwise one or more of the clock signals will be unroutable.
Pull-Up and Pull-Down Resistors
The optional pull-up and pull-down resistors are intended to establish High and Low levels, respectively, at unused I/Os. The
pull-up resistor optionally connects each IOB pad to V
. A pull-down resistor optionally connects each pad to GND. These
CCO
resistors are placed in a design using the PULLUP and PULLDOWN symbols in a schematic, respectively. They can also be
instantiated as components, set as constraints or passed as attributes in HDL code. These resistors can also be selected for
all unused I/O using the Bitstream Generator (BitGen) option UnusedPin. A Low logic level on HSWAP_EN activates the
pull-up resistors on all I/Os during configuration (see The I/Os During Power-On, Configuration, and User Mode, page 21).
The Spartan-3 FPGAs I/O pull-up and pull-down resistors are significantly stronger than the "weak" pull-up/pull-down
resistors used in previous Xilinx FPGA families. See Table 33, page 61 for equivalent resistor strengths.
Keeper Circuit
Each I/O has an optional keeper circuit that retains the last logic level on a line after all drivers have been turned off. This is
useful to keep bus lines from floating when all connected drivers are in a high-impedance state. This function is placed in a
design using the KEEPER symbol. Pull-up and pull-down resistors override the keeper circuit.
DS099 (v3.1) June 27, 2013
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Product Specification
13
Spartan-3 FPGA Family: Functional Description
ESD Protection
Clamp diodes protect all device pads against damage from Electro-Static Discharge (ESD) as well as excessive voltage
transients. Each I/O has two clamp diodes: One diode extends P-to-N from the pad to V and a second diode extends
CCO
N-to-P from the pad to GND. During operation, these diodes are normally biased in the off state. These clamp diodes are
always connected to the pad, regardless of the signal standard selected. The presence of diodes limits the ability of
Spartan-3 FPGA I/Os to tolerate high signal voltages. The V absolute maximum rating in Table 28, page 58 specifies the
IN
voltage range that I/Os can tolerate.
Slew Rate Control and Drive Strength
Two options, FAST and SLOW, control the output slew rate. The FAST option supports output switching at a high rate. The
SLOW option reduces bus transients. These options are only available when using one of the LVCMOS or LVTTL standards,
which also provide up to seven different levels of current drive strength: 2, 4, 6, 8, 12, 16, and 24 mA. Choosing the
appropriate drive strength level is yet another means to minimize bus transients.
Table 7 shows the drive strengths that the LVCMOS and LVTTL standards support.
Table 7: Programmable Output Drive Current
Current Drive (mA)
Signal Standard
(IOSTANDARD)
2
4
6
8
✓
✓
✓
✓
✓
–
12
✓
✓
✓
✓
✓
–
16
✓
✓
✓
✓
–
24
✓
✓
✓
–
LVTTL
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
–
–
–
Boundary-Scan Capability
All Spartan-3 FPGA IOBs support boundary-scan testing compatible with IEEE 1149.1 standards. During boundary- scan
operations such as EXTEST and HIGHZ the I/O pull-down resistor is active. For more information, see Boundary-Scan
(JTAG) Mode, page 50, and refer to the “Using Boundary-Scan and BSDL Files” chapter in UG331.
SelectIO Interface Signal Standards
The IOBs support 18 different single-ended signal standards, as listed in Table 8. Furthermore, the majority of IOBs can be
used in specific pairs supporting any of eight differential signal standards, as shown in Table 9.
™
To define the SelectIO interface signaling standard in a design, set the IOSTANDARD attribute to the appropriate setting.
Xilinx provides a variety of different methods for applying the IOSTANDARD for maximum flexibility. For a full description of
different methods of applying attributes to control IOSTANDARD, refer to the “Using I/O Resources” chapter in UG331.
Together with placing the appropriate I/O symbol, two externally applied voltage levels, V
and V
, select the desired
REF
CCO
signal standard. The V
lines provide current to the output driver. The voltage on these lines determines the output
CCO
voltage swing for all standards except GTL and GTLP.
All single-ended standards except the LVCMOS, LVTTL, and PCI varieties require a Reference Voltage (V
) to bias the
REF
input-switching threshold. Once a configuration data file is loaded into the FPGA that calls for the I/Os of a given bank to use
such a signal standard, a few specifically reserved I/O pins on the same bank automatically convert to V inputs. When
REF
using one of the LVCMOS standards, these pins remain I/Os because the V
voltage biases the input-switching
CCO
threshold, so there is no need for V . Select the V
and V
levels to suit the desired single-ended standard according
REF
CCO
REF
to Table 8.
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Product Specification
14
Spartan-3 FPGA Family: Functional Description
Table 8: Single-Ended I/O Standards
V
CCO (Volts)
Signal Standard
(IOSTANDARD)
VREF for Inputs
(Volts)(1)
Board Termination
Voltage (VTT) in Volts
For Outputs
Note 2
Note 2
1.5
For Inputs
GTL
Note 2
0.8
1
1.2
1.5
0.75
1.5
0.9
0.9
1.8
–
GTLP
Note 2
–
HSTL_I
0.75
0.9
0.9
0.9
1.1
–
HSTL_III
HSTL_I_18
HSTL_II_18
HSTL_III_18
LVCMOS12
LVCMOS15
LVCMOS18
LVCMOS25
LVCMOS33
LVTTL
1.5
–
1.8
–
1.8
–
1.8
–
1.2
1.2
1.5
1.8
2.5
3.3
3.3
3.0
–
1.5
–
–
1.8
–
–
2.5
–
–
3.3
–
–
3.3
–
–
PCI33_3
3.0
–
–
SSTL18_I
SSTL18_II
SSTL2_I
1.8
0.9
0.9
1.25
1.25
0.9
0.9
1.25
1.25
1.8
–
2.5
–
SSTL2_II
2.5
–
Notes:
1. Banks 4 and 5 of any Spartan-3 device in a VQ100 package do not support signal standards using V
.
REF
2. The V
level used for the GTL and GTLP standards must be no lower than the termination voltage (V ), nor can it be lower than the
CCO
TT
voltage at the I/O pad.
3. See Table 10 for a listing of the single-ended DCI standards.
Differential standards employ a pair of signals, one the opposite polarity of the other. The noise canceling (e.g.,
Common-Mode Rejection) properties of these standards permit exceptionally high data transfer rates. This section
introduces the differential signaling capabilities of Spartan-3 devices.
Each device-package combination designates specific I/O pairs that are specially optimized to support differential
standards. A unique “L-number”, part of the pin name, identifies the line-pairs associated with each bank (see Figure 40,
page 112). For each pair, the letters ‘P’ and ‘N’ designate the true and inverted lines, respectively. For example, the pin
names IO_L43P_7 and IO_L43N_7 indicate the true and inverted lines comprising the line pair L43 on Bank 7. The V
CCO
lines provide current to the outputs. The V
lines supply power to the differential inputs, making them independent of
CCAUX
the V
voltage for an I/O bank. The V
lines are not used. Select the V
level to suit the desired differential standard
CCO
REF
CCO
according to Table 9.
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Product Specification
15
Spartan-3 FPGA Family: Functional Description
Table 9: Differential I/O Standards
VCCO (Volts)
Signal Standard
(IOSTANDARD)
VREF for Inputs (Volts)
For Inputs
For Outputs
LDT_25 (ULVDS_25)
LVDS_25
2.5
2.5
2.5
2.5
2.5
2.5
1.8
2.5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
BLVDS_25
LVDSEXT_25
LVPECL_25
RSDS_25
DIFF_HSTL_II_18
DIFF_SSTL2_II
Notes:
1. See Table 10 for a listing of the differential DCI standards.
The need to supply V
and V
imposes constraints on which standards can be used in the same bank. See The
CCO
REF
Organization of IOBs into Banks section for additional guidelines concerning the use of the V
and V
lines.
CCO
REF
Digitally Controlled Impedance (DCI)
When the round-trip delay of an output signal—i.e., from output to input and back again—exceeds rise and fall times, it is
common practice to add termination resistors to the line carrying the signal. These resistors effectively match the impedance
of a device’s I/O to the characteristic impedance of the transmission line, thereby preventing reflections that adversely affect
signal integrity. However, with the high I/O counts supported by modern devices, adding resistors requires significantly more
components and board area. Furthermore, for some packages—e.g., ball grid arrays—it may not always be possible to
place resistors close to pins.
DCI answers these concerns by providing two kinds of on-chip terminations: Parallel terminations make use of an integrated
resistor network. Series terminations result from controlling the impedance of output drivers. DCI actively adjusts both
parallel and series terminations to accurately match the characteristic impedance of the transmission line. This adjustment
process compensates for differences in I/O impedance that can result from normal variation in the ambient temperature, the
supply voltage and the manufacturing process. When the output driver turns off, the series termination, by definition,
approaches a very high impedance; in contrast, parallel termination resistors remain at the targeted values.
DCI is available only for certain I/O standards, as listed in Table 10. DCI is selected by applying the appropriate I/O standard
extensions to symbols or components. There are five basic ways to configure terminations, as shown in Table 11. The DCI
I/O standard determines which of these terminations is put into effect.
HSTL_I_DCI-, HSTL_III_DCI-, and SSTL2_I_DCI-type outputs do not require the VRN and VRP reference resistors.
Likewise, LVDCI-type inputs do not require the VRN and VRP reference resistors. In a bank without any DCI I/O or a bank
containing non-DCI I/O and purely HSTL_I_DCI- or HSTL_III_DCI-type outputs, or SSTL2_I_DCI-type outputs or
LVDCI-type inputs, the associated VRN and VRP pins can be used as general-purpose I/O pins.
The HSLVDCI (High-Speed LVDCI) standard is intended for bidirectional use. The driver is identical to LVDCI, while the input
is identical to HSTL. By using a V
-referenced input, HSLVDCI allows greater input sensitivity at the receiver than when
REF
using a single-ended LVCMOS-type receiver.
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Product Specification
16
Spartan-3 FPGA Family: Functional Description
Table 10: DCI I/O Standards
V
CCO (V)
Termination Type
VREF for
Category of Signal
Standard
Signal Standard
(IOSTANDARD)
Inputs (V)
For Outputs For Inputs
At Output
At Input
Single-Ended
Gunning
Transceiver Logic
GTL_DCI
1.2
1.5
1.5
1.5
1.8
1.2
1.5
1.5
1.5
1.8
0.8
1.0
Single
Single
GTLP_DCI
High-Speed
Transceiver Logic
HSTL_I_DCI
HSTL_III_DCI
HSTL_I_DCI_18
0.75
0.9
None
None
None
Split
Single
0.9
Split
HSTL_II_DCI_18
DIFF_HSTL_II_18_DCI
1.8
1.8
0.9
Split
HSTL_III_DCI_18
LVDCI_15
1.8
1.5
1.8
2.5
3.3
1.5
1.8
2.5
3.3
1.5
1.8
2.5
3.3
1.8
2.5
1.8
1.5
1.8
2.5
3.3
1.5
1.8
2.5
3.3
1.5
1.8
2.5
3.3
1.8
2.5
1.1
–
None
Single
Low-Voltage CMOS
LVDCI_18
–
Controlled
impedance driver
LVDCI_25
–
LVDCI_33(2)
–
None
LVDCI_DV2_15
LVDCI_DV2_18
LVDCI_DV2_25
LVDCI_DV2_33
HSLVDCI_15
HSLVDCI_18
HSLVDCI_25
HSLVDCI_33
SSTL18_I_DCI
SSTL2_I_DCI
–
Controlled driver
with
half-impedance
–
–
–
Hybrid HSTL Input
and LVCMOS Output
0.75
0.9
1.25
1.65
0.9
1.25
Controlled
impedance driver
None
Split
Stub Series
25Ω driver
25Ω driver
Terminated Logic(3)
SSTL2_II_DCI
DIFF_SSTL2_II_DCI
2.5
2.5
1.25
Split with 25Ω driver
Differential
Low-Voltage
Differential Signaling
LVDS_25_DCI
N/A
N/A
2.5
2.5
–
–
Split on each
line of pair
None
LVDSEXT_25_DCI
Notes:
1. DCI signal standards are not supported in Bank 5 of any Spartan-3 FPGA packaged in a VQ100, CP132, or TQ144 package.
2. Equivalent to LVTTL DCI.
3. The SSTL18_II signal standard does not have a DCI equivalent.
DS099 (v3.1) June 27, 2013
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Product Specification
17
Spartan-3 FPGA Family: Functional Description
Signal Standards
Table 11: DCI Terminations
Termination
Schematic(1)
(IOSTANDARD)
Controlled impedance output driver
LVDCI_15
LVDCI_18
LVDCI_25
IOB
R
LVDCI_33
Z
0
HSLVDCI_15
HSLVDCI_18
HSLVDCI_25
HSLVDCI_33
ds099_06a_070903
Controlled output driver with half impedance
LVDCI_DV2_15
LVDCI_DV2_18
LVDCI_DV2_25
LVDCI_DV2_33
IOB
R/2
Z
0
ds099_06b_070903
Single resistor
GTL_DCI
GTLP_DCI
HSTL_III_DCI(2)
HSTL_III_DCI_18(2)
V
V
V
CCO
IOB
R
Z
0
ds099_06c_070903
Split resistors
HSTL_I_DCI(2)
CCO
IOB
HSTL_I_DCI_18(2)
HSTL_II_DCI_18
DIFF_HSTL_II_18_DCI
DIFF_SSTL2_II_DCI
LVDS_25_DCI
2R
Z
0
2R
LVDSEXT_25_DCI
ds099_06d_070903
Split resistors with output driver impedance fixed
to 25Ω
SSTL18_I_DCI(3)
SSTL2_I_DCI(3)
SSTL2_II_DCI
CCO
IOB
25Ω
2R
Z
0
2R
ds099_06e_070903
Notes:
1. The value of R is equivalent to the characteristic impedance of the line connected to the I/O. It is also equal to half the value of RREF for the
DV2 standards and RREF for all other DCI standards.
2. For DCI using HSTL Classes I and III, terminations only go into effect at inputs (not at outputs).
3. For DCI using SSTL Class I, the split termination only goes into effect at inputs (not at outputs).
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Product Specification
18
Spartan-3 FPGA Family: Functional Description
The DCI feature operates independently for each of the device’s eight banks. Each bank has an ‘N’ reference pin (VRN) and
a ‘P’ reference pin, (VRP), to calibrate driver and termination resistance. Only when using a DCI standard on a given bank
do these two pins function as VRN and VRP. When not using a DCI standard, the two pins function as user I/Os. As shown
in Figure 9, add an external reference resistor to pull the VRN pin up to V
and another reference resistor to pull the VRP
CCO
pin down to GND. Also see Figure 42, page 116. Both resistors have the same value—commonly 50Ω—with one-percent
tolerance, which is either the characteristic impedance of the line or twice that, depending on the DCI standard in use.
Standards having a symbol name that contains the letters “DV2” use a reference resistor value that is twice the line
impedance. DCI adjusts the output driver impedance to match the reference resistors’ value or half that, according to the
standard. DCI always adjusts the on-chip termination resistors to directly match the reference resistors’ value.
X-Ref Target - Figure 9
One of eight
I/O Banks
V
CCO
R
(1%)
(1%)
REF
VRN
VRP
R
REF
DS099-2_04_082104
Figure 9: Connection of Reference Resistors (R
)
REF
The rules guiding the use of DCI standards on banks are as follows:
•
•
•
No more than one DCI I/O standard with a Single Termination is allowed per bank.
No more than one DCI I/O standard with a Split Termination is allowed per bank.
Single Termination, Split Termination, Controlled- Impedance Driver, and Controlled-Impedance Driver with Half
Impedance can co-exist in the same bank.
See also The Organization of IOBs into Banks, immediately below, and DCI: User I/O or Digitally Controlled Impedance
Resistor Reference Input, page 115.
The Organization of IOBs into Banks
IOBs are allocated among eight banks, so that each side of the device has two banks, as shown in Figure 10. For all
packages, each bank has independent V
to all other banks.
lines. For example, V
Bank 3 lines are separate from the V
lines going
REF
REF
REF
For the Very Thin Quad Flat Pack (VQ), Plastic Quad Flat Pack (PQ), Fine Pitch Thin Ball Grid Array (FT), and Fine Pitch Ball
Grid Array (FG) packages, each bank has dedicated V
lines. For example, the V
Bank 7 lines are separate from the
CCO
CCO
V
lines going to all other banks. Thus, Spartan-3 devices in these packages support eight independent V
supplies.
CCO
CCO
X-Ref Target - Figure 10
Bank 0
Bank 1
Bank 5
Bank 4
DS099-2_03_082104
Figure 10: Spartan-3 FPGA I/O Banks (Top View)
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Spartan-3 FPGA Family: Functional Description
In contrast, the 144-pin Thin Quad Flat Pack (TQ144) package and the 132-pin Chip-Scale Package (CP132) tie V
CCO
together internally for the pair of banks on each side of the device. For example, the V
Bank 0 and the V
Bank 1 lines
CCO
CCO
are tied together. The interconnected bank-pairs are 0/1, 2/3, 4/5, and 6/7. As a result, Spartan-3 devices in the CP132 and
TQ144 packages support four independent V supplies.
CCO
Note: The CP132 package is discontinued. See http://www.xilinx.com/support/documentation /spartan-3_customer_notices.htm.
Spartan-3 FPGA Compatibility
Within the Spartan-3 family, all devices are pin-compatible by package. When the need for future logic resources outgrows
the capacity of the Spartan-3 device in current use, a larger device in the same package can serve as a direct replacement.
Larger devices may add extra V
and V
lines to support a greater number of I/Os. In the larger device, more pins can
REF
CCO
convert from user I/Os to V
lines. Also, additional V
lines are bonded out to pins that were “not connected” in the
REF
CCO
smaller device. Thus, it is important to plan for future upgrades at the time of the board’s initial design by laying out
connections to the extra pins.
The Spartan-3 family is not pin-compatible with any previous Xilinx FPGA family or with other platforms among the
Spartan-3 Generation FPGAs.
Rules Concerning Banks
When assigning I/Os to banks, it is important to follow the following V
rules:
CCO
•
•
•
Leave no V
pins unconnected on the FPGA.
CCO
Set all V
lines associated with the (interconnected) bank to the same voltage level.
CCO
The V
levels used by all standards assigned to the I/Os of the (interconnected) bank(s) must agree. The Xilinx
CCO
development software checks for this. Tables 8, 9, and 10 describe how different standards use the V
supply.
CCO
•
Only one of the following standards is allowed on outputs per bank: LVDS, LDT, LVDS_EXT, or RSDS. This restriction is
for the eight banks in each device, even if the V
packages.
levels are shared across banks, as in the CP132 and TQ144
CCO
•
•
If none of the standards assigned to the I/Os of the (interconnected) bank(s) uses V
2.5V.
, tie all associated V
lines to
CCO
CCO
In general, apply 2.5V to V
Bank 4 from power-on to the end of configuration. Apply the same voltage to V
Bank
CCO
CCO
5 during parallel configuration or a Readback operation. For information on how to program the FPGA using 3.3V
signals and power, see the 3.3V-Tolerant Configuration Interface section.
If any of the standards assigned to the Inputs of the bank use V , then observe the following additional rules:
REF
•
•
Connect all V
pins within the bank to the same voltage level.
REF
The V
levels used by all standards assigned to the Inputs of the bank must agree. The Xilinx development software
REF
checks for this. Tables 8 and 10 describe how different standards use the V
supply.
REF
If none of the standards assigned to the Inputs of a bank use V
pins function as User I/Os.
for biasing input switching thresholds, all associated V
REF
REF
Exceptions to Banks Supporting I/O Standards
Bank 5 of any Spartan-3 device in a VQ100, CP132, or TQ144 package does not support DCI signal standards. In this case,
bank 5 has neither VRN nor VRP pins.
Furthermore, banks 4 and 5 of any Spartan-3 device in a VQ100 package do not support signal standards using V
(see
REF
Table 8). In this case, the two banks do not have any V
pins.
REF
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Spartan-3 FPGA Family: Functional Description
Supply Voltages for the IOBs
Three different supplies power the IOBs:
•
The V
supplies, one for each of the FPGA’s I/O banks, power the output drivers, except when using the GTL and
CCO
GTLP signal standards. The voltage on the V
pins determines the voltage swing of the output signal.
CCO
•
•
V
is the main power supply for the FPGA’s internal logic.
CCINT
The V
is an auxiliary source of power, primarily to optimize the performance of various FPGA functions such as
CCAUX
I/O switching.
The I/Os During Power-On, Configuration, and User Mode
With no power applied to the FPGA, all I/Os are in a high-impedance state. The V
(1.2V), V
(2.5V), and V
CCAUX CCO
CCINT
supplies may be applied in any order. Before power-on can finish, V
, V
Bank 4, and V
must have reached
CCINT CCO
CCAUX
their respective minimum recommended operating levels (see Table 29, page 59). At this time, all I/O drivers also will be in
a high-impedance state. V Bank 4, V , and V serve as inputs to the internal Power-On Reset circuit (POR).
CCO
CCINT
CCAUX
A Low level applied to the HSWAP_EN input enables pull-up resistors on User I/Os from power-on throughout configuration.
A High level on HSWAP_EN disables the pull-up resistors, allowing the I/Os to float. If the HSWAP_EN pin is floating, then
an internal pull-up resistor pulls HSWAP_EN High. As soon as power is applied, the FPGA begins initializing its
configuration memory. At the same time, the FPGA internally asserts the Global Set-Reset (GSR), which asynchronously
resets all IOB storage elements to a Low state.
Upon the completion of initialization, INIT_B goes High, sampling the M0, M1, and M2 inputs to determine the configuration
mode. At this point, the configuration data is loaded into the FPGA. The I/O drivers remain in a high-impedance state (with
or without pull-up resistors, as determined by the HSWAP_EN input) throughout configuration.
The Global Three State (GTS) net is released during Start-Up, marking the end of configuration and the beginning of design
operation in the User mode. At this point, those I/Os to which signals have been assigned go active while all unused I/Os
remain in a high-impedance state. The release of the GSR net, also part of Start-up, leaves the IOB registers in a Low state
by default, unless the loaded design reverses the polarity of their respective RS inputs.
In User mode, all internal pull-up resistors on the I/Os are disabled and HSWAP_EN becomes a “don’t care” input. If it is
desirable to have pull-up or pull-down resistors on I/Os carrying signals, the appropriate symbol—e.g., PULLUP,
PULLDOWN—must be placed at the appropriate pads in the design. The Bitstream Generator (Bitgen) option UnusedPin
available in the Xilinx development software determines whether unused I/Os collectively have pull-up resistors, pull-down
resistors, or no resistors in User mode.
CLB Overview
For more details on the CLBs, refer to the chapter entitled “Using Configurable Logic Blocks” in UG331.
The Configurable Logic Blocks (CLBs) constitute the main logic resource for implementing synchronous as well as
combinatorial circuits. Each CLB comprises four interconnected slices, as shown in Figure 11. These slices are grouped in
pairs. Each pair is organized as a column with an independent carry chain.
The nomenclature that the FPGA Editor—part of the Xilinx development software—uses to designate slices is as follows:
The letter ‘X’ followed by a number identifies columns of slices. The ‘X’ number counts up in sequence from the left side of
the die to the right. The letter ‘Y’ followed by a number identifies the position of each slice in a pair as well as indicating the
CLB row. The ‘Y’ number counts slices starting from the bottom of the die according to the sequence: 0, 1, 0, 1 (the first CLB
row); 2, 3, 2, 3 (the second CLB row); etc. Figure 11 shows the CLB located in the lower left-hand corner of the die. Slices
X0Y0 and X0Y1 make up the column-pair on the left where as slices X1Y0 and X1Y1 make up the column-pair on the right.
For each CLB, the term “left-hand” (or SLICEM) indicates the pair of slices labeled with an even ‘X’ number, such as X0, and
the term “right-hand” (or SLICEL) designates the pair of slices with an odd ‘X’ number, e.g., X1.
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Spartan-3 FPGA Family: Functional Description
X-Ref Target - Figure 11
Left-Hand SLICEM
(Logic or Distributed RAM
or Shift Register)
Right-Hand SLICEL
(Logic Only)
COUT
CLB
SLICE
X1Y1
SLICE
X1Y0
COUT
Switch
Matrix
Interconnect
to Neighbors
CIN
SLICE
X0Y1
SHIFTOUT
SHIFTIN
SLICE
X0Y0
CIN
DS099-2_05_082104
Figure 11: Arrangement of Slices within the CLB
Elements Within a Slice
All four slices have the following elements in common: two logic function generators, two storage elements, wide-function
multiplexers, carry logic, and arithmetic gates, as shown in Figure 12, page 24. Both the left-hand and right-hand slice pairs
use these elements to provide logic, arithmetic, and ROM functions. Besides these, the left-hand pair supports two
additional functions: storing data using Distributed RAM and shifting data with 16-bit registers. Figure 12 is a diagram of the
left-hand slice; therefore, it represents a superset of the elements and connections to be found in all slices. See Function
Generator, page 25 for more information.
The RAM-based function generator—also known as a Look-Up Table or LUT—is the main resource for implementing logic
functions. Furthermore, the LUTs in each left-hand slice pair can be configured as Distributed RAM or a 16-bit shift register.
For information on the former, refer to the chapter entitled “Using Look-Up Tables as Distributed RAM” in UG331; for
information on the latter, refer to the chapter entitled “Using Look-Up Tables as Shift Registers” in UG331. The function
generators located in the upper and lower portions of the slice are referred to as the "G" and "F", respectively.
The storage element, which is programmable as either a D-type flip-flop or a level-sensitive latch, provides a means for
synchronizing data to a clock signal, among other uses. The storage elements in the upper and lower portions of the slice
are called FFY and FFX, respectively.
Wide-function multiplexers effectively combine LUTs in order to permit more complex logic operations. Each slice has two of
these multiplexers with F5MUX in the lower portion of the slice and FiMUX in the upper portion. Depending on the slice,
FiMUX takes on the name F6MUX, F7MUX, or F8MUX. For more details on the multiplexers, refer to the chapter entitled
“Using Dedicated Multiplexers” in UG331.
The carry chain, together with various dedicated arithmetic logic gates, support fast and efficient implementations of math
operations. The carry chain enters the slice as CIN and exits as COUT. Five multiplexers control the chain: CYINIT, CY0F,
and CYMUXF in the lower portion as well as CY0G and CYMUXG in the upper portion. The dedicated arithmetic logic
includes the exclusive-OR gates XORG and XORF (upper and lower portions of the slice, respectively) as well as the AND
gates GAND and FAND (upper and lower portions, respectively). For more details on the carry logic, refer to the chapter
entitled “Using Carry and Arithmetic Logic” in UG331.
Main Logic Paths
Central to the operation of each slice are two nearly identical data paths, distinguished using the terms top and bottom. The
description that follows uses names associated with the bottom path. (The top path names appear in parentheses.) The
basic path originates at an interconnect-switch matrix outside the CLB. Four lines, F1 through F4 (or G1 through G4 on the
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22
Spartan-3 FPGA Family: Functional Description
upper path), enter the slice and connect directly to the LUT. Once inside the slice, the lower 4-bit path passes through a
function generator ‘F’ (or ‘G’) that performs logic operations. The function generator’s Data output, ‘D’, offers five possible
paths:
•
•
Exit the slice via line ‘X’ (or ‘Y’) and return to interconnect.
Inside the slice, ‘X’ (or ‘Y’) serves as an input to the DXMUX (DYMUX) which feeds the data input, ‘D’, of the FFX (FFY)
storage element. The ‘Q’ output of the storage element drives the line XQ (or YQ) which exits the slice.
•
•
Control the CYMUXF (or CYMUXG) multiplexer on the carry chain.
With the carry chain, serve as an input to the XORF (or XORG) exclusive-OR gate that performs arithmetic operations,
producing a result on ‘X’ (or ‘Y’).
•
Drive the multiplexer F5MUX to implement logic functions wider than four bits. The ‘D’ outputs of both the F-LUT and
G-LUT serve as data inputs to this multiplexer.
In addition to the main logic paths described above, there are two bypass paths that enter the slice as BX and BY. Once
inside the FPGA, BX in the bottom half of the slice (or BY in the top half) can take any of several possible branches:
•
•
•
•
•
•
•
Bypass both the LUT and the storage element, then exit the slice as BXOUT (or BYOUT) and return to interconnect.
Bypass the LUT, then pass through a storage element via the D input before exiting as XQ (or YQ).
Control the wide function multiplexer F5MUX (or F6MUX).
Via multiplexers, serve as an input to the carry chain.
Drives the DI input of the LUT.
BY can control the REV inputs of both the FFY and FFX storage elements.
Finally, the DIG_MUX multiplexer can switch BY onto the DIG line, which exits the slice.
Other slice signals shown in Figure 12 are discussed in the sections that follow.
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Spartan-3 FPGA Family: Functional Description
X-Ref Target - Figure 12
WS DI
DI
D
WF[4:1]
DS312-2_32_042007
Notes:
1. Options to invert signal polarity as well as other options that enable lines for various functions are not shown.
2. The index i can be 6, 7, or 8, depending on the slice. In this position, the upper right-hand slice has an F8MUX, and the
upper left-hand slice has an F7MUX. The lower right-hand and left-hand slices both have an F6MUX.
Figure 12: Simplified Diagram of the Left-Hand SLICEM
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Spartan-3 FPGA Family: Functional Description
Function Generator
Each of the two LUTs (F and G) in a slice have four logic inputs (A1-A4) and a single output (D). This permits any
four-variable Boolean logic operation to be programmed into them. Furthermore, wide function multiplexers can be used to
effectively combine LUTs within the same CLB or across different CLBs, making logic functions with still more input variables
possible.
The LUTs in both the right-hand and left-hand slice-pairs not only support the logic functions described above, but also can
function as ROM that is initialized with data at the time of configuration.
The LUTs in the left-hand slice-pair (even-numbered columns such as X0 in Figure 11) of each CLB support two additional
functions that the right-hand slice-pair (odd-numbered columns such as X1) do not.
First, it is possible to program the “left-hand LUTs” as distributed RAM. This type of memory affords moderate amounts of
data buffering anywhere along a data path. One left-hand LUT stores 16 bits. Multiple left-hand LUTs can be combined in
various ways to store larger amounts of data. A dual port option combines two LUTs so that memory access is possible from
two independent data lines. A Distributed ROM option permits pre-loading the memory with data during FPGA configuration.
Second, it is possible to program each left-hand LUT as a 16-bit shift register. Used in this way, each LUT can delay serial
data anywhere from one to 16 clock cycles. The four left-hand LUTs of a single CLB can be combined to produce delays up
to 64 clock cycles. The SHIFTIN and SHIFTOUT lines cascade LUTs to form larger shift registers. It is also possible to
combine shift registers across more than one CLB. The resulting programmable delays can be used to balance the timing
of data pipelines.
Block RAM Overview
All Spartan-3 devices support block RAM, which is organized as configurable, synchronous 18Kbit blocks. Block RAM stores
relatively large amounts of data more efficiently than the distributed RAM feature described earlier. (The latter is better
suited for buffering small amounts of data anywhere along signal paths.) This section describes basic Block RAM functions.
For more information, refer to the chapter entitled “Using Block RAM” in UG331.
The aspect ratio—i.e., width vs. depth—of each block RAM is configurable. Furthermore, multiple blocks can be cascaded
to create still wider and/or deeper memories.
A choice among primitives determines whether the block RAM functions as dual- or single-port memory. A name of the form
RAMB16_S[w ]_S[w ] calls out the dual-port primitive, where the integers w and w specify the total data path width at
A
B
A
B
ports w and w , respectively. Thus, a RAMB16_S9_S18 is a dual-port RAM with a 9-bit-wide Port A and an 18-bit-wide Port
A
B
B. A name of the form RAMB16_S[w] identifies the single-port primitive, where the integer w specifies the total data path
width of the lone port. A RAMB16_S18 is a single-port RAM with an 18-bit-wide port. Other memory functions—e.g., FIFOs,
data path width conversion, ROM, etc.—are readily available using the CORE Generator™ software, part of the Xilinx
development software.
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Spartan-3 FPGA Family: Functional Description
Arrangement of RAM Blocks on Die
The XC3S50 has one column of block RAM. The Spartan-3 devices ranging from the XC3S200 to XC3S2000 have two
columns of block RAM. The XC3S4000 and XC3S5000 have four columns. The position of the columns on the die is shown
in Figure 1, page 3. For a given device, the total available RAM blocks are distributed equally among the columns. Table 12
shows the number of RAM blocks, the data storage capacity, and the number of columns for each device.
Table 12: Number of RAM Blocks by Device
Total Number TotalAddressable Numberof
Device
of RAM Blocks Locations (Bits)
Columns
XC3S50
4
12
16
24
32
40
96
104
73,728
221,184
294,912
442,368
589,824
737,280
1,769,472
1,916,928
1
2
2
2
2
2
4
4
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
Block RAM and multipliers have interconnects between them that permit simultaneous operation; however, since the
multiplier shares inputs with the upper data bits of block RAM, the maximum data path width of the block RAM is 18 bits in
this case.
The Internal Structure of the Block RAM
The block RAM has a dual port structure. The two identical data ports called A and B permit independent access to the
common RAM block, which has a maximum capacity of 18,432 bits—or 16,384 bits when no parity lines are used. Each port
has its own dedicated set of data, control and clock lines for synchronous read and write operations. There are four basic
data paths, as shown in Figure 13: (1) write to and read from Port A, (2) write to and read from Port B, (3) data transfer from
Port A to Port B, and (4) data transfer from Port B to Port A.
X-Ref Target - Figure 13
3
Write
Read
Read
Write
4
Spartan-3
Dual Port
Block RAM
Write
Write
2
1
Read
Read
DS099-2_12_030703
Figure 13: Block RAM Data Paths
Block RAM Port Signal Definitions
Representations of the dual-port primitive RAMB16_S[w ]_S[w ] and the single-port primitive RAMB16_S[w] with their
A
B
associated signals are shown in Figure 14. These signals are defined in Table 13.
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Spartan-3 FPGA Family: Functional Description
X-Ref Target - Figure 14
RAMB16_SwA_SwB
WEA
ENA
SSRA
DOPA[pA–1:0]
DOA[wA–1:0]
CLKA
ADDRA[rA–1:0]
DIA[wA–1:0]
DIPA[3:0]
RAMB16_Sw
WE
WEB
ENB
EN
SSRB
SSR
DOPB[pB–1:0]
DOB[wB–1:0]
DOP[p–1:0]
CLK
CLKB
DO[w–1:0]
ADDRB[rB–1:0]
DIB[wB–1:0]
DIPB[3:0]
ADDR[r–1:0]
DI[w–1:0]
DIP[p–1:0]
(a) Dual-Port
(b) Single-Port
DS099-2_13_112905
Notes:
1. w and w are integers representing the total data path width (i.e., data bits plus parity bits) at ports A and B, respectively.
A
B
2. p and p are integers that indicate the number of data path lines serving as parity bits.
A
B
3. r and r are integers representing the address bus width at ports A and B, respectively.
A
B
4. The control signals CLK, WE, EN, and SSR on both ports have the option of inverted polarity.
Figure 14: Block RAM Primitives
Table 13: Block RAM Port Signals
Signal
Description
Port A
Port B
Direction
Function
Signal Name Signal Name
Address Bus
ADDRA ADDRB
Input
The Address Bus selects a memory location for read or write
operations. The width (w) of the port’s associated data path determines
the number of available address lines (r).
Whenever a port is enabled (ENA or ENB = High), address transitions
must meet the data sheet setup and hold times with respect to the port
clock (CLKA or CLKB). This requirement must be met, even if the RAM
read output is of no interest.
Data Input Bus
DIA
DIB
Input
Data at the DI input bus is written to the addressed memory location
addressed on an enabled active CLK edge.
It is possible to configure a port’s total data path width (w) to be 1, 2, 4,
9, 18, or 36 bits. This selection applies to both the DI and DO paths of
a given port. Each port is independent. For a port assigned a width (w),
the number of addressable locations is 16,384/(w-p) where "p" is the
number of parity bits. Each memory location has a width of "w"
(including parity bits). See the DIP signal description for more
information of parity.
Parity Data
Input(s)
DIPA
DIPB
Input
Parity inputs represent additional bits included in the data input path to
support error detection. The number of parity bits "p" included in the DI
(same as for the DO bus) depends on a port’s total data path width (w).
See Table 14.
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Spartan-3 FPGA Family: Functional Description
Function
Table 13: Block RAM Port Signals (Cont’d)
Signal
Port A
Port B
Direction
Description
Signal Name Signal Name
Data Output Bus
DOA
DOB
Output
Basic data access occurs whenever WE is inactive. The DO outputs
mirror the data stored in the addressed memory location.
Data access with WE asserted is also possible if one of the following two
attributes is chosen: WRITE_FIRST and READ_FIRST. WRITE_FIRST
simultaneously presents the new input data on the DO output port and
writes the data to the address RAM location. READ_FIRST presents the
previously stored RAM data on the DO output port while writing new
data to RAM.
A third attribute, NO_CHANGE, latches the DO outputs upon the
assertion of WE.
It is possible to configure a port’s total data path width (w) to be 1, 2, 4,
9, 18, or 36 bits. This selection applies to both the DI and DO paths. See
the DI signal description.
Parity Data
Output(s)
DOPA
WEA
DOPB
WEB
Output
Input
Parity inputs represent additional bits included in the data input path to
support error detection. The number of parity bits "p" included in the DI
(same as for the DO bus) depends on a port’s total data path width (w).
See Table 14.
Write Enable
When asserted together with EN, this input enables the writing of data
to the RAM. In this case, the data access attributes WRITE_FIRST,
READ_FIRST or NO_CHANGE determines if and how data is updated
on the DO outputs. See the DO signal description.
When WE is inactive with EN asserted, read operations are still
possible. In this case, a transparent latch passes data from the
addressed memory location to the DO outputs.
Clock Enable
ENA
ENB
Input
When asserted, this input enables the CLK signal to synchronize Block
RAM functions as follows: the writing of data to the DI inputs (when WE
is also asserted), the updating of data at the DO outputs as well as the
setting/resetting of the DO output latches.
When de-asserted, the above functions are disabled.
Set/Reset
Clock
SSRA
CLKA
SSRB
CLKB
Input
Input
When asserted, this pin forces the DO output latch to the value that the
SRVAL attribute is set to. A Set/Reset operation on one port has no
effect on the other ports functioning, nor does it disturb the memory’s
data contents. It is synchronized to the CLK signal.
This input accepts the clock signal to which read and write operations
are synchronized. All associated port inputs are required to meet setup
times with respect to the clock signal’s active edge. The data output bus
responds after a clock-to-out delay referenced to the clock signal’s
active edge.
Port Aspect Ratios
On a given port, it is possible to select a number of different possible widths (w – p) for the DI/DO buses as shown in
Table 14. These two buses always have the same width. This data bus width selection is independent for each port. If the
data bus width of Port A differs from that of Port B, the Block RAM automatically performs a bus-matching function. When
data are written to a port with a narrow bus, then read from a port with a wide bus, the latter port will effectively combine
“narrow” words to form “wide” words. Similarly, when data are written into a port with a wide bus, then read from a port with
a narrow bus, the latter port will divide “wide” words to form “narrow” words. When the data bus width is eight bits or greater,
extra parity bits become available. The width of the total data path (w) is the sum of the DI/DO bus width and any parity bits
(p).
The width selection made for the DI/DO bus determines the number of address lines according to the relationship expressed
below:
r = 14 – [log(w–p)/log(2)]
Equation 1
In turn, the number of address lines delimits the total number (n) of addressable locations or depth according to the following
equation:
r
n = 2
Equation 2
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Spartan-3 FPGA Family: Functional Description
The product of w and n yields the total block RAM capacity. Equation 1 and Equation 2 show that as the data bus width
increases, the number of address lines along with the number of addressable memory locations decreases. Using the
permissible DI/DO bus widths as inputs to these equations provides the bus width and memory capacity measures shown
in Table 14.
Table 14: Port Aspect Ratios for Port A or B
DI/DO Bus Width
(w – p Bits)
DIP/DOP
Total Data Path
Width (w Bits)
ADDR Bus Width No. of Addressable
Block RAM
Bus Width (p Bits)
(r Bits)
Locations (n)
16,384
8,192
Capacity (Bits)
1
2
0
0
0
1
2
4
1
2
14
16,384
16,384
16,384
18,432
18,432
18,432
13
4
4
12
4,096
8
9
11
2,048
16
32
18
36
10
1,024
9
512
Block RAM Data Operations
Writing data to and accessing data from the block RAM are synchronous operations that take place independently on each
of the two ports.
The waveforms for the write operation are shown in the top half of the Figure 15, Figure 16, and Figure 17. When the WE
and EN signals enable the active edge of CLK, data at the DI input bus is written to the block RAM location addressed by the
ADDR lines.
There are a number of different conditions under which data can be accessed at the DO outputs. Basic data access always
occurs when the WE input is inactive. Under this condition, data stored in the memory location addressed by the ADDR lines
passes through a transparent output latch to the DO outputs. The timing for basic data access is shown in the portions of
Figure 15, Figure 16, and Figure 17 during which WE is Low.
X-Ref Target - Figure 15
CLK
WE
DI
XXXX
1111
2222
cc
XXXX
ADDR
DO
aa
bb
dd
0000
MEM(aa)
1111
2222
MEM(dd)
EN
WRITE
MEM(bb)=1111
WRITE
MEM(cc)=2222
READ
DISABLED
READ
DS099-2_14_091410
Figure 15: Waveforms of Block RAM Data Operations with WRITE_FIRST Selected
Data can also be accessed on the DO outputs when asserting the WE input. This is accomplished using two different
attributes:
Choosing the WRITE_FIRST attribute, data is written to the addressed memory location on an enabled active CLK edge and
is also passed to the DO outputs. WRITE_FIRST timing is shown in the portion of Figure 15 during which WE is High.
Choosing the READ_FIRST attribute, data already stored in the addressed location pass to the DO outputs before that
location is overwritten with new data from the DI inputs on an enabled active CLK edge. READ_FIRST timing is shown in the
portion of Figure 16 during which WE is High.
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Spartan-3 FPGA Family: Functional Description
X-Ref Target - Figure 16
CLK
WE
DI
XXXX
aa
1111
bb
2222
cc
XXXX
ADDR
DO
dd
0000
MEM(aa)
old MEM(bb)
old MEM(cc)
MEM(dd)
EN
DISABLED
READ
WRITE
MEM(bb)=1111
WRITE
MEM(cc)=2222
READ
DS099-2_15_030403
Figure 16: Waveforms of Block RAM Data Operations with READ_FIRST Selected
Choosing a third attribute called NO_CHANGE puts the DO outputs in a latched state when asserting WE. Under this
condition, the DO outputs will retain the data driven just before WE was asserted. NO_CHANGE timing is shown in the
portion of Figure 17 during which WE is High.
X-Ref Target - Figure 17
CLK
WE
DI
XXXX
aa
1111
bb
2222
cc
XXXX
ADDR
DO
dd
0000
MEM(aa)
MEM(dd)
EN
DISABLED
READ
WRITE
MEM(bb)=1111
WRITE
MEM(cc)=2222
READ
DS099-2_16_030403
Figure 17: Waveforms of Block RAM Data Operations with NO_CHANGE Selected
Dedicated Multipliers
All Spartan-3 devices provide embedded multipliers that accept two 18-bit words as inputs to produce a 36-bit product. This
section provides an introduction to multipliers. For further details, refer to the chapter entitled “Using Embedded Multipliers”
in UG331.
The input buses to the multiplier accept data in two’s-complement form (either 18-bit signed or 17-bit unsigned). One such
multiplier is matched to each block RAM on the die. The close physical proximity of the two ensures efficient data handling.
Cascading multipliers permits multiplicands more than three in number as well as wider than 18-bits. The multiplier is placed
in a design using one of two primitives: an asynchronous version called MULT18X18 and a version with a register called
MULT18X18S, as shown in Figure 18. The signals for these primitives are defined in Table 15.
The CORE Generator system produces multipliers based on these primitives that can be configured to suit a wide range of
requirements.
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Spartan-3 FPGA Family: Functional Description
X-Ref Target - Figure 18
MULT18X18S
A[17:0]
B[17:0]
CLK
P[35:0]
MULT18X18
A[17:0]
B[17:0]
P[35:0]
CE
RST
(a) Asynchronous 18-bit Multiplier
(b) 18-bit Multiplier with Register
DS099-2_17_091510
Figure 18: Embedded Multiplier Primitives
Table 15: Embedded Multiplier Primitives Descriptions
Signal
Direction
Name
Function
Apply one 18-bit multiplicand to these inputs. The MULT18X18S primitive requires a setup time before the
enabled rising edge of CLK.
A[17:0]
B[17:0]
P[35:0]
CLK
Input
Input
Apply the other 18-bit multiplicand to these inputs. The MULT18X18S primitive requires a setup time before
the enabled rising edge of CLK.
The output on the P bus is a 36-bit product of the multiplicands A and B. In the case of the MULT18X18S
primitive, an enabled rising CLK edge updates the P bus.
Output
Input(1)
Input(1)
Input(1)
CLK is only an input to the MULT18X18S primitive. The clock signal applied to this input, when enabled by
CE, updates the output register that drives the P bus.
CE is only an input to the MULT18X18S primitive. Enable for the CLK signal. Asserting this input enables the
CLK signal to update the P bus.
CE
RST is only an input to the MULT18X18S primitive. Asserting this input resets the output register on an
enabled, rising CLK edge, forcing the P bus to all zeroes.
RST
Notes:
1. The control signals CLK, CE and RST have the option of inverted polarity.
Digital Clock Manager (DCM)
Spartan-3 devices provide flexible, complete control over clock frequency, phase shift and skew through the use of the DCM
feature. To accomplish this, the DCM employs a Delay-Locked Loop (DLL), a fully digital control system that uses feedback
to maintain clock signal characteristics with a high degree of precision despite normal variations in operating temperature
and voltage. This section provides a fundamental description of the DCM. For further information, refer to the chapter
entitled “Using Digital Clock Managers” in UG331.
Each member of the Spartan-3 family has four DCMs, except the smallest, the XC3S50, which has two DCMs. The DCMs
are located at the ends of the outermost Block RAM column(s). See Figure 1, page 3. The Digital Clock Manager is placed
in a design as the “DCM” primitive.
The DCM supports three major functions:
•
Clock-skew Elimination: Clock skew describes the extent to which clock signals may, under normal circumstances,
deviate from zero-phase alignment. It occurs when slight differences in path delays cause the clock signal to arrive at
different points on the die at different times. This clock skew can increase set-up and hold time requirements as well as
clock-to-out time, which may be undesirable in applications operating at a high frequency, when timing is critical. The
DCM eliminates clock skew by aligning the output clock signal it generates with another version of the clock signal that
is fed back. As a result, the two clock signals establish a zero-phase relationship. This effectively cancels out clock
distribution delays that may lie in the signal path leading from the clock output of the DCM to its feedback input.
•
Frequency Synthesis: Provided with an input clock signal, the DCM can generate a wide range of different output
clock frequencies. This is accomplished by either multiplying and/or dividing the frequency of the input clock signal by
any of several different factors.
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Spartan-3 FPGA Family: Functional Description
•
Phase Shifting: The DCM provides the ability to shift the phase of all its output clock signals with respect to its input
clock signal.
The DCM has four functional components: the Delay-Locked Loop (DLL), the Digital Frequency Synthesizer (DFS), the
Phase Shifter (PS), and the Status Logic. Each component has its associated signals, as shown in Figure 19.
X-Ref Target - Figure 19
DCM
PSINCDEC
PSEN
Phase
Shifter
PSDONE
CLK0
PSCLK
Clock
Distribution
Delay
CLKIN
CLKFB
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
CLKFX
DFS
CLKFX180
DLL
LOCKED
Status
Logic
RST
8
STATUS [7:0]
DS099-2_07_040103
Figure 19: DCM Functional Blocks and Associated Signals
Delay-Locked Loop (DLL)
The most basic function of the DLL component is to eliminate clock skew. The main signal path of the DLL consists of an
input stage, followed by a series of discrete delay elements or taps, which in turn leads to an output stage. This path together
with logic for phase detection and control forms a system complete with feedback as shown in Figure 20.
X-Ref Target - Figure 20
CLK0
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
Delay
1
Delay
2
Delay
n-1
Delay
n
CLKIN
Control
LOCKED
Phase
Detection
CLKFB
RST
DS099-2_08_041103
Figure 20: Simplified Functional Diagram of DLL
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Spartan-3 FPGA Family: Functional Description
The DLL component has two clock inputs, CLKIN and CLKFB, as well as seven clock outputs, CLK0, CLK90, CLK180,
CLK270, CLK2X, CLK2X180, and CLKDV as described in Table 16. The clock outputs drive simultaneously; however, the
High Frequency mode only supports a subset of the outputs available in the Low Frequency mode. See DLL Frequency
Modes, page 35. Signals that initialize and report the state of the DLL are discussed in The Status Logic Component,
page 41.
Table 16: DLL Signals
Mode Support
Signal
Direction
Description
Low
High
Frequency Frequency
CLKIN
Input
Input
Accepts original clock signal.
Yes
Yes
Yes
Yes
Accepts either CLK0 or CLK2X as feed back signal. (Set CLK_FEEDBACK
attribute accordingly).
CLKFB
CLK0
Output
Output
Output
Output
Output
Generates clock signal with same frequency and phase as CLKIN.
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
No
No
CLK90
CLK180
CLK270
CLK2X
Generates clock signal with same frequency as CLKIN, only phase-shifted 90°.
Generates clock signal with same frequency as CLKIN, only phase-shifted 180°.
Generates clock signal with same frequency as CLKIN, only phase-shifted 270°.
Generates clock signal with same phase as CLKIN, only twice the frequency.
Generates clock signal with twice the frequency of CLKIN, phase-shifted 180°
with respect to CLKIN.
CLK2X180
CLKDV
Output
Output
Yes
Yes
No
Divides the CLKIN frequency by CLKDV_DIVIDE value to generate lower
frequency clock signal that is phase-aligned to CLKIN.
Yes
The clock signal supplied to the CLKIN input serves as a reference waveform, with which the DLL seeks to align the
feedback signal at the CLKFB input. When eliminating clock skew, the common approach to using the DLL is as follows: The
CLK0 signal is passed through the clock distribution network to all the registers it synchronizes. These registers are either
internal or external to the FPGA. After passing through the clock distribution network, the clock signal returns to the DLL via
a feedback line called CLKFB. The control block inside the DLL measures the phase error between CLKFB and CLKIN. This
phase error is a measure of the clock skew that the clock distribution network introduces. The control block activates the
appropriate number of delay elements to cancel out the clock skew. Once the DLL has brought the CLK0 signal in phase with
the CLKIN signal, it asserts the LOCKED output, indicating a “lock” on to the CLKIN signal.
DLL Attributes and Related Functions
A number of different functional options can be set for the DLL component through the use of the attributes described in
Table 17. Each attribute is described in detail in the sections that follow:
Table 17: DLL Attributes
Attribute
CLK_FEEDBACK
Description
Chooses either the CLK0 or CLK2X output to drive the CLKFB input NONE, 1X, 2X
Chooses between High Frequency and Low Frequency modes LOW, HIGH
Halves the frequency of the CLKIN signal just as it enters the DCM TRUE, FALSE
1.5, 2, 2.5, 3, 3.5, 4, 4.5,
Values
DLL_FREQUENCY_MODE
CLKIN_DIVIDE_BY_2
Selects constant used to divide the CLKIN input frequency to
generate the CLKDV output frequency
5, 5.5, 6.0, 6.5, 7.0, 7.5,
8, 9, 10, 11, 12, 13, 14,
15, and 16.
CLKDV_DIVIDE
Enables 50% duty cycle correction for the CLK0, CLK90, CLK180,
and CLK270 outputs
DUTY_CYCLE_CORRECTION
TRUE, FALSE
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Spartan-3 FPGA Family: Functional Description
DLL Clock Input Connections
An external clock source enters the FPGA using a Global Clock Input Buffer (IBUFG), which directly accesses the global
clock network or an Input Buffer (IBUF). Clock signals within the FPGA drive a global clock net using a Global Clock
Multiplexer Buffer (BUFGMUX). The global clock net connects directly to the CLKIN input. The internal and external
connections are shown in the [a] and [c] sections, respectively, of Figure 21. A differential clock (e.g., LVDS) can serve as an
input to CLKIN.
DLL Clock Output and Feedback Connections
As many as four of the nine DCM clock outputs can simultaneously drive the four BUFGMUX buffers on the same die edge
(top or bottom). All DCM clock outputs can simultaneously drive general routing resources, including interconnect leading to
OBUF buffers.
The feedback loop is essential for DLL operation and is established by driving the CLKFB input with either the CLK0 or the
CLK2X signal so that any undesirable clock distribution delay is included in the loop. It is possible to use either of these two
signals for synchronizing any of the seven DLL outputs: CLK0, CLK90, CLK180, CLK270, CLKDV, CLK2X, or CLK2X180.
The value assigned to the CLK_FEEDBACK attribute must agree with the physical feedback connection: a value of 1X for
the CLK0 case, 2X for the CLK2X case. If the DCM is used in an application that does not require the DLL—i.e., only the
DFS is used—then there is no feedback loop so CLK_FEEDBACK is set to NONE.
CLK2X feedback is only supported on all mask revision ‘E’ and later devices (see Mask and Fab Revisions, page 58), on
devices with the "GQ" fabrication code, and on all versions of the XC3S50 and XC3S1000.
There are two basic cases that determine how to connect the DLL clock outputs and feedback connections: on-chip
synchronization and off-chip synchronization, which are illustrated in Figure 21.
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Spartan-3 FPGA Family: Functional Description
X-Ref Target - Figure 21
FPGA
FPGA
BUFGMUX
CLK0
BUFGMUX
CLK90
CLK180
CLK270
CLKDV
CLK2X
CLK2X180
BUFG
BUFG
CLK90
CLK180
CLK270
CLKDV
CLK2X180
CLKIN
CLKIN
Clock
Net Delay
Clock
Net Delay
DCM
DCM
CLK2X
CLKFB
CLKFB
CLK0
BUFGMUX
BUFGMUX
CLK0
CLK2X
(a) On-Chip with CLK0 Feedback
FPGA
(b) On-Chip with CLK2X Feedback
FPGA
OBUF
CLK0
CLK90
CLK180
CLK270
CLKDV
CLK90
CLK180
CLK270
CLKDV
CLK2X
CLK2X180
OBUF
IBUFG
IBUFG
CLKIN
CLKIN
Clock
Net Delay
Clock
Net Delay
DCM
DCM
CLK2X180
CLKFB
CLK0
CLKFB
CLK2X
OBUF
IBUFG
IBUFG
OBUF
CLK0
CLK2X
(c) Off-Chip with CLK0 Feedback
(d) Off-Chip with CLK2X Feedback
DS099-2_09_082104
Notes:
1. In the Low Frequency mode, all seven DLL outputs are available. In the High Frequency mode, only the CLK0, CLK180, and
CLKDV outputs are available.
Figure 21: Input Clock, Output Clock, and Feedback Connections for the DLL
In the on-chip synchronization case (the [a] and [b] sections of Figure 21), it is possible to connect any of the DLL’s seven
output clock signals through general routing resources to the FPGA’s internal registers. Either a Global Clock Buffer (BUFG)
or a BUFGMUX affords access to the global clock network. As shown in the [a] section of Figure 21, the feedback loop is
created by routing CLK0 (or CLK2X, in the [b] section) to a global clock net, which in turn drives the CLKFB input.
In the off-chip synchronization case (the [c] and [d] sections of Figure 21), CLK0 (or CLK2X) plus any of the DLL’s other
output clock signals exit the FPGA using output buffers (OBUF) to drive an external clock network plus registers on the
board. As shown in the [c] section of Figure 21, the feedback loop is formed by feeding CLK0 (or CLK2X, in the [d] section)
back into the FPGA using an IBUFG, which directly accesses the global clock network, or an IBUF. Then, the global clock net
is connected directly to the CLKFB input.
DLL Frequency Modes
The DLL supports two distinct operating modes, High Frequency and Low Frequency, with each specified over a different
clock frequency range. The DLL_FREQUENCY_MODE attribute chooses between the two modes. When the attribute is set
to LOW, the Low Frequency mode permits all seven DLL clock outputs to operate over a low-to-moderate frequency range.
When the attribute is set to HIGH, the High Frequency mode allows the CLK0, CLK180 and CLKDV outputs to operate at the
highest possible frequencies. The remaining DLL clock outputs are not available for use in High Frequency mode.
Accommodating High Input Frequencies
If the frequency of the CLKIN signal is high such that it exceeds the maximum permitted, divide it down to an acceptable
value using the CLKIN_DIVIDE_BY_2 attribute. When this attribute is set to TRUE, the CLKIN frequency is divided by a
factor of two just as it enters the DCM.
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Spartan-3 FPGA Family: Functional Description
Coarse Phase Shift Outputs of the DLL Component
In addition to CLK0 for zero-phase alignment to the CLKIN signal, the DLL also provides the CLK90, CLK180 and CLK270
outputs for 90°, 180° and 270° phase-shifted signals, respectively. These signals are described in Table 16, page 33. Their
relative timing in the Low Frequency Mode is shown in Figure 22, page 37. The CLK90, CLK180 and CLK270 outputs are
not available when operating in the High Frequency mode. (See the description of the DLL_FREQUENCY_MODE attribute
in Table 17, page 33.) For control in finer increments than 90°, see Phase Shifter (PS), page 39.
Basic Frequency Synthesis Outputs of the DLL Component
The DLL component provides basic options for frequency multiplication and division in addition to the more flexible synthesis
capability of the DFS component, described in a later section. These operations result in output clock signals with
frequencies that are either a fraction (for division) or a multiple (for multiplication) of the incoming clock frequency. The
CLK2X output produces an in-phase signal that is twice the frequency of CLKIN. The CLK2X180 output also doubles the
frequency, but is 180° out-of-phase with respect to CLKIN. The CLKDIV output generates a clock frequency that is a
predetermined fraction of the CLKIN frequency. The CLKDV_DIVIDE attribute determines the factor used to divide the
CLKIN frequency. The attribute can be set to various values as described in Table 17. The basic frequency synthesis outputs
are described in Table 16. Their relative timing in the Low Frequency Mode is shown in Figure 22.
The CLK2X and CLK2X180 outputs are not available when operating in the High Frequency mode. See the description of
the DLL_FREQUENCY_MODE attribute in Table 18.
Duty Cycle Correction of DLL Clock Outputs
(1)
(2)
The CLK2X , CLK2X180, and CLKDV output signals ordinarily exhibit a 50% duty cycle—even if the incoming CLKIN
signal has a different duty cycle. A 50% duty cycle means that the High and Low times of each clock cycle are equal. The
DUTY_CYCLE_CORRECTION attribute determines whether or not duty cycle correction is applied to the CLK0, CLK90,
CLK180 and CLK270 outputs. If DUTY_CYCLE_CORRECTION is set to TRUE, then the duty cycle of these four outputs is
corrected to 50%. If DUTY_CYCLE_CORRECTION is set to FALSE, then these outputs exhibit the same duty cycle as the
CLKIN signal. Figure 22 compares the characteristics of the DLL’s output signals to those of the CLKIN signal.
1. The CLK2X output generates a 25% duty cycle clock at the same frequency as the CLKIN signal until the DLL has achieved lock.
2. The duty cycle of the CLKDV outputs may differ somewhat from 50% (i.e., the signal will be High for less than 50% of the period) when the
CLKDV_DIVIDE attribute is set to a non-integer value and the DLL is operating in the High Frequency mode.
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Spartan-3 FPGA Family: Functional Description
X-Ref Target - Figure 22
0o 90o 180o 270o 0o 90o 180o 270o 0o
Phase:
Input Signal (40% Duty Cycle)
t
CLKIN
Output Signal - Duty Cycle is Always Corrected
CLK2X
CLK2X180
(1)
CLKDV
Output Signal - Attribute Corrects Duty Cycle
DUTY_CYCLE_CORRECTION = FALSE
CLK0
CLK90
CLK180
CLK270
DUTY_CYCLE_CORRECTION = TRUE
CLK0
CLK90
CLK180
CLK270
DS099-2_10_051907
Figure 22: Characteristics of the DLL Clock Outputs
Digital Frequency Synthesizer (DFS)
The DFS component generates clock signals the frequency of which is a product of the clock frequency at the CLKIN input
and a ratio of two user-determined integers. Because of the wide range of possible output frequencies such a ratio permits,
the DFS feature provides still further flexibility than the DLL’s basic synthesis options as described in the preceding section.
The DFS component’s two dedicated outputs, CLKFX and CLKFX180, are defined in Table 19.
The signal at the CLKFX180 output is essentially an inversion of the CLKFX signal. These two outputs always exhibit a 50%
duty cycle. This is true even when the CLKIN signal does not. These DFS clock outputs are driven at the same time as the
DLL’s seven clock outputs.
The numerator of the ratio is the integer value assigned to the attribute CLKFX_MULTIPLY and the denominator is the
integer value assigned to the attribute CLKFX_DIVIDE. These attributes are described in Table 18.
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Spartan-3 FPGA Family: Functional Description
The output frequency (f
) can be expressed as a function of the incoming clock frequency (f
fCLKFX = fCLKIN(CLKFX_MULTIPLY/CLKFX_DIVIDE)
) as follows:
CLKIN
CLKFX
Equation 3
Regarding the two attributes, it is possible to assign any combination of integer values, provided that two conditions are met:
•
•
The two values fall within their corresponding ranges, as specified in Table 18.
The f frequency calculated from the above expression accords with the DCM’s operating frequency
CLKFX
specifications.
For example, if CLKFX_MULTIPLY = 5 and CLKFX_DIVIDE = 3, then the frequency of the output clock signal would be 5/3
that of the input clock signal.
DFS Frequency Modes
The DFS supports two operating modes, High Frequency and Low Frequency, with each specified over a different clock
frequency range. The DFS_FREQUENCY_MODE attribute chooses between the two modes. When the attribute is set to
LOW, the Low Frequency mode permits the two DFS outputs to operate over a low-to-moderate frequency range. When the
attribute is set to HIGH, the High Frequency mode allows both these outputs to operate at the highest possible frequencies.
DFS With or Without the DLL
The DFS component can be used with or without the DLL component:
Without the DLL, the DFS component multiplies or divides the CLKIN signal frequency according to the respective
CLKFX_MULTIPLY and CLKFX_DIVIDE values, generating a clock with the new target frequency on the CLKFX and
CLKFX180 outputs. Though classified as belonging to the DLL component, the CLKIN input is shared with the DFS
component. This case does not employ feedback loop; therefore, it cannot correct for clock distribution delay.
With the DLL, the DFS operates as described in the preceding case, only with the additional benefit of eliminating the clock
distribution delay. In this case, a feedback loop from the CLK0 output to the CLKFB input must be present.
The DLL and DFS components work together to achieve this phase correction as follows: Given values for the
CLKFX_MULTIPLY and CLKFX_DIVIDE attributes, the DLL selects the delay element for which the output clock edge
coincides with the input clock edge whenever mathematically possible. For example, when CLKFX_MULTIPLY = 5 and
CLKFX_DIVIDE = 3, the input and output clock edges will coincide every three input periods, which is equivalent in time to
five output periods.
Smaller CLKFX_MULTIPLY and CLKFX_DIVIDE values achieve faster lock times. With no factors common to the two
attributes, alignment will occur once with every number of cycles equal to the CLKFX_DIVIDE value. Therefore, it is
recommended that the user reduce these values by factoring wherever possible. For example, given CLKFX_MULTIPLY = 9
and CLKFX_DIVIDE = 6, removing a factor of three yields CLKFX_MULTIPLY = 3 and CLKFX_DIVIDE = 2. While both
value-pairs will result in the multiplication of clock frequency by 3/2, the latter value-pair will enable the DLL to lock more
quickly.
Table 18: DFS Attributes
Attribute
DFS_FREQUENCY_MODE
CLKFX_MULTIPLY
Description
Chooses between High Frequency and Low Frequency modes
Frequency multiplier constant
Values
Low, High
Integer from 2 to 32
Integer from 1 to 32
CLKFX_DIVIDE
Frequency divisor constant
Table 19: DFS Signals
Signal
CLKFX
CLKFX180
Direction
Description
Multiplies the CLKIN frequency by the attribute-value ratio (CLKFX_MULTIPLY/CLKFX_DIVIDE) to
generate a clock signal with a new target frequency.
Output
Output
Generates a clock signal with same frequency as CLKFX, only shifted 180° out-of-phase.
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Spartan-3 FPGA Family: Functional Description
DFS Clock Output Connections
There are two basic cases that determine how to connect the DFS clock outputs: on-chip and off-chip, which are illustrated
in sections [a] and [c], respectively, of Figure 21. This is similar to what has already been described for the DLL component.
See DLL Clock Output and Feedback Connections, page 34.
In the on-chip case, it is possible to connect either of the DFS’s two output clock signals through general routing resources
to the FPGA’s internal registers. Either a Global Clock Buffer (BUFG) or a BUFGMUX affords access to the global clock
network. The optional feedback loop is formed in this way, routing CLK0 to a global clock net, which in turn drives the CLKFB
input.
In the off-chip case, the DFS’s two output clock signals, plus CLK0 for an optional feedback loop, can exit the FPGA using
output buffers (OBUF) to drive a clock network plus registers on the board. The feedback loop is formed by feeding the CLK0
signal back into the FPGA using an IBUFG, which directly accesses the global clock network, or an IBUF. Then, the global
clock net is connected directly to the CLKFB input.
Phase Shifter (PS)
The DCM provides two approaches to controlling the phase of a DCM clock output signal relative to the CLKIN signal: First,
there are nine clock outputs that employ the DLL to achieve a desired phase relationship: CLK0, CLK90, CLK180, CLK270,
CLK2X, CLK2X180, CLKDV CLKFX, and CLKFX180. These outputs afford “coarse” phase control.
The second approach uses the PS component described in this section to provide a still finer degree of control. The PS
component is only available when the DLL is operating in its low-frequency mode. The PS component phase shifts the DCM
output clocks by introducing a "fine phase shift" (T ) between the CLKFB and CLKIN signals inside the DLL component.
PS
The user can control this fine phase shift down to a resolution of 1/256 of a CLKIN cycle or one tap delay (DCM_TAP),
whichever is greater. When in use, the PS component shifts the phase of all nine DCM clock output signals together. If the
PS component is used together with a DCM clock output such as the CLK90, CLK180, CLK270, CLK2X180 and CLKFX180,
then the fine phase shift of the former gets added to the coarse phase shift of the latter.
PS Component Enabling and Mode Selection
The CLKOUT_PHASE_SHIFT attribute enables the PS component for use in addition to selecting between two operating
modes. As described in Table 20, this attribute has three possible values: NONE, FIXED and VARIABLE. When
CLKOUT_PHASE_SHIFT is set to NONE, the PS component is disabled and its inputs, PSEN, PSCLK, and PSINCDEC,
must be tied to GND. The set of waveforms in section [a] of Figure 22 shows the disabled case, where the DLL maintains a
zero-phase alignment of signals CLKFB and CLKIN upon which the PS component has no effect. The PS component is
enabled by setting the attribute to either the FIXED or VARIABLE values, which select the Fixed Phase mode and the
Variable Phase mode, respectively. These two modes are described in the sections that follow
Determining the Fine Phase Shift
The user controls the phase shift of CLKFB relative to CLKIN by setting and/or adjusting the value of the PHASE_SHIFT
attribute. This value must be an integer ranging from –255 to +255. The PS component uses this value to calculate the
desired fine phase shift (T ) as a fraction of the CLKIN period (T
). Given values for PHASE-SHIFT and T
, it is
PS
CLKIN
CLKIN
possible to calculate T as follows:
PS
T
= T
(PHASE_SHIFT/256)
CLKIN
Equation 4
PS
Both the Fixed Phase and Variable Phase operating modes employ this calculation. If the PHASE_SHIFT value is zero, then
CLKFB and CLKIN will be in phase, the same as when the PS component is disabled. When the PHASE_SHIFT value is
positive, the CLKFB signal will be shifted later in time with respect to CLKIN. If the attribute value is negative, the CLKFB
signal will be shifted earlier in time with respect to CLKIN.
The Fixed Phase Mode
This mode fixes the desired fine phase shift to a fraction of the T
, as determined by Equation 4 and its user-selected
CLKIN
PHASE_SHIFT value P. The set of waveforms insection [b] of Figure 22 illustrates the relationship between CLKFB and
CLKIN in the Fixed Phase mode. In the Fixed Phase mode, the PSEN, PSCLK and PSINCDEC inputs are not used and
must be tied to GND. Fixed phase shift requires ISE software version 10.1.03 or later.
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Spartan-3 FPGA Family: Functional Description
Values
Table 20: PS Attributes
Attribute
Description
Disables PS component or chooses between Fixed Phase and
Variable Phase modes.
CLKOUT_PHASE_SHIFT
NONE, FIXED, VARIABLE
PHASE_SHIFT
Determines size and direction of initial fine phase shift.
Integers from –255 to +255(1)
Notes:
1. The practical range of values will be less when T
> FINE_SHIFT_RANGE in the Fixed Phase mode, also when T
>
CLKIN
CLKIN
(FINE_SHIFT_RANGE)/2 in the Variable Phase mode. the FINE_SHIFT_RANGE represents the sum total delay of all taps.
The Variable Phase Mode
The “Variable Phase” mode dynamically adjusts the fine phase shift over time using three inputs to the PS component,
namely PSEN, PSCLK and PSINCDEC, as defined in Table 21.
After device configuration, the PS component initially determines T by evaluating Equation (4) for the value assigned to
PS
the PHASE_SHIFT attribute. Then to dynamically adjust that phase shift, use the three PS inputs to increase or decrease
the fine phase shift.
PSINCDEC is synchronized to the PSCLK clock signal, which is enabled by asserting PSEN. It is possible to drive the
PSCLK input with the CLKIN signal or any other clock signal. A request for phase adjustment is entered as follows: For each
PSCLK cycle that PSINCDEC is High, the PS component adds 1/256 of a CLKIN cycle to T . Similarly, for each enabled
PS
PSCLK cycle that PSINCDEC is Low, the PS component subtracts 1/256 of a CLKIN cycle from T . The phase adjustment
PS
may require as many as 100 CLKIN cycles plus three PSCLK cycles to take effect, at which point the output PSDONE goes
High for one PSCLK cycle. This pulse indicates that the PS component has finished the present adjustment and is now
ready for the next request. Asserting the Reset (RST) input, returns T to its original shift time, as determined by the
PS
PHASE_SHIFT attribute value. The set of waveforms in section [c] of Figure 23, page 41 illustrates the relationship between
CLKFB and CLKIN in the Variable Phase mode.
Table 21: Signals for Variable Phase Mode
Signal
PSEN(1)
Direction
Input
Description
Enables PSCLK for variable phase adjustment.
PSCLK(1)
Input
Clock to synchronize phase shift adjustment.
Chooses between increment and decrement for phase adjustment. It is synchronized to the PSCLK
signal.
PSINCDEC(1)
Input
Goes High to indicate that present phase adjustment is complete and PS component is ready for next
phase adjustment request. It is synchronized to the PSCLK signal.
PSDONE
Output
Notes:
1. It is possible to program this input for either a true or inverted polarity
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Spartan-3 FPGA Family: Functional Description
X-Ref Target - Figure 23
a. CLKOUT_PHASE_SHIFT = NONE
CLKIN
CLKFB
b. CLKOUT_PHASE_SHIFT = FIXED
CLKIN
0
–255
+255
Shift Range over all P Values:
P
256
* T
CLKIN
CLKFB
c. CLKOUT_PHASE_SHIFT = VARIABLE
CLKIN
–255
+255
0
Shift Range over all P Values:
P
256
* T
CLKIN
CLKFB before
Decrement
–255
0
+255
Shift Range over all N Values:
N
256
* T
CLKIN
CLKFB after
Decrement
DS099-2_11_031303
Notes:
1. P represents the integer value ranging from –255 to +255 to which the PHASE_SHIFT attribute is assigned.
2. N is an integer value ranging from –255 to +255 that represents the net phase shift effect from a series of increment
and/or decrement operations.
N = {Total number of increments} – {Total number of decrements}
A positive value for N indicates a net increment; a negative value indicates a net decrement.
Figure 23: Phase Shifter Waveforms
The Status Logic Component
The Status Logic component not only reports on the state of the DCM but also provides a means of resetting the DCM to an
initial known state. The signals associated with the Status Logic component are described in Table 22.
As a rule, the Reset (RST) input is asserted only upon configuring the device or changing the CLKIN frequency. A DCM reset
does not affect attribute values (e.g., CLKFX_MULTIPLY and CLKFX_DIVIDE). If not used, RST must be tied to GND.
The eight bits of the STATUS bus are defined in Table 23.
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Spartan-3 FPGA Family: Functional Description
Description
Table 22: Status Logic Signals
Signal
Direction
A High resets the entire DCM to its initial power-on state. Initializes the DLL taps for a delay of zero.
Sets the LOCKED output Low. This input is asynchronous.
RST
Input
STATUS[7:0]
LOCKED
Output
Output
The bit values on the STATUS bus provide information regarding the state of DLL and PS operation
Indicates that the CLKIN and CLKFB signals are in phase by going High. The two signals are
out-of-phase when Low.
Table 23: DCM STATUS Bus
Bit
Name
Description
A value of 1 indicates a phase shift overflow when one of two conditions occurs:
0
Phase Shift Overflow Incrementing (or decrementing) TPS beyond 255/256 of a CLKIN cycle.
The DLL is producing its maximum possible phase shift (i.e., all delay taps are active).(1)
CLKIN Input Stopped A value of 1 indicates that the CLKIN input signal is not toggling. A value of 0 indicates toggling. This
Toggling
1
2
bit functions only when the CLKFB input is connected.(2)
CLKFX/CLKFX180
Output Stopped
Toggling
A value of 1 indicates that the CLKFX or CLKFX180 output signals are not toggling. A value of 0
indicates toggling. This bit functions only when using the Digital Frequency Synthesizer (DFS).
3:7
Reserved
–
Notes:
1. The DLL phase shift with all delay taps active is specified as the parameter FINE_SHIFT_RANGE.
2. If only the DFS clock outputs are used, but none of the DLL clock outputs, this bit will not go High when the CLKIN signal stops.
Table 24: Status Attributes
Attribute
Description
Values
STARTUP_WAIT
Delays transition from configuration to user mode until lock condition is achieved.
TRUE, FALSE
Stabilizing DCM Clocks Before User Mode
It is possible to delay the completion of device configuration until after the DLL has achieved a lock condition using the
STARTUP_WAIT attribute described in Table 24. This option ensures that the FPGA does not enter user mode—i.e., begin
functional operation—until all system clocks generated by the DCM are stable. In order to achieve the delay, it is necessary
to set the attribute to TRUE as well as set the BitGen option LCK_cycle to one of the six cycles making up the Startup phase
of configuration. The selected cycle defines the point at which configuration will halt until the LOCKED output goes High.
Global Clock Network
Spartan-3 devices have eight Global Clock inputs called GCLK0 - GCLK7. These inputs provide access to a
low-capacitance, low-skew network that is well-suited to carrying high-frequency signals. The Spartan-3 FPGAs clock
network is shown in Figure 23. GCLK0 through GCLK3 are located in the center of the bottom edge. GCLK4 through GCLK7
are located in the center of the top edge.
Eight Global Clock Multiplexers (also called BUFGMUX elements) are provided that accept signals from Global Clock inputs
and route them to the internal clock network as well as DCMs. Four BUFGMUX elements are located in the center of the
bottom edge, just above the GCLK0 - GCLK3 inputs. The remaining four BUFGMUX elements are located in the center of
the top edge, just below the GCLK4 - GCLK7 inputs.
Pairs of BUFGMUX elements share global inputs, as shown in Figure 24. For example, the GCLK4 and GCLK5 inputs both
potentially connect to BUFGMUX4 and BUFGMUX5 located in the upper right center. A differential clock input uses a pair of
GCLK inputs to connect to a single BUFGMUX element.
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Spartan-3 FPGA Family: Functional Description
Each BUFGMUX element, shown in Figure 24, is a 2-to-1 multiplexer that can receive signals from any of the four following
sources:
•
•
•
One of the four Global Clock inputs on the same side of the die—top or bottom—as the BUFGMUX element in use.
Any of four nearby horizontal Double lines.
Any of four outputs from the DCM in the right-hand quadrant that is on the same side of the die as the BUFGMUX
element in use.
•
Any of four outputs from the DCM in the left-hand quadrant that is on the same side of the die as the BUFGMUX
element in use.
The multiplexer select line, S, chooses which of the two inputs, I0 or I1, drives the BUFGMUX’s output signal, O, as
described in Table 25. The switching from one clock to the other is glitchless, and done in such a way that the output High
and Low times are never shorter than the shortest High or Low time of either input clock.
Table 25: BUFGMUX Select Mechanism
S Input
O Output
I0 Input
0
1
I1 Input
The two clock inputs can be asynchronous with regard to each other, and the S input can change at any time, except for a
short setup time prior to the rising edge of the presently selected clock (I0 or I1). Violating this setup time requirement can
result in an undefined runt pulse output.
The BUFG clock buffer primitive drives a single clock signal onto the clock network and is essentially the same element as
a BUFGMUX, just without the clock select mechanism. Similarly, the BUFGCE primitive creates an enabled clock buffer
using the BUFGMUX select mechanism.
Each BUFGMUX buffers incoming clock signals to two possible destinations:
•
The vertical spine belonging to the same side of the die—top or bottom—as the BUFGMUX element in use. The two
spines—top and bottom—each comprise four vertical clock lines, each running from one of the BUFGMUX elements
on the same side towards the center of the die. At the center of the die, clock signals reach the eight-line horizontal
spine, which spans the width of the die. In turn, the horizontal spine branches out into a subsidiary clock interconnect
that accesses the CLBs.
•
The clock input of either DCM on the same side of the die—top or bottom—as the BUFGMUX element in use.
Use either a BUFGMUX element or a BUFG (Global Clock Buffer) element to place a Global input in the design. For the
purpose of minimizing the dynamic power dissipation of the clock network, the Xilinx development software automatically
disables all clock line segments that a design does not use.
A global clock line ideally drives clock inputs on the various clocked elements within the FPGA, such as CLB or IOB flip-flops
or block RAMs. A global clock line also optionally drives combinatorial inputs. However, doing so provides additional loading
on the clock line that might also affect clock jitter. Ideally, drive combinatorial inputs using the signal that also drives the input
to the BUFGMUX or BUFG element.
For more details, refer to the chapter entitled “Using Global Clock Resources” in UG331.
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Spartan-3 FPGA Family: Functional Description
X-Ref Target - Figure 24
GCLK4
GCLK6
GCLK5
GCLK7
4
4
4
4
DCM
DCM
4 BUFGMUX
4
8
•
•
•
•
Array Dependent
•
•
8
8
8
Horizontal Spine
•
•
•
•
•
•
Array Dependent
4
4
4
4 BUFGMUX
4
4
DCM
DCM
GCLK1
GCLK3
GCLK0
GCLK2
DS099-2_18_091510
Figure 24: Spartan-3 FPGAs Clock Network (Top View)
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Spartan-3 FPGA Family: Functional Description
Interconnect
Interconnect (or routing) passes signals among the various functional elements of Spartan-3 devices. There are four kinds
of interconnect: Long lines, Hex lines, Double lines, and Direct lines.
Long lines connect to one out of every six CLBs (see section [a] of Figure 25). Because of their low capacitance, these lines
are well-suited for carrying high-frequency signals with minimal loading effects (e.g. skew). If all eight Global Clock Inputs
are already committed and there remain additional clock signals to be assigned, Long lines serve as a good alternative.
Hex lines connect one out of every three CLBs (see section [b] of Figure 25). These lines fall between Long lines and Double
lines in terms of capability: Hex lines approach the high-frequency characteristics of Long lines at the same time, offering
greater connectivity.
Double lines connect to every other CLB (see section [c] of Figure 25). Compared to the types of lines already discussed,
Double lines provide a higher degree of flexibility when making connections.
Direct lines afford any CLB direct access to neighboring CLBs (see section [d] of Figure 25). These lines are most often used
to conduct a signal from a "source" CLB to a Double, Hex, or Long line and then from the longer interconnect back to a Direct
line accessing a "destination" CLB.
For more details, refer to the “Using Interconnect” chapter in UG331.
X-Ref Target - Figure 25
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
6
6
6
6
6
DS099-2_19_040103
(a) Long Lines
8
CLB
CLB
CLB
CLB
CLB
CLB
CLB
DS099-2_20_040103
(b) Hex Lines
CLB
CLB
CLB
CLB
CLB
CLB
CLB
2
CLB
CLB
CLB
CLB
DS099-2_21_040103
(c) Double Lines
CLB
DS099-2_22_040103
(d) Direct Lines
Figure 25: Types of Interconnect
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Spartan-3 FPGA Family: Functional Description
Configuration
Spartan-3 devices are configured by loading application specific configuration data into the internal configuration memory.
Configuration is carried out using a subset of the device pins, some of which are "Dedicated" to one function only, while
others, indicated by the term "Dual-Purpose", can be re-used as general-purpose User I/Os once configuration is complete.
Depending on the system design, several configuration modes are supported, selectable via mode pins. The mode pins M0,
M1, and M2 are Dedicated pins. The mode pin settings are shown in Table 26.
Table 26: Spartan-3 FPGAs Configuration Mode Pin Settings
Configuration Mode(1)
M0
0
M1
0
M2
0
Synchronizing Clock
CCLK Output
CCLK Input
Data Width
Serial DOUT(2)
Master Serial
1
1
8
8
1
Yes
Yes
No
No
No
Slave Serial
Master Parallel
Slave Parallel
JTAG
1
1
1
1
1
0
CCLK Output
CCLK Input
0
1
1
1
0
1
TCK Input
Notes:
1. The voltage levels on the M0, M1, and M2 pins select the configuration mode.
2. The daisy chain is possible only in the Serial modes when DOUT is used.
The HSWAP_EN input pin defines whether the I/O pins that are not actively used during configuration have pull-up resistors
during configuration. By default, HSWAP_EN is tied High (via an internal pull-up resistor if left floating) which shuts off the
pull-up resistors on the user I/O pins during configuration. When HSWAP_EN is tied Low, user I/Os have pull-ups during
configuration. The Dedicated configuration pins (CCLK, DONE, PROG_B, M2, M1, M0, HSWAP_EN) and the JTAG pins
(TDI, TMS, TCK, and TDO) always have a pull-up resistor to VCCAUX during configuration, regardless of the value on the
HSWAP_EN pin. Similarly, the dual-purpose INIT_B pin has an internal pull-up resistor to VCCO_4 or VCCO_BOTTOM,
depending on the package style.
Depending on the chosen configuration mode, the FPGA either generates a CCLK output, or CCLK is an input accepting an
externally generated clock.
A persist option is available which can be used to force the configuration pins to retain their configuration function even after
device configuration is complete. If the persist option is not selected then the configuration pins with the exception of CCLK,
PROG_B, and DONE can be used as user I/O in normal operation. The persist option does not apply to the boundary-scan
related pins. The persist feature is valuable in applications that readback configuration data after entering the User mode.
Table 27 lists the total number of bits required to configure each FPGA as well as the PROMs suitable for storing those bits.
See DS123: Platform Flash In-System Programmable Configuration PROMs data sheet for more information.
Table 27: Spartan-3 FPGA Configuration Data
Xilinx Platform Flash PROM
Device
File Sizes
Serial Configuration
XCF01S
Parallel Configuration
XCF08P
XC3S50
439,264
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
1,047,616
1,699,136
3,223,488
5,214,784
7,673,024
11,316,864
13,271,936
XCF01S
XCF08P
XCF02S
XCF08P
XCF04S
XCF08P
XCF08P
XCF08P
XCF08P
XCF08P
XCF16P
XCF16P
XCF16P
XCF16P
The maximum bitstream length that Spartan-3 FPGAs support in serial daisy-chains is 4,294,967,264 bits (4 Gbits), roughly
equivalent to a daisy-chain with 323 XC3S5000 FPGAs. This is a limit only for serial daisy-chains where configuration data
is passed via the FPGA’s DOUT pin. There is no such limit for JTAG chains.
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Spartan-3 FPGA Family: Functional Description
The Standard Configuration Interface
Configuration signals belong to one of two different categories: Dedicated or Dual-Purpose. Which category determines
which of the FPGA’s power rails supplies the signal’s driver and, thus, helps describe the electrical characteristics at the pin.
The Dedicated configuration pins include PROG_B, HSWAP_EN, TDI, TMS, TCK, TDO, CCLK, DONE, and M0-M2. These
pins are powered by the V
supply.
CCAUX
The Dual-Purpose configuration pins comprise INIT_B, DOUT, BUSY, RDWR_B, CS_B, and DIN/D0-D7. Each of these pins,
according to its bank placement, uses the V lines for either Bank 4 (VCCO_4 on most packages, VCCO_BOTTOM on
CCO
TQ144 and CP132 packages) or Bank 5 (VCCO_5). All the signals used in the serial configuration modes rely on VCCO_4
power. Signals used in the parallel configuration modes and Readback require from VCCO_5 as well as from VCCO_4.
Both the Dedicated signals described above and the Dual-Purpose signals constitute the configuration interface. The
Dedicated pins, powered by the 2.5V V
supply, always use the LVCMOS25 I/O standard. The Dual-Purpose signals,
CCAUX
however, are powered by the VCCO_4 supply and also by the VCCO_5 supply in the Parallel configuration modes. The
simplest configuration interface uses 2.5V for VCCO_4 and VCCO_5, if required. However, VCCO_4 and, if needed,
VCCO_5 can be voltages other than 2.5V but then the configuration interface will have two voltage levels: 2.5V for V
CCAUX
and a separate V
supply. The Dual-Purpose signals default to the LVCMOS input and output levels for the associated
CCO
V
voltage supply.
CCO
3.3V-Tolerant Configuration Interface
A 3.3V-tolerant configuration interface simply requires adding a few external resistors as described in detail in XAPP453:
The 3.3V Configuration of Spartan-3 FPGAs.
The 3.3V-tolerance is implemented as follows (a similar approach can be used for other supply voltage levels):
Apply 3.3V to VCCO_4 and, in some configuration modes, to VCCO_5 to power the Dual-Purpose configuration pins. This
scales the output voltages and input thresholds associated with these pins so that they become 3.3V-compatible.
Apply 2.5V to V
to power the Dedicated configuration pins. For 3.3V-tolerance, the Dedicated inputs require series
CCAUX
resistors to limit the incoming current to 10 mA or less. The Dedicated outputs have reduced noise margin when the FPGA
drives a High logic level into another device’s 3.3V receiver. Choose a power regulator or supply that can tolerate reverse
current on the V
lines.
CCAUX
Configuration Modes
Spartan-3 FPGAs support the following five configuration modes:
•
•
•
•
•
Slave Serial mode
Master Serial mode
Slave Parallel (SelectMAP) mode
Master Parallel (SelectMAP) mode
Boundary-Scan (JTAG) mode (IEEE 1532/IEEE 1149.1)
Slave Serial Mode
In Slave Serial mode, the FPGA receives configuration data in bit-serial form from a serial PROM or other serial source of
configuration data. The FPGA on the far right of Figure 26 is set for the Slave Serial mode. The CCLK pin on the FPGA is
an input in this mode. The serial bitstream must be set up at the DIN input pin a short time before each rising edge of the
externally generated CCLK.
Multiple FPGAs can be daisy-chained for configuration from a single source. After a particular FPGA has been configured,
the data for the next device is routed internally to the DOUT pin. The data on the DOUT pin changes on the falling edge of
CCLK.
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Spartan-3 FPGA Family: Functional Description
X-Ref Target - Figure 26
3.3V: XCF0xS
1.8V: XCFxxP
2.5V
2.5V
2.5V
1.2V
1.2V
V
Bank 4
V
Bank 4
CCO
CCO
V
CCO
V
V
V
V
CCINT
CCAUX
CCINT
CCAUX
V
V
CCINT
CCJ
D0
DIN
DOUT
DIN
Spartan-3
FPGA
Spartan-3
FPGA
Platform
Flash PROM
2.5V
2.5V
Master
Slave
M0
M1
M2
M0
M1
M2
XCF0xS
or
All
4.7KΩ
XCFxxP
CE
DONE
DONE
OE/RESET
CF
INIT_B
PROG_B
CCLK
INIT_B
PROG_B
CCLK
CLK
GND
GND
GND
DS099_23_112905
Notes:
1. There are two ways to use the DONE line. First, one may set the BitGen option DriveDone to "Yes" only for the last
FPGA to be configured in the chain shown above (or for the single FPGA as may be the case). This enables the DONE
pin to drive High; thus, no pull-up resistor is necessary. DriveDone is set to "No" for the remaining FPGAs in the chain.
Second, DriveDone can be set to "No" for all FPGAs. Then all DONE lines are open-drain and require the pull-up
resistor shown in grey. In most cases, a value between 3.3KΩ to 4.7KΩ is sufficient. However, when using DONE
synchronously with a long chain of FPGAs, cumulative capacitance may necessitate lower resistor values (e.g. down
to 330Ω) in order to ensure a rise time within one clock cycle.
2. For information on how to program the FPGA using 3.3V signals and power, see 3.3V-Tolerant Configuration Interface.
Figure 26: Connection Diagram for Master and Slave Serial Configuration
Slave Serial mode is selected by applying <111> to the mode pins (M0, M1, and M2). A pull-up on the mode pins makes
slave serial the default mode if the pins are left unconnected.
Master Serial Mode
In Master Serial mode, the FPGA drives CCLK pin, which behaves as a bidirectional I/O pin. The FPGA in the center of
Figure 26 is set for Master Serial mode and connects to the serial configuration PROM and to the CCLK inputs of any slave
FPGAs in a configuration daisy-chain. The master FPGA drives the configuration clock on the CCLK pin to the Xilinx Serial
PROM, which, in response, provides bit-serial data to the FPGA’s DIN input. The FPGA accepts this data on each rising
CCLK edge. After the master FPGA finishes configuring, it passes data on its DOUT pin to the next FPGA device in a
daisy-chain. The DOUT data appears after the falling CCLK clock edge.
The Master Serial mode interface is identical to Slave Serial except that an internal oscillator generates the configuration
clock (CCLK). A wide range of frequencies can be selected for CCLK, which always starts at a default frequency of 6 MHz.
Configuration bits then switch CCLK to a higher frequency for the remainder of the configuration.
Slave Parallel Mode (SelectMAP)
The Parallel or SelectMAP modes support the fastest configuration. Byte-wide data is written into the FPGA with a BUSY
flag controlling the flow of data. An external source provides 8-bit-wide data, CCLK, an active-Low Chip Select (CS_B) signal
and an active-Low Write signal (RDWR_B). If BUSY is asserted (High) by the FPGA, the data must be held until BUSY goes
Low. Data can also be read using the Slave Parallel mode. If RDWR_B is asserted, configuration data is read out of the
FPGA as part of a readback operation.
After configuration, it is possible to use any of the Multipurpose pins (DIN/D0-D7, DOUT/BUSY, INIT_B, CS_B, and
RDWR_B) as User I/Os. To do this, simply set the BitGen option Persist to No and assign the desired signals to multipurpose
configuration pins using the Xilinx development software. Alternatively, it is possible to continue using the configuration port
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48
Spartan-3 FPGA Family: Functional Description
(e.g. all configuration pins taken together) when operating in the User mode. This is accomplished by setting the Persist
option to Yes.
Multiple FPGAs can be configured using the Slave Parallel mode and can be made to start-up simultaneously. Figure 27
shows the device connections. To configure multiple devices in this way, wire the individual CCLK, Data, RDWR_B, and
BUSY pins of all the devices in parallel. The individual devices are loaded separately by deasserting the CS_B pin of each
device in turn and writing the appropriate data.
X-Ref Target - Figure 27
D[0:7]
CCLK
RDWR_B
BUSY
2.5V
2.5V
1.2V
1.2V
V
Banks 4 & 5
V
Banks 4 & 5
CCO
CCO
V
V
V
V
CCINT
CCAUX
CCINT
CCAUX
Spartan-3
Slave
Spartan-3
Slave
D[0:7]
D[0:7]
CCLK
CCLK
RDWR_B
BUSY
RDWR_B
BUSY
2.5V
2.5V
CS_B
CS_B
CS_B
CS_B
M1
M2
M0
M1
M2
M0
PROG_B
DONE
PROG_B
DONE
2.5V
INIT_B
INIT_B
GND
GND
4.7KΩ
4.7KΩ
DONE
INIT_B
PROG_B
DS099_24_041103
Notes:
1. There are two ways to use the DONE line. First, one may set the BitGen option DriveDone to "Yes" only for the last FPGA to be
configured in the chain shown above (or for the single FPGA as may be the case). This enables the DONE pin to drive High; thus,
no pull-up resistor is necessary. DriveDone is set to "No" for the remaining FPGAs in the chain. Second, DriveDone can be set to
"No" for all FPGAs. Then all DONE lines are open-drain and require the pull-up resistor shown in grey. In most cases, a value
between 3.3KΩ to 4.7KΩ is sufficient. However, when using DONE synchronously with a long chain of FPGAs, cumulative
capacitance may necessitate lower resistor values (e.g. down to 330Ω) in order to ensure a rise time within one clock cycle.
2. If the FPGAs use different configuration data files, configure them in sequence by first asserting the CS_B of one FPGA then
asserting the CS_B of the other FPGA.
3. For information on how to program the FPGA using 3.3V signals and power, see 3.3V-Tolerant Configuration Interface.
Figure 27: Connection Diagram for Slave Parallel Configuration
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Spartan-3 FPGA Family: Functional Description
X-Ref Target - Figure 28
2.5V
1.8V
2.5V
1.2V
V
Banks 4 & 5
CCO
V
V
CCINT
CCAUX
V
CCO
Spartan-3
Master
V
V
CCJ
CCINT
DATA[0:7]
CCLK
D[0:7]
CCLK
2.5V
Platform Flash
PROM
All
4.7KΩ
XCFxxP
CF
PROG_B
DONE
CE
OE/RESET
INIT_B
GND
RDWR_B
CS_B
GND
DS099_25_112905
Notes:
1. There are two ways to use the DONE line. First, one may set the BitGen option DriveDone to "Yes" only for
the last FPGA to be configured in the chain shown above (or for the single FPGA as may be the case). This
enables the DONE pin to drive High; thus, no pull-up resistor is necessary. DriveDone is set to "No" for the
remaining FPGAs in the chain. Second, DriveDone can be set to "No" for all FPGAs. Then all DONE lines
are open-drain and require the pull-up resistor shown in grey. In most cases, a value between 3.3KΩ to
4.7KΩ is sufficient. However, when using DONE synchronously with a long chain of FPGAs, cumulative
capacitance may necessitate lower resistor values (e.g. down to 330Ω) in order to ensure a rise time within
one clock cycle.
Figure 28: Connection Diagram for Master Parallel Configuration
Master Parallel Mode
In this mode, the FPGA configures from byte-wide data, and the FPGA supplies the CCLK configuration clock. In Master
configuration modes, CCLK behaves as a bidirectional I/O pin. Timing is similar to the Slave Parallel mode except that CCLK
is supplied by the FPGA. The device connections are shown in Figure 28.
Boundary-Scan (JTAG) Mode
In Boundary-Scan mode, dedicated pins are used for configuring the FPGA. The configuration is done entirely through the
IEEE 1149.1 Test Access Port (TAP). FPGA configuration using the Boundary-Scan mode is compatible with the IEEE Std
1149.1-1993 standard and IEEE Std 1532 for In-System Configurable (ISC) devices.
Configuration through the boundary-scan port is always available, regardless of the selected configuration mode. In some
cases, however, the mode pin setting may affect proper programming of the device due to various interactions. For example,
if the mode pins are set to Master Serial or Master Parallel mode, and the associated PROM is already programmed with a
valid configuration image, then there is potential for configuration interference between the JTAG and PROM data. Selecting
the Boundary-Scan mode disables the other modes and is the most reliable mode when programming via JTAG.
Configuration Sequence
The configuration of Spartan-3 devices is a three-stage process that occurs after Power-On Reset or the assertion of
PROG_B. POR occurs after the V
, V
, and V
Bank 4 supplies have reached their respective maximum input
CCINT CCAUX
CCO
threshold levels (see Table 29, page 59). After POR, the three-stage process begins.
First, the configuration memory is cleared. Next, configuration data is loaded into the memory, and finally, the logic is
activated by a start-up process. A flow diagram for the configuration sequence of the Serial and Parallel modes is shown in
Figure 29. The flow diagram for the Boundary-Scan configuration sequence appears in Figure 30.
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Spartan-3 FPGA Family: Functional Description
X-Ref Target - Figure 29
Set PROG_B Low
after Power-On
Power-On
VCCINT >1V
and VCCAUX > 2V
No
and VCCO Bank 4 > 1V
Yes
Yes
Clear configuration
memory
PROG_B = Low
No
No
INIT_ B = High?
Yes
Sample mode pins
Load configuration
data frames
No
INIT_B goes Low.
Abort Start-Up
CRC
correct?
Yes
Start-Up
sequence
User mode
No
Yes
Reconfigure?
DS099_26_041103
Figure 29: Configuration Flow Diagram for the Serial and Parallel Modes
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Spartan-3 FPGA Family: Functional Description
X-Ref Target - Figure 30
Set PROG_B Low
after Power-On
Power-On
VCCINT >1V
and VCCAUX > 2V
No
and VCCO Bank 4 > 1V
Yes
Clear
configuration
memory
Yes
PROG_B = Low
No
No
INIT_B = High?
Yes
Sample
mode pins
(JTAG port becomes
available)
Load
JShutdown
instruction
Shutdown
sequence
Load CFG_IN
instruction
Load configuration
data frames
No
CRC
correct?
INIT_B goes Low.
Abort Start-Up
Yes
Synchronous
TAP reset
(Clock five 1's
on TMS)
Load JSTART
instruction
Start-Up
sequence
User mode
Yes
No
Reconfigure?
DS099_27_041103
Figure 30: Boundary-Scan Configuration Flow Diagram
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Spartan-3 FPGA Family: Functional Description
Configuration is automatically initiated after power-on unless it is delayed by the user. INIT_B is an open-drain line that the
FPGA holds Low during the clearing of the configuration memory. Extending the time that the pin is Low causes the
configuration sequencer to wait. Thus, configuration is delayed by preventing entry into the phase where data is loaded.
The configuration process can also be initiated by asserting the PROG_B pin. The end of the memory-clearing phase is
signaled by the INIT_B pin going High. At this point, the configuration data is written to the FPGA. The FPGA pulses the
Global Set/Reset (GSR) signal at the end of configuration, resetting all flip-flops. The completion of the entire process is
signaled by the DONE pin going High.
X-Ref Target - Figure 31
Default Cycles
Start-Up Clock
Phase
0
1
2
3
4
5
6 7
DONE
GTS
GWE
Sync-to-DONE
Start-Up Clock
Phase
0
1
2
3
4
5
6 7
DONE High
DONE
GTS
GWE
DS099_028_060905
Figure 31: Default Start-Up Sequence
The default start-up sequence, shown in Figure 31, serves as a transition to the User mode. The default start-up sequence
is that one CCLK cycle after DONE goes High, the Global Three-State signal (GTS) is released. This permits device outputs
to which signals have been assigned to become active. One CCLK cycle later, the Global Write Enable (GWE) signal is
released. This permits the internal storage elements to begin changing state in response to the design logic and the user
clock.
The relative timing of configuration events can be changed via the BitGen options in the Xilinx development software. In
addition, the GTS and GWE events can be made dependent on the DONE pins of multiple devices all going High, forcing the
devices to start synchronously. The sequence can also be paused at any stage, until lock has been achieved on any DCM.
Readback
Using Slave Parallel mode, configuration data from the FPGA can be read back. Readback is supported only in the Slave
Parallel and Boundary-Scan modes.
Along with the configuration data, it is possible to read back the contents of all registers, distributed RAM, and block RAM
resources. This capability is used for real-time debugging.
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Spartan-3 FPGA Family: Functional Description
Additional Configuration Details
Additional details about the Spartan-3 FPGA configuration architecture and command set are available in UG332: Spartan-3
Generation Configuration User Guide and in application note XAPP452: Spartan-3 Advanced Configuration Architecture.
Powering Spartan-3 FPGAs
Voltage Regulators
Various power supply manufacturers offer complete power solutions for Xilinx FPGAs, including some with integrated
multi-rail regulators specifically designed for Spartan-3 FPGAs. The Xilinx Power Corner web page provides links to vendor
solution guides as well as Xilinx power estimation and analysis tools.
Power Distribution System (PDS) Design and Bypass/Decoupling Capacitors
Good power distribution system (PDS) design is important for all FPGA designs, especially for high-performance
applications. Proper design results in better overall performance, lower clock and DCM jitter, and a generally more robust
system. Before designing the printed circuit board (PCB) for the FPGA design, review application note XAPP623: Power
Distribution System (PDS) Design: Using Bypass/Decoupling Capacitors.
Power-On Behavior
Spartan-3 FPGAs have a built-in Power-On Reset (POR) circuit that monitors the three power rails required to successfully
configure the FPGA. At power-up, the POR circuit holds the FPGA in a reset state until the V
, V
, and V
Bank
CCINT CCAUX
CCO
4 supplies reach their respective input threshold levels (see Table 29, page 59). After all three supplies reach their respective
threshold, the POR reset is released and the FPGA begins its configuration process.
Because the three supply inputs must be valid to release the POR reset and can be supplied in any order, there are no
specific voltage sequencing requirements. However, applying the FPGA’s V
supply before the V
supply uses the
CCAUX
CCINT
least I
current.
CCINT
Once all three supplies are valid, the minimum current required to power-on the FPGA is equal to the worst-case quiescent
current, as specified in Table 34, page 62. Spartan-3 FPGAs do not require Power-On Surge (POS) current to successfully
configure.
Surplus ICCINT if VCCINT Applied before VCCAUX
If the V
supply is applied before the V
supply, the FPGA may draw a surplus I
current in addition to the
CCINT
CCINT
CCAUX
I
quiescent current levels specified in Table 34. The momentary additional I
surplus current might be a few
CCINT
CCINT
hundred milliamperes under nominal conditions, significantly less than the instantaneous current consumed by the bypass
capacitors at power-on. However, the surplus current immediately disappears when the V supply is applied, and, in
CCAUX
response, the FPGA’s I
quiescent current demand drops to the levels specified in Table 34. The FPGA does not use
CCINT
nor does it require the surplus current to successfully power-on and configure. If applying V
- before V
, ensure
CCINT
CCAUX
that the regulator does not have a foldback feature that could inadvertently shut down in the presence of the surplus current.
Maximum Allowed VCCINT Ramp Rate on Early Devices, if VVCCINTSupply is Last in Sequence
All devices with a mask revision code ‘E’ or later do not have a V
page 58.
ramp rate requirement. See Mask and Fab Revisions,
CCINT
Early Spartan-3 FPGAs were produced at a 200 mm wafer production facility and are identified by a fabrication/process
code of "FQ" on the device top marking, as shown in Package Marking, page 5. These "FQ" devices have a maximum
V
ramp rate requirement if and only if V
is the last supply to ramp, after the V
and V
Bank 4 supplies.
CCINT
CCINT
CCAUX
CCO
This maximum ramp rate appears as T
in Table 30, page 60.
CCINT
Minimum Allowed VCCO Ramp Rate on Early Devices
Devices shipped since 2006 essentially have no V
ramp rate limits, shown in Table 30, page 60. Similarly, all devices
CCO
with a mask revision code ‘E’ or later do not have a V
ramp rate limit. See Mask and Fab Revisions, page 58.
CCO
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Spartan-3 FPGA Family: Functional Description
Initial Spartan-3 FPGA mask revisions have a limit on how fast the V
supply can ramp. The minimum allowed V
ramp
CCO
CCO
rate appears as T
in Table 30, page 60. The minimum rate is affected by the package inductance. Consequently, the ball
CCO
grid array and chip-scale packages (CP132, FT256, FG456, FG676, and FG900) allow a faster ramp rate than the quad-flat
packages (VQ100, TQ144, and PQ208).
Configuration Data Retention, Brown-Out
The FPGA’s configuration data is stored in robust CMOS configuration latches. The data in these latches is retained even
when the voltages drop to the minimum levels necessary to preserve RAM contents. This is specified in Table 31, page 60.
If, after configuration, the V
or V
supply drops below its data retention voltage, clear the current device
CCINT
CCAUX
configuration using one of the following methods:
•
Force the V
page 59).
or V
supply voltage below the minimum Power On Reset (POR) voltage threshold Table 29,
CCINT
CCAUX
•
Assert PROG_B Low.
The POR circuit does not monitor the VCCO_4 supply after configuration. Consequently, dropping the VCCO_4 voltage
does not reset the device by triggering a Power-On Reset (POR) event.
No Internal Charge Pumps or Free-Running Oscillators
Some system applications are sensitive to sources of analog noise. Spartan-3 FPGA circuitry is fully static and does not
employ internal charge pumps.
The CCLK configuration clock is active during the FPGA configuration process. After configuration completes, the CCLK
oscillator is automatically disabled unless the Bitstream Generator (BitGen) option Persist=Yes. See Module 4: Table 80,
page 125.
Spartan-3 FPGAs optionally support a featured called Digitally Controlled Impedance (DCI). When used in an application,
the DCI logic uses an internal oscillator. The DCI logic is only enabled if the FPGA application specifies an I/O standard that
requires DCI (LVDCI_33, LVDCI_25, etc.). If DCI is not used, the associated internal oscillator is also disabled.
In summary, unless an application uses the Persist=Yes option or specifies a DCI I/O standard, an FPGA with no external
switching remains fully static.
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Spartan-3 FPGA Family: Functional Description
Revision History
Date
Version No.
Description
04/11/2003
05/19/2003
07/11/2003
1.0
1.1
1.2
Initial Xilinx release
Added Block RAM column, DCMs, and multipliers to XC3S50 descriptions.
Explained the configuration port Persist option in Slave Parallel Mode (SelectMAP) section. Updated
Figure 8 and Double-Data-Rate Transmission section to indicate that DDR clocking for the XC3S50 is the
same as that for all other Spartan-3 devices. Updated description of I/O voltage tolerance in ESD
Protection section. In Table 10, changed input termination type for DCI version of the LVCMOS standard
to None. Added additional flexibility for making DLL connections in Figure 21 and accompanying text. In
the Configuration section, inserted an explanation of how to choose power supplies for the configuration
interface, including guidelines for achieving 3.3V-tolerance.
08/24/2004
08/19/2005
1.3
1.4
Showed inversion of 3-state signal (Figure 7). Clarified description of pull-up and pull-down resistors
(Table 6 and page 13). Added information on operating block RAM with multipliers to page 26. Corrected
output buffer name in Figure 21. Corrected description of how DOUT is synchronized to CCLK (page 47).
Corrected description of WRITE_FIRST and READ_FIRST in Table 13. Added note regarding address
setup and hold time requirements whenever a block RAM port is enabled (Table 13). Added information
in the maximum length of a Configuration daisy-chain. Added reference to XAPP453 in 3.3V-Tolerant
Configuration Interface section. Added information on the STATUS[2] DCM output (Table 23). Added
information on CCLK behavior and termination recommendations to Configuration. Added Additional
Configuration Details section. Added Powering Spartan-3 FPGAs section. Removed GSR from Figure 31
because its timing is not programmable.
04/03/2006
04/26/2006
05/25/2007
2.0
2.1
2.2
Updated Figure 7. Updated Figure 14. Updated Table 10. Updated Figure 22. Corrected Platform Flash
supply voltage name and value in Figure 26 and Figure 28. Added No Internal Charge Pumps or
Free-Running Oscillators. Corrected a few minor typographical errors.
Added more information on the pull-up resistors that are active during configuration to Configuration.
Added information to Boundary-Scan (JTAG) Mode about potential interactions when configuring via
JTAG if the mode select pins are set for other than JTAG.
Added Spartan-3 FPGA Design Documentation. Noted SSTL2_I_DCI 25-Ohm driver in Table 10 and
Table 11. Added note that pull-down is active during boundary scan tests.
11/30/2007
06/25/2008
12/04/2009
2.3
2.4
2.5
Updated links to documentation on xilinx.com.
Added HSLVDCI to Table 10. Updated formatting and links.
Updated HSLVDCI description in Digitally Controlled Impedance (DCI). Updated the low-voltage
differential signaling VCCO values in Table 10. Noted that the CP132 package is being discontinued in The
Organization of IOBs into Banks. Updated rule 4 in Rules Concerning Banks. Added software version
requirement in The Fixed Phase Mode.
10/29/2012
06/27/2013
3.0
3.1
Added Notice of Disclaimer. Per XCN07022, updated the discontinued FG1156 and FGG1156 package
discussion throughout document. Per XCN08011, updated the discontinued CP132 and CPG132
package discussion throughout document. This product is not recommended for new designs.
Removed banner. This product IS recommended for new designs.
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Spartan-3 FPGA Family: Functional Description
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED
WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE
SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
CRITICAL APPLICATIONS DISCLAIMER
XILINX PRODUCTS (INCLUDING HARDWARE, SOFTWARE AND/OR IP CORES) ARE NOT DESIGNED OR INTENDED TO BE
FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS IN LIFE-SUPPORT OR
SAFETY DEVICES OR SYSTEMS, CLASS III MEDICAL DEVICES, NUCLEAR FACILITIES, APPLICATIONS RELATED TO THE
DEPLOYMENT OF AIRBAGS, OR ANY OTHER APPLICATIONS THAT COULD LEAD TO DEATH, PERSONAL INJURY OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE (INDIVIDUALLY AND COLLECTIVELY, “CRITICAL APPLICATIONS”). FURTHERMORE,
XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN ANY APPLICATIONS THAT AFFECT CONTROL OF A
VEHICLE OR AIRCRAFT, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF
SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE
OPERATOR. CUSTOMER AGREES, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE XILINX
PRODUCTS, TO THOROUGHLY TEST THE SAME FOR SAFETY PURPOSES. TO THE MAXIMUM EXTENT PERMITTED BY
APPLICABLE LAW, CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN CRITICAL
APPLICATIONS.
AUTOMOTIVE APPLICATIONS DISCLAIMER
XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING
FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A
VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN
THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III)
USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY
USE OF XILINX PRODUCTS IN SUCH APPLICATIONS.
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106
Spartan-3 FPGA Family:
DC and Switching Characteristics
DS099 (v3.1) June 27, 2013
Product Specification
DC Electrical Characteristics
In this section, specifications may be designated as Advance, Preliminary, or Production. These terms are defined as
follows:
•
•
•
Advance: Initial estimates are based on simulation, early characterization, and/or extrapolation from the characteristics
of other families. Values are subject to change. Although speed grades with this designation are considered relatively
stable and conservative, some under-reporting might still occur. Use as estimates, not for production.
Preliminary: Based on complete early silicon characterization. Devices and speed grades with this designation are
intended to give a better indication of the expected performance of production silicon. The probability of under-reported
delays is greatly reduced compared to Advance data. Use as estimates, not for production.
Production: These specifications are approved only after silicon has been characterized over numerous production
lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes.
Parameter values are considered stable with no future changes expected.
Production-quality systems must only use FPGA designs compiled with a Production status speed file. FPGA designs
using a less mature speed file designation should only be used during system prototyping or preproduction qualification.
FPGA designs with speed files designated as Advance or Preliminary should not be used in a production-quality
system.
Whenever a speed file designation changes, as a device matures toward Production status, rerun the latest Xilinx ISE®
software on the FPGA design to ensure that the FPGA design incorporates the latest timing information and software
updates.
All parameter limits are representative of worst-case supply voltage and junction temperature conditions. The following
applies unless otherwise noted: The parameter values published in this module apply to all Spartan®-3 devices. AC
and DC characteristics are specified using the same numbers for both commercial and industrial grades. All
parameters representing voltages are measured with respect to GND.
Mask and Fab Revisions
Some specifications list different values for one or more mask or fab revisions, indicated by the device top marking (see
Package Marking, page 5). The revision differences involve the power ramp rates, differential DC specifications, and DCM
characteristics. The most recent revision (mask rev E and GQ fab/geometry code) is errata-free with improved specifications
than earlier revisions.
Mask rev E with fab rev GQ has been shipping since 2005 (see XCN05009) and has been 100% of Xilinx Spartan-3 device
shipments since 2006. SCD 0974 was provided to ensure the receipt of the rev E silicon, but it is no longer needed. Parts
ordered under the SCD appended “0974” to the standard part number. For example, “XC3S50-4VQ100C” became
“XC3S50-4VQ100C0974”.
Table 28: Absolute Maximum Ratings
Symbol
Description
Conditions
Min
–0.5
–0.5
–0.5
–0.5
–0.95
–0.85
–0.5
Max
1.32
Units
VCCINT
Internal supply voltage relative to GND
V
V
V
V
V
VCCAUX Auxiliary supply voltage relative to GND
3.00
VCCO
VREF
VIN
Output driver supply voltage relative to GND
Input reference voltage relative to GND
3.75
VCCO +0.5
4.4
Voltage applied to all User I/O pins and
Dual-Purpose pins relative to GND(2,4)
Driver in a
Commercial
Industrial
high-impedance
state
4.3
Voltage applied to all Dedicated pins relative
to GND(3)
All temp. ranges
VCCAUX + 0.5
V
© Copyright 2003–2013 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, Artix, Kintex, Zynq, Vivado and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
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Spartan-3 FPGA Family: DC and Switching Characteristics
Table 28: Absolute Maximum Ratings (Cont’d)
Symbol
IIK
Description
Conditions
Min
–
Max
100
2000
500
200
125
220
150
Units
mA
V
Input clamp current per I/O pin
–0.5 V < VIN < (VCCO + 0.5 V)
VESD
Electrostatic Discharge Voltage pins relative Human body model
–
to GND
Charged device model
–
V
Machine model
Junction temperature
–
V
TJ
–
°C
°C
°C
TSOL
TSTG
Soldering temperature(4)
–
Storage temperature
–65
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only;
functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions is not
implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time adversely affects device reliability.
2. All User I/O and Dual-Purpose pins (DIN/D0, D1–D7, CS_B, RDWR_B, BUSY/DOUT, and INIT_B) draw power from the V
power rail of
CCO
the associated bank. Keeping VIN within 500 mV of the associated V
rails or ground rail ensures that the internal diode junctions that
CCO
exist between each of these pins and the V
limit. Input voltages outside the –0.5V to V
and GND rails do not turn on. Table 32 specifies the V
range used to determine the max
CCO
CCO
+0.5V voltage range are permissible provided that the I input clamp diode rating is met and
CCO
IK
no more than 100 pins exceed the range simultaneously. Prolonged exposure to such current may compromise device reliability. A sustained
current of 10 mA will not compromise device reliability. See XAPP459, Eliminating I/O Coupling Effects when Interfacing Large-Swing
Single-Ended Signals to User I/O Pins on Spartan-3 Generation FPGAs for more details. The VIN limits apply to both the DC and AC
components of signals. Simple application solutions are available that show how to handle overshoot/undershoot as well as achieve PCI
compliance. Refer to the following application notes: XAPP457, Powering and Configuring Spartan-3 Generation FPGAs in Compliant PCI
Applications and XAPP659, Virtex®-II Pro / Virtex-II Pro X 3.3V I/O Design Guidelines.
3. All Dedicated pins (M0–M2, CCLK, PROG_B, DONE, HSWAP_EN, TCK, TDI, TDO, and TMS) draw power from the V
rail (2.5V).
CCAUX
Meeting the V max limit ensures that the internal diode junctions that exist between each of these pins and the V
rail do not turn on.
IN
CCAUX
Table 32 specifies the V
range used to determine the max limit. When V
is at its maximum recommended operating level
CCAUX
CCAUX
(2.625V), V max < 3.125V. As long as the V max specification is met, oxide stress is not possible. For information concerning the use of
IN
IN
3.3V signals, see the 3.3V-Tolerant Configuration Interface, page 47. See also XAPP459.
4. For soldering guidelines, see UG112, Device Packaging and Thermal Characteristics and XAPP427, Implementation and Solder Reflow
Guidelines for Pb-Free Packages.
Table 29: Supply Voltage Thresholds for Power-On Reset
Symbol
VCCINTT
VCCAUXT
VCCO4T
Description
Threshold for the VCCINT supply
Min
0.4
0.8
0.4
Max
1.0
Units
V
V
V
Threshold for the VCCAUX supply
2.0
Threshold for the VCCO Bank 4 supply
1.0
Notes:
1.
V
, V
, and V
supplies may be applied in any order. When applying V
power before V
CCAUX
power, the FPGA may draw
CCAUX
CCINT CCAUX
CCO
CCINT
a surplus current in addition to the quiescent current levels specified in Table 34. Applying V
eliminates the surplus current. The FPGA
does not use any of the surplus current for the power-on process. For this power sequence, make sure that regulators with foldback features
will not shut down inadvertently.
2. To ensure successful power-on, V
with no dips at any point.
, V
Bank 4, and V
supplies must rise through their respective threshold-voltage ranges
CCAUX
CCINT CCO
3. If a brown-out condition occurs where V
or V
drops below the retention voltage indicated in Table 31, then V
or V
CCAUX CCINT
CCAUX
CCINT
must drop below the minimum power-on reset voltage in order to clear out the device configuration content.
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Spartan-3 FPGA Family: DC and Switching Characteristics
Table 30: Power Voltage Ramp Time Requirements
Symbol
TCCO
Description
Device
All
Package
Min
No limit(4)
Max
–
No limit(5)
Units
N/A
VCCO ramp time for all eight banks
All
All
TCCINT
VCCINT ramp time, only if VCCINT is last in
three-rail power-on sequence
All
No limit
N/A
Notes:
1. If a limit exists, this specification is based on characterization.
2. The ramp time is measured from 10% to 90% of the full nominal voltage swing for all I/O standards.
3. For information on power-on current needs, see Power-On Behavior, page 54
4. For mask revisions earlier than revision E (see Mask and Fab Revisions, page 58), T
min is limited to 2.0 ms for the XC3S200 and
CCO
XC3S400 devices in QFP packages, and limited to 0.6 ms for the XC3S200, XC3S400, XC3S1500, and XC3S4000 devices in the FT and
FG packages.
5. For earlier device versions with the FQ fabrication/process code (see Mask and Fab Revisions, page 58), T
max is limited to 500 µs.
CCINT
Table 31: Power Voltage Levels Necessary for Preserving RAM Contents
Symbol
VDRINT
VDRAUX
Description
VCCINT level required to retain RAM data
VCCAUX level required to retain RAM data
Min
1.0
2.0
Units
V
V
Notes:
1. RAM contents include data stored in CMOS configuration latches.
2. The level of the V supply has no effect on data retention.
CCO
3. If a brown-out condition occurs where V
or V
drops below the retention voltage, then V
or V
must drop below the
CCAUX
CCINT
CCAUX
CCINT
minimum power-on reset voltage indicated in Table 29 in order to clear out the device configuration content.
Table 32: General Recommended Operating Conditions
Symbol
Description
Min
0
Nom
Max
85
Units
TJ
Junction temperature
Commercial
Industrial
25
°C
–40
25
100
°C
VCCINT
Internal supply voltage
Output driver supply voltage
Auxiliary supply voltage
1.140
1.140
2.375
–
1.200
1.260
3.465
2.625
10
V
(1)
VCCO
–
V
VCCAUX
2.500
V
(2)
ΔVCCAUX
Voltage variance on VCCAUX when using a DCM
–
–
–
–
–
–
mV/ms
(3)
VIN
Voltage applied to all User I/O pins and
Dual-Purpose pins relative to GND(4)(6)
VCCO = 3.3V, IO
–0.3
–0.3
–0.3
–0.3
–0.3
3.75
3.75
V
V
V
V
V
VCCO = 3.3V, IO_Lxxy(7)
VCCO ≤ 2.5V, IO
VCCO ≤ 2.5V, IO_Lxxy(7)
VCCO + 0.3(4)
VCCO + 0.3(4)
VCCAUX+0.3(5)
Voltage applied to all Dedicated pins relative to GND(5)
Notes:
1. The V
range given here spans the lowest and highest operating voltages of all supported I/O standards. The recommended V
range
CCO
CCO
specific to each of the single-ended I/O standards is given in Table 35, and that specific to the differential standards is given in Table 37.
not exceed 10 mV/ms.
2. Only during DCM operation is it recommended that the rate of change of V
CCAUX
3. Input voltages outside the recommended range are permissible provided that the I input diode clamp diode rating is met. Refer to Table 28.
IK
4. Each of the User I/O and Dual-Purpose pins is associated with one of the V
rails. Meeting the V limit ensures that the internal diode
CCO
IN
junctions that exist between these pins and their associated V
in Table 28.
and GND rails do not turn on. The absolute maximum rating is provided
CCO
5. All Dedicated pins (PROG_B, DONE, TCK, TDI, TDO, and TMS) draw power from the V
rail (2.5V). Meeting the V max limit ensures
IN
CCAUX
that the internal diode junctions that exist between each of these pins and the V
and GND rails do not turn on.
CCAUX
6. See XAPP459, Eliminating I/O Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins on Spartan-3
Generation FPGAs.
7. For single-ended signals that are placed on a differential-capable I/O, V of –0.2V to –0.3V is supported but can cause increased leakage
IN
between the two pins. See the Parasitic Leakage section in UG331, Spartan-3 Generation FPGA User Guide.
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Spartan-3 FPGA Family: DC and Switching Characteristics
Table 33: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins
Symbol
Description
Test Conditions
Min
–
Typ
Max
25
Units
μA
(2)(4)
IL
Leakage current at User I/O,
Dual-Purpose, and Dedicated pins
Driver is Hi-Z, VIN VCCO ≥ 3.0V
=
-
-
0V or VCCO max,
VCCO < 3.0V
sample-tested
–
10
μA
(3)
IRPU
Current through pull-up resistor at User I/O,
Dual-Purpose, and Dedicated pins
VIN = 0V, VCCO = 3.3V
IN = 0V, VCCO = 3.0V
VIN = 0V, VCCO = 2.5V
IN = 0V, VCCO = 1.8V
–0.84
–0.69
–0.47
–0.21
–0.13
–0.06
1.27
-
-
-
-
-
-
-
-
-
-
-
-
–2.35
–1.99
–1.41
–0.69
–0.43
–0.22
4.11
mA
mA
mA
mA
mA
mA
kΩ
V
V
VIN = 0V, VCCO = 1.5V
VIN = 0V, VCCO = 1.2V
VCCO = 3.0V to 3.465V
VCCO = 2.3V to 2.7V
VCCO = 1.7V to 1.9V
(3)
RPU
Equivalent resistance of pull-up resistor at
User I/O, Dual-Purpose, and Dedicated
pins, derived from IRPU
1.15
3.25
kΩ
kΩ
kΩ
2.45
9.10
VCCO = 1.4V to 1.6V
3.25
12.10
21.00
1.67
VCCO = 1.14 to 1.26V
5.15
kΩ
(3)
IRPD
Current through pull-down resistor at User
I/O, Dual-Purpose, and Dedicated pins
VIN = VCCO
0.37
mA
(3)
RPD
Equivalent resistance of pull-down resistor
at User I/O, Dual-Purpose, and Dedicated
pins, driven from IRPD
VIN = VCCO = 3.0V to 3.465V
VIN = VCCO = 2.3V to 2.7V
1.75
1.35
1.00
0.85
0.68
20
-
-
-
-
-
-
-
-
-
9.35
7.30
5.15
4.35
3.465
100
25
kΩ
kΩ
kΩ
kΩ
kΩ
Ω
V
IN = VCCO = 1.7V to 1.9V
IN = VCCO = 1.4V to 1.6V
V
VIN = VCCO = 1.14 to 1.26V
Value of external reference resistor to support DCI I/O standards
RDCI
IREF
VREF current per pin
VCCO ≥ 3.0V
VCCO < 3.0V
–
μA
μA
pF
–
10
CIN
Input capacitance
3
10
Notes:
1. The numbers in this table are based on the conditions set forth in Table 32.
2. The I specification applies to every I/O pin throughout power-on as long as the voltage on that pin stays between the absolute V minimum
L
IN
and maximum values (Table 28). For hot-swap applications, at the time of card connection, be sure to keep all I/O voltages within this range
before applying V power. Consider applying V power before connecting the signal lines, to avoid turning on the ESD protection
CCO
CCO
diodes, shown in Module 2: Figure 7, page 11. When the FPGA is completely unpowered, the I/O pins are high impedance, but there is a
path through the upper and lower ESD protection diodes.
3. This parameter is based on characterization. The pull-up resistance R = V
/ I
. The pull-down resistance R = V / I
.
PU
CCO RPU
PD
IN RPD
Spartan-3 family values for both resistances are stronger than they have been for previous FPGA families.
4. For single-ended signals that are placed on a differential-capable I/O, V of –0.2V to –0.3V is supported but can cause increased leakage
IN
between the two pins. See the Parasitic Leakage section in UG331, Spartan-3 Generation FPGA User Guide.
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Spartan-3 FPGA Family: DC and Switching Characteristics
Table 34: Quiescent Supply Current Characteristics
Commercial
Maximum(1)
Industrial
Symbol
Description
Device
XC3S50
Typical(1)
Units
Maximum(1)
ICCINTQ
Quiescent VCCINT supply current
5
24
54
31
80
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
XC3S50
10
15
110
160
260
360
450
600
2.0
3.0
3.0
4.0
4.0
5.0
5.0
5.0
20
157
262
332
470
810
870
2.5
3.5
3.5
5.0
5.0
6.0
6.0
6.0
22
35
45
60
100
120
1.5
1.5
1.5
2.0
2.5
3.0
3.5
3.5
7
ICCOQ
Quiescent VCCO supply current
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
XC3S50
ICCAUXQ
Quiescent VCCAUX supply current
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
10
30
33
15
40
44
20
50
55
35
75
85
45
90
100
125
145
55
110
130
70
Notes:
1. The numbers in this table are based on the conditions set forth in Table 32. Quiescent supply current is measured with all I/O drivers in a
high-impedance state and with all pull-up/pull-down resistors at the I/O pads disabled. Typical values are characterized using devices with
typical processing at room temperature (T of 25°C at V
= 1.2V, V
= 3.3V, and V
= 2.5V). Maximum values are the
J
CCINT
CCO
CCAUX
production test limits measured for each device at the maximum specified junction temperature and at maximum voltage limits with
= 1.26V, V = 3.465V, and V = 2.625V. The FPGA is programmed with a "blank" configuration data file (i.e., a design with
V
CCINT
CCO
CCAUX
no functional elements instantiated). For conditions other than those described above, (e.g., a design including functional elements, the use
of DCI standards, etc.), measured quiescent current levels may be different than the values in the table. Use the XPower Estimator or
XPower Analyzer for more accurate estimates. See Note 2.
2. There are two recommended ways to estimate the total power consumption (quiescent plus dynamic) for a specific design: a) The Spartan-3
XPower Estimator provides quick, approximate, typical estimates, and does not require a netlist of the design. b) XPower Analyzer, part of
the Xilinx ISE development software, uses the FPGA netlist as input to provide more accurate maximum and typical estimates.
3. The maximum numbers in this table also indicate the minimum current each power rail requires in order for the FPGA to power-on
successfully, once all three rails are supplied. If V
is applied before V
, there may be temporary additional I
current until
CCINT
CCAUX
CCINT
V
is applied. See Surplus I
if V
Applied before V
, page 54
CCAUX
CCINT
CCINT
CCAUX
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Spartan-3 FPGA Family: DC and Switching Characteristics
Table 35: Recommended Operating Conditions for User I/Os Using Single-Ended Standards
VCCO
Nom (V)
–
VREF
Nom (V)
0.8
VIL
VIH
Signal Standard
(IOSTANDARD)
Min (V)
Max (V)
Min (V)
0.74
0.74
0.88
0.88
–
Max (V)
0.86
0.86
1.12
1.12
–
Max (V)
Min (V)
(3)
GTL
–
–
–
–
V
V
– 0.05
V
V
+ 0.05
REF
REF
REF
REF
GTL_DCI
1.2
0.8
– 0.05
– 0.1
– 0.1
– 0.1
– 0.1
– 0.1
– 0.1
– 0.1
+ 0.05
+ 0.1
+ 0.1
+ 0.1
+ 0.1
+ 0.1
+ 0.1
+ 0.1
(3)
GTLP
–
–
–
1
V
V
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
GTLP_DCI
–
1.5
–
1
V
V
HSLVDCI_15
HSLVDCI_18
HSLVDCI_25
HSLVDCI_33
HSTL_I, HSTL_I_DCI
1.4
1.7
2.3
3.0
1.4
1.5
1.6
1.9
2.7
3.465
1.6
0.75
0.9
V
V
V
V
V
V
V
V
V
V
1.8
–
–
2.5
–
1.25
1.65
0.75
–
3.3
–
–
1.5
0.68
0.9
HSTL_III,
1.4
1.7
1.7
1.5
1.8
1.8
1.6
1.9
1.9
–
0.8
–
0.9
0.9
0.9
–
1.1
–
V
V
V
V
– 0.1
– 0.1
– 0.1
– 0.1
V
V
V
V
+ 0.1
+ 0.1
+ 0.1
+ 0.1
REF
REF
REF
REF
REF
REF
REF
REF
HSTL_III_DCI
HSTL_I_18,
HSTL_I_DCI_18
HSTL_II_18,
HSTL_II_DCI_18
HSTL_III_18,
HSTL_III_DCI_18
1.7
1.8
1.2
1.9
1.3
–
–
1.1
–
–
–
LVCMOS12
1.14
0.37V
0.30V
0.58V
0.70V
CCO
CCO
CCO
CCO
LVCMOS15,
LVDCI_15,
LVDCI_DV2_15
1.4
1.7
2.3
3.0
1.5
1.8
2.5
3.3
1.6
1.9
–
–
–
–
–
–
–
–
–
–
–
–
LVCMOS18,
LVDCI_18,
LVDCI_DV2_18
0.30V
0.70V
CCO
CCO
(4,5)
LVCMOS25
LVDCI_25,
LVDCI_DV2_25
,
2.7
0.7
1.7
(4)
LVCMOS33,
LVDCI_33,
LVDCI_DV2_33
3.465
0.8
0.8
2.0
2.0
(4)
LVTTL
3.0
3.0
3.3
3.3
3.465
3.465
–
–
–
–
–
–
(7)
PCI33_3
0.30V
0.50V
CCO
CCO
SSTL18_I,
1.7
1.7
2.3
1.8
1.8
2.5
1.9
1.9
2.7
0.833
0.833
1.15
0.900
0.900
1.25
0.969
0.969
1.35
V
V
– 0.125
– 0.125
– 0.15
V
V
+ 0.125
+ 0.125
+ 0.15
REF
REF
REF
REF
SSTL18_I_DCI
SSTL18_II
SSTL2_I,
SSTL2_I_DCI
V
V
REF
REF
REF
SSTL2_II,
SSTL2_II_DCI
2.3
2.5
2.7
1.15
1.25
1.35
V
– 0.15
V
+ 0.15
REF
Notes:
1. Descriptions of the symbols used in this table are as follows:
VCCO – the supply voltage for output drivers as well as LVCMOS, LVTTL, and PCI inputs
V
V
REF – the reference voltage for setting the input switching threshold
IL – the input voltage that indicates a Low logic level
VIH – the input voltage that indicates a High logic level
2. For device operation, the maximum signal voltage (VIH max) may be as high as VIN max. See Table 28.
3. Because the GTL and GTLP standards employ open-drain output buffers, VCCO lines do not supply current to the I/O circuit, rather this current is
provided using an external pull-up resistor connected from the I/O pin to a termination voltage (VTT). Nevertheless, the voltage applied to the
associated VCCO lines must always be at or above VTT and I/O pad voltages.
4. There is approximately 100 mV of hysteresis on inputs using LVCMOS25 or LVCMOS33 standards.
5. All dedicated pins (M0-M2, CCLK, PROG_B, DONE, HSWAP_EN, TCK, TDI, TDO, and TMS) use the LVCMOS standard and draw power from the
V
CCAUX rail (2.5V). The dual-purpose configuration pins (DIN/D0, D1-D7, CS_B, RDWR_B, BUSY/DOUT, and INIT_B) use the LVCMOS standard
before the user mode. For these pins, apply 2.5V to the VCCO Bank 4 and VCCO Bank 5 rails at power-on and throughout configuration. For information
concerning the use of 3.3V signals, see 3.3V-Tolerant Configuration Interface, page 47.
6. The Global Clock Inputs (GCLK0-GCLK7) are dual-purpose pins to which any signal standard can be assigned.
7. For more information, see XAPP457.
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Spartan-3 FPGA Family: DC and Switching Characteristics
Table 36: DC Characteristics of User I/Os Using Single-Ended Standards
Test Conditions
Logic Level Characteristics
Signal Standard
(IOSTANDARD) and Current
Drive Attribute (mA)
IOL
(mA)
IOH
(mA)
VOL
VOH
Min (V)
Max (V)
GTL
32
–
0.4
0.6
0.4
–
GTL_DCI
Note 3
36
Note 3
–
GTLP
–
GTLP_DCI
Note 3
Note 3
Note 3
Note 3
HSLVDCI_15
HSLVDCI_18
HSLVDCI_25
HSLVDCI_33
HSTL_I
V
– 0.4
CCO
8
–8
Note 3
–8
0.4
0.4
0.4
0.4
0.4
0.4
V
V
V
V
V
V
– 0.4
– 0.4
– 0.4
– 0.4
– 0.4
– 0.4
CCO
CCO
CCO
CCO
CCO
CCO
HSTL_I_DCI
HSTL_III
Note 3
24
HSTL_III_DCI
HSTL_I_18
HSTL_I_DCI_18
HSTL_II_18
HSTL_II_DCI_18
HSTL_III_18
HSTL_III_DCI_18
Note 3
Note 3
–8
8
Note 3
Note 3
–16
Note 3
–8
16
Note 3
24
Note 3
Note 3
–2
(4)
LVCMOS12
2
4
2
4
–4
6
6
–6
(4)
LVCMOS15
2
2
–2
0.4
V
– 0.4
CCO
4
4
6
–4
6
–6
8
8
–8
12
12
–12
Note 3
LVDCI_15,
LVDCI_DV2_15
Note 3
(4)
LVCMOS18
2
4
2
–2
–4
0.4
V
– 0.4
CCO
4
6
6
–6
8
8
–8
12
16
12
–12
–16
Note 3
16
LVDCI_18,
LVDCI_DV2_18
Note 3
(4,5)
LVCMOS25
2
4
2
4
–2
–4
0.4
V
– 0.4
CCO
6
6
–6
8
8
–8
12
16
24
12
16
24
Note 3
–12
–16
–24
Note 3
LVDCI_25,
LVDCI_DV2_25
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Spartan-3 FPGA Family: DC and Switching Characteristics
Table 36: DC Characteristics of User I/Os Using Single-Ended Standards (Cont’d)
Test Conditions
Logic Level Characteristics
Signal Standard
(IOSTANDARD) and Current
Drive Attribute (mA)
IOL
(mA)
IOH
(mA)
VOL
VOH
Min (V)
Max (V)
(4)
LVCMOS33
2
4
–2
–4
0.4
V
– 0.4
2
4
CCO
6
–6
6
8
–8
8
12
16
24
Note 3
–12
–16
–24
Note 3
12
16
24
LVDCI_33,
LVDCI_DV2_33
(4)
LVTTL
2
4
–2
–4
0.4
2.4
2
4
6
–6
6
8
–8
8
12
–12
12
16
24
16
–16
24
–24
PCI33_3
Note 6
6.7
Note 6
–6.7
Note 3
–13.4
–8.1
Note 3
–16.2
Note 3
0.10V
0.90V
CCO
CCO
SSTL18_I
V
– 0.475
V
+ 0.475
TT
TT
SSTL18_I_DCI
SSTL18_II
SSTL2_I
Note 3
13.4
8.1
V
– 0.475
– 0.61
V
+ 0.475
+ 0.61
TT
TT
V
V
TT
TT
SSTL2_I_DCI
Note 3
16.2
Note 3
(7)
SSTL2_II
V
– 0.81
V
+ 0.81
TT
TT
(7)
SSTL2_II_DCI
Notes:
1. The numbers in this table are based on the conditions set forth in Table 32 and Table 35.
2. Descriptions of the symbols used in this table are as follows:
I
OL – the output current condition under which VOL is tested
IOH – the output current condition under which VOH is tested
VOL – the output voltage that indicates a Low logic level
V
OH – the output voltage that indicates a High logic level
VIL – the input voltage that indicates a Low logic level
VIH – the input voltage that indicates a High logic level
V
V
CCO – the supply voltage for output drivers as well as LVCMOS, LVTTL, and PCI inputs
REF – the reference voltage for setting the input switching threshold
VTT – the voltage applied to a resistor termination
3. Tested according to the standard’s relevant specifications. When using the DCI version of a standard on a given I/O bank, that bank will consume
more power than if the non-DCI version had been used instead. The additional power is drawn for the purpose of impedance-matching at the I/O pins.
A portion of this power is dissipated in the two RREF resistors.
4. For the LVCMOS and LVTTL standards: the same VOL and VOH limits apply for both the Fast and Slow slew attributes.
5. All dedicated output pins (CCLK, DONE, and TDO) and dual-purpose totem-pole output pins (D0-D7 and BUSY/DOUT) exhibit the characteristics of
LVCMOS25 with 12 mA drive and slow slew rate. For information concerning the use of 3.3V signals, see 3.3V-Tolerant Configuration Interface,
page 47.
6. Tested according to the relevant PCI specifications. For more information, see XAPP457.
7. The minimum usable VTT voltage is 1.25V.
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65
Spartan-3 FPGA Family: DC and Switching Characteristics
X-Ref Target - Figure 32
VINP
Differential
I/O Pair Pins
P
N
Internal
Logic
VINN
VINN
VID
50%
VINP
VICM
GND level
VINP + VINN
V
ICM = Input common mode voltage =
2
V
VINP - VINN
ID = Differential input voltage =
DS099-3_01_012304
Figure 32: Differential Input Voltages
Table 37: Recommended Operating Conditions for User I/Os Using Differential Signal Standards
(1)
(3)
VCCO
VID
VICM
Signal Standard
(IOSTANDARD)
Min (V) Nom (V) Max (V) Min (mV) Nom (mV) Max (mV) Min (V) Nom (V) Max (V)
LDT_25 (ULVDS_25)
LVDS_25, LVDS_25_DCI
BLVDS_25
2.375
2.375
2.375
2.375
2.50
2.50
2.50
2.50
2.625
2.625
2.625
2.625
200
100
-
600
350
350
540
1000
600
-
0.44
0.30
-
0.60
1.25
1.25
1.20
0.78
2.20
-
LVDSEXT_25,
100
1000
0.30
2.20
LVDSEXT_25_DCI
LVPECL_25
RSDS_25
2.375
2.375
1.70
2.50
2.50
1.80
2.625
2.625
1.90
100
100
200
-
200
-
-
-
-
0.30
-
1.20
1.20
-
2.00
-
DIFF_HSTL_II_18,
0.80
1.00
DIFF_HSTL_II_18_DCI
DIFF_SSTL2_II,
2.375
2.50
2.625
300
-
-
1.05
-
1.45
DIFF_SSTL2_II_DCI
Notes:
1.
2.
3.
V
V
V
only supplies differential output drivers, not input circuits.
inputs are not used for any of the differential I/O standards.
is a differential measurement.
CCO
REF
ID
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Spartan-3 FPGA Family: DC and Switching Characteristics
X-Ref Target - Figure 33
VOUTP
Differential
I/O Pair Pins
P
N
Internal
Logic
VOUTN
VOH
VOUTN
VOD
50%
VOUTP
VOL
VOCM
GND level
VOUTP + VOUTN
V
OCM = Output common mode voltage =
2
VOUTP - VOUTN
= Output voltage indicating a High logic level
= Output voltage indicating a Low logic level
V
OD = Output differential voltage =
VOH
VOL
DS099-3_02_091710
Figure 33: Differential Output Voltages
Table 38: DC Characteristics of User I/Os Using Differential Signal Standards
Mask(3)
VOD
VOCM
VOH
Min (V)
0.71
VOL
Max (V)
0.50
Signal Standard
Revision
Min (mV) Typ (mV) Max (mV) Min (V) Typ (V) Max (V)
LDT_25 (ULVDS_25)
LVDS_25
All
All
‘E’
All
All
‘E’
All
All
‘E’
All
All
430(4)
100
200
250
100
300
–
600
–
670
600
500
450
600
700
-
0.495
0.80
1.0
–
0.600
0.715
1.6
1.5
–
–
–
0.85
1.55
–
1.10
1.40
BLVDS_25(5)
LVDSEXT_25
350
–
1.20
–
–
–
0.80
1.0
–
1.6
1.5
-
0.85
1.55
–
–
1.15
1.35
LVPECL_25(5)
RSDS_25(6)
–
–
1.35
1.005
1.55
100
200
–
–
600
500
–
0.80
1.0
–
–
1.6
1.5
–
0.85
–
–
1.10
1.40
DIFF_HSTL_II_18
DIFF_SSTL2_II
–
–
VCCO – 0.40
VTT + 0.80
0.40
–
–
–
–
–
–
VTT – 0.80
Notes:
1. The numbers in this table are based on the conditions set forth in Table 32 and Table 37.
2. Output voltage measurements for all differential standards are made with a termination resistor (R ) of 100Ω across the N and P pins of the
T
differential signal pair.
3. Mask revision E devices have tighter output ranges but can be used in any design that was in a previous revision. See Mask and Fab
Revisions, page 58.
4. This value must be compatible with the receiver to which the FPGA’s output pair is connected.
5. Each LVPECL_25 or BLVDS_25 output-pair requires three external resistors for proper output operation as shown in Figure 34. Each
LVPECL_25 or BLVDS_25 input-pair uses a 100W termination resistor at the receiver.
6. Only one of the differential standards RSDS_25, LDT_25, LVDS_25, and LVDSEXT_25 may be used for outputs within a bank.
Each differential standard input-pair requires an external 100Ω termination resistor.
X-Ref Target - Figure 34
BLVDS
LVPECL 70Ω
BLVDS
LVPECL
165Ω
Z0=50Ω
140Ω
Z0=50Ω
Z0=50Ω
240Ω
Z0=50Ω
100Ω
100Ω
165Ω
70Ω
ds099-3_08_112105
Figure 34: External Termination Required for LVPECL and BLVDS Output and Input
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67
Spartan-3 FPGA Family: DC and Switching Characteristics
Switching Characteristics
All Spartan-3 devices are available in two speed grades: –4 and the higher performance –5. Switching characteristics in this
document may be designated as Advance, Preliminary, or Production. Each category is defined as follows:
Advance: These specifications are based on simulations only and are typically available soon after establishing FPGA
specifications. Although speed grades with this designation are considered relatively stable and conservative, some
under-reported delays may still occur.
Preliminary: These specifications are based on complete early silicon characterization. Devices and speed grades with this
designation are intended to give a better indication of the expected performance of production silicon. The probability of
under-reporting preliminary delays is greatly reduced compared to Advance data.
Production: These specifications are approved once enough production silicon of a particular device family member has
been characterized to provide full correlation between speed files and devices over numerous production lots. There is no
under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest
speed grades transition to Production before faster speed grades.
Production-quality systems must use FPGA designs compiled using a Production status speed file. FPGAs designs using a
less mature speed file designation may only be used during system prototyping or preproduction qualification. FPGA
designs using Advance or Preliminary status speed files should never be used in a production-quality system.
Whenever a speed file designation changes, as a device matures toward Production status, rerun the Xilinx ISE software on
the FPGA design to ensure that the FPGA design incorporates the latest timing information and software updates.
Xilinx ISE Software Updates: http://www.xilinx.com/support/download/index.htm
All specified limits are representative of worst-case supply voltage and junction temperature conditions. Unless otherwise
noted, the following applies: Parameter values apply to all Spartan-3 devices. All parameters representing voltages are
measured with respect to GND.
Selected timing parameters and their representative values are included below either because they are important as general
design requirements or they indicate fundamental device performance characteristics. The Spartan-3 FPGA v1.38 speed
files are the original source for many but not all of the values. The v1.38 speed files are available in Xilinx Integrated Software
Environment (ISE) software version 8.2i.
The speed grade designations for these files are shown in Table 39. For more complete, more precise, and worst-case data,
use the values reported by the Xilinx static timing analyzer (TRACE in the Xilinx development software) and back-annotated
to the simulation netlist.
Table 39: Spartan-3 FPGA Speed Grade Designations (ISE v8.2i or Later)
Device
XC3S50
Advance
Preliminary
Production
-4, -5 (v1.37 and later)
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
-4, -5 (v1.38 and later)
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Spartan-3 FPGA Family: DC and Switching Characteristics
I/O Timing
Table 40: Pin-to-Pin Clock-to-Output Times for the IOB Output Path
Speed Grade
Symbol
Description
Conditions
Device
-5
-4
Units
Max(2)
Max(2)
Clock-to-Output Times
TICKOFDCM
When reading from the Output
LVCMOS25(3), 12 mA
output drive, Fast slew rate,
XC3S50
2.04
1.45
1.45
2.07
2.05
2.03
1.94
2.00
3.70
3.89
3.91
4.00
4.07
4.19
4.44
4.38
2.35
1.75
1.75
2.39
2.36
2.34
2.24
2.30
4.24
4.46
4.48
4.59
4.66
4.80
5.09
5.02
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Flip-Flop (OFF), the time from the
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
XC3S50
active transition on the Global Clock pin with DCM(4)
to data appearing at the Output pin.
The DCM is in use.
TICKOF
When reading from OFF, the time from LVCMOS25(3), 12 mA
the active transition on the Global Clock output drive, Fast slew rate,
pin to data appearing at the Output pin. without DCM
The DCM is not in use.
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
Notes:
1. The numbers in this table are tested using the methodology presented in Table 48 and are based on the operating conditions set forth in
Table 32 and Table 35.
2. For minimums, use the values reported by the Xilinx timing analyzer.
3. This clock-to-output time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or a
standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. If the former is true, add the appropriate
Input adjustment from Table 44. If the latter is true, add the appropriate Output adjustment from Table 47.
4. DCM output jitter is included in all measurements.
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Spartan-3 FPGA Family: DC and Switching Characteristics
Table 41: System-Synchronous Pin-to-Pin Setup and Hold Times for the IOB Input Path
Speed Grade
Symbol
Description
Conditions
Device
-5
-4
Units
Min
Min
Setup Times
TPSDCM
When writing to the Input
Flip-Flop (IFF), the time from the IOBDELAY = NONE,
setup of data at the Input pin to
the active transition at a Global
Clock pin. The DCM is in use. No
Input Delay is programmed.
LVCMOS25(2)
,
XC3S50
2.37
2.13
2.15
2.58
2.55
2.59
2.76
2.69
3.00
2.63
2.50
3.50
3.78
4.98
5.25
5.37
2.71
2.35
2.36
2.95
2.91
2.96
3.15
3.08
3.46
3.02
2.87
4.03
4.35
5.73
6.05
6.18
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
XC3S50
with DCM(4)
TPSFD
When writing to IFF, the time from LVCMOS25(2)
the setup of data at the Input pin IOBDELAY = IFD,
to an active transition at the
Global Clock pin. The DCM is not
in use. The Input Delay is
programmed.
,
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
without DCM
Hold Times
TPHDCM
When writing to IFF, the time from LVCMOS25(3)
the active transition at the Global IOBDELAY = NONE,
Clock pin to the point when data with DCM(4)
must be held at the Input pin. The
DCM is in use. No Input Delay is
programmed.
,
XC3S50
–0.45
–0.12
–0.12
–0.43
–0.45
–0.47
–0.61
–0.62
–0.40
–0.05
–0.05
–0.38
–0.40
–0.42
–0.56
–0.57
ns
ns
ns
ns
ns
ns
ns
ns
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
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Spartan-3 FPGA Family: DC and Switching Characteristics
Table 41: System-Synchronous Pin-to-Pin Setup and Hold Times for the IOB Input Path (Cont’d)
Speed Grade
Symbol
Description
Conditions
Device
-5
-4
Units
Min
Min
TPHFD
When writing to IFF, the time from LVCMOS25(3)
the active transition at the Global IOBDELAY = IFD,
Clock pin to the point when data without DCM
must be held at the Input pin. The
DCM is not in use. The Input
Delay is programmed.
,
XC3S50
–0.98
–0.40
–0.27
–1.19
–1.43
–2.33
–2.47
–2.66
–0.93
–0.35
–0.22
–1.14
–1.38
–2.28
–2.42
–2.61
ns
ns
ns
ns
ns
ns
ns
ns
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
Notes:
1. The numbers in this table are tested using the methodology presented in Table 48 and are based on the operating conditions set forth in
Table 32 and Table 35.
2. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from Table 44. If this is true of the data Input, add the
appropriate Input adjustment from the same table.
3. This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from Table 44. If this is true of the data Input, subtract the
appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
4. DCM output jitter is included in all measurements.
Table 42: Setup and Hold Times for the IOB Input Path
Speed Grade
Symbol
Description
Conditions
Device
-5
-4
Units
Min
Min
Setup Times
(2)
T
Time from the setup of data at the Input pin LVCMOS25
,
XC3S50
1.65
1.37
1.37
1.65
1.65
1.65
1.73
1.82
4.39
4.76
4.63
5.02
5.40
6.68
7.16
7.33
1.89
1.57
1.57
1.89
1.89
1.89
1.99
2.09
5.04
5.47
5.32
5.76
6.20
7.68
8.24
8.42
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IOPICK
to the active transition at the ICLK input of IOBDELAY = NONE
the Input Flip-Flop (IFF). No Input Delay is
programmed.
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
XC3S50
(2)
T
Time from the setup of data at the Input pin LVCMOS25
to the active transition at the IFF’s ICLK
input. The Input Delay is programmed.
,
IOPICKD
IOBDELAY = IFD
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
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Spartan-3 FPGA Family: DC and Switching Characteristics
Table 42: Setup and Hold Times for the IOB Input Path (Cont’d)
Speed Grade
Symbol
Description
Conditions
Device
-5
-4
Units
Min
Min
Hold Times
(3)
T
Time from the active transition at the IFF’s LVCMOS25
,
XC3S50
-0.55
-0.29
-0.29
-0.55
-0.55
-0.55
-0.61
-0.68
-2.74
-3.00
-2.90
-3.24
-3.55
-4.57
-4.96
-5.09
-0.55
-0.29
-0.29
-0.55
-0.55
-0.55
-0.61
-0.68
-2.74
-3.00
-2.90
-3.24
-3.55
-4.57
-4.96
-5.09
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IOICKP
ICLK input to the point where data must be IOBDELAY = NONE
held at the Input pin. No Input Delay is
programmed.
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
XC3S50
(3)
T
Time from the active transition at the IFF’s LVCMOS25
,
IOICKPD
ICLK input to the point where data must be IOBDELAY = IFD
held at the Input pin. The Input Delay is
programmed.
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
Set/Reset Pulse Width
T
Minimum pulse width to SR control input
on IOB
All
0.66
0.76
ns
RPW_IOB
Notes:
1. The numbers in this table are tested using the methodology presented in Table 48 and are based on the operating conditions set forth in
Table 32 and Table 35.
2. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the
appropriate Input adjustment from Table 44.
3. These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract
the appropriate Input adjustment from Table 44. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
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Spartan-3 FPGA Family: DC and Switching Characteristics
Speed Grade
Table 43: Propagation Times for the IOB Input Path
Symbol
Description
Conditions
Device
-5
-4
Units
Max
Max
Propagation Times
TIOPLI
The time it takes for data to travel LVCMOS25(2)
,
XC3S50
2.01
1.50
1.50
2.01
2.01
2.01
2.09
2.18
4.75
4.89
4.76
5.38
5.76
7.04
7.52
7.69
2.31
1.72
1.72
2.31
2.31
2.31
2.41
2.51
5.46
5.62
5.48
6.18
6.62
8.09
8.65
8.84
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
from the Input pin through the
IFF latch to the I output with no
input delay programmed
IOBDELAY = NONE
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
XC3S50
TIOPLID
The time it takes for data to travel LVCMOS25(2)
,
from the Input pin through the
IFF latch to the I output with the
input delay programmed
IOBDELAY = IFD
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
Notes:
1. The numbers in this table are tested using the methodology presented in Table 48 and are based on the operating conditions set forth in
Table 32 and Table 35.
2. This propagation time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. When this is
true, add the appropriate Input adjustment from Table 44.
Table 44: Input Timing Adjustments for IOB
Add the Adjustment Below
Convert Input Time from LVCMOS25 to the
Following Signal Standard (IOSTANDARD)
Speed Grade
Units
-5
-4
Single-Ended Standards
GTL, GTL_DCI
0.44
0.36
0.51
0.29
0.51
0.51
0.51
0.37
0.36
0.39
0.45
0.63
0.50
0.42
0.59
0.33
0.59
0.59
0.59
0.42
0.41
0.45
0.52
0.72
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GTLP, GTLP_DCI
HSLVDCI_15
HSLVDCI_18
HSLVDCI_25
HSLVDCI_33
HSTL_I, HSTL_I_DCI
HSTL_III, HSTL_III_DCI
HSTL_I_18, HSTL_I_DCI_18
HSTL_II_18, HSTL_II_DCI_18
HSTL_III_18, HSTL_III_DCI_18
LVCMOS12
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73
Spartan-3 FPGA Family: DC and Switching Characteristics
Table 44: Input Timing Adjustments for IOB (Cont’d)
Add the Adjustment Below
Speed Grade
-5
Convert Input Time from LVCMOS25 to the
Following Signal Standard (IOSTANDARD)
Units
-4
0.49
0.43
0.44
0.28
0.33
0.33
0
LVCMOS15
0.42
0.38
0.38
0.24
0.29
0.28
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVDCI_15
LVDCI_DV2_15
LVCMOS18
LVDCI_18
LVDCI_DV2_18
LVCMOS25
LVDCI_25
0.05
0.04
–0.05
0.18
0.20
0.39
0.39
0.40
0.36
0.05
0.04
–0.02
0.21
0.22
0.45
0.45
0.46
0.41
LVDCI_DV2_25
LVCMOS33, LVDCI_33, LVDCI_DV2_33
LVTTL
PCI33_3
SSTL18_I, SSTL18_I_DCI
SSTL18_II
SSTL2_I, SSTL2_I_DCI
SSTL2_II, SSTL2_II_DCI
Differential Standards
LDT_25 (ULVDS_25)
LVDS_25, LVDS_25_DCI
BLVDS_25
0.76
0.65
0.34
0.80
0.18
0.43
0.34
0.65
0.88
0.75
0.39
0.92
0.21
0.50
0.39
0.75
ns
ns
ns
ns
ns
ns
ns
ns
LVDSEXT_25, LVDSEXT_25_DCI
LVPECL_25
RSDS_25
DIFF_HSTL_II_18, DIFF_HSTL_II_18_DCI
DIFF_SSTL2_II, DIFF_SSTL2_II_DCI
Notes:
1. The numbers in this table are tested using the methodology presented in Table 48 and are based on
the operating conditions set forth in Table 32, Table 35, and Table 37.
2. These adjustments are used to convert input path times originally specified for the LVCMOS25
standard to times that correspond to other signal standards.
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74
Spartan-3 FPGA Family: DC and Switching Characteristics
Speed Grade
Table 45: Timing for the IOB Output Path
Symbol
Description
Conditions
Device
-5
-4
Units
Max(3)
Max(3)
Clock-to-Output Times
TIOCKP
When reading from the Output
LVCMOS25(2), 12 mA output
drive, Fast slew rate
XC3S200
XC3S400
1.28
1.95
1.47
2.24
ns
ns
Flip-Flop (OFF), the time from the
active transition at the OTCLK input to
data appearing at the Output pin
XC3S50
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
Propagation Times
TIOOP
The time it takes for data to travel from LVCMOS25(2), 12 mA output
XC3S200
XC3S400
1.28
1.94
1.46
2.23
ns
ns
the IOB’s O input to the Output pin
drive, Fast slew rate
XC3S50
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
TIOOLP
The time it takes for data to travel from
the O input through the OFF latch to
the Output pin
XC3S200
XC3S400
1.28
1.95
1.47
2.24
ns
ns
XC3S50
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
Set/Reset Times
TIOSRP
Time from asserting the OFF’s SR
input to setting/resetting data at the
Output pin
LVCMOS25(2), 12 mA output
drive, Fast slew rate
XC3S200
XC3S400
2.10
2.77
2.41
3.18
ns
ns
XC3S50
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
TIOGSRQ
Time from asserting the Global Set
Reset (GSR) net to setting/resetting
data at the Output pin
All
8.07
9.28
ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 48 and are based on the operating conditions set forth in
Table 32 and Table 35.
2. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data
Output. When this is true, add the appropriate Output adjustment from Table 47.
3. For minimums, use the values reported by the Xilinx timing analyzer.
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75
Spartan-3 FPGA Family: DC and Switching Characteristics
Speed Grade
Table 46: Timing for the IOB Three-State Path
Symbol
Description
Conditions
Device
-5
-4
Units
Max(3)
Max(3)
Synchronous Output Enable/Disable Times
TIOCKHZ
Time from the active transition at the
OTCLK input of the Three-state Flip-Flop
(TFF) to when the Output pin enters the
high-impedance state
LVCMOS25, 12 mA
output drive, Fast slew
rate
All
All
0.74
0.72
0.85
0.82
ns
ns
(2)
TIOCKON
Time from the active transition at TFF’s
OTCLK input to when the Output pin drives
valid data
Asynchronous Output Enable/Disable Times
TGTS
Time from asserting the Global Three State LVCMOS25, 12 mA
(GTS) net to when the Output pin enters the output drive, Fast slew
XC3S200
XC3S400
7.71
8.38
8.87
9.63
ns
ns
high-impedance state
rate
XC3S50
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
Set/Reset Times
TIOSRHZ
Time from asserting TFF’s SR input to when LVCMOS25, 12 mA
All
1.55
1.78
ns
the Output pin enters a high-impedance
state
output drive, Fast slew
rate
(2)
TIOSRON
Time from asserting TFF’s SR input at TFF
to when the Output pin drives valid data
XC3S200
XC3S400
2.24
2.91
2.57
3.34
ns
ns
XC3S50
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
Notes:
1. The numbers in this table are tested using the methodology presented in Table 48 and are based on the operating conditions set forth in
Table 32 and Table 35.
2. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data
Output. When this is true, add the appropriate Output adjustment from Table 47.
3. For minimums, use the values reported by the Xilinx timing analyzer.
Table 47: Output Timing Adjustments for IOB
Add the Adjustment Below
Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the
Speed Grade
Units
Following Signal Standard (IOSTANDARD)
-5
-4
Single-Ended Standards
GTL
0
0.02
0.15
0.04
0.27
1.74
0.94
ns
ns
ns
ns
ns
ns
GTL_DCI
GTLP
0.13
0.03
0.23
1.51
0.81
GTLP_DCI
HSLVDCI_15
HSLVDCI_18
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Spartan-3 FPGA Family: DC and Switching Characteristics
Add the Adjustment Below
Table 47: Output Timing Adjustments for IOB (Cont’d)
Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the
Speed Grade
Units
Following Signal Standard (IOSTANDARD)
-5
-4
HSLVDCI_25
HSLVDCI_33
HSTL_I
0.27
0.28
0.60
0.59
0.19
0.20
0.18
0.17
–0.02
0.75
0.28
0.28
7.60
7.42
6.67
3.16
2.70
2.41
4.55
3.76
3.57
3.55
3.00
3.11
1.71
1.44
1.26
1.11
1.51
1.32
0.31
0.32
0.69
0.68
0.22
0.23
0.21
0.19
–0.01
0.86
0.32
0.32
8.73
8.53
7.67
3.63
3.10
2.77
5.23
4.32
4.11
4.09
3.45
3.57
1.96
1.66
1.44
1.27
1.74
1.52
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
HSTL_I_DCI
HSTL_III
HSTL_III_DCI
HSTL_I_18
HSTL_I_DCI_18
HSTL_II_18
HSTL_II_DCI_18
HSTL_III_18
HSTL_III_DCI_18
LVCMOS12
Slow
Fast
Slow
2 mA
4 mA
6 mA
2 mA
4 mA
6 mA
2 mA
4 mA
6 mA
8 mA
12 mA
2 mA
4 mA
6 mA
8 mA
12 mA
LVCMOS15
Fast
LVDCI_15
LVDCI_DV2_15
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Spartan-3 FPGA Family: DC and Switching Characteristics
Add the Adjustment Below
Table 47: Output Timing Adjustments for IOB (Cont’d)
Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the
Speed Grade
Units
Following Signal Standard (IOSTANDARD)
-5
-4
LVCMOS18
Slow
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
5.49
3.45
2.84
2.62
2.11
2.07
2.50
1.15
0.96
0.87
0.79
0.76
0.81
0.67
6.43
4.15
3.38
2.99
2.53
2.50
2.22
3.27
1.87
0.32
0.19
0
6.31
3.97
3.26
3.01
2.43
2.38
2.88
1.32
1.10
1.01
0.91
0.87
0.94
0.77
7.39
4.77
3.89
3.44
2.91
2.87
2.55
3.76
2.15
0.37
0.22
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Fast
LVDCI_18
LVDCI_DV2_18
LVCMOS25
Slow
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
2 mA
Fast
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
–0.02
–0.04
0.27
0.16
–0.01
–0.02
0.31
0.19
LVDCI_25
LVDCI_DV2_25
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Spartan-3 FPGA Family: DC and Switching Characteristics
Add the Adjustment Below
Table 47: Output Timing Adjustments for IOB (Cont’d)
Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the
Speed Grade
Units
Following Signal Standard (IOSTANDARD)
-5
-4
LVCMOS33
Slow
2 mA
4 mA
6.38
4.83
4.01
3.92
2.91
2.81
2.49
3.86
1.87
0.62
0.61
0.16
0.14
0.06
0.28
0.26
7.27
4.94
3.98
3.98
2.97
2.84
2.65
4.32
1.87
1.27
1.19
0.42
0.27
0.16
7.34
5.55
4.61
4.51
3.35
3.23
2.86
4.44
2.15
0.71
0.70
0.19
0.16
0.07
0.32
0.30
8.36
5.69
4.58
4.58
3.42
3.26
3.04
4.97
2.15
1.47
1.37
0.48
0.32
0.18
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6 mA
8 mA
12 mA
16 mA
24 mA
2 mA
Fast
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
LVDCI_33
LVDCI_DV2_33
LVTTL
Slow
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
2 mA
Fast
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
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Spartan-3 FPGA Family: DC and Switching Characteristics
Add the Adjustment Below
Table 47: Output Timing Adjustments for IOB (Cont’d)
Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the
Speed Grade
Units
Following Signal Standard (IOSTANDARD)
-5
-4
PCI33_3
0.74
0.07
0.22
0.30
0.23
0.19
0.13
0.10
0.85
0.07
0.25
0.34
0.26
0.22
0.15
0.11
ns
ns
ns
ns
ns
ns
ns
ns
SSTL18_I
SSTL18_I_DCI
SSTL18_II
SSTL2_I
SSTL2_I_DCI
SSTL2_II
SSTL2_II_DCI
Differential Standards
LDT_25 (ULVDS_25)
LVDS_25
–0.06
–0.09
0.02
–0.05
–0.07
0.04
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
BLVDS_25
LVDSEXT_25
LVPECL_25
–0.15
0.16
–0.13
0.18
RSDS_25
0.05
0.06
DIFF_HSTL_II_18
DIFF_HSTL_II_18_DCI
DIFF_SSTL2_II
DIFF_SSTL2_II_DCI
–0.02
0.75
–0.01
0.86
0.13
0.15
0.10
0.11
Notes:
1. The numbers in this table are tested using the methodology presented in Table 48 and are based on the operating conditions set forth
in Table 32, Table 35, and Table 37.
2. These adjustments are used to convert output- and three-state-path times originally specified for the LVCMOS25 standard with
12 mA drive and Fast slew rate to times that correspond to other signal standards. Do not adjust times that measure when outputs
go into a high-impedance state.
3. For minimums, use the values reported by the Xilinx timing analyzer.
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80
Spartan-3 FPGA Family: DC and Switching Characteristics
Timing Measurement Methodology
When measuring timing parameters at the programmable I/Os, different signal standards call for different test conditions.
Table 48 presents the conditions to use for each standard.
The method for measuring Input timing is as follows: A signal that swings between a Low logic level of VL and a High logic
level of VH is applied to the Input under test. Some standards also require the application of a bias voltage to the V
pins
REF
of a given bank to properly set the input-switching threshold. The measurement point of the Input signal (VM) is commonly
located halfway between VL and VH.
The Output test setup is shown in Figure 35. A termination voltage VT is applied to the termination resistor RT, the other end
of which is connected to the Output. For each standard, RT and VT generally take on the standard values recommended for
minimizing signal reflections. If the standard does not ordinarily use terminations (e.g., LVCMOS, LVTTL), then RT is set to
1MΩ to indicate an open connection, and VT is set to zero. The same measurement point (VM) that was used at the Input is
also used at the Output.
X-Ref Target - Figure 35
V (V
)
REF
T
FPGA Output
R (R
T
)
REF
V
(V
)
M
MEAS
)
C (C
L
REF
ds099-3_07_012004
Notes:
1. The names shown in parentheses are
used in the IBIS file.
Figure 35: Output Test Setup
Table 48: Test Methods for Timing Measurement at I/Os
Inputs and
Outputs
Inputs
VL (V)
Outputs
Signal Standard
(IOSTANDARD)
VREF (V)
0.8
VH (V)
RT (Ω)
VT (V)
VM (V)
VREF
VREF
Single-Ended
GTL
VREF – 0.2
VREF – 0.2
VREF + 0.2
VREF + 0.2
VREF + 0.5
25
50
25
50
1M
1.2
1.2
1.5
1.5
0
GTL_DCI
GTLP
1.0
GTLP_DCI
HSLVDCI_15
HSLVDCI_18
HSLVDCI_25
HSLVDCI_33
HSTL_I
0.9
V
REF – 0.5
0.75
0.90
1.25
1.65
VREF
0.75
0.90
0.90
0.90
V
V
V
REF – 0.5
REF – 0.5
REF – 0.5
VREF + 0.5
VREF + 0.5
VREF + 0.5
VREF + 0.5
50
50
50
50
0.75
1.5
0.9
0.9
HSTL_I_DCI
HSTL_III
VREF
VREF
VREF
HSTL_III_DCI
HSTL_I_18
HSTL_I_DCI_18
HSTL_II_18
HSTL_II_DCI_18
VREF – 0.5
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81
Spartan-3 FPGA Family: DC and Switching Characteristics
Table 48: Test Methods for Timing Measurement at I/Os (Cont’d)
Inputs and
Outputs
Inputs
Outputs
Signal Standard
(IOSTANDARD)
VREF (V)
VL (V)
VH (V)
RT (Ω)
VT (V)
VM (V)
HSTL_III_18
1.1
VREF – 0.5
VREF + 0.5
50
1.8
VREF
HSTL_III_DCI_18
LVCMOS12
LVCMOS15
LVDCI_15
-
-
0
0
1.2
1.5
1M
1M
0
0
0.6
0.75
LVDCI_DV2_15
HSLVDCI_15
LVCMOS18
LVDCI_18
-
-
-
0
0
0
1.8
2.5
3.3
1M
1M
1M
0
0
0
0.9
LVDCI_DV2_18
HSLVDCI_18
LVCMOS25
LVDCI_25
1.25
1.65
LVDCI_DV2_25
HSLVDCI_25
LVCMOS33
LVDCI_33
LVDCI_DV2_33
HSLVDCI_33
LVTTL
-
-
0
3.3
1M
25
25
50
0
1.4
0.94
2.03
VREF
PCI33_3
Rising
Falling
Note 3
Note 3
0
3.3
0.9
SSTL18_I
0.9
V
REF – 0.5
REF – 0.5
VREF + 0.5
SSTL18_I_DCI
SSTL18_II
0.9
V
VREF + 0.5
50
50
0.9
VREF
VREF
SSTL2_I
1.25
VREF – 0.75
VREF + 0.75
1.25
SSTL2_I_DCI
SSTL2_II
1.25
V
REF – 0.75
VREF + 0.75
25
50
1.25
1.25
VREF
SSTL2_II_DCI
Differential
LDT_25 (ULVDS_25)
LVDS_25
-
-
VICM – 0.125
VICM – 0.125
VICM + 0.125
VICM + 0.125
60
50
0.6
1.2
N/A
0
VICM
VICM
LVDS_25_DCI
BLVDS_25
N/A
1M
50
-
-
V
ICM – 0.125
VICM + 0.125
VICM + 0.125
VICM
VICM
LVDSEXT_25
VICM – 0.125
1.2
N/A
0
LVDSEXT_25_DCI
LVPECL_25
N/A
1M
50
-
-
-
V
ICM – 0.3
VICM + 0.3
VICM + 0.1
VICM + 0.5
VICM
VICM
VICM
RSDS_25
VICM – 0.1
VICM – 0.5
1.2
1.8
DIFF_HSTL_II_18
DIFF_HSTL_II_18_DCI
50
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82
Spartan-3 FPGA Family: DC and Switching Characteristics
Table 48: Test Methods for Timing Measurement at I/Os (Cont’d)
Inputs and
Outputs
Inputs
Outputs
Signal Standard
(IOSTANDARD)
VREF (V)
VL (V)
VH (V)
RT (Ω)
VT (V)
VM (V)
DIFF_SSTL2_II
-
VICM – 0.75
VICM + 0.75
50
1.25
VICM
DIFF_SSTL2_II_DCI
Notes:
1. Descriptions of the relevant symbols are as follows:
VREF – The reference voltage for setting the input switching threshold
VICM – The common mode input voltage
VM – Voltage of measurement point on signal transition
VL – Low-level test voltage at Input pin
VH – High-level test voltage at Input pin
RT – Effective termination resistance, which takes on a value of 1MW when no parallel termination is required
VT – Termination voltage
2. The load capacitance (CL) at the Output pin is 0 pF for all signal standards.
3. According to the PCI specification.
The capacitive load (CL) is connected between the output and GND. The Output timing for all standards, as published in the speed files
and the data sheet, is always based on a C value of zero. High-impedance probes (less than 1 pF) are used for all measurements.
L
Any delay that the test fixture might contribute to test measurements is subtracted from those measurements to produce the
final timing numbers as published in the speed files and data sheet.
Using IBIS Models to Simulate Load Conditions in Application
IBIS Models permit the most accurate prediction of timing delays for a given application. The parameters found in the IBIS
model (VREF, RREF, and VMEAS) correspond directly with the parameters used in Table 48, VT, RT, and VM. Do not confuse
V
REF (the termination voltage) from the IBIS model with VREF (the input-switching threshold) from the table. A fourth
parameter, CREF, is always zero. The four parameters describe all relevant output test conditions. IBIS models are found in
the Xilinx development software as well as at the following link.
http://www.xilinx.com/support/download/index.htm
Simulate delays for a given application according to its specific load conditions as follows:
1. Simulate the desired signal standard with the output driver connected to the test setup shown in Figure 35. Use
parameter values VT, RT, and VM from Table 48. CREF is zero.
2. Record the time to VM.
3. Simulate the same signal standard with the output driver connected to the PCB trace with load. Use the appropriate IBIS
model (including V , RREF, CREF, and VMEAS values) or capacitive value to represent the load.
REF
4. Record the time to VMEAS
.
5. Compare the results of steps 2 and 4. The increase (or decrease) in delay should be added to (or subtracted from) the
appropriate Output standard adjustment (Table 47) to yield the worst-case delay of the PCB trace.
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Spartan-3 FPGA Family: DC and Switching Characteristics
Simultaneously Switching Output Guidelines
This section provides guidelines for the maximum allowable number of Simultaneous Switching Outputs (SSOs). These
guidelines describe the maximum number of user I/O pins, of a given output signal standard, that should simultaneously
switch in the same direction, while maintaining a safe level of switching noise. Meeting these guidelines for the stated test
conditions ensures that the FPGA operates free from the adverse effects of ground and power bounce.
Ground or power bounce occurs when a large number of outputs simultaneously switch in the same direction. The output
drive transistors all conduct current to a common voltage rail. Low-to-High transitions conduct to the V
rail; High-to-Low
CCO
transitions conduct to the GND rail. The resulting cumulative current transient induces a voltage difference across the
inductance that exists between the die pad and the power supply or ground return. The inductance is associated with
bonding wires, the package lead frame, and any other signal routing inside the package. Other variables contribute to SSO
noise levels, including stray inductance on the PCB as well as capacitive loading at receivers. Any SSO-induced voltage
consequently affects internal switching noise margins and ultimately signal quality.
Table 49 and Table 50 provide the essential SSO guidelines. For each device/package combination, Table 49 provides the
number of equivalent V
/GND pairs. The equivalent number of pairs is based on characterization and will possibly not
CCO
match the physical number of pairs. For each output signal standard and drive strength, Table 50 recommends the maximum
number of SSOs, switching in the same direction, allowed per V /GND pair within an I/O bank. The Table 50 guidelines
CCO
are categorized by package style. Multiply the appropriate numbers from Table 49 and Table 50 to calculate the maximum
number of SSOs allowed within an I/O bank. Exceeding these SSO guidelines may result in increased power or ground
bounce, degraded signal integrity, or increased system jitter.
SSO
/IO Bank = Table 49 x Table 50
MAX
The recommended maximum SSO values assume that the FPGA is soldered on the printed circuit board and that the board
uses sound design practices. The SSO values do not apply for FPGAs mounted in sockets, due to the lead inductance
introduced by the socket.
The number of SSOs allowed for quad-flat packages (VQ, TQ, PQ) is lower than for ball grid array packages (FG) due to the
larger lead inductance of the quad-flat packages. Ball grid array packages are recommended for applications with a large
number of simultaneously switching outputs.
Table 49: Equivalent V
/GND Pairs per Bank
CCO
Device
XC3S50
VQ100
CP132(1)(2)
TQ144(1)
PQ208
FT256
FG320
FG456
FG676
FG900
FG1156(2)
1
1
–
–
–
–
–
–
1.5
–
1.5
1.5
1.5
–
2
2
2
–
–
–
–
–
–
3
3
3
–
–
–
–
–
–
3
3
3
–
–
–
–
–
5
5
5
5
–
–
–
–
–
5
6
6
6
6
–
–
–
–
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
–
–
–
–
–
–
–
–
–
–
–
–
9
–
–
–
10
10
12
12
–
–
Notes:
1. The V
lines for the pair of banks on each side of the CP132 and TQ144 packages are internally tied together. Each pair of interconnected
CCO
banks shares three V
/GND pairs. Consequently, the per bank number is 1.5.
CCO
2. The CP132, CPG132, FG1156, and FGG1156 packages are discontinued. See
http://www.xilinx.com/support/documentation/spartan-3_customer_notices.htm.
3. The information in this table also applies to Pb-free packages.
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Spartan-3 FPGA Family: DC and Switching Characteristics
Table 50: Recommended Number of Simultaneously Switching Outputs per V
/GND Pair
CCO
Package
Signal Standard
(IOSTANDARD)
FT256, FG320, FG456,
FG676, FG900, FG1156
VQ100
TQ144
PQ208
CP132
Single-Ended Standards
GTL
0
0
0
0
0
0
1
1
14
14
19
19
14
10
11
10
17
17
7
GTL_DCI
GTLP
0
0
0
1
GTLP_DCI
HSLVDCI_15
HSLVDCI_18
HSLVDCI_25
HSLVDCI_33
HSTL_I
0
0
0
1
6
6
6
6
7
7
7
7
7
7
7
7
10
11
11
7
10
11
11
7
10
11
11
7
10
11
11
7
HSTL_I_DCI
HSTL_III
HSTL_III_DCI
HSTL_I_18
HSTL_I_DCI_18
HSTL_II_18
HSTL_II_DCI_18
HSTL_III_18
HSTL_III_DCI_18
LVCMOS12
7
7
7
7
7
13
13
9
13
13
9
13
13
9
13
13
9
17
17
9
9
9
9
9
9
8
8
8
8
8
8
8
8
8
8
Slow
Fast
Slow
2
4
17
13
10
12
11
9
17
13
10
12
11
9
17
13
10
12
11
9
17
13
10
12
11
9
55
32
18
31
13
9
6
2
4
6
LVCMOS15
2
16
8
12
7
12
7
19
9
55
31
18
15
10
25
16
13
11
7
4
6
7
7
7
9
8
6
6
6
6
12
2
5
5
5
5
Fast
10
6
10
7
10
7
13
7
4
6
7
7
7
7
8
6
6
6
6
12
6
6
6
6
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Spartan-3 FPGA Family: DC and Switching Characteristics
Table 50: Recommended Number of Simultaneously Switching Outputs per V
/GND Pair (Cont’d)
CCO
Package
Signal Standard
(IOSTANDARD)
FT256, FG320, FG456,
FG676, FG900, FG1156
VQ100
TQ144
PQ208
CP132
LVDCI_15
6
6
6
6
6
6
6
6
14
14
14
64
34
22
18
13
10
36
21
13
10
9
LVDCI_DV2_15
HSLVDCI_15
LVCMOS18
6
6
6
6
Slow
2
4
19
13
8
13
8
13
8
29
19
9
6
8
8
8
7
7
7
9
12
16
2
5
5
5
5
5
5
5
5
Fast
13
8
13
8
13
8
19
13
8
4
6
8
8
8
8
7
7
7
7
12
16
5
5
5
5
5
5
5
5
6
LVDCI_18
7
7
7
7
10
10
10
76
46
33
24
18
11
7
LVDCI_DV2_18
HSLVDCI_18
LVCMOS25
7
7
7
7
7
7
7
7
Slow
2
4
28
13
13
7
16
10
8
12
10
8
42
19
19
9
6
8
7
7
12
16
24
2
6
6
6
9
6
6
6
6
5
5
5
5
Fast
17
10
8
12
10
8
12
10
8
26
13
13
7
42
20
15
13
11
8
4
6
8
7
7
7
12
16
24
6
6
6
6
6
6
6
6
5
5
5
5
5
LVDCI_25
7
7
7
7
11
11
11
LVDCI_DV2_25
HSLVDCI_25
7
7
7
7
7
7
7
7
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Spartan-3 FPGA Family: DC and Switching Characteristics
Table 50: Recommended Number of Simultaneously Switching Outputs per V
/GND Pair (Cont’d)
CCO
Package
Signal Standard
(IOSTANDARD)
FT256, FG320, FG456,
FG676, FG900, FG1156
VQ100
TQ144
PQ208
CP132
LVCMOS33
Slow
2
4
34
17
17
10
9
24
14
11
10
9
24
14
11
10
9
52
26
26
13
13
8
76
46
27
20
13
10
9
6
8
12
16
24
2
8
8
8
8
8
8
8
Fast
20
15
11
10
8
20
15
11
10
8
20
15
11
10
8
26
15
13
10
8
44
26
16
12
10
8
4
6
8
12
16
24
8
8
8
8
7
7
7
7
7
LVDCI_33
10
10
10
34
17
17
12
10
10
8
10
10
10
25
16
15
12
10
10
8
10
10
10
25
16
15
12
10
10
8
10
10
10
52
26
26
13
13
10
8
10
10
10
60
41
29
22
13
11
9
LVDCI_DV2_33
HSLVDCI_33
LVTTL
Slow
2
4
6
8
12
16
24
2
Fast
20
13
11
10
9
20
13
11
10
9
20
13
11
10
9
26
13
13
10
9
34
20
15
12
10
9
4
6
8
12
16
24
8
8
8
8
7
7
7
7
7
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Spartan-3 FPGA Family: DC and Switching Characteristics
Table 50: Recommended Number of Simultaneously Switching Outputs per V
/GND Pair (Cont’d)
CCO
Package
Signal Standard
(IOSTANDARD)
FT256, FG320, FG456,
FG676, FG900, FG1156
VQ100
TQ144
PQ208
CP132
PCI33_3
9
13
13
8
9
13
13
8
9
13
13
8
9
13
13
8
9
17
17
9
SSTL18_I
SSTL18_I_DCI
SSTL18_II
SSTL2_I
10
10
6
10
10
6
10
10
6
10
10
6
13
13
9
SSTL2_I_DCI
SSTL2_II
SSTL2_II_DCI
6
6
6
6
9
Differential Standards (Number of I/O Pairs or Channels)
LDT_25 (ULVDS_25)
LVDS_25
5
7
2
5
2
7
4
4
3
3
5
5
1
5
1
5
4
4
3
3
5
5
1
5
1
5
4
4
3
3
5
5
20
4
12
BLVDS_25
LVDSEXT_25
5
5
LVPECL_25
4
RSDS_25
12
4
20
4
DIFF_HSTL_II_18
DIFF_HSTL_II_18_DCI
DIFF_SSTL2_II
DIFF_SSTL2_II_DCI
4
4
3
4
3
4
Notes:
1. The numbers in this table are recommendations that assume the FPGA is soldered on a printed circuit board using sound practices. This
table assumes the following parasitic factors: combined PCB trace and land inductance per V and GND pin of 1.0 nH, receiver capacitive
CCO
load of 15 pF. Test limits are the V /V voltage limits for the respective I/O standard.
IL IH
2. Regarding the SSO numbers for all DCI standards, the R
resistors connected to the VRN and VRP pins of the FPGA are 50W..
REF
3. If more than one signal standard is assigned to the I/Os of a given bank, refer to XAPP689: Managing Ground Bounce in Large FPGAs for
information on how to perform weighted average SSO calculations.
4. Results are based on actual silicon testing using an FPGA soldered on a typical printed-circuit board.
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Spartan-3 FPGA Family: DC and Switching Characteristics
Internal Logic Timing
Table 51: CLB Timing
Speed Grade
Symbol
Description
-5
-4
Units
Min
Max
Min
Max
Clock-to-Output Times
TCKO
When reading from the FFX (FFY) Flip-Flop, the time
from the active transition at the CLK input to data
appearing at the XQ (YQ) output
–
0.63
–
0.72
ns
Setup Times
TAS
Time from the setup of data at the F or G input to the
active transition at the CLK input of the CLB
0.46
1.27
–
–
0.53
1.57
–
–
ns
ns
TDICK
Time from the setup of data at the BX or BY input to
the active transition at the CLK input of the CLB
Hold Times
TAH
Time from the active transition at the CLK input to
the point where data is last held at the F or G input
0
–
–
0
–
–
ns
ns
TCKDI
Time from the active transition at the CLK input to
the point where data is last held at the BX or BY input
0.25
0.29
Clock Timing
TCH
CLB CLK signal High pulse width
0.69
0.69
–
∞
∞
0.79
0.79
–
∞
∞
ns
ns
TCL
CLB CLK signal Low pulse width
FTOG
Maximum toggle frequency (for export control)
725
630
MHz
Propagation Times
TILO
The time it takes for data to travel from the CLB’s
F (G) input to the X (Y) output
–
0.53
–
–
0.61
–
ns
ns
Set/Reset Pulse Width
TRPW_CLB
The minimum allowable pulse width, High or Low, to
the CLB’s SR input
0.76
0.87
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 32.
2. The timing shown is for SLICEM.
3. For minimums, use the values reported by the Xilinx timing analyzer.
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Spartan-3 FPGA Family: DC and Switching Characteristics
Table 52: CLB Distributed RAM Switching Characteristics
-5
-4
Symbol
Description
Units
Min
Max
Min
Max
Clock-to-Output Times
TSHCKO
Time from the active edge at the CLK input to data appearing on
the distributed RAM output
–
1.87
–
2.15
ns
Setup Times
TDS
Setup time of data at the BX or BY input before the active
transition at the CLK input of the distributed RAM
0.46
0.46
0.33
–
–
–
0.52
0.53
0.37
–
–
–
ns
ns
ns
TAS
Setup time of the F/G address inputs before the active transition
at the CLK input of the distributed RAM
TWS
Setup time of the write enable input before the active transition at
the CLK input of the distributed RAM
Hold Times
TDH, TAH, TWH
Hold time of the BX, BY data inputs, the F/G address inputs, or
the write enable input after the active transition at the CLK input
of the distributed RAM
0
–
–
0
–
–
ns
ns
Clock Pulse Width
TWPH, TWPL
Minimum High or Low pulse width at CLK input
0.85
0.97
Table 53: CLB Shift Register Switching Characteristics
-5
-4
Symbol
Description
Units
Min
Max
Min
Max
Clock-to-Output Times
TREG
Time from the active edge at the CLK input to data appearing on
the shift register output
–
3.30
–
3.79
ns
Setup Times
TSRLDS
Setup time of data at the BX or BY input before the active
transition at the CLK input of the shift register
0.46
0
–
–
–
0.52
0
–
–
–
ns
ns
ns
Hold Times
TSRLDH
Hold time of the BX or BY data input after the active transition at
the CLK input of the shift register
Clock Pulse Width
TWPH, TWPL
Minimum High or Low pulse width at CLK input
0.85
0.97
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Spartan-3 FPGA Family: DC and Switching Characteristics
Speed Grade
Table 54: Synchronous 18 x 18 Multiplier Timing
Symbol
Description
P Outputs
-5
-4
Units
Min
Max
Min
Max
Clock-to-Output Times
TMULTCK
When reading from the
Multiplier, the time from the
active transition at the C clock
input to data appearing at the P
outputs
P[0]
–
–
–
–
–
–
–
1.00
1.15
1.30
1.45
1.76
2.37
2.67
–
–
–
–
–
–
–
1.15
1.32
1.50
1.67
2.02
2.72
3.07
ns
ns
ns
ns
ns
ns
ns
P[15]
P[17]
P[19]
P[23]
P[31]
P[35]
Setup Times
TMULIDCK
Time from the setup of data at
the A and B inputs to the active
transition at the C input of the
Multiplier
-
1.84
–
2.11
–
ns
Hold Times
TMULCKID
Time from the active transition
at the Multiplier’s C input to the
point where data is last held at
the A and B inputs
-
0
–
0
–
ns
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 32.
Table 55: Asynchronous 18 x 18 Multiplier Timing
Speed Grade
Symbol
Description
P Outputs
-5
-4
Units
Max
Max
Propagation Times
TMULT
The time it takes for data to travel from the A and B inputs
to the P outputs
P[0]
1.55
3.15
3.36
3.49
3.73
4.23
4.47
1.78
3.62
3.86
4.01
4.29
4.86
5.14
ns
ns
ns
ns
ns
ns
ns
P[15]
P[17]
P[19]
P[23]
P[31]
P[35]
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 32.
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Spartan-3 FPGA Family: DC and Switching Characteristics
Speed Grade
Table 56: Block RAM Timing
Symbol
Description
-5
-4
Units
Min
Max
Min
Max
Clock-to-Output Times
TBCKO
When reading from the Block RAM,
the time from the active transition at
the CLK input to data appearing at
the DOUT output
–
2.09
–
2.40
ns
Setup Times
TBDCK
Time from the setup of data at the
DIN inputs to the active transition at
the CLK input of the Block RAM
0.43
0
–
–
0.49
0
–
–
ns
ns
Hold Times
TBCKD
Time from the active transition at the
Block RAM’s CLK input to the point
where data is last held at the DIN
inputs
Clock Timing
TBPWH
Block RAM CLK signal High pulse
width
1.19
1.19
∞
∞
1.37
1.37
∞
∞
ns
ns
TBPWL
Block RAM CLK signal Low pulse
width
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 32.
2. For minimums, use the values reported by the Xilinx timing analyzer.
Clock Distribution Switching Characteristics
Table 57: Clock Distribution Switching Characteristics
Maximum
Description
Symbol
Speed Grade
Units
-5
-4
Global clock buffer (BUFG, BUFGMUX, BUFGCE) I-input to O-output delay
TGIO
TGSI
0.36
0.53
0.41
0.60
ns
ns
Global clock multiplexer (BUFGMUX) select S-input setup to I0- and I1-inputs. Same
as BUFGCE enable CE-input
Notes:
1. For minimums, use the values reported by the Xilinx timing analyzer.
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Spartan-3 FPGA Family: DC and Switching Characteristics
Digital Clock Manager (DCM) Timing
For specification purposes, the DCM consists of three key components: the Delay-Locked Loop (DLL), the Digital Frequency
Synthesizer (DFS), and the Phase Shifter (PS).
Aspects of DLL operation play a role in all DCM applications. All such applications inevitably use the CLKIN and the CLKFB
inputs connected to either the CLK0 or the CLK2X feedback, respectively. Thus, specifications in the DLL tables (Table 58
and Table 59) apply to any application that only employs the DLL component. When the DFS and/or the PS components are
used together with the DLL, then the specifications listed in the DFS and PS tables (Table 60 through Table 63) supersede
any corresponding ones in the DLL tables. DLL specifications that do not change with the addition of DFS or PS functions
are presented in Table 58 and Table 59.
Period jitter and cycle-cycle jitter are two (of many) different ways of characterizing clock jitter. Both specifications describe
statistical variation from a mean value.
Period jitter is the worst-case deviation from the average clock period of all clock cycles in the collection of clock periods
sampled (usually from 100,000 to more than a million samples for specification purposes). In a histogram of period jitter, the
mean value is the clock period.
Cycle-cycle jitter is the worst-case difference in clock period between adjacent clock cycles in the collection of clock periods
sampled. In a histogram of cycle-cycle jitter, the mean value is zero.
Delay-Locked Loop (DLL)
Table 58: Recommended Operating Conditions for the DLL
Speed Grade
Frequency Mode/
FCLKIN Range
Symbol
Description
-5
-4
Units
Min
Max
Min
Max
Input Frequency Ranges
(2)
18
(3)
(2)
18
(3)
FCLKIN CLKIN_FREQ_DLL_LF Frequency for the CLKIN input
CLKIN_FREQ_DLL_HF
Low
167
280
167
MHz
MHz
(3)
(3)(4)
High
48
48
280
Input Pulse Requirements
CLKIN_PULSE
CLKIN pulse width as a
percentage of the CLKIN period
FCLKIN ≤ 100 MHz
FCLKIN > 100 MHz
40%
45%
60%
55%
40%
45%
60%
55%
-
-
(5)
Input Clock Jitter Tolerance and Delay Path Variation
CLKIN_CYC_JITT_DLL_LF
CLKIN_CYC_JITT_DLL_HF
CLKIN_PER_JITT_DLL_LF
CLKIN_PER_JITT_DLL_HF
CLKFB_DELAY_VAR_EXT
Cycle-to-cycle jitter at the CLKIN
input
Low
High
All
–
–
–
–
–
300
150
1
–
–
–
–
–
300
150
1
ps
ps
ns
Period jitter at the CLKIN input
Allowable variation of off-chip
feedback delay from the DCM
output to the CLKFB input
All
1
1
ns
Notes:
1. DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.
2. The DFS, when operating independently of the DLL, supports lower F frequencies. See Table 60.
CLKIN
3. The CLKIN_DIVIDE_BY_2 attribute can be used to increase the effective input frequency range up to F
CLKIN_DIVIDE_BY_2 divides the incoming clock frequency by two as it enters the DCM.
. When set to TRUE,
BUFG
4. Industrial temperature range devices have additional requirements for continuous clocking, as specified in Table 64.
5. CLKIN input jitter beyond these limits may cause the DCM to lose lock. See UG331 for more details.
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Spartan-3 FPGA Family: DC and Switching Characteristics
Table 59: Switching Characteristics for the DLL
Speed Grade
Frequency Mode /
FCLKIN Range
Symbol
Description
Device
-5
-4
Units
Min Max Min Max
Output Frequency Ranges
CLKOUT_FREQ_1X_LF
Frequency for the CLK0,
CLK90, CLK180, and CLK270
outputs
Low
All
18
167
18
167
MHz
CLKOUT_FREQ_1X_HF
Frequency for the CLK0 and
CLK180 outputs
High
Low
48
36
280
334
48
36
280
334
MHz
MHz
(3)
CLKOUT_FREQ_2X_LF
Frequency for the CLK2X and
CLK2X180 outputs
1.125
3
1.125
3
CLKOUT_FREQ_DV_LF
CLKOUT_FREQ_DV_HF
Output Clock Jitter(4)
CLKOUT_PER_JITT_0
Frequency for the CLKDV
output
Low
110
185
110
185
MHz
MHz
High
Period jitter at the CLK0
output
All
All
100
150
150
150
200
150
100
150
150
150
200
150
ps
ps
ps
ps
ps
ps
–
–
–
–
–
–
–
–
–
–
–
–
CLKOUT_PER_JITT_90
CLKOUT_PER_JITT_180
CLKOUT_PER_JITT_270
CLKOUT_PER_JITT_2X
CLKOUT_PER_JITT_DV1
Period jitter at the CLK90
output
Period jitter at the CLK180
output
Period jitter at the CLK270
output
Period jitter at the CLK2X and
CLK2X180 outputs
Period jitter at the CLKDV
output when performing
integer division
CLKOUT_PER_JITT_DV2
Period jitter at the CLKDV
output when performing
non-integer division
300
300
ps
–
–
Duty Cycle
(5)
CLKOUT_DUTY_CYCLE_DLL
Duty cycle variation for the
CLK0, CLK90, CLK180,
CLK270, CLK2X, CLK2X180,
and CLKDV outputs
All
150
150
250
400
400
400
400
400
150
150
250
400
400
400
400
400
ps
ps
ps
ps
ps
ps
ps
ps
XC3S50
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
Phase Alignment
CLKIN_CLKFB_PHASE
Phase offset between the
CLKIN and CLKFB inputs
All
All
150
140
150
140
ps
ps
–
–
–
–
CLKOUT_PHASE
Phase offset between any two
DLL outputs (except CLK2X
and CLK0)
Phase offset between the
CLK2X and CLK0 outputs
250
250
ps
–
–
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Spartan-3 FPGA Family: DC and Switching Characteristics
Table 59: Switching Characteristics for the DLL (Cont’d)
Speed Grade
Frequency Mode /
FCLKIN Range
Symbol
Description
Device
-5
-4
Units
Min Max Min Max
Lock Time
18 MHz ≤ FCLKIN ≤ 30 MHz
30 MHz < FCLKIN ≤ 40 MHz
40 MHz < FCLKIN ≤ 50 MHz
50 MHz < FCLKIN ≤ 60 MHz
FCLKIN > 60 MHz
LOCK_DLL
When using the DLL alone:
The time from deassertion at
the DCM’s Reset input to the
rising transition at its
LOCKED output. When the
DCM is locked, the CLKIN and
CLKFB signals are in phase
All
2.88
2.16
1.20
0.60
0.48
2.88
2.16
1.20
0.60
0.48
ms
ms
ms
ms
ms
–
–
–
–
–
–
–
–
–
–
Delay Lines
DCM_TAP
Delay tap resolution
All
All
30.0 60.0 30.0 60.0
ps
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 32 and Table 58.
2. DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.
3. Only mask revision ‘E’ and later devices (see Mask and Fab Revisions, page 58) and all revisions of the XC3S50 and the XC3S1000 support
DLL feedback using the CLK2X output. For all other Spartan-3 devices, use feedback from the CLK0 output (instead of the CLK2X output)
and set the CLK_FEEDBACK attribute to 1X.
4. Indicates the maximum amount of output jitter that the DCM adds to the jitter on the CLKIN input.
5. This specification only applies if the attribute DUTY_CYCLE_CORRECTION = TRUE.
Digital Frequency Synthesizer (DFS)
Table 60: Recommended Operating Conditions for the DFS
Speed Grade
Frequency
Symbol
Description
-5
-4
Units
Mode
Min
Max
Min
Max
Input Frequency Ranges(2)
FCLKIN
CLKIN_FREQ_FX
Frequency for the CLKIN input
All
1
280
1
280
MHz
Input Clock Jitter Tolerance(3)
CLKIN_CYC_JITT_FX_LF
CLKIN_CYC_JITT_FX_HF
CLKIN_PER_JITT_FX
Cycle-to-cycle jitter at the CLKIN
input
Low
High
All
–
–
–
300
150
1
–
–
–
300
150
1
ps
ps
ns
Period jitter at the CLKIN input
Notes:
1. DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) are used.
2. If both DFS and DLL outputs are used on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in Table 58.
3. CLKIN input jitter beyond these limits may cause the DCM to lose lock.
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Spartan-3 FPGA Family: DC and Switching Characteristics
Table 61: Switching Characteristics for the DFS
Speed Grade
Frequency
Symbol
Description
Device
-5
-4
Units
Mode
Min
Max
Min
Max
Output Frequency Ranges
CLKOUT_FREQ_FX_LF
CLKOUT_FREQ_FX_HF
Output Clock Jitter
Frequency for the CLKFX and
CLKFX180 outputs
Low
All
All
18
210
18
210
MHz
High
210
326(2)
210
307(2) MHz
CLKOUT_PER_JITT_FX
Period jitter at the CLKFX and
CLKFX180 outputs
All
All
All
Note 3 Note 3 Note 3 Note 3
ps
Duty Cycle(4)
CLKOUT_DUTY_CYCLE_FX Duty cycle precision for the CLKFX
and CLKFX180 outputs
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
–
–
–
–
–
–
–
–
100
100
250
400
400
400
400
400
–
–
–
–
–
–
–
–
100
100
250
400
400
400
400
400
ps
ps
ps
ps
ps
ps
ps
ps
Phase Alignment
CLKOUT_PHASE
Phase offset between the DFS
output and the CLK0 output
All
All
All
All
–
–
300
–
–
300
ps
Lock Time
LOCK_DLL_FX
When using the DFS in conjunction
with the DLL: The time from
deassertion at the DCM’s Reset
input to the rising transition at its
LOCKED output. When the DCM is
locked, the CLKIN and CLKFB
signals are in phase.
10.0
10.0
ms
LOCK_FX
When using the DFS without the
DLL: The time from deassertion at
the DCM’s Reset input to the rising
transition at its LOCKED output. By
asserting the LOCKED signal, the
DFS indicates valid CLKFX and
CLKFX180 signals.
All
All
–
10.0
–
10.0
ms
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 32 and Table 60.
2. Mask revisions prior to the E mask revision have a CLKOUT_FREQ_FX_HF max of 280 MHz. See Mask and Fab Revisions, page 58.
3. Use the DCM Clocking Wizard in the ISE software for a Spartan-3 device specific number. Jitter number assumes 150 ps of input clock jitter.
4. The CLKFX and CLKFX180 outputs always approximate 50% duty cycles.
5. DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) is in use.
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Spartan-3 FPGA Family: DC and Switching Characteristics
Phase Shifter (PS)
Phase shifter operation is only supported if the DLL is in low-frequency mode, see Table 58. Fixed phase shift requires ISE
software version 10.1.03 (or later).
Table 62: Recommended Operating Conditions for the PS in Variable Phase Mode
Speed Grade
Frequency Mode/
FCLKIN Range
Symbol
Description
-5
-4
Units
Min
Max
Min
Max
Operating Frequency Ranges
PSCLK_FREQ Frequency for the
Low
1
167
1
167
MHz
(FPSCLK PSCLK input
)
Input Pulse Requirements
PSCLK_PULSE PSCLK pulse width
Low
FCLKIN ≤ 100 MHz
FCLKIN > 100 MHz
40%
45%
60%
55%
40%
45%
60%
55%
-
-
as a percentage of
the PSCLK period
Table 63: Switching Characteristics for the PS in Variable or Fixed Phase Shift Mode
Speed Grade
Frequency Mode/
FCLKIN Range
Symbol
Description
-5
-4
Units
Min
Max
Min
Max
Phase Shifting Range
FINE_SHIFT_RANGE Phase shift range
Low
–
10.0
–
10.0
ns
Lock Time
LOCK_DLL_PS
LOCK_DLL_PS_FX
Notes:
When using the PS in conjunction 18 MHz ≤ FCLKIN ≤ 30 MHz
–
–
–
–
–
–
3.28
2.56
1.60
1.00
0.88
10.40
–
–
–
–
–
–
3.28
2.56
1.60
1.00
0.88
10.40
ms
ms
ms
ms
ms
ms
with the DLL: The time from
30 MHz < FCLKIN ≤ 40 MHz
deassertion at the DCM’s Reset
input to the rising transition at its
LOCKED output. When the DCM
is locked, the CLKIN and CLKFB
signals are in phase.
40 MHz < FCLKIN ≤ 50 MHz
50 MHz < FCLKIN ≤ 60 MHz
60 MHz < FCLKIN ≤ 165 MHz
Low
When using the PS in conjunction
with the DLL and DFS: The time
from deassertion at the DCM’s
Reset input to the rising transition
at its LOCKED output. When the
DCM is locked, the CLKIN and
CLKFB signals are in phase.
1. The numbers in this table are based on the operating conditions set forth in Table 32 and Table 62.
2. The PS specifications in this table apply when the PS attribute CLKOUT_PHASE_SHIFT= VARIABLE or FIXED.
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Spartan-3 FPGA Family: DC and Switching Characteristics
Miscellaneous DCM Timing
Table 64: Miscellaneous DCM Timing
DLL
Frequency
Mode
Temperature Range
Symbol
Description
Units
Commercial Industrial
DCM_INPUT_CLOCK_STOP Maximum duration that the CLKIN and
CLKFB signals can be stopped(1,2)
Any
100
100
ms
DCM_RST_PW_MIN
Minimum duration of a RST pulse width
Any
3
3
CLKIN
cycles
DCM_RST_PW_MAX(3)
Maximum duration of a RST pulse width(1,2)
Low
High
Low
N/A
N/A
N/A
N/A
10
seconds
seconds
minutes
DCM_CONFIG_LAG_TIME(4) Maximum duration from VCCINT applied to
FPGA configuration successfully completed
(DONE pin goes High) and clocks applied to
DCM DLL(1,2)
N/A
High
N/A
10
minutes
Notes:
1. These limits only apply to applications that use the DCM DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV).
The DCM DFS outputs (CLKFX, CLKFX180) are unaffected. Required due to effects of device cooling: see “Momentarily Stopping CLKIN”
in Chapter 3 of UG331.
2. Industrial-temperature applications that use the DLL in High-Frequency mode must use a continuous or increasing operating frequency. The
DLL under these conditions does not support reducing the operating frequency once establishing an initial operating frequency.
3. This specification is equivalent to the Virtex-4 FPGA DCM_RESET specification.
4. This specification is equivalent to the Virtex-4 FPGA TCONFIG specification.
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Spartan-3 FPGA Family: DC and Switching Characteristics
Configuration and JTAG Timing
X-Ref Target - Figure 36
1.2V
2.5V
V
CCINT
1.0V
2.0V
1.0V
(Supply)
V
CCAUX
(Supply)
V
Bank 4
CCO
(Supply)
TPOR
PROG_B
(Input)
TPL
TPROG
INIT_B
(Open-Drain)
TICCK
CCLK
(Output)
DS099-3_03_120604
Notes:
1. The V
, V
, and V
supplies may be applied in any order.
CCO
CCINT CCAUX
2. The Low-going pulse on PROG_B is optional after power-on but necessary for reconfiguration without a power cycle.
3. The rising edge of INIT_B samples the voltage levels applied to the mode pins (M0 - M2).
Figure 36: Waveforms for Power-On and the Beginning of Configuration
Table 65: Power-On Timing and the Beginning of Configuration
All Speed Grades
Symbol
Description
Device
Units
Min
–
Max
5
(2)
TPOR
The time from the application of VCCINT, VCCAUX, and VCCO XC3S50
Bank 4 supply voltage ramps (whichever occurs last) to the
rising transition of the INIT_B pin
ms
ms
ms
ms
ms
ms
ms
ms
μs
XC3S200
–
5
XC3S400
–
5
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
–
5
–
7
–
7
–
7
–
7
TPROG
The width of the low-going pulse on the PROG_B pin
All
0.3
–
–
(2)
TPL
The time from the rising edge of the PROG_B pin to the
rising transition on the INIT_B pin
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
All
2
ms
ms
ms
ms
ms
ms
ms
ms
ns
–
2
–
2
–
2
–
3
–
3
–
3
–
3
TINIT
Minimum Low pulse width on INIT_B output
250
0.25
–
(3)
TICCK
The time from the rising edge of the INIT_B pin to the
generation of the configuration clock signal at the CCLK
output pin
All
4.0
μs
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 32. This means power must be applied to all V
, V
,
CCINT CCO
and V
lines.
CCAUX
2. Power-on reset and the clearing of configuration memory occurs during this period.
3. This specification applies only for the Master Serial and Master Parallel modes.
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Spartan-3 FPGA Family: DC and Switching Characteristics
X-Ref Target - Figure 37
PROG_B
(Input)
INIT_B
(Open-Drain)
TCCL
TCCH
CCLK
(Input/Output)
TDCC
1/FCCSER
TCCD
DIN
(Input)
Bit n+1
TCCO
Bit n
Bit 0
Bit 1
DOUT
(Output)
Bit n-63
Bit n-64
DS099-3_04_071604
Figure 37: Waveforms for Master and Slave Serial Configuration
Table 66: Timing for the Master and Slave Serial Configuration Modes
All Speed Grades
Slave/
Master
Symbol
Description
Units
Min
Max
Clock-to-Output Times
TCCO
The time from the falling transition on the CCLK pin to data appearing at the
DOUT pin
Both
Both
Both
Slave
1.5
12.0
ns
Setup Times
TDCC
The time from the setup of data at the DIN pin to the rising transition at the
CCLK pin
10.0
0
–
–
ns
ns
Hold Times
TCCD
The time from the rising transition at the CCLK pin to the point when data is
last held at the DIN pin
Clock Timing
TCCH
CCLK input pin High pulse width
5.0
5.0
0
∞
∞
66(2)
ns
ns
TCCL
CCLK input pin Low pulse width
FCCSER
Frequency of the clock signal at the
CCLK input pin
No bitstream compression
With bitstream compression
During STARTUP phase
MHz
MHz
MHz
–
0
20
0
50
ΔFCCSER
Variation from the CCLK output frequency set using the ConfigRate BitGen
option
Master
–50%
+50%
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 32.
2. For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz.
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Spartan-3 FPGA Family: DC and Switching Characteristics
X-Ref Target - Figure 38
PROG_B
(Input)
INIT_B
(Open-Drain)
TSMCSCC
TSMCCCS
CS_B
(Input)
TSMCCW
TSMWCC
RDWR_B
(Input)
TCCH
TCCL
CCLK
(Input/Output)
1/FCCPAR
Byte n
TSMDCC
TSMCCD
D0 - D7
(Inputs)
Byte 0
Byte 1
Byte n+1
TSMCKBY
TSMCKBY
High-Z
High-Z
BUSY
(Output)
BUSY
DS099-3_05_041103
Figure 38: Waveforms for Master and Slave Parallel Configuration
Table 67: Timing for the Master and Slave Parallel Configuration Modes
All Speed Grades
Slave/
Master
Symbol
Description
Units
Min
Max
Clock-to-Output Times
TSMCKBY
The time from the rising transition on the CCLK pin to a signal transition at
the BUSY pin
Slave
Both
–
12.0
ns
Setup Times
TSMDCC
The time from the setup of data at the D0-D7 pins to the rising transition at
the CCLK pin
10.0
10.0
10.0
–
–
–
ns
ns
ns
TSMCSCC
The time from the setup of a logic level at the CS_B pin to the rising
transition at the CCLK pin
(3)
TSMCCW
The time from the setup of a logic level at the RDWR_B pin to the rising
transition at the CCLK pin
Hold Times
TSMCCD
The time from the rising transition at the CCLK pin to the point when data
is last held at the D0-D7 pins
Both
0
0
0
–
–
–
ns
ns
ns
TSMCCCS
The time from the rising transition at the CCLK pin to the point when a logic
level is last held at the CS_B pin
(3)
TSMWCC
The time from the rising transition at the CCLK pin to the point when a logic
level is last held at the RDWR_B pin
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Spartan-3 FPGA Family: DC and Switching Characteristics
Table 67: Timing for the Master and Slave Parallel Configuration Modes (Cont’d)
All Speed Grades
Slave/
Master
Symbol
Description
Units
Min
Max
Clock Timing
TCCH
CCLK input pin High pulse width
CCLK input pin Low pulse width
Slave
5
∞
∞
ns
ns
TCCL
5
FCCPAR
Frequency of the clock
signal at the CCLK input compression
pin
No bitstream
Not using the BUSY pin(4)
Using the BUSY pin
0
50
MHz
MHz
MHz
MHz
–
0
0
66
With bitstream compression
20
During STARTUP phase
0
50
ΔFCCPAR
Variation from the CCLK output frequency set using the BitGen option
ConfigRate
Master
–50%
+50%
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 32.
2. Some Xilinx documents may refer to Parallel modes as "SelectMAP" modes.
3. RDWR_B is synchronized to CCLK for the purpose of performing the Abort operation. The same pin asynchronously controls the driver
impedance of the D0 - D7 pins. To avoid contention when writing configuration data to the D0 - D7 bus, do not bring RDWR_B High when
CS_B is Low.
4. In the Slave Parallel mode, it is necessary to use the BUSY pin when the CCLK frequency exceeds this maximum specification.
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Spartan-3 FPGA Family: DC and Switching Characteristics
X-Ref Target - Figure 39
TCCH
TCCL
TCK
(Input)
1/FTCK
TTCKTMS
TTMSTCK
TMS
(Input)
TTDITCK
TTCKTDI
TDI
(Input)
TTCKTDO
TDO
(Output)
DS099_06_102909
Figure 39: JTAG Waveforms
Table 68: Timing for the JTAG Test Access Port
All Speed Grades
Symbol
Description
Units
Min
Max
Clock-to-Output Times
TTCKTDO
The time from the falling transition on the TCK pin to data appearing at
the TDO pin
1.0
11.0
ns
Setup Times
TTDITCK
The time from the setup of data at the TDI pin to the rising transition at
the TCK pin
7.0
7.0
–
–
ns
ns
TTMSTCK
The time from the setup of a logic level at the TMS pin to the rising
transition at the TCK pin
Hold Times
TTCKTDI
The time from the rising transition at the TCK pin to the point when data
is last held at the TDI pin
0
0
–
–
ns
ns
TTCKTMS
The time from the rising transition at the TCK pin to the point when a logic
level is last held at the TMS pin
Clock Timing
TTCKH
TCK pin High pulse width
TCK pin Low pulse width
5
5
0
0
∞
∞
ns
ns
TTCKL
FTCK
Frequency of the TCK signal
JTAG Configuration
Boundary-Scan
33
25
MHz
MHz
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 32.
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Spartan-3 FPGA Family: DC and Switching Characteristics
Revision History
Date
Version
Description
04/11/2003
07/11/2003
1.0
Initial Xilinx release.
1.1
Extended Absolute Maximum Rating for junction temperature in Table 28. Added numbers for typical
quiescent supply current (Table 34) and DLL timing.
02/06/2004
1.2
Revised VIN maximum rating (Table 28). Added power-on requirements (Table 30), leakage current
number (Table 33), and differential output voltage levels (Table 38) for Rev. 0. Published new quiescent
current numbers (Table 34). Updated pull-up and pull-down resistor strengths (Table 33). Added
LVDCI_DV2 and LVPECL standards (Table 37 and Table 38). Changed CCLK setup time (Table 66 and
Table 67).
03/04/2004
08/24/2004
1.3
1.4
Added timing numbers from v1.29 speed files as well as DCM timing (Table 58 through Table 63).
Added reference to errata documents on page 49. Clarified Absolute Maximum Ratings and added ESD
information (Table 28). Explained VCCO ramp time measurement (Table 30). Clarified IL specification
(Table 33). Updated quiescent current numbers and added information on power-on and surplus current
(Table 34). Adjusted VREF range for HSTL_III and HSTL_I_18 and changed VIH min for LVCMOS12
(Table 35). Added note limiting VTT range for SSTL2_II signal standards (Table 36). Calculated VOH and
VOL levels for differential standards (Table 38). Updated Switching Characteristics with speed file v1.32
(Table 40 through Table 48 and Table 51 through Table 56). Corrected IOB test conditions (Table 41).
Updated DCM timing with latest characterization data (Table 58 through Table 62). Improved DCM CLKIN
pulse width specification (Table 58). Recommended use of Virtex-II FPGA Jitter calculator (Table 61).
Improved DCM PSCLK pulse width specification (Table 62). Changed Phase Shifter lock time parameter
(Table 63). Because the BitGen option Centered_x#_y# is not necessary for Variable Phase Shift mode,
removed BitGen command table and referring text. Adjusted maximum CCLK frequency for the slave
serial and parallel configuration modes (Table 66). Inverted CCLK waveform (Figure 37). Adjusted JTAG
setup times (Table 68).
12/17/2004
08/19/2005
1.5
1.6
Updated timing parameters to match v1.35 speed file. Improved VCCO ramp time specification (Table 30).
Added a note limiting the rate of change of VCCAUX (Table 32). Added typical quiescent current values for
the XC3S2000, XC3S4000, and XC3S5000 (Table 34). Increased IOH and IOL for SSTL2-I and SSTL2-II
standards (Table 36). Added SSO guidelines for the VQ, TQ, and PQ packages as well as edited SSO
guidelines for the FT and FG packages (Table 50). Added maximum CCLK frequencies for configuration
using compressed bitstreams (Table 66 and Table 67). Added specifications for the HSLVDCI standards
(Table 35, Table 36, Table 44, Table 47, Table 48, and Table 50).
Updated timing parameters to match v1.37 speed file. All Spartan-3 FPGA part types, except XC3S5000,
promoted to Production status. Removed VCCO ramp rate restriction from all mask revision ‘E’ and later
devices (Table 30). Added equivalent resistance values for internal pull-up and pull-down resistors
(Table 33). Added worst-case quiescent current values for XC3S2000, XC3S4000, XC3S5000 (Table 34).
Added industrial temperature range specification and improved typical quiescent current values
(Table 34). Improved the DLL minimum clock input frequency specification from 24 MHz down to 18 MHz
(Table 58). Improved the DFS minimum and maximum clock output frequency specifications (Table 60,
Table 61). Added new miscellaneous DCM specifications (Table 64), primarily affecting Industrial
temperature range applications. Updated Simultaneously Switching Output Guidelines and Table 50 for
QFP packages. Added information on SSTL18_II I/O standard and timing to support DDR2 SDRAM
interfaces. Added differential (or complementary single-ended) DIFF_HSTL_II_18 and DIFF_SSTL2_II
I/O standards, including DCI terminated versions. Added electro-static discharge (ESD) data for the
XC3S2000 and larger FPGAs (Table 28). Added link to Spartan-3 FPGA errata notices and how to
receive automatic notifications of data sheet or errata changes.
04/03/2006
04/26/2006
2.0
2.1
Upgraded Module 3, removing Preliminary status. Moved XC3S5000 to Production status in Table 39.
Finalized I/O timing on XC3S5000 for v1.38 speed files. Added minimum timing values for various logic
and I/O paths. Corrected labels for RPU and RPD and updated RPD conditions for in Table 33. Added final
mask revision ‘E’ specifications for LVDS_25, RSDS_25, LVDSEXT_25 differential outputs to Table 38.
Added BLVDS termination requirements to Figure 34. Improved recommended Simultaneous Switching
Outputs (SSOs) limits in Table 50 for quad-flat packaged based on silicon testing using devices soldered
on a printed circuit board. Updated Note 2 in Table 63. Updated Note 6 in Table 30. Added INIT_B
minimum pulse width specification, TINIT, to Table 65.
Updated document links.
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Spartan-3 FPGA Family: DC and Switching Characteristics
Description
Date
Version
05/25/2007
2.2
Improved absolute maximum voltage specifications in Table 28, providing additional overshoot allowance.
Improved XC3S50 HBM ESD to 2000V in Table 28. Based on extensive 90 nm production data, improved
(reduced) the maximum quiescent current limits for the ICCINTQ and ICCOQ specifications in Table 34.
Widened the recommended voltage range for the PCI standard and clarified the hysteresis footnote in
Table 35. Noted restriction on combining differential outputs in Table 38. Updated footnote 1 in Table 64.
11/30/2007
06/25/2008
2.3
2.4
Updated 3.3V VCCO max from 3.45V to 3.465V in Table 32 and elsewhere. Reduced tICCK minimum from
0.50μs to 0.25μs in Table 65. Updated links to technical documentation.
Clarified dual marking. Added Mask and Fab Revisions. Added references to XAPP459 in Table 28 and
Table 32. Removed absolute minimum and added footnote referring to timing analyzer for minimum delay
values. Added HSLVDCI to Table 48 and Table 50. Updated tDICK in Table 51 to match largest possible
value in speed file. Updated formatting and links.
12/04/2009
2.5
Updated notes 2 and 3 in Table 28. Removed silicon process specific information and revised notes in
Table 30. Updated note 3 in Table 32. Updated note 3 in Table 34. Updated note 5 in Table 35. Updated
VOL max and VOH min for SSTL2_II in Table 36. Updated note 5 in Table 36. Updated JTAG Waveforms
in Figure 39. Updated VICM max for LVPECL_25 in Table 37. Updated RT and VT for LVDS_25_DCI in
Table 48. Updated Simultaneously Switching Output Guidelines. Noted that the CP132 package is being
discontinued in Table 49. Removed minimum values for TMULTCK clock-to-output times in Table 54.
Updated footnote 3 in Table 58. Removed minimum values for TMULT propagation times in Table 55.
Removed silicon process specific information and revised notes in Table 61. Updated Phase Shifter (PS).
10/29/2012
06/27/2013
3.0
3.1
Added Notice of Disclaimer. Per XCN07022, updated the discontinued FG1156 and FGG1156 package
discussion throughout document. Per XCN08011, updated the discontinued CP132 and CPG132
package discussion throughout document. Revised description of VIN in Table 32 and added note 7.
Added note 4 to Table 33. This product is not recommended for new designs.
Removed banner. This product IS recommended for new designs.
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Spartan-3 FPGA Family: DC and Switching Characteristics
Notice of Disclaimer
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272
Spartan-3 FPGA Family:
Pinout Descriptions
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Introduction
This data sheet module describes the various pins on a Spartan®-3 FPGA and how they connect to the supported
component packages.
•
•
•
The Pin Types section categorizes all of the FPGA pins by their function type.
The Pin Definitions section provides a top-level description for each pin on the device.
The Detailed, Functional Pin Descriptions section offers significantly more detail about each pin, especially for the dual-
or special-function pins used during device configuration.
•
•
Some pins have associated behavior that is controlled by settings in the configuration bitstream. These options are
described in the Bitstream Options section.
The Package Overview section describes the various packaging options available for Spartan-3 FPGAs. Detailed pin
list tables and footprint diagrams are provided for each package solution.
Pin Descriptions
Pin Types
A majority of the pins on a Spartan-3 FPGA are general-purpose, user-defined I/O pins. There are, however, up to 12
different functional types of pins on Spartan-3 device packages, as outlined in Table 69. In the package footprint drawings
that follow, the individual pins are color-coded according to pin type as in the table.
Table 69: Types of Pins on Spartan-3 FPGAs
Pin Type/
Color Code
Description
Pin Name
I/O
Unrestricted, general-purpose user-I/O pin. Most pins can be paired together to
form differential I/Os.
IO,
IO_Lxxy_#
DUAL
Dual-purpose pin used in some configuration modes during the configuration
IO_Lxxy_#/DIN/D0, IO_Lxxy_#/D1,
process and then usually available as a user I/O after configuration. If the pin is not IO_Lxxy_#/D2, IO_Lxxy_#/D3,
used during configuration, this pin behaves as an I/O-type pin. There are 12 IO_Lxxy_#/D4, IO_Lxxy_#/D5,
dual-purpose configuration pins on every package. The INIT_B pin has an internal IO_Lxxy_#/D6, IO_Lxxy_#/D7,
pull-up resistor to VCCO_4 or VCCO_BOTTOM during configuration.
IO_Lxxy_#/CS_B,
IO_Lxxy_#/RDWR_B,
IO_Lxxy_#/BUSY/DOUT,
IO_Lxxy_#/INIT_B
CONFIG
JTAG
Dedicated configuration pin. Not available as a user-I/O pin. Every package has
seven dedicated configuration pins. These pins are powered by VCCAUX and have PROG_B, HSWAP_EN
a dedicated internal pull-up resistor to VCCAUX during configuration.
CCLK, DONE, M2, M1, M0,
Dedicated JTAG pin. Not available as a user-I/O pin. Every package has four
dedicated JTAG pins. These pins are powered by VCCAUX and have a dedicated
internal pull-up resistor to VCCAUX during configuration.
TDI, TMS, TCK, TDO
DCI
Dual-purpose pin that is either a user-I/O pin or used to calibrate output buffer
impedance for a specific bank using Digital Controlled Impedance (DCI). There are IO_Lxxy_#/VRN_#
IO/VRN_#
two DCI pins per I/O bank.
IO/VRP_#
IO_Lxxy_#/VRP_#
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Spartan-3 FPGA Family: Pinout Descriptions
Pin Name
Table 69: Types of Pins on Spartan-3 FPGAs (Cont’d)
Pin Type/
Description
Color Code
VREF
Dual-purpose pin that is either a user-I/O pin or, along with all other VREF pins in IO/VREF_#
the same bank, provides a reference voltage input for certain I/O standards. If used IO_Lxxy_#/VREF_#
for a reference voltage within a bank, all VREF pins within the bank must be
connected.
GND
Dedicated ground pin. The number of GND pins depends on the package used. All GND
must be connected.
VCCAUX Dedicated auxiliary power supply pin. The number of VCCAUX pins depends on the VCCAUX
package used. All must be connected to +2.5V.
VCCINT
Dedicated internal core logic power supply pin. The number of VCCINT pins
depends on the package used. All must be connected to +1.2V.
VCCINT
VCCO
Dedicated I/O bank, output buffer power supply pin. Along with other VCCO pins in VCCO_#
the same bank, this pin supplies power to the output buffers within the I/O bank and CP132 and TQ144 Packages Only:
sets the input threshold voltage for some I/O standards.
VCCO_LEFT, VCCO_TOP,
VCCO_RIGHT, VCCO_BOTTOM
GCLK
Dual-purpose pin that is either a user-I/O pin or an input to a specific global buffer IO_Lxxy_#/GCLK0,
input. Every package has eight dedicated GCLK pins.
IO_Lxxy_#/GCLK1,
IO_Lxxy_#/GCLK2,
IO_Lxxy_#/GCLK3,
IO_Lxxy_#/GCLK4,
IO_Lxxy_#/GCLK5,
IO_Lxxy_#/GCLK6,
IO_Lxxy_#/GCLK7
N.C.
This package pin is not connected in this specific device/package combination but N.C.
may be connected in larger devices in the same package.
Notes:
1. # = I/O bank number, an integer between 0 and 7.
I/Os with Lxxy_# are part of a differential output pair. ‘L’ indicates differential output capability. The “xx” field is a two-digit
integer, unique to each bank that identifies a differential pin-pair. The ‘y’ field is either ‘P’ for the true signal or ‘N’ for the
inverted signal in the differential pair. The ‘#’ field is the I/O bank number.
Pin Definitions
Table 70 provides a brief description of each pin listed in the Spartan-3 FPGA pinout tables and package footprint diagrams.
Pins are categorized by their pin type, as listed in Table 69. See Detailed, Functional Pin Descriptions for more information.
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Spartan-3 FPGA Family: Pinout Descriptions
Table 70: Spartan-3 FPGA Pin Definitions
Pin Name
Direction
Description
I/O: General-purpose I/O pins
I/O
User-defined as input, output,
bidirectional, three-state output,
open-drain output, open-source
output
User I/O:
Unrestricted single-ended user-I/O pin. Supports all I/O standards except
the differential standards.
I/O_Lxxy_#
User-defined as input, output,
bidirectional, three-state output,
open-drain output, open-source
output
User I/O, Half of Differential Pair:
Unrestricted single-ended user-I/O pin or half of a differential pair.
Supports all I/O standards including the differential standards.
DUAL: Dual-purpose configuration pins
IO_Lxxy_#/DIN/D0,
IO_Lxxy_#/D1,
IO_Lxxy_#/D2,
IO_Lxxy_#/D3,
IO_Lxxy_#/D4,
IO_Lxxy_#/D5,
IO_Lxxy_#/D6,
IO_Lxxy_#/D7
Input during configuration
Configuration Data Port:
Possible bidirectional I/O after
configuration if SelectMap port is
retained
Otherwise, user I/O after
configuration
In Parallel (SelectMAP) modes, D0-D7 are byte-wide configuration data
pins. These pins become user I/Os after configuration unless the
SelectMAP port is retained via the Persist bitstream option.
In Serial modes, DIN (D0) serves as the single configuration data input.
This pin becomes a user I/O after configuration unless retained by the
Persist bitstream option.
IO_Lxxy_#/CS_B
Input during Parallel mode
configuration
Chip Select for Parallel Mode Configuration:
Possible input after configuration
if SelectMap port is retained
Otherwise, user I/O after
configuration
In Parallel (SelectMAP) modes, this is the active-Low Chip Select signal.
This pin becomes a user I/O after configuration unless the SelectMAP port
is retained via the Persist bitstream option.
IO_Lxxy_#/RDWR_B
Input during Parallel mode
configuration
Possible input after configuration
if SelectMap port is retained
Otherwise, user I/O after
configuration
Read/Write Control for Parallel Mode Configuration:
In Parallel (SelectMAP) modes, this is the active-Low Write Enable,
active-High Read Enable signal. This pin becomes a user I/O after
configuration unless the SelectMAP port is retained via the Persist
bitstream option.
IO_Lxxy_#/
BUSY/DOUT
Output during configuration
Possible output after
Configuration Data Rate Control for Parallel Mode, Serial Data
Output for Serial Mode:
configuration if SelectMap port is In Parallel (SelectMAP) modes, BUSY throttles the rate at which
retained
Otherwise, user I/O after
configuration
configuration data is loaded. This pin becomes a user I/O after
configuration unless the SelectMAP port is retained via the Persist
bitstream option.
In Serial modes, DOUT provides preamble and configuration data to
downstream devices in a multi-FPGA daisy-chain. This pin becomes a
user I/O after configuration.
IO_Lxxy_#/INIT_B
Bidirectional (open-drain) during
configuration
User I/O after configuration
Initializing Configuration Memory/Detected Configuration Error:
When Low, this pin indicates that configuration memory is being cleared.
When held Low, this pin delays the start of configuration. After this pin is
released or configuration memory is cleared, the pin goes High. During
configuration, a Low on this output indicates that a configuration data error
occurred. This pin always has an internal pull-up resistor to VCCO_4 or
VCCO_BOTTOM during configuration, regardless of the HSWAP_EN pin.
This pin becomes a user I/O after configuration.
DCI: Digitally Controlled Impedance reference resistor input pins
IO_Lxxy_#/VRN_# or
IO/VRN_#
Input when using DCI
Otherwise, same as I/O
DCI Reference Resistor for NMOS I/O Transistor (per bank):
If using DCI, a 1% precision impedance-matching resistor is connected
between this pin and the VCCO supply for this bank. Otherwise, this pin is
a user I/O.
IO_Lxxy_#/VRP_# or
IO/VRP_#
Input when using DCI
Otherwise, same as I/O
DCI Reference Resistor for PMOS I/O Transistor (per bank):
If using DCI, a 1% precision impedance-matching resistor is connected
between this pin and the ground supply. Otherwise, this pin is a user I/O.
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Spartan-3 FPGA Family: Pinout Descriptions
Description
Table 70: Spartan-3 FPGA Pin Definitions (Cont’d)
Pin Name
Direction
GCLK: Global clock buffer inputs
IO_Lxxy_#/GCLK0,
IO_Lxxy_#/GCLK1,
IO_Lxxy_#/GCLK2,
IO_Lxxy_#/GCLK3,
IO_Lxxy_#/GCLK4,
IO_Lxxy_#/GCLK5,
IO_Lxxy_#/GCLK6,
IO_Lxxy_#/GCLK7
Input if connected to global clock
buffers
Otherwise, same as I/O
Global Buffer Input:
Direct input to a low-skew global clock buffer. If not connected to a global
clock buffer, this pin is a user I/O.
VREF: I/O bank input reference voltage pins
IO_Lxxy_#/VREF_# or
IO/VREF_#
Voltage supply input when VREF Input Buffer Reference Voltage for Special I/O Standards (per
pins are used within a bank.
Otherwise, same as I/O
bank):
If required to support special I/O standards, all the VREF pins within a bank
connect to a input threshold voltage source.
If not used as input reference voltage pins, these pins are available as
individual user-I/O pins.
CONFIG: Dedicated configuration pins (pull-up resistor to VCCAUX always active during configuration, regardless of
HSWAP_EN pin)
CCLK
Input in Slave configuration
modes
Output in Master configuration
modes
Configuration Clock:
The configuration clock signal synchronizes configuration data. This pin
has an internal pull-up resistor to VCCAUX during configuration.
PROG_B
DONE
Input
Program/Configure Device:
Active Low asynchronous reset to configuration logic. Asserting PROG_B
Low for an extended period delays the configuration process. This pin has
an internal pull-up resistor to VCCAUX during configuration.
Bidirectional with open-drain or
totem-pole Output
Configuration Done, Delay Start-up Sequence:
A Low-to-High output transition on this bidirectional pin signals the end of
the configuration process.
The FPGA produces a Low-to-High transition on this pin to indicate that the
configuration process is complete. The DriveDone bitstream generation
option defines whether this pin functions as a totem-pole output that
actively drives High or as an open-drain output. An open-drain output
requires a pull-up resistor to produce a High logic level. The open-drain
option permits the DONE lines of multiple FPGAs to be tied together, so
that the common node transitions High only after all of the FPGAs have
completed configuration. Externally holding the open-drain output Low
delays the start-up sequence, which marks the transition to user mode.
M0, M1, M2
HSWAP_EN
Input
Input
Configuration Mode Selection:
These inputs select the configuration mode. The logic levels applied to the
mode pins are sampled on the rising edge of INIT_B. See Table 75. These
pins have an internal pull-up resistor to VCCAUX during configuration,
making Slave Serial the default configuration mode.
Disable Pull-up Resistors During Configuration:
A Low on this pin enables pull-up resistors on all pins that are not actively
involved in the configuration process. A High value disables all pull-ups,
allowing the non-configuration pins to float.
JTAG: JTAG interface pins (pull-up resistor to VCCAUX always active during configuration, regardless of HSWAP_EN
pin)
TCK
Input
JTAG Test Clock:
The TCK clock signal synchronizes all JTAG port operations. This pin has
an internal pull-up resistor to VCCAUX during configuration.
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Description
Table 70: Spartan-3 FPGA Pin Definitions (Cont’d)
Pin Name Direction
TDI
Input
JTAG Test Data Input:
TDI is the serial data input for all JTAG instruction and data registers. This
pin has an internal pull-up resistor to VCCAUX during configuration.
TMS
TDO
Input
JTAG Test Mode Select:
The serial TMS input controls the operation of the JTAG port. This pin has
an internal pull-up resistor to VCCAUX during configuration.
Output
JTAG Test Data Output:
TDO is the serial data output for all JTAG instruction and data registers.
This pin has an internal pull-up resistor to VCCAUX during configuration.
VCCO: I/O bank output voltage supply pins
VCCO_# Supply
Power Supply for Output Buffer Drivers (per bank):
These pins power the output drivers within a specific I/O bank.
VCCAUX: Auxiliary voltage supply pins
VCCAUX Supply
Power Supply for Auxiliary Circuits:
+2.5V power pins for auxiliary circuits, including the Digital Clock
Managers (DCMs), the dedicated configuration pins (CONFIG), and the
dedicated JTAG pins. All VCCAUX pins must be connected.
VCCINT: Internal core voltage supply pins
VCCINT Supply
Power Supply for Internal Core Logic:
+1.2V power pins for the internal logic. All pins must be connected.
GND: Ground supply pins
GND
Supply
Ground:
Ground pins, which are connected to the power supply’s return path. All
pins must be connected.
N.C.: Unconnected package pins
N.C.
Unconnected Package Pin:
These package pins are unconnected.
Notes:
1. All unused inputs and bidirectional pins must be tied either High or Low. For unused enable inputs, apply the level that disables the
associated function. One common approach is to activate internal pull-up or pull-down resistors. An alternative approach is to externally
connect the pin to either VCCO or GND.
2. All outputs are of the totem-pole type — i.e., they can drive High as well as Low logic levels — except for the cases where “Open Drain” is
indicated. The latter can only drive a Low logic level and require a pull-up resistor to produce a High logic level.
Detailed, Functional Pin Descriptions
I/O Type: Unrestricted, General-purpose I/O Pins
After configuration, I/O-type pins are inputs, outputs, bidirectional I/O, three-state outputs, open-drain outputs, or
open-source outputs, as defined in the application
Pins labeled "IO" support all SelectIO™ interface signal standards except differential standards. A given device at most only
has a few of these pins.
A majority of the general-purpose I/O pins are labeled in the format “IO_Lxxy_#”. These pins support all SelectIO signal
standards, including the differential standards such as LVDS, ULVDS, BLVDS, RSDS, or LDT.
For additional information, see IOBs, page 10
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Spartan-3 FPGA Family: Pinout Descriptions
Differential Pair Labeling
A pin supports differential standards if the pin is labeled in the format “Lxxy_#”. The pin name suffix has the following
significance. Figure 40 provides a specific example showing a differential input to and a differential output from Bank 2.
•
•
•
•
‘L’ indicates differential capability.
"xx" is a two-digit integer, unique for each bank, that identifies a differential pin-pair.
‘y’ is replaced by ‘P’ for the true signal or ‘N’ for the inverted. These two pins form one differential pin-pair.
‘#’ is an integer, 0 through 7, indicating the associated I/O bank.
If unused, these pins are in a high impedance state. The Bitstream generator option UnusedPin enables a pull-up or
pull-down resistor on all unused I/O pins.
Behavior from Power-On through End of Configuration
During the configuration process, all pins that are not actively involved in the configuration process are in a high-impedance
state. The CONFIG- and JTAG-type pins have an internal pull-up resistor to VCCAUX during configuration. For all other I/O
pins, the HSWAP_EN input determines whether or not pull-up resistors are activated during configuration. HSWAP_EN = 0
enables the pull-up resistors. HSWAP_EN = 1 disables the pull-up resistors allowing the pins to float, which is the desired
state for hot-swap applications.
X-Ref Target - Figure 40
Pair Number
Bank Number
Bank 0
Bank 1
IO_L38P_2
IO_L38N_2
Positive Polarity,
True Receiver
IO_L39P_2
IO_L39N_2
Negative Polarity,
Inverted Receiver
Bank 5
Bank 4
DS099-4_01_091710
Figure 40: Differential Pair Labelling
DUAL Type: Dual-Purpose Configuration and I/O Pins
These pins serve dual purposes. The user-I/O pins are temporarily borrowed during the configuration process to load
configuration data into the FPGA. After configuration, these pins are then usually available as a user I/O in the application.
If a pin is not applicable to the specific configuration mode—controlled by the mode select pins M2, M1, and M0—then the
pin behaves as an I/O-type pin.
There are 12 dual-purpose configuration pins on every package, six of which are part of I/O Bank 4, the other six part of I/O
Bank 5. Only a few of the pins in Bank 4 are used in the Serial configuration modes.
See Pin Behavior During Configuration, page 122.
Serial Configuration Modes
This section describes the dual-purpose pins used during either Master or Slave Serial mode. See Table 75 for Mode Select
pin settings required for Serial modes. All such pins are in Bank 4 and powered by VCCO_4.
In both the Master and Slave Serial modes, DIN is the serial configuration data input. The D1-D7 inputs are unused in serial
mode and behave like general-purpose I/O pins.
In all the cases, the configuration data is synchronized to the rising edge of the CCLK clock signal.
The DIN, DOUT, and INIT_B pins can be retained in the application to support reconfiguration by setting the Persist
bitstream generation option. However, the serial modes do not support device readback.
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Table 71: Dual-Purpose Pins Used in Master or Slave Serial Mode
Pin Name
DIN
Direction
Description
Input
Serial Data Input:
During the Master or Slave Serial configuration modes, DIN is the serial configuration data input, and
all data is synchronized to the rising CCLK edge. After configuration, this pin is available as a user I/O.
This signal is located in Bank 4 and its output voltage determined by VCCO_4.
The BitGen option Persist permits this pin to retain its configuration function in the User mode.
DOUT
INIT_B
Output
Serial Data Output:
In a multi-FPGA design where all the FPGAs use serial mode, connect the DOUT output of one
FPGA—in either Master or Slave Serial mode—to the DIN input of the next FPGA—in Slave Serial
mode—so that configuration data passes from one to the next, in daisy-chain fashion. This “daisy
chain” permits sequential configuration of multiple FPGAs.
This signal is located in Bank 4 and its output voltage determined by VCCO_4.
The BitGen option Persist permits this pin to retain its configuration function in the User mode.
Bidirectional Initializing Configuration Memory/Configuration Error:
(open-drain)
Just after power is applied, the FPGA produces a Low-to-High transition on this pin indicating that
initialization (i.e., clearing) of the configuration memory has finished. Before entering the User mode,
this pin functions as an open-drain output, which requires a pull-up resistor in order to produce a High
logic level. In a multi-FPGA design, tie (wire AND) the INIT_B pins from all FPGAs together so that the
common node transitions High only after all of the FPGAs have been successfully initialized.
Externally holding this pin Low beyond the initialization phase delays the start of configuration. This
action stalls the FPGA at the configuration step just before the mode select pins are sampled.
During configuration, the FPGA indicates the occurrence of a data (i.e., CRC) error by asserting
INIT_B Low.
This signal is located in Bank 4 and its output voltage determined by VCCO_4.
The BitGen option Persist permits this pin to retain its configuration function in the User mode.
X-Ref Target - Figure 41
I/O Bank 4 (VCCO_4)
High Nibble
I/O Bank 5 (VCCO_5)
Low Nibble
Configuration Data Byte
D0
1
D1
D2
D3
D4
D5
D6
D7
0
0xFC =
1
1
1
1
1
0
(MSB)
(LSB)
Figure 41: Configuration Data Byte Mapping to D0-D7 Bits
Parallel Configuration Modes (SelectMAP)
This section describes the dual-purpose configuration pins used during the Master and Slave Parallel configuration modes,
sometimes also called the SelectMAP modes. In both Master and Slave Parallel configuration modes, D0-D7 form the
byte-wide configuration data input. See Table 75 for Mode Select pin settings required for Parallel modes.
As shown in Figure 41, D0 is the most-significant bit while D7 is the least-significant bit. Bits D0-D3 form the high nibble of
the byte and bits D4-D7 form the low nibble.
In the Parallel configuration modes, both the VCCO_4 and VCCO_5 voltage supplies are required and must both equal the
voltage of the attached configuration device, typically either 2.5V or 3.3V.
Assert Low both the chip-select pin, CS_B, and the read/write control pin, RDWR_B, to write the configuration data byte
presented on the D0-D7 pins to the FPGA on a rising-edge of the configuration clock, CCLK. The order of CS_B and
RDWR_B does not matter, although RDWR_B must be asserted throughout the configuration process. If RDWR_B is
de-asserted during configuration, the FPGA aborts the configuration operation.
After configuration, these pins are available as general-purpose user I/O. However, the SelectMAP configuration interface is
optionally available for debugging and dynamic reconfiguration. To use these SelectMAP pins after configuration, set the
Persist bitstream generation option.
The Readback debugging option, for example, requires the Persist bitstream generation option. During Readback mode,
assert CS_B Low, along with RDWR_B High, to read a configuration data byte from the FPGA to the D0-D7 bus on a rising
CCLK edge. During Readback mode, D0-D7 are output pins.
In all the cases, the configuration data and control signals are synchronized to the rising edge of the CCLK clock signal.
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Table 72: Dual-Purpose Configuration Pins for Parallel (SelectMAP) Configuration Modes
Pin Name
Direction
Description
D0,
D1,
D2,
D3
•
•
Input during
configuration
Configuration Data Port (high nibble):
Collectively, the D0-D7 pins are the byte-wide configuration data port for the Parallel (SelectMAP)
Outputduring configuration modes. Configuration data is synchronized to the rising edge of CCLK clock signal.
readback
The D0-D3 pins are the high nibble of the configuration data byte and located in Bank 4 and powered by
VCCO_4.
The BitGen option Persist permits this pin to retain its configuration function in the User mode.
D4,
D5,
D6,
D7
•
•
Input during
configuration
Outputduring Bank 5 and powered by VCCO_5.
Configuration Data Port (low nibble):
The D4-D7 pins are the low nibble of the configuration data byte. However, these signals are located in
readback
The BitGen option Persist permits this pin to retain its configuration function in the User mode.
CS_B
Input
Chip Select for Parallel Mode Configuration:
Assert this pin Low, together with RDWR_B to write a configuration data byte from the D0-D7 bus to the
FPGA on a rising CCLK edge.
During Readback, assert this pin Low, along with RDWR_B High, to read a configuration data byte from
the FPGA to the D0-D7 bus on a rising CCLK edge.
This signal is located in Bank 5 and powered by VCCO_5.
The BitGen option Persist permits this pin to retain its configuration function in the User mode.
CS_B
Function
0
1
FPGA selected. SelectMAP inputs are valid on the next rising edge of CCLK.
FPGA deselected. All SelectMAP inputs are ignored.
RDWR_B
Input
Read/Write Control for Parallel Mode Configuration:
In Master and Slave Parallel modes, assert this pin Low together with CS_B to write a configuration data
byte from the D0-D7 bus to the FPGA on a rising CCLK edge. Once asserted during configuration,
RDWR_B must remain asserted until configuration is complete.
During Readback, assert this pin High with CS_B Low to read a configuration data byte from the FPGA
to the D0-D7 bus on a rising CCLK edge.
This signal is located in Bank 5 and powered by VCCO_5.
The BitGen option Persist permits this pin to retain its configuration function in the User mode.
RDWR_B
Function
0
1
If CS_B is Low, then load (write) configuration data to the FPGA.
This option is valid only if the Persist bitstream option is set to Yes. If CS_B is
Low, then read configuration data from the FPGA.
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Table 72: Dual-Purpose Configuration Pins for Parallel (SelectMAP) Configuration Modes (Cont’d)
Pin Name
Direction
Description
BUSY
Output
Configuration Data Rate Control for Parallel Mode:
In the Slave and Master Parallel modes, BUSY throttles the rate at which configuration data is loaded.
BUSY is only necessary if CCLK operates at greater than 50 MHz. Ignore BUSY for frequencies of 50
MHz and below.
When BUSY is Low, the FPGA accepts the next configuration data byte on the next rising CCLK edge for
which CS_B and RDWR_B are Low. When BUSY is High, the FPGA ignores the next configuration data
byte. The next configuration data value must be held or reloaded until the next rising CCLK edge when
BUSY is Low. When CS_B is High, BUSY is in a high impedance state.
BUSY
Function
0
1
The FPGA is ready to accept the next configuration data byte.
The FPGA is busy processing the current configuration data byte and is not
ready to accept the next byte.
Hi-Z
If CS_B is High, then BUSY is high impedance.
This signal is located in Bank 4 and its output voltage is determined by VCCO_4. The BitGen option
Persist permits this pin to retain its configuration function in the User mode.
INIT_B
Bidirectional
(open-drain)
Initializing Configuration Memory/Configuration Error (active-Low):
See description under Serial Configuration Modes, page 112.
JTAG Configuration Mode
In the JTAG configuration mode all dual-purpose configuration pins are unused and behave exactly like user-I/O pins, as
shown in Table 79. See Table 75 for Mode Select pin settings required for JTAG mode.
Dual-Purpose Pin I/O Standard During Configuration
During configuration, the dual-purpose pins default to CMOS input and output levels for the associated VCCO voltage
supply pins. For example, in the Parallel configuration modes, both VCCO_4 and VCCO_5 are required. If connected to
+2.5V, then the associated pins conform to the LVCMOS25 I/O standard. If connected to +3.3V, then the pins drive LVCMOS
output levels and accept either LVTTL or LVCMOS input levels.
Dual-Purpose Pin Behavior After Configuration
After the configuration process completes, these pins, if they were borrowed during configuration, become user-I/O pins
available to the application. If a dual-purpose configuration pin is not used during the configuration process—i.e., the parallel
configuration pins when using serial mode—then the pin behaves exactly like a general-purpose I/O. See I/O Type:
Unrestricted, General-purpose I/O Pins section.
DCI: User I/O or Digitally Controlled Impedance Resistor Reference Input
These pins are individual user-I/O pins unless one of the I/O standards used in the bank requires the Digitally Controlled
Impedance (DCI) feature. If DCI is used, then 1% precision resistors connected to the VRP_# and VRN_# pins match the
impedance on the input or output buffers of the I/O standards that use DCI within the bank. The ‘#’ character in the pin name
indicates the associated I/O bank and is an integer, 0 through 7.
There are two DCI pins per I/O bank, except in the CP132 and TQ144 packages, which do not have any DCI inputs for
Bank 5.
VRP and VRN Impedance Resistor Reference Inputs
The 1% precision impedance-matching resistor attached to the VRP_# pin controls the pull-up impedance of PMOS
transistor in the input or output buffer. Consequently, the VRP_# pin must connect to ground. The ‘P’ character in “VRP”
indicates that this pin controls the I/O buffer’s PMOS transistor impedance. The VRP_# pin is used for both single and split
termination.
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The 1% precision impedance-matching resistor attached to the VRN_# pin controls the pull-down impedance of NMOS
transistor in the input or output buffer. Consequently, the VRN_# pin must connect to VCCO. The ‘N’ character in “VRN”
indicates that this pin controls the I/O buffer’s NMOS transistor impedance. The VRN_# pin is only used for split termination.
Each VRN or VRP reference input requires its own resistor. A single resistor cannot be shared between VRN or VRP pins
associated with different banks.
During configuration, these pins behave exactly like user-I/O pins. The associated DCI behavior is not active or valid until
after configuration completes.
Also see Digitally Controlled Impedance (DCI), page 16.
DCI Termination Types
If the I/O in an I/O bank do not use the DCI feature, then no external resistors are required and both the VRP_# and VRN_#
pins are available for user I/O, as shown in section [a] of Figure 42.
If the I/O standards within the associated I/O bank require single termination—such as GTL_DCI, GTLP_DCI, or
HSTL_III_DCI—then only the VRP_# signal connects to a 1% precision impedance-matching resistor, as shown in section
[b] of Figure 42. A resistor is not required for the VRN_# pin.
Finally, if the I/O standards with the associated I/O bank require split termination—such as HSTL_I_DCI, SSTL2_I_DCI,
SSTL2_II_DCI, or LVDS_25_DCI and LVDSEXT_25_DCI receivers—then both the VRP_# and VRN_# pins connect to
separate 1% precision impedance-matching resistors, as shown in section [c] of Figure 42. Neither pin is available for user
I/O.
X-Ref Target - Figure 42
One of eight
I/O Banks
One of eight
I/O Banks
One of eight
I/O Banks
V
CCO
R
(1%)
(1%)
REF
User I/O
VRN
VRN
User I/O
VRP
VRP
R
(1%)
R
REF
REF
(a) No termination
(b) Single termination
(c) Split termination
DS099-4_03_091910
Figure 42: DCI Termination Types
GCLK: Global Clock Buffer Inputs or General-Purpose I/O Pins
These pins are user-I/O pins unless they specifically connect to one of the eight low-skew global clock buffers on the device,
specified using the IBUFG primitive.
There are eight GCLK pins per device and two each appear in the top-edge banks, Bank 0 and 1, and the bottom-edge
banks, Banks 4 and 5. See Figure 40 for a picture of bank labeling.
During configuration, these pins behave exactly like user-I/O pins.
Also see Global Clock Network, page 42.
CONFIG: Dedicated Configuration Pins
The dedicated configuration pins control the configuration process and are not available as user-I/O pins. Every package
has seven dedicated configuration pins. All CONFIG-type pins are powered by the +2.5V VCCAUX supply.
Also see Configuration, page 46.
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CCLK: Configuration Clock
The configuration clock signal on this pin synchronizes the reading or writing of configuration data. The CCLK pin is an
input-only pin for the Slave Serial and Slave Parallel configuration modes. In the Master Serial and Master Parallel
configuration modes, the FPGA drives the CCLK pin and CCLK should be treated as a full bidirectional I/O pin for signal
integrity analysis.
Although the CCLK frequency is relatively low, Spartan-3 FPGA output edge rates are fast. Any potential signal integrity
problems on the CCLK board trace can cause FPGA configuration to fail. Therefore, pay careful attention to the CCLK signal
integrity on the printed circuit board. Signal integrity simulation with IBIS is recommended. For all configuration modes
except JTAG, consider the signal integrity at every CCLK trace destination, including the FPGA’s CCLK pin. For more details
on CCLK design considerations, see Chapter 2 of UG332, Spartan-3 Generation Configuration User Guide.
During configuration, the CCLK pin has a pull-up resistor to VCCAUX, regardless of the HSWAP_EN pin. After configuration,
the CCLK pin is pulled High to VCCAUX by default as defined by the CclkPin bitstream selection, although this behavior is
programmable. Any clocks applied to CCLK after configuration are ignored unless the bitstream option Persist is set to Yes,
which retains the configuration interface. Persist is set to No by default. However, if Persist is set to Yes, then all clock
edges are potentially active events, depending on the other configuration control signals.
The bitstream generator option ConfigRate determines the frequency of the internally-generated CCLK oscillator required
for the Master configuration modes. The actual frequency is approximate due to the characteristics of the silicon oscillator
and varies by up to 50% over the temperature and voltage range. By default, CCLK operates at approximately 6 MHz. Via
the ConfigRate option, the oscillator frequency is set at approximately 3, 6, 12, 25, or 50 MHz. At power-on, CCLK always
starts operation at its lowest frequency. The device does not start operating at the higher frequency until the ConfigRate
control bits are loaded during the configuration process.
PROG_B: Program/Configure Device
This asynchronous pin initiates the configuration or re-configuration processes. A Low-going pulse resets the configuration
logic, initializing the configuration memory. This initialization process cannot finish until PROG_B returns High. Asserting
PROG_B Low for an extended period delays the configuration process. At power-up, there is always a pull-up resistor to
VCCAUX on this pin, regardless of the HSWAP_EN input. After configuration, the bitstream generator option ProgPin
determines whether or not the pull-up resistor is present. By default, the ProgPin option retains the pull-up resistor.
After configuration, hold the PROG_B input High. Any Low-going pulse on PROG_B lasting 300 ns or longer restarts the
configuration process.
Table 73: PROG_B Operation
PROG_B Input
Power-up
Response
Automatically initiates configuration process.
Low-going pulse
Initiate (re-)configuration process and continue to completion.
Extended Low
1
Initiate (re-)configuration process and stall process at step where configuration memory is cleared. Process is
stalled until PROG_B returns High.
If the configuration process is started, continue to completion. If configuration process is complete, stay in User
mode.
DONE: Configuration Done, Delay Start-Up Sequence
The FPGA produces a Low-to-High transition on this pin indicating that the configuration process is complete. The bitstream
generator option DriveDone determines whether this pin functions as a totem-pole output that can drive High or as an
open-drain output. If configured as an open-drain output—which is the default behavior—then a pull-up resistor is required
to produce a High logic level. There is a bitstream option that provides an internal pull-up resistor, otherwise an external
pull-up resistor is required.
The open-drain option permits the DONE lines of multiple FPGAs to be tied together, so that the common node transitions
High only after all of the FPGAs have completed configuration. Externally holding the open-drain DONE pin Low delays the
start-up sequence, which marks the transition to user mode.
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Once the FPGA enters User mode after completing configuration, the DONE pin no longer drives the DONE pin Low. The
bitstream generator option DonePin determines whether or not a pull-up resistor is present on the DONE pin to pull the pin
to VCCAUX. If the pull-up resistor is eliminated, then the DONE pin must be pulled High using an external pull-up resistor or
one of the FPGAs in the design must actively drive the DONE pin High via the DriveDone bitstream generator option.
The bitstream generator option DriveDone causes the FPGA to actively drive the DONE output High after configuration. This
option should only be used in single-FPGA designs or on the last FPGA in a multi-FPGA daisy-chain.
By default, the bitstream generator software retains the pull-up resistor and does not actively drive the DONE pin as
highlighted in Table 74, which shows the interaction of these bitstream options in single- and multi-FPGA designs.
Table 74: DonePin and DriveDone Bitstream Option Interaction
Single- or Multi-
FPGA Design
DonePin
DriveDone
Comments
Pullnone
Pullnone
No
No
Single
External pull-up resistor, with value between 330Ω to 3.3kΩ, required on DONE.
Multi
External pull-up resistor, with value between 330Ω to 3.3kΩ, required on common
node connecting to all DONE pins.
Pullnone
Pullnone
Pullup
Yes
Yes
No
Single
Multi
OK, no external requirements.
DriveDone on last device in daisy-chain only. No external requirements.
Single
OK, but pull-up on DONE pin has slow rise time. May require 330Ω pull-up resistor
for high CCLK frequencies.
Pullup
No
Multi
External pull-up resistor, with value between 330Ω to 3.3kΩ, required on common
node connecting to all DONE pins.
Pullup
Pullup
Yes
Yes
Single
Multi
OK, no external requirements.
DriveDone on last device in daisy-chain only. No external requirements.
M2, M1, M0: Configuration Mode Selection
The M2, M1, and M0 inputs select the FPGA configuration mode, as described in Table 75. The logic levels applied to the
mode pins are sampled on the rising edge of INIT_B.
Table 75: Spartan-3 FPGA Mode Select Settings
Configuration Mode
Master Serial
M2
0
M1
0
M0
0
Slave Serial
Master Parallel
Slave Parallel
JTAG
1
1
1
0
1
1
1
1
0
1
0
1
Reserved
0
0
1
Reserved
0
1
0
Reserved
1
0
0
After Configuration
X
X
X
Notes:
1. X = don’t care, either 0 or 1.
Before and during configuration, the mode pins have an internal pull-up resistor to VCCAUX, regardless of the HSWAP_EN
pin. If the mode pins are unconnected, then the FPGA defaults to the Slave Serial configuration mode. After configuration
successfully completes, any levels applied to these input are ignored. Furthermore, the bitstream generator options M0Pin,
M1Pin, and M2Pin determines whether a pull-up resistor, pull-down resistor, or no resistor is present on its respective mode
pin, M0, M1, or M2.
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HSWAP_EN: Disable Pull-up Resistors During Configuration
As shown in Table 76, a Low on this asynchronous pin enables pull-up resistors on all user I/Os not actively involved in the
configuration process, although only until device configuration completes. A High disables the pull-up resistors during
configuration, which is the desired state for some applications.
The dedicated configuration CONFIG pins (CCLK, DONE, PROG_B, HSWAP_EN, M2, M1, M0), the JTAG pins (TDI, TMS,
TCK, TDO) and the INIT_B always have active pull-up resistors during configuration, regardless of the value on
HSWAP_EN.
After configuration, HSWAP_EN becomes a "don’t care" input and any pull-up resistors previously enabled by HSWAP_EN
are disabled. If a user I/O in the application requires a pull-up resistor after configuration, place a PULLUP primitive on the
associated I/O pin or, for some pins, set the associated bitstream generator option.
Table 76: HSWAP_EN Encoding
HSWAP_EN
Function
During Configuration
0
Enable pull-up resistors on all pins not actively involved in the configuration process. Pull-ups are only active until
configuration completes. See Table 79.
1
No pull-up resistors during configuration.
After Configuration, User Mode
This pin has no function except during device configuration.
X
Notes:
1. X = don’t care, either 0 or 1.
The Bitstream generator option HswapenPin determines whether a pull-up resistor to VCCAUX, a pull-down resistor, or no
resistor is present on HSWAP_EN after configuration.
JTAG: Dedicated JTAG Port Pins
Table 77: JTAG Pin Descriptions
Pin Name
TCK
Direction
Description
Bitstream Generation Option
Input
Test Clock: The TCK clock signal synchronizes all boundary The BitGen option TckPin determines
scan operations on its rising edge.
whether a pull-up resistor, pull-down
resistor or no resistor is present.
TDI
Input
Test Data Input: TDI is the serial data input for all JTAG
instruction and data registers. This input is sampled on the
rising edge of TCK.
The BitGen option TdiPin determines
whether a pull-up resistor, pull-down
resistor or no resistor is present.
TMS
TDO
Input
Test Mode Select: The TMS input controls the sequence of
states through which the JTAG TAP state machine passes.
This input is sampled on the rising edge of TCK.
The BitGen option TmsPin determines
whether a pull-up resistor, pull-down
resistor or no resistor is present.
Output
Test Data Output: The TDO pin is the data output for all JTAG The BitGen option TdoPin determines
instruction and data registers. This output is sampled on the
rising edge of TCK. The TDO output is an active totem-pole
driver and is not like the open-collector TDO output on
Virtex®-II Pro FPGAs.
whether a pull-up resistor, pull-down
resistor or no resistor is present.
These pins are dedicated connections to the four-wire IEEE 1532/IEEE 1149.1 JTAG port, shown in Figure 43 and
described in Table 77. The JTAG port is used for boundary-scan testing, device configuration, application debugging, and
possibly an additional serial port for the application. These pins are dedicated and are not available as user-I/O pins. Every
package has four dedicated JTAG pins and these pins are powered by the +2.5V VCCAUX supply.
For additional information on JTAG configuration, see Boundary-Scan (JTAG) Mode, page 50.
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X-Ref Target - Figure 43
JTAG Port
TDI
Data In
TDO
Data Out
TMS
TCK
Mode Select
Clock
DS099_4_04_020811
Figure 43: JTAG Port
IDCODE Register
Spartan-3 FPGAs contain a 32-bit identification register called the IDCODE register, as defined in the IEEE 1149.1 JTAG
standard. The fixed value electrically identifies the manufacture (Xilinx) and the type of device being addressed over a JTAG
chain. This register allows the JTAG host to identify the device being tested or programmed via JTAG. See Table 78.
Using JTAG Port After Configuration
The JTAG port is always active and available before, during, and after FPGA configuration. Add the BSCAN_SPARTAN3
primitive to the design to create user-defined JTAG instructions and JTAG chains to communicate with internal logic.
Furthermore, the contents of the User ID register within the JTAG port can be specified as a Bitstream Generation option.
By default, the 32-bit User ID register contains 0xFFFFFFFF.
Table 78: Spartan-3 JTAG IDCODE Register Values (hexadecimal)
Part Number
IDCODE Register
0x0140C093
0x01414093
0x0141C093
0x01428093
0x01434093
0x01440093
0x01448093
0x01450093
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
Precautions When Using the JTAG Port in 3.3V Environments
The JTAG port is powered by the +2.5V VCCAUX power supply. When connecting to a 3.3V interface, the JTAG input pins
must be current-limited using a series resistor. Similarly, the TDO pin is a CMOS output powered from +2.5V. The TDO
output can directly drive a 3.3V input but with reduced noise immunity. See 3.3V-Tolerant Configuration Interface, page 47.
See also XAPP453: The 3.3V Configuration of Spartan-3 FPGAs for additional details.
The following interface precautions are recommended when connecting the JTAG port to a 3.3V interface.
•
Avoid actively driving the JTAG input signals High with 3.3V signal levels. If required in the application, use series
current-limiting resistors to keep the current below 10 mA per pin.
•
If possible, drive the FPGA JTAG inputs with drivers that can be placed in high-impedance (Hi-Z) after using the JTAG
port. Alternatively, drive the FPGA JTAG inputs with open-drain outputs, which only drive Low. In both cases, pull-up
resistors are required. The FPGA JTAG pins have pull-up resistors to VCCAUX before configuration and optional
pull-up resistors after configuration, controlled by Bitstream Options, page 125.
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VREF: User I/O or Input Buffer Reference Voltage for Special Interface Standards
These pins are individual user-I/O pins unless collectively they supply an input reference voltage, VREF_#, for any SSTL,
HSTL, GTL, or GTLP I/Os implemented in the associated I/O bank. The ‘#’ character in the pin name represents an integer,
0 through 7, that indicates the associated I/O bank.
The VREF function becomes active for this pin whenever a signal standard requiring a reference voltage is used in the
associated bank. If used as a user I/O, then each pin behaves as an independent I/O described in the I/O type section. If
used for a reference voltage within a bank, then all VREF pins within the bank must be connected to the same reference
voltage.
Spartan-3 devices are designed and characterized to support certain I/O standards when VREF is connected to +1.25V,
+1.10V, +1.00V, +0.90V, +0.80V, and +0.75V. During configuration, the VREF pins behave exactly like user-I/O pins.
If designing for footprint compatibility across the range of devices in a specific package, and if the VREF_# pins within a bank
connect to an input reference voltage, then also connect any N.C. (not connected) pins on the smaller devices in that
package to the input reference voltage. More details are provided later for each package type.
N.C. Type: Unconnected Package Pins
Pins marked as “N.C.” are unconnected for the specific device/package combination. For other devices in this same
package, this pin may be used as an I/O or VREF connection. In both the pinout tables and the footprint diagrams,
unconnected pins are noted with either a black diamond symbol () or a black square symbol ().
If designing for footprint compatibility across multiple device densities, check the pin types of the other Spartan-3 devices
available in the same footprint. If the N.C. pin matches to VREF pins in other devices, and the VREF pins are used in the
associated I/O bank, then connect the N.C. to the VREF voltage source.
VCCO Type: Output Voltage Supply for I/O Bank
Each I/O bank has its own set of voltage supply pins that determines the output voltage for the output buffers in the I/O bank.
Furthermore, for some I/O standards such as LVCMOS, LVCMOS25, LVTTL, etc., VCCO sets the input threshold voltage on
the associated input buffers.
Spartan-3 devices are designed and characterized to support various I/O standards for VCCO values of +1.2V, +1.5V, +1.8V,
+2.5V, and +3.3V.
Most VCCO pins are labeled as VCCO_# where the ‘#’ symbol represents the associated I/O bank number, an integer
ranging from 0 to 7. In the 144-pin TQFP package (TQ144) however, the VCCO pins along an edge of the device are
combined into a single VCCO input. For example, the VCCO inputs for Bank 0 and Bank 1 along the top edge of the package
are combined and relabeled VCCO_TOP. The bottom, left, and right edges are similarly combined.
In Serial configuration mode, VCCO_4 must be at a level compatible with the attached configuration memory or data source.
In Parallel configuration mode, both VCCO_4 and VCCO_5 must be at the same compatible voltage level.
All VCCO inputs to a bank must be connected together and to the voltage supply. Furthermore, there must be sufficient
supply decoupling to guarantee problem-free operation, as described in XAPP623: Power Distribution System (PDS)
Design: Using Bypass/Decoupling Capacitors.
VCCINT Type: Voltage Supply for Internal Core Logic
Internal core logic circuits such as the configurable logic blocks (CLBs) and programmable interconnect operate from the
VCCINT voltage supply inputs. VCCINT must be +1.2V.
All VCCINT inputs must be connected together and to the +1.2V voltage supply. Furthermore, there must be sufficient
supply decoupling to guarantee problem-free operation, as described in XAPP623.
VCCAUX Type: Voltage Supply for Auxiliary Logic
The VCCAUX pins supply power to various auxiliary circuits, such as to the Digital Clock Managers (DCMs), the JTAG pins,
and to the dedicated configuration pins (CONFIG type). VCCAUX must be +2.5V.
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All VCCAUX inputs must be connected together and to the +2.5V voltage supply. Furthermore, there must be sufficient
supply decoupling to guarantee problem-free operation, as described in XAPP623.
Because VCCAUX connects to the DCMs and the DCMs are sensitive to voltage changes, be sure that the VCCAUX supply
and the ground return paths are designed for low noise and low voltage drop, especially that caused by a large number of
simultaneous switching I/Os.
GND Type: Ground
All GND pins must be connected and have a low resistance path back to the various VCCO, VCCINT, and VCCAUX
supplies.
Pin Behavior During Configuration
Table 79 shows how various pins behave during the FPGA configuration process. The actual behavior depends on the
values applied to the M2, M1, and M0 mode select pins and the HSWAP_EN pin. The mode select pins determine which of
the DUAL type pins are active during configuration. In JTAG configuration mode, none of the DUAL-type pins are used for
configuration and all behave as user-I/O pins.
All DUAL-type pins not actively used during configuration and all I/O-type, DCI-type, VREF-type, GCLK-type pins are high
impedance (floating, three-stated, Hi-Z) during the configuration process. These pins are indicated in Table 79 as shaded
table entries or cells. These pins have a pull-up resistor to their associated VCCO if the HSWAP_EN pin is Low. When
HSWAP_EN is High, these pull-up resistors are disabled during configuration.
Some pins always have an active pull-up resistor during configuration, regardless of the value applied to the HSWAP_EN
pin. After configuration, these pull-up resistors are controlled by Bitstream Options.
•
All the dedicated CONFIG-type configuration pins (CCLK, PROG_B, DONE, M2, M1, M0, and HSWAP_EN) have a
pull-up resistor to VCCAUX.
•
•
All JTAG-type pins (TCK, TDI, TMS, TDO) have a pull-up resistor to VCCAUX.
The INIT_B DUAL-purpose pin has a pull-up resistor to VCCO_4 or VCCO_BOTTOM, depending on package style.
After configuration completes, some pins have optional behavior controlled by the configuration bitstream loaded into the
part. For example, via the bitstream, all unused I/O pins can be collectively configured as input pins with either a pull-up
resistor, a pull-down resistor, or be left in a high-impedance state.
Table 79: Pin Behavior After Power-Up, During Configuration
Configuration Mode Settings <M2:M1:M0>
Bitstream
Pin Name
Serial Modes
SelectMap Parallel Modes
Configuration
Option
JTAG Mode
<1:0:1>
Master <0:0:0> Slave <1:1:1>
Master <0:1:1>
Slave <1:1:0>
I/O: General-purpose I/O pins
IO
UnusedPin
UnusedPin
IO_Lxxy_#
DUAL: Dual-purpose configuration pins
IO_Lxxy_#/
DIN/D0
DIN (I)
DIN (I)
D0 (I/O)
D1 (I/O)
D2 (I/O)
D3 (I/O)
D4 (I/O)
D0 (I/O)
D1 (I/O)
D2 (I/O)
D3 (I/O)
D4 (I/O)
Persist UnusedPin
Persist UnusedPin
Persist UnusedPin
Persist UnusedPin
Persist UnusedPin
IO_Lxxy_#/
D1
IO_Lxxy_#/
D2
IO_Lxxy_#/
D3
IO_Lxxy_#/
D4
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Table 79: Pin Behavior After Power-Up, During Configuration (Cont’d)
Configuration Mode Settings <M2:M1:M0>
Serial Modes SelectMap Parallel Modes
Bitstream
Configuration
Option
Pin Name
JTAG Mode
<1:0:1>
Master <0:0:0>
Slave <1:1:1>
Master <0:1:1>
Slave <1:1:0>
IO_Lxxy_#/
D5
D5 (I/O)
D5 (I/O)
Persist UnusedPin
Persist UnusedPin
Persist UnusedPin
Persist UnusedPin
Persist UnusedPin
Persist UnusedPin
IO_Lxxy_#/
D6
D6 (I/O)
D7 (I/O)
D6 (I/O)
D7 (I/O)
IO_Lxxy_#/
D7
IO_Lxxy_#/
CS_B
CS_B (I)
CS_B (I)
IO_Lxxy_#/
RDWR_B
RDWR_B (I)
BUSY (O)
RDWR_B (I)
BUSY (O)
IO_Lxxy_#/
DOUT (O)
DOUT (O)
BUSY/DOUT
DUAL: Dual-purpose configuration pins (INIT_B has a pull-up resistor to VCCO_4 or VCCO_BOTTOM always active during
configuration, regardless of HSWAP_EN pin)
IO_Lxxy_#/
INIT_B
INIT_B (I/OD)
INIT_B (I/OD)
INIT_B (I/OD)
INIT_B (I/OD)
UnusedPin
DCI: Digitally Controlled Impedance reference resistor input pins
IO_Lxxy_#/
VRN_#
UnusedPin
IO/VRN_#
UnusedPin
UnusedPin
IO_Lxxy_#/
VRP_#
IO/VRP_#
UnusedPin
UnusedPin
GCLK: Global clock buffer inputs
IO_Lxxy_#/
GCLK0 through
GCLK7
VREF: I/O bank input reference voltage pins
IO_Lxxy_#/
VREF_#
UnusedPin
UnusedPin
IO/VREF_#
CONFIG: Dedicated configuration pins (pull-up resistor to VCCAUX always active during configuration, regardless of
HSWAP_EN pin)
CCLK
CCLK (I/O)
CCLK (I)
CCLK (I/O)
CCLK (I)
CclkPin ConfigRate
ProgPin
PROG_B
PROG_B (I)
(pull-up)
PROG_B (I)
(pull-up)
PROG_B (I)
(pull-up)
PROG_B (I)
(pull-up)
PROG_B (I), Via
JPROG_B
instruction
DONE
DONE (I/OD)
DONE (I/OD)
DONE (I/OD)
DONE (I/OD)
DONE (I/OD)
DriveDone
DonePin DonePipe
M2
M2=0 (I)
M1=0 (I)
M2=1 (I)
M1=1 (I)
M2=0 (I)
M1=1 (I)
M2=1 (I)
M1=1 (I)
M2=1 (I)
M1=0 (I)
M2Pin
M1Pin
M1
M0
M0=0 (I)
M0=1 (I)
M0=1 (I)
M0=0 (I)
M0=1 (I)
M0Pin
HSWAP_EN
HSWAP_EN (I)
HSWAP_EN (I)
HSWAP_EN (I)
HSWAP_EN (I)
HSWAP_EN (I)
HswapenPin
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Table 79: Pin Behavior After Power-Up, During Configuration (Cont’d)
Configuration Mode Settings <M2:M1:M0>
Serial Modes SelectMap Parallel Modes
Master <0:0:0> Slave <1:1:1> Master <0:1:1> Slave <1:1:0>
Bitstream
Configuration
Option
Pin Name
JTAG Mode
<1:0:1>
JTAG: JTAG interface pins (pull-up resistor to VCCAUX always active during configuration, regardless of HSWAP_EN pin)
TDI
TDI (I)
TMS (I)
TCK (I)
TDO (O)
TDI (I)
TMS (I)
TCK (I)
TDO (O)
TDI (I)
TMS (I)
TCK (I)
TDO (O)
TDI (I)
TMS (I)
TCK (I)
TDO (O)
TDI (I)
TMS (I)
TCK (I)
TDO (O)
TdiPin
TmsPin
TckPin
TdoPin
TMS
TCK
TDO
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Table 79: Pin Behavior After Power-Up, During Configuration (Cont’d)
Configuration Mode Settings <M2:M1:M0>
Serial Modes SelectMap Parallel Modes
Master <0:0:0> Slave <1:1:1> Master <0:1:1> Slave <1:1:0>
VCCO: I/O bank output voltage supply pins
Bitstream
Configuration
Option
Pin Name
JTAG Mode
<1:0:1>
VCCO_4
(for DUAL pins)
Same voltage as Same voltage as Same voltage as Same voltage as
external interface external interface external interface external interface
VCCO_4
VCCO_5
VCCO_#
N/A
N/A
N/A
VCCO_5
(for DUAL pins)
VCCO_5
VCCO_5
Same voltage as Same voltage as
external interface external interface
VCCO_#
VCCO_#
VCCO_#
VCCO_#
+2.5V
+1.2V
GND
VCCO_#
+2.5V
+1.2V
GND
VCCAUX: Auxiliary voltage supply pins
VCCAUX +2.5V
+2.5V
+2.5V
+1.2V
GND
N/A
N/A
N/A
VCCINT: Internal core voltage supply pins
VCCINT
+1.2V
+1.2V
GND: Ground supply pins
GND
GND
GND
Notes:
1. #= I/O bank number, an integer from 0 to 7.
2. (I) = input, (O) = output, (OD) = open-drain output, (I/O) = bidirectional, (I/OD) = bidirectional with open-drain output. Open-drain output
requires pull-up to create logic High level.
3.
Shaded cell indicates that the pin is high-impedance during configuration. To enable a soft pull-up resistor during configuration, drive or
tie HSWAP_EN Low.
Bitstream Options
Table 80 lists the various bitstream options that affect pins on a Spartan-3 FPGA. The table shows the names of the affected
pins, describes the function of the bitstream option, the name of the bitstream generator option variable, and the legal values
for each variable. The default option setting for each variable is indicated with bold, underlined text.
Table 80: Bitstream Options Affecting Spartan-3 Device Pins
Option
Values
Affected Pin Name(s)
Bitstream Generation Function
Variable
Name
(Default)
All unused I/O pins of
type I/O, DUAL, GCLK,
DCI, VREF
For all I/O pins that are unused in the application after configuration, this
option defines whether the I/Os are individually tied to VCCO via a pull-up
resistor, tied ground via a pull-down resistor, or left floating. If left floating,
the unused pins should be connected to a defined logic level, either from
a source internal to the FPGA or external.
UnusedPin
•
•
•
Pulldown
Pullup
Pullnone
IO_Lxxy_#/DIN,
IO_Lxxy_#/DOUT,
IO_Lxxy_#/INIT_B
Serial configuration mode: If set to Yes, then these pins retain their
functionality after configuration completes, allowing for device
(re-)configuration. Readback is not supported in with serial mode.
Persist
Persist
•
•
No
Yes
IO_Lxxy_#/D0,
IO_Lxxy_#/D1,
IO_Lxxy_#/D2,
IO_Lxxy_#/D3,
IO_Lxxy_#/D4,
IO_Lxxy_#/D5,
IO_Lxxy_#/D6,
IO_Lxxy_#/D7,
IO_Lxxy_#/CS_B,
IO_Lxxy_#/RDWR_B,
IO_Lxxy_#/BUSY,
IO_Lxxy_#/INIT_B
Parallel configuration mode (also called SelectMAP): If set to Yes, then
these pins retain their SelectMAP functionality after configuration
completes, allowing for device readback and for partial or complete
(re-)configuration.
•
•
No
Yes
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Table 80: Bitstream Options Affecting Spartan-3 Device Pins (Cont’d)
Option
Values
Variable
(Default)
Name
Affected Pin Name(s)
Bitstream Generation Function
CCLK
After configuration, this bitstream option either pulls CCLK to VCCAUX via
a pull-up resistor, or allows CCLK to float.
CclkPin
•
•
Pullup
Pullnone
CCLK
For Master configuration modes, this option sets the approximate
frequency, in MHz, for the internal silicon oscillator.
ConfigRate
ProgPin
•
3, 6, 12, 25,
50
PROG_B
A pull-up resistor to VCCAUX exists on PROG_B during configuration.
After configuration, this bitstream option either pulls PROG_B to VCCAUX
via a pull-up resistor, or allows PROG_B to float.
•
•
Pullup
Pullnone
DONE
DONE
After configuration, this bitstream option either pulls DONE to VCCAUX via
a pull-up resistor, or allows DONE to float. See also DriveDone option.
DonePin
•
•
Pullup
Pullnone
If set to Yes, this option allows the FPGA’s DONE pin to drive High when
configuration completes. By default, the DONE is an open-drain output
and can only drive Low. Only single FPGAs and the last FPGA in a
multi-FPGA daisy-chain should use this option.
DriveDone
•
•
No
Yes
M2
After configuration, this bitstream option either pulls M2 to VCCAUX via a
pull-up resistor, to ground via a pull-down resistor, or allows M2 to float.
M2Pin
M1Pin
•
•
•
Pullup
Pulldown
Pullnone
M1
After configuration, this bitstream option either pulls M1 to VCCAUX via a
pull-up resistor, to ground via a pull-down resistor, or allows M1 to float.
•
•
•
Pullup
Pulldown
Pullnone
M0
After configuration, this bitstream option either pulls M0 to VCCAUX via a
pull-up resistor, to ground via a pull-down resistor, or allows M0 to float.
M0Pin
•
•
•
Pullup
Pulldown
Pullnone
HSWAP_EN
TDI
After configuration, this bitstream option either pulls HSWAP_EN to
VCCAUX via a pull-up resistor, to ground via a pull-down resistor, or allows
HSWAP_EN to float.
HswapenPin
TdiPin
•
•
•
Pullup
Pulldown
Pullnone
After configuration, this bitstream option either pulls TDI to VCCAUX via a
pull-up resistor, to ground via a pull-down resistor, or allows TDI to float.
•
•
•
Pullup
Pulldown
Pullnone
TMS
TCK
TDO
After configuration, this bitstream option either pulls TMS to VCCAUX via
a pull-up resistor, to ground via a pull-down resistor, or allows TMS to float.
TmsPin
TckPin
•
•
•
Pullup
Pulldown
Pullnone
After configuration, this bitstream option either pulls TCK to VCCAUX via
a pull-up resistor, to ground via a pull-down resistor, or allows TCK to float.
•
•
•
Pullup
Pulldown
Pullnone
After configuration, this bitstream option either pulls TDO to VCCAUX via
a pull-up resistor, to ground via a pull-down resistor, or allows TDO to float.
TdoPin
•
•
•
Pullup
Pulldown
Pullnone
Setting Bitstream Generator Options
®
Refer to the “BitGen” chapter in the Xilinx ISE software documentation.
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Package Overview
Table 81 shows the 10 low-cost, space-saving production package styles for the Spartan-3 family. Each package style is
available as a standard and an environmentally-friendly lead-free (Pb-free) option. The Pb-free packages include an extra
‘G’ in the package style name. For example, the standard "VQ100" package becomes "VQG100" when ordered as the
Pb-free option. The mechanical dimensions of the standard and Pb-free packages are similar, as shown in the mechanical
drawings provided in Table 83.
Not all Spartan-3 device densities are available in all packages. However, for a specific package there is a common footprint
that supports the various devices available in that package. See the footprint diagrams that follow.
Table 81: Spartan-3 Family Package Options
Maximum
I/O
Pitch
(mm)
Footprint
(mm)
Height
(mm)
Package
Leads
Type
VQ100 / VQG100
CP132 / CPG132(1)
TQ144 / TQG144
PQ208 / PQG208
FT256 / FTG256
FG320 / FGG320
FG456 / FGG456
FG676 / FGG676
FG900 / FGG900
FG1156 / FGG1156(1)
100
132
144
208
256
320
456
676
900
1156
Very-thin Quad Flat Pack
Chip-Scale Package
63
89
0.5
0.5
0.5
0.5
1.0
1.0
1.0
1.0
1.0
1.0
16 x 16
8 x 8
1.20
1.10
1.60
4.10
1.55
2.00
2.60
2.60
2.60
2.60
Thin Quad Flat Pack
97
22 x 22
30.6 x 30.6
17 x 17
19 x 19
23 x 23
27 x 27
31 x 31
35 x 35
Quad Flat Pack
141
173
221
333
489
633
784
Fine-pitch, Thin Ball Grid Array
Fine-pitch Ball Grid Array
Fine-pitch Ball Grid Array
Fine-pitch Ball Grid Array
Fine-pitch Ball Grid Array
Fine-pitch Ball Grid Array
Notes:
1. The CP132, CPG132, FG1156, and FGG1156 packages are discontinued. See
http://www.xilinx.com/support/documentation/spartan-3_customer_notices.htm.
Selecting the Right Package Option
Spartan-3 FPGAs are available in both quad-flat pack (QFP) and ball grid array (BGA) packaging options. While QFP
packaging offers the lowest absolute cost, the BGA packages are superior in almost every other aspect, as summarized in
Table 82. Consequently, Xilinx recommends using BGA packaging whenever possible.
Table 82: Comparing Spartan-3 Device Packaging Options
Characteristic
Quad Flat-Pack (QFP)
Ball Grid Array (BGA)
Maximum User I/O
141
Good
Fair
633
Better
Better
Better
Better
6
Packing Density (Logic/Area)
Signal Integrity
Simultaneous Switching Output (SSO) Support
Thermal Dissipation
Limited
Fair
Minimum Printed Circuit Board (PCB) Layers
Hand Assembly/Rework
4
Possible
Very Difficult
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Mechanical Drawings
Detailed mechanical drawings for each package type are available from the Xilinx website at the specified location in
Table 83.
Material Declaration Data Sheets (MDDS) are also available on the Xilinx website for each package.
Table 83: Xilinx Package Mechanical Drawings
Package
VQ100 and VQG100
Web Link (URL)
http://www.xilinx.com/support/documentation/package_specs/vq100.pdf
http://www.xilinx.com/support/documentation/package_specs/cp132.pdf
http://www.xilinx.com/support/documentation/package_specs/tq144.pdf
http://www.xilinx.com/support/documentation/package_specs/pq208.pdf
http://www.xilinx.com/support/documentation/package_specs/ft256.pdf
http://www.xilinx.com/support/documentation/package_specs/fg320.pdf
http://www.xilinx.com/support/documentation/package_specs/fg456.pdf
http://www.xilinx.com/support/documentation/package_specs/fg676.pdf
http://www.xilinx.com/support/documentation/package_specs/fg900.pdf
http://www.xilinx.com/support/documentation/package_specs/fg1156.pdf
CP132 and CPG132(1)
TQ144 and TQG144
PQ208 and PQG208
FT256 and FTG256
FG320 and FGG320
FG456 and FGG456
FG676 and FGG676
FG900 and FGG900
FG1156 and FGG1156(1)
Notes:
1. The CP132, CPG132, FG1156, and FGG1156 packages are discontinued. See
http://www.xilinx.com/support/documentation/spartan-3_customer_notices.htm.
Power, Ground, and I/O by Package
Each package has three separate voltage supply inputs—VCCINT, VCCAUX, and VCCO—and a common ground return,
GND. The numbers of pins dedicated to these functions varies by package, as shown in Table 84.
Table 84: Power and Ground Supply Pins by Package
Package
VQ100
VCCINT
VCCAUX
VCCO
8
GND
10
4
4
4
4
CP132(1)
TQ144
PQ208
FT256
12
12
4
4
12
16
4
8
12
28
8
8
24
32
FG320
FG456
FG676
FG900
FG1156(1)
12
12
20
32
40
8
28
40
8
40
52
16
24
32
64
76
80
120
184
104
Notes:
1. The CP132, CPG132, FG1156, and FGG1156 packages are discontinued. See
http://www.xilinx.com/support/documentation/spartan-3_customer_notices.htm.
A majority of package pins are user-defined I/O pins. However, the numbers and characteristics of these I/O depends on the
device type and the package in which it is available, as shown in Table 85. The table shows the maximum number of
single-ended I/O pins available, assuming that all I/O-, DUAL-, DCI-, VREF-, and GCLK-type pins are used as
general-purpose I/O. Likewise, the table shows the maximum number of differential pin-pairs available on the package.
Finally, the table shows how the total maximum user I/Os are distributed by pin type, including the number of
unconnected—i.e., N.C.—pins on the device.
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Table 85: Maximum User I/Os by Package
Maximum
Differential
Pairs
All Possible I/O Pins by Type
N.C.
Maximum
User I/Os
Device
Package
I/O
DUAL
DCI
VREF
GCLK
XC3S50
VQ100
VQ100
CP132(1)
TQ144
TQ144
TQ144
PQ208
PQ208
PQ208
FT256
63
29
29
22
22
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
14
14
14
14
14
14
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
7
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
0
0
XC3S200
XC3S50
63
7
89
44
44
11
12
12
12
16
22
22
24
24
24
29
29
29
32
36
36
36
40
48
48
48
48
48
48
48
55
56
0
XC3S50
97
46
51
0
XC3S200
XC3S400
XC3S50
97
46
51
0
97
46
51
0
124
141
141
173
173
173
221
221
221
264
333
333
333
391
487
489
489
489
565
633
633
712
784
56
72
17
0
XC3S200
XC3S400
XC3S200
XC3S400
XC3S1000
XC3S400
XC3S1000
XC3S1500
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
XC3S2000
XC3S4000
XC3S5000
XC3S4000
XC3S5000
62
83
62
83
0
76
113
113
113
156
156
156
196
261
261
261
315
403
405
405
405
481
549
549
621
692
0
FT256
76
0
FT256
76
0
FG320
FG320
FG320
FG456
FG456
FG456
FG456
FG676
FG676
FG676
FG676
FG676
FG900
FG900
FG900
FG1156(1)
FG1156(1)
100
100
100
116
149
149
149
175
221
221
221
221
270
300
300
312
344
0
0
0
69
0
0
0
98
2
0
0
0
68
0
0
73
1
Notes:
1. The CP132, CPG132, FG1156, and FGG1156 packages are discontinued. See
http://www.xilinx.com/support/documentation/spartan-3_customer_notices.htm.
Electronic versions of the package pinout tables and footprints are available for download from the Xilinx website. Using a
spreadsheet program, the data can be sorted and reformatted according to any specific needs. Similarly, the ASCII-text file
is easily parsed by most scripting programs. Download the files from the following location:
http://www.xilinx.com/support/documentation/data_sheets/s3_pin.zip
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Spartan-3 FPGA Family: Pinout Descriptions
Package Thermal Characteristics
The power dissipated by an FPGA application has implications on package selection and system design. The power
consumed by a Spartan-3 FPGA is reported using either the XPower Estimator (XPE) or the XPower Analyzer integrated in
the Xilinx ISE development software. Table 86 provides the thermal characteristics for the various Spartan-3 device/package
offerings.
The junction-to-case thermal resistance (θ ) indicates the difference between the temperature measured on the package
JC
body (case) and the die junction temperature per watt of power consumption. The junction-to-board (θ ) value similarly
JB
reports the difference between the board and junction temperature. The junction-to-ambient (θ ) value reports the
JA
temperature difference per watt between the ambient environment and the junction temperature. The θ value is reported
JA
at different air velocities, measured in linear feet per minute (LFM). The “Still Air (0 LFM)” column shows the θ value in a
JA
system without a fan. The thermal resistance drops with increasing air flow.
Table 86: Spartan-3 FPGA Package Thermal Characteristics
Junction-to-Ambient (θJA) at Different Air Flows
Junction-to-
Junction-to-B
oard (θJB)
Package
Device
Units
Still Air
(0 LFM)
Case (θJC
)
250 LFM
500 LFM
750 LFM
XC3S50
XC3S200
XC3S50
12.0
10.0
14.5
7.6
6.6
6.1
10.6
8.6
7.5
9.9
7.9
5.6
8.9
7.8
6.7
8.4
6.4
4.9
3.7
6.0
4.9
4.1
3.6
3.4
3.7
3.3
2.9
–
–
46.2
40.5
53.0
41.0
34.5
32.8
37.4
36.2
35.4
31.7
28.4
24.8
24.4
22.3
20.3
20.8
19.3
18.3
17.7
17.9
16.8
15.6
15.0
14.7
14.3
13.6
13.1
38.4
33.7
46.4
31.9
26.9
25.5
27.6
26.7
26.1
25.6
22.8
19.2
19.0
17.0
15.18
15.1
13.4
12.4
11.7
13.7
12.4
11.1
10.5
10.3
10.3
9.7
35.8
31.3
44.0
27.2
23.0
21.8
24.4
23.6
23.1
24.5
21.5
18.0
17.8
15.8
13.8
13.9
12.3
11.2
10.5
12.6
11.3
9.9
34.9
30.5
42.5
25.6
21.6
20.4
22.6
21.9
21.4
24.2
21.0
17.5
17.0
15.0
13.1
13.4
11.7
10.7
10.0
12.0
10.7
9.3
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
VQ(G)100
CP(G)132(1)
32.8
–
XC3S50
TQ(G)144
PQ(G)208
FT(G)256
FG(G)320
XC3S200
XC3S400
XC3S50
–
–
–
XC3S200
XC3S400
XC3S200
XC3S400
XC3S1000
XC3S400
XC3S1000
XC3S1500
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
XC3S2000
XC3S4000
XC3S5000
–
–
22.9
19.0
14.7
13.9
11.8
9.8
13.6
10.6
8.3
6.5
10.4
8.8
7.9
7.0
6.3
7.0
6.4
5.9
FG(G)456
FG(G)676
FG(G)900
9.3
8.7
9.1
8.5
9.3
8.8
8.7
8.2
9.2
8.1
7.6
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Table 86: Spartan-3 FPGA Package Thermal Characteristics (Cont’d)
Junction-to-Ambient (θJA) at Different Air Flows
Junction-to-
Junction-to-B
oard (θJB)
Package
Device
Units
Still Air
Case (θJC
)
250 LFM
500 LFM
750 LFM
(0 LFM)
XC3S4000
XC3S5000
1.9
1.9
–
14.7
11.4
11.3
10.1
10.0
9.0
8.9
°C/Watt
°C/Watt
FG(G)1156(1)
8.9
14.5
Notes:
1. The CP132, CPG132, FG1156, and FGG1156 packages are discontinued. See
http://www.xilinx.com/support/documentation/spartan-3_customer_notices.htm.
VQ100: 100-lead Very-Thin Quad Flat Package
The XC3S50 and the XC3S200 devices are available in the 100-lead very-thin quad flat package, VQ100. Both devices
share a common footprint for this package as shown in Table 87 and Figure 44.
All the package pins appear in Table 87 and are sorted by bank number, then by pin name. Pairs of pins that form a
differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type, as
defined earlier.
An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at
http://www.xilinx.com/support/documentation/data_ sheets/s3_pin.zip.
Pinout Table
Table 87: VQ100 Package Pinout
XC3S50
XC3S200
Pin Name
VQ100
Pin
Number
Bank
Type
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
2
2
2
2
2
IO_L01N_0/VRP_0
IO_L01P_0/VRN_0
IO_L31N_0
P97
P96
P92
P91
P90
P89
P94
P81
P80
P79
P86
P85
P88
P87
P83
P75
P74
P72
P71
P68
P67
DCI
DCI
I/O
IO_L31P_0/VREF_0
IO_L32N_0/GCLK7
IO_L32P_0/GCLK6
VCCO_0
VREF
GCLK
GCLK
VCCO
I/O
IO
IO_L01N_1/VRP_1
IO_L01P_1/VRN_1
IO_L31N_1/VREF_1
IO_L31P_1
DCI
DCI
VREF
I/O
IO_L32N_1/GCLK5
IO_L32P_1/GCLK4
VCCO_1
GCLK
GCLK
VCCO
DCI
IO_L01N_2/VRP_2
IO_L01P_2/VRN_2
IO_L21N_2
DCI
I/O
IO_L21P_2
I/O
IO_L24N_2
I/O
IO_L24P_2
I/O
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Table 87: VQ100 Package Pinout (Cont’d)
XC3S50
XC3S200
Pin Name
VQ100
Bank
Pin
Type
Number
2
2
2
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
IO_L40N_2
P65
P64
P70
P55
P59
P54
P53
P61
P60
P63
P62
P57
P50
P49
P48
P47
P44
P43
P42
P40
P39
P38
P46
P28
P27
P32
P30
P35
P34
P37
P36
P31
P17
P21
P23
P22
P16
P15
P14
I/O
VREF
VCCO
I/O
IO_L40P_2/VREF_2
VCCO_2
IO
IO
I/O
IO_L01N_3/VRP_3
IO_L01P_3/VRN_3
IO_L24N_3
DCI
DCI
I/O
IO_L24P_3
I/O
IO_L40N_3/VREF_3
IO_L40P_3
VREF
I/O
VCCO_3
VCCO
DCI
IO_L01N_4/VRP_4
IO_L01P_4/VRN_4
IO_L27N_4/DIN/D0
IO_L27P_4/D1
IO_L30N_4/D2
IO_L30P_4/D3
IO_L31N_4/INIT_B
IO_L31P_4/DOUT/BUSY
IO_L32N_4/GCLK1
IO_L32P_4/GCLK0
VCCO_4
DCI
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
GCLK
GCLK
VCCO
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
GCLK
GCLK
VCCO
I/O
IO_L01N_5/RDWR_B
IO_L01P_5/CS_B
IO_L28N_5/D6
IO_L28P_5/D7
IO_L31N_5/D4
IO_L31P_5/D5
IO_L32N_5/GCLK3
IO_L32P_5/GCLK2
VCCO_5
IO
IO
I/O
IO_L01N_6/VRP_6
IO_L01P_6/VRN_6
IO_L24N_6/VREF_6
IO_L24P_6
DCI
DCI
VREF
I/O
IO_L40N_6
I/O
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Table 87: VQ100 Package Pinout (Cont’d)
XC3S50
XC3S200
Pin Name
VQ100
Bank
Pin
Type
Number
6
IO_L40P_6/VREF_6
VCCO_6
IO_L01N_7/VRP_7
IO_L01P_7/VRN_7
IO_L21N_7
IO_L21P_7
IO_L23N_7
IO_L23P_7
IO_L40N_7/VREF_7
IO_L40P_7
VCCO_7
GND
P13
P19
P2
VREF
VCCO
DCI
6
7
7
P1
DCI
7
P5
I/O
7
P4
I/O
7
P9
I/O
7
P8
I/O
7
P12
P11
P6
VREF
I/O
7
7
VCCO
GND
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
P3
GND
P10
P20
P29
P41
P56
P66
P73
P82
P95
P7
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
JTAG
P33
P58
P84
P18
P45
P69
P93
P52
P51
P98
P25
P24
P26
P99
P77
P100
VCCINT
VCCINT
VCCINT
VCCAUX CCLK
VCCAUX DONE
VCCAUX HSWAP_EN
VCCAUX M0
VCCAUX M1
VCCAUX M2
VCCAUX PROG_B
VCCAUX TCK
VCCAUX TDI
JTAG
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Spartan-3 FPGA Family: Pinout Descriptions
Table 87: VQ100 Package Pinout (Cont’d)
XC3S50
XC3S200
Pin Name
VQ100
Bank
Pin
Type
Number
VCCAUX TDO
VCCAUX TMS
P76
P78
JTAG
JTAG
User I/Os by Bank
Table 88 indicates how the available user-I/O pins are distributed between the eight I/O banks on the VQ100 package.
Table 88: User I/Os Per Bank in VQ100 Package
All Possible I/O Pins by Type
Package Edge
Top
I/O Bank
Maximum I/O
I/O
1
DUAL
DCI
2
VREF
GCLK
0
1
2
3
4
5
6
7
6
7
0
0
0
0
6
6
0
0
1
1
1
1
0
0
2
1
2
2
0
0
2
2
0
0
2
2
8
5
2
Right
8
5
2
10
8
0
2
Bottom
Left
0
0
8
4
2
8
5
2
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VQ100 Footprint
X-Ref Target - Figure 44
IO_L01P_7/VRN_7
1
2
75 IO_L01N_2/VRP_2
Bank 0
Bank 1
74 IO_L01P_2/VRN_2
73 GND
IO_L01N_7/VRP_7
GND
3
IO_L21P_7
IO_L21N_7
4
72 IO_L21N_2
71 IO_L21P_2
70 VCCO_2
5
6
VCCO_7
VCCAUX
7
69 VCCINT
IO_L23P_7
IO_L23N_7
8
68 IO_L24N_2
67 IO_L24P_2
66 GND
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
GND
IO_L40P_7
65 IO_L40N_2
64 IO_L40P_2/VREF_2
63 IO_L40N_3/VREF_3
62 IO_L40P_3
61 IO_L24N_3
60 IO_L24P_3
59 IO
IO_L40N_7/VREF_7
IO_L40P_6/VREF_6
IO_L40N_6
IO_L24P_6
IO_L24N_6/VREF_6
IO
VCCINT
58 VCCAUX
57 VCCO_3
VCCO_6
56 GND
GND
55 IO
IO
IO_L01P_6/VRN_6
54 IO_L01N_3/VRP_3
53 IO_L01P_3/VRN_3
52 CCLK
IO_L01N_6/VRP_6
M1
M0
Bank 5
Bank 4
no VREF, no DCI)
(no VREF)
(
51 DONE
DS099-4_15_042303
Figure 44: VQ100 Package Footprint (Top View). Note pin 1 indicator in top-left corner and logo orientation.
DUAL: Configuration pin, then possible
VREF: User I/O or input voltage reference for
22 I/O: Unrestricted, general-purpose user I/O
12
8
7
8
4
4
user I/O
bank
DCI: User I/O or reference resistor input for
GCLK: User I/O or global clock buffer
input
14
7
VCCO: Output voltage supply for bank
VCCINT: Internal core voltage supply (+1.2V)
VCCAUX: Auxiliary voltage supply (+2.5V)
bank
CONFIG: Dedicated configuration pins
4
JTAG: Dedicated JTAG port pins
0
N.C.: No unconnected pins in this package
10 GND: Ground
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Spartan-3 FPGA Family: Pinout Descriptions
CP132: 132-Ball Chip-Scale Package
Note: The CP132 and CPG132 packages are discontinued. See
www.xilinx.com/support/documentation/spartan-3.htm#19600.
The pinout and footprint for the XC3S50 in the 132-ball chip-scale package, CP132, appear in Table 89 and Figure 45.
All the package pins appear in Table 89 and are sorted by bank number, then by pin name. Pins that form a differential I/O
pair appear together in the table. The table also shows the pin number for each pin and the pin type, as defined earlier.
The CP132 footprint has eight I/O banks. However, the voltage supplies for the two I/O banks along an edge are connected
together internally. Consequently, there are four output voltage supplies, labeled VCCO_TOP, VCCO_RIGHT,
VCCO_BOTTOM, and VCCO_LEFT.
Pinout Table
Table 89: CP132 Package Pinout
CP132
Ball
Bank
XC3S50 Pin Name
Type
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
IO_L01N_0/VRP_0
IO_L01P_0/VRN_0
IO_L27N_0
A3
DCI
DCI
I/O
C4
C5
IO_L27P_0
B5
I/O
IO_L30N_0
B6
I/O
IO_L30P_0
A6
I/O
IO_L31N_0
C7
I/O
IO_L31P_0/VREF_0
IO_L32N_0/GCLK7
IO_L32P_0/GCLK6
IO_L01N_1/VRP_1
IO_L01P_1/VRN_1
IO_L27N_1
B7
VREF
GCLK
GCLK
DCI
DCI
I/O
A7
C8
A13
B13
C11
A12
A11
B11
C9
IO_L27P_1
I/O
IO_L28N_1
I/O
IO_L28P_1
I/O
IO_L31N_1/VREF_1
IO_L31P_1
VREF
I/O
A10
A8
IO_L32N_1/GCLK5
IO_L32P_1/GCLK4
IO_L01N_2/VRP_2
IO_L01P_2/VRN_2
IO_L20N_2
GCLK
GCLK
DCI
DCI
I/O
A9
D12
C14
E12
E13
E14
F12
F13
F14
G12
IO_L20P_2
I/O
IO_L21N_2
I/O
IO_L21P_2
I/O
IO_L23N_2/VREF_2
IO_L23P_2
VREF
I/O
IO_L24N_2
I/O
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Spartan-3 FPGA Family: Pinout Descriptions
Table 89: CP132 Package Pinout (Cont’d)
CP132
Ball
Bank
XC3S50 Pin Name
IO_L24P_2
Type
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
6
6
6
6
G13
G14
H12
N13
N14
L12
M14
L14
L13
K13
K12
J12
K14
H14
J13
N12
P12
M11
M10
N10
N9
I/O
I/O
IO_L40N_2
IO_L40P_2/VREF_2
IO_L01N_3/VRP_3
IO_L01P_3/VRN_3
IO_L20N_3
VREF
DCI
DCI
I/O
IO_L20P_3
I/O
IO_L22N_3
I/O
IO_L22P_3
I/O
IO_L23N_3
I/O
IO_L23P_3/VREF_3
IO_L24N_3
VREF
I/O
IO_L24P_3
I/O
IO_L40N_3/VREF_3
IO_L40P_3
VREF
I/O
IO/VREF_4
VREF
DCI
IO_L01N_4/VRP_4
IO_L01P_4/VRN_4
IO_L27N_4/DIN/D0
IO_L27P_4/D1
IO_L30N_4/D2
IO_L30P_4/D3
IO_L31N_4/INIT_B
IO_L31P_4/DOUT/BUSY
IO_L32N_4/GCLK1
IO_L32P_4/GCLK0
IO_L01N_5/RDWR_B
IO_L01P_5/CS_B
IO_L27N_5/VREF_5
IO_L27P_5
DCI
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
GCLK
GCLK
DUAL
DUAL
VREF
I/O
P9
M8
N8
P8
M7
P2
N2
M4
P3
IO_L28N_5/D6
IO_L28P_5/D7
IO_L31N_5/D4
IO_L31P_5/D5
IO_L32N_5/GCLK3
IO_L32P_5/GCLK2
IO_L01N_6/VRP_6
IO_L01P_6/VRN_6
IO_L20N_6
P4
DUAL
DUAL
DUAL
DUAL
GCLK
GCLK
DCI
N4
M6
P5
P7
P6
L3
M1
DCI
K3
I/O
IO_L20P_6
K2
I/O
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Spartan-3 FPGA Family: Pinout Descriptions
Table 89: CP132 Package Pinout (Cont’d)
CP132
Ball
Bank
XC3S50 Pin Name
IO_L22N_6
Type
6
6
K1
J3
I/O
I/O
IO_L22P_6
IO_L23N_6
IO_L23P_6
IO_L24N_6/VREF_6
IO_L24P_6
IO_L40N_6
IO_L40P_6/VREF_6
IO_L01N_7/VRP_7
IO_L01P_7/VRN_7
IO_L21N_7
IO_L21P_7
IO_L22N_7
IO_L22P_7
IO_L23N_7
IO_L23P_7
IO_L24N_7
IO_L24P_7
IO_L40N_7/VREF_7
IO_L40P_7
VCCO_TOP
VCCO_TOP
VCCO_TOP
VCCO_RIGHT
VCCO_RIGHT
VCCO_RIGHT
VCCO_BOTTOM
VCCO_BOTTOM
VCCO_BOTTOM
VCCO_LEFT
VCCO_LEFT
VCCO_LEFT
GND
6
J2
I/O
6
J1
I/O
6
H3
H2
H1
G3
B2
VREF
I/O
6
6
I/O
6
VREF
DCI
7
7
B1
DCI
7
C1
D3
D1
D2
E2
I/O
7
I/O
7
I/O
7
I/O
7
I/O
7
E3
I/O
7
F3
I/O
7
E1
I/O
7
G1
F2
VREF
I/O
7
0,1
0,1
0,1
2,3
2,3
2,3
4,5
4,5
4,5
6,7
6,7
6,7
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
B12
A4
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
GND
GND
GND
GND
GND
GND
GND
GND
B8
D13
H13
M12
N7
P11
N3
G2
L2
C3
B4
GND
B9
GND
C2
C12
D14
F1
GND
GND
GND
GND
J14
L1
GND
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Spartan-3 FPGA Family: Pinout Descriptions
Table 89: CP132 Package Pinout (Cont’d)
CP132
Ball
Bank
XC3S50 Pin Name
GND
Type
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
M3
M13
N6
GND
GND
GND
GND
GND
GND
N11
A5
GND
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
JTAG
C10
M5
P10
B10
C6
M9
N5
VCCAUX CCLK
VCCAUX DONE
VCCAUX HSWAP_EN
VCCAUX M0
P14
P13
B3
N1
VCCAUX M1
M2
P1
VCCAUX M2
VCCAUX PROG_B
VCCAUX TCK
VCCAUX TDI
A2
B14
A1
JTAG
VCCAUX TDO
VCCAUX TMS
C13
A14
JTAG
JTAG
User I/Os by Bank
Table 90 indicates how the 89 available user-I/O pins are distributed between the eight I/O banks on the CP132 package.
There are only four output banks, each with its own VCCO voltage input.
Table 90: User I/Os Per Bank for XC3S50 in CP132 Package
All Possible I/O Pins by Type
Package Edge
Top
I/O Bank
Maximum I/O
I/O
5
DUAL
DCI
2
VREF
GCLK
0
1
2
3
4
5
6
7
10
10
12
12
11
10
12
12
0
0
0
0
6
6
0
0
1
1
2
2
1
1
2
1
2
2
0
0
2
2
0
0
5
2
8
2
Right
8
2
0
2
Bottom
Left
1
0
8
2
9
2
Notes:
1. The CP132 and CPG132 packages are discontinued. See www.xilinx.com/support/documentation/spartan-3.htm#19600.
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Spartan-3 FPGA Family: Pinout Descriptions
CP132 Footprint
X-Ref Target - Figure 45
VCCO_TOP for Top Edge Outputs
Bank 0
5
Bank 1
1
2
3
4
6
7
8
9
10
11
12
13
14
I/O
L32N_0
GCLK7
I/O
L32N_1
GCLK5
I/O
L32P_1
GCLK4
I/O
L01N_0
VRP_0
I/O
L01N_1
VRP_1
VCCO_
TOP
I/O
L30P_0
I/O
L31P_1
I/O
L28N_1
I/O
L27P_1
PROG_B
VCCAUX
TDI
TMS
A
B
C
D
E
F
I/O
I/O
L01N_7
VRP_7
I/O
L31P_0
VREF_0
I/O
L01P_1
VRN_1
VCCO_
TOP
VCCO_
TOP
HSWAP_
EN
I/O
L27P_0
I/O
L30N_0
I/O
L28P_1
GND
GND
VCCINT
TCK
L01P_7
VRN_7
I/O
L01P_2
VRN_2
I/O
L32P_0
GCLK6
I/O
L31N_1
VREF_1
I/O
L01P_0
VRN_0
VCCO_
LEFT
I/O
L21N_7
I/O
L27N_0
I/O
L31N_0
I/O
L27N_1
GND
VCCINT
VCCAUX
TDO
GND
I/O
L01N_2
VRP_2
VCCO_
RIGHT
I/O
L22N_7
I/O
L22P_7
I/O
L21P_7
GND
I/O
L23N_7
I/O
L23P_7
I/O
L24P_7
I/O
L20N_2
I/O
L20P_2
I/O
L21N_2
I/O
L23N_2
VREF_2
I/O
L40P_7
I/O
L24N_7
I/O
L21P_2
I/O
L23P_2
GND
I/O
L40N_7
VREF_7
I/O
L40P_6
VREF_6
I/O
L24N_2
I/O
L24P_2
I/O
L40N_2
VCCO_
LEFT
G
H
J
I/O
L24N_6
VREF_6
I/O
L40P_2
VREF_2
I/O
L40N_3
VREF_3
VCCO_
RIGHT
I/O
L40N_6
I/O
L24P_6
I/O
L24N_3
I/O
L40P_3
I/O
L23P_6
I/O
L23N_6
I/O
L22P_6
GND
I/O
L23P_3
VREF_3
I/O
L23N_3
I/O
L24P_3
I/O
L22N_6
I/O
L20P_6
I/O
L20N_6
K
L
I/O
L01N_6
VRP_6
VCCO_
LEFT
I/O
L20N_3
I/O
L22P_3
I/O
L22N_3
GND
I/O
L27N_4
DIN
I/O
L32P_4
GCLK0
I/O
L01P_6
VRN_6
I/O
I/O
L31N_5
D4
I/O
L31N_4
INIT_B
VCCO_
RIGHT
GND
GND
VCCINT
M1
L27N_5 VCCAUX
VREF_5
M
N
P
L01P_4
VRN_4
L20P_3
D0
I/O
I/O
L01P_5
CS_B
I/O
L28P_5
D7
I/O
L30N_4
D2
I/O
L27P_4
D1
I/O
L01N_3
VRP_3
I/O
L01P_3
VRN_3
VCCO_
BOTTOM
VCCO_
BOTTOM
L31P_4
DOUT
BUSY
I/O
VREF_4
VCCINT
GND
GND
M0
M2
I/O
L01N_5
RDWR_B
I/O
L28N_5
D6
I/O
L31P_5
D5
I/O
L32P_5
GCLK2
I/O
L32N_5
GCLK3
I/O
L32N_4
GCLK1
I/O
L30P_4
D3
I/O
L01N_4
VRP_4
VCCO_
BOTTOM
I/O
L27P_5
VCCAUX
DONE
CCLK
Bank 5
VCCO_BOTTOM for Bottom Edge Outputs
Bank 4
DS099-4_17_011005
Figure 45: CP132 Package Footprint (Top View). Note pin 1 indicator in top-left corner and logo orientation.
DUAL: Configuration pin, then possible
VREF: User I/O or input voltage reference for
44 I/O: Unrestricted, general-purpose user I/O
12
8
11
user I/O
bank
DCI: User I/O or reference resistor input for
GCLK: User I/O, input, or global buffer
input
14
12 VCCO: Output voltage supply for bank
bank
7
0
CONFIG: Dedicated configuration pins
4
JTAG: Dedicated JTAG port pins
4
4
VCCINT: Internal core voltage supply (+1.2V)
VCCAUX: Auxiliary voltage supply (+2.5V)
N.C.: No unconnected pins in this package
12 GND: Ground
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Spartan-3 FPGA Family: Pinout Descriptions
TQ144: 144-lead Thin Quad Flat Package
The XC3S50, the XC3S200, and the XC3S400 are available in the 144-lead thin quad flat package, TQ144. All devices
share a common footprint for this package as shown in Table 91 and Figure 46.
The TQ144 package only has four separate VCCO inputs, unlike the BGA packages, which have eight separate VCCO
inputs. The TQ144 package has a separate VCCO input for the top, bottom, left, and right. However, there are still eight
separate I/O banks, as shown in Table 91 and Figure 46. Banks 0 and 1 share the VCCO_TOP input, Banks 2 and 3 share
the VCCO_RIGHT input, Banks 4 and 5 share the VCCO_BOTTOM input, and Banks 6 and 7 share the VCCO_LEFT input.
All the package pins appear in Table 91 and are sorted by bank number, then by pin name. Pairs of pins that form a
differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type, as
defined earlier.
An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at
http://www.xilinx.com/support/documentation/data_ sheets/s3_pin.zip.
Pinout Table
Table 91: TQ144 Package Pinout
XC3S50, XC3S200,
XC3S400 Pin Name
TQ144 Pin
Number
Bank
Type
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
IO_L01N_0/VRP_0
IO_L01P_0/VRN_0
IO_L27N_0
P141
P140
P137
P135
P132
P131
P130
P129
P128
P127
P116
P113
P112
P119
P118
P123
P122
P125
P124
P108
P107
P105
P104
P103
P102
P100
P99
DCI
DCI
I/O
IO_L27P_0
I/O
IO_L30N_0
I/O
IO_L30P_0
I/O
IO_L31N_0
I/O
IO_L31P_0/VREF_0
IO_L32N_0/GCLK7
IO_L32P_0/GCLK6
IO
VREF
GCLK
GCLK
I/O
IO_L01N_1/VRP_1
IO_L01P_1/VRN_1
IO_L28N_1
DCI
DCI
I/O
IO_L28P_1
I/O
IO_L31N_1/VREF_1
IO_L31P_1
VREF
I/O
IO_L32N_1/GCLK5
IO_L32P_1/GCLK4
IO_L01N_2/VRP_2
IO_L01P_2/VRN_2
IO_L20N_2
GCLK
GCLK
DCI
DCI
I/O
IO_L20P_2
I/O
IO_L21N_2
I/O
IO_L21P_2
I/O
IO_L22N_2
I/O
IO_L22P_2
I/O
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Table 91: TQ144 Package Pinout (Cont’d)
XC3S50, XC3S200,
XC3S400 Pin Name
TQ144 Pin
Bank
Type
Number
P98
P97
P96
P95
P93
P92
P76
P74
P73
P78
P77
P80
P79
P83
P82
P85
P84
P87
P86
P90
P89
P70
P69
P68
P65
P63
P60
P59
P58
P57
P56
P55
P44
P41
P40
P47
P46
P51
P50
P53
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
IO_L23N_2/VREF_2
IO_L23P_2
VREF
I/O
IO_L24N_2
I/O
IO_L24P_2
I/O
IO_L40N_2
I/O
IO_L40P_2/VREF_2
IO
VREF
I/O
IO_L01N_3/VRP_3
IO_L01P_3/VRN_3
IO_L20N_3
DCI
DCI
I/O
IO_L20P_3
I/O
IO_L21N_3
I/O
IO_L21P_3
I/O
IO_L22N_3
I/O
IO_L22P_3
I/O
IO_L23N_3
I/O
IO_L23P_3/VREF_3
IO_L24N_3
VREF
I/O
IO_L24P_3
I/O
IO_L40N_3/VREF_3
IO_L40P_3
VREF
I/O
IO/VREF_4
VREF
DCI
IO_L01N_4/VRP_4
IO_L01P_4/VRN_4
IO_L27N_4/DIN/D0
IO_L27P_4/D1
IO_L30N_4/D2
IO_L30P_4/D3
IO_L31N_4/INIT_B
IO_L31P_4/DOUT/BUSY
IO_L32N_4/GCLK1
IO_L32P_4/GCLK0
IO/VREF_5
DCI
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
GCLK
GCLK
VREF
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
GCLK
IO_L01N_5/RDWR_B
IO_L01P_5/CS_B
IO_L28N_5/D6
IO_L28P_5/D7
IO_L31N_5/D4
IO_L31P_5/D5
IO_L32N_5/GCLK3
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Spartan-3 FPGA Family: Pinout Descriptions
Table 91: TQ144 Package Pinout (Cont’d)
XC3S50, XC3S200,
XC3S400 Pin Name
TQ144 Pin
Bank
Type
Number
P52
P36
P35
P33
P32
P31
P30
P28
P27
P26
P25
P24
P23
P21
P20
P4
5
6
IO_L32P_5/GCLK2
IO_L01N_6/VRP_6
IO_L01P_6/VRN_6
IO_L20N_6
GCLK
DCI
6
DCI
6
I/O
6
IO_L20P_6
I/O
6
IO_L21N_6
I/O
6
IO_L21P_6
I/O
6
IO_L22N_6
I/O
6
IO_L22P_6
I/O
6
IO_L23N_6
I/O
6
IO_L23P_6
I/O
6
IO_L24N_6/VREF_6
IO_L24P_6
VREF
I/O
6
6
IO_L40N_6
I/O
6
IO_L40P_6/VREF_6
IO/VREF_7
VREF
VREF
DCI
7
7
IO_L01N_7/VRP_7
IO_L01P_7/VRN_7
IO_L20N_7
P2
7
P1
DCI
7
P6
I/O
7
IO_L20P_7
P5
I/O
7
IO_L21N_7
P8
I/O
7
IO_L21P_7
P7
I/O
7
IO_L22N_7
P11
P10
P13
P12
P15
P14
P18
P17
P126
P138
P115
P106
P75
P91
P54
P43
P66
P19
I/O
7
IO_L22P_7
I/O
7
IO_L23N_7
I/O
7
IO_L23P_7
I/O
7
IO_L24N_7
I/O
7
IO_L24P_7
I/O
7
IO_L40N_7/VREF_7
IO_L40P_7
VREF
I/O
7
0,1
0,1
0,1
2,3
2,3
2,3
4,5
4,5
4,5
6,7
VCCO_TOP
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO_TOP
VCCO_TOP
VCCO_RIGHT
VCCO_RIGHT
VCCO_RIGHT
VCCO_BOTTOM
VCCO_BOTTOM
VCCO_BOTTOM
VCCO_LEFT
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Spartan-3 FPGA Family: Pinout Descriptions
Table 91: TQ144 Package Pinout (Cont’d)
XC3S50, XC3S200,
XC3S400 Pin Name
TQ144 Pin
Number
Bank
Type
6,7
6,7
VCCO_LEFT
VCCO_LEFT
GND
P34
VCCO
VCCO
GND
P3
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
P136
P139
P114
P117
P94
GND
GND
GND
GND
GND
GND
GND
GND
GND
P101
P81
GND
GND
GND
GND
P88
GND
GND
P64
GND
GND
P67
GND
GND
P42
GND
GND
P45
GND
GND
P22
GND
GND
P29
GND
GND
P9
GND
GND
P16
GND
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
P134
P120
P62
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
JTAG
P48
P133
P121
P61
P49
VCCAUX CCLK
VCCAUX DONE
VCCAUX HSWAP_EN
VCCAUX M0
P72
P71
P142
P38
VCCAUX M1
P37
VCCAUX M2
P39
VCCAUX PROG_B
VCCAUX TCK
VCCAUX TDI
P143
P110
P144
P109
P111
JTAG
VCCAUX TDO
VCCAUX TMS
JTAG
JTAG
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Spartan-3 FPGA Family: Pinout Descriptions
User I/Os by Bank
Table 92 indicates how the available user-I/O pins are distributed between the eight I/O banks on the TQ144 package.
Table 92: User I/Os Per Bank in TQ144 Package
All Possible I/O Pins by Type
Package Edge
Top
I/O Bank
Maximum I/O
I/O
5
DUAL
DCI
2
VREF
GCLK
0
1
2
3
4
5
6
7
10
9
0
0
0
0
6
6
0
0
1
1
2
2
1
1
2
2
2
2
0
0
2
2
0
0
4
2
14
15
11
9
10
11
0
2
Right
2
2
Bottom
Left
0
0
14
15
10
11
2
2
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Spartan-3 FPGA Family: Pinout Descriptions
TQ144 Footprint
X-Ref Target - Figure 46
IO_L01P_7/VRN_7
IO_L01N_7/VRP_7
VCCO_LEFT
IO/VREF_7
IO_L20P_7
1
2
3
4
5
6
7
8
9
108 IO_L01N_2/VRP_2
Bank 0
Bank 1
107 IO_L01P_2/VRN_2
VCCO for Top Edge
106 VCCO_RIGHT
105 IO_L20N_2
104 IO_L20P_2
103 IO_L21N_2
102 IO_L21P_2
101 GND
IO_L20N_7
IO_L21P_7
IO_L21N_7
GND
100 IO_L22N_2
99 IO_L22P_2
98 IO_L23N_2/VREF_2
97 IO_L23P_2
96 IO_L24N_2
95 IO_L24P_2
94 GND
IO_L22P_7 10
IO_L22N_7 11
IO_L23P_7 12
IO_L23N_7 13
IO_L24P_7 14
IO_L24N_7 15
GND 16
93 IO_L40N_2
92 IO_L40P_2/VREF_2
91 VCCO_RIGHT
90 IO_L40N_3/VREF_3
89 IO_L40P_3
88 GND
IO_L40P_7 17
IO_L40N_7/VREF_7 18
VCCO_LEFT 19
IO_L40P_6/VREF_6 20
IO_L40N_6 21
GND 22
87 IO_L24N_3
86 IO_L24P_3
85 IO_L23N_3
84 IO_L23P_3/VREF_3
83 IO_L22N_3
82 IO_L22P_3
81 GND
IO_L24P_6 23
IO_L24N_6/VREF_6 24
IO_L23P_6 25
IO_L23N_6 26
IO_L22P_6 27
IO_L22N_6 28
GND 29
80 IO_L21N_3
79 IO_L21P_3
78 IO_L20N_3
77 IO_L20P_3
76 IO
IO_L21P_6 30
IO_L21N_6 31
IO_L20P_6 32
IO_L20N_6 33
VCCO_LEFT 34
IO_L01P_6/VRN_6 35
IO_L01N_6/VRP_6 36
VCCO for Bottom Edge
75 VCCO_RIGHT
74
73
IO_L01N_3/VRP_3
IO_L01P_3/VRN_3
Bank 5
Bank 4
(no DCI)
DS099-4_08_121103
Figure 46: TQ144 Package Footprint (Top View). Note pin 1 indicator in top-left corner and logo orientation.
DUAL: Configuration pin, then possible
VREF: User I/O or input voltage reference for
51 I/O: Unrestricted, general-purpose user I/O
12
8
12
user I/O
bank
DCI: User I/O or reference resistor input for
GCLK: User I/O or global clock buffer
input
14
12 VCCO: Output voltage supply for bank
bank
7
0
CONFIG: Dedicated configuration pins
4
JTAG: Dedicated JTAG port pins
4
4
VCCINT: Internal core voltage supply (+1.2V)
VCCAUX: Auxiliary voltage supply (+2.5V)
N.C.: No unconnected pins in this package
16 GND: Ground
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Spartan-3 FPGA Family: Pinout Descriptions
PQ208: 208-lead Plastic Quad Flat Pack
The 208-lead plastic quad flat package, PQ208, supports three different Spartan-3 devices, including the XC3S50, the
XC3S200, and the XC3S400. The footprints for the XC3S200 and XC3S400 are identical, as shown in Table 93 and
Figure 47. The XC3S50, however, has fewer I/O pins resulting in 17 unconnected pins on the PQ208 package, labeled as
“N.C.” In Table 93 and Figure 47, these unconnected pins are indicated with a black diamond symbol ().
All the package pins appear in Table 93 and are sorted by bank number, then by pin name. Pairs of pins that form a
differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type, as
defined earlier.
If there is a difference between the XC3S50 pinout and the pinout for the XC3S200 and XC3S400, then that difference is
highlighted in Table 93. If the table entry is shaded grey, then there is an unconnected pin on the XC3S50 that maps to a
user-I/O pin on the XC3S200 and XC3S400. If the table entry is shaded tan, then the unconnected pin on the XC3S50 maps
to a VREF-type pin on the XC3S200 and XC3S400. If the other VREF pins in the bank all connect to a voltage reference to
support a special I/O standard, then also connect the N.C. pin on the XC3S50 to the same VREF voltage. This provides
maximum flexibility as you could potentially migrate a design from the XC3S50 device to an XC3S200 or XC3S400 FPGA
without changing the printed circuit board.
An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at
http://www.xilinx.com/support/documentation/data_ sheets/s3_pin.zip
Pinout Table
Table 93: PQ208 Package Pinout
XC3S50
Pin Name
XC3S200, XC3S400
Pin Names
PQ208Pin
Number
Bank
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
IO
IO
IO
IO
P189
P197
P200
P205
P204
P203
P199
P198
P196
P194
P191
P190
P187
P185
P184
P183
P188
P201
P167
P175
P182
P162
P161
I/O
I/O
N.C. ()
IO/VREF_0
IO/VREF_0
IO_L01N_0/VRP_0
IO_L01P_0/VRN_0
IO_L25N_0
IO_L25P_0
VREF
VREF
DCI
DCI
I/O
IO/VREF_0
IO_L01N_0/VRP_0
IO_L01P_0/VRN_0
IO_L25N_0
IO_L25P_0
IO_L27N_0
IO_L27P_0
IO_L30N_0
IO_L30P_0
IO_L31N_0
IO_L31P_0/VREF_0
IO_L32N_0/GCLK7
IO_L32P_0/GCLK6
VCCO_0
I/O
IO_L27N_0
IO_L27P_0
I/O
I/O
IO_L30N_0
IO_L30P_0
I/O
I/O
IO_L31N_0
IO_L31P_0/VREF_0
IO_L32N_0/GCLK7
IO_L32P_0/GCLK6
VCCO_0
I/O
VREF
GCLK
GCLK
VCCO
VCCO
I/O
VCCO_0
VCCO_0
IO
IO
IO
IO
I/O
IO
IO
I/O
IO_L01N_1/VRP_1
IO_L01P_1/VRN_1
IO_L01N_1/VRP_1
IO_L01P_1/VRN_1
DCI
DCI
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Spartan-3 FPGA Family: Pinout Descriptions
Table 93: PQ208 Package Pinout (Cont’d)
XC3S50
XC3S200, XC3S400
PQ208Pin
Number
Bank
Type
Pin Name
Pin Names
IO_L10N_1/VREF_1
IO_L10P_1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
IO_L10N_1/VREF_1
IO_L10P_1
P166
P165
P169
P168
P172
P171
P178
P176
P181
P180
P164
P177
P154
P156
P155
P152
P150
P149
P148
P147
P146
P144
P143
P141
P140
P139
P138
P137
P135
P133
P132
P136
P153
P107
P106
P109
P108
P113
P111
P115
VREF
I/O
IO_L27N_1
IO_L27N_1
I/O
IO_L27P_1
IO_L27P_1
I/O
IO_L28N_1
IO_L28N_1
I/O
IO_L28P_1
IO_L28P_1
I/O
IO_L31N_1/VREF_1
IO_L31P_1
IO_L31N_1/VREF_1
IO_L31P_1
VREF
I/O
IO_L32N_1/GCLK5
IO_L32P_1/GCLK4
VCCO_1
IO_L32N_1/GCLK5
IO_L32P_1/GCLK4
VCCO_1
GCLK
GCLK
VCCO
VCCO
VREF
DCI
DCI
I/O
VCCO_1
VCCO_1
N.C. ()
IO/VREF_2
IO_L01N_2/VRP_2
IO_L01P_2/VRN_2
IO_L19N_2
IO_L01N_2/VRP_2
IO_L01P_2/VRN_2
IO_L19N_2
IO_L19P_2
IO_L19P_2
I/O
IO_L20N_2
IO_L20N_2
I/O
IO_L20P_2
IO_L20P_2
I/O
IO_L21N_2
IO_L21N_2
I/O
IO_L21P_2
IO_L21P_2
I/O
IO_L22N_2
IO_L22N_2
I/O
IO_L22P_2
IO_L22P_2
I/O
IO_L23N_2/VREF_2
IO_L23P_2
IO_L23N_2/VREF_2
IO_L23P_2
VREF
I/O
IO_L24N_2
IO_L24N_2
I/O
IO_L24P_2
IO_L24P_2
I/O
N.C. ()
IO_L39N_2
I/O
N.C. ()
IO_L39P_2
I/O
IO_L40N_2
IO_L40N_2
I/O
IO_L40P_2/VREF_2
VCCO_2
IO_L40P_2/VREF_2
VCCO_2
VREF
VCCO
VCCO
DCI
DCI
I/O
VCCO_2
VCCO_2
IO_L01N_3/VRP_3
IO_L01P_3/VRN_3
N.C. ()
IO_L01N_3/VRP_3
IO_L01P_3/VRN_3
IO_L17N_3
N.C. ()
IO_L17P_3/VREF_3
IO_L19N_3
VREF
I/O
IO_L19N_3
IO_L19P_3
IO_L19P_3
I/O
IO_L20N_3
IO_L20N_3
I/O
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Spartan-3 FPGA Family: Pinout Descriptions
Table 93: PQ208 Package Pinout (Cont’d)
XC3S50
Pin Name
XC3S200, XC3S400
Pin Names
PQ208Pin
Number
Bank
Type
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
IO_L20P_3
IO_L20P_3
P114
P117
P116
P120
P119
P123
P122
P125
P124
P128
P126
P131
P130
P110
P127
P93
I/O
I/O
IO_L21N_3
IO_L21N_3
IO_L21P_3
IO_L21P_3
I/O
IO_L22N_3
IO_L22N_3
I/O
IO_L22P_3
IO_L22P_3
I/O
IO_L23N_3
IO_L23N_3
I/O
IO_L23P_3/VREF_3
IO_L24N_3
IO_L23P_3/VREF_3
IO_L24N_3
VREF
I/O
IO_L24P_3
IO_L24P_3
I/O
N.C. ()
IO_L39N_3
I/O
N.C. ()
IO_L39P_3
I/O
IO_L40N_3/VREF_3
IO_L40P_3
IO_L40N_3/VREF_3
IO_L40P_3
VREF
I/O
VCCO_3
VCCO_3
VCCO
VCCO
I/O
VCCO_3
VCCO_3
IO
IO
N.C. ()
IO
P97
I/O
IO/VREF_4
IO/VREF_4
P85
VREF
VREF
VREF
DCI
N.C. ()
IO/VREF_4
P96
IO/VREF_4
IO/VREF_4
P102
P101
P100
P95
IO_L01N_4/VRP_4
IO_L01P_4/VRN_4
IO_L25N_4
IO_L01N_4/VRP_4
IO_L01P_4/VRN_4
IO_L25N_4
DCI
I/O
IO_L25P_4
IO_L25P_4
P94
I/O
IO_L27N_4/DIN/D0
IO_L27P_4/D1
IO_L30N_4/D2
IO_L30P_4/D3
IO_L31N_4/INIT_B
IO_L27N_4/DIN/D0
IO_L27P_4/D1
IO_L30N_4/D2
IO_L30P_4/D3
IO_L31N_4/INIT_B
P92
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
GCLK
GCLK
VCCO
VCCO
I/O
P90
P87
P86
P83
IO_L31P_4/DOUT/BUSY IO_L31P_4/DOUT/BUSY
P81
IO_L32N_4/GCLK1
IO_L32P_4/GCLK0
VCCO_4
IO_L32N_4/GCLK1
IO_L32P_4/GCLK0
VCCO_4
P80
P79
P84
VCCO_4
VCCO_4
P98
IO
IO
P63
IO
IO
P71
I/O
IO/VREF_5
IO/VREF_5
P78
VREF
DUAL
DUAL
DCI
IO_L01N_5/RDWR_B
IO_L01P_5/CS_B
IO_L10N_5/VRP_5
IO_L01N_5/RDWR_B
IO_L01P_5/CS_B
IO_L10N_5/VRP_5
P58
P57
P62
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Spartan-3 FPGA Family: Pinout Descriptions
Table 93: PQ208 Package Pinout (Cont’d)
XC3S50
XC3S200, XC3S400
PQ208Pin
Number
Bank
Type
Pin Name
Pin Names
IO_L10P_5/VRN_5
IO_L27N_5/VREF_5
IO_L27P_5
5
5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
IO_L10P_5/VRN_5
IO_L27N_5/VREF_5
IO_L27P_5
P61
P65
P64
P68
P67
P74
P72
P77
P76
P60
P73
P50
P52
P51
P48
P46
P45
P44
P43
P42
P40
P39
P37
P36
P35
P34
P33
P31
P29
P28
P32
P49
P3
DCI
VREF
I/O
IO_L28N_5/D6
IO_L28P_5/D7
IO_L31N_5/D4
IO_L31P_5/D5
IO_L32N_5/GCLK3
IO_L32P_5/GCLK2
VCCO_5
IO_L28N_5/D6
IO_L28P_5/D7
IO_L31N_5/D4
IO_L31P_5/D5
IO_L32N_5/GCLK3
IO_L32P_5/GCLK2
VCCO_5
DUAL
DUAL
DUAL
DUAL
GCLK
GCLK
VCCO
VCCO
VREF
DCI
VCCO_5
VCCO_5
N.C. ()
IO/VREF_6
IO_L01N_6/VRP_6
IO_L01P_6/VRN_6
IO_L19N_6
IO_L01N_6/VRP_6
IO_L01P_6/VRN_6
IO_L19N_6
DCI
I/O
IO_L19P_6
IO_L19P_6
I/O
IO_L20N_6
IO_L20N_6
I/O
IO_L20P_6
IO_L20P_6
I/O
IO_L21N_6
IO_L21N_6
I/O
IO_L21P_6
IO_L21P_6
I/O
IO_L22N_6
IO_L22N_6
I/O
IO_L22P_6
IO_L22P_6
I/O
IO_L23N_6
IO_L23N_6
I/O
IO_L23P_6
IO_L23P_6
I/O
IO_L24N_6/VREF_6
IO_L24P_6
IO_L24N_6/VREF_6
IO_L24P_6
VREF
I/O
N.C. ()
IO_L39N_6
I/O
N.C. ()
IO_L39P_6
I/O
IO_L40N_6
IO_L40N_6
I/O
IO_L40P_6/VREF_6
VCCO_6
IO_L40P_6/VREF_6
VCCO_6
VREF
VCCO
VCCO
DCI
VCCO_6
VCCO_6
IO_L01N_7/VRP_7
IO_L01P_7/VRN_7
N.C. ()
IO_L01N_7/VRP_7
IO_L01P_7/VRN_7
IO_L16N_7
P2
DCI
P5
I/O
N.C. ()
IO_L16P_7/VREF_7
IO_L19N_7/VREF_7
IO_L19P_7
P4
VREF
VREF
I/O
IO_L19N_7/VREF_7
IO_L19P_7
P9
P7
IO_L20N_7
IO_L20N_7
P11
P10
I/O
IO_L20P_7
IO_L20P_7
I/O
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Spartan-3 FPGA Family: Pinout Descriptions
Table 93: PQ208 Package Pinout (Cont’d)
XC3S50
Pin Name
XC3S200, XC3S400
Pin Names
PQ208Pin
Number
Bank
Type
7
IO_L21N_7
IO_L21N_7
P13
P12
P16
P15
P19
P18
P21
P20
P24
P22
P27
P26
P6
I/O
I/O
7
IO_L21P_7
IO_L22N_7
IO_L22P_7
IO_L23N_7
IO_L23P_7
IO_L24N_7
IO_L24P_7
N.C. ()
N.C. ()
IO_L40N_7/VREF_7
IO_L40P_7
VCCO_7
VCCO_7
GND
IO_L21P_7
IO_L22N_7
IO_L22P_7
IO_L23N_7
IO_L23P_7
IO_L24N_7
IO_L24P_7
IO_L39N_7
IO_L39P_7
IO_L40N_7/VREF_7
IO_L40P_7
VCCO_7
VCCO_7
GND
7
I/O
7
I/O
7
I/O
7
I/O
7
I/O
7
I/O
7
I/O
7
I/O
7
VREF
I/O
7
7
VCCO
VCCO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
7
P23
P1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
GND
GND
P186
P195
P202
P163
P170
P179
P134
P145
P151
P157
P112
P118
P129
P82
P91
P99
P105
P53
P59
P66
P75
P30
P41
P47
P8
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
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Spartan-3 FPGA Family: Pinout Descriptions
Table 93: PQ208 Package Pinout (Cont’d)
XC3S50
Pin Name
XC3S200, XC3S400
Pin Names
PQ208Pin
Number
Bank
Type
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
GND
GND
GND
GND
P14
P25
GND
GND
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
CCLK
P193
P173
P142
P121
P89
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
JTAG
P69
P38
P17
P192
P174
P88
P70
VCCAUX CCLK
VCCAUX DONE
VCCAUX HSWAP_EN
VCCAUX M0
P104
P103
P206
P55
DONE
HSWAP_EN
M0
VCCAUX M1
M1
P54
VCCAUX M2
M2
P56
VCCAUX PROG_B
VCCAUX TCK
VCCAUX TDI
PROG_B
TCK
P207
P159
P208
P158
P160
TDI
JTAG
VCCAUX TDO
VCCAUX TMS
TDO
JTAG
TMS
JTAG
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Spartan-3 FPGA Family: Pinout Descriptions
User I/Os by Bank
Table 94 indicates how the available user-I/O pins are distributed between the eight I/O banks for the XC3S50 in the PQ208
package. Similarly, Table 95 shows how the available user-I/O pins are distributed between the eight I/O banks for the
XC3S200 and XC3S400 in the PQ208 package.
Table 94: User I/Os Per Bank for XC3S50 in PQ208 Package
All Possible I/O Pins by Type
Package Edge
Top
I/O Bank
Maximum I/O
I/O
9
DUAL
DCI
2
VREF
GCLK
0
1
2
3
4
5
6
7
15
15
16
16
15
15
16
16
0
0
0
0
6
6
0
0
2
2
2
2
2
2
2
2
2
2
0
0
2
2
0
0
9
2
13
12
3
2
Right
2
2
Bottom
Left
3
2
12
12
2
2
Table 95: User I/Os Per Bank for XC3S200 and XC3S400 in PQ208 Package
All Possible I/O Pins by Type
Package Edge
Top
I/O Bank
Maximum I/O
I/O
9
DUAL
DCI
2
VREF
GCLK
0
1
2
3
4
5
6
7
16
15
19
20
17
15
19
20
0
0
0
0
6
6
0
0
3
2
3
3
3
2
3
3
2
2
0
0
2
2
0
0
9
2
14
15
4
2
Right
2
2
Bottom
Left
3
2
14
15
2
2
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Spartan-3 FPGA Family: Pinout Descriptions
X-Ref Target - Figure 47
PQ208 Footprint
Left Half of Package
(Top View)
XC3S50
(124 max. user I/O)
I/O: Unrestricted,
1
GND
IO_L01P_7/VRN_7
IO_L01N_7/VRP_7
() IO_L16P_7/VREF_7
() IO_L16N_7
VCCO_7
72
Bank 0
general-purpose user I/O
2
3
4
5
6
7
8
9
VREF: User I/O or input
16
voltage reference for bank
IO_L19P_7
N.C.: Unconnected pins for
XC3S50 ()
17
GND
IO_L19N_7/VREF_7
IO_L20P_7 10
IO_L20N_7 11
IO_L21P_7 12
IO_L21N_7 13
GND 14
XC3S200, XC3S400
(141 max user I/O)
I/O: Unrestricted,
83
general-purpose user I/O
IO_L22P_7 15
IO_L22N_7 16
VCCAUX 17
VREF: User I/O or input
22
voltage reference for bank
IO_L23P_7 18
IO_L23N_7 19
IO_L24P_7 20
IO_L24N_7 21
() IO_L39P_7 22
VCCO_7 23
N.C.: No unconnected pins
in this package
0
All devices
() IO_L39N_7 24
GND 25
DUAL: Configuration pin,
then possible user I/O
12
IO_L40P_7 26
IO_L40N_7/VREF_7 27
IO_L40P_6/VREF_6 28
IO_L40N_6 29
GND 30
GCLK: User I/O or global
clock buffer input
8
() IO_L39P_6 31
VCCO_6 32
DCI: User I/O or reference
16
resistor input for bank
() IO_L39N_6 33
IO_L24P_6 34
IO_L24N_6/VREF_6 35
IO_L23P_6 36
IO_L23N_6 37
VCCAUX 38
CONFIG: Dedicated
7
configuration pins
JTAG: Dedicated JTAG
port pins
4
IO_L22P_6 39
IO_L22N_6 40
GND 41
IO_L21P_6 42
IO_L21N_6 43
IO_L20P_6 44
IO_L20N_6 45
IO_L19P_6 46
GND 47
VCCINT: Internal core
voltage supply (+1.2V)
4
VCCO: Output voltage
supply for bank
12
IO_L19N_6 48
VCCO_6 49
VCCAUX: Auxiliary voltage
supply (+2.5V)
8
() IO/VREF_6 50
IO_L01P_6/VRN_6 51
IO_L01N_6/VRP_6 52
Bank 5
28 GND: Ground
DS099-4_09a_121103
Figure 47: PQ208 Package Footprint (Top View). Note pin 1 indicator in top-left corner and logo orientation.
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Spartan-3 FPGA Family: Pinout Descriptions
Right Half of Package
(Top View)
156 IO_L01N_2/VRP_2
155 IO_L01P_2/VRN_2
154 IO/VREF_2 ()
153 VCCO_2
Bank 1
152 IO_L19N_2
151 GND
150 IO_L19P_2
149 IO_L20N_2
148 IO_L20P_2
147 IO_L21N_2
146 IO_L21P_2
145 GND
144 IO_L22N_2
143 IO_L22P_2
142 VCCAUX
141 IO_L23N_2/VREF_2
140 IO_L23P_2
139 IO_L24N_2
138 IO_L24P_2
137 IO_L39N_2 ()
136 VCCO_2
135 IO_L39P_2 ()
134 GND
133 IO_L40N_2
132 IO_L40P_2/VREF_2
131 IO_L40N_3/VREF_3
130 IO_L40P_3
129 GND
128 IO_L39N_3 ()
127 VCCO_3
126 IO_L39P_3 ()
125 IO_L24N_3
124 IO_L24P_3
123 IO_L23N_3
122 IO_L23P_3/VREF_3
121 VCCAUX
120 IO_L22N_3
119 IO_L22P_3
118 GND
117 IO_L21N_3
116 IO_L21P_3
115 IO_L20N_3
114 IO_L20P_3
113 IO_L19N_3
112 GND
111 IO_L19P_3
110 VCCO_3
109 IO_L17N_3 ()
108 IO_L17P_3/VREF_3 ()
107 IO_L01N_3/VRP_3
106 IO_L01P_3/VRN_3
105 GND
Bank 4
DS099-4_9b_121103
Figure 48: PQ208 Package Footprint (Top View) Continued
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Spartan-3 FPGA Family: Pinout Descriptions
FT256: 256-lead Fine-pitch Thin Ball Grid Array
The 256-lead fine-pitch thin ball grid array package, FT256, supports three different Spartan-3 devices, including the
XC3S200, the XC3S400, and the XC3S1000. The footprints for all three devices are identical, as shown in Table 96 and
Figure 49.
All the package pins appear in Table 96 and are sorted by bank number, then by pin name. Pairs of pins that form a
differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type, as
defined earlier.
An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at
http://www.xilinx.com/support/documentation/data_ sheets/s3_pin.zip.
Pinout Table
Table 96: FT256 Package Pinout
XC3S200, XC3S400, XC3S1000 FT256 Pin
Bank
Type
Pin Name
Number
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
IO
A5
I/O
I/O
IO
A7
IO/VREF_0
IO/VREF_0
A3
VREF
VREF
DCI
DCI
I/O
D5
IO_L01N_0/VRP_0
IO_L01P_0/VRN_0
IO_L25N_0
IO_L25P_0
IO_L27N_0
IO_L27P_0
IO_L28N_0
IO_L28P_0
IO_L29N_0
IO_L29P_0
IO_L30N_0
IO_L30P_0
IO_L31N_0
IO_L31P_0/VREF_0
IO_L32N_0/GCLK7
IO_L32P_0/GCLK6
VCCO_0
B4
A4
C5
B5
I/O
E6
I/O
D6
I/O
C6
I/O
B6
I/O
E7
I/O
D7
I/O
C7
I/O
B7
I/O
D8
I/O
C8
VREF
GCLK
GCLK
VCCO
VCCO
VCCO
I/O
B8
A8
E8
VCCO_0
F7
VCCO_0
F8
IO
A9
IO
A12
C10
D12
A14
B14
I/O
IO
I/O
IO/VREF_1
IO_L01N_1/VRP_1
IO_L01P_1/VRN_1
VREF
DCI
DCI
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Spartan-3 FPGA Family: Pinout Descriptions
Table 96: FT256 Package Pinout (Cont’d)
XC3S200, XC3S400, XC3S1000 FT256 Pin
Bank
Type
Pin Name
IO_L10N_1/VREF_1
IO_L10P_1
Number
A13
B13
B12
C12
D11
E11
B11
C11
D10
E10
A10
B10
C9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
VREF
I/O
IO_L27N_1
I/O
IO_L27P_1
I/O
IO_L28N_1
I/O
IO_L28P_1
I/O
IO_L29N_1
I/O
IO_L29P_1
I/O
IO_L30N_1
I/O
IO_L30P_1
I/O
IO_L31N_1/VREF_1
IO_L31P_1
VREF
I/O
IO_L32N_1/GCLK5
IO_L32P_1/GCLK4
VCCO_1
GCLK
GCLK
VCCO
VCCO
VCCO
I/O
D9
E9
VCCO_1
F9
VCCO_1
F10
G16
B16
C16
C15
D14
D15
D16
E13
E14
E15
E16
F12
F13
F14
F15
G12
G13
G14
G15
H13
H14
H15
H16
IO
IO_L01N_2/VRP_2
IO_L01P_2/VRN_2
IO_L16N_2
DCI
DCI
I/O
IO_L16P_2
I/O
IO_L17N_2
I/O
IO_L17P_2/VREF_2
IO_L19N_2
VREF
I/O
IO_L19P_2
I/O
IO_L20N_2
I/O
IO_L20P_2
I/O
IO_L21N_2
I/O
IO_L21P_2
I/O
IO_L22N_2
I/O
IO_L22P_2
I/O
IO_L23N_2/VREF_2
IO_L23P_2
VREF
I/O
IO_L24N_2
I/O
IO_L24P_2
I/O
IO_L39N_2
I/O
IO_L39P_2
I/O
IO_L40N_2
I/O
IO_L40P_2/VREF_2
VREF
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Spartan-3 FPGA Family: Pinout Descriptions
Table 96: FT256 Package Pinout (Cont’d)
XC3S200, XC3S400, XC3S1000 FT256 Pin
Pin Name
Bank
Type
Number
G11
H11
H12
K15
P16
R16
P15
P14
N16
N15
M14
N14
M16
M15
L13
M13
L15
L14
K12
L12
K14
K13
J14
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
VCCO_2
VCCO_2
VCCO_2
IO
VCCO
VCCO
VCCO
I/O
IO_L01N_3/VRP_3
IO_L01P_3/VRN_3
IO_L16N_3
DCI
DCI
I/O
IO_L16P_3
I/O
IO_L17N_3
I/O
IO_L17P_3/VREF_3
IO_L19N_3
VREF
I/O
IO_L19P_3
I/O
IO_L20N_3
I/O
IO_L20P_3
I/O
IO_L21N_3
I/O
IO_L21P_3
I/O
IO_L22N_3
I/O
IO_L22P_3
I/O
IO_L23N_3
I/O
IO_L23P_3/VREF_3
IO_L24N_3
VREF
I/O
IO_L24P_3
I/O
IO_L39N_3
I/O
IO_L39P_3
J13
I/O
IO_L40N_3/VREF_3
IO_L40P_3
J16
VREF
I/O
K16
J11
VCCO_3
VCCO
VCCO
VCCO
I/O
VCCO_3
J12
VCCO_3
K11
T12
T14
N12
P13
T10
R13
T13
P12
R12
M11
N11
IO
IO
I/O
IO/VREF_4
VREF
VREF
VREF
DCI
DCI
I/O
IO/VREF_4
IO/VREF_4
IO_L01N_4/VRP_4
IO_L01P_4/VRN_4
IO_L25N_4
IO_L25P_4
I/O
IO_L27N_4/DIN/D0
IO_L27P_4/D1
DUAL
DUAL
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Spartan-3 FPGA Family: Pinout Descriptions
Table 96: FT256 Package Pinout (Cont’d)
XC3S200, XC3S400, XC3S1000 FT256 Pin
Bank
Type
Pin Name
Number
P11
R11
M10
N10
P10
R10
N9
P9
4
4
4
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6
6
6
6
IO_L28N_4
IO_L28P_4
IO_L29N_4
IO_L29P_4
I/O
I/O
I/O
I/O
IO_L30N_4/D2
IO_L30P_4/D3
IO_L31N_4/INIT_B
IO_L31P_4/DOUT/BUSY
IO_L32N_4/GCLK1
IO_L32P_4/GCLK0
VCCO_4
DUAL
DUAL
DUAL
DUAL
GCLK
GCLK
VCCO
VCCO
VCCO
I/O
R9
T9
L9
VCCO_4
L10
M9
N5
P7
VCCO_4
IO
IO
I/O
IO
T5
I/O
IO/VREF_5
T8
VREF
DUAL
DUAL
DCI
IO_L01N_5/RDWR_B
IO_L01P_5/CS_B
IO_L10N_5/VRP_5
IO_L10P_5/VRN_5
IO_L27N_5/VREF_5
IO_L27P_5
T3
R3
T4
R4
R5
P5
DCI
VREF
I/O
IO_L28N_5/D6
IO_L28P_5/D7
IO_L29N_5
N6
M6
R6
P6
DUAL
DUAL
I/O
IO_L29P_5/VREF_5
IO_L30N_5
VREF
I/O
N7
M7
T7
IO_L30P_5
I/O
IO_L31N_5/D4
IO_L31P_5/D5
IO_L32N_5/GCLK3
IO_L32P_5/GCLK2
VCCO_5
DUAL
DUAL
GCLK
GCLK
VCCO
VCCO
VCCO
I/O
R7
P8
N8
L7
VCCO_5
L8
VCCO_5
M8
K1
IO
IO_L01N_6/VRP_6
IO_L01P_6/VRN_6
IO_L16N_6
R1
P1
DCI
DCI
P2
I/O
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Spartan-3 FPGA Family: Pinout Descriptions
Table 96: FT256 Package Pinout (Cont’d)
XC3S200, XC3S400, XC3S1000 FT256 Pin
Bank
Type
Pin Name
Number
N3
N2
N1
M4
M3
M2
M1
L5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
IO_L16P_6
IO_L17N_6
I/O
I/O
IO_L17P_6/VREF_6
IO_L19N_6
IO_L19P_6
VREF
I/O
I/O
IO_L20N_6
IO_L20P_6
I/O
I/O
IO_L21N_6
IO_L21P_6
I/O
L4
I/O
IO_L22N_6
IO_L22P_6
L3
I/O
L2
I/O
IO_L23N_6
IO_L23P_6
K5
K4
K3
K2
J4
I/O
I/O
IO_L24N_6/VREF_6
IO_L24P_6
VREF
I/O
IO_L39N_6
IO_L39P_6
I/O
J3
I/O
IO_L40N_6
IO_L40P_6/VREF_6
VCCO_6
J2
I/O
J1
VREF
VCCO
VCCO
VCCO
I/O
J5
VCCO_6
J6
VCCO_6
K6
G2
C1
B1
C2
C3
D1
D2
E3
D3
E1
E2
F4
E4
F2
F3
G5
F5
G3
IO
IO_L01N_7/VRP_7
IO_L01P_7/VRN_7
IO_L16N_7
IO_L16P_7/VREF_7
IO_L17N_7
IO_L17P_7
DCI
DCI
I/O
VREF
I/O
I/O
IO_L19N_7/VREF_7
IO_L19P_7
VREF
I/O
IO_L20N_7
IO_L20P_7
I/O
I/O
IO_L21N_7
IO_L21P_7
I/O
I/O
IO_L22N_7
IO_L22P_7
I/O
I/O
IO_L23N_7
IO_L23P_7
I/O
I/O
IO_L24N_7
I/O
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Spartan-3 FPGA Family: Pinout Descriptions
Table 96: FT256 Package Pinout (Cont’d)
XC3S200, XC3S400, XC3S1000 FT256 Pin
Bank
Type
Pin Name
Number
G4
H3
7
IO_L24P_7
IO_L39N_7
IO_L39P_7
I/O
I/O
7
7
H4
I/O
7
IO_L40N_7/VREF_7
IO_L40P_7
VCCO_7
VCCO_7
VCCO_7
GND
H1
VREF
I/O
7
G1
G6
H5
7
VCCO
VCCO
VCCO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
7
7
H6
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
A1
GND
A16
B2
GND
GND
B9
GND
B15
F6
GND
GND
F11
G7
G8
G9
G10
H2
GND
GND
GND
GND
GND
GND
H7
GND
H8
GND
H9
GND
H10
J7
GND
GND
J8
GND
J9
GND
J10
J15
K7
GND
GND
GND
K8
GND
K9
GND
K10
L6
GND
GND
L11
R2
GND
GND
R8
GND
R15
T1
GND
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Spartan-3 FPGA Family: Pinout Descriptions
Table 96: FT256 Package Pinout (Cont’d)
XC3S200, XC3S400, XC3S1000 FT256 Pin
Bank
Type
Pin Name
Number
T16
A6
N/A
N/A
GND
GND
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
CCLK
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
JTAG
N/A
A11
F1
N/A
N/A
F16
L1
N/A
N/A
L16
T6
N/A
N/A
T11
D4
N/A
N/A
D13
E5
N/A
N/A
E12
M5
N/A
N/A
M12
N4
N/A
N/A
N13
T15
R14
C4
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
DONE
HSWAP_EN
M0
P3
M1
T2
M2
P4
PROG_B
TCK
B3
C14
A2
TDI
JTAG
TDO
A15
C13
JTAG
TMS
JTAG
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Spartan-3 FPGA Family: Pinout Descriptions
User I/Os by Bank
Table 97 indicates how the available user-I/O pins are distributed between the eight I/O banks on the FT256 package.
Table 97: User I/Os Per Bank in FT256 Package
All Possible I/O Pins by Type
Package Edge
Top
I/O Bank
Maximum I/O
I/O
13
13
18
18
8
DUAL
DCI
2
VREF
GCLK
0
1
2
3
4
5
6
7
20
20
23
23
21
20
23
23
0
0
0
0
6
6
0
0
3
3
3
3
3
3
3
3
2
2
0
0
2
2
0
0
2
2
Right
2
2
Bottom
Left
7
2
18
18
2
2
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163
Spartan-3 FPGA Family: Pinout Descriptions
FT256 Footprint
X-Ref Target - Figure 49
Bank 0
Bank 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
I/O
L01P_0
VRN_0
I/O
L32P_0
GCLK6
I/O
L31N_1
VREF_1
I/O
I/O
IO
VREF_0
VCCAUX
VCCAUX
TDI
I/O
I/O
I/O
I/O
TDO
GND
A
GND
L10N_1 L01N_1
VREF_1 VRP_1
I/O
L01P_7
VRN_7
I/O
L01N_0
VRP_0
I/O
L32N_0
GCLK7
I/O
I/O
I/O
L01N_2
VRP_2
I/O
I/O
I/O
I/O
I/O
I/O
PROG_B
GND
I/O
GND
B
C
D
E
F
GND
L01P_1
L25P_0 L28P_0 L30P_0
L31P_1 L29N_1 L27N_1 L10P_1
VRN_1
I/O
L01N_7
VRP_7
I/O
L16P_7
VREF_7
I/O
I/O
L01P_2
VRN_2
I/O
L16N_7
I/O
I/O
I/O
I/O
I/O
I/O
L16N_2
HSWAP_
EN
I/O
TMS
TCK
L31P_0 L32N_1
VREF_0 GCLK5
L25N_0 L28N_0 L30N_0
L29P_1 L27P_1
I/O
I/O
I/O
L17P_2
VREF_2
IO
IO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCINT
VCCINT
I/O
L32P_1
VREF_0
VREF_1
L17N_7 L17P_7 L19P_7
L27P_0 L29P_0 L31N_0
L30N_1 L28N_1
L16P_2 L17N_2
GCLK4
I/O
L19N_7
VREF_7
I/O
I/O
I/O
L21P_7
I/O
I/O
I/O
I/O
I/O I/O
I/O
VCCO_0 VCCO_1
VCCINT
I/O
VCCINT
I/O
L20N_7 L20P_7
L27N_0 L29N_0
L30P_1 L28P_1
L19N_2 L19P_2 L20N_2 L20P_2
I/O
I/O
I/O
I/O
I/O
I/O
VCCAUX
VCCO_0 VCCO_0 VCCO_1 VCCO_1
VCCAUX
I/O
GND
GND
VCCO_7
L22N_7 L22P_7 L21N_7 L23P_7
L21N_2 L21P_2 L22N_2 L22P_2
I/O
L23N_2
VREF_2
I/O
L40P_7
I/O
I/O
I/O
I/O
I/O
I/O
VCCO_2
I/O
G
H
J
GND
GND
GND
GND
GND
GND
GND
GND
L24N_7 L24P_7 L23N_7
L23P_2 L24N_2 L24P_2
I/O
L40N_7
VREF_7
I/O
L40P_2
VREF_2
I/O
I/O
I/O
I/O
I/O
VCCO_7 VCCO_7
VCCO_2 VCCO_2
GND
I/O
L39N_7 L39P_7
L39N_2 L39P_2 L40N_2
I/O
L40P_6
VREF_6
I/O
L40N_3
VREF_3
I/O
I/O
I/O
I/O
VCCO_6 VCCO_6
I/O
VCCO_3 VCCO_3
I/O
GND
GND
GND
GND
GND
GND
GND
L40N_6 L39P_6 L39N_6
L39P_3 L39N_3
I/O
L24N_6
VREF_6
I/O
L24P_6
I/O
I/O
I/O
I/O
L40P_3
VCCO_6 GND
GND VCCO_3
I/O
I/O
I/O
K
L
L23P_6 L23N_6
L23N_3 L24P_3 L24N_3
I/O
L23P_3
VREF_3
I/O
I/O
I/O
I/O
I/O
I/O
VCCAUX
I/O
VCCO_5 VCCO_5 VCCO_4 VCCO_4
VCCAUX
GND
GND
L22P_6 L22N_6 L21P_6 L21N_6
L21N_3 L22P_3 L22N_3
I/O
L27N_4
DIN
I/O
L28P_5
D7
I/O
I/O
I/O
I/O
L30P_5
I/O
L29N_4
I/O I/O I/O
I/O
VCCO_5 VCCO_4
VCCINT
I/O
VCCINT
M
N
P
R
T
L20P_6 L20N_6 L19P_6 L19N_6
L21P_3 L19N_3 L20P_3 L20N_3
I/O
D0
I/O
L17P_6
VREF_6
I/O
L28N_5
D6
I/O
I/O
I/O
L27P_4
D1
IO
VREF_4
I/O
I/O
I/O
L30N_5
I/O
L29P_4
I/O
L19P_3
I/O
L17N_3
VCCINT
VCCINT
L32P_5 L31N_4
GCLK2 INIT_B
L17P_3
VREF_3
L17N_6 L16P_6
I/O
I/O
I/O
L01P_6
VRN_6
I/O
L29P_5
VREF_5
I/O
L30N_4
D2
I/O
L01N_3
VRP_3
IO
VREF_4
I/O
M0
I/O
L27P_5
I/O
I/O
I/O
I/O
L31P_4
L32N_5
DOUT
M2
I/O
I/O
L16N_6
L28N_4 L25N_4
L16P_3 L16N_3
GCLK3
BUSY
I/O
L01N_6
VRP_6
I/O
I/O
I/O
L31P_5
D5
I/O
I/O
I/O
L01N_4
VRP_4
I/O
L01P_3
VRN_3
I/O
L29N_5
I/O
I/O
GND
GND
DONE
I/O
GND
L01P_5 L10P_5 L27N_5
CS_B VRN_5 VREF_5
L32N_4 L30P_4
GCLK1
L28P_4 L25P_4
D3
I/O
I/O
I/O
L31N_5
D4
I/O
L32P_4
GCLK0
I/O
L01P_4
VRN_4
IO
VREF_5
IO
VREF_4
VCCAUX
VCCAUX
M1
I/O
I/O
CCLK
GND
L01N_5 L10N_5
RDWR_B VRP_5
GND
Bank 5
Bank 4
DS099-4_10_030503
Figure 49: FT256 Package Footprint (Top View)
DUAL: Configuration pin, then possible
VREF: User I/O or input voltage reference
113 I/O: Unrestricted, general-purpose user I/O 12
DCI: User I/O or reference resistor input for
24
user I/O
for bank
16
8
GCLK: User I/O or global clock buffer input 24 VCCO: Output voltage supply for bank
VCCINT: Internal core voltage supply
bank
7
CONFIG: Dedicated configuration pins
4
JTAG: Dedicated JTAG port pins
8
(+1.2V)
VCCAUX: Auxiliary voltage supply
(+2.5V)
0
N.C.: No unconnected pins in this package 32 GND: Ground
8
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Spartan-3 FPGA Family: Pinout Descriptions
FG320: 320-lead Fine-pitch Ball Grid Array
The 320-lead fine-pitch ball grid array package, FG320, supports three different Spartan-3 devices, including the XC3S400,
the XC3S1000, and the XC3S1500. The footprint for all three devices is identical, as shown in Table 98 and Figure 50.
The FG320 package is an 18 x 18 array of solder balls minus the four center balls.
All the package pins appear in Table 98 and are sorted by bank number, then by pin name. Pairs of pins that form a
differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type, as
defined earlier.
An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at
http://www.xilinx.com/support/documentation/data_ sheets/s3_pin.zip.
Pinout Table
Table 98: FG320 Package Pinout
XC3S400, XC3S1000, XC3S1500
Pin Name
FG320
Pin Number
Bank
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO
D9
E7
B3
D6
A2
A3
B4
C4
C5
D5
A4
A5
B5
B6
C7
D7
C8
D8
E8
F8
A7
A8
B9
A9
E9
F9
B8
C6
G8
I/O
I/O
IO
IO/VREF_0
IO/VREF_0
IO_L01N_0/VRP_0
IO_L01P_0/VRN_0
IO_L09N_0
IO_L09P_0
IO_L10N_0
IO_L10P_0
IO_L15N_0
IO_L15P_0
IO_L25N_0
IO_L25P_0
IO_L27N_0
IO_L27P_0
IO_L28N_0
IO_L28P_0
IO_L29N_0
IO_L29P_0
IO_L30N_0
IO_L30P_0
IO_L31N_0
IO_L31P_0/VREF_0
IO_L32N_0/GCLK7
IO_L32P_0/GCLK6
VCCO_0
VREF
VREF
DCI
DCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
GCLK
GCLK
VCCO
VCCO
VCCO
VCCO_0
VCCO_0
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Spartan-3 FPGA Family: Pinout Descriptions
Table 98: FG320 Package Pinout (Cont’d)
XC3S400, XC3S1000, XC3S1500
FG320
Pin Number
Bank
Type
Pin Name
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
VCCO_0
G9
VCCO
I/O
IO
A11
B13
D10
A12
A16
A17
A15
B15
C14
C15
A14
B14
D14
D13
E13
E12
C12
D12
F11
E11
C11
D11
A10
B10
E10
F10
B11
C13
G10
G11
J13
IO
I/O
IO
I/O
IO/VREF_1
IO_L01N_1/VRP_1
IO_L01P_1/VRN_1
IO_L10N_1/VREF_1
IO_L10P_1
IO_L15N_1
IO_L15P_1
IO_L16N_1
IO_L16P_1
IO_L24N_1
IO_L24P_1
IO_L27N_1
IO_L27P_1
IO_L28N_1
IO_L28P_1
IO_L29N_1
IO_L29P_1
IO_L30N_1
IO_L30P_1
IO_L31N_1/VREF_1
IO_L31P_1
IO_L32N_1/GCLK5
IO_L32P_1/GCLK4
VCCO_1
VREF
DCI
DCI
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
GCLK
GCLK
VCCO
VCCO
VCCO
VCCO
I/O
VCCO_1
VCCO_1
VCCO_1
IO
IO_L01N_2/VRP_2
IO_L01P_2/VRN_2
IO_L16N_2
IO_L16P_2
IO_L17N_2
IO_L17P_2/VREF_2
IO_L19N_2
IO_L19P_2
C16
C17
B18
C18
D17
D18
D16
E16
DCI
DCI
I/O
I/O
I/O
VREF
I/O
I/O
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Spartan-3 FPGA Family: Pinout Descriptions
Table 98: FG320 Package Pinout (Cont’d)
XC3S400, XC3S1000, XC3S1500
FG320
Pin Number
Bank
Type
Pin Name
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO_L20N_2
IO_L20P_2
E17
E18
F15
E15
F14
G14
G18
F17
G15
G16
H13
H14
H16
H15
H17
H18
J18
I/O
I/O
IO_L21N_2
IO_L21P_2
I/O
I/O
IO_L22N_2
IO_L22P_2
I/O
I/O
IO_L23N_2/VREF_2
IO_L23P_2
VREF
I/O
IO_L24N_2
IO_L24P_2
I/O
I/O
IO_L27N_2
IO_L27P_2
I/O
I/O
IO_L34N_2/VREF_2
IO_L34P_2
VREF
I/O
IO_L35N_2
IO_L35P_2
I/O
I/O
IO_L39N_2
IO_L39P_2
I/O
J17
I/O
IO_L40N_2
IO_L40P_2/VREF_2
VCCO_2
J15
I/O
J14
VREF
VCCO
VCCO
VCCO
I/O
F16
H12
J12
VCCO_2
VCCO_2
IO
K15
T17
T16
T18
U18
P16
R16
R17
R18
P18
P17
P15
N15
M14
N14
M15
M16
IO_L01N_3/VRP_3
IO_L01P_3/VRN_3
IO_L16N_3
IO_L16P_3
DCI
DCI
I/O
I/O
IO_L17N_3
IO_L17P_3/VREF_3
IO_L19N_3
IO_L19P_3
I/O
VREF
I/O
I/O
IO_L20N_3
IO_L20P_3
I/O
I/O
IO_L21N_3
IO_L21P_3
I/O
I/O
IO_L22N_3
IO_L22P_3
I/O
I/O
IO_L23N_3
IO_L23P_3/VREF_3
I/O
VREF
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Spartan-3 FPGA Family: Pinout Descriptions
Table 98: FG320 Package Pinout (Cont’d)
XC3S400, XC3S1000, XC3S1500
FG320
Pin Number
Bank
Type
Pin Name
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
IO_L24N_3
IO_L24P_3
M18
N17
L14
L13
L15
L16
L18
L17
K13
K14
K17
K18
K12
L12
N16
P12
V14
R10
U13
V17
U16
V16
P14
R14
U15
V15
T14
U14
R13
P13
T12
R12
V12
V11
R11
T11
N11
P11
U10
I/O
I/O
IO_L27N_3
IO_L27P_3
I/O
I/O
IO_L34N_3
IO_L34P_3/VREF_3
IO_L35N_3
IO_L35P_3
I/O
VREF
I/O
I/O
IO_L39N_3
IO_L39P_3
I/O
I/O
IO_L40N_3/VREF_3
IO_L40P_3
VREF
I/O
VCCO_3
VCCO
VCCO
VCCO
I/O
VCCO_3
VCCO_3
IO
IO
I/O
IO/VREF_4
IO/VREF_4
IO/VREF_4
IO_L01N_4/VRP_4
IO_L01P_4/VRN_4
IO_L06N_4/VREF_4
IO_L06P_4
VREF
VREF
VREF
DCI
DCI
VREF
I/O
IO_L09N_4
IO_L09P_4
I/O
I/O
IO_L10N_4
IO_L10P_4
I/O
I/O
IO_L25N_4
IO_L25P_4
I/O
I/O
IO_L27N_4/DIN/D0
IO_L27P_4/D1
IO_L28N_4
IO_L28P_4
DUAL
DUAL
I/O
I/O
IO_L29N_4
IO_L29P_4
I/O
I/O
IO_L30N_4/D2
IO_L30P_4/D3
IO_L31N_4/INIT_B
DUAL
DUAL
DUAL
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Spartan-3 FPGA Family: Pinout Descriptions
Table 98: FG320 Package Pinout (Cont’d)
XC3S400, XC3S1000, XC3S1500
FG320
Pin Number
Bank
Type
Pin Name
4
IO_L31P_4/
DOUT/BUSY
V10
DUAL
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6
6
IO_L32N_4/GCLK1
IO_L32P_4/GCLK0
VCCO_4
N10
P10
M10
M11
T13
U11
N8
P8
U6
R9
V3
V2
T5
GCLK
GCLK
VCCO
VCCO
VCCO
VCCO
I/O
VCCO_4
VCCO_4
VCCO_4
IO
IO
I/O
IO
I/O
IO/VREF_5
VREF
DUAL
DUAL
I/O
IO_L01N_5/RDWR_B
IO_L01P_5/CS_B
IO_L06N_5
IO_L06P_5
T4
I/O
IO_L10N_5/VRP_5
IO_L10P_5/VRN_5
IO_L15N_5
V4
U4
R6
R5
V5
U5
P6
P7
R7
T7
DCI
DCI
I/O
IO_L15P_5
I/O
IO_L16N_5
I/O
IO_L16P_5
I/O
IO_L27N_5/VREF_5
IO_L27P_5
VREF
I/O
IO_L28N_5/D6
IO_L28P_5/D7
IO_L29N_5
DUAL
DUAL
I/O
V8
V7
R8
T8
IO_L29P_5/VREF_5
IO_L30N_5
VREF
I/O
IO_L30P_5
I/O
IO_L31N_5/D4
IO_L31P_5/D5
IO_L32N_5/GCLK3
IO_L32P_5/GCLK2
VCCO_5
U9
V9
N9
P9
M8
M9
T6
DUAL
DUAL
GCLK
GCLK
VCCO
VCCO
VCCO
VCCO
I/O
VCCO_5
VCCO_5
VCCO_5
U8
K6
T3
IO
IO_L01N_6/VRP_6
DCI
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169
Spartan-3 FPGA Family: Pinout Descriptions
Table 98: FG320 Package Pinout (Cont’d)
XC3S400, XC3S1000, XC3S1500
FG320
Pin Number
Bank
Type
Pin Name
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
7
7
IO_L01P_6/VRN_6
IO_L16N_6
T2
U1
T1
R2
R1
R3
P3
P2
P1
N4
P4
N5
M5
M3
M4
N2
M1
L6
DCI
I/O
IO_L16P_6
I/O
IO_L17N_6
I/O
IO_L17P_6/VREF_6
IO_L19N_6
VREF
I/O
IO_L19P_6
I/O
IO_L20N_6
I/O
IO_L20P_6
I/O
IO_L21N_6
I/O
IO_L21P_6
I/O
IO_L22N_6
I/O
IO_L22P_6
I/O
IO_L23N_6
I/O
IO_L23P_6
I/O
IO_L24N_6/VREF_6
IO_L24P_6
VREF
I/O
IO_L27N_6
I/O
IO_L27P_6
L5
I/O
IO_L34N_6/VREF_6
IO_L34P_6
L3
VREF
I/O
L4
IO_L35N_6
L2
I/O
IO_L35P_6
L1
I/O
IO_L39N_6
K5
K4
K1
K2
K7
L7
I/O
IO_L39P_6
I/O
IO_L40N_6
I/O
IO_L40P_6/VREF_6
VCCO_6
VREF
VCCO
VCCO
VCCO
I/O
VCCO_6
VCCO_6
N3
J6
IO
IO_L01N_7/VRP_7
IO_L01P_7/VRN_7
IO_L16N_7
C3
C2
C1
B1
D1
D2
E3
D3
E2
DCI
DCI
I/O
IO_L16P_7/VREF_7
IO_L17N_7
VREF
I/O
IO_L17P_7
I/O
IO_L19N_7/VREF_7
IO_L19P_7
VREF
I/O
IO_L20N_7
I/O
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170
Spartan-3 FPGA Family: Pinout Descriptions
Table 98: FG320 Package Pinout (Cont’d)
XC3S400, XC3S1000, XC3S1500
FG320
Pin Number
Bank
Type
Pin Name
7
7
IO_L20P_7
IO_L21N_7
IO_L21P_7
IO_L22N_7
IO_L22P_7
IO_L23N_7
IO_L23P_7
IO_L24N_7
IO_L24P_7
IO_L27N_7
IO_L27P_7/VREF_7
IO_L34N_7
IO_L34P_7
IO_L35N_7
IO_L35P_7
IO_L39N_7
IO_L39P_7
IO_L40N_7/VREF_7
IO_L40P_7
VCCO_7
VCCO_7
VCCO_7
GND
E1
E4
I/O
I/O
7
F4
I/O
7
G5
F5
I/O
7
I/O
7
G1
F2
I/O
7
I/O
7
G4
G3
H5
H6
H4
H3
H1
H2
J1
I/O
7
I/O
7
I/O
7
VREF
I/O
7
7
I/O
7
I/O
7
I/O
7
I/O
7
J2
I/O
7
J5
VREF
I/O
7
J4
7
F3
VCCO
VCCO
VCCO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
7
H7
J7
7
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
A1
GND
A13
A18
A6
GND
GND
GND
B17
B2
GND
GND
C10
C9
F1
GND
GND
GND
F18
G12
G7
H10
H11
H8
H9
J11
J16
GND
GND
GND
GND
GND
GND
GND
GND
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171
Spartan-3 FPGA Family: Pinout Descriptions
Table 98: FG320 Package Pinout (Cont’d)
XC3S400, XC3S1000, XC3S1500
FG320
Pin Number
Bank
Type
Pin Name
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
GND
J3
J8
GND
GND
GND
GND
K11
K16
K3
GND
GND
GND
GND
GND
GND
K8
GND
GND
L10
L11
L8
GND
GND
GND
GND
GND
GND
L9
GND
GND
M12
M7
GND
GND
GND
GND
N1
GND
GND
N18
T10
T9
GND
GND
GND
GND
GND
GND
U17
U2
GND
GND
GND
GND
V1
GND
GND
V13
V18
V6
GND
GND
GND
GND
GND
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
B12
B7
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
G17
G2
M17
M2
U12
U7
F12
F13
F6
F7
G13
G6
M13
M6
N12
N13
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172
Spartan-3 FPGA Family: Pinout Descriptions
Table 98: FG320 Package Pinout (Cont’d)
XC3S400, XC3S1000, XC3S1500
FG320
Pin Number
Bank
Type
Pin Name
N/A
N/A
VCCINT
VCCINT
N6
N7
VCCINT
VCCINT
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
JTAG
VCCAUX CCLK
VCCAUX DONE
VCCAUX HSWAP_EN
VCCAUX M0
T15
R15
E6
P5
VCCAUX M1
U3
VCCAUX M2
R4
VCCAUX PROG_B
VCCAUX TCK
VCCAUX TDI
E5
E14
D4
JTAG
VCCAUX TDO
VCCAUX TMS
D15
B16
JTAG
JTAG
User I/Os by Bank
Table 99 indicates how the available user-I/O pins are distributed between the eight I/O banks on the FG320 package.
Table 99: User I/Os Per Bank in FG320 Package
All Possible I/O Pins by Type
Maximum
I/O
Maximum
Package Edge
Top
I/O Bank
LVDS Pairs
I/O
19
19
23
23
13
13
23
23
DUAL
DCI
2
VREF
GCLK
0
1
2
3
4
5
6
7
26
26
29
29
27
26
29
29
11
11
14
14
11
11
14
14
0
0
0
0
6
6
0
0
3
3
4
4
4
3
4
4
2
2
0
0
2
2
0
0
2
2
Right
2
2
Bottom
Left
2
2
2
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Spartan-3 FPGA Family: Pinout Descriptions
FG320 Footprint
X-Ref Target
-
Figure 50
Bank 0
Bank 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
GND
L01N_0
L01P_0
GND
L31P_0
L31N_1
L10N_1
L01N_1
L01P_1
A
B
C
D
E
F
VREF_1
L15N_0
L15P_0
L30N_0
L30P_0
L16N_1
VRP_0
VRN_0
VREF_0 VREF_1
VRP_1
VRN_1
VREF_1
I/O
L16P_7
VREF_7
I/O
L16P_1
I/O
L10P_1
I/O
L16N_2
I/O
VREF_0
I/O
L31N_0
I/O
L31P_1
I/O
L25P_0
I/O
L09N_0
I/O
L25N_0
VCCAUX
GND
GND
VCCO_0
VCCO_1
VCCAUX
I/O
TMS
I/O
L01P_7
VRN_7
I/O
L01N_7
VRP_7
I/O
L01N_2
VRP_2
I/O
L01P_2
VRN_2
I/O
L30N_1
I/O
L28N_1
I/O
L15N_1
I/O
L15P_1
I/O
L16P_2
I/O
L16N_7
I/O
L09P_0
I/O
L10N_0
I/O
L27N_0
I/O
L28N_0
VCCO_0
VCCO_1
GND
GND
I/O
L17P_2
VREF_2
I/O
L17N_7
I/O
L17P_7
I/O
L19P_7
I/O
L10P_0
I/O
VREF_0
I/O
L27P_0
I/O
L28P_0
I/O
L30P_1
I/O
L28P_1
I/O
L24P_1
I/O
L24N_1
I/O
L19N_2
I/O
L17N_2
TDI
I/O
I/O
TDO
I/O
L19N_7
VREF_7
I/O
L32N_0
GCLK7
I/O
L32N_1
GCLK5
I/O
L29N_0
I/O
L29P_1
I/O
L27P_1
I/O
L27N_1
I/O
L21P_2
I/O
L19P_2
I/O
L20N_2
I/O
L20P_2
I/O
L20P_7
I/O
L20N_7
I/O
L21N_7
HSWAP_
EN
PROG_B
I/O
TCK
I/O
L32P_0
GCLK6
I/O
L32P_1
GCLK4
I/O
L23P_7
I/O
L21P_7
I/O
L22P_7
I/O
L29P_0
I/O
L29N_1
I/O
L22N_2
I/O
L21N_2
I/O
L23P_2
VCCO_2
VCCO_7
VCCINT VCCINT
VCCINT VCCINT
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCAUX
VCCO_1 VCCO_1
VCCINT
GND
VCCINT
GND
VCCO_0 VCCO_0
L23N_2
G
H
J
VCCAUX
L23N_7
L24P_7
L24N_7
L22N_7
L22P_2
L24N_2
L24P_2
VREF_2
I/O
L27P_7
I/O
L34N_2
VREF_2
I/O
L35N_7
I/O
L35P_7
I/O
L34P_7
I/O
L34N_7
I/O
L27N_7
I/O
L27N_2
I/O
L27P_2
I/O
L34P_2
I/O
L35N_2
I/O
L35P_2
VCCO_2
VCCO_2
VCCO_3
VCCO_3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCCO_7
VCCO_7
VCCO_6
VCCO_6
VREF_7
I/O
L40N_7
VREF_7
I/O
L40P_2
VREF_2
I/O
L39N_7
I/O
L39P_7
I/O
L40P_7
I/O
L40N_2
I/O
L39P_2
I/O
L39N_2
GND
GND
GND
GND
I/O
I/O
I/O
I/O
L40P_6
VREF_6
I/O
L40N_3
VREF_3
I/O
L40N_6
I/O
L39P_6
I/O
L39N_6
I/O
L39N_3
I/O
L39P_3
I/O
L40P_3
I/O
K
L
I/O
L34N_6
VREF_6
I/O
L34P_3
VREF_3
I/O
L35P_6
I/O
L35N_6
I/O
L34P_6
I/O
L27P_6
I/O
L27N_6
I/O
L27P_3
I/O
L27N_3
I/O
L34N_3
I/O
L35P_3
I/O
L35N_3
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCO_5 VCCO_5 VCCO_4 VCCO_4
VCCINT
VCCAUX
VCCAUX
GND
GND
L23P_3
M
N
P
R
T
VCCINT
L24P_6
L23N_6
L23P_6
L22P_6
L22N_3
L23N_3
L24N_3
VREF_3
I/O
L24N_6
VREF_6
I/O
I/O
I/O
I/O
L21N_6
I/O
L22N_6
I/O
L22P_3
I/O
L21P_3
I/O
L24P_3
I/O
I/O
GND
GND
VCCINT VCCINT
L32N_5
L32N_4
L30N_4 VCCINT VCCINT
VCCO_3
VCCO_6
D2
GCLK3
GCLK1
I/O
I/O
I/O
L32P_5
GCLK2
I/O
L32P_4
GCLK0
I/O
L30P_4
D3
I/O
L06N_4
VREF_4
I/O
L20P_6
I/O
L20N_6
I/O
L19P_6
I/O
L21P_6
I/O
L25P_4
I/O
L21N_3
I/O
L17N_3
I/O
L20P_3
I/O
L20N_3
M0
I/O
L27N_5
L27P_5
VREF_5
I/O
L17P_6
VREF_6
I/O
I/O
I/O
L27P_4
D1
I/O
L17P_3
VREF_3
I/O
L17N_6
I/O
L19N_6
I/O
L15P_5
I/O
L30N_5
I/O
I/O
I/O
L29N_4
I/O
L25N_4
I/O
L06P_4
I/O
L19N_3
I/O
L19P_3
M2
DONE
CCLK
L28N_5
L15N_5
D6
VREF_5 VREF_4
I/O
L27N_4
DIN
I/O
L01P_6
VRN_6
I/O
L01N_6
VRP_6
I/O
L28P_5
D7
I/O
L01P_3
VRN_3
I/O
L01N_3
VRP_3
I/O
L16P_6
I/O
L06P_5
I/O
L06N_5
I/O
L30P_5
I/O
L29P_4
I/O
L10N_4
I/O
L16N_3
VCCO_5
I/O
GND
GND
VCCO_4
D0
I/O
L10P_5
VRN_5
I/O
L31N_5
D4
I/O
I/O
L01N_4
VRP_4
I/O
L16N_6
I/O
L16P_5
I/O
VREF_4
I/O
L10P_4
I/O
L09N_4
I/O
L16P_3
VCCAUX
VCCAUX
VCCO_5
VCCO_4
GND
M1
GND
L31N_4
U
V
INIT_B
I/O
I/O
L01P_5
CS_B
I/O
L01N_5
RDWR_B VRP_5
I/O
L10N_5
I/O
L29P_5
VREF_5
I/O
L31P_5
D5
I/O
L01P_4
VRN_4
I/O
L16N_5
I/O
L29N_5
I/O
L28P_4
I/O
L28N_4
I/O
L09P_4
I/O
VREF_4
L31P_4
DOUT
GND
I/O
GND
GND
GND
BUSY
Bank 5
Bank 4
ds099-3_16_121103
Figure 50: FG320 Package Footprint (Top View)
DUAL: Configuration pin, then possible
VREF: User I/O or input voltage reference
156 I/O: Unrestricted, general-purpose user I/O 12
DCI: User I/O or reference resistor input for
29
user I/O
for bank
16
8
GCLK: User I/O or global clock buffer input 28 VCCO: Output voltage supply for bank
VCCINT: Internal core voltage supply
bank
7
CONFIG: Dedicated configuration pins
4
JTAG: Dedicated JTAG port pins
12
(+1.2V)
VCCAUX: Auxiliary voltage supply
(+2.5V)
0
N.C.: No unconnected pins in this package 40 GND: Ground
8
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174
Spartan-3 FPGA Family: Pinout Descriptions
FG456: 456-lead Fine-pitch Ball Grid Array
The 456-lead fine-pitch ball grid array package, FG456, supports four different Spartan-3 devices, including the XC3S400,
the XC3S1000, the XC3S1500, and the XC3S2000. The footprints for the XC3S1000, the XC3S1500, and the XC3S2000
are identical, as shown in Table 100 and Figure 51. The XC3S400, however, has fewer I/O pins which consequently results
in 69 unconnected pins on the FG456 package, labeled as “N.C.” In Table 100 and Figure 51, these unconnected pins are
indicated with a black diamond symbol ().
All the package pins appear in Table 100 and are sorted by bank number, then by pin name. Pairs of pins that form a
differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type, as
defined earlier.
If there is a difference between the XC3S400 pinout and the pinout for the XC3S1000, the XC3S1500, or the XC3S2000,
then that difference is highlighted in Table 100. If the table entry is shaded grey, then there is an unconnected pin on the
XC3S400 that maps to a user-I/O pin on the XC3S1000, XC3S1500, and XC3S2000. If the table entry is shaded tan, then
the unconnected pin on the XC3S400 maps to a VREF-type pin on the XC3S1000, the XC3S1500, or the XC3S2000. If the
other VREF pins in the bank all connect to a voltage reference to support a special I/O standard, then also connect the N.C.
pin on the XC3S400 to the same VREF voltage. This provides maximum flexibility as you could potentially migrate a design
from the XC3S400 device to an XC3S1000, an XC3S1500, or an XC3S2000 FPGA without changing the printed circuit
board.
An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at
http://www.xilinx.com/support/documentation/data_ sheets/s3_pin.zip.
Pinout Table
Table 100: FG456 Package Pinout
3S400
Pin Name
3S1000, 3S1500, 3S2000
Pin Name
FG456
Pin Number
Bank
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO
IO
IO
IO
IO
A10
D9
D10
F6
I/O
I/O
IO
IO
I/O
IO
I/O
IO/VREF_0
IO/VREF_0
N.C. ()
IO/VREF_0
IO/VREF_0
IO/VREF_0
IO/VREF_0
IO_L01N_0/VRP_0
IO_L01P_0/VRN_0
IO_L06N_0
IO_L06P_0
IO_L09N_0
IO_L09P_0
IO_L10N_0
IO_L10P_0
IO_L15N_0
IO_L15P_0
IO_L16N_0
IO_L16P_0
IO_L19N_0
IO_L19P_0
A3
C7
E5
F7
VREF
VREF
VREF
VREF
DCI
DCI
I/O
IO/VREF_0
IO_L01N_0/VRP_0
IO_L01P_0/VRN_0
IO_L06N_0
IO_L06P_0
IO_L09N_0
IO_L09P_0
IO_L10N_0
IO_L10P_0
IO_L15N_0
IO_L15P_0
IO_L16N_0
IO_L16P_0
N.C. ()
B4
A4
D5
C5
B5
A5
E6
D6
C6
B6
E7
D7
B7
A7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
N.C. ()
I/O
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Spartan-3 FPGA Family: Pinout Descriptions
Table 100: FG456 Package Pinout (Cont’d)
3S400
Pin Name
3S1000, 3S1500, 3S2000
Pin Name
FG456
Pin Number
Bank
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
N.C. ()
IO_L22N_0
E8
D8
I/O
I/O
N.C. ()
IO_L22P_0
IO_L24N_0
IO_L24P_0
IO_L25N_0
IO_L25P_0
IO_L27N_0
IO_L27P_0
IO_L28N_0
IO_L28P_0
IO_L29N_0
IO_L29P_0
IO_L30N_0
IO_L30P_0
IO_L31N_0
IO_L31P_0/VREF_0
IO_L32N_0/GCLK7
IO_L32P_0/GCLK6
VCCO_0
IO_L24N_0
IO_L24P_0
IO_L25N_0
IO_L25P_0
IO_L27N_0
IO_L27P_0
IO_L28N_0
IO_L28P_0
IO_L29N_0
IO_L29P_0
IO_L30N_0
IO_L30P_0
IO_L31N_0
IO_L31P_0/VREF_0
IO_L32N_0/GCLK7
IO_L32P_0/GCLK6
VCCO_0
B8
I/O
A8
I/O
F9
I/O
E9
I/O
B9
I/O
A9
I/O
F10
E10
C10
B10
F11
E11
D11
C11
B11
A11
C8
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
GCLK
GCLK
VCCO
VCCO
VCCO
VCCO
VCCO
I/O
VCCO_0
VCCO_0
F8
VCCO_0
VCCO_0
G9
VCCO_0
VCCO_0
G10
G11
A12
E16
F12
F13
F16
F17
E13
F14
C19
B20
A19
B19
C18
D18
A18
B18
D17
VCCO_0
VCCO_0
IO
IO
IO
IO
I/O
IO
IO
I/O
IO
IO
I/O
IO
IO
I/O
IO
IO
I/O
IO/VREF_1
N.C. ()
IO/VREF_1
IO/VREF_1
IO_L01N_1/VRP_1
IO_L01P_1/VRN_1
IO_L06N_1/VREF_1
IO_L06P_1
IO_L09N_1
IO_L09P_1
IO_L10N_1/VREF_1
IO_L10P_1
IO_L15N_1
VREF
VREF
DCI
DCI
VREF
I/O
IO_L01N_1/VRP_1
IO_L01P_1/VRN_1
IO_L06N_1/VREF_1
IO_L06P_1
IO_L09N_1
IO_L09P_1
IO_L10N_1/VREF_1
IO_L10P_1
IO_L15N_1
I/O
I/O
VREF
I/O
I/O
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Product Specification
176
Spartan-3 FPGA Family: Pinout Descriptions
Table 100: FG456 Package Pinout (Cont’d)
3S400
Pin Name
3S1000, 3S1500, 3S2000
Pin Name
FG456
Pin Number
Bank
Type
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
IO_L15P_1
IO_L15P_1
E17
B17
C17
C16
D16
A16
B16
D15
E15
B15
A15
D14
E14
A14
B14
C13
D13
A13
B13
D12
E12
B12
C12
C15
F15
G12
G13
G14
C22
C20
C21
D20
D19
D21
D22
E18
F18
E19
E20
E21
I/O
I/O
IO_L16N_1
IO_L16P_1
N.C. ()
IO_L16N_1
IO_L16P_1
IO_L19N_1
IO_L19P_1
IO_L22N_1
IO_L22P_1
IO_L24N_1
IO_L24P_1
IO_L25N_1
IO_L25P_1
IO_L27N_1
IO_L27P_1
IO_L28N_1
IO_L28P_1
IO_L29N_1
IO_L29P_1
IO_L30N_1
IO_L30P_1
IO_L31N_1/VREF_1
IO_L31P_1
IO_L32N_1/GCLK5
IO_L32P_1/GCLK4
VCCO_1
I/O
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
IO_L24N_1
IO_L24P_1
IO_L25N_1
IO_L25P_1
IO_L27N_1
IO_L27P_1
IO_L28N_1
IO_L28P_1
IO_L29N_1
IO_L29P_1
IO_L30N_1
IO_L30P_1
IO_L31N_1/VREF_1
IO_L31P_1
IO_L32N_1/GCLK5
IO_L32P_1/GCLK4
VCCO_1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
GCLK
GCLK
VCCO
VCCO
VCCO
VCCO
VCCO
I/O
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
IO
IO
IO_L01N_2/VRP_2
IO_L01P_2/VRN_2
IO_L16N_2
IO_L16P_2
IO_L17N_2
IO_L17P_2/VREF_2
IO_L19N_2
IO_L19P_2
IO_L20N_2
IO_L20P_2
IO_L21N_2
IO_L01N_2/VRP_2
IO_L01P_2/VRN_2
IO_L16N_2
IO_L16P_2
IO_L17N_2
IO_L17P_2/VREF_2
IO_L19N_2
IO_L19P_2
IO_L20N_2
IO_L20P_2
IO_L21N_2
DCI
DCI
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
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Product Specification
177
Spartan-3 FPGA Family: Pinout Descriptions
Table 100: FG456 Package Pinout (Cont’d)
3S400
Pin Name
3S1000, 3S1500, 3S2000
Pin Name
FG456
Pin Number
Bank
Type
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
IO_L21P_2
IO_L21P_2
E22
G17
G18
F19
G19
F20
F21
G20
H19
G21
G22
H18
J17
H21
H22
J18
J19
J21
J22
K17
K18
K19
K20
K21
K22
L17
L18
L19
L20
L21
L22
H17
H20
J16
K16
L16
Y21
Y20
Y19
W22
I/O
I/O
IO_L22N_2
IO_L22P_2
IO_L23N_2/VREF_2
IO_L23P_2
IO_L24N_2
IO_L24P_2
N.C. ()
IO_L22N_2
IO_L22P_2
IO_L23N_2/VREF_2
IO_L23P_2
IO_L24N_2
IO_L24P_2
IO_L26N_2
IO_L26P_2
IO_L27N_2
IO_L27P_2
IO_L28N_2
IO_L28P_2
IO_L29N_2
IO_L29P_2
IO_L31N_2
IO_L31P_2
IO_L32N_2
IO_L32P_2
IO_L33N_2
IO_L33P_2
IO_L34N_2/VREF_2
IO_L34P_2
IO_L35N_2
IO_L35P_2
IO_L38N_2
IO_L38P_2
IO_L39N_2
IO_L39P_2
IO_L40N_2
IO_L40P_2/VREF_2
VCCO_2
I/O
VREF
I/O
I/O
I/O
I/O
N.C. ()
I/O
IO_L27N_2
IO_L27P_2
N.C. ()
I/O
I/O
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
IO_L34N_2/VREF_2
IO_L34P_2
IO_L35N_2
IO_L35P_2
IO_L38N_2
IO_L38P_2
IO_L39N_2
IO_L39P_2
IO_L40N_2
IO_L40P_2/VREF_2
VCCO_2
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
VCCO
VCCO
VCCO
VCCO
VCCO
I/O
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
IO
IO
IO_L01N_3/VRP_3
IO_L01P_3/VRN_3
IO_L16N_3
IO_L01N_3/VRP_3
IO_L01P_3/VRN_3
IO_L16N_3
DCI
DCI
I/O
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Product Specification
178
Spartan-3 FPGA Family: Pinout Descriptions
Table 100: FG456 Package Pinout (Cont’d)
3S400
Pin Name
3S1000, 3S1500, 3S2000
Pin Name
FG456
Pin Number
Bank
Type
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO_L16P_3
IO_L16P_3
Y22
V19
W19
W21
W20
U19
V20
V22
V21
T17
U18
U21
U20
R18
T18
T20
T19
T22
T21
R22
R21
P19
R19
P18
P17
P22
P21
N18
N17
N20
N19
N22
N21
M18
M17
M20
M19
M22
M21
M16
I/O
I/O
IO_L17N_3
IO_L17P_3/VREF_3
IO_L19N_3
IO_L19P_3
IO_L20N_3
IO_L20P_3
IO_L21N_3
IO_L21P_3
IO_L22N_3
IO_L22P_3
IO_L23N_3
IO_L23P_3/VREF_3
IO_L24N_3
IO_L24P_3
N.C. ()
IO_L17N_3
IO_L17P_3/VREF_3
IO_L19N_3
IO_L19P_3
IO_L20N_3
IO_L20P_3
IO_L21N_3
IO_L21P_3
IO_L22N_3
IO_L22P_3
IO_L23N_3
IO_L23P_3/VREF_3
IO_L24N_3
IO_L24P_3
IO_L26N_3
IO_L26P_3
IO_L27N_3
IO_L27P_3
IO_L28N_3
IO_L28P_3
IO_L29N_3
IO_L29P_3
IO_L31N_3
IO_L31P_3
IO_L32N_3
IO_L32P_3
IO_L33N_3
IO_L33P_3
IO_L34N_3
IO_L34P_3/VREF_3
IO_L35N_3
IO_L35P_3
IO_L38N_3
IO_L38P_3
IO_L39N_3
IO_L39P_3
IO_L40N_3/VREF_3
IO_L40P_3
VCCO_3
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
N.C. ()
I/O
IO_L27N_3
IO_L27P_3
N.C. ()
I/O
I/O
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
IO_L34N_3
IO_L34P_3/VREF_3
IO_L35N_3
IO_L35P_3
IO_L38N_3
IO_L38P_3
IO_L39N_3
IO_L39P_3
IO_L40N_3/VREF_3
IO_L40P_3
VCCO_3
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
VCCO
DS099 (v3.1) June 27, 2013
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Product Specification
179
Spartan-3 FPGA Family: Pinout Descriptions
Table 100: FG456 Package Pinout (Cont’d)
3S400
Pin Name
3S1000, 3S1500, 3S2000
Pin Name
FG456
Pin Number
Bank
Type
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
VCCO_3
VCCO_3
N16
P16
VCCO
VCCO
VCCO
VCCO
I/O
VCCO_3
VCCO_3
VCCO_3
VCCO_3
R17
VCCO_3
VCCO_3
R20
IO
IO
U16
IO
IO
U17
I/O
IO
IO
W13
W14
AB13
V18
I/O
IO
IO
I/O
IO/VREF_4
IO/VREF_4
IO/VREF_4
IO_L01N_4/VRP_4
IO_L01P_4/VRN_4
N.C. ()
IO/VREF_4
IO/VREF_4
IO/VREF_4
IO_L01N_4/VRP_4
IO_L01P_4/VRN_4
IO_L05N_4
IO_L05P_4
IO_L06N_4/VREF_4
IO_L06P_4
IO_L09N_4
IO_L09P_4
IO_L10N_4
IO_L10P_4
IO_L15N_4
IO_L15P_4
IO_L16N_4
IO_L16P_4
IO_L19N_4
IO_L19P_4
VREF
VREF
VREF
DCI
DCI
I/O
Y16
AA20
AB20
AA19
AB19
W18
Y18
N.C. ()
I/O
IO_L06N_4/VREF_4
IO_L06P_4
IO_L09N_4
IO_L09P_4
IO_L10N_4
IO_L10P_4
IO_L15N_4
IO_L15P_4
IO_L16N_4
IO_L16P_4
N.C. ()
VREF
I/O
AA18
AB18
V17
I/O
I/O
I/O
W17
Y17
I/O
I/O
AA17
V16
I/O
I/O
W16
AA16
AB16
V15
I/O
I/O
N.C. ()
I/O
N.C. ()
IO_L22N_4/
VREF_4
VREF
4
4
4
4
4
4
4
4
4
4
4
N.C. ()
IO_L22P_4
IO_L24N_4
IO_L24P_4
IO_L25N_4
IO_L25P_4
IO_L27N_4/DIN/D0
IO_L27P_4/D1
IO_L28N_4
IO_L28P_4
IO_L29N_4
IO_L29P_4
W15
AA15
AB15
U14
I/O
I/O
IO_L24N_4
IO_L24P_4
IO_L25N_4
IO_L25P_4
IO_L27N_4/DIN/D0
IO_L27P_4/D1
IO_L28N_4
IO_L28P_4
IO_L29N_4
IO_L29P_4
I/O
I/O
V14
I/O
AA14
AB14
U13
DUAL
DUAL
I/O
V13
I/O
Y13
I/O
AA13
I/O
DS099 (v3.1) June 27, 2013
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Product Specification
180
Spartan-3 FPGA Family: Pinout Descriptions
Table 100: FG456 Package Pinout (Cont’d)
3S400
Pin Name
3S1000, 3S1500, 3S2000
Pin Name
FG456
Pin Number
Bank
Type
4
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
IO_L30N_4/D2
IO_L30N_4/D2
U12
V12
W12
Y12
AA12
AB12
T12
T13
T14
U15
Y15
U7
DUAL
DUAL
DUAL
DUAL
GCLK
GCLK
VCCO
VCCO
VCCO
VCCO
VCCO
I/O
IO_L30P_4/D3
IO_L30P_4/D3
IO_L31N_4/INIT_B
IO_L31N_4/INIT_B
IO_L31P_4/DOUT/BUSY IO_L31P_4/DOUT/BUSY
IO_L32N_4/GCLK1
IO_L32P_4/GCLK0
VCCO_4
IO_L32N_4/GCLK1
IO_L32P_4/GCLK0
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
IO
IO
N.C. ()
IO
U9
I/O
IO
IO
U10
U11
V7
I/O
IO
IO
I/O
IO
IO
I/O
IO
IO
V10
AB11
U6
I/O
IO/VREF_5
IO/VREF_5
IO_L01N_5/RDWR_B
IO_L01P_5/CS_B
IO_L06N_5
IO_L06P_5
IO_L09N_5
IO_L09P_5
IO_L10N_5/VRP_5
IO_L10P_5/VRN_5
IO_L15N_5
IO_L15P_5
IO_L16N_5
IO_L16P_5
N.C. ()
IO/VREF_5
IO/VREF_5
IO_L01N_5/RDWR_B
IO_L01P_5/CS_B
IO_L06N_5
IO_L06P_5
IO_L09N_5
IO_L09P_5
IO_L10N_5/VRP_5
IO_L10P_5/VRN_5
IO_L15N_5
IO_L15P_5
IO_L16N_5
IO_L16P_5
IO_L19N_5
VREF
VREF
DUAL
DUAL
I/O
Y4
AA3
AB4
AA4
Y5
I/O
I/O
W5
I/O
AB5
AA5
W6
DCI
DCI
I/O
V6
I/O
AA6
Y6
I/O
I/O
Y7
I/O
N.C. ()
IO_L19P_5/
VREF_5
W7
VREF
5
5
5
5
5
5
N.C. ()
IO_L22N_5
IO_L22P_5
IO_L24N_5
IO_L24P_5
IO_L25N_5
IO_L25P_5
AB7
AA7
W8
I/O
I/O
I/O
I/O
I/O
I/O
N.C. ()
IO_L24N_5
IO_L24P_5
IO_L25N_5
IO_L25P_5
V8
AB8
AA8
DS099 (v3.1) June 27, 2013
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Product Specification
181
Spartan-3 FPGA Family: Pinout Descriptions
Table 100: FG456 Package Pinout (Cont’d)
3S400
3S1000, 3S1500, 3S2000
FG456
Bank
Type
Pin Name
Pin Name
IO_L27N_5/VREF_5
IO_L27P_5
Pin Number
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
IO_L27N_5/VREF_5
IO_L27P_5
W9
V9
VREF
I/O
IO_L28N_5/D6
IO_L28P_5/D7
IO_L29N_5
IO_L28N_5/D6
IO_L28P_5/D7
IO_L29N_5
AB9
AA9
Y10
W10
AB10
AA10
W11
V11
AA11
Y11
T9
DUAL
DUAL
I/O
IO_L29P_5/VREF_5
IO_L30N_5
IO_L29P_5/VREF_5
IO_L30N_5
VREF
I/O
IO_L30P_5
IO_L30P_5
I/O
IO_L31N_5/D4
IO_L31P_5/D5
IO_L32N_5/GCLK3
IO_L32P_5/GCLK2
VCCO_5
IO_L31N_5/D4
IO_L31P_5/D5
IO_L32N_5/GCLK3
IO_L32P_5/GCLK2
VCCO_5
DUAL
DUAL
GCLK
GCLK
VCCO
VCCO
VCCO
VCCO
VCCO
I/O
VCCO_5
VCCO_5
T10
T11
U8
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
Y8
IO
IO
Y1
IO_L01N_6/VRP_6
IO_L01P_6/VRN_6
IO_L16N_6
IO_L01N_6/VRP_6
IO_L01P_6/VRN_6
IO_L16N_6
Y3
DCI
DCI
I/O
Y2
W4
W3
W2
W1
V5
IO_L16P_6
IO_L16P_6
I/O
IO_L17N_6
IO_L17N_6
I/O
IO_L17P_6/VREF_6
IO_L19N_6
IO_L17P_6/VREF_6
IO_L19N_6
VREF
I/O
IO_L19P_6
IO_L19P_6
U5
I/O
IO_L20N_6
IO_L20N_6
V4
I/O
IO_L20P_6
IO_L20P_6
V3
I/O
IO_L21N_6
IO_L21N_6
V2
I/O
IO_L21P_6
IO_L21P_6
V1
I/O
IO_L22N_6
IO_L22N_6
T6
I/O
IO_L22P_6
IO_L22P_6
T5
I/O
IO_L23N_6
IO_L23N_6
U4
I/O
IO_L23P_6
IO_L23P_6
T4
I/O
IO_L24N_6/VREF_6
IO_L24P_6
IO_L24N_6/VREF_6
IO_L24P_6
U3
VREF
I/O
U2
N.C. ()
IO_L26N_6
T3
I/O
N.C. ()
IO_L26P_6
R4
I/O
IO_L27N_6
IO_L27N_6
T2
I/O
IO_L27P_6
IO_L27P_6
T1
I/O
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Spartan-3 FPGA Family: Pinout Descriptions
Table 100: FG456 Package Pinout (Cont’d)
3S400
Pin Name
3S1000, 3S1500, 3S2000
Pin Name
FG456
Pin Number
Bank
Type
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
N.C. ()
IO_L28N_6
R5
P6
R2
R1
P5
P4
P2
P1
N6
N5
N4
N3
N2
N1
M6
M5
M4
M3
M2
M1
M7
N7
P7
R3
R6
C2
C3
C4
D1
C1
E4
D4
D3
D2
F4
E3
E1
E2
G6
F5
I/O
I/O
N.C. ()
IO_L28P_6
IO_L29N_6
IO_L29P_6
IO_L31N_6
IO_L31P_6
IO_L32N_6
IO_L32P_6
IO_L33N_6
IO_L33P_6
IO_L34N_6/VREF_6
IO_L34P_6
IO_L35N_6
IO_L35P_6
IO_L38N_6
IO_L38P_6
IO_L39N_6
IO_L39P_6
IO_L40N_6
IO_L40P_6/VREF_6
VCCO_6
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
IO_L34N_6/VREF_6
IO_L34P_6
IO_L35N_6
IO_L35P_6
IO_L38N_6
IO_L38P_6
IO_L39N_6
IO_L39P_6
IO_L40N_6
IO_L40P_6/VREF_6
VCCO_6
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
VCCO
VCCO
VCCO
VCCO
VCCO
I/O
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
IO
IO
IO_L01N_7/VRP_7
IO_L01P_7/VRN_7
IO_L16N_7
IO_L16P_7/VREF_7
IO_L17N_7
IO_L17P_7
IO_L19N_7/VREF_7
IO_L19P_7
IO_L20N_7
IO_L20P_7
IO_L21N_7
IO_L21P_7
IO_L22N_7
IO_L22P_7
IO_L01N_7/VRP_7
IO_L01P_7/VRN_7
IO_L16N_7
IO_L16P_7/VREF_7
IO_L17N_7
IO_L17P_7
IO_L19N_7/VREF_7
IO_L19P_7
IO_L20N_7
IO_L20P_7
IO_L21N_7
IO_L21P_7
IO_L22N_7
IO_L22P_7
DCI
DCI
I/O
VREF
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
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Spartan-3 FPGA Family: Pinout Descriptions
Table 100: FG456 Package Pinout (Cont’d)
3S400
Pin Name
3S1000, 3S1500, 3S2000
Pin Name
FG456
Pin Number
Bank
Type
7
7
IO_L23N_7
IO_L23N_7
F2
F3
I/O
I/O
IO_L23P_7
IO_L24N_7
IO_L24P_7
N.C. ()
N.C. ()
IO_L27N_7
IO_L27P_7/VREF_7
N.C. ()
N.C. ()
N.C. ()
N.C. ()
N.C. ()
N.C. ()
N.C. ()
N.C. ()
N.C. ()
N.C. ()
IO_L34N_7
IO_L34P_7
IO_L35N_7
IO_L35P_7
IO_L38N_7
IO_L38P_7
IO_L39N_7
IO_L39P_7
IO_L40N_7/VREF_7
IO_L40P_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
GND
IO_L23P_7
IO_L24N_7
IO_L24P_7
IO_L26N_7
IO_L26P_7
IO_L27N_7
IO_L27P_7/VREF_7
IO_L28N_7
IO_L28P_7
IO_L29N_7
IO_L29P_7
IO_L31N_7
IO_L31P_7
IO_L32N_7
IO_L32P_7
IO_L33N_7
IO_L33P_7
IO_L34N_7
IO_L34P_7
IO_L35N_7
IO_L35P_7
IO_L38N_7
IO_L38P_7
IO_L39N_7
IO_L39P_7
IO_L40N_7/VREF_7
IO_L40P_7
VCCO_7
7
H5
G5
G3
G4
G1
G2
H1
H2
J4
I/O
7
I/O
7
I/O
7
I/O
7
I/O
7
VREF
I/O
7
7
I/O
7
I/O
7
H4
J5
I/O
7
I/O
7
J6
I/O
7
J1
I/O
7
J2
I/O
7
K5
K6
K3
K4
K1
K2
L5
I/O
7
I/O
7
I/O
7
I/O
7
I/O
7
I/O
7
I/O
7
L6
I/O
7
L3
I/O
7
L4
I/O
7
L1
VREF
I/O
7
L2
7
H3
H6
J7
VCCO
VCCO
VCCO
VCCO
VCCO
GND
GND
GND
GND
GND
GND
GND
7
VCCO_7
7
VCCO_7
7
VCCO_7
K7
L7
7
VCCO_7
N/A
N/A
N/A
N/A
N/A
N/A
N/A
GND
A1
A22
AA2
AA21
AB1
AB22
B2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
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Spartan-3 FPGA Family: Pinout Descriptions
Table 100: FG456 Package Pinout (Cont’d)
3S400
Pin Name
3S1000, 3S1500, 3S2000
Pin Name
FG456
Pin Number
Bank
Type
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
B21
C9
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
C14
J3
J9
J10
J11
J12
J13
J14
J20
K9
K10
K11
K12
K13
K14
L9
L10
L11
L12
L13
L14
M9
M10
M11
M12
M13
M14
N9
N10
N11
N12
N13
N14
P3
P9
P10
P11
P12
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Spartan-3 FPGA Family: Pinout Descriptions
Table 100: FG456 Package Pinout (Cont’d)
3S400
Pin Name
3S1000, 3S1500, 3S2000
Pin Name
FG456
Pin Number
Bank
Type
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
P13
P14
P20
Y9
GND
GND
GND
GND
Y14
A6
GND
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
CCLK
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
JTAG
A17
AB6
AB17
F1
F22
U1
U22
G7
G8
G15
G16
H7
H16
R7
R16
T7
T8
T15
T16
AA22
AB21
B3
VCCAUX CCLK
VCCAUX DONE
VCCAUX HSWAP_EN
VCCAUX M0
DONE
HSWAP_EN
M0
AB2
AA1
AB3
A2
VCCAUX M1
M1
VCCAUX M2
M2
VCCAUX PROG_B
VCCAUX TCK
VCCAUX TDI
PROG_B
TCK
A21
B1
TDI
JTAG
VCCAUX TDO
VCCAUX TMS
TDO
B22
A20
JTAG
TMS
JTAG
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Spartan-3 FPGA Family: Pinout Descriptions
User I/Os by Bank
Table 101 indicates how the available user-I/O pins are distributed between the eight I/O banks for the XC3S400 in the
FG456 package. Similarly, Table 102 shows how the available user-I/O pins are distributed between the eight I/O banks for
the XC3S1000, XC3S1500, and XC3S2000 in the FG456 package.
Table 101: User I/Os Per Bank for XC3S400 in FG456 Package
All Possible I/O Pins by Type
I/O
Edge
Top
Maximum I/O
Bank
I/O
27
27
25
25
21
21
25
25
DUAL
DCI
VREF
GCLK
0
1
2
3
4
5
6
7
35
35
31
31
35
35
31
31
0
0
0
0
6
6
0
0
2
4
4
4
4
4
4
4
4
2
2
0
0
2
2
0
0
2
2
Right
Bottom
Left
2
2
2
2
2
Table 102: User I/Os Per Bank for XC3S1000, XC3S1500, and XC3S2000 in FG456 Package
All Possible I/O Pins by Type
Edge
Top
I/O Bank
Maximum I/O
I/O
31
31
37
37
26
25
37
37
DUAL
DCI
2
VREF
GCLK
0
1
2
3
4
5
6
7
40
40
43
43
41
40
43
43
0
0
0
0
6
6
0
0
5
5
4
4
5
5
4
4
2
2
0
0
2
2
0
0
2
2
Right
Bottom
Left
2
2
2
2
2
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Spartan-3 FPGA Family: Pinout Descriptions
X-Ref Target - Figure 51
FG456 Footprint
Bank 0
1
2
3
4
5
6
7
8
9
10
11
Left Half of FG456
Package (Top View)
I/O
I/O
L01P_0
VRN_0
I/O
L32P_0
GCLK6
IO
I/O
I/O
I/O
L19P_0
PROG_B
VCCAUX
I/O
A
B
C
D
E
F
GND
VREF_0
L09P_0
L24P_0 L27P_0
I/O
L19N_0
I/O
L01N_0
VRP_0
I/O
L32N_0
GCLK7
HSWAP_
EN
I/O
I/O
I/O
I/O
I/O
XC3S400
(264 max. user I/O)
TDI
GND
L09N_0 L15P_0
L24N_0 L27N_0 L29P_0
I/O: Unrestricted,
general-purpose user I/O
I/O
L16P_7
VREF_7
I/O
I/O
I/O
L31P_0
VREF_0
196
IO
VREF_0
I/O
I/O
I/O
VCCO_0
I/O
I/O
GND
L01N_7 L01P_7
VRP_7 VRN_7
L06P_0 L15N_0
L29N_0
I/O
I/O
L22P_0
VREF: User I/O or input
32
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L31N_0
voltage reference for bank
I/O
I/O
L19N_7
VREF_7
L16N_7 L19P_7
L17P_7 L06N_0 L10P_0 L16P_0
IO
VREF_0
I/O
L22N_0
N.C.: Unconnected pins for
XC3S400 ()
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
69
L21N_7 L21P_7 L20P_7 L17N_7
L10N_0 L16N_0
L25P_0 L28P_0 L30P_0
IO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
XC3S1000, XC3S1500,
XC3S2000 (333 max user I/O)
VCCAUX
VCCO_0
VREF_0
L23N_7 L23P_7 L20N_7 L22P_7
L25N_0 L28N_0 L30N_0
I/O: Unrestricted,
I/O
L27P_7
VREF_7
261
I/O
I/O
I/O
I/O
I/O
general-purpose user I/O
VCCO_0 VCCO_0 VCCO_0
VCCINT VCCINT
VCCINT
G
H
J
L26N_7 L26P_7
L27N_7
L24P_7 L22N_7
I/O
I/O
I/O
L29P_7
VREF: User I/O or input
36
I/O
L24N_7
L28N_7 L28P_7
VCCO_7
VCCO_7
voltage reference for bank
I/O
I/O
I/O
I/O
I/O
N.C.: No unconnected pins
in this package
0
L32N_7 L32P_7
L29N_7 L31N_7 L31P_7
VCCO_7
GND
I/O
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
All devices
L33N_7 L33P_7
VCCO_7
K
L35N_7 L35P_7 L34N_7 L34P_7
DUAL: Configuration pin,
then possible user I/O
12
I/O
I/O
I/O
I/O
I/O
I/O
VCCO_7
L L40N_7
L40P_7 L39N_7 L39P_7 L38N_7 L38P_7
VREF_7
GCLK: User I/O or global
clock buffer input
8
I/O
M L40P_6
VREF_6
I/O
I/O
I/O
I/O
I/O
VCCO_6
L40N_6 L39P_6 L39N_6 L38P_6 L38N_6
DCI: User I/O or reference
16
I/O
I/O
I/O
L34N_6
VREF_6
resistor input for bank
I/O
I/O
I/O
L33P_6 L33N_6
VCCO_6
N
GND
GND
GND
GND
GND
GND
L35P_6 L35N_6 L34P_6
CONFIG: Dedicated
I/O
I/O
I/O
I/O
I/O
7
configuration pins
L32P_6 L32N_6
L31P_6 L31N_6 L28P_6
VCCO_6
GND
P
R
T
JTAG: Dedicated JTAG
port pins
I/O
I/O
I/O
I/O
4
L29P_6 L29N_6
L26P_6 L28N_6
VCCO_6
VCCO_6
VCCINT
I/O
L26N_6
VCCINT: Internal core
12
I/O
I/O
I/O
I/O
I/O
VCCO_5 VCCO_5 VCCO_5
I/O
VCCINT VCCINT
voltage supply (+1.2V)
L27P_6 L27N_6
L23P_6 L22P_6 L22N_6
I/O
L24N_6
VREF_6
IO
VCCO: Output voltage
supply for bank
I/O
L24P_6
I/O
I/O
VCCAUX
VCCO_5
I/O
I/O
I/O
I/O
40
U
V
VREF_5
I/O
L23N_6 L19P_6
I/O
L31P_5
D5
I/O
I/O
I/O
I/O I/O
I/O
VCCAUX:Auxiliaryvoltage
supply (+2.5V)
I/O
I/O
I/O
8
L21P_6 L21N_6 L20P_6 L20N_6 L19N_6 L15P_5
L24P_5 L27P_5
I/O
L19P_5
VREF_5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
W L17P_6
L27N_5 L29P_5 L31N_5
L17N_6 L16P_6 L16N_6 L09P_5 L15N_5
L24N_5
52 GND: Ground
VREF_6
VREF_5 VREF_5
D4
I/O
I/O
I/O
I/O
I/O
L32P_5
GCLK2
I/O
I/O
I/O
GND
L19N_5
VCCO_5
I/O
M1
Y
L01P_6 L01N_6 L01N_5
L09N_5 L16P_5
L29N_5
VRN_6 VRP_6 RDWR_B
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L32N_5
GCLK3
A
A
I/O
I/O
L22P_5
GND
M0
L01P_5
CS_B
L10P_5
L16N_5
VRN_5
L28P_5
L30P_5
D7
L06P_5
L25P_5
I/O
L22N_5
I/O
I/O
I/O
A
B
IO
VREF_5
I/O
I/O
L25N_5
VCCAUX
L10N_5
GND
M2
L28N_5
L30N_5
D6
L06N_5
VRP_5
Bank 5
DS099-4_11a_030203
Figure 51: FG456 Package Footprint (Top View)
DS099 (v3.1) June 27, 2013
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Product Specification
188
Spartan-3 FPGA Family: Pinout Descriptions
Bank 1
12
13
14
15
16
17
18
19
20
21
22
I/O
Right Half of FG456
Package (Top View)
I/O
I/O
I/O
I/O
I/O
L22N_1
VCCAUX
I/O
TMS
TCK
GND
L10N_1 L06N_1
VREF_1 VREF_1
A
B
C
L30N_1 L28N_1 L25P_1
I/O
L22P_1
I/O
L32N_1
GCLK5
I/O
L01P_1
VRN_1
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
TDO
L30P_1 L28P_1 L25N_1
L16N_1 L10P_1 L06P_1
I/O
L19N_1
I/O
L32P_1
GCLK4
I/O
I/O
I/O
I/O
I/O
VCCO_1
I/O
GND
I/O
I/O
I/O
L01N_1 L01N_2 L01P_2
VRP_1 VRP_2 VRN_2
L29N_1
I/O
L16P_1 L09N_1
I/O
L19P_1
I/O
L31N_1
VREF_1
I/O
I/O
I/O
I/O
I/O
L17P_2 D
L29P_1 L27N_1 L24N_1
L15N_1 L09P_1 L16P_2 L16N_2 L17N_2
VREF_2
IO
VREF_1
I/O
L31P_1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
E
L27P_1 L24P_1
L15P_1 L19N_2 L20N_2 L20P_2 L21N_2 L21P_2
IO
I/O
L23N_2
VREF_2
I/O
I/O
I/O
VREF_1
VCCO_1
VCCAUX
I/O
I/O
I/O
I/O
I/O
I/O
F
G
H
J
L19P_2
L24N_2 L24P_2
I/O
L26N_2
I/O
I/O
I/O
VCCO_1 VCCO_1 VCCO_1
VCCINT VCCINT
VCCINT
L22N_2 L22P_2 L23P_2
L27N_2 L27P_2
I/O
I/O
I/O
I/O
L28N_2 L26P_2
L29N_2 L29P_2
VCCO_2
I/O
VCCO_2
I/O
I/O
I/O
I/O
L28P_2 L31N_2 L31P_2
L32N_2 L32P_2
VCCO_2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
I/O
I/O
I/O
I/O
L34N_2
VREF_2
I/O
I/O
L33N_2 L33P_2
VCCO_2
K
L
L34P_2 L35N_2 L35P_2
I/O
I/O
I/O
I/O
I/O
I/O
VCCO_2
L40P_2
L38N_2 L38P_2 L39N_2 L39P_2 L40N_2
VREF_2
I/O
I/O
I/O
I/O
I/O
I/O
VCCO_3
L40N_3 M
L38P_3 L38N_3 L39P_3 L39N_3 L40P_3
VREF_3
I/O
I/O
I/O
L34P_3
VREF_3
I/O
I/O
I/O
L33P_3 L33N_3
VCCO_3
N
L34N_3 L35P_3 L35N_3
I/O
I/O
I/O
I/O
I/O
L31P_3 L31N_3 L29N_3
L32P_3 L32N_3
VCCO_3
GND
P
R
T
I/O
L29P_3
I/O
I/O
I/O
L24N_3
L28P_3 L28N_3
VCCO_3
VCCO_3
I/O
VCCINT
I/O
I/O
I/O
I/O
I/O
L26P_3 L26N_3
VCCO_4 VCCO_4 VCCO_4
I/O
VCCINT VCCINT
L22N_3 L24P_3
L27P_3 L27N_3
I/O
L23P_3
VREF_3
I/O
I/O
I/O
I/O
I/O
I/O
L23N_3
VCCO_4
VCCAUX
I/O
I/O
L30N_4
D2
U
V
W
Y
L28N_4 L25N_4
L22P_3 L20N_3
I/O
L22N_4
VREF_4
I/O
L22P_4
I/O
L30P_4
D3
IO
VREF_4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L28P_4 L25P_4
L16N_4 L10N_4
L17N_3 L20P_3 L21P_3 L21N_3
I/O
L31N_4
INIT_B
I/O
L31P_4
DOUT L29N_4
BUSY
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L06N_4 L17P_3
VREF_4 VREF_3
L16P_4 L10P_4
L19P_3 L19N_3 L16N_3
I/O
I/O
I/O
IO
VREF_4
I/O
I/O
L16P_3
VCCO_4
GND
I/O
L01P_3 L01N_3
VRN_3 VRP_3
L15N_4 L06P_4
I/O
L27N_4
DIN
I/O
L19N_4
I/O
L05N_4
I/O
L01N_4
VRP_4
A
A
I/O
I/O
L24N_4
I/O
I/O
GND
CCLK
L32N_4
L29P_4
GCLK1
L15P_4 L09N_4
D0
I/O
I/O
I/O
IO
I/O
L27P_4
D1
I/O
L01P_4
VRN_4
A
B
I/O
L24P_4
I/O
L09P_4
L19P_4
L05P_4
VCCAUX
DONE GND
L32P_4
VREF_4
GCLK0
Bank 4
DS099-4_11b_030503
Figure 52: FG456 Package Footprint (Top View) Continued
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
189
Spartan-3 FPGA Family: Pinout Descriptions
FG676: 676-lead Fine-pitch Ball Grid Array
The 676-lead fine-pitch ball grid array package, FG676, supports five different Spartan-3 devices, including the XC3S1000,
XC3S1500, XC3S2000, XC3S4000, and XC3S5000. All five have nearly identical footprints but are slightly different,
primarily due to unconnected pins on the XC3S1000 and XC3S1500. For example, because the XC3S1000 has fewer I/O
pins, this device has 98 unconnected pins on the FG676 package, labeled as “N.C.” In Table 103 and Figure 53, these
unconnected pins are indicated with a black diamond symbol (). The XC3S1500, however, has only two unconnected pins,
also labeled “N.C.” in the pinout table but indicated with a black square symbol ().
All the package pins appear in Table 103 and are sorted by bank number, then by pin name. Pairs of pins that form a
differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type, as
defined earlier.
If there is a difference between the XC3S1000, XC3S1500, XC3S2000, XC3S4000, and XC3S5000 pinouts, then that
difference is highlighted in Table 103. If the table entry is shaded grey, then there is an unconnected pin on either the
XC3S1000 or XC3S1500 that maps to a user-I/O pin on the XC3S2000, XC3S4000, and XC3S5000. If the table entry is
shaded tan, then the unconnected pin on either the XC3S1000 or XC3S1500 maps to a VREF-type pin on the XC3S2000,
XC3S4000, and XC3S5000. If the other VREF pins in the bank all connect to a voltage reference to support a special I/O
standard, then also connect the N.C. pin on the XC3S1000 or XC3S1500 to the same VREF voltage. This provides
maximum flexibility as you could potentially migrate a design from the XC3S1000 through to the XC3S5000 FPGA without
changing the printed circuit board.
An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at
http://www.xilinx.com/support/documentation/data_ sheets/s3_pin.zip.
Pinout Table
Table 103: FG676 Package Pinout
XC3S1000
Pin Name
XC3S1500
Pin Name
XC3S2000
Pin Name
XC3S4000
Pin Name
XC3S5000
Pin Name
FG676 Pin
Number
Bank
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO_L04N_0(3)
A3
A5
I/O
I/O
IO
IO
A6
I/O
IO_L04P_0(3)
IO_L13N_0(3)
IO
C4
C8
C12
E13
H11
H12
B3
I/O
I/O
N.C. ()
IO
I/O
IO
IO
I/O
IO
IO
I/O
IO
IO
I/O
IO/VREF_0
IO/VREF_0
IO/VREF_0
IO_L01N_0/VRP_0
IO_L01P_0/VRN_0
IO_L05N_0
IO/VREF_0
IO/VREF_0
IO/VREF_0
IO/VREF_0
IO/VREF_0
IO/VREF_0
IO_L01N_0/VRP_0
IO_L01P_0/VRN_0
IO_L05N_0
IO_L05P_0/VREF_0
IO_L06N_0
IO_L06P_0
IO_L07N_0
IO_L07P_0
IO_L08N_0
IO_L08P_0
VREF
VREF
VREF
DCI
DCI
I/O
IO/VREF_0
IO/VREF_0
IO/VREF_0
F7
IO/VREF_0
IO/VREF_0
IO/VREF_0
G10
E5
IO_L01N_0/VRP_0
IO_L01P_0/VRN_0
IO_L05N_0
IO_L01N_0/VRP_0
IO_L01P_0/VRN_0
IO_L05N_0
IO_L01N_0/VRP_0
IO_L01P_0/VRN_0
IO_L05N_0
D5
B4
IO_L05P_0/VREF_0 IO_L05P_0/VREF_0
IO_L05P_0/VREF_0
IO_L06N_0
IO_L05P_0/VREF_0
IO_L06N_0
A4
VREF
I/O
IO_L06N_0
IO_L06P_0
IO_L07N_0
IO_L07P_0
IO_L08N_0
IO_L08P_0
IO_L06N_0
IO_L06P_0
IO_L07N_0
IO_L07P_0
IO_L08N_0
IO_L08P_0
C5
B5
IO_L06P_0
IO_L06P_0
I/O
IO_L07N_0
IO_L07N_0
E6
I/O
IO_L07P_0
IO_L07P_0
D6
C6
B6
I/O
IO_L08N_0
IO_L08N_0
I/O
IO_L08P_0
IO_L08P_0
I/O
DS099 (v3.1) June 27, 2013
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Product Specification
190
Spartan-3 FPGA Family: Pinout Descriptions
Table 103: FG676 Package Pinout (Cont’d)
XC3S1000
Pin Name
XC3S1500
Pin Name
XC3S2000
Pin Name
XC3S4000
Pin Name
XC3S5000
Pin Name
FG676 Pin
Number
Bank
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO_L09N_0
IO_L09N_0
IO_L09N_0
IO_L09N_0
IO_L09N_0
E7
D7
I/O
I/O
IO_L09P_0
IO_L10N_0
IO_L10P_0
N.C. ()
IO_L09P_0
IO_L10N_0
IO_L10P_0
IO_L11N_0
IO_L11P_0
IO_L12N_0
IO_L12P_0
IO_L15N_0
IO_L15P_0
IO_L16N_0
IO_L16P_0
IO_L17N_0
IO_L17P_0
IO_L18N_0
IO_L18P_0
IO_L19N_0
IO_L19P_0
IO_L22N_0
IO_L22P_0
IO_L23N_0
IO_L23P_0
IO_L24N_0
IO_L24P_0
IO_L25N_0
IO_L25P_0
IO_L26N_0
IO_L26P_0/VREF_0
IO_L27N_0
IO_L27P_0
IO_L28N_0
IO_L28P_0
IO_L29N_0
IO_L29P_0
IO_L30N_0
IO_L30P_0
IO_L31N_0
IO_L09P_0
IO_L10N_0
IO_L10P_0
IO_L11N_0
IO_L11P_0
IO_L12N_0
IO_L12P_0
IO_L15N_0
IO_L15P_0
IO_L16N_0
IO_L16P_0
IO_L17N_0
IO_L17P_0
IO_L18N_0
IO_L18P_0
IO_L19N_0
IO_L19P_0
IO_L22N_0
IO_L22P_0
IO_L23N_0
IO_L23P_0
IO_L24N_0
IO_L24P_0
IO_L25N_0
IO_L25P_0
IO_L26N_0
IO_L26P_0/VREF_0
IO_L27N_0
IO_L27P_0
IO_L28N_0
IO_L28P_0
IO_L29N_0
IO_L29P_0
IO_L30N_0
IO_L30P_0
IO_L31N_0
IO_L31P_0/VREF_0
IO_L32N_0/GCLK7
IO_L32P_0/GCLK6
VCCO_0
IO_L09P_0
IO_L10N_0
IO_L10P_0
IO_L11N_0
IO_L11P_0
IO_L12N_0
IO_L12P_0
IO_L15N_0
IO_L15P_0
IO_L16N_0
IO_L16P_0
IO_L17N_0
IO_L17P_0
IO_L18N_0
IO_L18P_0
IO_L19N_0
IO_L19P_0
IO_L22N_0
IO_L22P_0
IO_L23N_0
IO_L23P_0
IO_L24N_0
IO_L24P_0
IO_L25N_0
IO_L25P_0
IO_L26N_0
IO_L26P_0/VREF_0
IO_L27N_0
IO_L27P_0
IO_L28N_0
IO_L28P_0
IO_L29N_0
IO_L29P_0
IO_L30N_0
IO_L30P_0
IO_L31N_0
IO_L31P_0/VREF_0
IO_L32N_0/GCLK7
IO_L32P_0/GCLK6
VCCO_0
IO_L09P_0
IO_L10N_0
IO_L10P_0
IO_L11N_0
IO_L11P_0
IO(3)
B7
I/O
A7
I/O
G8
I/O
F8
I/O
N.C. ()
E8
I/O
N.C. ()
IO(3)
D8
I/O
N.C. ()
IO_L15N_0
IO_L15P_0
IO_L16N_0
IO_L16P_0
N.C. ()
IO_L13P_0(3)
IO(3)
B8
I/O
A8
I/O
IO_L16N_0
IO_L16P_0
IO_L17N_0
IO_L17P_0
IO_L18N_0
IO_L18P_0
IO_L19N_0
IO_L19P_0
IO_L22N_0
IO_L22P_0
IO_L23N_0
IO_L23P_0
IO_L24N_0
IO_L24P_0
IO_L25N_0
IO_L25P_0
IO_L26N_0
IO_L26P_0/VREF_0
IO_L27N_0
IO_L27P_0
IO_L28N_0
IO_L28P_0
IO_L29N_0
IO_L29P_0
IO_L30N_0
IO_L30P_0
IO_L31N_0
IO_L31P_0/VREF_0
IO_L32N_0/GCLK7
IO_L32P_0/GCLK6
VCCO_0
G9
I/O
F9
I/O
E9
I/O
D9
I/O
N.C. ()
C9
I/O
N.C. ()
B9
I/O
N.C. ()
IO_L19N_0
IO_L19P_0
IO_L22N_0
IO_L22P_0
N.C. ()
F10
E10
D10
C10
B10
A10
G11
F11
E11
D11
B11
A11
G12
H13
F12
E12
B12
A12
G13
F13
D13
C13
B13
A13
C7
I/O
I/O
I/O
I/O
I/O
I/O
N.C. ()
IO_L24N_0
IO_L24P_0
IO_L25N_0
IO_L25P_0
N.C. ()
I/O
I/O
I/O
I/O
I/O
VREF
I/O
N.C. ()
IO_L27N_0
IO_L27P_0
IO_L28N_0
IO_L28P_0
IO_L29N_0
IO_L29P_0
IO_L30N_0
IO_L30P_0
IO_L31N_0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IO_L31P_0/VREF_0 IO_L31P_0/VREF_0
VREF
GCLK
GCLK
VCCO
VCCO
IO_L32N_0/GCLK7
IO_L32P_0/GCLK6
VCCO_0
IO_L32N_0/GCLK7
IO_L32P_0/GCLK6
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
C11
DS099 (v3.1) June 27, 2013
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Product Specification
191
Spartan-3 FPGA Family: Pinout Descriptions
Table 103: FG676 Package Pinout (Cont’d)
XC3S1000
Pin Name
XC3S1500
Pin Name
XC3S2000
Pin Name
XC3S4000
Pin Name
XC3S5000
Pin Name
FG676 Pin
Number
Bank
Type
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
H9
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
I/O
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
IO
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
IO
VCCO_0
VCCO_0
VCCO_0
H10
J11
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
J12
VCCO_0
VCCO_0
VCCO_0
J13
VCCO_0
VCCO_0
VCCO_0
K13
A14
A22
A23
D16
E18
F14
F20
G19
C15
C17
D18
D22
E22
B23
C23
E21
F21
B22
C22
C21
D21
A21
B21
D20
E20
A20
B20
E19
F19
C19
D19
A19
B19
F18
G18
B18
IO
IO
IO
IO
IO
IO
IO
IO
I/O
IO
IO
IO
IO
IO
I/O
IO
IO
IO
IO
IO
I/O
IO
IO
IO
IO
IO_L17P_1(3)
IO
I/O
IO
IO
IO
IO
I/O
IO
IO
IO
IO
IO
I/O
IO
IO
IO
IO
IO
I/O
IO/VREF_1
IO/VREF_1
N.C. ()
IO_L01N_1/VRP_1
IO_L01P_1/VRN_1
IO_L04N_1
IO_L04P_1
IO_L05N_1
IO_L05P_1
IO/VREF_1
IO/VREF_1
IO/VREF_1
IO_L01N_1/VRP_1
IO_L01P_1/VRN_1
IO_L04N_1
IO_L04P_1
IO_L05N_1
IO_L05P_1
IO/VREF_1
IO/VREF_1
IO/VREF_1
IO_L01N_1/VRP_1
IO_L01P_1/VRN_1
IO_L04N_1
IO_L04P_1
IO_L05N_1
IO_L05P_1
IO_L06N_1/VREF_1
IO_L06P_1
IO_L07N_1
IO_L07P_1
IO_L08N_1
IO_L08P_1
IO_L09N_1
IO_L09P_1
IO_L10N_1/VREF_1
IO_L10P_1
IO_L11N_1
IO_L11P_1
IO_L12N_1
IO_L12P_1
IO_L15N_1
IO_L15P_1
IO_L16N_1
IO_L16P_1
IO_L18N_1
IO/VREF_1
IO/VREF_1
IO/VREF_1
IO_L01N_1/VRP_1
IO_L01P_1/VRN_1
IO_L04N_1
IO_L04P_1
IO_L05N_1
IO_L05P_1
IO_L06N_1/VREF_1
IO_L06P_1
IO_L07N_1
IO_L07P_1
IO_L08N_1
IO_L08P_1
IO_L09N_1
IO_L09P_1
IO_L10N_1/VREF_1
IO_L10P_1
IO_L11N_1
IO_L11P_1
IO_L12N_1
IO_L12P_1
IO_L15N_1
IO_L15P_1
IO_L16N_1
IO_L16P_1
IO_L18N_1
IO/VREF_1
IO/VREF_1
IO_L17N_1/VREF_1(3)
IO_L01N_1/VRP_1
IO_L01P_1/VRN_1
IO_L04N_1
IO_L04P_1
IO_L05N_1
IO_L05P_1
IO_L06N_1/VREF_1
IO_L06P_1
IO_L07N_1
IO_L07P_1
IO_L08N_1
IO_L08P_1
IO_L09N_1
IO_L09P_1
IO_L10N_1/VREF_1
IO_L10P_1
IO_L11N_1
IO_L11P_1
IO_L12N_1
IO_L12P_1
IO_L15N_1
IO_L15P_1
IO_L16N_1
IO_L16P_1
IO(3)
VREF
VREF
VREF
DCI
DCI
I/O
I/O
I/O
I/O
IO_L06N_1/VREF_1 IO_L06N_1/VREF_1
VREF
I/O
IO_L06P_1
IO_L07N_1
IO_L07P_1
IO_L08N_1
IO_L08P_1
IO_L09N_1
IO_L09P_1
IO_L06P_1
IO_L07N_1
IO_L07P_1
IO_L08N_1
IO_L08P_1
IO_L09N_1
IO_L09P_1
I/O
I/O
I/O
I/O
I/O
I/O
IO_L10N_1/VREF_1 IO_L10N_1/VREF_1
VREF
I/O
IO_L10P_1
N.C. ()
IO_L10P_1
IO_L11N_1
IO_L11P_1
IO_L12N_1
IO_L12P_1
IO_L15N_1
IO_L15P_1
IO_L16N_1
IO_L16P_1
IO_L18N_1
I/O
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
IO_L15N_1
IO_L15P_1
IO_L16N_1
IO_L16P_1
N.C. ()
I/O
I/O
I/O
I/O
I/O
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
192
Spartan-3 FPGA Family: Pinout Descriptions
Table 103: FG676 Package Pinout (Cont’d)
XC3S1000
Pin Name
XC3S1500
Pin Name
XC3S2000
Pin Name
XC3S4000
Pin Name
XC3S5000
Pin Name
FG676 Pin
Number
Bank
Type
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
IO_L18P_1
IO_L18P_1
IO_L18P_1
IO(3)
C18
F17
G17
D17
E17
A17
B17
G16
H16
E16
F16
A16
B16
G15
H15
E15
F15
A15
B15
G14
H14
D14
E14
B14
C14
C16
C20
H17
H18
J14
I/O
I/O
N.C. ()
IO_L19N_1
IO_L19P_1
IO_L22N_1
IO_L22P_1
N.C. ()
IO_L19N_1
IO_L19P_1
IO_L22N_1
IO_L22P_1
IO_L23N_1
IO_L23P_1
IO_L24N_1
IO_L24P_1
IO_L25N_1
IO_L25P_1
IO_L26N_1
IO_L26P_1
IO_L27N_1
IO_L27P_1
IO_L28N_1
IO_L28P_1
IO_L29N_1
IO_L29P_1
IO_L30N_1
IO_L30P_1
IO_L19N_1
IO_L19P_1
IO_L22N_1
IO_L22P_1
IO_L23N_1
IO_L23P_1
IO_L24N_1
IO_L24P_1
IO_L25N_1
IO_L25P_1
IO_L26N_1
IO_L26P_1
IO_L27N_1
IO_L27P_1
IO_L28N_1
IO_L28P_1
IO_L29N_1
IO_L29P_1
IO_L30N_1
IO_L30P_1
IO_L31N_1/VREF_1
IO_L31P_1
IO_L32N_1/GCLK5
IO_L32P_1/GCLK4
VCCO_1
IO_L19N_1
IO_L19P_1
IO_L22N_1
IO_L22P_1
IO_L23N_1
IO_L23P_1
IO_L24N_1
IO_L24P_1
IO_L25N_1
IO_L25P_1
IO_L26N_1
IO_L26P_1
IO_L27N_1
IO_L27P_1
IO_L28N_1
IO_L28P_1
IO_L29N_1
IO_L29P_1
IO_L30N_1
IO_L30P_1
IO_L31N_1/VREF_1
IO_L31P_1
IO_L32N_1/GCLK5
IO_L32P_1/GCLK4
VCCO_1
IO_L19N_1
IO_L19P_1
IO_L22N_1
IO_L22P_1
IO_L23N_1
IO_L23P_1
IO_L24N_1
IO_L24P_1
IO_L25N_1
IO_L25P_1
IO_L26N_1
IO_L26P_1
IO_L27N_1
IO_L27P_1
IO_L28N_1
IO_L28P_1
IO_L29N_1
IO_L29P_1
IO_L30N_1
IO_L30P_1
IO_L31N_1/VREF_1
IO_L31P_1
IO_L32N_1/GCLK5
IO_L32P_1/GCLK4
VCCO_1
I/O
I/O
I/O
I/O
I/O
N.C. ()
IO_L24N_1
IO_L24P_1
IO_L25N_1
IO_L25P_1
N.C. ()
I/O
I/O
I/O
I/O
I/O
I/O
N.C. ()
IO_L27N_1
IO_L27P_1
IO_L28N_1
IO_L28P_1
IO_L29N_1
IO_L29P_1
IO_L30N_1
IO_L30P_1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IO_L31N_1/VREF_1 IO_L31N_1/VREF_1
VREF
I/O
IO_L31P_1
IO_L32N_1/GCLK5
IO_L32P_1/GCLK4
VCCO_1
IO_L31P_1
IO_L32N_1/GCLK5
IO_L32P_1/GCLK4
VCCO_1
GCLK
GCLK
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
I/O
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
J15
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
J16
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
K14
F22
C25
C26
E23
E24
D25
D26
E25
E26
IO
IO
IO
N.C. ()
N.C. ()
IO_L01N_2/VRP_2
IO_L01P_2/VRN_2
IO_L02N_2
IO_L02P_2
IO_L01N_2/VRP_2
IO_L01P_2/VRN_2
IO_L02N_2
IO_L02P_2
IO_L01N_2/VRP_2
IO_L01P_2/VRN_2
IO_L02N_2
IO_L02P_2
IO_L01N_2/VRP_2
IO_L01P_2/VRN_2
IO_L02N_2
IO_L02P_2
IO_L03N_2/VREF_2
IO_L03P_2
IO_L05N_2
IO_L05P_2
IO_L01N_2/VRP_2
IO_L01P_2/VRN_2
IO_L02N_2
IO_L02P_2
IO_L03N_2/VREF_2
IO_L03P_2
IO_L05N_2
IO_L05P_2
DCI
DCI
I/O
I/O
IO_L03N_2/VREF_2 IO_L03N_2/VREF_2(1) IO_L03N_2/VREF_2
VREF(1)
I/O
IO_L03P_2
N.C. ()
N.C. ()
IO_L03P_2
IO_L05N_2
IO_L05P_2
IO_L03P_2
IO_L05N_2
IO_L05P_2
I/O
I/O
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
193
Spartan-3 FPGA Family: Pinout Descriptions
Table 103: FG676 Package Pinout (Cont’d)
XC3S1000
Pin Name
XC3S1500
Pin Name
XC3S2000
Pin Name
XC3S4000
Pin Name
XC3S5000
Pin Name
FG676 Pin
Number
Bank
Type
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO_L06N_2
IO_L06N_2
IO_L06N_2
IO_L06N_2
G20
G21
F23
F24
G22
G23
F25
F26
G25
G26
H20
H21
H22
J21
I/O
I/O
N.C. ()
IO_L06P_2
IO_L07N_2
IO_L07P_2
IO_L08N_2
IO_L08P_2
IO_L06P_2
IO_L07N_2
IO_L07P_2
IO_L08N_2
IO_L08P_2
IO_L06P_2
IO_L06P_2
IO_L07N_2
IO_L07P_2
IO_L08N_2
IO_L08P_2
IO_L09N_2/VREF_2
IO_L09P_2
IO_L10N_2
IO_L10P_2
IO_L11N_2
IO_L11P_2
IO_L12N_2
IO_L12P_2
IO(3)
N.C. ()
N.C. ()
N.C. ()
N.C. ()
N.C. ()
N.C. ()
N.C. ()
N.C. ()
N.C. ()
IO_L14N_2
IO_L14P_2
IO_L16N_2
IO_L16P_2
IO_L17N_2
IO_L07N_2
I/O
IO_L07P_2
I/O
IO_L08N_2
I/O
IO_L08P_2
I/O
IO_L09N_2/VREF_2(1) IO_L09N_2/VREF_2
IO_L09N_2/VREF_2
IO_L09P_2
VREF(1)
I/O
IO_L09P_2
IO_L10N_2
IO_L10P_2
IO_L14N_2
IO_L14P_2
IO_L16N_2
IO_L16P_2
IO_L17N_2
IO_L09P_2
IO_L10N_2
IO_L10N_2
I/O
IO_L10P_2
IO_L10P_2
I/O
IO_L14N_2(2)
IO_L14P_2(2)
IO_L16N_2(2)
IO_L16P_2(2)
IO_L17N_2(2)
IO_L11N_2(2)
IO_L11P_2(2)
IO_L12N_2(2)
IO_L12P_2(2)
IO_L13N_2(2)
I/O
I/O
I/O
I/O
H23
H24
H25
H26
J20
I/O
IO_L17P_2/VREF_2 IO_L17P_2/VREF_2
IO_L17P_2(2)/VREF_2 IO_L13P_2(2)/VREF_2 IO/VREF_2(3)
VREF
I/O
IO_L19N_2
IO_L19P_2
IO_L20N_2
IO_L20P_2
IO_L21N_2
IO_L21P_2
IO_L22N_2
IO_L22P_2
IO_L19N_2
IO_L19P_2
IO_L20N_2
IO_L20P_2
IO_L21N_2
IO_L21P_2
IO_L22N_2
IO_L22P_2
IO_L19N_2
IO_L19P_2
IO_L20N_2
IO_L20P_2
IO_L21N_2
IO_L21P_2
IO_L22N_2
IO_L22P_2
IO_L23N_2/VREF_2
IO_L23P_2
IO_L24N_2
IO_L24P_2
IO_L26N_2
IO_L26P_2
IO_L27N_2
IO_L27P_2
IO_L28N_2
IO_L28P_2
IO_L29N_2
IO_L29P_2
IO_L31N_2
IO_L31P_2
IO_L32N_2
IO_L32P_2
IO_L33N_2
IO_L33P_2
IO_L19N_2
IO_L19P_2
IO_L20N_2
IO_L20P_2
IO_L21N_2
IO_L21P_2
IO_L22N_2
IO_L22P_2
IO_L23N_2/VREF_2
IO_L23P_2
IO_L24N_2
IO_L24P_2
IO_L26N_2
IO_L26P_2
IO_L27N_2
IO_L27P_2
IO_L28N_2
IO_L28P_2
IO_L29N_2
IO_L29P_2
IO_L31N_2
IO_L31P_2
IO_L32N_2
IO_L32P_2
IO_L33N_2
IO_L33P_2
IO_L19N_2
IO_L19P_2
IO_L20N_2
IO_L20P_2
IO_L21N_2
IO_L21P_2
IO_L22N_2
IO_L22P_2
IO_L23N_2/VREF_2
IO_L23P_2
IO_L24N_2
IO_L24P_2
IO_L26N_2
IO_L26P_2
IO_L27N_2
IO_L27P_2
IO_L28N_2
IO_L28P_2
IO_L29N_2
IO_L29P_2
IO_L31N_2
IO_L31P_2
IO_L32N_2
IO_L32P_2
IO_L33N_2
IO_L33P_2
I/O
I/O
K20
J22
I/O
I/O
J23
I/O
J24
I/O
J25
I/O
IO_L23N_2/VREF_2 IO_L23N_2/VREF_2
K21
K22
K23
K24
K25
K26
L19
L20
L21
L22
L25
L26
M19
M20
M21
M22
L23
M24
VREF
I/O
IO_L23P_2
IO_L24N_2
IO_L24P_2
IO_L26N_2
IO_L26P_2
IO_L27N_2
IO_L27P_2
IO_L28N_2
IO_L28P_2
IO_L29N_2
IO_L29P_2
IO_L31N_2
IO_L31P_2
IO_L32N_2
IO_L32P_2
IO_L33N_2
IO_L33P_2
IO_L23P_2
IO_L24N_2
IO_L24P_2
IO_L26N_2
IO_L26P_2
IO_L27N_2
IO_L27P_2
IO_L28N_2
IO_L28P_2
IO_L29N_2
IO_L29P_2
IO_L31N_2
IO_L31P_2
IO_L32N_2
IO_L32P_2
IO_L33N_2
IO_L33P_2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
194
Spartan-3 FPGA Family: Pinout Descriptions
Table 103: FG676 Package Pinout (Cont’d)
XC3S1000
Pin Name
XC3S1500
Pin Name
XC3S2000
Pin Name
XC3S4000
Pin Name
XC3S5000
Pin Name
FG676 Pin
Number
Bank
Type
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO_L34N_2/VREF_2 IO_L34N_2/VREF_2
IO_L34N_2/VREF_2
IO_L34P_2
IO_L35N_2
IO_L35P_2
IO_L38N_2
IO_L38P_2
IO_L39N_2
IO_L39P_2
IO_L40N_2
IO_L40P_2/VREF_2
VCCO_2
IO_L34N_2/VREF_2
IO_L34P_2
IO_L35N_2
IO_L35P_2
IO_L38N_2
IO_L38P_2
IO_L39N_2
IO_L39P_2
IO_L40N_2
IO_L40P_2/VREF_2
VCCO_2
IO_L34N_2/VREF_2
IO_L34P_2
IO_L35N_2
IO_L35P_2
IO_L38N_2
IO_L38P_2
IO_L39N_2
IO_L39P_2
IO_L40N_2
IO_L40P_2/VREF_2
VCCO_2
M25
M26
N19
VREF
I/O
IO_L34P_2
IO_L35N_2
IO_L35P_2
IO_L38N_2
IO_L38P_2
IO_L39N_2
IO_L39P_2
IO_L40N_2
IO_L34P_2
IO_L35N_2
IO_L35P_2
IO_L38N_2
IO_L38P_2
IO_L39N_2
IO_L39P_2
IO_L40N_2
I/O
N20
I/O
N21
I/O
N22
I/O
N23
I/O
N24
I/O
N25
I/O
IO_L40P_2/VREF_2 IO_L40P_2/VREF_2
N26
VREF
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
DCI
DCI
VREF
I/O
VCCO_2
VCCO_2
G24
J19
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
K19
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
L18
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
L24
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
M18
N17
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
N18
IO_L01N_3/VRP_3
IO_L01P_3/VRN_3
IO_L01N_3/VRP_3
IO_L01P_3/VRN_3
IO_L01N_3/VRP_3
IO_L01P_3/VRN_3
IO_L02N_3/VREF_3
IO_L02P_3
IO_L03N_3
IO_L03P_3
IO_L05N_3
IO_L05P_3
IO_L06N_3
IO_L06P_3
IO_L07N_3
IO_L07P_3
IO_L08N_3
IO_L08P_3
IO_L09N_3
IO_L09P_3/VREF_3
IO_L10N_3
IO_L10P_3
IO_L14N_3
IO_L14P_3
IO_L16N_3
IO_L16P_3
IO_L17N_3
IO_L17P_3/VREF_3
IO_L01N_3/VRP_3
IO_L01P_3/VRN_3
IO_L02N_3/VREF_3
IO_L02P_3
IO_L03N_3
IO_L03P_3
IO_L05N_3
IO_L05P_3
IO_L06N_3
IO_L06P_3
IO_L07N_3
IO_L07P_3
IO_L08N_3
IO_L08P_3
IO_L09N_3
IO_L09P_3/VREF_3
IO_L10N_3
IO_L10P_3
IO_L14N_3
IO_L14P_3
IO_L16N_3
IO_L16P_3
IO_L17N_3
IO_L17P_3/VREF_3
IO_L01N_3/VRP_3
IO_L01P_3/VRN_3
IO_L02N_3/VREF_3
IO_L02P_3
IO_L03N_3
IO_L03P_3
IO_L05N_3
IO_L05P_3
IO_L06N_3
IO_L06P_3
IO_L07N_3
IO_L07P_3
IO_L08N_3
IO_L08P_3
IO_L09N_3
IO_L09P_3/VREF_3
IO_L10N_3
IO_L10P_3
IO_L14N_3
IO_L14P_3
IO_L16N_3
IO_L16P_3
IO_L17N_3
IO_L17P_3/VREF_3
AA22
AA21
AB24
AB23
AC26
AC25
Y21
IO_L02N_3/VREF_3 IO_L02N_3/VREF_3
IO_L02P_3
IO_L03N_3
IO_L03P_3
N.C. ()
IO_L02P_3
IO_L03N_3
IO_L03P_3
IO_L05N_3
IO_L05P_3
IO_L06N_3
IO_L06P_3
IO_L07N_3
IO_L07P_3
IO_L08N_3
IO_L08P_3
IO_L09N_3
IO_L09P_3/VREF_3
IO_L10N_3
IO_L10P_3
IO_L14N_3
IO_L14P_3
IO_L16N_3
IO_L16P_3
IO_L17N_3
I/O
I/O
I/O
Y20
I/O
N.C. ()
AB26
AB25
AA24
AA23
Y23
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
Y22
I/O
N.C. ()
AA26
AA25
W21
W20
Y26
I/O
N.C. ()
VREF
I/O
N.C. ()
N.C. ()
I/O
N.C. ()
IO_L14N_3
IO_L14P_3
IO_L16N_3
IO_L16P_3
IO_L17N_3
I/O
Y25
I/O
V21
I/O
W22
W24
W23
I/O
I/O
IO_L17P_3/VREF_3 IO_L17P_3/VREF_3
VREF
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
195
Spartan-3 FPGA Family: Pinout Descriptions
Table 103: FG676 Package Pinout (Cont’d)
XC3S1000
Pin Name
XC3S1500
Pin Name
XC3S2000
Pin Name
XC3S4000
Pin Name
XC3S5000
Pin Name
FG676 Pin
Number
Bank
Type
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO_L19N_3
IO_L19N_3
IO_L19N_3
IO_L19N_3
IO_L19N_3
W26
W25
U20
V20
V23
V22
V25
V24
U22
U21
U24
U23
U26
U25
T20
T19
T22
T21
T26
T25
R20
R19
R22
R21
R24
T23
R26
R25
P20
P19
P22
P21
P24
P23
P26
P25
P17
P18
R18
T18
T24
U19
V19
I/O
I/O
IO_L19P_3
IO_L20N_3
IO_L20P_3
IO_L21N_3
IO_L21P_3
IO_L22N_3
IO_L22P_3
IO_L23N_3
IO_L19P_3
IO_L20N_3
IO_L20P_3
IO_L21N_3
IO_L21P_3
IO_L22N_3
IO_L22P_3
IO_L23N_3
IO_L19P_3
IO_L20N_3
IO_L20P_3
IO_L21N_3
IO_L21P_3
IO_L22N_3
IO_L22P_3
IO_L23N_3
IO_L23P_3/VREF_3
IO_L24N_3
IO_L24P_3
IO_L26N_3
IO_L26P_3
IO_L27N_3
IO_L27P_3
IO_L28N_3
IO_L28P_3
IO_L29N_3
IO_L29P_3
IO_L31N_3
IO_L31P_3
IO_L32N_3
IO_L32P_3
IO_L33N_3
IO_L33P_3
IO_L34N_3
IO_L34P_3/VREF_3
IO_L35N_3
IO_L35P_3
IO_L38N_3
IO_L38P_3
IO_L39N_3
IO_L39P_3
IO_L40N_3/VREF_3
IO_L40P_3
VCCO_3
IO_L19P_3
IO_L20N_3
IO_L20P_3
IO_L21N_3
IO_L21P_3
IO_L22N_3
IO_L22P_3
IO_L23N_3
IO_L23P_3/VREF_3
IO_L24N_3
IO_L24P_3
IO_L26N_3
IO_L26P_3
IO_L27N_3
IO_L27P_3
IO_L28N_3
IO_L28P_3
IO_L29N_3
IO_L29P_3
IO_L31N_3
IO_L31P_3
IO_L32N_3
IO_L32P_3
IO_L33N_3
IO_L33P_3
IO_L34N_3
IO_L34P_3/VREF_3
IO_L35N_3
IO_L35P_3
IO_L38N_3
IO_L38P_3
IO_L39N_3
IO_L39P_3
IO_L40N_3/VREF_3
IO_L40P_3
VCCO_3
IO_L19P_3
IO_L20N_3
IO_L20P_3
IO_L21N_3
IO_L21P_3
IO_L22N_3
IO_L22P_3
IO_L23N_3
IO_L23P_3/VREF_3
IO_L24N_3
IO_L24P_3
IO_L26N_3
IO_L26P_3
IO_L27N_3
IO_L27P_3
IO_L28N_3
IO_L28P_3
IO_L29N_3
IO_L29P_3
IO_L31N_3
IO_L31P_3
IO_L32N_3
IO_L32P_3
IO_L33N_3
IO_L33P_3
IO_L34N_3
IO_L34P_3/VREF_3
IO_L35N_3
IO_L35P_3
IO_L38N_3
IO_L38P_3
IO_L39N_3
IO_L39P_3
IO_L40N_3/VREF_3
IO_L40P_3
VCCO_3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IO_L23P_3/VREF_3 IO_L23P_3/VREF_3
VREF
I/O
IO_L24N_3
IO_L24P_3
IO_L26N_3
IO_L26P_3
IO_L27N_3
IO_L27P_3
IO_L28N_3
IO_L28P_3
IO_L29N_3
IO_L29P_3
IO_L31N_3
IO_L31P_3
IO_L32N_3
IO_L32P_3
IO_L33N_3
IO_L33P_3
IO_L34N_3
IO_L24N_3
IO_L24P_3
IO_L26N_3
IO_L26P_3
IO_L27N_3
IO_L27P_3
IO_L28N_3
IO_L28P_3
IO_L29N_3
IO_L29P_3
IO_L31N_3
IO_L31P_3
IO_L32N_3
IO_L32P_3
IO_L33N_3
IO_L33P_3
IO_L34N_3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IO_L34P_3/VREF_3 IO_L34P_3/VREF_3
VREF
I/O
IO_L35N_3
IO_L35P_3
IO_L38N_3
IO_L38P_3
IO_L39N_3
IO_L39P_3
IO_L35N_3
IO_L35P_3
IO_L38N_3
IO_L38P_3
IO_L39N_3
IO_L39P_3
I/O
I/O
I/O
I/O
I/O
IO_L40N_3/VREF_3 IO_L40N_3/VREF_3
VREF
I/O
IO_L40P_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
IO_L40P_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
196
Spartan-3 FPGA Family: Pinout Descriptions
Table 103: FG676 Package Pinout (Cont’d)
XC3S1000
Pin Name
XC3S1500
Pin Name
XC3S2000
Pin Name
XC3S4000
Pin Name
XC3S5000
Pin Name
FG676 Pin
Number
Bank
Type
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
Y24
VCCO
I/O
IO
IO
IO
IO
IO
AA20
AD15
AD19
AD23
AF21
AF22
W15
IO
IO
IO
IO
IO
I/O
IO
IO
IO
IO
I/O
N.C. ()
IO
IO
IO
IO
IO
I/O
IO
IO
IO
IO
IO
I/O
IO
IO
IO
IO
IO
I/O
IO
IO
IO
IO
IO
I/O
IO
IO
IO
IO
IO
W16
I/O
IO/VREF_4
IO/VREF_4
IO/VREF_4
IO_L01N_4/VRP_4
IO_L01P_4/VRN_4
IO_L04N_4
IO_L04P_4
IO_L05N_4
IO_L05P_4
IO/VREF_4
IO/VREF_4
IO/VREF_4
IO_L01N_4/VRP_4
IO_L01P_4/VRN_4
IO_L04N_4
IO_L04P_4
IO_L05N_4
IO_L05P_4
IO/VREF_4
IO/VREF_4
IO/VREF_4
IO_L01N_4/VRP_4
IO_L01P_4/VRN_4
IO_L04N_4
IO_L04P_4
IO_L05N_4
IO_L05P_4
IO_L06N_4/VREF_4
IO_L06P_4
IO_L07N_4
IO_L07P_4
IO_L08N_4
IO_L08P_4
IO_L09N_4
IO_L09P_4
IO_L10N_4
IO_L10P_4
IO_L11N_4
IO_L11P_4
IO_L12N_4
IO_L12P_4
IO_L15N_4
IO_L15P_4
IO_L16N_4
IO_L16P_4
IO_L17N_4
IO_L17P_4
IO_L18N_4
IO_L18P_4
IO_L19N_4
IO_L19P_4
IO/VREF_4
IO/VREF_4
IO/VREF_4
IO_L01N_4/VRP_4
IO_L01P_4/VRN_4
IO_L04N_4
IO_L04P_4
IO_L05N_4
IO_L05P_4
IO_L06N_4/VREF_4
IO_L06P_4
IO_L07N_4
IO_L07P_4
IO_L08N_4
IO_L08P_4
IO_L09N_4
IO_L09P_4
IO_L10N_4
IO_L10P_4
IO_L11N_4
IO_L11P_4
IO_L12N_4
IO_L12P_4
IO_L15N_4
IO_L15P_4
IO_L16N_4
IO_L16P_4
IO_L17N_4
IO_L17P_4
IO_L18N_4
IO_L18P_4
IO_L19N_4
IO_L19P_4
IO/VREF_4
IO/VREF_4
IO/VREF_4
IO_L01N_4/VRP_4
IO_L01P_4/VRN_4
IO_L04N_4
IO_L04P_4
IO_L05N_4
IO_L05P_4
IO_L06N_4/VREF_4
IO_L06P_4
IO_L07N_4
IO_L07P_4
IO_L08N_4
IO_L08P_4
IO_L09N_4
IO_L09P_4
IO_L10N_4
IO_L10P_4
IO_L11N_4
IO_L11P_4
IO_L12N_4
IO_L12P_4
IO_L15N_4
IO_L15P_4
IO_L16N_4
IO_L16P_4
IO_L17N_4
IO_L17P_4
IO_L18N_4
IO_L18P_4
IO_L19N_4
IO_L19P_4
AB14
AD25
Y17
VREF
VREF
VREF
DCI
DCI
I/O
AB22
AC22
AE24
AF24
AE23
AF23
AD22
AE22
AB21
AC21
AD21
AE21
AB20
AC20
AE20
AF20
Y19
I/O
I/O
I/O
IO_L06N_4/VREF_4 IO_L06N_4/VREF_4
VREF
I/O
IO_L06P_4
IO_L07N_4
IO_L07P_4
IO_L08N_4
IO_L08P_4
IO_L09N_4
IO_L09P_4
IO_L10N_4
IO_L10P_4
N.C. ()
IO_L06P_4
IO_L07N_4
IO_L07P_4
IO_L08N_4
IO_L08P_4
IO_L09N_4
IO_L09P_4
IO_L10N_4
IO_L10P_4
IO_L11N_4
IO_L11P_4
IO_L12N_4
IO_L12P_4
IO_L15N_4
IO_L15P_4
IO_L16N_4
IO_L16P_4
IO_L17N_4
IO_L17P_4
IO_L18N_4
IO_L18P_4
IO_L19N_4
IO_L19P_4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AA19
AB19
AC19
AE19
AF19
Y18
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
IO_L15N_4
IO_L15P_4
IO_L16N_4
IO_L16P_4
N.C. ()
I/O
I/O
I/O
AA18
AB18
AC18
AD18
AE18
AC17
AA17
I/O
I/O
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
IO_L19N_4
IO_L19P_4
I/O
I/O
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
197
Spartan-3 FPGA Family: Pinout Descriptions
Table 103: FG676 Package Pinout (Cont’d)
XC3S1000
Pin Name
XC3S1500
Pin Name
XC3S2000
Pin Name
XC3S4000
Pin Name
XC3S5000
Pin Name
FG676 Pin
Number
Bank
Type
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
IO_L22N_4/VREF_4 IO_L22N_4/VREF_4
IO_L22N_4/VREF_4
IO_L22P_4
IO_L22N_4/VREF_4
IO_L22P_4
IO_L22N_4/VREF_4
IO_L22P_4
AD17
AB17
AE17
AF17
Y16
VREF
I/O
IO_L22P_4
N.C. ()
IO_L22P_4
IO_L23N_4
IO_L23N_4
IO_L23N_4
IO_L23N_4
I/O
IO_L23P_4
IO_L23P_4
IO_L23P_4
IO_L23P_4
I/O
N.C. ()
IO_L24N_4
IO_L24P_4
IO_L25N_4
IO_L25P_4
N.C. ()
IO_L24N_4
IO_L24N_4
IO_L24N_4
IO_L24N_4
I/O
IO_L24P_4
IO_L24P_4
IO_L24P_4
IO_L24P_4
AA16
AB16
AC16
AE16
AF16
Y15
I/O
IO_L25N_4
IO_L25N_4
IO_L25N_4
IO_L25N_4
I/O
IO_L25P_4
IO_L25P_4
IO_L25P_4
IO_L25P_4
I/O
IO_L26N_4
IO_L26N_4
IO_L26N_4
IO_L26N_4
I/O
IO_L26P_4/VREF_4
IO_L27N_4/DIN/D0
IO_L27P_4/D1
IO_L28N_4
IO_L26P_4/VREF_4
IO_L27N_4/DIN/D0
IO_L27P_4/D1
IO_L28N_4
IO_L26P_4/VREF_4
IO_L27N_4/DIN/D0
IO_L27P_4/D1
IO_L28N_4
IO_L26P_4/VREF_4
IO_L27N_4/DIN/D0
IO_L27P_4/D1
IO_L28N_4
VREF
DUAL
DUAL
I/O
N.C. ()
IO_L27N_4/DIN/D0
IO_L27P_4/D1
IO_L28N_4
IO_L28P_4
IO_L29N_4
IO_L29P_4
IO_L30N_4/D2
IO_L30P_4/D3
IO_L31N_4/INIT_B
W14
AA15
AB15
AE15
AF15
Y14
IO_L28P_4
IO_L28P_4
IO_L28P_4
IO_L28P_4
I/O
IO_L29N_4
IO_L29N_4
IO_L29N_4
IO_L29N_4
I/O
IO_L29P_4
IO_L29P_4
IO_L29P_4
IO_L29P_4
I/O
IO_L30N_4/D2
IO_L30P_4/D3
IO_L31N_4/INIT_B
IO_L30N_4/D2
IO_L30P_4/D3
IO_L31N_4/INIT_B
IO_L30N_4/D2
IO_L30P_4/D3
IO_L31N_4/INIT_B
IO_L30N_4/D2
IO_L30P_4/D3
IO_L31N_4/INIT_B
DUAL
DUAL
DUAL
DUAL
AA14
AC14
AD14
IO_L31P_4/
DOUT/BUSY
IO_L31P_4/
DOUT/BUSY
IO_L31P_4/
DOUT/BUSY
IO_L31P_4/
DOUT/BUSY
IO_L31P_4/
DOUT/BUSY
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
5
5
IO_L32N_4/GCLK1
IO_L32P_4/GCLK0
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
IO
IO_L32N_4/GCLK1
IO_L32N_4/GCLK1
IO_L32N_4/GCLK1
IO_L32N_4/GCLK1
IO_L32P_4/GCLK0
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
IO
AE14
AF14
AD16
AD20
U14
GCLK
GCLK
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
I/O
IO_L32P_4/GCLK0
IO_L32P_4/GCLK0
IO_L32P_4/GCLK0
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
IO
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
IO
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
IO
V14
V15
V16
W17
W18
AA7
IO
IO
IO
IO
IO
AA13
AB9
I/O
IO_L17P_5(3)
IO_L17N_5(3)
IO
IO
IO
IO
IO
I/O
IO
IO
IO
AC9
AC11
AD10
AD12
AF4
I/O
N.C. ()
IO
IO
IO
IO
I/O
IO
IO
IO
IO
IO
I/O
IO
IO
IO
IO
IO
I/O
IO
IO
IO
IO
IO
I/O
IO
IO
IO
IO
IO
Y8
I/O
IO/VREF_5
IO/VREF_5
IO/VREF_5
IO/VREF_5
IO/VREF_5
IO/VREF_5
IO/VREF_5
IO/VREF_5
IO/VREF_5
IO/VREF_5
AF5
VREF
VREF
DUAL
AF13
AC5
IO_L01N_5/RDWR_B IO_L01N_5/RDWR_B IO_L01N_5/RDWR_B IO_L01N_5/RDWR_B IO_L01N_5/RDWR_B
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
198
Spartan-3 FPGA Family: Pinout Descriptions
Table 103: FG676 Package Pinout (Cont’d)
XC3S1000
Pin Name
XC3S1500
Pin Name
XC3S2000
Pin Name
XC3S4000
Pin Name
XC3S5000
Pin Name
FG676 Pin
Number
Bank
Type
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
IO_L01P_5/CS_B
IO_L04N_5
IO_L04P_5
IO_L05N_5
IO_L05P_5
IO_L06N_5
IO_L06P_5
IO_L07N_5
IO_L07P_5
IO_L08N_5
IO_L08P_5
IO_L09N_5
IO_L09P_5
IO_L10N_5/VRP_5
IO_L10P_5/VRN_5
N.C. ()
IO_L01P_5/CS_B
IO_L04N_5
IO_L04P_5
IO_L01P_5/CS_B
IO_L04N_5
IO_L01P_5/CS_B
IO_L04N_5
IO_L01P_5/CS_B
IO_L04N_5
AB5
AE4
AD4
AB6
AA6
AE5
AD5
AD6
AC6
AF6
DUAL
I/O
IO_L04P_5
IO_L04P_5
IO_L04P_5
I/O
IO_L05N_5
IO_L05P_5
IO_L05N_5
IO_L05N_5
IO_L05N_5
I/O
IO_L05P_5
IO_L05P_5
IO_L05P_5
I/O
IO_L06N_5
IO_L06P_5
IO_L06N_5
IO_L06N_5
IO_L06N_5
I/O
IO_L06P_5
IO_L06P_5
IO_L06P_5
I/O
IO_L07N_5
IO_L07P_5
IO_L07N_5
IO_L07N_5
IO_L07N_5
I/O
IO_L07P_5
IO_L07P_5
IO_L07P_5
I/O
IO_L08N_5
IO_L08P_5
IO_L08N_5
IO_L08N_5
IO_L08N_5
I/O
IO_L08P_5
IO_L08P_5
IO_L08P_5
AE6
AC7
AB7
AF7
I/O
IO_L09N_5
IO_L09P_5
IO_L09N_5
IO_L09N_5
IO_L09N_5
I/O
IO_L09P_5
IO_L09P_5
IO_L09P_5
I/O
IO_L10N_5/VRP_5
IO_L10P_5/VRN_5
IO_L11N_5/VREF_5
IO_L11P_5
IO_L10N_5/VRP_5
IO_L10P_5/VRN_5
IO_L11N_5/VREF_5
IO_L11P_5
IO_L10N_5/VRP_5
IO_L10P_5/VRN_5
IO_L11N_5/VREF_5
IO_L11P_5
IO_L10N_5/VRP_5
IO_L10P_5/VRN_5
IO_L11N_5/VREF_5
IO_L11P_5
DCI
DCI
VREF
I/O
AE7
AB8
AA8
AD8
AC8
AF8
N.C. ()
IO_L12N_5
IO_L12P_5
IO_L12N_5
IO_L12N_5
IO_L12N_5
I/O
N.C. ()
IO_L12P_5
IO_L12P_5
IO_L12P_5
I/O
N.C. ()
IO_L15N_5
IO_L15P_5
IO_L16N_5
IO_L16P_5
N.C. ()
IO_L15N_5
IO_L15P_5
IO_L15N_5
IO_L15N_5
IO_L15N_5
I/O
IO_L15P_5
IO_L15P_5
IO_L15P_5
AE8
AA9
Y9
I/O
IO_L16N_5
IO_L16P_5
IO_L16N_5
IO_L16N_5
IO_L16N_5
I/O
IO_L16P_5
IO_L16P_5
IO_L16P_5
I/O
IO_L18N_5
IO_L18P_5
IO_L18N_5
IO_L18N_5
IO_L18N_5
AE9
AD9
AA10
Y10
I/O
IO_L18P_5
IO_L18P_5
IO_L18P_5
I/O
N.C. ()
IO_L19N_5
IO_L19N_5
IO_L19N_5
IO_L19N_5
IO_L19N_5
I/O
IO_L19P_5/VREF_5 IO_L19P_5/VREF_5
IO_L19P_5/VREF_5
IO_L22N_5
IO_L19P_5/VREF_5
IO_L22N_5
IO_L19P_5/VREF_5
IO_L22N_5
VREF
I/O
IO_L22N_5
IO_L22P_5
N.C. ()
IO_L22N_5
IO_L22P_5
IO_L23N_5
IO_L23P_5
IO_L24N_5
IO_L24P_5
IO_L25N_5
IO_L25P_5
IO_L26N_5
IO_L26P_5
AC10
AB10
AF10
AE10
Y11
IO_L22P_5
IO_L22P_5
IO_L22P_5
I/O
IO_L23N_5
IO_L23N_5
IO_L23N_5
I/O
IO_L23P_5
IO_L23P_5
IO_L23P_5
I/O
N.C. ()
IO_L24N_5
IO_L24P_5
IO_L25N_5
IO_L25P_5
N.C. ()
IO_L24N_5
IO_L24N_5
IO_L24N_5
I/O
IO_L24P_5
IO_L24P_5
IO_L24P_5
W11
AB11
AA11
AF11
AE11
Y12
I/O
IO_L25N_5
IO_L25N_5
IO_L25N_5
I/O
IO_L25P_5
IO_L25P_5
IO_L25P_5
I/O
IO_L26N_5
IO_L26N_5
IO_L26N_5
I/O
IO_L26P_5
IO_L26P_5
IO_L26P_5
I/O
N.C. ()
IO_L27N_5/VREF_5 IO_L27N_5/VREF_5
IO_L27N_5/VREF_5
IO_L27P_5
IO_L27N_5/VREF_5
IO_L27P_5
IO_L27N_5/VREF_5
IO_L27P_5
VREF
I/O
IO_L27P_5
IO_L27P_5
W12
AB12
AA12
AF12
IO_L28N_5/D6
IO_L28P_5/D7
IO_L29N_5
IO_L28N_5/D6
IO_L28P_5/D7
IO_L29N_5
IO_L28N_5/D6
IO_L28P_5/D7
IO_L29N_5
IO_L28N_5/D6
IO_L28P_5/D7
IO_L29N_5
IO_L28N_5/D6
IO_L28P_5/D7
IO_L29N_5
DUAL
DUAL
I/O
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
199
Spartan-3 FPGA Family: Pinout Descriptions
Table 103: FG676 Package Pinout (Cont’d)
XC3S1000
Pin Name
XC3S1500
Pin Name
XC3S2000
Pin Name
XC3S4000
Pin Name
XC3S5000
Pin Name
FG676 Pin
Number
Bank
Type
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
IO_L29P_5/VREF_5 IO_L29P_5/VREF_5
IO_L29P_5/VREF_5
IO_L30N_5
IO_L30P_5
IO_L29P_5/VREF_5
IO_L30N_5
IO_L30P_5
IO_L29P_5/VREF_5
IO_L30N_5
IO_L30P_5
AE12
Y13
W13
AC13
AB13
AE13
AD13
AD7
AD11
U13
V11
V12
V13
W9
VREF
I/O
IO_L30N_5
IO_L30P_5
IO_L31N_5/D4
IO_L31P_5/D5
IO_L32N_5/GCLK3
IO_L32P_5/GCLK2
VCCO_5
IO_L30N_5
IO_L30P_5
IO_L31N_5/D4
IO_L31P_5/D5
IO_L32N_5/GCLK3
IO_L32P_5/GCLK2
VCCO_5
I/O
IO_L31N_5/D4
IO_L31P_5/D5
IO_L32N_5/GCLK3
IO_L32P_5/GCLK2
VCCO_5
IO_L31N_5/D4
IO_L31P_5/D5
IO_L32N_5/GCLK3
IO_L32P_5/GCLK2
VCCO_5
IO_L31N_5/D4
IO_L31P_5/D5
IO_L32N_5/GCLK3
IO_L32P_5/GCLK2
VCCO_5
DUAL
DUAL
GCLK
GCLK
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
I/O
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
W10
AA5
AD2
AD1
AB4
AB3
AC2
AC1
AB2
AB1
Y7
IO
IO
IO
N.C. ()
N.C. ()
IO_L01N_6/VRP_6
IO_L01P_6/VRN_6
IO_L02N_6
IO_L02P_6
IO_L01N_6/VRP_6
IO_L01P_6/VRN_6
IO_L02N_6
IO_L02P_6
IO_L01N_6/VRP_6
IO_L01P_6/VRN_6
IO_L02N_6
IO_L02P_6
IO_L01N_6/VRP_6
IO_L01P_6/VRN_6
IO_L02N_6
IO_L02P_6
IO_L01N_6/VRP_6
IO_L01P_6/VRN_6
IO_L02N_6
IO_L02P_6
DCI
DCI
I/O
I/O
IO_L03N_6/VREF_6 IO_L03N_6/VREF_6
IO_L03N_6/VREF_6
IO_L03P_6
IO_L03N_6/VREF_6
IO_L03P_6
IO_L03N_6/VREF_6
IO_L03P_6
VREF
I/O
IO_L03P_6
N.C. ()
N.C. ()
N.C. ()
N.C. ()
N.C. ()
N.C. ()
N.C. ()
N.C. ()
N.C. ()
N.C. ()
N.C. ()
N.C. ()
IO_L14N_6
IO_L14P_6
IO_L16N_6
IO_L16P_6
IO_L17N_6
IO_L03P_6
IO_L05N_6
IO_L05P_6
IO_L06N_6
IO_L06P_6
IO_L07N_6
IO_L07P_6
IO_L08N_6
IO_L08P_6
IO_L09N_6/VREF_6
IO_L09P_6
IO_L10N_6
IO_L10P_6
IO_L14N_6
IO_L14P_6
IO_L16N_6
IO_L16P_6
IO_L17N_6
IO_L05N_6
IO_L05P_6
IO_L05N_6
IO_L05P_6
IO_L05N_6
IO_L05P_6
I/O
I/O
IO_L06N_6
IO_L06P_6
IO_L06N_6
IO_L06P_6
IO_L06N_6
IO_L06P_6
I/O
Y6
I/O
IO_L07N_6
IO_L07P_6
IO_L07N_6
IO_L07P_6
IO_L07N_6
IO_L07P_6
AA4
AA3
Y5
I/O
I/O
IO_L08N_6
IO_L08P_6
IO_L08N_6
IO_L08P_6
IO_L08N_6
IO_L08P_6
I/O
Y4
I/O
IO_L09N_6/VREF_6
IO_L09P_6
IO_L09N_6/VREF_6
IO_L09P_6
IO_L09N_6/VREF_6
IO_L09P_6
AA2
AA1
Y2
VREF
I/O
IO_L10N_6
IO_L10P_6
IO_L10N_6
IO_L10P_6
IO_L10N_6
IO_L10P_6
I/O
Y1
I/O
IO_L14N_6
IO_L14P_6
IO_L14N_6
IO_L14P_6
IO_L14N_6
IO_L14P_6
W7
I/O
W6
I/O
IO_L16N_6
IO_L16P_6
IO_L16N_6
IO_L16P_6
IO_L16N_6
IO_L16P_6
V6
I/O
W5
I/O
IO_L17N_6
IO_L17P_6/VREF_6
IO_L19N_6
IO_L19P_6
IO_L17N_6
IO_L17P_6/VREF_6
IO_L19N_6
IO_L19P_6
IO_L17N_6
IO_L17P_6/VREF_6
IO_L19N_6
IO_L19P_6
W4
I/O
IO_L17P_6/VREF_6 IO_L17P_6/VREF_6
W3
VREF
I/O
IO_L19N_6
IO_L19P_6
IO_L19N_6
IO_L19P_6
W2
W1
I/O
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
200
Spartan-3 FPGA Family: Pinout Descriptions
Table 103: FG676 Package Pinout (Cont’d)
XC3S1000
Pin Name
XC3S1500
Pin Name
XC3S2000
Pin Name
XC3S4000
Pin Name
XC3S5000
Pin Name
FG676 Pin
Number
Bank
Type
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
7
IO_L20N_6
IO_L20N_6
IO_L20N_6
IO_L20N_6
IO_L20N_6
V7
U7
V5
V4
V3
V2
U6
U5
U4
U3
U2
U1
T8
T7
T6
T5
T2
T1
R8
R7
R6
R5
T4
R3
R2
R1
P8
P7
P6
P5
P4
P3
P2
P1
P9
P10
R9
T3
T9
U8
V8
Y3
F5
I/O
I/O
IO_L20P_6
IO_L21N_6
IO_L21P_6
IO_L22N_6
IO_L22P_6
IO_L23N_6
IO_L23P_6
IO_L20P_6
IO_L21N_6
IO_L21P_6
IO_L22N_6
IO_L22P_6
IO_L23N_6
IO_L23P_6
IO_L20P_6
IO_L21N_6
IO_L21P_6
IO_L22N_6
IO_L22P_6
IO_L23N_6
IO_L23P_6
IO_L24N_6/VREF_6
IO_L24P_6
IO_L26N_6
IO_L26P_6
IO_L27N_6
IO_L27P_6
IO_L28N_6
IO_L28P_6
IO_L29N_6
IO_L29P_6
IO_L31N_6
IO_L31P_6
IO_L32N_6
IO_L32P_6
IO_L33N_6
IO_L33P_6
IO_L34N_6/VREF_6
IO_L34P_6
IO_L35N_6
IO_L35P_6
IO_L38N_6
IO_L38P_6
IO_L39N_6
IO_L39P_6
IO_L40N_6
IO_L40P_6/VREF_6
VCCO_6
IO_L20P_6
IO_L21N_6
IO_L21P_6
IO_L22N_6
IO_L22P_6
IO_L23N_6
IO_L23P_6
IO_L24N_6/VREF_6
IO_L24P_6
IO_L26N_6
IO_L26P_6
IO_L27N_6
IO_L27P_6
IO_L28N_6
IO_L28P_6
IO_L29N_6
IO_L29P_6
IO_L31N_6
IO_L31P_6
IO_L32N_6
IO_L32P_6
IO_L33N_6
IO_L33P_6
IO_L34N_6/VREF_6
IO_L34P_6
IO_L35N_6
IO_L35P_6
IO_L38N_6
IO_L38P_6
IO_L39N_6
IO_L39P_6
IO_L40N_6
IO_L40P_6/VREF_6
VCCO_6
IO_L20P_6
IO_L21N_6
IO_L21P_6
IO_L22N_6
IO_L22P_6
IO_L23N_6
IO_L23P_6
IO_L24N_6/VREF_6
IO_L24P_6
IO_L26N_6
IO_L26P_6
IO_L27N_6
IO_L27P_6
IO_L28N_6
IO_L28P_6
IO_L29N_6
IO_L29P_6
IO_L31N_6
IO_L31P_6
IO_L32N_6
IO_L32P_6
IO_L33N_6
IO_L33P_6
IO_L34N_6/VREF_6
IO_L34P_6
IO_L35N_6
IO_L35P_6
IO_L38N_6
IO_L38P_6
IO_L39N_6
IO_L39P_6
IO_L40N_6
IO_L40P_6/VREF_6
VCCO_6
I/O
I/O
I/O
I/O
I/O
I/O
IO_L24N_6/VREF_6 IO_L24N_6/VREF_6
VREF
I/O
IO_L24P_6
IO_L26N_6
IO_L26P_6
IO_L27N_6
IO_L27P_6
IO_L28N_6
IO_L28P_6
IO_L29N_6
IO_L29P_6
IO_L31N_6
IO_L31P_6
IO_L32N_6
IO_L32P_6
IO_L33N_6
IO_L33P_6
IO_L24P_6
IO_L26N_6
IO_L26P_6
IO_L27N_6
IO_L27P_6
IO_L28N_6
IO_L28P_6
IO_L29N_6
IO_L29P_6
IO_L31N_6
IO_L31P_6
IO_L32N_6
IO_L32P_6
IO_L33N_6
IO_L33P_6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IO_L34N_6/VREF_6 IO_L34N_6/VREF_6
VREF
I/O
IO_L34P_6
IO_L35N_6
IO_L35P_6
IO_L38N_6
IO_L38P_6
IO_L39N_6
IO_L39P_6
IO_L40N_6
IO_L34P_6
IO_L35N_6
IO_L35P_6
IO_L38N_6
IO_L38P_6
IO_L39N_6
IO_L39P_6
IO_L40N_6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IO_L40P_6/VREF_6 IO_L40P_6/VREF_6
VREF
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
DCI
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
IO_L01N_7/VRP_7
IO_L01N_7/VRP_7
IO_L01N_7/VRP_7
IO_L01N_7/VRP_7
IO_L01N_7/VRP_7
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
201
Spartan-3 FPGA Family: Pinout Descriptions
Table 103: FG676 Package Pinout (Cont’d)
XC3S1000
Pin Name
XC3S1500
Pin Name
XC3S2000
Pin Name
XC3S4000
Pin Name
XC3S5000
Pin Name
FG676 Pin
Number
Bank
Type
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
IO_L01P_7/VRN_7
IO_L02N_7
IO_L01P_7/VRN_7
IO_L02N_7
IO_L01P_7/VRN_7
IO_L02N_7
IO_L01P_7/VRN_7
IO_L02N_7
IO_L01P_7/VRN_7
IO_L02N_7
F6
E3
E4
D1
D2
G6
G7
E1
E2
F3
F4
G4
G5
F1
F2
H6
H7
G1
G2
J6
DCI
I/O
IO_L02P_7
IO_L02P_7
IO_L02P_7
IO_L02P_7
IO_L02P_7
I/O
IO_L03N_7/VREF_7 IO_L03N_7/VREF_7
IO_L03N_7/VREF_7
IO_L03P_7
IO_L03N_7/VREF_7
IO_L03P_7
IO_L03N_7/VREF_7
IO_L03P_7
VREF
I/O
IO_L03P_7
N.C. ()
N.C. ()
N.C. ()
N.C. ()
N.C. ()
N.C. ()
N.C. ()
N.C. ()
N.C. ()
N.C. ()
N.C. ()
N.C. ()
IO_L14N_7
IO_L14P_7
IO_L16N_7
IO_L03P_7
IO_L05N_7
IO_L05P_7
IO_L06N_7
IO_L06P_7
IO_L07N_7
IO_L07P_7
IO_L08N_7
IO_L08P_7
IO_L09N_7
IO_L09P_7
IO_L10N_7
IO_L10P_7/VREF_7
IO_L14N_7
IO_L14P_7
IO_L16N_7
IO_L05N_7
IO_L05N_7
IO_L05N_7
I/O
IO_L05P_7
IO_L05P_7
IO_L05P_7
I/O
IO_L06N_7
IO_L06N_7
IO_L06N_7
I/O
IO_L06P_7
IO_L06P_7
IO_L06P_7
I/O
IO_L07N_7
IO_L07N_7
IO_L07N_7
I/O
IO_L07P_7
IO_L07P_7
IO_L07P_7
I/O
IO_L08N_7
IO_L08N_7
IO_L08N_7
I/O
IO_L08P_7
IO_L08P_7
IO_L08P_7
I/O
IO_L09N_7
IO_L09N_7
IO_L09N_7
I/O
IO_L09P_7
IO_L09P_7
IO_L09P_7
I/O
IO_L10N_7
IO_L10N_7
IO_L10N_7
I/O
IO_L10P_7/VREF_7
IO_L14N_7
IO_L10P_7/VREF_7
IO_L14N_7
IO_L10P_7/VREF_7
IO_L14N_7
VREF
I/O
IO_L14P_7
IO_L14P_7
IO_L14P_7
I/O
IO_L16N_7
IO_L16N_7
IO_L16N_7
I/O
IO_L16P_7/VREF_7 IO_L16P_7/VREF_7
IO_L16P_7/VREF_7
IO_L17N_7
IO_L16P_7/VREF_7
IO_L17N_7
IO_L16P_7/VREF_7
IO_L17N_7
H5
H3
H4
H1
H2
K7
J7
VREF
I/O
IO_L17N_7
IO_L17P_7
IO_L17N_7
IO_L17P_7
IO_L17P_7
IO_L17P_7
IO_L17P_7
I/O
IO_L19N_7/VREF_7 IO_L19N_7/VREF_7
IO_L19N_7/VREF_7
IO_L19P_7
IO_L19N_7/VREF_7
IO_L19P_7
IO_L19N_7/VREF_7
IO_L19P_7
VREF
I/O
IO_L19P_7
IO_L20N_7
IO_L20P_7
IO_L21N_7
IO_L21P_7
IO_L22N_7
IO_L22P_7
IO_L23N_7
IO_L23P_7
IO_L24N_7
IO_L24P_7
IO_L26N_7
IO_L26P_7
IO_L27N_7
IO_L19P_7
IO_L20N_7
IO_L20P_7
IO_L21N_7
IO_L21P_7
IO_L22N_7
IO_L22P_7
IO_L23N_7
IO_L23P_7
IO_L24N_7
IO_L24P_7
IO_L26N_7
IO_L26P_7
IO_L27N_7
IO_L20N_7
IO_L20N_7
IO_L20N_7
I/O
IO_L20P_7
IO_L20P_7
IO_L20P_7
I/O
IO_L21N_7
IO_L21N_7
IO_L21N_7
J4
I/O
IO_L21P_7
IO_L21P_7
IO_L21P_7
J5
I/O
IO_L22N_7
IO_L22N_7
IO_L22N_7
J2
I/O
IO_L22P_7
IO_L22P_7
IO_L22P_7
J3
I/O
IO_L23N_7
IO_L23N_7
IO_L23N_7
K5
K6
K3
K4
K1
K2
L7
L8
L5
L6
L1
I/O
IO_L23P_7
IO_L23P_7
IO_L23P_7
I/O
IO_L24N_7
IO_L24N_7
IO_L24N_7
I/O
IO_L24P_7
IO_L24P_7
IO_L24P_7
I/O
IO_L26N_7
IO_L26N_7
IO_L26N_7
I/O
IO_L26P_7
IO_L26P_7
IO_L26P_7
I/O
IO_L27N_7
IO_L27N_7
IO_L27N_7
I/O
IO_L27P_7/VREF_7 IO_L27P_7/VREF_7
IO_L27P_7/VREF_7
IO_L28N_7
IO_L27P_7/VREF_7
IO_L28N_7
IO_L27P_7/VREF_7
IO_L28N_7
VREF
I/O
IO_L28N_7
IO_L28P_7
IO_L29N_7
IO_L28N_7
IO_L28P_7
IO_L29N_7
IO_L28P_7
IO_L28P_7
IO_L28P_7
I/O
IO_L29N_7
IO_L29N_7
IO_L29N_7
I/O
DS099 (v3.1) June 27, 2013
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Product Specification
202
Spartan-3 FPGA Family: Pinout Descriptions
Table 103: FG676 Package Pinout (Cont’d)
XC3S1000
Pin Name
XC3S1500
Pin Name
XC3S2000
Pin Name
XC3S4000
Pin Name
XC3S5000
Pin Name
FG676 Pin
Number
Bank
Type
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
IO_L29P_7
IO_L29P_7
IO_L29P_7
IO_L29P_7
IO_L29P_7
L2
M7
I/O
I/O
IO_L31N_7
IO_L31P_7
IO_L32N_7
IO_L32P_7
IO_L33N_7
IO_L33P_7
IO_L34N_7
IO_L34P_7
IO_L35N_7
IO_L35P_7
IO_L38N_7
IO_L38P_7
IO_L39N_7
IO_L39P_7
IO_L31N_7
IO_L31P_7
IO_L32N_7
IO_L32P_7
IO_L33N_7
IO_L33P_7
IO_L34N_7
IO_L34P_7
IO_L35N_7
IO_L35P_7
IO_L38N_7
IO_L38P_7
IO_L39N_7
IO_L39P_7
IO_L31N_7
IO_L31P_7
IO_L32N_7
IO_L32P_7
IO_L33N_7
IO_L33P_7
IO_L34N_7
IO_L34P_7
IO_L35N_7
IO_L35P_7
IO_L38N_7
IO_L38P_7
IO_L39N_7
IO_L39P_7
IO_L40N_7/VREF_7
IO_L40P_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
GND
IO_L31N_7
IO_L31P_7
IO_L32N_7
IO_L32P_7
IO_L33N_7
IO_L33P_7
IO_L34N_7
IO_L34P_7
IO_L35N_7
IO_L35P_7
IO_L38N_7
IO_L38P_7
IO_L39N_7
IO_L39P_7
IO_L40N_7/VREF_7
IO_L40P_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
GND
IO_L31N_7
IO_L31P_7
IO_L32N_7
IO_L32P_7
IO_L33N_7
IO_L33P_7
IO_L34N_7
IO_L34P_7
IO_L35N_7
IO_L35P_7
IO_L38N_7
IO_L38P_7
IO_L39N_7
IO_L39P_7
IO_L40N_7/VREF_7
IO_L40P_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
GND
M8
I/O
M6
I/O
M5
I/O
M3
I/O
L4
I/O
M1
I/O
M2
I/O
N7
I/O
N8
I/O
N5
I/O
N6
I/O
N3
I/O
N4
I/O
IO_L40N_7/VREF_7 IO_L40N_7/VREF_7
N1
VREF
I/O
IO_L40P_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
IO_L40P_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
GND
N2
G3
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
J8
K8
L3
L9
M9
N9
N10
A1
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
GND
GND
GND
GND
A26
AC4
AC12
AC15
AC23
AD3
AD24
AE2
AE25
AF1
AF26
B2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
B25
C3
GND
GND
GND
GND
GND
GND
GND
GND
C24
D4
GND
GND
GND
GND
GND
GND
GND
GND
D12
DS099 (v3.1) June 27, 2013
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Product Specification
203
Spartan-3 FPGA Family: Pinout Descriptions
Table 103: FG676 Package Pinout (Cont’d)
XC3S1000
Pin Name
XC3S1500
Pin Name
XC3S2000
Pin Name
XC3S4000
Pin Name
XC3S5000
Pin Name
FG676 Pin
Number
Bank
Type
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
D15
D23
K11
K12
K15
K16
L10
L11
L12
L13
L14
L15
L16
L17
M4
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
M10
M11
M12
M13
M14
M15
M16
M17
M23
N11
N12
N13
N14
N15
N16
P11
P12
P13
P14
P15
P16
R4
R10
R11
R12
R13
R14
R15
DS099 (v3.1) June 27, 2013
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Product Specification
204
Spartan-3 FPGA Family: Pinout Descriptions
Table 103: FG676 Package Pinout (Cont’d)
XC3S1000
Pin Name
XC3S1500
Pin Name
XC3S2000
Pin Name
XC3S4000
Pin Name
XC3S5000
Pin Name
FG676 Pin
Number
Bank
Type
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
R16
R17
R23
T10
T11
T12
T13
T14
T15
T16
T17
U11
U12
U15
U16
A2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
N/A VCCAUX
N/A VCCAUX
N/A VCCAUX
N/A VCCAUX
N/A VCCAUX
N/A VCCAUX
N/A VCCAUX
N/A VCCAUX
N/A VCCAUX
N/A VCCAUX
N/A VCCAUX
N/A VCCAUX
N/A VCCAUX
N/A VCCAUX
N/A VCCAUX
N/A VCCAUX
N/A VCCINT
N/A VCCINT
N/A VCCINT
N/A VCCINT
N/A VCCINT
N/A VCCINT
N/A VCCINT
N/A VCCINT
N/A VCCINT
N/A VCCINT
N/A VCCINT
N/A VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
A9
A18
A25
AE1
AE26
AF2
AF9
AF18
AF25
B1
B26
J1
J26
V1
V26
H8
H19
J9
J10
J17
J18
K9
K10
K17
K18
U9
U10
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
205
Spartan-3 FPGA Family: Pinout Descriptions
Table 103: FG676 Package Pinout (Cont’d)
XC3S1000
Pin Name
XC3S1500
Pin Name
XC3S2000
Pin Name
XC3S4000
Pin Name
XC3S5000
Pin Name
FG676 Pin
Number
Bank
Type
N/A VCCINT
N/A VCCINT
N/A VCCINT
N/A VCCINT
N/A VCCINT
N/A VCCINT
N/A VCCINT
N/A VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
U17
U18
V9
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
CONFIG
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
CCLK
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
CCLK
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
CCLK
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
CCLK
V10
V17
V18
W8
W19
AD26
VCC CCLK
AUX
VCC DONE
AUX
DONE
HSWAP_EN
M0
DONE
HSWAP_EN
M0
DONE
HSWAP_EN
M0
DONE
HSWAP_EN
M0
AC24
C2
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
JTAG
VCC HSWAP_EN
AUX
VCC M0
AUX
AE3
AC3
AF3
D3
VCC M1
AUX
M1
M1
M1
M1
VCC M2
AUX
M2
M2
M2
M2
VCC PROG_B
AUX
PROG_B
TCK
PROG_B
TCK
PROG_B
TCK
PROG_B
TCK
VCC TCK
AUX
B24
C1
VCC TDI
AUX
TDI
TDI
TDI
TDI
JTAG
VCC TDO
AUX
TDO
TDO
TDO
TDO
D24
A24
JTAG
VCC TMS
AUX
TMS
TMS
TMS
TMS
JTAG
Notes:
1. XC3S1500 balls D25 and F25 are not VREF pins although they are designated as such. If a design uses an IOSTANDARD requiring VREF in bank
2 then apply the workaround in Answer Record 20519.
2. XC3S4000 is pin compatible with XC3S2000 but uses alternate differential pair labeling on six package balls (H20, H21, H22, H23, H24, J21).
3. XC3S5000 is pin compatible with XC3S4000 but uses alternate differential pair functionality on fifteen package balls (A3, A8, B8, B18, C4, C8, C18,
D8, D18, E8, E18, H23, H24, AB9, and AC9).
DS099 (v3.1) June 27, 2013
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Product Specification
206
Spartan-3 FPGA Family: Pinout Descriptions
User I/Os by Bank
Table 104 indicates how the available user-I/O pins are distributed between the eight I/O banks for the XC3S1000 in the
FG676 package. Similarly, Table 105 shows how the available user-I/O pins are distributed between the eight I/O banks for
the XC3S1500 in the FG676 package. Finally, Table 106 shows the same information for the XC3S2000, XC3S4000, and
XC3S5000 in the FG676 package.
Table 104: User I/Os Per Bank for XC3S1000 in FG676 Package
All Possible I/O Pins by Type
I/O
Edge
Top
Maximum I/O
Bank
I/O
40
41
41
41
35
35
41
41
DUAL
DCI
VREF
GCLK
0
1
2
3
4
5
6
7
49
50
48
48
50
50
48
48
0
0
0
0
6
6
0
0
2
5
5
5
5
5
5
5
5
2
2
0
0
2
2
0
0
2
2
Right
Bottom
Left
2
2
2
2
2
Table 105: User I/Os Per Bank for XC3S1500 in FG676 Package
All Possible I/O Pins by Type
I/O
Edge
Top
Maximum I/O
Bank
I/O
52
51
52
52
47
45
52
52
DUAL
DCI
2
VREF
GCLK
0
1
2
3
4
5
6
7
62
61
60
60
63
61
60
60
0
0
0
0
6
6
0
0
6
6
6
6
6
6
6
6
2
2
0
0
2
2
0
0
2
2
Right
Bottom
Left
2
2
2
2
2
Table 106: User I/Os Per Bank for XC3S2000, XC3S4000, and XC3S5000 in FG676 Package
All Possible I/O Pins by Type
Edge
Top
I/O Bank
Maximum I/O
I/O
52
51
53
52
47
45
53
52
DUAL
DCI
2
VREF
GCLK
0
1
2
3
4
5
6
7
62
61
61
60
63
61
61
60
0
0
0
0
6
6
0
0
6
6
6
6
6
6
6
6
2
2
0
0
2
2
0
0
2
2
Right
Bottom
Left
2
2
2
2
2
DS099 (v3.1) June 27, 2013
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Product Specification
207
Spartan-3 FPGA Family: Pinout Descriptions
X-Ref Target - Figure 53
FG676 Footprint
Bank 0
1
2
3
4
I/O
L05P_0
VREF_0
5
6
7
8
9
VCCAUX
I/O
10
11
12
13
I/O
L32P_0
GCLK6
I/O
I/O
Left Half of Package
(Top View)
L26P_0
VREF_0
I/O
L10P_0
I/O
L15P_0
I/O
L29P_0
L23P_0
VCCAUX
GND
I/O
I/O
I/O
A
B
C
D
E
F
I/O
I/O
I/O
L32N_0
GCLK7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L29N_0
L18P_0 L23N_0 L26N_0
GND
VCCAUX
TD I
VREF_0 L05N_0 L06P_0 L08P_0 L10N_0 L15N_0
XC3S1000
(391 max. user I/O)
I/O
L18N_0
I/O
L31P_0
VREF_0
I/O
HSWAP_
EN
I/O
I/O
I/O
L22P_0
GND
VCCO_0
I/O
VCCO_0
I/O
I/O
L06N_0 L08N_0
I/O: Unrestricted,
general-purpose user I/O
315
I/O
I/O
I/O
L03N_7
VREF_7
I/O
I/O
I/O
L03P_7
I/O
I/O
I/O
L31N_0
L12P_0 L17P_0
PROG_B
I/O
GND
I/O
GND
I/O
L01P_0
L07P_0 L09P_0
L22N_0 L25P_0
VRN_0
VREF: User I/O or input
40
I/O
I/O
I/O
I/O
voltage reference for bank
I/O
L01N_0
VRP_0
I/O
I/O
I/O
L19P_0
I/O
L06N_7 L06P_7
L12N_0 L17N_0
I/O
L02N_7 L02P_7
L07N_0 L09N_0
L25N_0 L28P_0
N.C.: Unconnected pins for
XC3S1000 ()
I/O
I/O
I/O I/O
I/O
L11P_0
I/O
I/O
I/O
98
I/O
I/O
I/O
I/O
I/O
L09N_7 L09P_7 L07N_7 L07P_7
L01N_7 L01P_7
VRP_7
VREF_0
L16P_0 L19N_0 L24P_0 L28N_0 L30P_0
VRN_7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L16N_0
I/O
VREF_0
I/O
I/O
I/O
XC3S1500
L08N_7 L08P_7 L05N_7 L05P_7 L11N_0
VCCO_7
G
H
J
L14N_7 L14P_7
L24N_0 L27N_0 L30N_0
(487 max user I/O)
I/O
I/O
L10N_7
I/O: Unrestricted,
general-purpose user I/O
I/O
I/O
I/O
L16P_7
VREF_7
L10P_7
VREF_7
I/O
I/O
I/O
L27P_0
403
VCCO_0 VCCO_0
VCCINT VCCINT
VCCINT VCCINT
VCCINT
I/O
I/O
L19N_7
L19P_7 L17N_7 L17P_7
VREF_7
I/O
I/O
I/O
I/O
I/O
I/O
VCCAUX
VCCO_7
VCCO_7
VCCO_0 VCCO_0 VCCO_0
VREF: User I/O or input
48
L22N_7 L22P_7 L21N_7 L21P_7 L16N_7 L20P_7
voltage reference for bank
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCO_0
K
L
GND
GND
GND
GND
L26N_7 L26P_7 L24N_7 L24P_7 L23N_7 L23P_7 L20N_7
N.C.: Unconnected pins for
XC3S1500 ()
2
I/O
L27P_7
VREF_7
I/O
I/O
I/O
I/O
I/O
I/O
VCCO_7
VCCO_7
GND
GND
L29N_7 L29P_7
L33P_7 L28N_7 L28P_7 L27N_7
XC3S2000, XC3S4000,
I/O
I/O
I/O
I/O
I/O
I/O
I/O
XC3S5000 (489 max user I/O)
VCCO_7
GND
GND
I/O
GND
GND
GND
GND
GND
GND
M
N
P
R
T
L34N_7 L34P_7 L33N_7
L32P_7 L32N_7 L31N_7 L31P_7
I/O: Unrestricted,
general-purpose user I/O
405
I/O
L40N_7
VREF_7
I/O
I/O
I/O
I/O
I/O
I/O
VCCO_7 VCCO_7
VCCO_6 VCCO_6
L40P_7 L39N_7 L39P_7 L38N_7 L38P_7 L35N_7 L35P_7
VREF: User I/O or input
48
I/O
L40P_6
VREF_6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L35N_6
voltage reference for bank
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
L40N_6 L39P_6 L39N_6 L38P_6 L38N_6 L35P_6
I/O
L34N_6
VREF_6
I/O
L34P_6
I/O
L33P_6
I/O
I/O
I/O
I/O
L31N_6
VCCO_6
GND
0
N.C.: No unconnected pins
GND
I/O
L32P_6 L32N_6 L31P_6
I/O
I/O
I/O
I/O
I/O
I/O
L27N_6
VCCO_6
VCCO_6
GND
GND
All devices
L29P_6 L29N_6
L33N_6 L28P_6 L28N_6 L27P_6
DUAL: Configuration pin,
I/O
L24N_6
VREF_6
12
I/O
I/O
I/O
I/O
I/O
I/O
then possible user I/O
VCCO_6
VCCO_6
VCCINT
I/O
VCCO_5
VCCINT VCCINT
VCCINT VCCINT
VCCO_5 VCCO_5
U
V
W
Y
L26P_6 L26N_6 L24P_6
L23P_6 L23N_6 L20P_6
GCLK: User I/O or global
clock buffer input
I/O
I/O
I/O
I/O
I/O
I/O
VCCAUX
VCCO_5 VCCO_5 VCCO_5
8
L22P_6 L22N_6 L21P_6 L21N_6 L16N_6 L20N_6
I/O
L17P_6
VREF_6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DCI: User I/O or reference
resistor input for bank
L19P_6 L19N_6
L17N_6 L16P_6 L14P_6 L14N_6
L24P_5 L27P_5 L30P_5
16
7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L27N_5
VREF_5
I/O
L24N_5
I/O
L30N_5
L10P_6 L10N_6
L08P_6 L08N_6 L06P_6 L06N_6
VCCO_6
I/O
L19P_5
L16P_5
VREF_5
CONFIG: Dedicated
configuration pins
I/O
L09N_6
VREF_6
I/O
L09P_6
I/O
I/O
L11P_5
I/O
L28P_5
D7
I/O
A
A
I/O
L05P_5
I/O
I/O
I/O
L07P_6 L07N_6
I/O
I/O
I/O
L16N_5 L19N_5 L25P_5
JTAG: Dedicated JTAG
port pins
I/O
I/O
I/O
4
I/O
L01P_5
CS_B
I/O
A
B
L11N_5
VREF_5
I/O
I/O
I/O
I/O
I/O
L22P_5
I/O
L25N_5
L05P_6 L05N_6
I/O
L28N_5 L31P_5
D6
L02P_6 L02N_6
L05N_5 L09P_5
D5
I/O
L12P_5
I/O
L03N_6
VREF_6
I/O
L01N_5
RDWR_B
I/O
L31N_5
D4
VCCINT: Internal core
I/O
A
C
I/O
L03P_6
I/O
I/O
I/O
L22N_5
20
64
16
M1
GND
M0
GND
I/O
GND
L07P_5 L09N_5
voltage supply (+1.2V)
I/O
I/O
I/O
I/O
I/O
L32P_5
GCLK2
A
D
I/O
I/O
I/O
L12N_5 L18P_5
VCCO_5
VCCO_5
I/O
I/O
I/O
I/O
I/O
L01P_6 L01N_6
VCCO: Output voltage
supply for bank
L04P_5 L06P_5 L07N_5
VRN_6
VRP_6
I/O
I/O
L10P_5
VRN_5
I/O
A
E
I/O
I/O
I/O
I/O
L15P_5
L18N_5 L23P_5 L26P_5
VCCAUX
GND
L29P_5 L32N_5
VREF_5 GCLK3
L04N_5 L06N_5 L08P_5
VCCAUX: Auxiliary voltage
supply (+2.5V)
I/O
I/O
I/O
L10N_5
VRP_5
A
F
I/O
I/O
I/O
L15N_5
I/O
I/O
L23N_5 L26N_5
VCCAUX
M2
I/O
GND
VCCAUX
VREF_5 L08N_5
L29N_5 VREF_5
76 GND: Ground
Bank 5
DS099-4 12a 030203
Figure 53: FG676 Package Footprint (Top View)
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
208
Spartan-3 FPGA Family: Pinout Descriptions
Bank 1
14
15
16
17
18
VCCAUX
I/O
19
20
I/O
L10N_1
VREF_1
21
22
23
24
25
26
I/O
I/O
Right Half of Package
(Top View)
I/O
L29N_1
I/O
L15N_1
I/O
L08N_1
L26N_1 L23N_1
GND
VCCAUX
I/O
I/O
I/O
TMS
A
B
C
D
E
F
I/O
I/O
I/O
L32N_1
GCLK5
I/O
L06N_1
VREF_1
I/O
L29P_1
I/O
I/O
I/O
I/O
L04N_1
L26P_1 L23P_1 L18N_1
VCCAUX
I/O
TCK
GND
I/O
L01N_2 L01P_2
VRP_2
L15P_1 L10P_1 L08P_1
I/O
I/O
I/O
L32P_1
GCLK4
I/O
VREF_1
I/O
VREF_1
I/O
L07N_1
I/O
I/O
L18P_1 L12N_1
VCCO_1
VCCO_1
GND
L06P_1 L04P_1
VRN_2
I/O
I/O
I/O
L31N_1
VREF_1
I/O
L01N_1
VRP_1
I/O
L03N_2
VREF_2
I/O
L22N_1
I/O
I/O
I/O
L03P_2
VREF_1 L12P_1
GND
I/O
I/O
GND
TDO
I/O
L09N_1 L07P_1
I/O
L11N_1
I/O
I/O
I/O
L22P_1
I/O
I/O
I/O
I/O
I/O
I/O
L05N_2 L05P_2
I/O
L01P_1
L31P_1 L28N_1 L25N_1
L09P_1 L05N_1
L02N_2 L02P_2
VRN_1
I/O
I/O
L11P_1
I/O
I/O
I/O
L09P_2
I/O
L09N_2
VREF_2
I/O
I/O
I/O
I/O
I/O
I/O
L07N_2 L07P_2
I/O
L28P_1 L25P_1 L19N_1 L16N_1
L05P_1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L06N_2 L06P_2 L08N_2 L08P_2
L10N_2 L10P_2
VCCO_2
I/O
G
H
J
L30N_1 L27N_1 L24N_1 L19P_1 L16P_1
I/O
I/O
I/O
I/O
I/O
L17P_2
(L13P_2)
I/O
I/O
I/O
I/O
I/O
VCCO_1 VCCO_1
VCCINT VCCINT
VCCINT VCCINT
VCCINT
VCCO_2
L14N_2 L14P_2 L16N_2 L17N_2
(L11N_2) (L11P_2) (L12N_2) (L13N_2)
Notes:
L30P_1 L27P_1 L24P_1
L19N_2 L19P_2
VREF_2
1. Differential pair assignments
shown in parentheses on balls
H20, H21, H22, H23, H24,
and J21 are for XC3S4000
only.
2. Differential pair assignments
for the XC3S5000 are different
on 15 balls (see Table 103 for
details.)
I/O
L16P_2
(L12P_2)
I/O
L20N_2
I/O
I/O
I/O
L22N_2
I/O
L22P_2
VCCO_1 VCCO_1 VCCO_1
VCCAUX
L21N_2 L21P_2
I/O
L23N_2
VREF_2
I/O
L20P_2
I/O
I/O
I/O
I/O
I/O
VCCO_1
GND
VCCO_2
I/O
GND
GND
GND
GND
K
L
L23P_2 L24N_2 L24P_2 L26N_2 L26P_2
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
VCCO_2
VCCO_2
VCCO_2
L27N_2 L27P_2 L28N_2
L28P_2 L33N_2
L29N_2 L29P_2
I/O
I/O
I/O
I/O
I/O
L32P_2
I/O
L33P_2
I/O
GND
GND
GND
GND
GND
GND
L34N_2
L34P_2
VREF_2
M
N
P
R
T
L31N_2 L31P_2 L32N_2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCCO_2 VCCO_2
VCCO_3 VCCO_3
L40P_2
VREF_2
L35N_2 L35P_2 L38N_2
L38P_2 L39N_2 L39P_2 L40N_2
I/O
L40N_3
VREF_3
I/O
I/O
I/O
I/O
I/O
I/O
L39N_3
I/O
L40P_3
GND
GND
GND
GND
GND
GND
L35P_3 L35N_3 L38P_3 L38N_3 L39P_3
I/O
L34P_3
VREF_3
I/O
I/O
I/O
I/O
I/O
L33N_3
I/O
L34N_3
VCCO_3
GND
GND
I/O
L31P_3 L31N_3 L32P_3 L32N_3
I/O
I/O
I/O
I/O
I/O
L29P_3
I/O
L29N_3
VCCO_3
GND
VCCO_3
GND
GND
GND
GND
GND
L27P_3 L27N_3 L28P_3 L28N_3 L33P_3
I/O
L23P_3
VREF_3
I/O
L20N_3
I/O
I/O
I/O
L24N_3
I/O
L26P_3
I/O
L26N_3
VCCO_4
VCCO_3
VCCO_3
VCCINT VCCINT
VCCINT VCCINT
VCCO_4 VCCO_4
U
V
W
Y
L23N_3 L24P_3
I/O
I/O
I/O
I/O
I/O
I/O
VCCO_4 VCCO_4 VCCO_4
I/O
L27P_4
D1
VCCAUX
L20P_3 L16N_3
L21P_3 L21N_3 L22P_3 L22N_3
I/O
I/O
I/O
L17P_3
VREF_3
I/O
L16P_3
I/O
L17N_3
I/O
L19P_3
I/O
L19N_3
L10P_3 L10N_3
I/O
I/O
VCCINT
I/O
I/O
L27N_4
DIN
I/O
I/O
I/O
I/O
I/O
L30N_4
D2
I/O
I/O
I/O
I/O
L14P_3
I/O
L14N_3
L11N_4 L05P_3 L05N_3
L08P_3 L08N_3
VCCO_3
I/O
L24N_4 VREF_4 L16N_4
D0
I/O
I/O
L11P_4
I/O
I/O
L09N_3
I/O
L30P_4
D3
I/O
I/O
A
A
L09P_3
VREF_3
I/O
I/O
I/O
I/O
L07P_3 L07N_3
I/O
L01P_3 L01N_3
VRN_3
L28N_4 L24P_4 L19P_4 L16P_4
VRP_3
I/O
I/O
I/O
I/O
I/O
L01N_4
VRP_4
I/O
L02N_3
VREF_3
A
B
IO
VREF_4
I/O
I/O
I/O
I/O
I/O
I/O
L02P_3
L17N_4 L12N_4
L06P_3 L06N_3
L28P_4 L25N_4 L22P_4
L09N_4 L07N_4
I/O
I/O
I/O
L31N_4
INIT_B
I/O
L01P_4
VRN_4
A
C
I/O
I/O
I/O
I/O
I/O
L03P_3
I/O
L03N_3
L17P_4 L12P_4
GND
I/O
GND
DONE
L25P_4 L19N_4
L09P_4 L07P_4
I/O
I/O
L18N_4
I/O
I/O
L06N_4
VREF_4
I/O
A
D
I/O
L08N_4
I/O
VREF_4
L31P_4
DOUT
BUSY
VCCO_4
L22N_4
VCCO_4
GND
I/O
I/O
I/O
CCLK
VREF_4
I/O
I/O
I/O
I/O
L32N_4
GCLK1
A
E
I/O
L29N_4
I/O
I/O
I/O
I/O
L26N_4 L23N_4 L18P_4
VCCAUX
GND
L15N_4 L10N_4 L08P_4 L06P_4 L05N_4 L04N_4
I/O
I/O
L23P_4
I/O
L32P_4
GCLK0
A
F
L26P_4
VREF_4
I/O
L29P_4
I/O
I/O
I/O
L05P_4
I/O
L04P_4
VCCAUX
VCCAUX
I/O
I/O
GND
L15P_4 L10P_4
Bank 4
DS099-4_12b_011205
Figure 54: FG676 Package Footprint (Top View) Continued
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Product Specification
209
Spartan-3 FPGA Family: Pinout Descriptions
FG900: 900-lead Fine-pitch Ball Grid Array
The 900-lead fine-pitch ball grid array package, FG900, supports three different Spartan-3 devices, including the
XC3S2000, the XC3S4000, and the XC3S5000. The footprints for the XC3S4000 and XC3S5000 are identical, as shown in
Table 107 and Figure 55. The XC3S2000, however, has fewer I/O pins which consequently results in 68 unconnected pins
on the FG900 package, labeled as “N.C.” In Table 107 and Figure 55, these unconnected pins are indicated with a black
diamond symbol ().
All the package pins appear in Table 107 and are sorted by bank number, then by pin name. Pairs of pins that form a
differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type, as
defined earlier.
If there is a difference between the XC3S2000 pinout and the pinout for the XC3S4000 and XC3S5000, then that difference
is highlighted in Table 107. If the table entry is shaded, then there is an unconnected pin on the XC3S2000 that maps to a
user-I/O pin on the XC3S4000 and XC3S5000.
An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at
http://www.xilinx.com/support/documentation/data_ sheets/s3_pin.zip.
Pinout Table
Table 107: FG900 Package Pinout
XC3S2000
Pin Name
XC3S4000, XC3S5000 FG900 Pin
Bank
Type
Pin Name
Number
E15
K15
D13
K13
G8
F9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
I/O
I/O
I/O
I/O
I/O
IO/VREF_0
IO/VREF_0
VREF
VREF
DCI
DCI
I/O
IO/VREF_0
IO/VREF_0
C4
IO_L01N_0/VRP_0
IO_L01P_0/VRN_0
IO_L02N_0
IO_L01N_0/VRP_0
IO_L01P_0/VRN_0
IO_L02N_0
B4
A4
B5
IO_L02P_0
IO_L02P_0
A5
I/O
IO_L03N_0
IO_L03N_0
D5
I/O
IO_L03P_0
IO_L03P_0
E6
I/O
IO_L04N_0
IO_L04N_0
C6
I/O
IO_L04P_0
IO_L04P_0
B6
I/O
IO_L05N_0
IO_L05N_0
F6
I/O
IO_L05P_0/VREF_0
IO_L06N_0
IO_L05P_0/VREF_0
IO_L06N_0
F7
VREF
I/O
D7
IO_L06P_0
IO_L06P_0
C7
I/O
IO_L07N_0
IO_L07N_0
F8
I/O
IO_L07P_0
IO_L07P_0
E8
I/O
IO_L08N_0
IO_L08N_0
D8
I/O
IO_L08P_0
IO_L08P_0
C8
I/O
IO_L09N_0
IO_L09N_0
B8
I/O
IO_L09P_0
IO_L09P_0
A8
I/O
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210
Spartan-3 FPGA Family: Pinout Descriptions
Table 107: FG900 Package Pinout (Cont’d)
XC3S2000
Pin Name
XC3S4000, XC3S5000 FG900 Pin
Bank
Type
Pin Name
Number
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO_L10N_0
IO_L10N_0
J9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
IO_L10P_0
IO_L11N_0
IO_L11P_0
IO_L12N_0
IO_L12P_0
IO_L13N_0
IO_L13P_0
IO_L14N_0
IO_L14P_0
IO_L15N_0
IO_L15P_0
IO_L16N_0
IO_L16P_0
IO_L17N_0
IO_L17P_0
IO_L18N_0
IO_L18P_0
IO_L19N_0
IO_L19P_0
IO_L20N_0
IO_L20P_0
IO_L21N_0
IO_L21P_0
IO_L22N_0
IO_L22P_0
IO_L23N_0
IO_L23P_0
IO_L24N_0
IO_L24P_0
IO_L25N_0
IO_L25P_0
IO_L26N_0
IO_L26P_0/VREF_0
IO_L27N_0
IO_L27P_0
IO_L28N_0
IO_L28P_0
IO_L29N_0
IO_L29P_0
IO_L10P_0
IO_L11N_0
IO_L11P_0
IO_L12N_0
IO_L12P_0
IO_L13N_0
IO_L13P_0
IO_L14N_0
IO_L14P_0
IO_L15N_0
IO_L15P_0
IO_L16N_0
IO_L16P_0
IO_L17N_0
IO_L17P_0
IO_L18N_0
IO_L18P_0
IO_L19N_0
IO_L19P_0
IO_L20N_0
IO_L20P_0
IO_L21N_0
IO_L21P_0
IO_L22N_0
IO_L22P_0
IO_L23N_0
IO_L23P_0
IO_L24N_0
IO_L24P_0
IO_L25N_0
IO_L25P_0
IO_L26N_0
IO_L26P_0/VREF_0
IO_L27N_0
IO_L27P_0
IO_L28N_0
IO_L28P_0
IO_L29N_0
IO_L29P_0
H9
G10
F10
C10
B10
J10
K11
H11
G11
F11
E11
D11
C11
B11
A11
K12
J12
H12
G12
F12
E12
D12
C12
B12
A12
J13
H13
F13
E13
B13
A13
K14
J14
G14
F14
C14
B14
J15
H15
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211
Spartan-3 FPGA Family: Pinout Descriptions
Table 107: FG900 Package Pinout (Cont’d)
XC3S2000
Pin Name
XC3S4000, XC3S5000 FG900 Pin
Bank
Type
Pin Name
Number
G15
F15
D15
C15
B15
A15
B7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IO_L30N_0
IO_L30N_0
I/O
I/O
IO_L30P_0
IO_L31N_0
IO_L31P_0/VREF_0
IO_L32N_0/GCLK7
IO_L32P_0/GCLK6
N.C. ()
IO_L30P_0
IO_L31N_0
IO_L31P_0/VREF_0
IO_L32N_0/GCLK7
IO_L32P_0/GCLK6
IO_L35N_0
IO_L35P_0
IO_L36N_0
IO_L36P_0
IO_L37N_0
IO_L37P_0
IO_L38N_0
IO_L38P_0
VCCO_0
I/O
VREF
GCLK
GCLK
I/O
N.C. ()
A7
I/O
N.C. ()
G7
I/O
N.C. ()
H8
I/O
N.C. ()
E9
I/O
N.C. ()
D9
I/O
N.C. ()
B9
I/O
N.C. ()
A9
I/O
VCCO_0
C5
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
I/O
VCCO_0
VCCO_0
E7
VCCO_0
VCCO_0
C9
VCCO_0
VCCO_0
G9
VCCO_0
VCCO_0
J11
L12
C13
G13
L13
L14
E25
J21
K20
F18
F16
A16
J17
A27
B27
D26
C27
A26
B26
B25
C25
F24
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
IO
IO
IO
IO
I/O
IO
IO
I/O
IO
IO
I/O
IO
IO
I/O
IO
IO
I/O
IO/VREF_1
IO_L01N_1/VRP_1
IO_L01P_1/VRN_1
IO_L02N_1
IO_L02P_1
IO_L03N_1
IO_L03P_1
IO_L04N_1
IO_L04P_1
IO_L05N_1
IO/VREF_1
IO_L01N_1/VRP_1
IO_L01P_1/VRN_1
IO_L02N_1
IO_L02P_1
IO_L03N_1
IO_L03P_1
IO_L04N_1
IO_L04P_1
IO_L05N_1
VREF
DCI
DCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
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212
Spartan-3 FPGA Family: Pinout Descriptions
Table 107: FG900 Package Pinout (Cont’d)
XC3S2000
Pin Name
XC3S4000, XC3S5000 FG900 Pin
Pin Name
Bank
Type
Number
F25
C24
D24
A24
B24
H23
G24
F23
G23
C23
D23
A23
B23
H22
J22
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IO_L05P_1
IO_L05P_1
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IO_L06N_1/VREF_1
IO_L06P_1
IO_L07N_1
IO_L07P_1
IO_L08N_1
IO_L08P_1
IO_L09N_1
IO_L09P_1
IO_L10N_1/VREF_1
IO_L10P_1
IO_L11N_1
IO_L11P_1
IO_L12N_1
IO_L12P_1
IO_L13N_1
IO_L13P_1
IO_L14N_1
IO_L14P_1
IO_L15N_1
IO_L15P_1
IO_L16N_1
IO_L16P_1
IO_L17N_1/VREF_1
IO_L17P_1
IO_L18N_1
IO_L18P_1
IO_L19N_1
IO_L19P_1
IO_L20N_1
IO_L20P_1
IO_L21N_1
IO_L21P_1
IO_L22N_1
IO_L22P_1
IO_L23N_1
IO_L23P_1
IO_L24N_1
IO_L24P_1
IO_L25N_1
IO_L06N_1/VREF_1
IO_L06P_1
IO_L07N_1
IO_L07P_1
IO_L08N_1
IO_L08P_1
IO_L09N_1
IO_L09P_1
IO_L10N_1/VREF_1
IO_L10P_1
IO_L11N_1
IO_L11P_1
IO_L12N_1
IO_L12P_1
IO_L13N_1
IO_L13P_1
IO_L14N_1
IO_L14P_1
IO_L15N_1
IO_L15P_1
IO_L16N_1
IO_L16P_1
IO_L17N_1/VREF_1
IO_L17P_1
IO_L18N_1
IO_L18P_1
IO_L19N_1
IO_L19P_1
IO_L20N_1
IO_L20P_1
IO_L21N_1
IO_L21P_1
IO_L22N_1
IO_L22P_1
IO_L23N_1
IO_L23P_1
IO_L24N_1
IO_L24P_1
IO_L25N_1
F22
E23
D22
E22
A22
B22
F21
G21
B21
C21
G20
H20
E20
F20
C20
D20
A20
B20
J19
K19
G19
H19
E19
F19
C19
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Spartan-3 FPGA Family: Pinout Descriptions
Table 107: FG900 Package Pinout (Cont’d)
XC3S2000
Pin Name
XC3S4000, XC3S5000 FG900 Pin
Bank
Type
Pin Name
Number
D19
A19
B19
F17
G17
B17
C17
J16
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
IO_L25P_1
IO_L25P_1
I/O
I/O
IO_L26N_1
IO_L26P_1
IO_L27N_1
IO_L27P_1
IO_L28N_1
IO_L28P_1
IO_L29N_1
IO_L29P_1
IO_L30N_1
IO_L30P_1
IO_L31N_1/VREF_1
IO_L31P_1
IO_L32N_1/GCLK5
IO_L32P_1/GCLK4
N.C. ()
IO_L26N_1
IO_L26P_1
IO_L27N_1
IO_L27P_1
IO_L28N_1
IO_L28P_1
IO_L29N_1
IO_L29P_1
IO_L30N_1
IO_L30P_1
IO_L31N_1/VREF_1
IO_L31P_1
IO_L32N_1/GCLK5
IO_L32P_1/GCLK4
IO_L37N_1
IO_L37P_1
IO_L38N_1
IO_L38P_1
IO_L39N_1
IO_L39P_1
IO_L40N_1
IO_L40P_1
VCCO_1
I/O
I/O
I/O
I/O
I/O
I/O
K16
G16
H16
D16
E16
B16
C16
H18
J18
I/O
I/O
I/O
VREF
I/O
GCLK
GCLK
I/O
N.C. ()
I/O
N.C. ()
D18
E18
A18
B18
K17
K18
L17
C18
G18
L18
L19
J20
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
VCCO_1
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
I/O
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
C22
G22
E24
C26
J25
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
IO
IO
IO_L01N_2/VRP_2
IO_L01P_2/VRN_2
IO_L02N_2
IO_L02P_2
IO_L03N_2/VREF_2
IO_L03P_2
IO_L01N_2/VRP_2
IO_L01P_2/VRN_2
IO_L02N_2
IO_L02P_2
IO_L03N_2/VREF_2
IO_L03P_2
C29
C30
D27
D28
D29
D30
DCI
DCI
I/O
I/O
VREF
I/O
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214
Spartan-3 FPGA Family: Pinout Descriptions
Table 107: FG900 Package Pinout (Cont’d)
XC3S2000
Pin Name
XC3S4000, XC3S5000 FG900 Pin
Pin Name
Bank
Type
Number
E29
E30
F28
F29
G27
G28
G29
G30
G25
H24
H25
H26
H27
H28
H29
H30
J26
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO_L04N_2
IO_L04N_2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IO_L04P_2
IO_L05N_2
IO_L05P_2
IO_L06N_2
IO_L06P_2
IO_L07N_2
IO_L07P_2
IO_L08N_2
IO_L08P_2
IO_L09N_2/VREF_2
IO_L09P_2
IO_L10N_2
IO_L10P_2
IO_L12N_2
IO_L12P_2
IO_L13N_2
IO_L13P_2/VREF_2
IO_L14N_2
IO_L14P_2
IO_L15N_2
IO_L15P_2
IO_L16N_2
IO_L16P_2
IO_L19N_2
IO_L19P_2
IO_L20N_2
IO_L20P_2
IO_L21N_2
IO_L21P_2
IO_L22N_2
IO_L22P_2
IO_L23N_2/VREF_2
IO_L23P_2
IO_L24N_2
IO_L24P_2
IO_L26N_2
IO_L26P_2
IO_L27N_2
IO_L27P_2
IO_L04P_2
IO_L05N_2
IO_L05P_2
IO_L06N_2
IO_L06P_2
IO_L07N_2
IO_L07P_2
IO_L08N_2
IO_L08P_2
IO_L09N_2/VREF_2
IO_L09P_2
IO_L10N_2
IO_L10P_2
IO_L12N_2
IO_L12P_2
IO_L13N_2
IO_L13P_2/VREF_2
IO_L14N_2
IO_L14P_2
IO_L15N_2
IO_L15P_2
IO_L16N_2
IO_L16P_2
IO_L19N_2
IO_L19P_2
IO_L20N_2
IO_L20P_2
IO_L21N_2
IO_L21P_2
IO_L22N_2
IO_L22P_2
IO_L23N_2/VREF_2
IO_L23P_2
IO_L24N_2
IO_L24P_2
IO_L26N_2
IO_L26P_2
IO_L27N_2
IO_L27P_2
J27
J29
J30
J23
K22
K24
K25
L25
L26
L27
L28
L29
L30
M22
M23
M24
M25
M27
M28
M21
N21
N22
N23
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Product Specification
215
Spartan-3 FPGA Family: Pinout Descriptions
Table 107: FG900 Package Pinout (Cont’d)
XC3S2000
Pin Name
XC3S4000, XC3S5000 FG900 Pin
Pin Name
Bank
Type
Number
M26
N25
N26
N27
N29
N30
P21
P22
P24
P25
P28
P29
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
E27
F26
K28
K29
K21
L21
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO_L28N_2
IO_L28N_2
I/O
I/O
IO_L28P_2
IO_L29N_2
IO_L29P_2
IO_L31N_2
IO_L31P_2
IO_L32N_2
IO_L32P_2
IO_L33N_2
IO_L33P_2
IO_L34N_2/VREF_2
IO_L34P_2
IO_L35N_2
IO_L35P_2
IO_L37N_2
IO_L37P_2
IO_L38N_2
IO_L38P_2
IO_L39N_2
IO_L39P_2
IO_L40N_2
IO_L40P_2/VREF_2
N.C. ()
IO_L28P_2
IO_L29N_2
IO_L29P_2
IO_L31N_2
IO_L31P_2
IO_L32N_2
IO_L32P_2
IO_L33N_2
IO_L33P_2
IO_L34N_2/VREF_2
IO_L34P_2
IO_L35N_2
IO_L35P_2
IO_L37N_2
IO_L37P_2
IO_L38N_2
IO_L38P_2
IO_L39N_2
IO_L39P_2
IO_L40N_2
IO_L40P_2/VREF_2
IO_L41N_2
IO_L41P_2
IO_L45N_2
IO_L45P_2
IO_L46N_2
IO_L46P_2
IO_L47N_2
IO_L47P_2
IO_L50N_2
IO_L50P_2
VCCO_2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
L23
I/O
N.C. ()
L24
I/O
N.C. ()
M29
M30
M20
N20
P20
L22
I/O
N.C. ()
I/O
VCCO_2
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
J24
VCCO_2
VCCO_2
N24
G26
E28
VCCO_2
VCCO_2
VCCO_2
VCCO_2
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216
Spartan-3 FPGA Family: Pinout Descriptions
Table 107: FG900 Package Pinout (Cont’d)
XC3S2000
Pin Name
XC3S4000, XC3S5000 FG900 Pin
Bank
Type
Pin Name
Number
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
VCCO_2
VCCO_2
J28
VCCO
VCCO
I/O
VCCO_2
VCCO_2
N28
IO
IO
AB25
AH30
AH29
AG28
AG27
AG30
AG29
AF30
AF29
AE26
AF27
AE29
AE28
AD28
AD27
AD30
AD29
AC24
AD25
AC26
AC25
AC28
AC27
AC30
AC29
AB27
AB26
AB30
AB29
AA22
AB23
AA25
AA24
AA29
AA28
Y21
IO_L01N_3/VRP_3
IO_L01P_3/VRN_3
IO_L02N_3/VREF_3
IO_L02P_3
IO_L03N_3
IO_L03P_3
IO_L04N_3
IO_L04P_3
IO_L05N_3
IO_L05P_3
IO_L06N_3
IO_L06P_3
IO_L07N_3
IO_L07P_3
IO_L08N_3
IO_L08P_3
IO_L09N_3
IO_L09P_3/VREF_3
IO_L10N_3
IO_L10P_3
IO_L11N_3
IO_L11P_3
IO_L13N_3/VREF_3
IO_L13P_3
IO_L14N_3
IO_L14P_3
IO_L15N_3
IO_L15P_3
IO_L16N_3
IO_L16P_3
IO_L17N_3
IO_L17P_3/VREF_3
IO_L19N_3
IO_L19P_3
IO_L20N_3
IO_L20P_3
IO_L21N_3
IO_L01N_3/VRP_3
IO_L01P_3/VRN_3
IO_L02N_3/VREF_3
IO_L02P_3
IO_L03N_3
IO_L03P_3
IO_L04N_3
IO_L04P_3
IO_L05N_3
IO_L05P_3
IO_L06N_3
IO_L06P_3
IO_L07N_3
IO_L07P_3
IO_L08N_3
IO_L08P_3
IO_L09N_3
IO_L09P_3/VREF_3
IO_L10N_3
IO_L10P_3
IO_L11N_3
IO_L11P_3
IO_L13N_3/VREF_3
IO_L13P_3
IO_L14N_3
IO_L14P_3
IO_L15N_3
IO_L15P_3
IO_L16N_3
IO_L16P_3
IO_L17N_3
IO_L17P_3/VREF_3
IO_L19N_3
IO_L19P_3
IO_L20N_3
IO_L20P_3
IO_L21N_3
DCI
DCI
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
AA21
Y24
I/O
I/O
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Product Specification
217
Spartan-3 FPGA Family: Pinout Descriptions
Table 107: FG900 Package Pinout (Cont’d)
XC3S2000
Pin Name
XC3S4000, XC3S5000 FG900 Pin
Pin Name
Bank
Type
Number
Y23
Y26
Y25
Y28
Y27
Y30
Y29
W30
W29
V21
W21
V23
V22
V25
W26
V30
V29
U22
U21
U25
U24
U29
U28
T22
T21
T24
T23
T26
T25
T28
T27
T30
T29
W23
W22
W25
W24
W28
W27
V27
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO_L21P_3
IO_L21P_3
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IO_L22N_3
IO_L22P_3
IO_L23N_3
IO_L23P_3/VREF_3
IO_L24N_3
IO_L24P_3
IO_L26N_3
IO_L26P_3
IO_L27N_3
IO_L27P_3
IO_L28N_3
IO_L28P_3
IO_L29N_3
IO_L29P_3
IO_L31N_3
IO_L31P_3
IO_L32N_3
IO_L32P_3
IO_L33N_3
IO_L33P_3
IO_L34N_3
IO_L34P_3/VREF_3
IO_L35N_3
IO_L35P_3
IO_L37N_3
IO_L37P_3
IO_L38N_3
IO_L38P_3
IO_L39N_3
IO_L39P_3
IO_L40N_3/VREF_3
IO_L40P_3
N.C. ()
IO_L22N_3
IO_L22P_3
IO_L23N_3
IO_L23P_3/VREF_3
IO_L24N_3
IO_L24P_3
IO_L26N_3
IO_L26P_3
IO_L27N_3
IO_L27P_3
IO_L28N_3
IO_L28P_3
IO_L29N_3
IO_L29P_3
IO_L31N_3
IO_L31P_3
IO_L32N_3
IO_L32P_3
IO_L33N_3
IO_L33P_3
IO_L34N_3
IO_L34P_3/VREF_3
IO_L35N_3
IO_L35P_3
IO_L37N_3
IO_L37P_3
IO_L38N_3
IO_L38P_3
IO_L39N_3
IO_L39P_3
IO_L40N_3/VREF_3
IO_L40P_3
IO_L46N_3
IO_L46P_3
IO_L47N_3
IO_L47P_3
IO_L48N_3
IO_L48P_3
IO_L50N_3
N.C. ()
N.C. ()
N.C. ()
N.C. ()
N.C. ()
N.C. ()
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Product Specification
218
Spartan-3 FPGA Family: Pinout Descriptions
Table 107: FG900 Package Pinout (Cont’d)
XC3S2000
Pin Name
XC3S4000, XC3S5000 FG900 Pin
Bank
Type
Pin Name
Number
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
N.C. ()
IO_L50P_3
V26
I/O
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
I/O
VCCO_3
VCCO_3
U20
VCCO_3
VCCO_3
V20
VCCO_3
VCCO_3
W20
VCCO_3
VCCO_3
Y22
VCCO_3
VCCO_3
V24
VCCO_3
VCCO_3
AB24
AD26
V28
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
AB28
AF28
AA16
AG18
AA18
AE22
AD23
AH27
AF16
AK28
AJ27
AK27
AJ26
AK26
AG26
AF25
AD24
AC23
AE23
AF23
AG23
AH23
AJ23
AK23
AB22
AC22
AF22
AG22
AJ22
AK22
AD21
VCCO_3
VCCO_3
IO
IO
IO
IO
I/O
IO
IO
I/O
IO
IO
I/O
IO
IO
I/O
IO
IO
I/O
IO/VREF_4
IO/VREF_4
IO_L01N_4/VRP_4
IO_L01P_4/VRN_4
IO_L02N_4
IO_L02P_4
IO_L03N_4
IO_L03P_4
IO_L04N_4
IO_L04P_4
IO_L05N_4
IO_L05P_4
IO_L06N_4/VREF_4
IO_L06P_4
IO_L07N_4
IO_L07P_4
IO_L08N_4
IO_L08P_4
IO_L09N_4
IO_L09P_4
IO_L10N_4
IO_L10P_4
IO_L11N_4
IO/VREF_4
IO/VREF_4
IO_L01N_4/VRP_4
IO_L01P_4/VRN_4
IO_L02N_4
IO_L02P_4
IO_L03N_4
IO_L03P_4
IO_L04N_4
IO_L04P_4
IO_L05N_4
IO_L05P_4
IO_L06N_4/VREF_4
IO_L06P_4
IO_L07N_4
IO_L07P_4
IO_L08N_4
IO_L08P_4
IO_L09N_4
IO_L09P_4
IO_L10N_4
IO_L10P_4
IO_L11N_4
VREF
VREF
DCI
DCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
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219
Spartan-3 FPGA Family: Pinout Descriptions
Table 107: FG900 Package Pinout (Cont’d)
XC3S2000
Pin Name
XC3S4000, XC3S5000 FG900 Pin
Pin Name
Bank
Type
Number
AE21
AH21
AJ21
AB21
AA20
AC20
AD20
AE20
AF20
AG20
AH20
AJ20
AK20
AA19
AB19
AC19
AD19
AE19
AF19
AG19
AH19
AJ19
AK19
AB18
AC18
AE18
AF18
AJ18
AK18
AA17
AB17
AD17
AE17
AH17
AJ17
AB16
AC16
AD16
AE16
AG16
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
IO_L11P_4
IO_L11P_4
I/O
I/O
IO_L12N_4
IO_L12P_4
IO_L12N_4
IO_L12P_4
I/O
IO_L13N_4
IO_L13P_4
IO_L13N_4
IO_L13P_4
I/O
I/O
IO_L14N_4
IO_L14P_4
IO_L14N_4
IO_L14P_4
I/O
I/O
IO_L15N_4
IO_L15P_4
IO_L15N_4
IO_L15P_4
I/O
I/O
IO_L16N_4
IO_L16P_4
IO_L16N_4
IO_L16P_4
I/O
I/O
IO_L17N_4
IO_L17P_4
IO_L17N_4
IO_L17P_4
I/O
I/O
IO_L18N_4
IO_L18P_4
IO_L18N_4
IO_L18P_4
I/O
I/O
IO_L19N_4
IO_L19P_4
IO_L19N_4
IO_L19P_4
I/O
I/O
IO_L20N_4
IO_L20P_4
IO_L20N_4
IO_L20P_4
I/O
I/O
IO_L21N_4
IO_L21P_4
IO_L21N_4
IO_L21P_4
I/O
I/O
IO_L22N_4/VREF_4
IO_L22P_4
IO_L22N_4/VREF_4
IO_L22P_4
VREF
I/O
IO_L23N_4
IO_L23P_4
IO_L23N_4
IO_L23P_4
I/O
I/O
IO_L24N_4
IO_L24P_4
IO_L24N_4
IO_L24P_4
I/O
I/O
IO_L25N_4
IO_L25P_4
IO_L25N_4
IO_L25P_4
I/O
I/O
IO_L26N_4
IO_L26P_4/VREF_4
IO_L27N_4/DIN/D0
IO_L27P_4/D1
IO_L28N_4
IO_L28P_4
IO_L26N_4
IO_L26P_4/VREF_4
IO_L27N_4/DIN/D0
IO_L27P_4/D1
IO_L28N_4
IO_L28P_4
I/O
VREF
DUAL
DUAL
I/O
I/O
IO_L29N_4
IO_L29P_4
IO_L29N_4
IO_L29P_4
I/O
I/O
IO_L30N_4/D2
IO_L30P_4/D3
IO_L31N_4/INIT_B
IO_L30N_4/D2
IO_L30P_4/D3
IO_L31N_4/INIT_B
DUAL
DUAL
DUAL
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220
Spartan-3 FPGA Family: Pinout Descriptions
Table 107: FG900 Package Pinout (Cont’d)
XC3S2000
Pin Name
XC3S4000, XC3S5000 FG900 Pin
Bank
Type
Pin Name
Number
AH16
AJ16
AK16
AH25
AJ25
AE25
AE24
AG24
AH24
AJ24
AK24
Y17
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
IO_L31P_4/DOUT/BUSY IO_L31P_4/DOUT/BUSY
DUAL
GCLK
GCLK
I/O
IO_L32N_4/GCLK1
IO_L32P_4/GCLK0
N.C. ()
IO_L32N_4/GCLK1
IO_L32P_4/GCLK0
IO_L33N_4
IO_L33P_4
IO_L34N_4
IO_L34P_4
IO_L35N_4
IO_L35P_4
IO_L38N_4
IO_L38P_4
VCCO_4
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
VCCO_4
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
I/O
VCCO_4
VCCO_4
Y18
VCCO_4
VCCO_4
AD18
AH18
Y19
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
AB20
AD22
AH22
AF24
AH26
AE6
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
IO
IO
IO
IO
AB10
AA11
AA15
AE15
AH4
I/O
IO
IO
I/O
IO
IO
I/O
IO
IO
I/O
IO/VREF_5
IO/VREF_5
IO_L01N_5/RDWR_B
IO_L01P_5/CS_B
IO_L02N_5
IO_L02P_5
IO_L03N_5
IO_L03P_5
IO_L04N_5
IO_L04P_5
IO_L05N_5
IO_L05P_5
IO_L06N_5
IO_L06P_5
IO/VREF_5
IO/VREF_5
IO_L01N_5/RDWR_B
IO_L01P_5/CS_B
IO_L02N_5
IO_L02P_5
IO_L03N_5
IO_L03P_5
IO_L04N_5
IO_L04P_5
IO_L05N_5
IO_L05P_5
IO_L06N_5
IO_L06P_5
VREF
VREF
DUAL
DUAL
I/O
AK15
AK4
AJ4
AK5
AJ5
I/O
AF6
I/O
AG5
I/O
AJ6
I/O
AH6
I/O
AE7
I/O
AD7
I/O
AH7
I/O
AG7
I/O
DS099 (v3.1) June 27, 2013
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Product Specification
221
Spartan-3 FPGA Family: Pinout Descriptions
Table 107: FG900 Package Pinout (Cont’d)
XC3S2000
Pin Name
XC3S4000, XC3S5000 FG900 Pin
Bank
Type
Pin Name
Number
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
IO_L07N_5
IO_L07N_5
AK8
I/O
I/O
I/O
I/O
I/O
I/O
DCI
DCI
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IO_L07P_5
IO_L08N_5
IO_L08P_5
IO_L09N_5
IO_L09P_5
IO_L10N_5/VRP_5
IO_L10P_5/VRN_5
IO_L11N_5/VREF_5
IO_L11P_5
IO_L12N_5
IO_L12P_5
IO_L13N_5
IO_L13P_5
IO_L14N_5
IO_L14P_5
IO_L15N_5
IO_L15P_5
IO_L16N_5
IO_L16P_5
IO_L17N_5
IO_L17P_5
IO_L18N_5
IO_L18P_5
IO_L19N_5
IO_L19P_5/VREF_5
IO_L20N_5
IO_L20P_5
IO_L21N_5
IO_L21P_5
IO_L22N_5
IO_L22P_5
IO_L23N_5
IO_L23P_5
IO_L24N_5
IO_L24P_5
IO_L25N_5
IO_L25P_5
IO_L26N_5
IO_L26P_5
IO_L07P_5
IO_L08N_5
IO_L08P_5
IO_L09N_5
IO_L09P_5
IO_L10N_5/VRP_5
IO_L10P_5/VRN_5
IO_L11N_5/VREF_5
IO_L11P_5
IO_L12N_5
IO_L12P_5
IO_L13N_5
IO_L13P_5
IO_L14N_5
IO_L14P_5
IO_L15N_5
IO_L15P_5
IO_L16N_5
IO_L16P_5
IO_L17N_5
IO_L17P_5
IO_L18N_5
IO_L18P_5
IO_L19N_5
IO_L19P_5/VREF_5
IO_L20N_5
IO_L20P_5
IO_L21N_5
IO_L21P_5
IO_L22N_5
IO_L22P_5
IO_L23N_5
IO_L23P_5
IO_L24N_5
IO_L24P_5
IO_L25N_5
IO_L25P_5
IO_L26N_5
IO_L26P_5
AJ8
AC9
AB9
AG9
AF9
AK9
AJ9
AE10
AE9
AJ10
AH10
AD11
AD10
AF11
AE11
AH11
AG11
AK11
AJ11
AB12
AC11
AD12
AC12
AF12
AE12
AH12
AG12
AK12
AJ12
AA13
AA12
AC13
AB13
AG13
AF13
AK13
AJ13
AB14
AA14
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222
Spartan-3 FPGA Family: Pinout Descriptions
Table 107: FG900 Package Pinout (Cont’d)
XC3S2000
Pin Name
XC3S4000, XC3S5000 FG900 Pin
Bank
Type
Pin Name
IO_L27N_5/VREF_5
IO_L27P_5
Number
AE14
AE13
AJ14
AH14
AC15
AB15
AD15
AD14
AG15
AF15
AJ15
AH15
AK7
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
IO_L27N_5/VREF_5
IO_L27P_5
IO_L28N_5/D6
IO_L28P_5/D7
IO_L29N_5
IO_L29P_5/VREF_5
IO_L30N_5
IO_L30P_5
IO_L31N_5/D4
IO_L31P_5/D5
IO_L32N_5/GCLK3
IO_L32P_5/GCLK2
N.C. ()
VREF
I/O
IO_L28N_5/D6
IO_L28P_5/D7
IO_L29N_5
IO_L29P_5/VREF_5
IO_L30N_5
IO_L30P_5
DUAL
DUAL
I/O
VREF
I/O
I/O
IO_L31N_5/D4
IO_L31P_5/D5
IO_L32N_5/GCLK3
IO_L32P_5/GCLK2
IO_L35N_5
IO_L35P_5
DUAL
DUAL
GCLK
GCLK
I/O
N.C. ()
AJ7
I/O
N.C. ()
IO_L36N_5
IO_L36P_5
AD8
I/O
N.C. ()
AC8
I/O
N.C. ()
IO_L37N_5
IO_L37P_5
AF8
I/O
N.C. ()
AE8
I/O
N.C. ()
IO_L38N_5
IO_L38P_5
AH8
I/O
N.C. ()
AG8
AH5
I/O
VCCO_5
VCCO_5
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
I/O
VCCO_5
VCCO_5
AF7
VCCO_5
VCCO_5
AD9
VCCO_5
VCCO_5
AH9
VCCO_5
VCCO_5
AB11
Y12
VCCO_5
VCCO_5
VCCO_5
VCCO_5
Y13
VCCO_5
VCCO_5
AD13
AH13
Y14
VCCO_5
VCCO_5
VCCO_5
VCCO_5
IO
IO
AB6
IO_L01N_6/VRP_6
IO_L01P_6/VRN_6
IO_L02N_6
IO_L02P_6
IO_L03N_6/VREF_6
IO_L03P_6
IO_L04N_6
IO_L04P_6
IO_L05N_6
IO_L01N_6/VRP_6
IO_L01P_6/VRN_6
IO_L02N_6
IO_L02P_6
AH2
DCI
AH1
DCI
AG4
AG3
AG2
AG1
AF2
I/O
I/O
IO_L03N_6/VREF_6
IO_L03P_6
VREF
I/O
IO_L04N_6
IO_L04P_6
I/O
AF1
I/O
IO_L05N_6
AF4
I/O
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223
Spartan-3 FPGA Family: Pinout Descriptions
Table 107: FG900 Package Pinout (Cont’d)
XC3S2000
Pin Name
XC3S4000, XC3S5000 FG900 Pin
Pin Name
Bank
Type
Number
AE5
AE3
AE2
AD4
AD3
AD2
AD1
AD6
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AB5
AB4
AB2
AB1
AB8
AA9
AA7
AA6
AA3
AA2
AA10
Y10
Y8
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
IO_L05P_6
IO_L05P_6
I/O
I/O
IO_L06N_6
IO_L06P_6
IO_L07N_6
IO_L07P_6
IO_L08N_6
IO_L08P_6
IO_L09N_6/VREF_6
IO_L09P_6
IO_L10N_6
IO_L10P_6
IO_L11N_6
IO_L11P_6
IO_L13N_6
IO_L13P_6/VREF_6
IO_L14N_6
IO_L14P_6
IO_L15N_6
IO_L15P_6
IO_L16N_6
IO_L16P_6
IO_L17N_6
IO_L17P_6/VREF_6
IO_L19N_6
IO_L19P_6
IO_L20N_6
IO_L20P_6
IO_L21N_6
IO_L21P_6
IO_L22N_6
IO_L22P_6
IO_L24N_6/VREF_6
IO_L24P_6
N.C. ()
IO_L06N_6
IO_L06P_6
IO_L07N_6
IO_L07P_6
IO_L08N_6
IO_L08P_6
IO_L09N_6/VREF_6
IO_L09P_6
IO_L10N_6
IO_L10P_6
IO_L11N_6
IO_L11P_6
IO_L13N_6
IO_L13P_6/VREF_6
IO_L14N_6
IO_L14P_6
IO_L15N_6
IO_L15P_6
IO_L16N_6
IO_L16P_6
IO_L17N_6
IO_L17P_6/VREF_6
IO_L19N_6
IO_L19P_6
IO_L20N_6
IO_L20P_6
IO_L21N_6
IO_L21P_6
IO_L22N_6
IO_L22P_6
IO_L24N_6/VREF_6
IO_L24P_6
IO_L25N_6
IO_L25P_6
IO_L26N_6
IO_L26P_6
IO_L27N_6
IO_L27P_6
IO_L28N_6
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
Y7
I/O
Y6
I/O
Y5
I/O
Y2
VREF
I/O
Y1
W9
I/O
N.C. ()
W8
I/O
IO_L26N_6
IO_L26P_6
IO_L27N_6
IO_L27P_6
IO_L28N_6
W7
I/O
W6
I/O
W4
I/O
W3
I/O
W2
I/O
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Product Specification
224
Spartan-3 FPGA Family: Pinout Descriptions
Table 107: FG900 Package Pinout (Cont’d)
XC3S2000
Pin Name
XC3S4000, XC3S5000 FG900 Pin
Bank
Type
Pin Name
Number
W1
W10
V10
V9
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
7
IO_L28P_6
IO_L28P_6
I/O
I/O
IO_L29N_6
IO_L29P_6
N.C. ()
IO_L29N_6
IO_L29P_6
IO_L30N_6
IO_L30P_6
IO_L31N_6
IO_L31P_6
IO_L32N_6
IO_L32P_6
IO_L33N_6
IO_L33P_6
IO_L34N_6/VREF_6
IO_L34P_6
IO_L35N_6
IO_L35P_6
IO_L36N_6
IO_L36P_6
IO_L37N_6
IO_L37P_6
IO_L38N_6
IO_L38P_6
IO_L39N_6
IO_L39P_6
IO_L40N_6
IO_L40P_6/VREF_6
IO_L45N_6
IO_L45P_6
IO_L52N_6
IO_L52P_6
VCCO_6
I/O
I/O
N.C. ()
V8
I/O
IO_L31N_6
IO_L31P_6
IO_L32N_6
IO_L32P_6
IO_L33N_6
IO_L33P_6
IO_L34N_6/VREF_6
IO_L34P_6
IO_L35N_6
IO_L35P_6
N.C. ()
W5
V6
I/O
I/O
V5
I/O
V4
I/O
V2
I/O
V1
I/O
U10
U9
VREF
I/O
U7
I/O
U6
I/O
U3
I/O
N.C. ()
U2
I/O
IO_L37N_6
IO_L37P_6
IO_L38N_6
IO_L38P_6
IO_L39N_6
IO_L39P_6
IO_L40N_6
IO_L40P_6/VREF_6
N.C. ()
T10
T9
I/O
I/O
T6
I/O
T5
I/O
T4
I/O
T3
I/O
T2
I/O
T1
VREF
I/O
Y4
N.C. ()
Y3
I/O
N.C. ()
T8
I/O
N.C. ()
T7
I/O
VCCO_6
V3
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
I/O
VCCO_6
VCCO_6
AB3
AF3
AD5
V7
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
AB7
Y9
VCCO_6
VCCO_6
VCCO_6
VCCO_6
U11
V11
W11
J6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
IO
IO
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225
Spartan-3 FPGA Family: Pinout Descriptions
Table 107: FG900 Package Pinout (Cont’d)
XC3S2000
Pin Name
XC3S4000, XC3S5000 FG900 Pin
Bank
Type
Pin Name
IO_L01N_7/VRP_7
IO_L01P_7/VRN_7
IO_L02N_7
Number
C1
C2
D3
D4
D1
D2
E1
E2
F5
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
IO_L01N_7/VRP_7
IO_L01P_7/VRN_7
IO_L02N_7
DCI
DCI
I/O
IO_L02P_7
IO_L02P_7
I/O
IO_L03N_7/VREF_7
IO_L03P_7
IO_L03N_7/VREF_7
IO_L03P_7
VREF
I/O
IO_L04N_7
IO_L04N_7
I/O
IO_L04P_7
IO_L04P_7
I/O
IO_L05N_7
IO_L05N_7
I/O
IO_L05P_7
IO_L05P_7
E4
F2
I/O
IO_L06N_7
IO_L06N_7
I/O
IO_L06P_7
IO_L06P_7
F3
I/O
IO_L07N_7
IO_L07N_7
G3
G4
G1
G2
H7
G6
H5
H6
H3
H4
H1
H2
J4
I/O
IO_L07P_7
IO_L07P_7
I/O
IO_L08N_7
IO_L08N_7
I/O
IO_L08P_7
IO_L08P_7
I/O
IO_L09N_7
IO_L09N_7
I/O
IO_L09P_7
IO_L09P_7
I/O
IO_L10N_7
IO_L10N_7
I/O
IO_L10P_7/VREF_7
IO_L11N_7
IO_L10P_7/VREF_7
IO_L11N_7
VREF
I/O
IO_L11P_7
IO_L11P_7
I/O
IO_L13N_7
IO_L13N_7
I/O
IO_L13P_7
IO_L13P_7
I/O
IO_L14N_7
IO_L14N_7
I/O
IO_L14P_7
IO_L14P_7
J5
I/O
IO_L15N_7
IO_L15N_7
J1
I/O
IO_L15P_7
IO_L15P_7
J2
I/O
IO_L16N_7
IO_L16N_7
K9
J8
I/O
IO_L16P_7/VREF_7
IO_L17N_7
IO_L16P_7/VREF_7
IO_L17N_7
VREF
I/O
K6
K7
K2
K3
L10
K10
L7
IO_L17P_7
IO_L17P_7
I/O
IO_L19N_7/VREF_7
IO_L19P_7
IO_L19N_7/VREF_7
IO_L19P_7
VREF
I/O
IO_L20N_7
IO_L20N_7
I/O
IO_L20P_7
IO_L20P_7
I/O
IO_L21N_7
IO_L21N_7
I/O
IO_L21P_7
IO_L21P_7
L8
I/O
IO_L22N_7
IO_L22N_7
L5
I/O
IO_L22P_7
IO_L22P_7
L6
I/O
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Product Specification
226
Spartan-3 FPGA Family: Pinout Descriptions
Table 107: FG900 Package Pinout (Cont’d)
XC3S2000
Pin Name
XC3S4000, XC3S5000 FG900 Pin
Bank
Type
Pin Name
Number
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
IO_L23N_7
IO_L23N_7
L3
I/O
I/O
IO_L23P_7
IO_L24N_7
IO_L24P_7
N.C. ()
IO_L23P_7
IO_L24N_7
IO_L24P_7
IO_L25N_7
IO_L25P_7
IO_L26N_7
IO_L26P_7
IO_L27N_7
IO_L27P_7/VREF_7
IO_L28N_7
IO_L28P_7
IO_L29N_7
IO_L29P_7
IO_L31N_7
IO_L31P_7
IO_L32N_7
IO_L32P_7
IO_L33N_7
IO_L33P_7
IO_L34N_7
IO_L34P_7
IO_L35N_7
IO_L35P_7
IO_L37N_7
IO_L37P_7/VREF_7
IO_L38N_7
IO_L38P_7
IO_L39N_7
IO_L39P_7
IO_L40N_7/VREF_7
IO_L40P_7
IO_L46N_7
IO_L46P_7
IO_L49N_7
IO_L49P_7
IO_L50N_7
IO_L50P_7
VCCO_7
L4
L1
I/O
L2
I/O
M6
M7
M3
M4
M1
M2
N10
M10
N8
N9
N1
N2
P9
I/O
N.C. ()
I/O
IO_L26N_7
IO_L26P_7
IO_L27N_7
IO_L27P_7/VREF_7
IO_L28N_7
IO_L28P_7
IO_L29N_7
IO_L29P_7
IO_L31N_7
IO_L31P_7
IO_L32N_7
IO_L32P_7
IO_L33N_7
IO_L33P_7
IO_L34N_7
IO_L34P_7
IO_L35N_7
IO_L35P_7
IO_L37N_7
IO_L37P_7/VREF_7
IO_L38N_7
IO_L38P_7
IO_L39N_7
IO_L39P_7
IO_L40N_7/VREF_7
IO_L40P_7
N.C. ()
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P10
P6
I/O
I/O
P7
I/O
P2
I/O
P3
I/O
R9
R10
R7
R8
R5
R6
R3
R4
R1
R2
M8
M9
N6
M5
N4
N5
E3
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
VREF
I/O
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
VCCO_7
VCCO
VCCO
VCCO_7
VCCO_7
J3
DS099 (v3.1) June 27, 2013
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Product Specification
227
Spartan-3 FPGA Family: Pinout Descriptions
Table 107: FG900 Package Pinout (Cont’d)
XC3S2000
Pin Name
XC3S4000, XC3S5000 FG900 Pin
Bank
Type
Pin Name
Number
7
VCCO_7
VCCO_7
N3
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
GND
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
GND
G5
7
J7
7
N7
7
L9
7
M11
N11
P11
A1
7
7
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
GND
GND
B1
GND
GND
F1
GND
GND
K1
GND
GND
P1
GND
GND
U1
GND
GND
AA1
AE1
AJ1
AK1
A2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
B2
GND
GND
AJ2
E5
GND
GND
GND
GND
K5
GND
GND
P5
GND
GND
U5
GND
GND
AA5
AF5
A6
GND
GND
GND
GND
GND
GND
AK6
K8
GND
GND
GND
GND
P8
GND
GND
U8
GND
GND
AA8
A10
E10
H10
AC10
AF10
AK10
R12
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
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228
Spartan-3 FPGA Family: Pinout Descriptions
Table 107: FG900 Package Pinout (Cont’d)
XC3S2000
Pin Name
XC3S4000, XC3S5000 FG900 Pin
Bank
Type
Pin Name
Number
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
T12
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
N13
P13
R13
T13
U13
V13
A14
E14
H14
N14
P14
R14
T14
U14
V14
AC14
AF14
AK14
M15
N15
P15
R15
T15
U15
V15
W15
M16
N16
P16
R16
T16
U16
V16
W16
A17
E17
H17
N17
P17
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229
Spartan-3 FPGA Family: Pinout Descriptions
Table 107: FG900 Package Pinout (Cont’d)
XC3S2000
Pin Name
XC3S4000, XC3S5000 FG900 Pin
Bank
Type
Pin Name
Number
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
R17
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
T17
U17
V17
AC17
AF17
AK17
N18
P18
R18
T18
U18
V18
R19
T19
A21
E21
H21
AC21
AF21
AK21
K23
P23
U23
AA23
A25
AK25
E26
K26
P26
U26
AA26
AF26
A29
B29
AJ29
AK29
A30
B30
F30
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230
Spartan-3 FPGA Family: Pinout Descriptions
Table 107: FG900 Package Pinout (Cont’d)
XC3S2000
Pin Name
XC3S4000, XC3S5000 FG900 Pin
Bank
Type
Pin Name
Number
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
K30
GND
P30
GND
U30
AA30
AE30
AJ30
AK30
AK2
F4
GND
GND
GND
GND
GND
GND
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
K4
P4
U4
AA4
AE4
D6
AG6
D10
AG10
D14
AG14
D17
AG17
D21
AG21
D25
AG25
F27
K27
P27
U27
AA27
AE27
L11
R11
T11
Y11
M12
N12
P12
U12
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231
Spartan-3 FPGA Family: Pinout Descriptions
Table 107: FG900 Package Pinout (Cont’d)
XC3S2000
Pin Name
XC3S4000, XC3S5000 FG900 Pin
Bank
Type
Pin Name
Number
V12
W12
M13
W13
M14
W14
L15
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
JTAG
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
CCLK
Y15
L16
Y16
M17
W17
M18
W18
M19
N19
P19
U19
V19
W19
L20
R20
T20
Y20
AH28
AJ28
A3
VCCAUX CCLK
VCCAUX DONE
VCCAUX HSWAP_EN
VCCAUX M0
DONE
HSWAP_EN
M0
AJ3
AH3
AK3
B3
VCCAUX M1
M1
VCCAUX M2
M2
VCCAUX PROG_B
VCCAUX TCK
VCCAUX TDI
PROG_B
TCK
B28
C3
TDI
JTAG
VCCAUX TDO
VCCAUX TMS
TDO
C28
A28
JTAG
TMS
JTAG
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232
Spartan-3 FPGA Family: Pinout Descriptions
User I/Os by Bank
Table 108 indicates how the available user-I/O pins are distributed between the eight I/O banks for the XC3S2000 in the
FG900 package. Similarly, Table 109 shows how the available user-I/O pins are distributed between the eight I/O banks for
the XC3S4000 and XC3S5000 in the FG900 package.
Table 108: User I/Os Per Bank for XC3S2000 in FG900 Package
All Possible I/O Pins by Type
Edge
Top
I/O Bank
Maximum I/O
I/O
62
62
61
62
57
55
60
62
DUAL
DCI
2
VREF
GCLK
0
1
2
3
4
5
6
7
71
71
69
71
72
71
69
71
0
0
0
0
6
6
0
0
5
5
6
7
5
6
7
7
2
2
0
0
2
2
0
0
2
2
Right
Bottom
Left
2
2
2
2
2
Table 109: User I/Os Per Bank for XC3S4000 and XC3S5000 in FG900 Package
All Possible I/O Pins by Type
Edge
Top
I/O Bank
Maximum I/O
I/O
70
70
71
70
65
63
70
70
DUAL
DCI
2
VREF
GCLK
0
1
2
3
4
5
6
7
79
79
79
79
80
79
79
79
0
0
0
0
6
6
0
0
5
5
6
7
5
6
7
7
2
2
0
0
2
2
0
0
2
2
Right
Bottom
Left
2
2
2
2
2
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Product Specification
233
Spartan-3 FPGA Family: Pinout Descriptions
X-Ref Target - Figure 55
FG900 Footprint
Bank 0
1
2
3
4
5
I/O
6
7
8
I/O
9
10
11
I/O
12
I/O
13
I/O
14
15
I/O
L35P_0
I/O
L38P_0
I/O
I/O
HSWAP_
EN
Left Half of FG900
Package (Top View)
A
B
C
D
E
F
L01P_0
VRN_0
L32P_0
GCLK6
GND
GND
GND
GND
GND
L02P_0
L09P_0
L17P_0 L22P_0 L25P_0
I/O
L35N_0
I/O
L38N_0
I/O
L01N_0
VRP_0
I/O
L32N_0
GCLK7
I/O
I/O
I/O
L09N_0
I/O
I/O
I/O
I/O
I/O
PROG_B
GND
I/O
L01N_7 L01P_7
VRP_7
GND
I/O
L02N_0 L04P_0
L12P_0 L17N_0 L22N_0 L25N_0 L28P_0
I/O
L31P_0
VREF_0
XC3S2000
(565 max. user I/O)
IO
VREF_0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L28N_0
V
CCO_0
V
CCO_0
VCCO_0
TDI
I/O
L04N_0 L06P_0 L08P_0
L12N_0 L16P_0 L21P_0
V
RN_
7
I/O
I/O
L03N_7
VREF_7
I/O: Unrestricted,
general-purpose user I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L31N_0
L37P_0
481
VCCAUX
VCCAUX
VCCAUX
I/O
I/O
L03P_7 L02N_7 L02P_7 L03N_0
L06N_0 L08N_0
L16N_0 L21N_0
I/O
I/O
I/O
I/O
L05P_7
I/O
L03P_0
I/O
L07P_0
I/O
I/O
L37N_0
V
CCO_7
GND
V
CCO_0
GND
I/O
GND
I/O
I/O
L04N_7 L04P_7
L15P_0 L20P_0 L24P_0
VREF: User I/O or input
48
voltage reference for bank
I/O
L05P_0
VREF_0
IO
VREF_0
I/O
I/O
I/O
I/O
I/O
L07N_0
I/O I/O I/O
I/O
VCCAUX
GND
L06N_7 L06P_7
L05N_7 L05N_0
L11P_0 L15N_0 L20N_0 L24N_0 L27P_0 L30P_0
I/O
L36N_0
N.C.: Unconnected pins for
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
68
V
CCO_7
VCCO_0
VCCO_0
I/O
G
H
J
L08N_7 L08P_7 L07N_7 L07P_7
L09P_7
L11N_0 L14P_0 L19P_0
L27N_0 L30N_0
XC3S2000 ()
I/O
L36P_0
I/O
L10P_7
VREF_7
I/O
I/O
I/O
I/O
I/O
I/O
L09N_7
I/O
L10P_0
I/O
I/O
I/O
I/O
GND
GND
I/O
L13N_7 L13P_7 L11N_7 L11P_7 L10N_7
L14N_0 L19N_0 L23P_0
L29P_0
XC3S4000, XC3S5000
(633 max user I/O)
I/O
L16P_7
VREF_7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
V
CCO_7
VCCO_7
VCCO_0
I/O
L26P_0
L29N_0
VREF_0
L15N_7 L15P_7
L14N_7 L14P_7
L10N_0 L13N_0
L18P_0 L23N_0
I/O: Unrestricted,
general-purpose user I/O
549
I/O
I/O
L19P_7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCAUX
I/O
GND
GND
I/O
GND
I/O
K
L
L19N_7
L17N_7 L17P_7
L16N_7 L20P_7 L13P_0 L18N_0
I/O
VCCO_0 VCCO_0 VCCO_0
VCCINT VCCINT
L26N_0
VREF_7
VREF: User I/O or input
48
I/O
I/O
I/O
I/O I/O
VCCO_7
L24N_7 L24P_7 L23N_7 L23P_7 L22N_7 L22P_7 L21N_7 L21P_7
L20N_7
voltage reference for bank
I/O
I/O
I/O
I/O
I/O
I/O
L27P_7
VREF_7
I/O
L27N_7
I/O
I/O
I/O
L28P_7
L49P_7 L25N_7 L25P_7 L46N_7 L46P_7
V
CCO_7
VCCINT VCCINT VCCINT GND
M
N
P
R
T
L26N_7 L26P_7
N.C.: No unconnected pins
in this package
0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L50N_7 L50P_7 L49N_7
V
CCO_7
V
CCO_7
VCCO_7
VCCINT GND
GND
GND
L31N_7 L31P_7
L29N_7 L29P_7 L28N_7
I/O
I/O
I/O
I/O
I/O
I/O
All devices
VCCAUX
VCCO_7
VCCINT
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCCINT
I/O
L34N_7 L34P_7
L33N_7 L33P_7
L32N_7 L32P_7
DUAL: Configuration pin,
then possible user I/O
12
I/O
L40N_7
VREF_7
I/O
L37P_7
VREF_7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCINT
VCCINT
GND
GND
GND
GND
GND
GND
L40P_7 L39N_7 L39P_7 L38N_7 L38P_7 L37N_7
L35N_7 L35P_7
I/O
I/O
I/O
L40P_6
VREF_6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L52P_6 L52N_6
GCLK: User I/O or global
clock buffer input
L40N_6 L39P_6 L39N_6 L38P_6 L38N_6
L37P_6 L37N_6
8
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L36P_6 L36N_6
VCCO_6
GND
VCCAUX GND
VCCINT
VCCINT
U
V
L34N_6
L34P_6
VREF_6
L35P_6 L35N_6
DCI: User I/O or reference
16
I/O
I/O
resistor input for bank
I/O
I/O
I/O
I/O
I/O
L30P_6 L30N_6
VCCO_6
VCCO_6
VCCO_6
L33P_6 L33N_6
L32P_6 L32N_6 L31P_6
L29P_6
I/O
I/O
I/O
I/O
I/O
I/O I/O I/O
L28N_6 L27P_6 L27N_6 L31N_6 L26P_6 L26N_6
I/O
I/O
L29N_6
L25P_6 L25N_6
CONFIG: Dedicated
configuration pins
VCCO_6
VCCINT VCCINT VCCINT
W L28P_6
7
I/O
I/O
I/O
L24N_6
VREF_6
I/O
Y
I/O
I/O
I/O
I/O
I/O
L20P_6
L45P_6 L45N_6
V
CCO_6
VCCO_5 VCCO_5 VCCO_5
VCCINT
I/O
L24P_6
L22P_6 L22N_6 L21P_6 L21N_6
JTAG: Dedicated JTAG port
pins
4
I/O
I/O
A
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
A
GND
GND
VCCAUX
L17P_6
VREF_6
L19P_6 L19N_6
L17N_6
L16P_6 L20N_6
L22P_5 L22N_5 L26P_5
I/O
L29P_5
VREF_5
A
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
V
CCO_6
V
CCO_6
VCCO_5
VCCINT: Internal core
32
I/O
L15P_6 L15N_6
L14P_6 L14N_6
L16N_6 L08P_5
L17N_5 L23P_5 L26N_5
B
voltage supply (+1.2V)
I/O
L36P_5
I/O
A L13P_6
C VREF_6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L29N_5
GND
I/O
GND
I/O
L13N_6 L11P_6 L11N_6 L10P_6 L10N_6 L09P_6
L08N_5
L17P_5 L18P_5 L23N_5
VCCO: Output voltage
I/O
L36N_5
80
I/O
L09N_6
VREF_6
A
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
supply for bank
V
CCO_6
V
CCO_5
VCCO_5
L08P_6 L08N_6 L07P_6 L07N_6
L05P_5
L13P_5 L13N_5 L18N_5
L30P_5 L30N_5
D
I/O
I/O
L11N_5
VREF_5
I/O
L19P_5
VREF_5
I/O
L27N_5
VREF_5
A
E
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L37P_5
VCCAUX
GND
I/O
I/O
I/O
VCCAUX: Auxiliary voltage
supply (+2.5V)
L06P_6 L06N_6
L05P_6
L05N_5
L11P_5
L14P_5
L27P_5
24
I/O
I/O
L31P_5
D5
A
F
I/O
I/O
L05N_6
I/O
L03N_5
I/O
L09P_5
I/O
I/O
I/O
L37N_5
VCCO_5
VCCO_6
GND
GND
GND
L04P_6 L04N_6
L14N_5 L19N_5 L24P_5
I/O
120 GND: Ground
I/O
I/O
I/O
L31N_5
D4
A
G
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L38P_5
V
CCAUX
L03N_6
L03P_6
VREF_6
VCCAUX
I/O
VCCAUX
I/O
L02P_6 L02N_6 L03P_5
L06P_5
L09N_5
L15P_5 L20P_5 L24N_5
I/O
L38N_5
I/O
I/O
I/O
I/O
A
H
IO
VREF_5
I/O
I/O
I/O
V
CCO_5
V
CCO_5
V
CCO_5
M1
M0
M2
L01P_6 L01N_6
VRN_6 VRP_6
L28P_5 L32P_5
L04P_5 L06N_5
L12P_5 L15N_5 L20N_5
D7
GCLK2
I/O
L35P_5
I/O
L01P_5
CS_B
I/O
L10P_5
VRN_5
I/O
I/O
A
J
I/O
I/O
I/O
L07P_5
I/O
I/O
I/O
I/O
GND
GND
GND
GND
L28N_5 L32N_5
L02P_5 L04N_5
L12N_5 L16P_5 L21P_5 L25P_5
D6
GCLK3
I/O
L35N_5
I/O
L01N_5
RDWR_B
I/O
L10N_5
VRP_5
A
K
IO
VREF_5
I/O
GND
I/O
L07N_5
I/O
I/O
I/O
GND
GND
L02N_5
L16N_5 L21N_5 L25N_5
Bank 5
DS099-4_13a_121103
Figure 55: FG900 Package Footprint (Top View)
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
234
Spartan-3 FPGA Family: Pinout Descriptions
Bank 1
16
17
18
19
I/O
20
I/O
21
22
23
I/O
24
I/O
25
26
I/O
27
28
29
30
I/O
I/O
I/O
L39N_1
I/O
GND
GND
GND
TMS
GND
GND
L01N_1
VRP_1
A
Right Half of FG900
Package (Top View)
L26N_1 L21N_1
L15N_1 L11N_1 L07N_1
L03N_1
I/O
I/O
L32N_1
GCLK5
I/O
L17N_1
VREF_1
I/O
I/O
L28N_1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L39P_1
TCK
GND
I/O
GND
I/O
L01P_1
L15P_1 L11P_1 L07P_1 L04N_1 L03P_1
VRN_1
B
L26P_1 L21P_1
I/O
L32P_1
GCLK4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCO_1
VCCO_1
TDO
I/O
L10N_1 L06N_1
VREF_1 VREF_1
L01N_2 L01P_2 C
VCCO_1
L28P_1
L25N_1 L20N_1 L17P_1
L04P_1
L02P_1
VRP_2 VRN_2
I/O
L38N_1
I/O
L31N_1
VREF_1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCAUX
GND
L03N_2
VREF_2
D
E
F
VCCAUX
VCCAUX
L25P_1 L20P_1
L14N_1 L10P_1 L06P_1
L02N_1 L02N_2 L02P_2
L03P_2
I/O
L38P_1
I/O
L41N_2
I/O
L31P_1
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
GND
VCCO_2
I/O
VCCO_1
L24N_1 L19N_1
L14P_1 L13P_1
L04N_2 L04P_2
I/O
L41P_2
I/O
L27N_1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCCAUX
L24P_1 L19P_1 L16N_1 L13N_1 L09N_1 L05N_1 L05P_1
L05N_2 L05P_2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCO_1
VCCO_2
VCCO_1
G
H
J
L30N_1 L27P_1
L23N_1 L18N_1 L16P_1
L09P_1 L08P_1 L08N_2
L06N_2 L06P_2 L07N_2 L07P_2
I/O
L37N_1
I/O
L09N_2
VREF_2
I/O
L30P_1
I/O
I/O
I/O
I/O
I/O
I/O
I/O I/O I/O I/O
L09P_2 L10N_2 L10P_2 L12N_2 L12P_2
GND
GND
I/O
L23P_1 L18P_1
L12N_1 L08N_1 L08P_2
I/O
L37P_1
I/O
L13P_2
VREF_2
IO
VREF_1
I/O
L29N_1
I/O
I/O
I/O
I/O
L13N_2
I/O
I/O
VCCO_1
L22N_1
I/O
VCCO_2
I/O
VCCO_2
I/O
L45N_2 L45P_2
L12P_1 L15N_2
L14N_2 L14P_2
I/O
I/O
I/O
L46N_2
I/O
I/O
L29P_1
I/O
I/O
I/O
L15P_2
I/O
L40N_1 L40P_1
GND
GND
GND
I/O
K
L
VCCAUX
L22P_1
L16N_2 L16P_2
I/O
L46P_2
I/O
I/O
I/O
L47N_2 L47P_2
I/O
I/O
I/O
I/O
VCCO_2
VCCINT
VCCINT
VCCO_1 VCCO_1 VCCO_1
L19N_2 L19P_2 L20N_2 L20P_2 L21N_2 L21P_2
I/O
I/O
I/O
L23N_2
VREF_2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L50N_2 L50P_2
GND VCCINT VCCINT VCCINT
VCCO_2
M
N
P
L26N_2 L22N_2 L22P_2
L23P_2 L28N_2 L24N_2 L24P_2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND VCCINT
GND VCCINT
VCCO_2
VCCO_2
VCCO_2
VCCO_2
L26P_2 L27N_2 L27P_2
L28P_2 L29N_2 L29P_2
L31N_2 L31P_2
I/O
L34N_2
VREF_2
I/O
I/O
I/O
I/O
I/O
L34P_2
GND
I/O
GND
GND
VCCAUX
L32N_2 L32P_2
L33N_2 L33P_2
I/O I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
GND VCCINT
GND VCCINT
L40P_2 R
L35N_2 L35P_2 L37N_2 L37P_2 L38N_2 L38P_2 L39N_2 L39P_2 L40N_2
VREF_2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L40N_3 T
L35P_3 L35N_3 L37P_3 L37N_3 L38P_3 L38N_3 L39P_3 L39N_3 L40P_3
VREF_3
I/O
L34P_3
VREF_3
I/O
I/O
I/O
I/O
I/O
L34N_3
GND VCCINT
GND
I/O
GND
I/O
VCCAUX
I/O
GND
U
VCCO_3
L32P_3 L32N_3
L33P_3 L33N_3
I/O
I/O
I/O
VCCO_3
I/O
I/O
L50P_3 L50N_3
GND VCCINT VCCO_3
VCCO_3
I/O
V
L27N_3 L28P_3 L28N_3
L29N_3
L31P_3 L31N_3
I/O
I/O
I/O
I/O
I/O
I/O
L27P_3
I/O
L29P_3
I/O
I/O
L46P_3 L46N_3 L47P_3 L47N_3
L48P_3 L48N_3
VCCO_3
GND VCCINT VCCINT VCCINT
W
Y
L26P_3 L26N_3
I/O
I/O
L20N_3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCINT VCCO_4 VCCO_4 VCCO_4 VCCINT
L23P_3
L23N_3 L24P_3 L24N_3
VREF_3
VCCO_3
L21P_3 L21N_3 L22P_3 L22N_3
I/O
I/O
A
A
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCAUX
I/O
I/O
I/O
GND
GND
GND
I/O
L17P_3
VREF_3
L26N_4
L18N_4 L13P_4 L20P_3 L16N_3
L17N_3
L19P_3 L19N_3
I/O
L26P_4
VREF_4
A
B
I/O
L29N_4
I/O
I/O
L13N_4
I/O
I/O
I/O
I/O
I/O
VCCO_4
I/O
VCCO_3
VCCO_3
L23N_4 L18P_4
L08N_4 L16P_3
L14P_3 L14N_3
I/O I/O
L15P_3 L15N_3
I/O
I/O
A
C
I/O
L29P_4
I/O I/O
L23P_4 L19N_4 L14N_4
I/O
I/O I/O
I/O
I/O
I/O
GND
GND
L13N_3
VREF_3
L08P_4 L04P_4 L09N_3 L10P_3 L10N_3 L11P_3 L11N_3 L13P_3
I/O
L27N_4
DIN
I/O
L30N_4
D2
I/O
A
D
I/O
I/O
I/O
I/O
L04N_4
I/O
I/O
I/O
I/O
VCCO_4
I/O
L09P_3 VCCO_3
VREF_3
VCCO_4
L19P_4 L14P_4 L11N_4
L07P_3 L07N_3 L08P_3 L08N_3
D0
I/O
I/O
I/O
I/O
I/O
A
E
I/O
I/O I/O I/O
I/O
I/O
I/O
L34P_4 L34N_4
I/O
I/O
VCCAUX
GND
L30P_4 L27P_4
L24N_4 L20N_4 L15N_4 L11P_4
L05N_4
L05N_3
GND
I/O
L06P_3 L06N_3
D3
D1
A
F
I/O
VREF_4
I/O
I/O
I/O
I/O
I/O
L03P_4
I/O
L05P_3
I/O
I/O
VCCO_3
GND
GND
VCCO_4
L24P_4 L20P_4 L15P_4
L09N_4 L05P_4
L04P_3 L04N_3
I/O
L35N_4
I/O
L31N_4
INIT_B
I/O
I/O
I/O
L02N_3
VREF_3
A
G
I/O
I/O
I/O
I/O
I/O
VCCAUX
I/O
I/O
VCCAUX
I/O
VCCAUX
I/O
L06N_4
L09P_4
VREF_4
L21N_4 L16N_4
L03N_4 L02P_3
L03P_3 L03N_3
I/O
I/O
I/O
I/O
A
H
I/O
I/O
I/O
L31P_4
L35P_4 L33N_4
I/O
CCLK
DONE
L01P_3 L01N_3
VRN_3 VRP_3
VCCO_4
I/O
VCCO_4
L06P_4
VCCO_4
DOUT L28N_4
L21P_4 L16P_4 L12N_4
BUSY
I/O
I/O
I/O
I/O
I/O
L22N_4
VREF_4
I/O
I/O
A
J
I/O
I/O
I/O
I/O
L38N_4 L33P_4
GND
GND
GND
GND
L32N_4
L01N_4
L02N_4
VRP_4
L28P_4 L25N_4
L17N_4 L12P_4 L10N_4 L07N_4
GCLK1
I/O
L38P_4
I/O
L32P_4
GCLK0
I/O
I/O
A
K
IO
VREF_4
I/O
I/O
I/O
I/O
I/O
GND
GND
GND
L01P_4
L02P_4
VRN_4
L25P_4 L22P_4 L17P_4
L10P_4 L07P_4
Bank 4
DS099-4_13b_121103
Figure 56: FG900 Package Footprint (Top View) Continued
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
235
Spartan-3 FPGA Family: Pinout Descriptions
FG1156: 1156-lead Fine-pitch Ball Grid Array
Note: The FG(G)1156 package is discontinued. See
http://www.xilinx.com/support/documentation/spartan-3_customer_notices.htm.
The 1,156-lead fine-pitch ball grid array package, FG1156, supports two different Spartan-3 devices, namely the XC3S4000
and the XC3S5000. The XC3S4000, however, has fewer I/O pins, which consequently results in 73 unconnected pins on the
FG1156 package, labeled as “N.C.” In Table 110 and Figure 53, these unconnected pins are indicated with a black diamond
symbol ().
The XC3S5000 has a single unconnected package pin, ball AK31, which is also unconnected for the XC3S4000.
All the package pins appear in Table 110 and are sorted by bank number, then by pin name. Pairs of pins that form a
differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type, as
defined earlier.
On ball L29 in I/O Bank 2, the unconnected pin on the XC3S4000 maps to a VREF-type pin on the XC3S5000. If the other
VREF_2 pins all connect to a voltage reference to support a special I/O standard, then also connect the N.C. pin on the
XC3S4000 to the same VREF_2 voltage.
Pinout Table
Table 110: FG1156 Package Pinout
XC3S4000
Pin Name
XC3S5000
Pin Name
FG1156
Pin Number
Bank
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
B9
E17
F6
I/O
I/O
I/O
F8
I/O
G12
H8
I/O
I/O
H9
I/O
J11
J9
I/O
N.C. ()
N.C. ()
IO
I/O
K11
K13
K16
K17
L13
L16
L17
D5
I/O
I/O
IO
I/O
IO
I/O
IO
I/O
IO
I/O
IO
I/O
IO/VREF_0
IO/VREF_0
IO/VREF_0
IO/VREF_0
IO_L01N_0/VRP_0
IO_L01P_0/VRN_0
IO_L02N_0
IO_L02P_0
IO_L03N_0
IO/VREF_0
VREF
VREF
VREF
VREF
DCI
DCI
I/O
IO/VREF_0
E10
J14
L15
B3
IO/VREF_0
IO/VREF_0
IO_L01N_0/VRP_0
IO_L01P_0/VRN_0
IO_L02N_0
A3
B4
IO_L02P_0
A4
I/O
IO_L03N_0
C5
I/O
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
236
Spartan-3 FPGA Family: Pinout Descriptions
Table 110: FG1156 Package Pinout (Cont’d)
XC3S4000
Pin Name
XC3S5000
Pin Name
FG1156
Pin Number
Bank
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO_L03P_0
IO_L03P_0
B5
D6
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IO_L04N_0
IO_L04P_0
IO_L05N_0
IO_L05P_0/VREF_0
IO_L06N_0
IO_L06P_0
IO_L07N_0
IO_L07P_0
IO_L08N_0
IO_L08P_0
IO_L09N_0
IO_L09P_0
IO_L10N_0
IO_L10P_0
IO_L11N_0
IO_L11P_0
IO_L12N_0
IO_L12P_0
IO_L13N_0
IO_L13P_0
IO_L14N_0
IO_L14P_0
IO_L15N_0
IO_L15P_0
IO_L16N_0
IO_L16P_0
IO_L17N_0
IO_L17P_0
IO_L18N_0
IO_L18P_0
IO_L19N_0
IO_L19P_0
IO_L20N_0
IO_L20P_0
IO_L21N_0
IO_L21P_0
IO_L22N_0
IO_L22P_0
IO_L23N_0
IO_L04N_0
IO_L04P_0
IO_L05N_0
IO_L05P_0/VREF_0
IO_L06N_0
IO_L06P_0
IO_L07N_0
IO_L07P_0
IO_L08N_0
IO_L08P_0
IO_L09N_0
IO_L09P_0
IO_L10N_0
IO_L10P_0
IO_L11N_0
IO_L11P_0
IO_L12N_0
IO_L12P_0
IO_L13N_0
IO_L13P_0
IO_L14N_0
IO_L14P_0
IO_L15N_0
IO_L15P_0
IO_L16N_0
IO_L16P_0
IO_L17N_0
IO_L17P_0
IO_L18N_0
IO_L18P_0
IO_L19N_0
IO_L19P_0
IO_L20N_0
IO_L20P_0
IO_L21N_0
IO_L21P_0
IO_L22N_0
IO_L22P_0
IO_L23N_0
C6
B6
A6
F7
E7
G9
F9
D9
C9
J10
H10
G10
F10
L12
K12
J12
H12
F12
E12
D12
C12
B12
A12
H13
G13
D13
C13
L14
K14
H14
G14
F14
E14
D14
C14
B14
A14
K15
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Product Specification
237
Spartan-3 FPGA Family: Pinout Descriptions
Table 110: FG1156 Package Pinout (Cont’d)
XC3S4000
Pin Name
XC3S5000
Pin Name
FG1156
Pin Number
Bank
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO_L23P_0
IO_L23P_0
J15
G15
F15
D15
C15
B15
A15
G16
F16
C16
B16
J17
H17
G17
F17
D17
C17
B17
A17
D7
I/O
I/O
IO_L24N_0
IO_L24P_0
IO_L25N_0
IO_L25P_0
IO_L26N_0
IO_L26P_0/VREF_0
IO_L27N_0
IO_L27P_0
IO_L28N_0
IO_L28P_0
IO_L29N_0
IO_L29P_0
IO_L30N_0
IO_L30P_0
IO_L31N_0
IO_L31P_0/VREF_0
IO_L32N_0/GCLK7
IO_L32P_0/GCLK6
N.C. ()
IO_L24N_0
IO_L24P_0
IO_L25N_0
IO_L25P_0
IO_L26N_0
IO_L26P_0/VREF_0
IO_L27N_0
IO_L27P_0
IO_L28N_0
IO_L28P_0
IO_L29N_0
IO_L29P_0
IO_L30N_0
IO_L30P_0
IO_L31N_0
IO_L31P_0/VREF_0
IO_L32N_0/GCLK7
IO_L32P_0/GCLK6
IO_L33N_0
IO_L33P_0
IO_L34N_0
IO_L34P_0
IO_L35N_0
IO_L35P_0
IO_L36N_0
IO_L36P_0
IO_L37N_0
IO_L37P_0
IO_L38N_0
IO_L38P_0
IO_L39N_0
IO_L39P_0
IO_L40N_0
IO_L40P_0
VCCO_0
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
GCLK
GCLK
I/O
N.C. ()
C7
I/O
N.C. ()
B7
I/O
N.C. ()
A7
I/O
IO_L35N_0
IO_L35P_0
IO_L36N_0
IO_L36P_0
IO_L37N_0
IO_L37P_0
IO_L38N_0
IO_L38P_0
N.C. ()
E8
I/O
D8
I/O
B8
I/O
A8
I/O
D10
C10
B10
A10
G11
F11
B11
A11
B13
C4
I/O
I/O
I/O
I/O
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
VCCO_0
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO_0
VCCO_0
VCCO_0
VCCO_0
C8
VCCO_0
VCCO_0
D11
D16
VCCO_0
VCCO_0
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Product Specification
238
Spartan-3 FPGA Family: Pinout Descriptions
Table 110: FG1156 Package Pinout (Cont’d)
XC3S4000
Pin Name
XC3S5000
Pin Name
FG1156
Pin Number
Bank
Type
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VCCO_0
VCCO_0
F13
G8
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
I/O
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
IO
VCCO_0
VCCO_0
H11
H15
M13
M14
M15
M16
B26
A18
C23
E21
E25
F18
F27
F29
H23
H26
J26
K19
L19
L20
L21
L23
L24
D30
K21
L18
A32
B32
A31
B31
B30
C30
C29
D29
A29
B29
E28
F28
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
IO
IO
IO
I/O
IO
IO
I/O
IO
IO
I/O
IO
IO
I/O
IO
IO
I/O
IO
IO
I/O
IO
IO
I/O
IO
IO
I/O
IO
IO
I/O
N.C. ()
IO
IO
I/O
IO
I/O
IO
IO
I/O
IO
IO
I/O
IO
IO
I/O
N.C. ()
IO
IO
I/O
IO
I/O
IO/VREF_1
IO/VREF_1
IO/VREF_1
IO_L01N_1/VRP_1
IO_L01P_1/VRN_1
IO_L02N_1
IO_L02P_1
IO_L03N_1
IO_L03P_1
IO_L04N_1
IO_L04P_1
IO_L05N_1
IO_L05P_1
IO_L06N_1/VREF_1
IO_L06P_1
IO/VREF_1
IO/VREF_1
IO/VREF_1
IO_L01N_1/VRP_1
IO_L01P_1/VRN_1
IO_L02N_1
IO_L02P_1
IO_L03N_1
IO_L03P_1
IO_L04N_1
IO_L04P_1
IO_L05N_1
IO_L05P_1
IO_L06N_1/VREF_1
IO_L06P_1
VREF
VREF
VREF
DCI
DCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
DS099 (v3.1) June 27, 2013
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Product Specification
239
Spartan-3 FPGA Family: Pinout Descriptions
Table 110: FG1156 Package Pinout (Cont’d)
XC3S4000
Pin Name
XC3S5000
Pin Name
FG1156
Pin Number
Bank
Type
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IO_L07N_1
IO_L07N_1
D27
E27
A27
B27
F26
G26
C26
D26
H25
J25
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IO_L07P_1
IO_L08N_1
IO_L08P_1
IO_L09N_1
IO_L09P_1
IO_L10N_1/VREF_1
IO_L10P_1
IO_L11N_1
IO_L11P_1
IO_L12N_1
IO_L12P_1
IO_L13N_1
IO_L13P_1
IO_L14N_1
IO_L14P_1
IO_L15N_1
IO_L15P_1
IO_L16N_1
IO_L16P_1
IO_L17N_1/VREF_1
IO_L17P_1
IO_L18N_1
IO_L18P_1
IO_L19N_1
IO_L19P_1
IO_L20N_1
IO_L20P_1
IO_L21N_1
IO_L21P_1
IO_L22N_1
IO_L22P_1
IO_L23N_1
IO_L23P_1
IO_L24N_1
IO_L24P_1
IO_L25N_1
IO_L25P_1
IO_L26N_1
IO_L26P_1
IO_L07P_1
IO_L08N_1
IO_L08P_1
IO_L09N_1
IO_L09P_1
IO_L10N_1/VREF_1
IO_L10P_1
IO_L11N_1
IO_L11P_1
IO_L12N_1
IO_L12P_1
IO_L13N_1
IO_L13P_1
IO_L14N_1
IO_L14P_1
IO_L15N_1
IO_L15P_1
IO_L16N_1
IO_L16P_1
IO_L17N_1/VREF_1
IO_L17P_1
IO_L18N_1
IO_L18P_1
IO_L19N_1
IO_L19P_1
IO_L20N_1
IO_L20P_1
IO_L21N_1
IO_L21P_1
IO_L22N_1
IO_L22P_1
IO_L23N_1
IO_L23P_1
IO_L24N_1
IO_L24P_1
IO_L25N_1
IO_L25P_1
IO_L26N_1
IO_L26P_1
F25
G25
C25
D25
A25
B25
A24
B24
J23
K23
F23
G23
D23
E23
A23
B23
K22
L22
G22
H22
C22
D22
H21
J21
F21
G21
C21
D21
A21
B21
DS099 (v3.1) June 27, 2013
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Product Specification
240
Spartan-3 FPGA Family: Pinout Descriptions
Table 110: FG1156 Package Pinout (Cont’d)
XC3S4000
Pin Name
XC3S5000
Pin Name
FG1156
Pin Number
Bank
Type
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IO_L27N_1
IO_L27N_1
F19
G19
B19
C19
J18
I/O
I/O
IO_L27P_1
IO_L28N_1
IO_L28P_1
IO_L29N_1
IO_L29P_1
IO_L30N_1
IO_L30P_1
IO_L31N_1/VREF_1
IO_L31P_1
IO_L32N_1/GCLK5
IO_L32P_1/GCLK4
N.C. ()
IO_L27P_1
IO_L28N_1
IO_L28P_1
IO_L29N_1
IO_L29P_1
IO_L30N_1
IO_L30P_1
IO_L31N_1/VREF_1
IO_L31P_1
IO_L32N_1/GCLK5
IO_L32P_1/GCLK4
IO_L33N_1
IO_L33P_1
IO_L34N_1
IO_L34P_1
IO_L35N_1
IO_L35P_1
IO_L36N_1
IO_L36P_1
IO_L37N_1
IO_L37P_1
IO_L38N_1
IO_L38P_1
IO_L39N_1
IO_L39P_1
IO_L40N_1
IO_L40P_1
VCCO_1
I/O
I/O
I/O
K18
G18
H18
D18
E18
B18
C18
C28
D28
A28
B28
J24
I/O
I/O
I/O
VREF
I/O
GCLK
GCLK
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
K24
F24
G24
J20
I/O
N.C. ()
I/O
N.C. ()
I/O
IO_L37N_1
IO_L37P_1
IO_L38N_1
IO_L38P_1
IO_L39N_1
IO_L39P_1
IO_L40N_1
IO_L40P_1
VCCO_1
I/O
K20
F20
G20
C20
D20
A20
B20
B22
C27
C31
D19
D24
F22
G27
H20
H24
M19
M20
M21
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
DS099 (v3.1) June 27, 2013
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Product Specification
241
Spartan-3 FPGA Family: Pinout Descriptions
Table 110: FG1156 Package Pinout (Cont’d)
XC3S4000
Pin Name
XC3S5000
Pin Name
FG1156
Pin Number
Bank
Type
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
VCCO_1
VCCO_1
M22
G33
G34
U25
U26
C33
C34
D33
D34
E32
E33
F31
F32
G29
G30
H29
H30
H33
H34
J28
J29
H31
J31
J32
J33
J27
K26
K27
K28
K29
K30
K31
K32
K33
K34
L25
L26
L28
L29
VCCO
I/O
IO
IO
IO
IO
I/O
IO
IO
I/O
IO
IO
I/O
IO_L01N_2/VRP_2
IO_L01P_2/VRN_2
IO_L02N_2
IO_L02P_2
IO_L03N_2/VREF_2
IO_L03P_2
IO_L04N_2
IO_L04P_2
IO_L05N_2
IO_L05P_2
IO_L06N_2
IO_L06P_2
IO_L07N_2
IO_L07P_2
IO_L08N_2
IO_L08P_2
IO_L09N_2/VREF_2
IO_L09P_2
IO_L10N_2
IO_L10P_2
IO_L11N_2
IO_L11P_2
IO_L12N_2
IO_L12P_2
IO_L13N_2
IO_L13P_2/VREF_2
IO_L14N_2
IO_L14P_2
IO_L15N_2
IO_L15P_2
IO_L16N_2
IO_L16P_2
N.C. ()
IO_L01N_2/VRP_2
IO_L01P_2/VRN_2
IO_L02N_2
IO_L02P_2
IO_L03N_2/VREF_2
IO_L03P_2
IO_L04N_2
IO_L04P_2
IO_L05N_2
IO_L05P_2
IO_L06N_2
IO_L06P_2
IO_L07N_2
IO_L07P_2
IO_L08N_2
IO_L08P_2
IO_L09N_2/VREF_2
IO_L09P_2
IO_L10N_2
IO_L10P_2
IO_L11N_2
IO_L11P_2
IO_L12N_2
IO_L12P_2
IO_L13N_2
IO_L13P_2/VREF_2
IO_L14N_2
IO_L14P_2
IO_L15N_2
IO_L15P_2
IO_L16N_2
IO_L16P_2
IO_L17N_2
DCI
DCI
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
N.C. ()
IO_L17P_2/
VREF_2
VREF
DS099 (v3.1) June 27, 2013
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Product Specification
242
Spartan-3 FPGA Family: Pinout Descriptions
Table 110: FG1156 Package Pinout (Cont’d)
XC3S4000
Pin Name
XC3S5000
Pin Name
FG1156
Pin Number
Bank
Type
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO_L19N_2
IO_L19N_2
M29
M30
M31
M32
M26
N25
N27
N28
N31
N32
N24
P24
P29
P30
P31
P32
P33
P34
R24
R25
R28
R29
R31
R32
R33
R34
R26
T25
T28
T29
T32
T33
U27
U28
U29
U30
U31
U32
U33
U34
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
IO_L19P_2
IO_L20N_2
IO_L20P_2
IO_L21N_2
IO_L21P_2
IO_L22N_2
IO_L22P_2
IO_L23N_2/VREF_2
IO_L23P_2
IO_L24N_2
IO_L24P_2
IO_L26N_2
IO_L26P_2
IO_L27N_2
IO_L27P_2
IO_L28N_2
IO_L28P_2
IO_L29N_2
IO_L29P_2
IO_L30N_2
IO_L30P_2
IO_L31N_2
IO_L31P_2
IO_L32N_2
IO_L32P_2
IO_L33N_2
IO_L33P_2
IO_L34N_2/VREF_2
IO_L34P_2
IO_L35N_2
IO_L35P_2
IO_L37N_2
IO_L37P_2
IO_L38N_2
IO_L38P_2
IO_L39N_2
IO_L39P_2
IO_L40N_2
IO_L40P_2/VREF_2
IO_L19P_2
IO_L20N_2
IO_L20P_2
IO_L21N_2
IO_L21P_2
IO_L22N_2
IO_L22P_2
IO_L23N_2VREF_2
IO_L23P_2
IO_L24N_2
IO_L24P_2
IO_L26N_2
IO_L26P_2
IO_L27N_2
IO_L27P_2
IO_L28N_2
IO_L28P_2
IO_L29N_2
IO_L29P_2
IO_L30N_2
IO_L30P_2
IO_L31N_2
IO_L31P_2
IO_L32N_2
IO_L32P_2
IO_L33N_2
IO_L33P_2
IO_L34N_2/VREF_2
IO_L34P_2
IO_L35N_2
IO_L35P_2
IO_L37N_2
IO_L37P_2
IO_L38N_2
IO_L38P_2
IO_L39N_2
IO_L39P_2
IO_L40N_2
IO_L40P_2/VREF_2
DS099 (v3.1) June 27, 2013
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Product Specification
243
Spartan-3 FPGA Family: Pinout Descriptions
Table 110: FG1156 Package Pinout (Cont’d)
XC3S4000
Pin Name
XC3S5000
Pin Name
FG1156
Pin Number
Bank
Type
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
IO_L41N_2
IO_L41N_2
F33
F34
I/O
I/O
IO_L41P_2
N.C. ()
IO_L41P_2
IO_L42N_2
IO_L42P_2
IO_L45N_2
IO_L45P_2
IO_L46N_2
IO_L46P_2
IO_L47N_2
IO_L47P_2
IO_L48N_2
IO_L48P_2
IO_L49N_2
IO_L49P_2
IO_L50N_2
IO_L50P_2
IO_L51N_2
IO_L51P_2
VCCO_2
G31
G32
L33
I/O
N.C. ()
I/O
IO_L45N_2
IO_L45P_2
IO_L46N_2
IO_L46P_2
IO_L47N_2
IO_L47P_2
IO_L48N_2
IO_L48P_2
N.C. ()
I/O
L34
I/O
M24
M25
M27
M28
M33
M34
P25
P26
P27
P28
T24
I/O
I/O
I/O
I/O
I/O
I/O
I/O
N.C. ()
I/O
IO_L50N_2
IO_L50P_2
N.C. ()
I/O
I/O
I/O
N.C. ()
U24
D32
H28
H32
L27
I/O
VCCO_2
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
I/O
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
L31
VCCO_2
VCCO_2
N23
N29
N33
P23
R23
R27
T23
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
T31
IO
IO
AH33
AH34
V25
V26
AM34
AM33
AL34
AL33
AK33
IO
IO
I/O
IO
IO
I/O
IO
IO
I/O
IO_L01N_3/VRP_3
IO_L01P_3/VRN_3
IO_L02N_3/VREF_3
IO_L02P_3
IO_L03N_3
IO_L01N_3/VRP_3
IO_L01P_3/VRN_3
IO_L02N_3/VREF_3
IO_L02P_3
IO_L03N_3
DCI
DCI
VREF
I/O
I/O
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244
Spartan-3 FPGA Family: Pinout Descriptions
Table 110: FG1156 Package Pinout (Cont’d)
XC3S4000
Pin Name
XC3S5000
Pin Name
FG1156
Pin Number
Bank
Type
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO_L03P_3
IO_L03P_3
AK32
AJ32
AJ31
AJ34
AJ33
AH30
AH29
AG30
AG29
AG34
AG33
AF29
AF28
AF31
AG31
AF33
AF32
AE26
AF27
AE28
AE27
AE30
AE29
AE32
AE31
AE34
AE33
AD26
AD25
AD34
AD33
AC25
AC24
AC28
AC27
AC30
AC29
AC32
AC31
AB25
I/O
I/O
IO_L04N_3
IO_L04P_3
IO_L05N_3
IO_L05P_3
IO_L06N_3
IO_L06P_3
IO_L07N_3
IO_L07P_3
IO_L08N_3
IO_L08P_3
IO_L09N_3
IO_L09P_3/VREF_3
IO_L10N_3
IO_L10P_3
IO_L11N_3
IO_L11P_3
IO_L12N_3
IO_L12P_3
IO_L13N_3/VREF_3
IO_L13P_3
IO_L14N_3
IO_L14P_3
IO_L15N_3
IO_L15P_3
IO_L16N_3
IO_L16P_3
IO_L17N_3
IO_L17P_3/VREF_3
IO_L19N_3
IO_L19P_3
IO_L20N_3
IO_L20P_3
IO_L21N_3
IO_L21P_3
IO_L22N_3
IO_L22P_3
IO_L23N_3
IO_L23P_3/VREF_3
IO_L24N_3
IO_L04N_3
IO_L04P_3
IO_L05N_3
IO_L05P_3
IO_L06N_3
IO_L06P_3
IO_L07N_3
IO_L07P_3
IO_L08N_3
IO_L08P_3
IO_L09N_3
IO_L09P_3/VREF_3
IO_L10N_3
IO_L10P_3
IO_L11N_3
IO_L11P_3
IO_L12N_3
IO_L12P_3
IO_L13N_3/VREF_3
IO_L13P_3
IO_L14N_3
IO_L14P_3
IO_L15N_3
IO_L15P_3
IO_L16N_3
IO_L16P_3
IO_L17N_3
IO_L17P_3/VREF_3
IO_L19N_3
IO_L19P_3
IO_L20N_3
IO_L20P_3
IO_L21N_3
IO_L21P_3
IO_L22N_3
IO_L22P_3
IO_L23N_3
IO_L23P_3/VREF_3
IO_L24N_3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
DS099 (v3.1) June 27, 2013
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Product Specification
245
Spartan-3 FPGA Family: Pinout Descriptions
Table 110: FG1156 Package Pinout (Cont’d)
XC3S4000
Pin Name
XC3S5000
Pin Name
FG1156
Pin Number
Bank
Type
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO_L24P_3
IO_L24P_3
AC26
AA28
AA27
AA30
AA29
AA32
AA31
AA34
AA33
Y29
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IO_L26N_3
IO_L26P_3
IO_L27N_3
IO_L27P_3
IO_L28N_3
IO_L28P_3
IO_L29N_3
IO_L29P_3
IO_L30N_3
IO_L30P_3
IO_L31N_3
IO_L31P_3
IO_L32N_3
IO_L32P_3
IO_L33N_3
IO_L33P_3
IO_L34N_3
IO_L34P_3/VREF_3
IO_L35N_3
IO_L35P_3
IO_L37N_3
IO_L37P_3
IO_L38N_3
IO_L38P_3
IO_L39N_3
IO_L39P_3
IO_L40N_3/VREF_3
IO_L40P_3
N.C. ()
IO_L26N_3
IO_L26P_3
IO_L27N_3
IO_L27P_3
IO_L28N_3
IO_L28P_3
IO_L29N_3
IO_L29P_3
IO_L30N_3
IO_L30P_3
IO_L31N_3
IO_L31P_3
IO_L32N_3
IO_L32P_3
IO_L33N_3
IO_L33P_3
IO_L34N_3
IO_L34P_3/VREF_3
IO_L35N_3
IO_L35P_3
IO_L37N_3
IO_L37P_3
IO_L38N_3
IO_L38P_3
IO_L39N_3
IO_L39P_3
IO_L40N_3/VREF_3
IO_L40P_3
IO_L41N_3
IO_L41P_3
IO_L44N_3
IO_L44P_3
IO_L45N_3
IO_L45P_3
IO_L46N_3
IO_L46P_3
IO_L47N_3
IO_L47P_3
IO_L48N_3
Y28
Y32
Y31
Y34
Y33
W25
Y26
W29
W28
W33
W32
V28
V27
V30
V29
V32
V31
V34
V33
AH32
AH31
AD29
AD28
AC34
AC33
AB28
AB27
AB32
AB31
AA24
N.C. ()
N.C. ()
N.C. ()
IO_L45N_3
IO_L45P_3
IO_L46N_3
IO_L46P_3
IO_L47N_3
IO_L47P_3
IO_L48N_3
DS099 (v3.1) June 27, 2013
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Product Specification
246
Spartan-3 FPGA Family: Pinout Descriptions
Table 110: FG1156 Package Pinout (Cont’d)
XC3S4000
Pin Name
XC3S5000
Pin Name
FG1156
Pin Number
Bank
Type
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
IO_L48P_3
IO_L48P_3
AB24
AA26
AA25
Y25
I/O
I/O
N.C. ()
N.C. ()
IO_L50N_3
IO_L50P_3
N.C. ()
N.C. ()
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
IO
IO_L49N_3
IO_L49P_3
IO_L50N_3
IO_L50P_3
IO_L51N_3
IO_L51P_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
IO
I/O
I/O
Y24
I/O
V24
I/O
W24
I/O
AA23
AB23
AB29
AB33
AD27
AD31
AG28
AG32
AL32
W23
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
I/O
W31
Y23
Y27
AD18
AD19
AD20
AD22
AE18
AE19
AE22
AE24
AF24
AF26
AG26
AG27
AJ27
AJ29
AK25
AN26
AF21
AH23
AK18
AL30
IO
IO
I/O
IO
IO
I/O
IO
IO
I/O
IO
IO
I/O
IO
IO
I/O
IO
IO
I/O
N.C. ()
IO
IO
I/O
IO
I/O
N.C. ()
IO
IO
I/O
IO
I/O
IO
IO
I/O
IO
IO
I/O
IO
IO
I/O
IO
IO
I/O
IO
IO
I/O
IO/VREF_4
IO/VREF_4
IO/VREF_4
IO/VREF_4
IO/VREF_4
IO/VREF_4
IO/VREF_4
IO/VREF_4
VREF
VREF
VREF
VREF
DS099 (v3.1) June 27, 2013
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Product Specification
247
Spartan-3 FPGA Family: Pinout Descriptions
Table 110: FG1156 Package Pinout (Cont’d)
XC3S4000
Pin Name
XC3S5000
FG1156
Bank
Type
Pin Name
IO_L01N_4/VRP_4
IO_L01P_4/VRN_4
IO_L02N_4
IO_L02P_4
IO_L03N_4
IO_L03P_4
IO_L04N_4
IO_L04P_4
IO_L05N_4
IO_L05P_4
IO_L06N_4/VREF_4
IO_L06P_4
IO_L07N_4
IO_L07P_4
IO_L08N_4
IO_L08P_4
IO_L09N_4
IO_L09P_4
IO_L10N_4
IO_L10P_4
IO_L11N_4
IO_L11P_4
IO_L12N_4
IO_L12P_4
IO_L13N_4
IO_L13P_4
IO_L14N_4
IO_L14P_4
IO_L15N_4
IO_L15P_4
IO_L16N_4
IO_L16P_4
IO_L17N_4
IO_L17P_4
IO_L18N_4
IO_L18P_4
IO_L19N_4
IO_L19P_4
IO_L20N_4
IO_L20P_4
Pin Number
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
IO_L01N_4/VRP_4
IO_L01P_4/VRN_4
IO_L02N_4
IO_L02P_4
IO_L03N_4
IO_L03P_4
IO_L04N_4
IO_L04P_4
IO_L05N_4
IO_L05P_4
IO_L06N_4/VREF_4
IO_L06P_4
IO_L07N_4
IO_L07P_4
IO_L08N_4
IO_L08P_4
IO_L09N_4
IO_L09P_4
IO_L10N_4
IO_L10P_4
IO_L11N_4
IO_L11P_4
IO_L12N_4
IO_L12P_4
IO_L13N_4
IO_L13P_4
IO_L14N_4
IO_L14P_4
IO_L15N_4
IO_L15P_4
IO_L16N_4
IO_L16P_4
IO_L17N_4
IO_L17P_4
IO_L18N_4
IO_L18P_4
IO_L19N_4
IO_L19P_4
IO_L20N_4
IO_L20P_4
AN32
AP32
AN31
AP31
AM30
AN30
AN27
AP27
AH26
AJ26
AL26
AM26
AF25
AG25
AH25
AJ25
AL25
AM25
AN25
AP25
AD23
AE23
AF23
AG23
AJ23
AK23
AL23
AM23
AN23
AP23
AG22
AH22
AL22
AM22
AD21
AE21
AG21
AH21
AJ21
AK21
DCI
DCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DS099 (v3.1) June 27, 2013
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Product Specification
248
Spartan-3 FPGA Family: Pinout Descriptions
Table 110: FG1156 Package Pinout (Cont’d)
XC3S4000
Pin Name
XC3S5000
Pin Name
FG1156
Pin Number
Bank
Type
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
IO_L21N_4
IO_L21N_4
AL21
AM21
AN21
AP21
AE20
AF20
AH20
AJ20
AL20
AM20
AN20
AP20
AH19
AJ19
AM19
AN19
AF18
AG18
AH18
AJ18
AL18
AM18
AN18
AP18
AL29
AM29
AN29
AP29
AJ28
AK28
AL28
AM28
AN28
AP28
AK27
AL27
AH24
AJ24
AN24
AP24
I/O
I/O
IO_L21P_4
IO_L21P_4
IO_L22N_4/VREF_4
IO_L22P_4
IO_L22N_4/VREF_4
IO_L22P_4
VREF
I/O
IO_L23N_4
IO_L23N_4
I/O
IO_L23P_4
IO_L23P_4
I/O
IO_L24N_4
IO_L24N_4
I/O
IO_L24P_4
IO_L24P_4
I/O
IO_L25N_4
IO_L25N_4
I/O
IO_L25P_4
IO_L25P_4
I/O
IO_L26N_4
IO_L26N_4
I/O
IO_L26P_4/VREF_4
IO_L27N_4/DIN/D0
IO_L27P_4/D1
IO_L28N_4
IO_L26P_4/VREF_4
IO_L27N_4/DIN/D0
IO_L27P_4/D1
IO_L28N_4
VREF
DUAL
DUAL
I/O
IO_L28P_4
IO_L28P_4
I/O
IO_L29N_4
IO_L29N_4
I/O
IO_L29P_4
IO_L29P_4
I/O
IO_L30N_4/D2
IO_L30P_4/D3
IO_L31N_4/INIT_B
IO_L30N_4/D2
IO_L30P_4/D3
IO_L31N_4/INIT_B
DUAL
DUAL
DUAL
DUAL
GCLK
GCLK
I/O
IO_L31P_4/DOUT/BUSY IO_L31P_4/DOUT/BUSY
IO_L32N_4/GCLK1
IO_L32P_4/GCLK0
IO_L33N_4
IO_L33P_4
IO_L34N_4
IO_L34P_4
IO_L35N_4
IO_L35P_4
N.C. ()
IO_L32N_4/GCLK1
IO_L32P_4/GCLK0
IO_L33N_4
IO_L33P_4
IO_L34N_4
IO_L34P_4
IO_L35N_4
IO_L35P_4
IO_L36N_4
IO_L36P_4
IO_L37N_4
IO_L37P_4
IO_L38N_4
IO_L38P_4
IO_L39N_4
IO_L39P_4
IO_L40N_4
IO_L40P_4
I/O
I/O
I/O
I/O
I/O
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
IO_L38N_4
IO_L38P_4
N.C. ()
I/O
I/O
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
DS099 (v3.1) June 27, 2013
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Product Specification
249
Spartan-3 FPGA Family: Pinout Descriptions
Table 110: FG1156 Package Pinout (Cont’d)
XC3S4000
Pin Name
XC3S5000
Pin Name
FG1156
Pin Number
Bank
Type
4
4
4
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
VCCO_4
VCCO_4
AC19
AC20
AC21
AC22
AG20
AG24
AH27
AJ22
AL19
AL24
AM27
AM31
AN22
AD11
AD12
AD14
AD15
AD16
AD17
AE14
AE16
AF9
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
I/O
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
IO
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
IO
N.C. ()
IO
IO
I/O
IO
I/O
IO
IO
I/O
IO
IO
I/O
IO
IO
I/O
IO
IO
I/O
IO
IO
I/O
N.C. ()
IO
IO
I/O
IO
AG9
I/O
IO
IO
AG12
AJ6
I/O
IO
IO
I/O
IO
IO
AJ17
AK10
AK14
AM12
AN9
I/O
IO
IO
I/O
IO
IO
I/O
IO
IO
I/O
IO
IO
I/O
IO/VREF_5
IO/VREF_5
IO/VREF_5
IO_L01N_5/RDWR_B
IO_L01P_5/CS_B
IO_L02N_5
IO_L02P_5
IO_L03N_5
IO_L03P_5
IO_L04N_5
IO/VREF_5
IO/VREF_5
IO/VREF_5
IO_L01N_5/RDWR_B
IO_L01P_5/CS_B
IO_L02N_5
IO_L02P_5
IO_L03N_5
IO_L03P_5
IO_L04N_5
AJ8
VREF
VREF
VREF
DUAL
DUAL
I/O
AL5
AP17
AP3
AN3
AP4
AN4
I/O
AN5
I/O
AM5
I/O
AM6
I/O
DS099 (v3.1) June 27, 2013
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Product Specification
250
Spartan-3 FPGA Family: Pinout Descriptions
Table 110: FG1156 Package Pinout (Cont’d)
XC3S4000
Pin Name
XC3S5000
Pin Name
FG1156
Pin Number
Bank
Type
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
IO_L04P_5
IO_L04P_5
AL6
AP6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DCI
DCI
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IO_L05N_5
IO_L05P_5
IO_L06N_5
IO_L06P_5
IO_L07N_5
IO_L07P_5
IO_L08N_5
IO_L08P_5
IO_L09N_5
IO_L09P_5
IO_L10N_5/VRP_5
IO_L10P_5/VRN_5
IO_L11N_5/VREF_5
IO_L11P_5
IO_L12N_5
IO_L12P_5
IO_L13N_5
IO_L13P_5
IO_L14N_5
IO_L14P_5
IO_L15N_5
IO_L15P_5
IO_L16N_5
IO_L16P_5
IO_L17N_5
IO_L17P_5
IO_L18N_5
IO_L18P_5
IO_L19N_5
IO_L19P_5/VREF_5
IO_L20N_5
IO_L20P_5
IO_L21N_5
IO_L21P_5
IO_L22N_5
IO_L22P_5
IO_L23N_5
IO_L23P_5
IO_L24N_5
IO_L05N_5
IO_L05P_5
IO_L06N_5
IO_L06P_5
IO_L07N_5
IO_L07P_5
IO_L08N_5
IO_L08P_5
IO_L09N_5
IO_L09P_5
IO_L10N_5/VRP_5
IO_L10P_5/VRN_5
IO_L11N_5/VREF_5
IO_L11P_5
IO_L12N_5
IO_L12P_5
IO_L13N_5
IO_L13P_5
IO_L14N_5
IO_L14P_5
IO_L15N_5
IO_L15P_5
IO_L16N_5
IO_L16P_5
IO_L17N_5
IO_L17P_5
IO_L18N_5
IO_L18P_5
IO_L19N_5
IO_L19P_5/VREF_5
IO_L20N_5
IO_L20P_5
IO_L21N_5
IO_L21P_5
IO_L22N_5
IO_L22P_5
IO_L23N_5
IO_L23P_5
IO_L24N_5
AN6
AK7
AJ7
AG10
AF10
AJ10
AH10
AM10
AL10
AP10
AN10
AP11
AN11
AF12
AE12
AJ12
AH12
AL12
AK12
AP12
AN12
AE13
AD13
AH13
AG13
AM13
AL13
AG14
AF14
AJ14
AH14
AM14
AL14
AP14
AN14
AF15
AE15
AJ15
DS099 (v3.1) June 27, 2013
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Product Specification
251
Spartan-3 FPGA Family: Pinout Descriptions
Table 110: FG1156 Package Pinout (Cont’d)
XC3S4000
Pin Name
XC3S5000
Pin Name
FG1156
Pin Number
Bank
Type
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
IO_L24P_5
IO_L24P_5
AH15
AM15
AL15
AP15
AN15
AJ16
AH16
AN16
AM16
AF17
AE17
AH17
AG17
AL17
AK17
AN17
AM17
AM7
I/O
I/O
IO_L25N_5
IO_L25P_5
IO_L26N_5
IO_L26P_5
IO_L27N_5/VREF_5
IO_L27P_5
IO_L28N_5/D6
IO_L28P_5/D7
IO_L29N_5
IO_L29P_5/VREF_5
IO_L30N_5
IO_L30P_5
IO_L31N_5/D4
IO_L31P_5/D5
IO_L32N_5/GCLK3
IO_L32P_5/GCLK2
N.C. ()
IO_L25N_5
IO_L25P_5
IO_L26N_5
IO_L26P_5
IO_L27N_5/VREF_5
IO_L27P_5
IO_L28N_5/D6
IO_L28P_5/D7
IO_L29N_5
IO_L29P_5/VREF_5
IO_L30N_5
IO_L30P_5
IO_L31N_5/D4
IO_L31P_5/D5
IO_L32N_5/GCLK3
IO_L32P_5/GCLK2
IO_L33N_5
IO_L33P_5
IO_L34N_5
IO_L34P_5
IO_L35N_5
IO_L35P_5
IO_L36N_5
IO_L36P_5
IO_L37N_5
IO_L37P_5
IO_L38N_5
IO_L38P_5
IO_L39N_5
IO_L39P_5
IO_L40N_5
IO_L40P_5
VCCO_5
I/O
I/O
I/O
VREF
I/O
DUAL
DUAL
I/O
VREF
I/O
I/O
DUAL
DUAL
GCLK
GCLK
I/O
N.C. ()
AL7
I/O
N.C. ()
AP7
I/O
N.C. ()
AN7
I/O
IO_L35N_5
IO_L35P_5
IO_L36N_5
IO_L36P_5
IO_L37N_5
IO_L37P_5
IO_L38N_5
IO_L38P_5
N.C. ()
AL8
I/O
AK8
I/O
AP8
I/O
AN8
I/O
AJ9
I/O
AH9
I/O
AM9
I/O
AL9
I/O
AF11
AE11
AJ11
AH11
AC13
AC14
AC15
AC16
AG11
AG15
AH8
I/O
N.C. ()
I/O
N.C. ()
I/O
N.C. ()
I/O
VCCO_5
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
DS099 (v3.1) June 27, 2013
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Product Specification
252
Spartan-3 FPGA Family: Pinout Descriptions
Table 110: FG1156 Package Pinout (Cont’d)
XC3S4000
Pin Name
XC3S5000
Pin Name
FG1156
Pin Number
Bank
Type
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
VCCO_5
VCCO_5
AJ13
AL11
AL16
AM4
AM8
AN13
AH1
AH2
V9
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
I/O
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
IO
IO
IO
IO
I/O
IO
IO
I/O
IO
IO
V10
AM2
AM1
AL2
AL1
AK3
AK2
AJ4
I/O
IO_L01N_6/VRP_6
IO_L01P_6/VRN_6
IO_L02N_6
IO_L02P_6
IO_L03N_6/VREF_6
IO_L03P_6
IO_L04N_6
IO_L04P_6
IO_L05N_6
IO_L05P_6
IO_L06N_6
IO_L06P_6
IO_L07N_6
IO_L07P_6
IO_L08N_6
IO_L08P_6
IO_L09N_6/VREF_6
IO_L09P_6
IO_L10N_6
IO_L10P_6
IO_L11N_6
IO_L11P_6
IO_L12N_6
IO_L12P_6
IO_L13N_6
IO_L13P_6/VREF_6
IO_L14N_6
IO_L14P_6
IO_L15N_6
IO_L15P_6
IO_L01N_6/VRP_6
IO_L01P_6/VRN_6
IO_L02N_6
IO_L02P_6
IO_L03N_6/VREF_6
IO_L03P_6
IO_L04N_6
IO_L04P_6
IO_L05N_6
IO_L05P_6
IO_L06N_6
IO_L06P_6
IO_L07N_6
IO_L07P_6
IO_L08N_6
IO_L08P_6
IO_L09N_6/VREF_6
IO_L09P_6
IO_L10N_6
IO_L10P_6
IO_L11N_6
IO_L11P_6
IO_L12N_6
IO_L12P_6
IO_L13N_6
IO_L13P_6/VREF_6
IO_L14N_6
IO_L14P_6
IO_L15N_6
IO_L15P_6
DCI
DCI
I/O
I/O
VREF
I/O
I/O
AJ3
I/O
AJ2
I/O
AJ1
I/O
AH6
AH5
AG6
AG5
AG2
AG1
AF7
AF6
AG4
AF4
AF3
AF2
AF8
AE9
AE8
AE7
AE6
AE5
AE4
AE3
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
DS099 (v3.1) June 27, 2013
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Product Specification
253
Spartan-3 FPGA Family: Pinout Descriptions
Table 110: FG1156 Package Pinout (Cont’d)
XC3S4000
Pin Name
XC3S5000
Pin Name
FG1156
Pin Number
Bank
Type
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
IO_L16N_6
IO_L16N_6
AE2
AE1
AD10
AD9
AD2
AD1
AC11
AC10
AC8
AC7
AC6
AC5
AC2
AC1
AC9
AB10
AB8
AB7
AB4
AB3
AB11
AA11
AA8
AA7
AA6
AA5
AA4
AA3
AA2
AA1
Y11
Y10
Y4
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
IO_L16P_6
IO_L17N_6
IO_L17P_6/VREF_6
IO_L19N_6
IO_L19P_6
IO_L20N_6
IO_L20P_6
IO_L21N_6
IO_L21P_6
IO_L22N_6
IO_L22P_6
IO_L23N_6
IO_L23P_6
IO_L24N_6/VREF_6
IO_L24P_6
IO_L25N_6
IO_L25P_6
IO_L26N_6
IO_L26P_6
IO_L27N_6
IO_L27P_6
IO_L28N_6
IO_L28P_6
IO_L29N_6
IO_L29P_6
IO_L30N_6
IO_L30P_6
IO_L31N_6
IO_L31P_6
IO_L32N_6
IO_L32P_6
IO_L33N_6
IO_L33P_6
IO_L34N_6/VREF_6
IO_L34P_6
IO_L35N_6
IO_L35P_6
IO_L36N_6
IO_L36P_6
IO_L16P_6
IO_L17N_6
IO_L17P_6/VREF_6
IO_L19N_6
IO_L19P_6
IO_L20N_6
IO_L20P_6
IO_L21N_6
IO_L21P_6
IO_L22N_6
IO_L22P_6
IO_L23N_6
IO_L23P_6
IO_L24N_6/VREF_6
IO_L24P_6
IO_L25N_6
IO_L25P_6
IO_L26N_6
IO_L26P_6
IO_L27N_6
IO_L27P_6
IO_L28N_6
IO_L28P_6
IO_L29N_6
IO_L29P_6
IO_L30N_6
IO_L30P_6
IO_L31N_6
IO_L31P_6
IO_L32N_6
IO_L32P_6
IO_L33N_6
IO_L33P_6
IO_L34N_6/VREF_6
IO_L34P_6
IO_L35N_6
IO_L35P_6
IO_L36N_6
IO_L36P_6
Y3
Y2
Y1
Y9
W10
W7
W6
DS099 (v3.1) June 27, 2013
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Product Specification
254
Spartan-3 FPGA Family: Pinout Descriptions
Table 110: FG1156 Package Pinout (Cont’d)
XC3S4000
Pin Name
XC3S5000
Pin Name
FG1156
Pin Number
Bank
Type
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
7
7
7
7
7
IO_L37N_6
IO_L37N_6
W3
W2
I/O
I/O
IO_L37P_6
IO_L38N_6
IO_L38P_6
IO_L39N_6
IO_L39P_6
IO_L40N_6
IO_L40P_6/VREF_6
N.C. ()
N.C. ()
N.C. ()
N.C. ()
IO_L45N_6
IO_L45P_6
N.C. ()
N.C. ()
IO_L48N_6
IO_L48P_6
N.C. ()
N.C. ()
IO_L52N_6
IO_L52P_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
IO
IO_L37P_6
IO_L38N_6
IO_L38P_6
IO_L39N_6
IO_L39P_6
IO_L40N_6
IO_L40P_6/VREF_6
IO_L41N_6
IO_L41P_6
IO_L44N_6
IO_L44P_6
IO_L45N_6
IO_L45P_6
IO_L46N_6
IO_L46P_6
IO_L48N_6
IO_L48P_6
IO_L49N_6
IO_L49P_6
IO_L52N_6
IO_L52P_6
VCCO_6
V6
I/O
V5
I/O
V4
I/O
V3
I/O
V2
I/O
V1
VREF
I/O
AH4
AH3
AD7
AD6
AC4
AC3
AA10
AA9
Y7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Y6
I/O
W11
V11
V8
I/O
I/O
I/O
V7
I/O
AA12
AB12
AB2
AB6
AD4
AD8
AG3
AG7
AL3
W12
W4
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
I/O
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
Y12
Y8
VCCO_6
IO
G1
IO
IO
G2
I/O
IO
IO
U10
U9
I/O
IO
IO
I/O
IO_L01N_7/VRP_7
IO_L01N_7/VRP_7
C1
DCI
DS099 (v3.1) June 27, 2013
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Product Specification
255
Spartan-3 FPGA Family: Pinout Descriptions
Table 110: FG1156 Package Pinout (Cont’d)
XC3S4000
Pin Name
XC3S5000
FG1156
Bank
Type
Pin Name
IO_L01P_7/VRN_7
IO_L02N_7
Pin Number
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
IO_L01P_7/VRN_7
IO_L02N_7
IO_L02P_7
C2
D1
D2
E2
E3
F3
F4
F1
F2
G5
G6
H5
H6
H1
H2
J6
DCI
I/O
IO_L02P_7
I/O
IO_L03N_7/VREF_7
IO_L03P_7
IO_L03N_7/VREF_7
IO_L03P_7
VREF
I/O
IO_L04N_7
IO_L04P_7
IO_L04N_7
I/O
IO_L04P_7
I/O
IO_L05N_7
IO_L05P_7
IO_L05N_7
I/O
IO_L05P_7
I/O
IO_L06N_7
IO_L06P_7
IO_L06N_7
I/O
IO_L06P_7
I/O
IO_L07N_7
IO_L07P_7
IO_L07N_7
I/O
IO_L07P_7
I/O
IO_L08N_7
IO_L08P_7
IO_L08N_7
I/O
IO_L08P_7
I/O
IO_L09N_7
IO_L09P_7
IO_L09N_7
I/O
IO_L09P_7
J7
I/O
IO_L10N_7
IO_L10P_7/VREF_7
IO_L11N_7
IO_L11P_7
IO_L10N_7
J4
I/O
IO_L10P_7/VREF_7
IO_L11N_7
H4
J2
VREF
I/O
IO_L11P_7
J3
I/O
IO_L12N_7
IO_L12P_7
IO_L12N_7
K9
J8
I/O
IO_L12P_7
I/O
IO_L13N_7
IO_L13P_7
IO_L13N_7
K7
K8
K5
K6
K3
K4
K1
K2
L9
I/O
IO_L13P_7
I/O
IO_L14N_7
IO_L14P_7
IO_L14N_7
I/O
IO_L14P_7
I/O
IO_L15N_7
IO_L15P_7
IO_L15N_7
I/O
IO_L15P_7
I/O
IO_L16N_7
IO_L16P_7/VREF_7
IO_L17N_7
IO_L17P_7
IO_L16N_7
I/O
IO_L16P_7/VREF_7
IO_L17N_7
VREF
I/O
IO_L17P_7
L10
L1
I/O
IO_L19N_7/VREF_7
IO_L19P_7
IO_L19N_7/VREF_7
IO_L19P_7
VREF
I/O
L2
IO_L20N_7
IO_L20P_7
IO_L20N_7
M10
M11
M7
M8
M5
I/O
IO_L20P_7
I/O
IO_L21N_7
IO_L21P_7
IO_L21N_7
I/O
IO_L21P_7
I/O
IO_L22N_7
IO_L22N_7
I/O
DS099 (v3.1) June 27, 2013
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Product Specification
256
Spartan-3 FPGA Family: Pinout Descriptions
Table 110: FG1156 Package Pinout (Cont’d)
XC3S4000
Pin Name
XC3S5000
Pin Name
FG1156
Pin Number
Bank
Type
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
IO_L22P_7
IO_L22P_7
M6
M3
M4
N10
M9
N3
N4
P11
N11
P7
P8
P5
P6
P3
P4
R6
R7
R3
R4
R1
R2
T10
R9
T6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
IO_L23N_7
IO_L23P_7
IO_L24N_7
IO_L24P_7
IO_L25N_7
IO_L25P_7
IO_L26N_7
IO_L26P_7
IO_L27N_7
IO_L27P_7/VREF_7
IO_L28N_7
IO_L28P_7
IO_L29N_7
IO_L29P_7
IO_L30N_7
IO_L30P_7
IO_L31N_7
IO_L31P_7
IO_L32N_7
IO_L32P_7
IO_L33N_7
IO_L33P_7
IO_L34N_7
IO_L34P_7
IO_L35N_7
IO_L35P_7
IO_L37N_7
IO_L37P_7/VREF_7
IO_L38N_7
IO_L38P_7
IO_L39N_7
IO_L39P_7
IO_L40N_7/VREF_7
IO_L40P_7
N.C. ()
IO_L23N_7
IO_L23P_7
IO_L24N_7
IO_L24P_7
IO_L25N_7
IO_L25P_7
IO_L26N_7
IO_L26P_7
IO_L27N_7
IO_L27P_7/VREF_7
IO_L28N_7
IO_L28P_7
IO_L29N_7
IO_L29P_7
IO_L30N_7
IO_L30P_7
IO_L31N_7
IO_L31P_7
IO_L32N_7
IO_L32P_7
IO_L33N_7
IO_L33P_7
IO_L34N_7
IO_L34P_7
IO_L35N_7
IO_L35P_7
IO_L37N_7
IO_L37P_7/VREF_7
IO_L38N_7
IO_L38P_7
IO_L39N_7
IO_L39P_7
IO_L40N_7/VREF_7
IO_L40P_7
IO_L41N_7
IO_L41P_7
IO_L44N_7
IO_L44P_7
IO_L45N_7
T7
T2
T3
U7
U8
U5
U6
U3
U4
U1
U2
G3
G4
L6
N.C. ()
N.C. ()
N.C. ()
L7
IO_L45N_7
M1
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
257
Spartan-3 FPGA Family: Pinout Descriptions
Table 110: FG1156 Package Pinout (Cont’d)
XC3S4000
Pin Name
XC3S5000
Pin Name
FG1156
Pin Number
Bank
Type
7
7
IO_L45P_7
IO_L45P_7
M2
N7
I/O
I/O
IO_L46N_7
IO_L46P_7
N.C. ()
N.C. ()
IO_L49N_7
IO_L49P_7
IO_L50N_7
IO_L50P_7
N.C. ()
N.C. ()
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
GND
IO_L46N_7
IO_L46P_7
IO_L47N_7
IO_L47P_7
IO_L49N_7
IO_L49P_7
IO_L50N_7
IO_L50P_7
IO_L51N_7
IO_L51P_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
GND
7
N8
I/O
7
P9
I/O
7
P10
P1
I/O
7
I/O
7
P2
I/O
7
R10
R11
U11
T11
D3
I/O
7
I/O
7
I/O
7
I/O
7
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
7
H3
7
H7
7
L4
7
L8
7
N12
N2
7
7
N6
7
P12
R12
R8
7
7
7
T12
T4
7
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
A1
GND
GND
A13
A16
A19
A2
GND
GND
GND
GND
GND
GND
GND
GND
A22
A26
A30
A33
A34
A5
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A9
GND
GND
AA14
AA15
AA16
AA17
GND
GND
GND
GND
GND
GND
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
258
Spartan-3 FPGA Family: Pinout Descriptions
Table 110: FG1156 Package Pinout (Cont’d)
XC3S4000
Pin Name
XC3S5000
Pin Name
FG1156
Pin Number
Bank
Type
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AA18
AA19
AA20
AA21
AB1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AB17
AB18
AB26
AB30
AB34
AB5
AB9
AD3
AD32
AE10
AE25
AF1
AF13
AF16
AF19
AF22
AF30
AF34
AF5
AH28
AH7
AK1
AK13
AK16
AK19
AK22
AK26
AK30
AK34
AK5
AK9
AM11
AM24
AM3
AM32
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
259
Spartan-3 FPGA Family: Pinout Descriptions
Table 110: FG1156 Package Pinout (Cont’d)
XC3S4000
Pin Name
XC3S5000
Pin Name
FG1156
Pin Number
Bank
Type
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AN1
AN2
AN33
AN34
AP1
AP13
AP16
AP19
AP2
AP22
AP26
AP30
AP33
AP34
AP5
AP9
B1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
B2
B33
B34
C11
C24
C3
C32
E1
E13
E16
E19
E22
E26
E30
E34
E5
E9
G28
G7
J1
J13
J16
J19
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
260
Spartan-3 FPGA Family: Pinout Descriptions
Table 110: FG1156 Package Pinout (Cont’d)
XC3S4000
Pin Name
XC3S5000
Pin Name
FG1156
Pin Number
Bank
Type
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
J22
J30
J34
J5
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
K10
K25
L3
L32
N1
N17
N18
N26
N30
N34
N5
N9
P14
P15
P16
P17
P18
P19
P20
P21
R14
R15
R16
R17
R18
R19
R20
R21
T1
T14
T15
T16
T17
T18
T19
T20
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
261
Spartan-3 FPGA Family: Pinout Descriptions
Table 110: FG1156 Package Pinout (Cont’d)
XC3S4000
Pin Name
XC3S5000
Pin Name
FG1156
Pin Number
Bank
Type
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
T21
T26
T30
T34
T5
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
T9
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
W1
W14
W15
W16
W17
W18
W19
W20
W21
W26
W30
W34
W5
W9
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
262
Spartan-3 FPGA Family: Pinout Descriptions
Table 110: FG1156 Package Pinout (Cont’d)
XC3S4000
Pin Name
XC3S5000
Pin Name
FG1156
Pin Number
Bank
Type
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
AK31
AD30
AD5
AG16
AG19
AJ30
AJ5
AK11
AK15
AK20
AK24
AK29
AK6
E11
E15
E20
E24
E29
E6
GND
GND
GND
GND
GND
GND
GND
GND
N.C. ()
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
N.C. ()
N.C.
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
F30
F5
H16
H19
L30
L5
R30
R5
T27
T8
W27
W8
Y30
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
263
Spartan-3 FPGA Family: Pinout Descriptions
Table 110: FG1156 Package Pinout (Cont’d)
XC3S4000
Pin Name
XC3S5000
Pin Name
FG1156
Pin Number
Bank
Type
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
VCCAUX
VCCAUX
Y5
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
AA13
AA22
AB13
AB14
AB15
AB16
AB19
AB20
AB21
AB22
AC12
AC17
AC18
AC23
M12
M17
M18
M23
N13
N14
N15
N16
N19
N20
N21
N22
P13
P22
R13
R22
T13
T22
U12
U23
V12
V23
W13
W22
Y13
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
264
Spartan-3 FPGA Family: Pinout Descriptions
Table 110: FG1156 Package Pinout (Cont’d)
XC3S4000
Pin Name
XC3S5000
Pin Name
FG1156
Pin Number
Bank
Type
N/A
VCCINT
VCCINT
Y22
AL31
AD24
L11
VCCINT
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
JTAG
VCCAUX CCLK
VCCAUX DONE
CCLK
DONE
HSWAP_EN
M0
VCCAUX HSWAP_EN
VCCAUX M0
AL4
AK4
AG8
D4
VCCAUX M1
M1
VCCAUX M2
M2
VCCAUX PROG_B
VCCAUX TCK
VCCAUX TDI
PROG_B
TCK
D31
E4
TDI
JTAG
VCCAUX TDO
VCCAUX TMS
TDO
E31
H27
JTAG
TMS
JTAG
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
265
Spartan-3 FPGA Family: Pinout Descriptions
User I/Os by Bank
Note: The FG(G)1156 package is discontinued. See
http://www.xilinx.com/support/documentation/spartan-3_customer_notices.htm.
Table 111 indicates how the available user-I/O pins are distributed between the eight I/O banks for the XC3S4000 in the
FG1156 package. Similarly, Table 112 shows how the available user-I/O pins are distributed between the eight I/O banks for
the XC3S5000 in the FG1156 package.
Table 111: User I/Os Per Bank for XC3S4000 in FG1156 Package
All Possible I/O Pins by Type
I/O
Package Edge
Top
Maximum I/O
Bank
I/O
79
79
80
79
73
73
79
79
DUAL
DCI
VREF
GCLK
0
1
2
3
4
5
6
7
90
90
88
88
90
90
88
88
0
0
0
0
6
6
0
0
2
7
7
6
7
7
7
7
7
2
2
0
0
2
2
0
0
2
2
Right
2
2
Bottom
Left
2
2
2
Notes:
1. The FG1156 and FGG1156 packages are discontinued. See www.xilinx.com/support/documentation/spartan-3.htm#19600.
Table 112: User I/Os Per Bank for XC3S5000 in FG1156 Package
All Possible I/O Pins by Type
I/O
Package Edge
Top
Maximum I/O
Bank
I/O
89
89
87
87
83
83
87
87
DUAL
DCI
VREF
GCLK
0
1
2
3
4
5
6
7
100
100
96
0
0
0
0
6
6
0
0
2
7
7
7
7
7
7
7
7
2
2
0
0
2
2
0
0
2
2
Right
96
2
100
100
96
2
Bottom
Left
2
2
96
2
Notes:
1. The FG1156 and FGG1156 packages are discontinued. See www.xilinx.com/support/documentation/spartan-3.htm#19600.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
266
Spartan-3 FPGA Family: Pinout Descriptions
FG1156 Footprint
Top Left Corner of FG1156
Package (Top View)
XC3S4000
(712 max. user I/O)
I/O: Unrestricted,
general-purpose user I/O
VREF: User I/O or input voltage
N.C.: Unconnected pins for
XC3S4000 ()
621
55
56
73
1
reference for bank
XC3S5000
(784 max. user I/O)
I/O: Unrestricted,
general-purpose user I/O
VREF: User I/O or input voltage
reference for bank
N.C.: Unconnected pins for
XC3S5000 ()
692
X-Ref Target - Figure 57
Bank 0
1
2
3
I/O
L01P_0
VRN_0
4
5
6
I/O
L05P_0
VREF_0
7
8
9
10
11
12
13
14
15
I/O
L26P_0
VREF_0
16
17
I/O
L32P_0
GCLK6
I/O
I/O
I/O
L02P_0
I/O
L36P_0
I/O
L38P_0
I/O
L15P_0
I/O
L22P_0
L34P_0
L40P_0
GND
GND
GND
GND
GND
GND
A
B
C
D
E
F
I/O
L34N_0
I/O
L40N_0
I/O
L01N_0
VRP_0
I/O
L32N_0
GCLK7
I/O
L02N_0
I/O
L03P_0
I/O
L05N_0
I/O
L36N_0
I/O
L38N_0
I/O
L15N_0
I/O
L22N_0
I/O
L26N_0
I/O
L28P_0
GND
GND
VCCO_0
I/O
I/O
L33P_0
I/O
L01N_7
VRP_7
I/O
L01P_7
VRN_7
I/O
L31P_0
VREF_0
I/O
L03N_0
I/O
L04P_0
I/O
L08P_0
I/O
L37P_0
I/O
L14P_0
I/O
L17P_0
I/O
L21P_0
I/O
L25P_0
I/O
L28N_0
VCCO_0
VCCO_0
GND
GND
I/O
L33N_0
IO
VREF_0
I/O
L02N_7
I/O
L02P_7
I/O
L04N_0
I/O
L35P_0
I/O
L08N_0
I/O
L37N_0
I/O
L14N_0
I/O
L17N_0
I/O
L21N_0
I/O
L25N_0
I/O
L31N_0
VCCO_7 PROG_B
VCCO_0
VCCAUX
VCCO_0
GND
I/O
L03N_7
VREF_7
IO
VREF_0
I/O
TDI
I/O
L06P_0
I/O
L35N_0
I/O
L13P_0
I/O
L20P_0
GND
GND
VCCAUX
I/O
GND
VCCAUX
I/O
GND
L03P_7
I/O
L39P_0
I/O
L05N_7
I/O
L05P_7
I/O
L04N_7
I/O
L04P_7
I/O
L06N_0
I/O
L07P_0
I/O
L10P_0
I/O
L13N_0
I/O
L20N_0
I/O
L24P_0
I/O
L27P_0
I/O
L30P_0
VCCAUX
VCCO_0
I/O
VCCO_0
I/O
I/O
L41N_7
I/O
L41P_7
I/O
L39N_0
I/O
L06N_7
I/O
L06P_7
I/O
L07N_0
I/O
L10N_0
I/O
L16P_0
I/O
L19P_0
I/O
L24N_0
I/O
L27N_0
I/O
L30N_0
I/O
I/O
GND
I/O
G
H
J
I/O
L10P_7
VREF_7
I/O
L08N_7
I/O
L08P_7
I/O
L07N_7
I/O
L07P_7
I/O
L09P_0
I/O
L12P_0
I/O
L16N_0
I/O
L19N_0
I/O
L29P_0
VCCO_7
VCCO_7
VCCO_0
VCCO_0 VCCAUX
I/O
I/O
IO
VREF_0
I/O
L11N_7
I/O
L11P_7
I/O
L10N_7
I/O
L09N_7
I/O
L09P_7
I/O
L12P_7
I/O
L09N_0
I/O
L12N_0
I/O
L23P_0
I/O
L29N_0
GND
GND
I/O
GND
I/O
GND
I/O
L16P_7
VREF_7
I/O
I/O
L16N_7
I/O
L15N_7
I/O
L15P_7
I/O
L14N_7
I/O
L14P_7
I/O
L13N_7
I/O
L13P_7
I/O
L12N_7
I/O
L11P_0
I/O
L18P_0
I/O
I/O
GND
I/O
I/O
K
L
L23N_0
I/O
L44N_7
I/O
L44P_7
I/O
L19N_7
VREF_7
HSWAP_
EN
IO
I/O
I/O
L19P_7
I/O
L17N_7
I/O
L17P_7
I/O
L11N_0
I/O
L18N_0
GND
VCCO_7 VCCAUX
VCCO_7
I/O
VREF_0
I/O
L45N_7
I/O
L45P_7
I/O
L23N_7
I/O
L23P_7
I/O
L22N_7
I/O
L22P_7
I/O
L21N_7
I/O
L21P_7
I/O
L24P_7
I/O
L20N_7
I/O
L20P_7
VCCO_0 VCCO_0 VCCO_0 VCCO_0
VCCINT VCCINT VCCINT VCCINT
VCCINT
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCINT
VCCINT
GND
GND
GND
M
N
P
R
T
I/O
L25N_7
I/O
L25P_7
I/O
L46N_7
I/O
L46P_7
I/O
L24N_7
I/O
L26P_7
VCCO_7
GND
VCCO_7
GND
GND
I/O
L47N_7
I/O
L47P_7
I/O
L27P_7
VREF_7
I/O
L49N_7
I/O
L49P_7
I/O
L29N_7
I/O
L29P_7
I/O
L28N_7
I/O
L28P_7
I/O
L27N_7
I/O
L26N_7
GND
GND
GND
GND
GND
GND
VCCINT
VCCINT
VCCINT
GND
I/O
L32N_7
I/O
L32P_7
I/O
L31N_7
I/O
L31P_7
I/O
L30N_7
I/O
L30P_7
I/O
L33P_7
I/O
L50N_7
I/O
L50P_7
VCCAUX
GND
VCCO_7
VCCAUX
I/O
L51P_7
I/O
L35N_7
I/O
L35P_7
I/O
L34N_7
I/O
L34P_7
I/O
L33N_7
VCCO_7
GND
I/O
GND
GND
GND
GND
GND
GND
GND
GND
GND
I/O
L51N_7
I/O
L40N_7
VREF_7
I/O
L37P_7
VREF_7
I/O
L40P_7
I/O
L39N_7
I/O
L39P_7
I/O
L38N_7
I/O
L38P_7
I/O
L37N_7
U
I/O
DS099-4_14a_072903
Figure 57: FG1156 Package Footprint (Top View)
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
267
Spartan-3 FPGA Family: Pinout Descriptions
Top Right Corner of FG1156 Package
(Top View)
All Devices
DUAL: Configuration pin, then
DCI: User I/O or reference
GCLK: User I/O or global clock
12
7
16
4
8
possible user I/O
resistor input for bank
buffer input
CONFIG: Dedicated
configuration pins
VCCO: Output voltage supply
for bank
JTAG: Dedicated JTAG port pins 104
VCCAUX: Auxiliary voltage
VCCINT: Internal core voltage
supply (+1.2V)
40
32
184 GND: Ground
supply (+2.5V)
Bank 1
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
I/O
L01N_1
VRP_1
33
34
I/O
I/O
L40N_1
I/O
L26N_1
I/O
L19N_1
I/O
L15N_1
I/O
L14N_1
I/O
L08N_1
I/O
L05N_1
I/O
L02N_1
L34N_1
I/O
GND
GND
GND
GND
A
B
C
D
E
F
GND
GND
I/O
L34P_1
I/O
L32N_1
GCLK5
I/O
L01P_1
VRN_1
I/O
L28N_1
I/O
L40P_1
I/O
L26P_1
I/O
L19P_1
I/O
L15P_1
I/O
L14P_1
I/O
L08P_1
I/O
L05P_1
I/O
L03N_1
I/O
L02P_1
VCCO_1
I/O
GND
GND
I/O
L33N_1
I/O
L32P_1
GCLK4
I/O
L10N_1
VREF_1
I/O
L01N_2
VRP_2
I/O
L01P_2
VRN_2
I/O
L28P_1
I/O
L39N_1
I/O
L25N_1
I/O
L22N_1
I/O
L13N_1
I/O
L04N_1
I/O
L03P_1
GND
VCCO_1
VCCO_1
I/O
GND
I/O
L33P_1
I/O
L31N_1
VREF_1
IO
VREF_1
I/O
L39P_1
I/O
L25P_1
I/O
L22P_1
I/O
L18N_1
I/O
L13P_1
I/O
L10P_1
I/O
L07N_1
I/O
L04P_1
I/O
L02N_2
I/O
L02P_2
VCCO_1
GND
VCCO_1
VCCAUX
VCCO_2
TCK
TDO
I/O
L06N_1
VREF_1
I/O
L03N_2
VREF_2
I/O
L31P_1
I/O
L18P_1
I/O
L07P_1
I/O
L03P_2
VCCAUX
VCCAUX
I/O
I/O
GND
I/O
GND
GND
GND
I/O
L36N_1
I/O
L17N_1
VREF_1
I/O
L27N_1
I/O
L38N_1
I/O
L24N_1
I/O
L12N_1
I/O
L09N_1
I/O
L06P_1
I/O
L04N_2
I/O
L04P_2
I/O
L41N_2
I/O
L41P_2
VCCO_1
VCCAUX
I/O
I/O
I/O
L36P_1
I/O
L42N_2
I/O
L42P_2
I/O
L30N_1
I/O
L27P_1
I/O
L38P_1
I/O
L24P_1
I/O
L21N_1
I/O
L17P_1
I/O
L12P_1
I/O
L09P_1
I/O
L05N_2
I/O
L05P_2
I/O
I/O
VCCO_1
TMS
GND
G
H
J
I/O
L09N_2
VREF_2
I/O
L30P_1
I/O
L23N_1
I/O
L21P_1
I/O
L11N_1
I/O
L06N_2
I/O
L06P_2
I/O
L07N_2
I/O
L07P_2
VCCAUX VCCO_1
VCCO_1
VCCO_2
VCCO_2
I/O
I/O
I/O
L35N_1
I/O
I/O
L29N_1
I/O
L37N_1
I/O
L23P_1
I/O
L16N_1
I/O
L11P_1
I/O
L11N_2
I/O
L08N_2
I/O
L08P_2
I/O
L09P_2
I/O
L10N_2
I/O
L10P_2
GND
GND
GND
GND
I/O
L35P_1
I/O
L13P_2
VREF_2
IO
VREF_1
I/O
L29P_1
I/O
I/O
I/O
L20N_1
I/O
L16P_1
I/O
L11P_2
I/O
L12N_2
I/O
L12P_2
I/O
L13N_2
I/O
L14N_2
I/O
L14P_2
I/O
L15N_2
I/O
L15P_2
GND
K
L
L37P_1
I/O
I/O
L17N_2
I/O
L17P_2
VREF_2
IO
VREF_1
I/O
L20P_1
I/O
L16N_2
I/O
L16P_2
I/O
L45N_2
I/O
L45P_2
GND
VCCO_2
VCCAUX VCCO_2
I/O
I/O
I/O
I/O
I/O
L46N_2
I/O
L46P_2
I/O
L21N_2
I/O
L47N_2
I/O
L47P_2
I/O
L19N_2
I/O
L19P_2
I/O
L20N_2
I/O
L20P_2
I/O
L48N_2
I/O
L48P_2
VCCO_1 VCCO_1 VCCO_1 VCCO_1
VCCINT VCCINT VCCINT VCCINT
VCCINT
VCCINT
GND
VCCINT
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCINT
M
N
P
R
T
I/O
L23N_2
VREF_2
I/O
L24N_2
I/O
L21P_2
I/O
L22N_2
I/O
L22P_2
I/O
L23P_2
GND
VCCO_2
VCCO_2
GND
GND
I/O
L49N_2
I/O
L49P_2
I/O
L24P_2
I/O
L50N_2
I/O
L50P_2
I/O
L26N_2
I/O
L26P_2
I/O
L27N_2
I/O
L27P_2
I/O
L28N_2
I/O
L28P_2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
I/O
L29N_2
I/O
L29P_2
I/O
L33N_2
I/O
L30N_2
I/O
L30P_2
I/O
L31N_2
I/O
L31P_2
I/O
L32N_2
I/O
L32P_2
VCCO_2
VCCAUX
VCCAUX
GND
VCCINT
VCCINT
GND
I/O
L51N_2
I/O
L34N_2
VREF_2
I/O
L33P_2
I/O
L34P_2
I/O
L35N_2
I/O
L35P_2
VCCO_2
GND
I/O
GND
I/O
L51P_2
I/O
L40P_2
VREF_2
I/O
L37N_2
I/O
L37P_2
I/O
L38N_2
I/O
L38P_2
I/O
L39N_2
I/O
L39P_2
I/O
L40N_2
I/O
U
DS099-4_14b_072903
Figure 58: FG1156 Package Footprint (Top View) Continued
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
268
Spartan-3 FPGA Family: Pinout Descriptions
1
I/O
L40P_6
VREF_6
2
3
4
5
6
7
8
9
10
11
I/O
L49P_6
12
13
14
15
16
17
I/O
L40N_6
I/O
L39P_6
I/O
L39N_6
I/O
L38P_6
I/O
L38N_6
I/O
L52P_6
I/O
L52N_6
VCCINT
V
W
Y
I/O
I/O
GND
GND
GND
GND
GND
I/O
L49N_6
I/O
L37P_6
I/O
L37N_6
I/O
L36P_6
I/O
L36N_6
I/O
L35P_6
GND
VCCO_6
GND
VCCAUX
VCCO_6
GND
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCINT
VCCINT
VCCINT
VCCINT
GND
GND
GND
GND
I/O
L34N_6
VREF_6
I/O
L34P_6
I/O
L33P_6
I/O
L33N_6
I/O
L48P_6
I/O
L48N_6
I/O
L35N_6
I/O
L32P_6
I/O
L32N_6
VCCAUX
GND
GND
GND
GND
GND
GND
GND
GND
GND
I/O
L46P_6
I/O
L46N_6
A
A
I/O
L31P_6
I/O
L31N_6
I/O
L30P_6
I/O
L30N_6
I/O
L29P_6
I/O
L29N_6
I/O
L28P_6
I/O
L28N_6
I/O
L27P_6
A
B
I/O
L26P_6
I/O
L26N_6
I/O
L25P_6
I/O
L25N_6
I/O
L24P_6
I/O
L27N_6
VCCO_6
VCCO_6
GND
GND
GND
VCCINT VCCINT VCCINT VCCINT
I/O
L24N_6
VREF_6
A
C
I/O
L23P_6
I/O
L23N_6
I/O
L45P_6
I/O
L45N_6
I/O
L22P_6
I/O
L22N_6
I/O
L21P_6
I/O
L21N_6
I/O
L20P_6
I/O
L20N_6
VCCO_5 VCCO_5 VCCO_5 VCCO_5
VCCINT
I/O
I/O
L44P_6
I/O
L44N_6
I/O
L17P_6
VREF_6
I/O
A
D
I/O
L19P_6
I/O
L19N_6
I/O
L17N_6
I/O
L16P_5
VCCO_6 VCCAUX
VCCO_6
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
L39P_5
I/O
L13P_6
VREF_6
I/O
L29P_5
VREF_5
A
E
I/O
L16P_6
I/O
L16N_6
I/O
L15P_6
I/O
L15N_6
I/O
L14P_6
I/O
L14N_6
I/O
L13N_6
I/O
L12P_6
I/O
L12P_5
I/O
L16N_5
I/O
L23P_5
GND
I/O
L39N_5
I/O
L09N_6
VREF_6
I/O
L19P_5
VREF_5
I/O
A
F
I/O
L11P_6
I/O
L11N_6
I/O
L10P_6
I/O
L09P_6
I/O
L12N_6
I/O
L07P_5
I/O
L12N_5
I/O
L23N_5
I/O
L29N_5
GND
GND
GND
GND
A
G
I/O
L08P_6
I/O
L08N_6
I/O
L10N_6
I/O
L07P_6
I/O
L07N_6
I/O
L07N_5
I/O
L17P_5
I/O
L19N_5
I/O
L30P_5
VCCO_6
VCCO_6
GND
VCCO_5
VCCO_5 VCCAUX
M2
I/O
I/O
I/O
L41P_6
I/O
L41N_6
I/O
L40P_5
A
H
I/O
L06P_6
I/O
L06N_6
I/O
L37P_5
I/O
L08P_5
I/O
L13P_5
I/O
L17N_5
I/O
L20P_5
I/O
I/O
I/O
L30N_5
I/O
I/O
VCCO_5
L24P_5
L27P_5
I/O
L40N_5
I/O
L27N_5
VREF_5
A
J
IO
VREF_5
I/O
L05P_6
I/O
L05N_6
I/O
L04P_6
I/O
L04N_6
I/O
L06P_5
I/O
L37N_5
I/O
L08N_5
I/O
L13N_5
I/O
L20N_5
I/O
L24N_5
VCCAUX
GND
VCCO_5
GND
I/O
I/O
I/O
L03N_6
VREF_6
I/O
L31P_5
D5
A
K
I/O
L03P_6
I/O
L06N_5
I/O
L35P_5
I/O
L14P_5
VCCAUX
VCCAUX
VCCO_5
GND
VCCAUX
M1
M0
I/O
I/O
GND
GND
GND
I/O
L33P_5
I/O
L31N_5
D4
A
L
IO
VREF_5
I/O
L02P_6
I/O
L02N_6
I/O
L04P_5
I/O
L35N_5
I/O
L38P_5
I/O
L09P_5
I/O
L14N_5
I/O
L18P_5
I/O
L21P_5
I/O
L25P_5
VCCO_6
GND
VCCO_5
I/O
L33N_5
I/O
L01P_6
VRN_6
I/O
L01N_6
VRP_6
I/O
L28P_5
D7
I/O
L32P_5
GCLK2
A
M
I/O
L03P_5
I/O
L04N_5
I/O
L38N_5
I/O
L09N_5
I/O
L18N_5
I/O
L21N_5
I/O
L25N_5
VCCO_5
VCCO_5
I/O
I/O
L34P_5
I/O
L01P_5
CS_B
I/O
L10P_5
VRN_5
I/O
L28N_5
D6
I/O
L32N_5
GCLK3
A
N
I/O
L02P_5
I/O
L03N_5
I/O
L05P_5
I/O
L36P_5
I/O
L11P_5
I/O
L15P_5
I/O
L22P_5
I/O
L26P_5
VCCO_5
GND
I/O
GND
GND
GND
GND
I/O
L34N_5
I/O
L01N_5
RDWR_B
I/O
L10N_5
VRP_5
I/O
L11N_5
VREF_5
A
P
IO
VREF_5
I/O
L02N_5
I/O
L05N_5
I/O
L36N_5
I/O
L15N_5
I/O
L22N_5
I/O
L26N_5
GND
GND
GND
Bank 5
DS099-4_14c_072503
Bottom Left Corner of
FG1156 Package
(Top View)
Figure 59: FG1156 Package Footprint (Top View) Continued
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
269
Spartan-3 FPGA Family: Pinout Descriptions
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
I/O
L40N_3
VREF_3
I/O
I/O
L37P_3
I/O
L37N_3
I/O
L38P_3
I/O
L38N_3
I/O
L39P_3
I/O
L39N_3
I/O
L40P_3
L51N_3
I/O
I/O
GND
GND
GND
GND
GND
VCCINT
V
W
Y
I/O
L51P_3
I/O
L34P_3
VREF_3
I/O
L33N_3
I/O
L34N_3
I/O
L35P_3
I/O
L35N_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCINT
VCCAUX
VCCO_3
VCCO_3
GND
GND
GND
GND
VCCINT
I/O
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCCINT
VCCINT
VCCINT
GND
GND
GND
I/O
L50P_3
I/O
L50N_3
I/O
L33P_3
I/O
L30P_3
I/O
L30N_3
I/O
L31P_3
I/O
L31N_3
I/O
L32P_3
I/O
L32N_3
VCCAUX
I/O
L49P_3
I/O
L49N_3
A
A
I/O
L48N_3
I/O
L26P_3
I/O
L26N_3
I/O
L27P_3
I/O
L27N_3
I/O
L28P_3
I/O
L28N_3
I/O
L29P_3
I/O
L29N_3
A
B
I/O
L48P_3
I/O
L24N_3
I/O
L46P_3
I/O
L46N_3
I/O
L47P_3
I/O
L47N_3
VCCO_3
VCCO_3
VCCINT VCCINT VCCINT VCCINT
GND
GND
GND
I/O
L23P_3
VREF_3
A
C
I/O
L20P_3
I/O
L20N_3
I/O
L24P_3
I/O
L21P_3
I/O
L21N_3
I/O
L22P_3
I/O
L22N_3
I/O
L23N_3
I/O
L45P_3
I/O
L45N_3
VCCO_4 VCCO_4 VCCO_4 VCCO_4
I/O
L44P_3
I/O
L44N_3
I/O
L17P_3
VREF_3
A
D
I/O
L18N_4
I/O
L11N_4
I/O
L17N_3
I/O
L19P_3
I/O
L19N_3
VCCO_3
VCCAUX VCCO_3
GND
I/O
I/O
I/O
I/O
I/O
DONE
I/O
L13N_3
VREF_3
I/O
A
E
I/O
L23N_4
I/O
L18P_4
I/O
L11P_4
I/O
L12N_3
I/O
L13P_3
I/O
L14P_3
I/O
L14N_3
I/O
L15P_3
I/O
L15N_3
I/O
L16P_3
I/O
L16N_3
GND
I/O
I/O
L09P_3
VREF_3
I/O
A
F
IO
VREF_4
I/O
L29N_4
I/O
L23P_4
I/O
L12N_4
I/O
L07N_4
I/O
L12P_3
I/O
L09N_3
I/O
L10N_3
I/O
L11P_3
I/O
L11N_3
I/O
GND
GND
GND
GND
A
G
I/O
L29P_4
I/O
L19N_4
I/O
L16N_4
I/O
L12P_4
I/O
L07P_4
I/O
L07P_3
I/O
L07N_3
I/O
L10P_3
I/O
L08P_3
I/O
L08N_3
VCCAUX VCCO_4
I/O
VCCO_4
VCCO_3
GND
VCCO_3
I/O
I/O
VCCO_4
I/O
I/O
L39N_4
I/O
L41P_3
I/O
L41N_3
I/O
L30N_4
D2
A
H
IO
VREF_4
I/O
L24N_4
I/O
L19P_4
I/O
L16P_4
I/O
L08N_4
I/O
L05N_4
I/O
L06P_3
I/O
L06N_3
L27N_4
DIN
I/O
I/O
D0
I/O
L39P_4
I/O
L30P_4
D3
I/O
L27P_4
D1
A
J
I/O
L24P_4
I/O
L20N_4
I/O
L13N_4
I/O
L08P_4
I/O
L05P_4
I/O
L35N_4
I/O
L04P_3
I/O
L04N_3
I/O
L05P_3
I/O
L05N_3
VCCO_4
GND
VCCAUX
GND
I/O
N.C.
A
K
IO
VREF_4
I/O
L20P_4
I/O
L13P_4
I/O
L38N_4
I/O
L35P_4
I/O
L03P_3
I/O
L03N_3
VCCAUX
VCCAUX
VCCAUX
I/O
GND
GND
GND
I/O
L36N_4
I/O
L31N_4
INIT_B
I/O
L06N_4
VREF_4
I/O
L02N_3
VREF_3
A
L
IO
VREF_4
I/O
L25N_4
I/O
L21N_4
I/O
L17N_4
I/O
L14N_4
I/O
L09N_4
I/O
L38P_4
I/O
L33N_4
I/O
L02P_3
VCCO_4
VCCO_4
GND
VCCO_3
GND
CCLK
I/O
I/O
L36P_4
I/O
L01P_3
VRN_3
I/O
L01N_3
VRP_3
A
M
I/O
L28N_4
I/O
L25P_4
I/O
L21P_4
I/O
L17P_4
I/O
L14P_4
I/O
L09P_4
I/O
L06P_4
I/O
L33P_4
I/O
L03N_4
L31P_4
DOUT
BUSY
VCCO_4
VCCO_4
I/O
L40N_4
I/O
L37N_4
I/O
L32N_4
GCLK1
I/O
L22N_4
VREF_4
I/O
L01N_4
VRP_4
A
N
I/O
L28P_4
I/O
L26N_4
I/O
L15N_4
I/O
L10N_4
I/O
L04N_4
I/O
L34N_4
I/O
L03P_4
I/O
L02N_4
VCCO_4
GND
GND
GND
GND
GND
I/O
I/O
L40P_4
I/O
L37P_4
I/O
L32P_4
GCLK0
I/O
L26P_4
VREF_4
I/O
L01P_4
VRN_4
A
P
I/O
L22P_4
I/O
L15P_4
I/O
L10P_4
I/O
L04P_4
I/O
L34P_4
I/O
L02P_4
GND
GND
GND
Bank 4
DS099-4_14d_072903
Bottom Right Corner
of FG1156 Package
(Top View)
Figure 60: FG1156 Package Footprint (Top View) Continued
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
270
Spartan-3 FPGA Family: Pinout Descriptions
Revision History
Date
Version
Description
04/03/2003
04/21/2003
1.0
Initial Xilinx release.
1.1
Added information on the VQ100 package footprint, including a complete pinout table (Table 87) and
footprint diagram (Figure 44). Updated Table 85 with final I/O counts for the VQ100 package. Also added
final differential I/O pair counts for the TQ144 package. Added clarifying comments to HSWAP_EN pin
description on page 119. Updated the footprint diagram for the FG900 package shown in Figure 55a and
Figure 55b. Some thick lines separating I/O banks were incorrect. Made cosmetic changes to Figure 40,
Figure 42, and Figure 43. Updated Xilinx hypertext links. Added XC3S200 and XC3S400 to Pin Name
column in Table 91.
05/12/2003
07/11/2003
1.1.1
1.1.2
AM32 pin was missing GND label in FG1156 package diagram (Figure 53).
Corrected misspellings of GCLK in Table 69 and Table 70. Changed CMOS25 to LVCMOS25 in
Dual-Purpose Pin I/O Standard During Configuration section. Clarified references to Module 2. For
XC3S5000 in FG1156 package, corrected N.C. symbol to a black square in Table 110, key, and package
drawing.
07/29/2003
1.2
Corrected pin names on FG1156 package. Some package balls incorrectly included LVDS pair names.
The affected balls on the FG1156 package include G1, G2, G33, G34, U9, U10, U25, U26, V9, V10, V25,
V26, AH1, AH2, AH33, AH34. The number of LVDS pairs is unaffected. Modified affected balls and
re-sorted rows in Table 110. Updated affected balls in Figure 53. Also updated ASCII and Excel electronic
versions of FG1156 pinout.
08/19/2003
10/09/2003
1.2.1
1.2.2
Removed 100 MHz ConfigRate option in CCLK: Configuration Clock section and in Table 80. Added note
that TDO is a totem-pole output in Table 77.
Some pins had incorrect bank designations and were improperly sorted in Table 93. No pin names or
functions changed. Renamed DCI_IN to DCI and added black diamond to N.C. pins in Table 93. In
Figure 47, removed some extraneous text from pin 106 and corrected spelling of pins 45, 48, and 81.
12/17/2003
1.3
Added FG320 pin tables and pinout diagram (FG320: 320-lead Fine-pitch Ball Grid Array). Made cosmetic
changes to the TQ144 footprint (Figure 46), the PQ208 footprint (Figure 47), the FG676 footprint
(Figure 53), and the FG900 footprint (Figure 55). Clarified wording in Precautions When Using the JTAG
Port in 3.3V Environments section.
02/27/2004
07/13/2004
1.4
1.5
Clarified wording in Using JTAG Port After Configuration section. In Table 81, reduced package height for
FG320 and increased maximum I/O values for the FG676, FG900, and FG1156 packages.
Added information on lead-free (Pb-free) package options to the Package Overview section plus Table 81
and Table 83. Clarified the VRN_# reference resistor requirements for I/O standards that use single
termination as described in the DCI Termination Types section and in Figure 42b. Graduated from
Advance Product Specification to Product Specification.
08/24/2004
01/17/2005
1.5.1
1.6
Removed XC3S2000 references from FG1156: 1156-lead Fine-pitch Ball Grid Array.
Added XC3S50 in CP132 package option. Added XC3S2000 in FG456 package option. Added
XC3S4000 in FG676 package option. Added Selecting the Right Package Option section. Modified or
added Table 81, Table 83, Table 84, Table 85, Table 89, Table 90, Table 100, Table 102, Table 103,
Table 106, Figure 45, and Figure 53.
08/19/2005
04/03/2006
1.7
2.0
Removed term “weak” from the description of pull-up and pull-down resistors. Added IDCODE Register
values. Added signal integrity precautions to CCLK: Configuration Clock and indicated that CCLK should
be treated as an I/O during Master mode in Table 79.
Added Package Thermal Characteristics. Updated Figure 41 to make it a more obvious example. Added
detail about which pins have dedicated pull-up resistors during configuration, regardless of the
HSWAP_EN value to Table 70 and to Pin Behavior During Configuration. Updated Precautions When
Using the JTAG Port in 3.3V Environments.
04/26/2006
05/25/2007
2.1
2.2
Corrected swapped data row in Table 86. The Theta-JA with zero airflow column was swapped with the
Theta-JC column. Made additional notations on CONFIG and JTAG pins that have pull-up resistors during
configuration, regardless of the HSWAP_EN input.
Added link on page 128 to Material Declaration Data Sheets. Corrected units typo in Table 74. Added
Note 1 to Table 103 about VREF for XC3S1500 in FG676.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
271
Spartan-3 FPGA Family: Pinout Descriptions
Date
Version
Description
11/30/2007
2.3
Added XC3S5000 FG(G)676 package. Noted that the FG(G)1156 package is being discontinued.
Updated Table 86 with latest thermal characteristics data.
06/25/2008
12/04/2009
2.4
2.5
Updated formatting and links.
Added link to UG332 in CCLK: Configuration Clock. Noted that the CP132, CPG132, FG1156, and
FGG1156 packages are being discontinued in Table 81, Table 83, Table 84, Table 85, and Table 86.
Updated CP132: 132-Ball Chip-Scale Package to indicate that the CP132 and CPG132 packages are
being discontinued.
10/29/2012
06/27/2013
3.0
3.1
Added Notice of Disclaimer. Per XCN07022, updated the FG1156 and FGG1156 package discussion
throughout document including in Table 81, Table 83, Table 84, Table 85, and Table 86. Per XCN08011,
updated CP132 and CPG132 package discussion throughout document including in Table 81, Table 83,
Table 84, Table 85, and Table 86. This product is not recommended for new designs.
Removed banner. This product IS recommended for new designs.
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED
WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE
SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
CRITICAL APPLICATIONS DISCLAIMER
XILINX PRODUCTS (INCLUDING HARDWARE, SOFTWARE AND/OR IP CORES) ARE NOT DESIGNED OR INTENDED TO BE
FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS IN LIFE-SUPPORT OR
SAFETY DEVICES OR SYSTEMS, CLASS III MEDICAL DEVICES, NUCLEAR FACILITIES, APPLICATIONS RELATED TO THE
DEPLOYMENT OF AIRBAGS, OR ANY OTHER APPLICATIONS THAT COULD LEAD TO DEATH, PERSONAL INJURY OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE (INDIVIDUALLY AND COLLECTIVELY, “CRITICAL APPLICATIONS”). FURTHERMORE,
XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN ANY APPLICATIONS THAT AFFECT CONTROL OF A
VEHICLE OR AIRCRAFT, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF
SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE
OPERATOR. CUSTOMER AGREES, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE XILINX
PRODUCTS, TO THOROUGHLY TEST THE SAME FOR SAFETY PURPOSES. TO THE MAXIMUM EXTENT PERMITTED BY
APPLICABLE LAW, CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN CRITICAL
APPLICATIONS.
AUTOMOTIVE APPLICATIONS DISCLAIMER
XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING
FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A
VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN
THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III)
USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY
USE OF XILINX PRODUCTS IN SUCH APPLICATIONS.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
272
相关型号：
XC3S50-4FTG256I
Field Programmable Gate Array, 192 CLBs, 50000 Gates, PBGA256, LEAD FREE, FTBGA-256
XILINX
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