XC4002A-6VQ100C [XILINX]
Field Programmable Gate Array, 64 CLBs, 1600 Gates, 90.9MHz, 64-Cell, CMOS, PQFP100, PLASTIC, VQFP-100;型号: | XC4002A-6VQ100C |
厂家: | XILINX, INC |
描述: | Field Programmable Gate Array, 64 CLBs, 1600 Gates, 90.9MHz, 64-Cell, CMOS, PQFP100, PLASTIC, VQFP-100 时钟 栅 可编程逻辑 |
文件: | 总15页 (文件大小:99K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
XC4000A
Logic Cell Array Family
Product Specifications
Description
Features
TheXC4000AfamilyofFPGAsoffersfourdevicesatthelow
end of the XC4000 family complexity range. XC4000A
differs from XC4000 in four areas: fewer routing resources,
fewer wide-edge decoders, higher output sink current, and
improved output slew-rate control.
•
Third Generation Field-Programmable Gate Arrays
– Abundant flip-flops
– Flexible function generators
– On-chip ultra-fast RAM
– Dedicated high-speed carry-propagation circuit
– Wide edge decoders (two per edge)
– Hierarchy of interconnect lines
– Internal 3-state bus capability
– Eight global low-skew clock or signal distribution
network
•
The XC4000 routing structure is optimized for smaller
designs, naturally requiring fewer routing resources. The
XC4000A devices have four Longlines and four single-
length lines per row and column, while the XC4000
devices have six Longlines and eight single-length lines
per row and column. This results in a smaller chip area
and lower cost per device.
•
•
•
Flexible Array Architecture
– Programmable logic blocks and I/O blocks
– Programmable interconnects and wide decoders
•
•
•
XC4000A has two wide-edge decoders on every device
edge, while the XC4000 has four. All other wide-decoder
features are identical in XC4000 and XC4000A.
Sub-micron CMOS Process
– High-speed logic and Interconnect
– Low power consumption
XC4000A outputs are specified at 24 mA, sink current,
while XC4000 outputs are specified at 12 mA. The source
current is the same 4 mA for both families.
Systems-Oriented Features
– IEEE 1149.1-compatible boundary-scan logic support
– Programmable output slew rate (4 modes)
– Programmable input pull-up or pull-down resistors
– 24-mA sink current per output (48 per pair)
The XC4000A family offers a more sophisticated output
slew-rate control structure with four configurable options
for each individual output driver: fast, medium fast, me-
dium slow, and slow. Slew-rate control can alleviate
ground-bounce problems when multiple outputs switch
simultaneously, and it can reduce or eliminate crosstalk
and transmission-line effects on printed circuit boards.
•
•
Configured by Loading Binary File
– Unlimited reprogrammability
– Six programming modes
XACT Development System runs on ’386/’486-type PC,
NEC PC, Apollo, Sun-4, and Hewlett-Packard 700 Series
– Interfaces to popular design environments like
Viewlogic, Mentor Graphics and OrCAD
– Fully automatic partitioning, placement and routing
– Interactive design editor for design optimization
– 288 macros, 34 hard macros, RAM/ROM compiler
Note that the XC4003 and XC4005 devices are available in
both flavors, the lower-priced XC4003A/XC4005A with re-
duced routing, and the higher-priced XC4003/XC4005 with
more abundant routing resources. The XC4000A devices
are intended for less demanding and more structured
designs, and the XC4000 devices for more random designs
requiring additional routing resources.
The equivalent devices are pin-compatible and are avail-
able in identical packages, but they are not bitstream
compatible. In order to move from a XC4000A to a XC4000,
or vice versa, the design must be recompiled.
Table 1. The XC4000A Family of Field-Programmable Gate Arrays
Device
Appr. Gate Count
CLB Matrix
Number of CLBs
Number of Flip-Flops
Max Decode Inputs (per side)
Max RAM Bits
XC4002A
XC4003A
XC4004A
XC4005A
2,000
8 x 8
64
256
24
2,048
64
3,000
10 x 10
100
360
30
3,200
80
4,000
12 x 12
144
480
36
4,608
96
5,000
14 x 14
196
616
42
6,272
112
Number of IOBs
2-71
XC4000A Logic Cell Array Family
Absolute Maximum Ratings
Symbol Description
Units
V
VCC Supply voltage relative to GND
VIN Input voltage with respect to GND
–0.5 to +7.0
–0.5 to VCC +0.5
–0.5 to VCC +0.5
–65 to + 150
+ 260
V
VTS Voltage applied to 3-state output
V
TSTG Storage temperature (ambient)
°C
°C
°C
TSOL Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm)
TJ
Junction temperature
+ 150
Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond those
listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions
for extended periods of time may affect device reliability.
Operating Conditions
Symbol
Description
Min
4.75
4.5
4.5
2.0
0
Max Units
VCC
Supply voltage relative to GND Commercial 0°C to 85°C junction
Supply voltage relative to GND Industrial -40°C to 100°C junction
Supply voltage relative to GND Military –55°C to 125°C case
High-level input voltage (XC4000 has TTL-like input thresholds)
Low-level input voltage (XC4000 has TTL-like input thresholds)
Input signal transition time
5.25
5.5
V
V
5.5
V
VIH
VIL
TIN
VCC
0.8
V
V
250
ns
At junction temperatures above those listed as Operating conditions, all delay parameters increase by 0.35% per °C.
DC Characteristics Over Operating Conditions
Symbol
VOH
VOL
ICCO
IIL
Description
Min
Max Units
High-level output voltage @ IOH = –4.0 mA, VCC min
Low-level output voltage @ IOL = 24 mA, VCC min (Note 1)
Quiescent LCA supply current (Note 2)
Leakage current
2.4
V
0.4
V
10 mA
–10
+10
15
µA
CIN
Input capacitance (sample tested)
pF
IRIN
Pad pull-up (when selected) @ VIN = 0V (sample tested)
Horizontal Long Line pull-up (when selected) @ logic Low
0.02
0.2
0.25 mA
2.5 mA
IRLL
Note: 1. With 50% of the outputs simultaneously sinking 24 mA.
2. With no output current loads, no active input or longline pull-up resistors, all package pins at VCC or GND, and
the LCA configured with a MakeBits tie option.
2-72
Wide Decoder Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally
tested. Since many internal timing parameters cannot be measured directly, there derived from benchmark timing patterns. The following
guidelines relflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date
timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade
Symbol
-6
-5
-4
Description
Device
Max
Max
Max
Units
Full length, both pull-ups,
inputs from IOB I-pins
TWAF
XC4002A
XC4003A
XC4004A
XC4005A
8.5
9.0
9.5
7.5
8.0
8.5
9.0
ns
ns
ns
ns
5.0
6.0
10.0
Full length, both pull-ups
inputs from internal logic
TWAFL
TWAO
TWAOL
XC4002A
XC4003A
XC4004A
XC4005A
11.5
12.0
12.5
13.0
10.5
11.0
11.5
12.0
ns
ns
ns
ns
7.0
8.0
Half length, one pull-up
inputs from IOB I-pins
XC4002A
XC4003A
XC4004A
XC4005A
8.5
9.0
9.5
7.5
8.0
8.5
9.0
ns
ns
ns
ns
6.0
7.0
10.0
Half length, one pull-up
inputs from internal logic
XC4002A
XC4003A
XC4004A
XC4005A
11.5
12.0
12.5
13.0
10.5
11.0
11.5
12.0
ns
ns
ns
ns
8.0
9.0
Note: These delays are specified from the decoder input to the decoder output. For pin-to-pin delays, add the input delay (TPID
)
and output delay (one of 4 modes), as listed on page 2-70.
Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally
tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The
following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more
up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade
-6
-5
-4
Description
Symbol
Device
Max
Max
Max Units
Global Signal Distribution
From pad through primary buffer, to any clock k
TPG
XC4002A
XC4003A
XC4004A
XC4005A
7.7
7.8
7.9
8.0
5.7
5.8
5.9
6.0
ns
5.1
5.5
ns
ns
ns
From pad through secondary buffer, to any clock k
TSG
XC4002A
XC4003A
XC4004A
XC4005A
8.7
8.8
8.9
9.0
6.7
6.8
6.9
7.0
ns
ns
ns
ns
6.3
6.7
2-73
XC4000A Logic Cell Array Family
Horizontal Longline Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally
tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The
following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more
up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade
-6
-5
-4
Description
Symbol
Device
Max
Max
Max Units
TBUF driving a Horizontal Longline (L.L.)
I going High or Low to L.L. going High or Low,
while T is Low, i.e. buffer is constantly active
TIO1
TIO2
TON
XC4002A
XC4003A
XC4004A
XC4005A
8.2
8.8
9.4
6.0
6.2
6.6
7.0
ns
4.4
5.5
ns
ns
ns
10.0
I going Low to L.L. going from resistive pull-up
High to active Low, (TBUF configured as open drain)
XC4002A
XC4003A
XC4004A
XC4005A
8.7
9.3
9.9
6.5
6.7
7.1
7.5
ns
ns
ns
ns
5.0
6.0
10.5
T going Low to L.L. going from resistive pull-up
or floating High to active Low, (TUBF configured
as open drain)
XC4002A
XC4003A
XC4004A
XC4005A
10.1
10.7
11.4
12.0
8.4
9.0
9.5
ns
ns
ns
ns
7.2
10.0
8.0
1.8
T going High to TBUF going inactive, not driving L.L.
TOFF
TPUS
All devices
3.0
2.0
ns
T going High to L.L. going from Low to High,
pulled up by a single resistor
XC4002A
XC4003A
XC4004A
XC4005A
23.0
24.0
25.0
26.0
19.0
20.0
21.0
22.0
ns
ns
ns
ns
14.0
16.0
T going High to L.L. going from Low to High,
pulled up by two resistors
TPUF
XC4002A
XC4003A
XC4004A
XC4005A
10.5
11.0
11.5
12.0
8.5
9.0
9.5
ns
ns
ns
ns
7.0
8.0
10.0
2-74
Guaranteed Input and Output Parameters (Pin-to-Pin)
All values listed below are tested directly. and guaranteed over the operating conditions. The same parameters can also be derived
indirectly from the IOB and Global Buffer specifications. The XACT delay calculator uses this indirect method. When there is a discrepancy
between these two methods, the directly tested values listed below should be used, and the derived values should be ignored.
Speed Grade
-6
-5
-4
Description
Symbol
Device
Units
Global Clock to Output (fast)
TICKOF
XC4002A
XC4003A
XC4004A
XC4005A
14.9
15.1
15.3
15.5
12.2
12.5
12.8
13.0
ns
ns
ns
ns
11.6
12.0
(Max)
Global Clock to Output (slew limited)
Input Set-up Time, using IFF (no delay)
Input Hold time, using IFF (no delay)
Input Set-up Time, using IFF (with delay)
Input Hold Time, using IFF (with delay)
TICKO
XC4002A
XC4003A
XC4004A
XC4005A
19.9
20.1
20.3
20.5
15.2
15.5
15.8
16.0
ns
ns
ns
ns
14.6
15.0
(Max)
TPSUF
(Min)
XC4002A
XC4003A
XC4004A
XC4005A
2.6
2.4
2.2
2.0
2.3
2.0
1.7
1.5
ns
ns
ns
ns
1.6
1.2
TPHF
XC4002A
XC4003A
XC4004A
XC4005A
4.9
5.1
5.3
5.5
3.7
4.0
4.3
4.5
ns
ns
ns
ns
4.0
4.5
(Min)
TPSU
XC4002A
XC4003A
XC4004A
XC4005A
21.8
21.5
21.2
21.0
18.8
18.5
18.2
18.0
ns
ns
ns
ns
12.0
12.0
(Min)
TPH
XC4002A
XC4003A
XC4004A
XC4005A
0
0
0
0
0
0
0
0
ns
ns
ns
ns
0
0
(Min)
Timing is measured at pin threshold, with 50 pF external
capacitive loads (incl. test fixture). When testing fast out-
puts, only one output switches. When testing slew-rate
limitedoutputs,halfthenumberofoutputsononesideofthe
device are switching. These parameter values are tested
and guaranteed for worst-case conditions of supply voltage
and temperature, and also with the most unfavorable clock
polarity choice.
Input
Set-Up
&
Hold
Time
IFF
OFF
•
•
•
•
•
T
PG
Global Clock-to-Output Delay
X3192
T
for -4 Speed Grade
T
for -4 Speed Grade
PICKD
PDLI
Pad to I1, I2
via transparent
latch, with delay
Input set-up time
pad to clock (IK)
with delay
XC4003A 17.6 ns
XC4003A 15.6 ns
XC4005A 17.9 ns
XC4005A 15.9 ns
PRELIMINARY
See page 2-76
PRELIMINARY
X6091
2-75
XC4000A Logic Cell Array Family
IOB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally
tested.Sincemanyinternaltimingparameterscannotbemeasureddirectly,theyarederivedfrombenchmarktimingpatterns.Thefollowing
guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date
timing information, use the values provided by the XACT timing calculator and used in the simulator.
XC4003A
XC4005A
-6
-5
-4
Description
Symbol Min Max Min Max Min Max Units
INPUT
Propagation Delays
Pad to I1, I2
TPID
TPLI
TPDLI
TIKRI
TIKLI
4.0
8.0
26.0
8.0
3.0
7.0
24.0
7.0
2.8
6.0
**
6.0
6.0
ns
ns
ns
ns
ns
Pad to I1, I2, via transparent latch (no delay)
Pad to I1, I2, via transparent latch (with delay)
Clock (IK) toI1, I2, (flip-flop)
Clock (IK) to I1, I2 (latch enable, active Low)
8.0
7.0
Set-up Time (Note 3)
Pad to Clock (IK), no delay
Pad to Clock (IK) with delay
TPICK
TPICKD 25.0
7.0
6.0
24 .0
4.0
**
ns
ns
Hold Time (Note 3)
Pad to Clock (IK), no delay
Pad to Clock (IK) with delay
TIKPI
TIKPID
1.0
neg
1.0
neg
1.0
neg
ns
ns
OUTPUT
Propagation Delays
Clock (OK) to Pad (fast)
Output (O) to Pad (fast)
3-state to Pad begin hi-Z (slew-rate independent)
3-state to Pad active and valid (fast)
TOKPOF
TOPF
TTSHZ
TTSONF
7.5
9.0
9.0
7.0
7.0
7.0
6.5
5.5
6.5
9.5
ns
ns
ns
ns
13.0
10.0
Additional Delay
For medium fast outputs
For medium slow outputs
For slow outputs
2.0
4.0
6.0
1.5
3.0
4.5
1.0
2.0
3.0
ns
ns
ns
Set-up and Hold Times
Output (O) to clock (OK) set-up time
Output (O) to clock (OK) hold time
TOOK
TOKO
8.0
0.0
6.0
0.0
5.5
0
ns
ns
Clock
Clock High or Low time
TCH/TCL 5.0
4.0
4.0
ns
Global Set/Reset
Delay from GSR net through Q to I1, I2
Delay from GSR net to Pad
GSR width*
TRRI
TRPO
TMRW
14.5
18.0
13.5
17.0
13.5
14.6
ns
ns
ns
21.0
18.0
18.0
* Timing is based on the XC4005. For other devices see XACT timing calculator.
** See preceding page.
Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture).
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the
internal pull-up or pull-down resistor or alternatively configured as a driven output or be driven from an external source.
3. Input pad setup times and hold times are specified with respect to the internal clock (IK). To calculate system setup time,
subtract clock delay (clock pad to IK) from the specified input pad setup time value, but do not subtract below zero.
Negative hold time means that the delay in the input data is adequate for the external system hold time to be zero,
provided the input clock uses the Global signal distribution from pad to IK.
2-76
CLB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally
tested.Sincemanyinternaltimingparameterscannotbemeasureddirectly,theyarederivedfrombenchmarktimingpatterns.Thefollowing
guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date
timing information, use the values provided by the XACT timing calculator and used in the simulator.
XC4003A
XC4005A
Speed Grade
Symbol
-6
-5
-4
Description
Min Max Min Max Min Max Units
Combinatorial Delays
F/G inputs to X/Y outputs
F/G inputs via H' to X/Y outputs
C inputs via H' to X/Y outputs
TILO
TIHO
THHO
6.0
8.0
7.0
4.5
7.0
5.0
4.0
6.0
4.5
ns
ns
ns
CLB Fast Carry Logic
Operand inputs (F1,F2,G1,G4) to COUT
Add/Subtract input (F3) to COUT
Initialization inputs (F1,F3) to COUT
TOPCY
TASCY
TINCY
TSUM
TBYP
7.0
8.0
6.0
8.0
2.0
5.5
6.0
4.0
6.0
1.5
5.0
5.5
3.5
5.5
1.5
ns
ns
ns
ns
ns
CIN through function generators to X/Y outputs
IN to COUT, bypass function generators.
C
Sequential Delays
Clock K to outputs Q
TCKO
5.0
3.0
3.0
ns
Set-up Time before Clock K
F/G inputs
TICK
6.0
8.0
7.0
4.0
7.0
6.0
8.0
10.0
4.5
6.0
5.0
3.0
4.0
4.5
6.0
7.5
4.5
6.0
5.0
3.0
3.0
4.0
5.5
7.3
ns
ns
ns
ns
ns
ns
ns
ns
F/G inputs via H'
C inputs via H1
C inputs via DIN
C inputs via EC
C inputs via S/R, going Low (inactive)
CIN input via F'/G'
CIN input via F'/G' and H'
TIHCK
THHCK
TDICK
TECCK
TRCK
Hold Time after Clock K
F/G inputs
TCKI
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
F/G inputs via H'
C inputs via H1
C inputs via DIN
C inputs via EC
TCKIH
TCKHH
TCKDI
TCKEC
TCKR
C inputs via S/R, going Low (inactive)
Clock
Clock High time
Clock Low time
TCH
TCL
5.0
5.0
4.0
4.0
4.0
4.0
ns
ns
Set/Reset Direct
Width (High)
Delay from C inputs via S/R, going High to Q
TRPW
TRIO
5.0
4.0
4.0
ns
ns
9.0
8.0
7.0
Master Set/Reset*
Width (High or Low)
Delay from Global Set/Reset net to Q
TMRW
TMRQ
21.0
18.0
18.0
ns
ns
33.0
31.0
28.0
* Timing is based on the XC4005. For other devices see XACT timing calculator.
2-77
XC4000A Logic Cell Array Family
CLB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally
tested.Sincemanyinternaltimingparameterscannotbemeasureddirectly,theyarederivedfrombenchmarktimingpatterns.Thefollowing
guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date
timing information, use the values provided by the XACT timing calculator and used in the simulator.
XC4003A
XC4005A
CLB RAM OPTION
Description
Speed Grade
Symbol
-6
-5
-4
Min Max Min Max Min Max Units
Write Operation
Address write cycle time
16 x 2
TWC
TWCT
TWP
TWPT
TAS
TAST
TAH
TAHT
TDS
9.0
9.0
5.0
5.0
2.0
2.0
2.0
2.0
4.0
5.0
2.0
8.0
8.0
4.0
4.0
2.0
2.0
2.0
2.0
4.0
5.0
2.0
8.0
8.0
4.0
4.0
2.0
2.0
2.0
2.0
4.0
5.0
2.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
32 x 1
16 x 2
32 x 1
16 x 2
32 x 1
16 x 2
32 x 1
16 x 2
32 x 1
both
Write Enable pulse width (High)
Address set-up time before beginning of WE
Address hold time after end of WE
DIN set-up time before end of WE
DIN hold time after end of WE
TDST
TDHT
Read Operation
Address read cycle time
16 x 2
32 x 1
16 x 2
32 x 1
TRC
7.0
10.0
5.5
7.5
5.0
7.0
ns
ns
4.0 ns
6.0 ns
TRCT
TILO
TIHO
Data valid after address change
(no Write Enable)
6.0
8.0
4.5
7.0
Read Operation, Clocking Data into Flip-Flop
Address setup time before clock K
16 x 2
32 x 1
TICK
TIHCK
6.0
8.0
4.5
6.0
4.5
6.0
ns
ns
Read During Write
Data valid after WE going active
(DIN stable before WE)
Data valid after DIN
16 x 2
32 x 1
16 x 2
32 x 1
TWO
TWOT
TDO
12.0
15.0
11.0
14.0
10.0
12.0
9.0
9.0 ns
11.0 ns
8.5 ns
(DIN change during WE)
TDOT
11.0
11.0 ns
Read During Write, Clocking Data into Flip-Flop
WE setup time before clock K
16 x 2
32 x 1
16 x 2
32 x 1
TWCK
TWCKT 15.0
TDCK
TDCKT
12.0
10.0
12.0
9.0
9.5
11.5
9.0
ns
ns
ns
ns
Data setup time before clock K
11.0
14.0
11.0
11.0
Note: Timing for the 16 x 1 RAM option is identical to 16 x 2 RAM timing
2-78
CLB RAM Timing Characteristics
T
RC
ADDRESS
WRITE
T
AS
T
T
WP
AH
T
WRITE ENABLE
T
DH
DS
DATA IN
REQUIRED
T
ILO
READ
X,Y OUTPUTS
VALID
VALID
READ, CLOCKING DATA INTO FLIP-FLOP
T
ICK
T
CH
CLOCK
T
CKO
VALID
(OLD)
VALID
(NEW)
XQ,YQ OUTPUTS
READ DURING WRITE
T
WP
WRITE ENABLE
T
DH
DATA IN
(stable during WE)
T
WO
X,Y OUTPUTS
VALID
VALID
DATA IN
(changing during WE)
OLD
NEW
T
T
DO
WO
VALID
(PREVIOUS)
VALID
(OLD)
VALID
(NEW)
X,Y OUTPUTS
READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP
T
WP
WRITE ENABLE
T
WCK
T
DCK
DATA IN
CLOCK
T
CKO
XQ,YQ OUTPUTS
X2640
XC4002A Pinouts
Pin
Description
Bound
Pin
Description
Bound
PC84 PQ100 VQ100 PG120 Scan
Pin
Description
Bound
PC84 PQ100 VQ100 PG120 Scan
PC84 PQ100 VQ100 PG120 Scan
VCC
I/O (A8)
I/O (A9)
–
2
3
4
–
–
5
6
–
7
8
–
–
9
92
93
94
95*
96*
97
98
–
89
90
91
92*
93*
94
95
–
G3
G1
F1
–
26
29
–
I/O
28
29
30
31
32
33
34
35
36
–
23
24
25
26
27
28
29
30
31
–
20
21
22
23
24
25
26
27
28
–
C9
92
95
98
–
–
–
–
58
59
60
61
62*
63*
64
65
66
67
68
69
70*
–
–
55
56
57
58
59*
60*
61
62
63
64
65
66
67*
–
L9
–
SGCK2 (I/O)
A12
B11
C10
I/O (D6)
58
–
M10 157
O (M1)
I/O
N11
M9
N10
L8*
N9*
M8
N8
M7
L7
160
163
166
–
E1*
F2*
F3
GND
I/O (D5)
59
60
–
–
–
I (M0)
C11 101†
D11
B12 102†
I/O (CSO)
I/O (A10)
I/O (A11)
–
32
35
–
VCC
–
–
D1
I (M2)
–
–
–
E2*
C1
PGCK2 (I/O)
C12
A13
B13*
E11*
D12
C13
E12
D13
103
106
–
I/O (D4)
61
62
63
64
65
66
–
169
172
–
I/O (A12)
I/O (A13)
–
99
100
–
96
97
–
38
41
–
I/O (HDC)
I/O
D2
–
VCC
E3*
B1*
C2
–
–
–
–
–
GND
–
–
–
–
–
I/O
–
32
33
34
35
36*
37*
38
39
40
41
42
43
44*
45*
46
47
48
49
–
29
30
31
32
109
112
115
118
–
I/O (D3)
N7
N6
N5*
M6*
L6
175
178
–
I/O (A14)
1
98
99
100
1
44
47
–
I/O (LDC)
37
38
39
–
I/O (RS)
SGCK1 (A15, I/O) 10
2
D3
I/O
–
VCC
GND
11
12
3
C3
I/O
–
–
–
4
C4
–
–
33* F11*
34* E13*
I/O (D2)
67
68
69
70
–
71
72
73
74
–
68
69
70
71
–
181
184
187
190
–
PGCK1 (A16, I/O) 13
5
2
B2
50
53
–
–
–
–
I/O
N4
M5
N3
M4*
L5*
N2
M3
L4
I/O (A17)
14
–
6
3
B3
I/O
40
41
42
43
44
45
–
35
36
37
38
39
40
F12
F13
G12
G11
G13
H13
121
124
–
I/O (D1)
–
–
–
A1*
A2*
C5
I/O (ERR, INIT)
I/O (RCLK-BUSY/RDY)
–
–
–
–
–
VCC
–
–
I/O (TDI)
15
16
–
7
4
56
59
–
GND
–
–
–
–
–
I/O (TCK)
8
5
B4
I/O
127
130
–
I/O (D0, DIN)
SGCK4 (DOUT, I/O)
CCLK
71
72
73
74
75
76
77
78
–
75
76
77
78
79
80
81
82
–
72
73
74
75
76
77
78
79
–
193
196
–
–
I/O (TMS)
I/O
–
–
–
A3*
B5
I/O
17
18
–
9
6
62
65
–
–
41* J13*
42* H12*
10
–
7
A4
–
–
–
VCC
L3
–
–
C6*
A5*
B6
I/O
46
47
48
49
–
43
44
45
46
–
H11
K13
J12
133
136
139
142
–
O (TDO)
GND
M2
K3
–
–
–
11*
12
13
14
15
16
17
18*
–
8*
9
–
I/O
–
I/O
I/O
GND
VCC
I/O
I/O
–
19
20
21
22
23
24
–
68
71
–
I/O
I/O (A0, WS)
PGCK4 (I/O,A1)
–
L2
2
10
11
12
13
14
15*
–
A6
I/O
L13
N1
M1*
J3*
K2
5
B7
–
–
K12*
J11*
M13
L12
–
C7
–
–
–
–
–
–
–
–
–
–
A7
74
77
–
I/O
50
51
52
53
54
55
56
57
–
50
51
52
53
54
55
56
57
–
47
48
49
50
51
52
53
54
–
145
148
–
I/O (CS1, A2)
I/O (A3)
I/O (A4)
I/O (A5)
–
79
80
81
82
–
83
84
85
86
87*
88*
89
90
91
80
81
82
83
84*
85*
86
87
88
8
A8
SGCK3 (I/O)
GND
L1
11
14
17
–
A9*
B8*
C8
K11
L11
J2
–
–
–
DONE
VCC
–
K1
I/O
I/O
I/O
I/O
–
25
26
27
–
19
20
21
22
–
16
17
18
19
–
80
83
86
89
–
L10
–
H3*
J1*
H2
H1
G2
A10
B9
M12
M11
N13
N12*
–
–
–
–
PROG
I/O (D7)
PGCK3 (I/O)
–
151
154
–
I/O (A6)
I/O (A7)
GND
83
84
1
20
23
–
A11
B10*
–
* Indicates unconnected package pins.
† Contributes only one bit (.i) to the boundary scan register.
Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O
Boundary Scan Bit 199 = BSCANT.UPD
XC4003A Pinouts
Pin
Description
Bound
PC84 VQ100 PQ100 PG120 Scan
Pin
Description
Bound
PC84 VQ100 PQ100 PG120 Scan
VCC
2
3
89
90
91
92
93
94
95
–
92
93
94
95
96
97
98
–
G3
G1
–
32
35
38
41
44
47
–
GND
43
44
45
–
38
39
40
41
42
43
44
45
46
–
41
42
43
44
45
46
47
48
49
–
G11
G13
H13
J13
H12
H11
K13
J12
L13
K12*
J11*
M13
L12
K11
L11
L10
M12
M11
N13
N12*
L9*
M10
N11
M9
N10
L8
–
157
160
163
166
169
172
175
178
–
I/O (A8)
I/O
I/O (A9)
4
F1
I/O
I/O
–
E1
I/O
I/O
–
F2
I/O
–
I/O (A10)
5
F3
I/O
46
47
48
49
–
I/O (A11)
6
D1
I/O
–
–
E2*
C1
I/O
I/O (A12)
7
96
97
–
99
100
–
50
53
–
I/O
I/O (A13)
8
D2
–
–
–
E3*
B1*
C2
–
–
–
–
–
–
–
–
–
–
I/O
50
51
52
53
54
55
56
57
–
47
48
49
50
51
52
53
54
–
50
51
52
53
54
55
56
57
–
181
184
–
I/O (A14)
9
98
99
100
1
1
56
59
–
SGCK3 (I/O)
SGCK1 (A15,I/O)
10
11
12
13
14
–
2
D3
GND
VCC
3
C3
DONE
–
GND
4
C4
–
VCC
–
PGCK1 (A16, I/O)
2
5
B2
62
65
–
–
PROG
I/O (A17)
3
6
B3
I/O (D7)
187
190
–
–
–
–
A1*
A2*
C5
PGCK3 (I/O)
–
–
–
–
–
–
I/O (TDI)
15
16
–
4
7
68
71
–
–
–
–
–
–
I/O (TCK)
5
8
B4
I/O (D6)
58
–
55
56
57
58
59
60
61
62
63
64
65
66
67
–
58
59
60
61
62
63
64
65
66
67
68
69
70
–
193
196
199
202
205
208
211
214
–
–
–
–
A3*
B5
I/O
I/O (TMS)
17
18
–
6
9
74
77
80
83
86
89
–
I/O (D5)
59
60
–
I/O
7
10
–
A4
I/O (CS0)
I/O
–
C6
I/O
I/O
–
8
11
12
13
14
15
16
17
18
–
A5
I/O
–
N9
I/O
19
20
21
22
23
24
–
9
B6
I/O (D4)
61
62
63
64
65
66
–
M8
N8
I/O
10
11
12
13
14
15
–
A6
I/O
GND
B7
VCC
M7
L7
VCC
C7
–
GND
–
I/O
A7
92
95
98
101
104
107
110
113
–
I/O (D3)
N7
217
220
223
226
229
232
235
238
–
I/O
A8
I/O (RS)
N6
I/O
A9
I/O
N5
I/O
–
B8
I/O
–
M6
L6
I/O
25
26
27
–
16
17
18
19
–
19
20
21
22
–
C8
I/O (D2)
67
68
69
70
–
68
69
70
71
–
71
72
73
74
–
I/O
A10
B9
I/O
N4
I/O
I/O (D1)
M5
N3
I/O
A11
B10*
C9
I/O (RCLK-BUSY/RDY)
–
I/O
–
–
–
M4*
L5*
N2
28
29
30
31
32
33
34
35
36
–
20
21
22
23
24
25
26
27
28
–
23
24
25
26
27
28
29
30
31
–
116
119
122
–
–
–
–
–
SGCK2 (I/O)
O (M1)
GND
A12
B11
C10
C11
D11
B12
C12
A13
B13*
E11*
D12
C13
E12
D13
F11
E13
F12
F13
G12
I/O (D0, DIN)
SGCK4 (DOUT, I/O)
CCLK
71
72
73
74
75
76
77
78
–
72
73
74
75
76
77
78
79
–
75
76
77
78
79
80
81
82
–
241
244
–
M3
L4
I (M0)
VCC
125†
VCC
L3
–
–
O (TDO)
GND
M2
K3
–
I (M2)
PGCK2 (I/O)
I/O (HDC)
–
126†
127
130
–
–
I/O (A0, WS)
PGCK4 (A1, I/O)
–
L2
2
N1
5
M1*
J3*
K2
–
–
–
–
–
–
–
–
–
–
–
I/O
–
29
30
31
32
33
34
35
36
37
32
33
34
35
36
37
38
39
40
133
136
139
142
145
148
151
154
–
I/O (CS1, A2)
I/O (A3)
I/O (A4)
I/O (A5)
I/O
79
80
81
82
–
80
81
82
83
84
85
86
87
88
83
84
85
86
87
88
89
90
91
8
I/O (LDC)
I/O
37
38
39
–
L1
11
14
17
20
23
26
29
–
J2
I/O
K1
I/O
H3
I/O
–
I/O
–
J1
I/O
40
41
42
I/O (A6)
I/O (A7)
GND
83
84
1
H2
I/O (ERR, INIT)
VCC
H1
G2
* Indicates unconnected package pins.
† Contributes only one bit (.i) to the boundary scan register.
Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O
Boundary Scan Bit 247 = BSCANT.UPD
XC4004A Pinouts
Pin
Description
Bound
Pin
Description
Bound
PC84 TQ144 PQ160 PG120 Scan
Pin
Description
Bound
PC84 TQ144 PQ160 PG120 Scan
PC84 TQ144 PQ160 PG120 Scan
VCC
I/O (A8)
I/O (A9)
I/O
2
3
4
–
–
5
6
–
–
–
–
–
7
8
–
–
9
128
129
130
131
132
133
134
142
143
144
145
146
147
148
G3
G1
F1
E1
F2
F3
D1
–
–
38
41
44
47
50
53
–
I/O
28
29
30
31
32
33
34
35
36
–
32
33
34
35
36
37
38
39
40
41
42
43
44
–
36
37
38
39
40
41
42
43
44
45
46
47
48
49*
50*
51
52*
53*
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68*
69*
70
71*
72*
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89*
C9
140
143
146
–
–
–
–
–
81
82*
83*
84
85
86
87
88
89
90
91
92
93
94
95
96
97
90*
91
–
–
–
–
SGCK2 (I/O)
A12
B11
C10
C11 149†
D11
B12 150†
GND
O (M1)
–
–
92*
93*
94
–
–
GND
–
–
–
–
I/O
I (M0)
I/O (D5)
59
60
–
M9
N10
L8
N9
M8
N8
M7
L7
N7
N6
N5
M6
L6
N4
–
241
244
247
250
253
256
–
I/O (A10)
I/O (A11)
–
VCC
–
I/O (CSO)
95
I (M2)
I/O
96
135* 149*
136* 150*
PGCK2 (I/O)
C12
A13
B13
E11
D12
C13
–
151
154
157
160
163
166
–
I/O
–
97
–
–
–
I/O (HDC)
I/O (D4)
61
62
63
64
65
66
–
98
GND
–
137
–
151
152*
153*
154
155
156
157
158
159
160
1
E2
–
–
I/O
I/O
99
–
I/O
–
VCC
100
101
102
103
104
105
106
107
–
–
–
–
I/O
–
GND
–
I/O (A12)
I/O (A13)
I/O
138
139
140
141
142
143
144
1
C1
D2
E3
B1
C2
D3
C3
C4
B2
B3
A1
A2
C5
B4
–
56
59
62
65
68
71
–
I/O (LDC)
37
–
I/O (D3)
259
262
265
268
271
274
–
–
I/O (RS)
–
–
–
–
–
I/O
I/O
GND
–
45
46*
47*
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62*
63*
64
–
–
–
I/O
–
I/O (A14)
–
–
–
–
I/O (D2)
67
68
–
SGCK1 (A15, I/O) 10
–
–
–
–
I/O
VCC
GND
11
12
I/O
38
39
–
E12
D13
F11
E13
F12
F13
G12
G11
G13
H13
J13
H12
H11
K13
–
169
172
175
178
181
184
–
–
98* 108*
99* 109*
–
I/O
–
–
–
–
PGCK1 (A16, I/O) 13
2
2
74
77
80
83
86
89
–
I/O
GND
–
100
–
110
111*
112*
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
–
–
I/O (A17)
14
–
3
3
I/O
–
–
–
–
–
I/O
4
4
I/O
40
41
42
43
44
45
–
–
–
–
–
–
I/O
–
5
5
I/O (ERR, INIT)
I/O (D1)
69
70
–
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
M5
N3
M4
L5
N2
M3
L4
L3
M2
K3
L2
N1
M1
J3
K2
L1
–
277
280
283
286
289
292
–
I/O (TDI)
15
16
–
6
6
VCC
I/(ORCLK-BUSY/RDY)
I/O (TCK)
7
7
GND
–
I/O
–
–
–
8*
9*
I/O
187
190
193
196
199
202
–
I/O
–
–
–
–
–
I/O
I/O (D0, DIN)
71
72
73
74
75
76
77
78
–
GND
–
–
8
10
A3
–
–
I/O
SGCK4 (DOUT, I/O)
–
9*
10*
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25*
26*
27
–
11*
12*
13
–
I/O
–
CCLK
–
–
–
–
I/O
46
47
–
VCC
–
I/O (TMS)
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
–
17
18
–
B5
A4
C6
A5
B6
A6
B7
C7
A7
A8
A9
B8
C8
A10
–
92
95
98
101
104
107
–
I/O
O (TDO)
–
14
–
GND
–
15
–
–
–
–
I/O (A0, WS)
2
–
16
GND
–
–
–
PGCK4 (I/O,A1)
5
19
20
21
22
23
24
–
17
–
–
–
–
I/O
8
18
–
I/O
–
–
–
I/O
–
11
14
17
–
19
48
49
–
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
-
J12
L13
K12
J11
M13
L12
K11
L11
L10
M12
M11
N13
N12
L9
205
201
211
214
217
220
–
I/O (CS1, A2)
79
80
–
20
–
I/O
I/O (A3)
21
110
113
116
119
122
125
–
I/O
–
–
117* 129*
22
I/O
–
–
–
130*
131
–
–
23
I/O
50
51
52
53
54
55
56
57
-
GND
–
–
118
–
–
–
24
SGCK3 (I/O)
GND
DONE
VCC
–
119* 132*
120* 133*
–
–
25
26
–
25
–
–
–
–
26
–
I/O (A4)
I/O (A5)
–
81
82
–
121
122
–
134
135
136*
137
138
139
140
141
J2
K1
–
20
23
–
27*
28*
29
–
–
–
–
–
PROG
I/O (D7)
PGCK3 (I/O)
I/O
–
GND
–
–
–
–
223
226
229
232
235
238
–
I/O
–
123
124
125
126
127
H3
J1
H2
H1
G2
26
29
32
35
–
–
30*
31*
32
–
–
I/O
–
–
–
–
–
–
I/O (A6)
I/O (A7)
GND
83
84
1
I/O
I/O
I/O
I/O
27
–
28
29
30
31
B9
A11
B10
–
128
131
134
137
I/O
-
33
I/O (D6)
I/O
58
-
M10
N11
-
–
34
–
35
-
-
* Indicates unconnected package pins.
† Contributes only one bit (.i) to the boundary scan register.
Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O
Boundary Scan Bit 295 = BSCANT.UPD
XC4005A Pinouts
Pin
Description
Bound
PC84 TQ144 PQ160 PQ208 PG156 Scan
Pin
Description
Bound
PC84 TQ144 PQ160 PQ208 PG156 Scan
VCC
2
3
128
129
130
131
132
–
142
143
144
145
146
–
183
184
185
186
187
188*
189*
190
191
192
193
194
195*
196*
197*
198*
199
200
–
H3
H1
G1
G2
G3
–
–
44
47
50
53
–
I/O
–
–
31
–
35
–
45
–
C12
–
161
–
I/O (A8)
–
I/O (A9)
4
I/O
28
29
30
31
32
–
32
33
34
35
36
–
36
37
38
39
40
–
46
B13
B14
A15
C13
A16
–
164
167
170
–
I/O
–
SGCK2 (I/O)
47
I/O
–
O (M1)
48
–
–
GND
49
†
–
–
–
–
–
–
I (M0)
50
173
–
I/O (A10)
5
133
134
135
136
137
–
147
148
149
150
151
–
F1
F2
E1
E2
F3
–
56
59
62
65
–
–
51*
52*
53*
54*
55
I/O (A11)
6
–
–
–
–
–
–
I/O
–
–
–
–
–
–
–
I/O
–
–
–
–
–
–
–
GND
–
VCC
33
34
35
36
–
37
38
39
40
41
–
41
42
43
44
45
–
C14
B15
B16
D14
C15
–
–
†
–
–
–
I (M2)
56
174
–
–
–
–
–
–
PGCK2 (I/O)
57
175
178
181
–
–
–
–
152*
153*
154
155
–
D1*
D2*
E3
C1
–
–
I/O (HDC)
58
–
–
–
–
I/O
59
I/O (A12)
7
138
139
–
68
71
–
–
–
–
I/O (A13)
8
I/O
–
42
43
44
–
46
47
48
49*
50*
–
60
D15
E14
C16
E15*
D16*
–
184
187
190
–
–
–
I/O
–
61
I/O
–
140
141
142
143
144
–
156
157
158
159
160
–
201
202
203
204
205
206*
207*
208*
1*
C2
D3
B1
B2
C3
–
74
77
80
83
–
I/O (LDC)
37
–
62
I/O
–
–
63*
64*
65*
66*
67
I/O (A14)
9
–
–
–
–
SGCK1 (A15, I/O)
10
11
–
–
–
–
–
VCC
–
–
–
–
–
–
–
–
GND
–
45
46
47
48
49
–
51
52
53
54
55
–
F14
F15
E16
F16
G14
–
–
–
–
–
–
–
–
I/O
–
68
193
196
199
202
–
–
–
–
–
–
–
I/O
–
69
–
–
–
–
–
–
I/O
38
39
–
70
GND
12
–
1
1
2
C4
–
–
I/O
71
–
–
–
3*
4
–
–
72*
73*
74
PGCK1 (A16, I/O)
13
14
–
2
2
B3
A1
A2
C5
–
86
89
92
95
–
–
–
–
–
–
–
I/O (A17)
3
3
5
I/O
–
50
51
52
53
54
55
56
57
58
59
–
56
57
58
59
60
61
62
63
64
65
–
G15
G16
H16
H15
H14
J14
J15
J16
K16
K15
–
205
208
211
214
–
I/O
4
4
6
I/O
–
75
I/O
–
5
5
7
I/O
40
41
42
43
44
45
–
76
–
–
–
–
–
I/O (ERR, INIT)
77
I/O (TDI)
15
16
–
6
6
8
B4
A3
A4*
–
98
101
–
VCC
78
I/O (TCK)
7
7
9
GND
79
–
–
–
–
8*
9*
–
10*
11*
12*
13*
14
I/O
80
217
220
223
226
–
–
–
–
I/O
81
–
–
–
–
–
I/O
82
–
–
–
–
–
–
I/O
–
83
GND
I/O
I/O
I/O (TMS)
I/O
–
–
8
10
11
12
13
14
–
C6
B5
B6
A5
C7
–
–
–
–
84*
85*
86
–
9
15
104
107
110
113
–
–
–
–
–
–
–
–
10
11
12
–
16
I/O
46
47
–
60
61
62
63
64
–
66
67
68
69
70
–
K14
L16
M16
L15
L14
–
229
232
235
238
–
17
18
–
17
I/O
87
18
I/O
88
19*
20*
21
I/O
–
89
–
–
–
–
–
–
GND
–
90
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
–
–
13
14
15
16
17
18
19
20
21
22
–
15
16
17
18
19
20
21
22
23
24
–
B7
A6
A7
A8
C8
B8
C9
B9
A9
B10
–
116
119
122
125
–
–
–
91*
92*
93*
94*
95
–
–
22
–
–
–
–
–
–
19
20
21
22
23
24
–
23
–
–
–
71*
72*
73
74
75
76
77
78
79
–
N16*
M15*
P16
M14
N15
P15
N14
R16
P14
–
–
24
–
–
–
–
25
I/O
48
49
–
65
66
67
68
69
70
71
–
241
244
247
250
253
256
–
26
–
I/O
96
27
128
131
134
137
–
I/O
97
28
I/O
–
98
29
I/O
50
51
52
–
99
–
30
SGCK3 (I/O)
100
101
102*
103
104*
105*
106
107*
108
109
110
111
–
–
31*
32*
33
GND
–
–
–
–
–
–
–
–
I/O
I/O
I/O
I/O
GND
–
25
26
–
23
24
25
26
27
–
25
26
27
28
29
–
C10
A10
A11
B11
C11
–
140
143
146
149
–
DONE
53
–
72
–
80
–
R15
–
–
34
–
–
35
–
VCC
–
–
–
–
–
–
36
54
–
73
–
81
–
P13
–
–
–
37
–
–
–
38*
39*
40*
41*
42
–
PROG
I/O (D7)
PGCK3 (I/O)
I/O
55
56
57
–
74
75
76
77
–
82
83
84
85
–
R14
T16
T15
R13
–
–
–
–
–
–
–
–
259
262
265
–
–
–
–
30*
31*
32
33
34
A12*
–
–
–
–
–
–
I/O
I/O
I/O
27
–
28
29
30
B12
A13
A14
152
155
158
–
–
43
I/O
–
78
79
86
87
112
113
P12
T14
268
271
–
44
I/O(D6)
58
* Indicates unconnected package pins.
† Contributes only one bit (.i) to the boundary scan register.
XC4005A Pinouts (continued)
Pin
Bound
Descriptions
PC84
TQ144
PQ160
88
PQ208
114
PG156
T13
R12*
T12*
–
Scan
I/O
–
–
–
–
–
–
–
80
–
274
–
89*
90*
–
115*
116*
117*
118*
119
–
–
–
–
–
–
–
–
–
–
–
81
91
P11
–
GND
I/O
–
–
82
83
84
85
–
92
93
94
95
–
120
121
122
123
124*
125*
126
127
128
129
130
R11
T11
T10
P10
–
277
280
283
286
–
I/O
I/O (D5)
I/O (CS0)
–
59
60
–
–
–
–
–
–
–
I/O
–
86
87
88
89
90
96
97
98
99
100
R10
T9
289
292
295
298
–
I/O
–
I/O (D4)
I/O
61
62
63
R9
P9
R8
VCC
64
91
101
131
P8
–
GND
I/O (D3)
65
66
–
92
93
94
95
–
102
103
104
105
–
132
133
134
135
136*
137*
138
139
140
141
142
T8
T7
T6
R7
–
301
304
307
310
–
I/O (RS)
I/O
I/O
–
–
–
–
–
–
–
–
–
I/O (D2)
67
68
–
96
97
98
99
100
106
107
108
109
110
P7
T5
R6
T4
P6
313
316
319
322
–
I/O
I/O
I/O
–
–
GND
–
–
–
–
–
143*
144*
145*
146*
147
148
149
–
–
–
–
–
–
–
–
–
–
–
111*
112*
113
114
115
–
R5*
–
–
–
–
–
–
I/O (D1)
69
70
–
101
102
103
–
T3
P5
R4
–
325
328
331
–
I/O (RCLK-BUSY/RDY)
I/O
–
–
I/O
–
104
105
106
107
108
116
117
118
119
120
150
151
152
153
154
R3
P4
T2
R2
P3
334
337
340
–
I/O (D0, DIN)
71
72
73
74
SGCK4 (DOUT, I/O)
CCLK
–
VCC
–
–
–
–
–
–
–
155*
156*
157*
158*
159
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
O (TDO)
75
76
109
110
121
122
T1
N3
160
GND
I/O (A0,WS)
77
78
–
111
112
113
–
123
124
125
–
161
162
163
–
R1
P2
N2
–
2
5
PGCK4 (A1,I/O)
I/O
8
–
–
–
I/O
–
114
115
116
117*
–
126
127
128
129*
130*
–
164
165
166
167*
168*
169*
170*
171
M3
P1
N1
M2*
M1*
–
11
14
17
–
I/O (CS1,A2)
79
80
–
I/O (A3)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
118
131
L3
–
GND
I/O
–
–
119
120
121
122
–
132
133
134
135
–
172
173
174
175
176*
177*
178
179
180
181
182
L2
L1
K3
K2
–
20
23
26
29
–
I/O
I/O (A4)
I/O (A5)
–
81
82
–
–
–
–
136*
137
138
139
140
141
–
–
I/O
–
123
124
125
126
127
K1
J1
J2
J3
H2
32
35
38
41
–
I/O
–
I/O (A6)
I/O (A7)
GND
83
84
1
* Indicates unconnected package pins.
Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O
Boundary Scan Bit 343 = BSCANT.UPD
Ordering Information
Example:
XC4005A-5 PQ160C
Device Type
Temperature Range
Speed Grade
Number of Pins
Package Type
Component Availability
PINS
84
100
120
144
156
160
164
TOP
191
196
TOP
208
223
225
240
299
TOP
TYPE
PLAST. PLAST. PLAST. BRAZED CERAM. PLAST. CERAM PLAST. BRAZED CERAM. BRAZED PLAST. METAL CERAM. PLAST. PLAST. METAL METAL
PLCC PQFP VQFP CQFP PGA TQFP PGA PQFP CQFP PGA CQFP PQFP PQFP PGA BGA PQFP PQFP PQFP
CODE
PC84 PQ100 VQ100 CB100 PG120 TQ144 PG156 PQ160 CB164 PG191 CB196 PQ208 MQ208 PG223 BG225 PQ240 MQ240 PG299
XC4002A
-6
-5
C I
C
C I
C
C I
C
C I
C
-4
XC4003A
-10
-6
M B
M B
M B
C I
C
C I
C
C I
C
C I M B
-5
C
C
-4
C
C
C
XC4004A
XC4005A
-6
C I
C
C I
C
C I
C
C I
C
-5
-4
-6
-5
-4
C I
C I
C
C I
C I
C
C I
C I
C
C I
C I
C
C I
C I
C
M = Mil Temp = -55° to +125° C
C = Commercial = 0° to +85° C
I = Industrial = -40° to +100° C
B = MIL-STD-883C Class B
Parentheses indicate future product plans
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