XC4005-36XL [XILINX]
XC4000XL Electrical Specifications; XC4000XL电气连接特定的阳离子
| 型号： | XC4005-36XL |
| 厂家： | 
XILINX, INC |
| 描述： | XC4000XL Electrical Specifications |
| 文件： | 总16页 (文件大小：69K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000XL Electrical Specifications
Definition of Terms
In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as
follows:
Advance:
Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or
devicefamilies. Values are subject to change. Use as estimates, not for production.
Preliminary:
Unmarked:
Based on preliminary characterization. Further changes are not expected.
Specifications not identified as either Advance or Preliminary are to be considered Final.
Except for pin-to-pin input and output parameters, the a.c. parameter delay specifications included in this document are
derived from measuring internal test patterns. All specifications are representative of worst-case supply voltage and junction
temperature conditions.
All specifications subject to change without notice.
XC4000XL D.C. Characteristics
Absolute Maximum Ratings
Description
Supply voltage relative to Ground
Units
V
VCC
VIN
-0.5 to 4.0
-0.5 to 5.5
-0.5 to 5.5
50
Input voltage relative to Ground (Note 1)
V
6
VTS
Voltage applied to 3-state output (Note 1)
Longest Supply Voltage Rise Time from 1 V to 3V
Storage temperature (ambient)
V
VCCt
TSTG
TSOL
ms
°C
°C
°C
°C
-65 to +150
+260
Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm)
Ceramic packages
Plastic packages
+150
TJ
Junction Temperature
+125
Note 1: Maximum DC excursion above V or below Ground must be limited to either 0.5 V or 10 mA, whichever is easier to
cc
achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot toV +2.0 V, provided this over or
CC
undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA.
Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended
periods of time may affect device reliability.
Recommended Operating Conditions
Symbol
Description
Min
Max
3.6
Units
V
Supply voltage relative to Gnd, TJ = 0 °C to +85°C
Commercial
3.0
VCC
Supply voltage relative to Gnd, TJ = -40°C to +100°C Industrial
High-level input voltage
3.0
50% of VCC
0
3.6
V
VIH
VIL
5.5
V
Low-level input voltage
30% of VCC
250
V
TIN
Input signal transition time
ns
Notes:
At junction temperatures above those listed above, all delay parameters increase by 0.35% per °C.
Input and output measurement threshold is ~50% of V
.
CC
DS005 (v. 1.8 October 18, 1999 - Product Specification
6-73
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
D.C. Characteristics Over Recommended Operating Conditions
Symbol
Description
Min
2.4
Max
Units
V
High-level output voltage @ IOH = -4.0 mA, VCC min (LVTTL)
High-level output voltage @ IOH = -500 µA, (LVCMOS)
Low-level output voltage @ IOL = 12.0 mA, VCC min (LVTTL) (Note 1)
Low-level output voltage @ IOL = 1500 µA, (LVCMOS)
Data Retention Supply Voltage (below which configuration data may be lost)
Quiescent FPGA supply current (Note 2)
VOH
90% VCC
V
0.4
V
VOL
10% VCC
V
VDR
ICCO
IL
2.5
-10
V
5
mA
µA
pF
Input or output leakage current
+10
10
Input capacitance (sample tested)
BGA, SBGA, PQ, HQ, MQ
packages
CIN
PGA packages
16
pF
mA
mA
mA
IRPU
IRPD
IRLL
Pad pull-up (when selected) @ Vin = 0 V (sample tested)
Pad pull-down (when selected) @ Vin = 3.6 V (sample tested)
Horizontal Longline pull-up (when selected) @ logic Low
With up to 64 pins simultaneously sinking 12 mA.
0.02
0.02
0.3
0.25
0.15
2.0
Note 1:
Note 2:
With no output current loads, no active input or Longline pull-up resistors, all I/O pins Tri-stated and floating.
Power-0n Power Supply Requirements
Xilinx FPGAs require a minimum rated power supply current capacity to insure proper initialization, and the power supply
ramp-up time does affect the current required. A fast ramp-up time requires more current than a slow ramp-up time. The
slowest ramp-up time is 50 ms. Current capacity is not specified for a ramp-up time faster than 2ms. The current capacity
varies linealy with ramp-up time, e.g., an XC4036XL with a ramp-up time of 25 ms would require a capacity predicted by the
point on the straight line drawn from 1A at 120 µs to 500 mA at 50 ms at the 25 ms time mark. This point is approximately
750 mA .
Ramp-up Time
Product
Description
Fast (120 µs)
Slow (50 ms)
500 mA
XC4005 - 36XL
XC4044- 62XL
XC4085XL1
Minimum required current supply
Minimum required current supply
Minimum required current supply
1 A
2 A
2 A1
500 mA
500 mA
Notes: 1. The XC4085XL fast ramp-up time is 5 ms.
Devices are guaranteed to initialize properly with the minimum current listed above. A larger capacity power supply may
result in a larger initialization current.
This specification applies to Commercial and Industrial grade products only.
Ramp-up Time is measured from 0 V to 3.6 V . Peak current required lasts less than 3 ms, and occurs near the
DC
DC
internal power on reset threshold voltage. After initialization and before configuration, I max is less than 10 mA.
CC
6-74
DS005 (v. 1.8 October 18, 1999 - Product Specification
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000XL A.C. Characteristics
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven
from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data, reflecting
the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System)
and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static
timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction
temperature. Values apply to all XC4000XL devices and are expressed in nanoseconds unless otherwise noted.
Global Low Skew Buffer to Clock K
Speed Grade
Device
All
-3
-2
-1
-09
-08
Units
Description
Symbol
Min
Max
Max
Max
Max
Max
Delay from pad through GLS buffer to
any clock input, K
TGLS
XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
0.3
0.4
0.5
0.6
0.7
0.9
1.1
1.2
1.3
1.4
1.6
2.1
2.7
3.2
3.6
4.0
4.4
4.8
5.3
5.7
6.3
7.2
1.8
2.3
2.8
3.1
3.5
3.8
4.2
4.6
5.0
5.4
6.2
1.6
2.0
2.4
2.7
3.0
3.3
3.6
4.0
4.5
4.7
5.7
1.5
1.9
2.3
2.6
2.9
3.2
3.5
3.9
4.4
4.6
5.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.3
3.1
4.0
6
DS005 (v. 1.8 October 18, 1999 - Product Specification
6-75
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XC4000E and XC4000X Series Field Programmable Gate Arrays
Global Early BUFGEs 1, 2, 5, and 6 to IOB Clock
Speed Grade
Device
All
-3
-2
-1
-09
-08
Units
Description
Symbol
Min
Max
Max
Max
Max
Max
Delay from pad through GE buffer to any
IOB clock input.
TGE
XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
0.1
0.3
0.3
0.4
0.4
0.3
0.3
0.2
0.3
0.3
0.4
1.6
1.9
2.2
2.4
2.6
2.8
3.1
3.5
4.0
4.9
5.8
1.4
1.8
1.9
2.1
2.2
2.4
2.7
3.0
3.5
4.3
5.1
1.3
1.7
1.7
1.8
2.1
2.1
2.3
2.6
3.0
3.7
4.7
1.2
1.6
1.7
1.7
2.0
2.0
2.2
2.4
3.0
3.4
4.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.5
1.9
3.0
Global Early BUFGEs 3, 4, 7, and 8 to IOB Clock
Speed Grade
All
-3
-2
-1
-09
-08
Units
Description
Symbol
Device
Min
Max
Max
Max
Max
Max
Delay from pad through GE buffer to any
IOB clock input.
TGE
XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
0.5
0.7
0.7
0.7
0.8
0.9
0.9
1.0
1.1
1.2
1.3
2.8
3.1
3.5
3.8
4.1
4.4
4.7
5.1
5.5
5.9
6.8
2.5
2.8
3.1
3.3
3.6
3.9
4.2
4.5
4.8
5.2
6.0
2.1
2.7
2.8
2.9
3.4
3.4
3.7
4.0
4.3
4.8
5.5
1.7
2.5
2.7
2.8
3.2
3.3
3.6
3.7
4.3
4.5
5.2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.4
3.1
4.0
6-76
DS005 (v. 1.8 October 18, 1999 - Product Specification
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000XL CLB Characteristics
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
XC4000XL devices and are expressed in nanoseconds unless otherwise noted.
CLB Switching Characteristic Guidelines
Speed Grade
Symbol
-3
-2
-1
-09
-08
Description
Combinatorial Delays
Min Max Min Max Min Max Min Max Min Max
F/G inputs to X/Y outputs
F/G inputs via H’ to X/Y outputs
T
T
T
T
T
T
T
1.6
2.7
2.9
2.5
2.4
2.5
1.5
1.5
2.4
2.6
2.2
2.1
2.2
1.3
1.3
2.2
2.2
2.0
1.9
2.0
1.1
1.2
2.0
2.0
1.8
1.6
1.8
1.0
1.1
1.9
1.8
1.8
1.5
1.8
0.9
ILO
IHO
F/G inputs via transparent latch to Q outputs
C inputs via SR/H0 via H to X/Y outputs
C inputs via H1 via H to X/Y outputs
C inputs via DIN/H2 via H to X/Y outputs
C inputs via EC, DIN/H2 to YQ, XQ output (bypass)
ITO
HH0O
HH1O
HH2O
CBYP
CLB Fast Carry Logic
Operand inputs (F1, F2, G1, G4) to C
T
T
T
T
T
T
2.7
3.3
2.0
2.8
0.26
0.32
2.3
2.9
1.8
2.6
0.23
0.28
2.0
2.5
1.5
2.4
0.20
0.25
1.6
1.8
1.0
1.7
0.14
0.24
1.6
1.8
0.9
1.5
0.14
0.24
OUT
OPCY
ASCY
INCY
SUM
BYP
Add/Subtract input (F3) to C
OUT
Initialization inputs (F1, F3) to C
OUT
C
C
through function generators to X/Y outputs
IN
to C
, bypass function generators
IN
OUT
Carry Net Delay, C
to C
6
OUT
IN
NET
Sequential Delays
Clock K to Flip-Flop outputs Q
Clock K to Latch outputs Q
T
T
2.1
2.1
1.9
1.9
1.6
1.6
1.5
1.5
1.4
1.4
CKO
CKLO
Setup Time before Clock K
F/G inputs
F/G inputs via H
C inputs via H0 through H
C inputs via H1 through H
C inputs via H2 through H
C inputs via DIN
C inputs via EC
C inputs via S/R, going Low (inactive)
CIN input via F/G
T
T
T
T
T
T
T
T
T
T
1.1
2.2
2.0
1.9
2.0
0.9
1.0
0.6
2.3
3.4
1.0
1.9
1.7
1.6
1.7
0.8
0.9
0.5
2.1
3.0
0.9
1.7
1.6
1.4
1.6
0.7
0.8
0.5
1.9
2.7
0.8
1.6
1.4
1.2
1.4
0.6
0.7
0.4
1.3
2.1
0.8
1.5
1.4
1.1
1.4
0.6
0.7
0.4
1.2
2.0
ICK
IHCK
HH0CK
HH1CK
HH2CK
DICK
ECCK
RCK
CCK
CIN input via F/G and H
CHCK
Hold Time after Clock K
F/G inputs
F/G inputs via H
C inputs via SR/H0 through H
C inputs via H1 through H
C inputs via DIN/H2 through H
C inputs via DIN/H2
T
T
T
T
T
T
T
T
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CKI
CKIH
CKHH0
CKHH1
CKHH2
CKDI
C inputs via EC
C inputs via SR, going Low (inactive)
CKEC
CKR
Clock
Clock High time
Clock Low time
T
T
3.0
3.0
2.8
2.8
2.5
2.5
2.3
2.3
2.1
2.1
CH
CL
Set/Reset Direct
Width (High)
Delay from C inputs via S/R, going High to Q
T
T
3.0
2.8
2.5
2.3
2.3
RPW
RIO
3.7
3.2
2.8
2.7
2.6
14.0
238
Global Set/Reset
T
T
F
19.8
17.3
15.0
14.0
Minimum GSR Pulse Width
Delay from GSR input to any Q
Toggle Frequency (MHz) (for export control)
MRW
MRQ
See Table on page 85 for T
values per device.
RRI
(MHz)
166
179
200
217
TOG
DS005 (v. 1.8 October 18, 1999 - Product Specification
6-77
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
CLB Single-Port RAM Synchronous (Edge-Triggered) Write Operation Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
XC4000XL devices and are expressed in nanoseconds unless otherwise noted.
Speed Grade
-3
-2
-1
-09
-08
Single Port RAM
Size Symbol Min Max Min Max Min Max Min Max Min Max
Write Operation
Address write cycle time (clock K period) 16x2 TWCS
32x1 TWCTS
9.0
9.0
8.4
8.4
7.7
7.7
7.4
7.4
7.4
7.4
Clock K pulse width (active edge)
Address setup time before clock K
Address hold time after clock K
DIN setup time before clock K
DIN hold time after clock K
WE setup time before clock K
WE hold time after clock K
16x2 TWPS
32x1 TWPTS
4.5
4.5
4.2
4.2
3.9
3.9
3.7
3.7
3.7
3.7
16x2 TASS
32x1 TASTS
2.2
2.2
2.0
2.0
1.7
1.7
1.7
1.7
1.6
1.7
16x2 TAHS
32x1 TAHTS
0
0
0
0
0
0
0
0
0
0
16x2 TDSS
32x1 TDSTS
2.0
2.5
1.9
2.3
1.7
2.1
1.7
2.1
1.7
2.1
16x2 TDHS
32x1 TDHTS
0
0
0
0
0
0
0
0
0
0
16x2 TWSS
32x1 TWSTS
2.0
1.8
1.8
1.7
1.6
1.5
1.6
1.5
1.6
1.5
16x2 TWHS
32x1 TWHTS
0
0
0
0
0
0
0
0
0
0
Data valid after clock K
16x2 TWOS
32x1 TWOTS
6.8
8.1
6.3
7.5
5.8
6.9
5.8
6.7
5.7
6.7
Read Operation
Address read cycle time
16x2 TRC
32x1 TRCT
4.5
6.5
3.1
5.5
2.6
3.8
2.6
3.8
2.6
3.8
Data Valid after address change (no
Write Enable)
16x2 TILO
32x1 TIHO
1.6
2.7
1.5
2.4
1.3
2.2
1.2
2.0
1.1
1.9
Address setup time before clock K
16x2 TICK
32x1 TIHCK
1.1
2.2
1.0
1.9
0.9
1.7
0.8
1.6
0.8
1.5
6-78
DS005 (v. 1.8 October 18, 1999 - Product Specification
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Operation Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
XC4000XL devices and are expressed in nanoseconds unless otherwise noted.
Speed Grade
-3
-2
--1
-09
-08
Dual Port RAM
Size Symbol Min Max Min Max Min Max Min Max Min Max
Address write cycle time (clock K period) 16x1 TWCDS
9.0
4.5
2.5
0
2.5
0
8.4
4.2
2.0
0
2.3
0
7.7
3.9
1.7
0
2.0
0
7.4
3.7
1.7
0
2.0
0
7.4
3.7
1.6
0
2.0
0
Clock K pulse width (active edge)
Address setup time before clock K
Address hold time after clock K
DIN setup time before clock K
DIN hold time after clock K
WE setup time before clock K
WE hold time after clock K
16x1 TWPDS
16x1 TASDS
16x1 TAHDS
16x1 TDSDS
16x1 TDHDS
16x1 TWSDS
16x1 TWHDS
16x1 TWODS
1.8
0
1.7
0
1.6
0
1.6
0
1.6
0
Data valid after clock K
7.8
7.3
6.7
6.7
6.6
CLB RAM Synchronous (Edge-Triggered) Write Timing Waveforms
6
TWPS
TWPDS
WCLK (K)
WE
WCLK (K)
WE
TWHS
TDHS
TAHS
TWSS
TWHDS
TWSDS
TDSS
TDHDS
TDSDS
DATA IN
DATA IN
TASS
TASDS
TAHDS
ADDRESS
ADDRESS
TILO
TILO
TILO
TILO
TWOS
TWODS
DATA OUT
OLD
NEW
DATA OUT
OLD
NEW
X6461
X6474
Single-Port RAM
Dual-Port RAM
DS005 (v. 1.8 October 18, 1999 - Product Specification
6-79
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000XL Pin-to-Pin Output Parameter Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted.
Output Flip-Flop, Clock to Out
Speed Grade
Device
All
-3
-2
-1
-09
-08
Units
Description
Symbol
Min
Max
Max
Max
Max
Max
Global Low Skew Clock to Output us- TICKOF
ing Output Flip Flop
XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
1.2
1.3
1.4
1.5
1.6
1.8
2.0
2.1
2.2
2.3
2.5
7.1
7.7
8.2
8.6
9.0
9.4
9.8
10.3
10.7
11.3
12.2
6.1
6.6
7.1
7.4
7.8
8.1
8.5
8.9
9.3
9.7
10.5
5.4
5.8
6.2
6.5
6.8
7.1
7.4
7.8
8.3
8.5
9.5
5.1
5.4
5.8
6.1
6.4
6.7
7.0
7.4
7.9
8.1
9.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5.6
6.4
7.3
1.6
For output SLOW option add
TSLOW All Devices
0.5
3.0
2.5
2.0
1.7
ns
Notes: Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is
measured using the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all
accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined
by the static timing analyzer (TRCE) can be added to the AC parameter Tokpof and used as a worst-case pin-to-pin
clock-to-out delay for clocked outputs for FAST mode configurations.
Output timing is measured at ~50% V threshold with 50 pF external capacitive load. For different loads, see Figure 1.
CC
Capacitive Load Factor
3
2
Figure 60 shows the relationship between I/O output delay
and load capacitance. It allows a user to adjust the speci-
fied output delay if the load capacitance is different than
50 pF. For example, if the actual load capacitance is
120 pF, add 2.5 ns to the specified delay. If the load capac-
itance is 20 pF, subtract 0.8 ns from the specified output
delay.
1
0
-1
-2
Figure 60 is usable over the specified operating conditions
of voltage and temperature and is independent of the out-
put slew rate control.
0
20 40 60 80 100 120 140
Capacitance (pF)
X8257
Figure 60: Delay Factor at Various Capacitive Loads
6-80
DS005 (v. 1.8 October 18, 1999 - Product Specification
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Output Flip-Flop, Clock to Out, BUFGE #s 1, 2, 5, and 6
Speed Grade
Device
All
-3
-2
-1
-09
-08
Units
Description
Symbol
Min
Max
Max
Max
Max
Max
Global Early Clock to Output using
Output Flip Flop. Values are for BUF-
GE #s 1, 2, 5, and 6.
TICKEOF XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
1.0
1.2
1.2
1.3
1.3
1.2
1.2
1.1
1.2
1.2
1.3
6.6
6.9
7.2
7.4
7.6
7.8
8.1
8.5
9.0
9.9
10.8
5.7
6.1
6.2
6.4
6.5
6.7
7.0
7.3
7.8
8.6
9.4
5.1
5.5
5.5
5.6
5.9
5.9
6.1
6.4
6.8
7.5
8.5
4.8
5.2
5.3
5.3
5.6
5.6
5.8
6.0
6.6
7.0
7.9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.8
5.2
6.3
Notes: Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is
measured using the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all
accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined
by the static timing analyzer (TRCE) can be added to the AC parameter Tokpof and used as a worst-case pin-to-pin
clock-to-out delay for clocked outputs for FAST mode configurations.
Output timing is measured at ~50% V threshold with 50 pF external capacitive load. For different loads, see Figure 1.
CC
Output Flip-Flop, Clock to Out, BUFGE #s 3, 4, 7, and 8
Speed Grade
Device
All
-3
-2
-1
-09
-08
6
Units
Description
Symbol
Min
Max
Max
Max
Max
Max
Global Early Clock to Output using
Output Flip Flop. Values are for BUF-
GE #s 3, 4, 7, and 8.
TICKEOF XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
1.3
1.5
1.6
1.6
1.7
1.7
1.8
1.9
2.0
2.0
2.2
7.8
8.1
8.5
8.8
9.1
9.4
9.7
10.1
10.5
10.9
11.8
6.8
7.1
7.4
7.6
7.9
8.2
8.5
8.8
9.1
9.5
10.3
5.9
6.5
6.6
6.7
7.2
7.2
7.5
7.8
8.1
8.6
9.3
5.3
6.1
6.3
6.4
6.8
6.9
7.2
7.3
7.9
8.1
8.8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5.7
6.4
7.3
Notes: Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is
measured using the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all
accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined
by the static timing analyzer (TRCE) can be added to the AC parameter Tokpof and used as a worst-case pin-to-pin
clock-to-out delay for clocked outputs for FAST mode configurations.
Output timing is measured at ~50% V threshold with 50 pF external capacitive load. For different loads, see Figure 1.
CC
DS005 (v. 1.8 October 18, 1999 - Product Specification
6-81
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000XL Pin-to-Pin Input Parameter Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted
Global Low Skew Clock, Set-Up and Hold
Speed Grade
Device
-3
-2
-1
-09
-08
Units
Description
Input Setup and Hold Times
No Delay
Global Low Skew Clock and IFF
Global Low Skew Clock and FCL
Symbol
Min
Min
Min
Min
Min
TPSN/TPHN XC4002XL
XC4005XL
2.5 / 1.5 2.2 / 1.3 1.9 / 1.2 1.7 / 1.0
1.2 / 2.6 1.1 / 2.2 0.9 / 2.0 0.8 / 1.7
1.2 / 3.0 1.1 / 2.6 0.9 / 2.3 0.8 / 2.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
1.2 / 3.2 1.1 / 2.8 0.9 / 2.4 0.8 / 2.1 0.8 / 2.1
1.2 / 3.7 1.1 / 3.2 0.9 / 2.8 0.8 / 2.4
1.2 / 4.4 1.1 / 3.8 0.9 / 3.3 0.8 / 2.9
1.2 / 5.5 1.1 / 4.8 0.9 / 4.1 0.8 / 3.6 0.8 / 3.6
1.2 / 5.8 1.1 / 5.0 0.9 / 4.4 0.8 / 3.8
1.2 / 7.1 1.1 / 6.2 0.9 / 5.4 0.8 / 4.7
1.2 / 7.0 1.1 / 6.1 0.9 / 5.3 0.8 / 4.6 0.8 / 4.6
1.2 / 9.4 1.1 / 8.2 0.9 / 7.1 0.8 / 6.2
8.4 / 0.0 7.3 / 0.0 6.3 / 0.0 5.5 / 0.0
XC4085XL
Partial Delay
Global Low Skew Clock and IFF
Global Low Skew Clock and FCL
TPSP/TPHP XC4002XL
XC4005XL 10. 5 / 0.0 9.1 / 0.0 7.9 / 0.0 6.9 / 0.0
XC4010XL 11.1 / 0.0 9.7 / 0.0 8.4 / 0.0 7.3 / 0.0
XC4013XL*
XC4020XL 11.9 / 1.0 10.3 / 1.0 9.0 / 1.0 7.8 / 1.0
XC4028XL 12.3 / 1.0 10.7 / 1.0 9.3 / 1.0 8.1 / 1.0
XC4036XL*
XC4044XL 13.1 / 1.0 11.4 / 1.0 9.9 / 1.0 8.6 / 1.0
XC4052XL 11.9 / 1.0 10.3 / 1.0 9.0 / 1.0 7.8 / 1.0
XC4062XL*
6.1 / 1.0 5.3 / 1.0 4.6 / 1.0 4.0 / 1.0 3.7 / 0.5
6.4 / 1.0 5.6 / 1.0 4.8 / 1.0 4.2 / 1.0 4.0/ 0.8
6.7 / 1.2 5.8 / 1.2 5.1 / 1.2 4.4 / 1.2 4.2/ 1.0
XC4085XL 12.9 / 1.2 11.2 / 1.2 9.8 / 1.2 8.5 / 1.2
Full Delay
Global Low Skew Clock and IFF
T
PSD/TPHD XC4002XL
6.8 / 0.0 6.0 / 0.0 5.2 / 0.0 4.5 / 0.0
8.8 / 0.0 7.6 / 0.0 6.6 / 0.0 5.6 / 0.0
9.0 / 0.0 7.8 / 0.0 6.8 / 0.0 5.8 / 0.0
6.4 / 0.0 6.0 / 0.0 5.6 / 0.0 4.8 / 0.0 4.8 / 0.0
8.8 / 0.0 7.6 / 0.0 6.6 / 0.0 6.2 / 0.0
9.3 / 0.0 8.1 / 0.0 7.0 / 0.0 6.4 / 0.0
6.6 / 0.0 6.2 / 0.0 5.8 / 0.0 5.3 / 0.0 5.3 / 0.0
XC4005XL
XC4010XL
XC4013XL*
XC4020XL
XC4028XL
XC4036XL*
XC4044XL 10.6 / 0.0 9.2 / 0.0 8.0 / 0.0 6.8 / 0.0
XC4052XL 11.2 / 0.0 9.7 / 0.0 8.4 / 0.0 7.0 / 0.0
XC4062XL*
6.8 / 0.0 6.4 / 0.0 6.0 / 0.0 5.5 / 0.0 5.5 / 0.0
XC4085XL 12.7 / 0.0 11.0 / 0.0 9.6 / 0.0 8.4 / 0.0
IFF = Input Flip-Flop or Latch
* The XC4013XL, XC4036XL, and 4062XL have significantly faster partial and full delay setup times than other devices.
Notes: Input setup time is measured with the fastest route and the lightest load.
Input hold time is measured using the furthest distance and a reference load of one clock pin per IOB as well as driving all
accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined
by the static timing analyzer (TRCE) can be used as a worst-case pin-to-pin no-delay input hold specification.
6-82
DS005 (v. 1.8 October 18, 1999 - Product Specification
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Global Early Clock BUFGEs 1, 2, 5, and 6 Set-up and Hold for IFF and FCL
Speed Grade
Device
-3
-2
-1
-09
-08
Units
Description
Input Setup and Hold
Times
Symbol
Min
Min
Min
Min
Min
No Delay
XC4002XL 2.8 / 1.5 2.5 / 1.3 2.2 / 1.2 1.9 / 1.0
XC4005XL 1.2 / 4.1 1.1 / 3.6 0.9 / 3.1 0.8 / 2.7
TPFSEN/TPFHEN XC4010XL 1.2 / 4.4 1.1 / 3.8 0.9 / 3.3 0.8 / 2.9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Global Early Clock and IFF TPSEN/TPHEN
Global Early Clock and
FCL
XC4013XL 1.2 / 4.7 1.1 / 4.1 0.9 / 3.6 0.8 / 3.1 0.5 / 2.7
XC4020XL 1.2 / 4.6 1.1 / 4.0 0.9 / 3.5 0.8 / 3.0
XC4028XL 1.2 / 5.3 1.1 / 4.6 0.9 / 4.0 0.8 / 3.5
XC4036XL 1.2 / 6.7 1.1 / 5.8 0.9 / 5.1 0.8 / 4.4 0.5 / 3.7
XC4044XL 1.2 / 6.5 1.1 / 5.7 0.9 / 4.9 0.8 / 4.3
XC4052XL 1.2 / 6.7 1.1 / 5.8 0.9 / 5.1 0.8 / 4.4
XC4062XL 1.2 / 8.4 1.1 / 7.3 0.9 / 6.3 0.8 / 5.5 0.5 / 4.7
XC4085XL 1.2 / 8.7 1.1 / 7.5 0.9 / 6.6 0.8 / 5.7
XC4002XL 8.1 / 0.9 7.0 / 0.8 6.1 / 0.7 5.3 / 0.6
XC4005XL 9.0 / 0.0 8.5 / 0.0 8.0 / 0.0 7.5 / 0.0
Partial Delay
Global Early Clock and IFF TPSEP/TPHEP
Global Early Clock and
FCL
TPFSEP/TPFHEP XC4010XL 11.9 / 0.0 10.4 / 0.0 9.0 / 0.0 8.0 / 0.0
XC4013XL* 6.4 / 0.0 5.9 / 0.0 5.4 / 0.0 4.9 / 0.0 4.4 / 0.0
XC4020XL 10.8 / 0.0 10.3 / 0.0 9.8 / 0.0 9.0 / 0.0
XC4028XL 14.0 / 0.0 12.2 / 0.0 10.6 / 0.0 9.8 / 0.0
XC4036XL* 7.0 / 0.0 6.6 / 0.0 6.2 / 0.0 5.2 / 0.0 4.7 / 0.0
XC4044XL 14.6 / 0.0 12.7 / 0.0 11.0 / 0.0 10.8 / 0.0
XC4052XL 16.4 / 0.0 14.3 / 0.0 12.4 / 0.0 11.4 / 0.0
XC4062XL* 9.0 / 0.8 8.6 / 0.8 8.2 / 0.8 7.0 / 0.8 6.3 / 0.5
XC4085XL 16.7 / 0.0 14.5 / 0.0 12.6 / 0.0 11.6 / 0.0
XC4002XL 6.7 / 0.0 5.8 / 0.0 5.1 / 0.0 4.4 / 0.0
6
Full Delay
Global Early Clock and IFF TPSED/TPHED
XC4005XL 10.8 / 0.0 9.4 / 0.0 8.2 / 0.0 7.1 / 0.0
XC4010XL 10.3 / 0.0 9.0 / 0.0 7.8 / 0.0 6.8 / 0.0
XC4013XL* 10.0 / 0.0 8.7 / 0.0 7.6 / 0.0 6.6 / 0.0 6.0 / 0.0
XC4020XL 12.0 / 0.0 10.4 / 0.0 9.1 / 0.0 7.9 / 0.0
XC4028XL 12.6 / 0.0 11.0 / 0.0 9.5 / 0.0 8.3 / 0.0
XC4036XL* 12.2 / 0.0 10.6 / 0.0 9.2 / 0.0 8.0 / 0.0 7.2 / 0.0
XC4044XL 13.8 / 0.0 12.0 / 0.0 10.5 / 0.0 9.1 / 0.0
XC4052XL 14.1 / 0.0 12.3 / 0.0 10.7 / 0.0 9.3 / 0.0
XC4062XL* 13.1 / 0.0 11.4 / 0.0 9.9 / 0.0 8.6 / 0.0 7.8 / 0.0
XC4085XL 17.9 / 0.0 15.6 / 0.0 13.6 / 0.0 11.8 / 0.0
IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch
* The XC4013XL, XC4036XL, and 4062XL have significantly faster partial and full delay setup times than other devices.
Notes: Input setup time is measured with the fastest route and the lightest load.
Input hold time is measured using the furthest distance and a reference load of one clock pin per IOB as well as driving all
accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined
by the static timing analyzer (TRCE) can be used as a worst-case pin-to-pin no-delay input hold specification.
DS005 (v. 1.8 October 18, 1999 - Product Specification
6-83
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Global Early Clock BUFGEs 3, 4, 7, and 8 Set-up and Hold for IFF and FCL
Speed Grade
Device
-3
-2
-1
-09
-08
Units
Description
Input Setup & Hold Times
No Delay
Global Early Clock and
IFF
Symbol
Min
Min
Min
Min
Min
XC4002XL 3.0 / 2.0 2.6 / 1.7 2.3 / 1.5 2.0 / 1.3
XC4005XL 1.2 / 4.1 1.1 / 3.6 0.9 / 3.1 0.8 / 2.7
TPFSEN/TPFHEN XC4010XL 1.2 / 4.4 1.1 / 3.8 0.9 / 3.3 0.8 / 2.9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TPSEN/TPHEN
Global Early Clock and
FCL
XC4013XL 1.2 / 4.7 1.1 / 4.1 0.9 / 3.6 0.8 / 3.1 0.5 / 2.7
XC4020XL 1.2 / 4.6 1.1 / 4.0 0.9 / 3.5 0.8 / 3.0
XC4028XL 1.2 / 5.3 1.1 / 4.6 0.9 / 4.0 0.8 / 3.5
XC4036XL 1.2 / 6.7 1.1 / 5.8 0.9 / 5.1 0.8 / 4.4 0.5 / 3.7
XC4044XL 1.2 / 6.5 1.1 / 5.7 0.9 / 4.9 0.8 / 4.3
XC4052XL 1.2 / 6.7 1.1 / 5.8 0.9 / 5.1 0.8 / 4.4
XC4062XL 1.2 / 8.4 1.1 / 7.3 0.9 / 6.3 0.8 / 5.5 0.5 / 4.7
XC4085XL 1.2 / 8.7 1.1 / 7.5 0.9 / 6.6 0.8 / 5.7
XC4002XL 7.3 / 1.5 6.4 / 1.3 5.5 / 1.2 4.8 / 1.0
XC4005XL 8.4 / 0.0 7.9 / 0.0 7.4 / 0.0 7.2 / 0.0
Partial Delay
Global Early Clock and
IFF
Global Early Clock and
FCL
TPSEP/TPHEP
TPFSEP/TPFHEP XC4010XL 10.3 / 0.0 9.0 / 0.0 7.8 / 0.0 7.4 / 0.0
XC4013XL* 5.4 / 0.0 4.9 / 0.0 4.4 / 0.0 4.3 / 0.0 4.0 / 0.0
XC4020XL 9.8 / 0.0 9.3 / 0.0 8.8 / 0.0 8.5 / 0.0
XC4028XL 12.7 / 0.0 11.0 / 0.0 9.6 / 0.0 9.3 / 0.0
XC4036XL* 6.4 / 0.8 5.9 / 0.8 5.4 / 0.8 5.0 / 0.8 4.6 / 0.2
XC4044XL 13.8 / 0.0 12.0 / 0.0 10.4 / 0.0 10.2 / 0.0
XC4052XL 14.5 / 0.0 12.7 / 0.0 11.0 / 0.0 10.7 / 0.0
XC4062XL* 8.4 / 1.5 7.9 / 1.5 7.4 / 1.5 6.8 / 1.5 6.2 / 0.0
XC4085XL 14.5 / 0.0 12.7 / 0.0 11.0 / 0.0 10.8 / 0.0
XC4002XL 5.9 / 0.0 5.2 / 0.0 4.5 / 0.0 3.9 / 0.0
Full Delay
Global Early Clock and
IFF
T
PSED/TPHED
XC4005XL 10.8 / 0.0 9.4 / 0.0 8.2 / 0.0 7.1 / 0.0
XC4010XL 10.3 / 0.0 9.0 / 0.0 7.8 / 0.0 6.8 / 0.0
XC4013XL* 10.0 / 0.0 8.7 / 0.0 7.6 / 0.0 6.6 / 0.0 6.0 / 0.0
XC4020XL 12.0 / 0.0 10.4 / 0.0 9.1 / 0.0 7.9 / 0.0
XC4028XL 12.6 / 0.0 11.0 / 0.0 9.5 / 0.0 8.3 / 0.0
XC4036XL* 12.2 / 0.0 10.6 / 0.0 9.2 / 0.0 8.0 / 0.0 7.2 / 0.0
XC4044XL 13.8 / 0.0 12.0 / 0.0 10.5 / 0.0 9.1 / 0.0
XC4052XL 14.1 / 0.0 12.3 / 0.0 10.7 / 0.0 9.3 / 0.0
XC4062XL* 13.1 / 0.0 11.4 / 0.0 9.9 / 0.0 8.6 / 0.0 7.8 / 0.0
XC4085XL 17.9 / 0.0 15.6 / 0.0 13.6 / 0.0 11.8 / 0.0
* The XC4013XL, XC4036XL, and 4062XL have significantly faster partial and full delay setup times than other devices.
IFF = Input Flip Flop or Latch. FCL = Fast Capture Latch
Notes: Input setup time is measured with the fastest route and the lightest load.
Input hold time is measured using the furthest distance and a reference load of one clock pin per IOB as well as driving all
accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined
by the static timing analyzer (TRCE) can be used as a worst-case pin-to-pin no-delay input hold specification.
6-84
DS005 (v. 1.8 October 18, 1999 - Product Specification
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000XL IOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature).
Speed Grade
Device
-3
-2
-1
-09
-08
Units
Description
Symbol
Min
Min
Min
Min
Min
Clocks
Clock Enable (EC) to Clock (IK)
T
T
All devices
0.1
0.1
0.1
0.1
0.1
1.6
ns
ECIK
Delay from FCL enable (OK) active edge to
IFF clock (IK) active edge
XC4002XL
XC4013, 36, 62XL
Balance of Family
3.0
2.2
2.2
2.7
1.9
1.9
2.3
1.6
1.6
2.3
1.6
1.6
ns
ns
ns
OKIK
Setup Times
Pad to Clock (IK), no delay
T
XC4002XL
XC4013, 36, 62XL
Balance of Family
2.6
1.7
1.7
2.3
1.5
1.5
2.0
1.3
1.3
2.0
1.3
1.3
ns
ns
ns
PICK
1.2
Pad to Clock (IK), via transparent Fast Cap-
ture Latch, no delay
T
XC4002XL
XC4013, 36, 62XL
Balance of Family
3.2
2.3
2.3
2.9
2.0
2.0
2.5
1.8
1.8
2.4
1.7
1.7
ns
ns
ns
PICKF
1.6
0.9
Pad to Fast Capture Latch Enable (OK), no
delay
T
XC4013, 36, 62XL
Balance of Family
1.2
1.2
1.0
1.0
0.9
0.9
0.9
0.9
ns
ns
POCK
Hold Times
All Hold Times
All Devices
All devices
0
0
0
0
0
6
Global Set/Reset
Minimum GSR Pulse Width
Global Set/Reset
T
19.8
Max
17.3
Max
15.0
Max
14.0
Max
14.0
Max
ns
MRW
Delay from GSR input to any Q
T
XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
9.8
8.5
9.8
7.4
8.5
7.0
8.1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RRI*
11.3
13.9
15.9
18.6
20.5
22.5
25.1
27.2
29.1
34.4
12.1
13.8
16.1
17.9
19.6
21.9
23.6
25.3
29.9
10.5
12.0
14.0
15.5
17.0
19.0
20.5
22.0
26.0
10.0
11.4
13.3
14.3
16.2
18.1
19.5
20.9
24.7
10.9
16.2
20.4
Propagation Delays
Pad to I1, I2
TPID
TPLI
All devices
XC4002XL
XC4013, 36, 62XL
Balance of Family
X4002XL
XC4013, 36, 62XL
Balance of Family
All devices
All devices
XC4002XL
XC4013, 36, 62XL
Balance of Family
1.6
4.7
3.1
3.1
5.4
3.7
3.7
1.7
1.8
5.2
3.6
3.6
1.4
4.2
2.7
2.7
4.7
3.3
3.3
1.5
1.6
4.6
3.1
3.1
1.2
3.6
2.4
2.4
4.1
2.8
2.8
1.3
1.4
4.0
2.7
2.7
1.1
3.5
2.2
2.2
3.9
2.7
2.7
1.2
1.3
3.8
2.6
2.6
1.0
2.1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Pad to I1, I2 via transparent input latch,
no delay
Pad to I1, I2 via transparent FCL and in- TPFLI
put latch, no delay
2.5
Clock (IK) to I1, I2 (flip-flop)
Clock (IK) to I1, I2 (latch enable, active
Low)
FCL Enable (OK) active edge to I1, I2
(via transparent standard input latch)
TIKRI
TIKLI
TOKLI
1.2
1.3
2.5
IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch
* Indicates Minimum Amount of Time to Assure Valid Data.
DS005 (v. 1.8 October 18, 1999 - Product Specification
6-85
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000XL IOB Output Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). For Propagation Delays, slew-rate = fast unless
otherwise noted. Values are expressed in nanoseconds unless otherwise noted.
-3
-2
-1
-09
-08
Description
Symbol Min Max Min Max Min Max Min Max Min Max
Clocks
Clock High
Clock Low
TCH
TCL
3.0
3.0
2.8
2.8
2.5
2.5
2.3
2.3
2.1
2.1
Propagation Delays
Clock (OK) to Pad
Output (O) to Pad
3-state to Pad hi-Z (slew-rate independent) TTSHZ
3-state to Pad active and valid
Output (O) to Pad via Fast Output MUX
Select (OK) to Pad via Fast MUX
TOKPOF
TOPF
5.0
4.1
4.0
4.4
5.5
5.1
4.3
3.6
3.5
3.8
4.8
4.5
3.8
3.1
3.0
3.3
4.2
3.9
3.5
3.0
2.9
3.3
4.0
3.7
3.3
2.8
2.9
3.3
3.7
3.4
TTSONF
TOFPF
TOKFPF
Setup and Hold Times
Output (O) to clock (OK) setup time
Output (O) to clock (OK) hold time
Clock Enable (EC) to clock (OK) setup time TECOK
Clock Enable (EC) to clock (OK) hold time TOKEC
TOOK
TOKO
0.5
0.0
0.0
0.3
0.4
0.0
0.0
0.2
0.3
0.0
0.0
0.1
0.3
0.0
0.0
0.0
0.3
0.0
0.0
0.0
Global Set/Reset
Minimum GSR pulse width
Delay from GSR input to any Pad
XC4002XL
TMRW
TRPO*
19.8
17.3
15.0
14.0
14.0
14.3
15.9
18.5
20.5
23.2
25.1
27.1
29.7
31.7
33.7
39.0
12.5
13.8
16.1
17.8
20.1
21.9
23.6
25.9
27.6
29.3
33.9
10.9
12.0
14.0
15.5
17.5
19.0
20.5
22.5
24.0
25.5
29.5
10.3
11.4
13.3
14.7
16.6
17.6
19.4
21.4
22.8
24.2
28.0
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
14.0
19.3
23.5
XC4062XL
XC4085XL
Slew Rate Adjustment
For output SLOW option add
TSLOW
3.0
2.5
2.0
1.7
1.6
Note: Output timing is measured at ~50% V threshold, with 50 pF external capacitive loads.
CC
* Indicates Minimum Amount of Time to Assure Valid Data.
6-86
DS005 (v. 1.8 October 18, 1999 - Product Specification
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Revision Control
Version
Nature of Changes
2/1/99 (1.5) Release included in the 1999 data book, section 6
5/14/99 (1.6) Replaced Electrical Specification and pinout pages for E, EX, and XL families with separate updates and
added URL link on placeholder page for electrical specifications/pinouts for WebLINX users
9/30/99 (1.7) Added Power-on specification.
10/18/99 (1.8) Corrected posted file to include missing page (IOB Output Parameters).
6
DS005 (v. 1.8 October 18, 1999 - Product Specification
6-87
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-88
DS005 (v. 1.8 October 18, 1999 - Product Specification
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