XC4013E-4CBG228M [XILINX]
Field Programmable Gate Array, 576 CLBs, 10000 Gates, 111MHz, CMOS, CQFP228, CERAMIC, QFP-228;
| 型号： | XC4013E-4CBG228M |
| 厂家： | 
XILINX, INC |
| 描述： | Field Programmable Gate Array, 576 CLBs, 10000 Gates, 111MHz, CMOS, CQFP228, CERAMIC, QFP-228 栅 |
| 文件： | 总23页 (文件大小：138K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0
XC4000E High-Reliability
Field Programmable Gate Arrays
0
8*
November 21, 1997 (Version 1.3)
Product Specification
-
-
Program verification
Internal node observability
XC4000E High-Reliability Features
•
System featured Field-Programmable Gate Arrays
-
•
•
Backward Compatible with XC4000 Devices
Development System runs on most common computer
platforms
-
-
-
Available in class Q fully compliant QML and Military
temperature range only
-
Select-RAMTM memory: on-chip ultra-fast RAM with
-
-
synchronous write option
dual-port RAM option
Interfaces to popular design environments
Fully automatic mapping, placement and routing
Interactive design editor for design optimization
-
-
-
-
-
-
-
Abundant flip-flops
Flexible function generators
Dedicated high-speed carry logic
Wide edge decoders on each edge
Hierarchy of interconnect lines
Internal 3-state bus capability
8 global low-skew clock or signal distribution
networks
•
Certified to MIL-PRF-38535, appendix A QML
(Qualified Manufacturers Listing)
•
•
•
•
System Performance beyond 60 MHz
Flexible Array Architecture
Low Power Segmented Routing Architecture
Systems-Oriented Features
Xilinx High-Reliability
XC4000E family is supplied under the following standard
microcircuit drawings (SMDs):
-
IEEE 1149.1-compatible boundary scan logic
support
Individually programmable output slew rate
Programmable input pull-up or pull-down resistors
12-mA sink current per XC4000E output
XC4005E 5962-97522
XC4010E 5962-97523
XC4013E 5962-97524
XC4025E 5962-97525
For more information contact DSCC (Defense Supply Cen-
ter Columbus) Columbus, Ohio.
-
-
-
•
•
Configured by Loading Binary File
Unlimited reprogrammability
Readback Capability
-
Table 1: XC4000E Field Programmable Gate Arrays
Max.
Logic
Gates
Typical
Max. RAM Gate Range
Max.
Decode
Inputs
Number
of
Bits
(Logic and
RAM)*
CLB
Total
Max.
Device
(No RAM) (No Logic)
Matrix CLBs Flip-Flops per side User I/O Packages
XC4005E
5,000
10,000
13,000
25,000
6,272
12,800
18,432
32,768
3,000 - 9,000 14 x 14
196
400
576
616
42
60
72
96
112
160
192
256
PG156,
CB164
XC4010E
XC4013E
XC4025E
7,000 - 20,000 20 x 20
1,120
1,536
2,560
PG191,
CB196
10,000 -
30,000
24 x 24
PG223,
CB228
15,000 -
45,000
32 x 32 1,024
PG299,
CB228
*
Max values of Typical Gate Range include 20-30% of CLBs used as RAM.
November 21, 1997 (Version 1.3)
8-11
XC4000E High-Reliability Field Programmable Gate Arrays
XC4000E Switching Characteristics
XC4000E Absolute Maximum Ratings
Symbol
VCC
Description
Value
-0.5 to +7.0
-0.5 to VCC +0.5
-0.5 to VCC +0.5
-65 to +150
+260
Units
V
Supply voltage relative to GND
VIN
Input voltage relative to GND (Note 1)
V
VTS
TSTG
TSOL
TJ
Voltage applied to 3-state output (Note 1)
Storage temperature (ambient)
V
°C
°C
°C
Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm)
Junction temperature
Ceramic packages
+150
Note 1:
Maximum DC overshoot or undershoot above Vcc or below GND must be limited to either 0.5 V or 10 mA, whichever is
easier to achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to Vcc + 2.0 V, provided this
over- or undershoot lasts less than 20 ns.
Note 2:
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may
affect device reliability.
XC4000E Recommended Operating Conditions
Symbol
VCC
Description
Supply voltage relative to GND, TC = -55°C to +125°C
High-level input voltage
Min
4.5
2.0
0
Max
5.5
Units
V
VIH
VIL
TIN
TTL inputs
TTL inputs
VCC
0.8
V
Low-level input voltage
V
Input signal transition time
250
ns
Note:
At case temperatures above those listed as Recommended Operating Conditions, all delay parameters increase by 0.35%
per °C.
Input and output Measurement thresholds are: 1.5V for TTL and 2.5V for CMOS.
All specifications are subject to change without notice.
8-12
November 21, 1997 (Version 1.3)
XC4000E DC Characteristics Over Operating Conditions
Symbol
VOH
Description
Min
Max
Units
V
High-level output voltage @ IOH = -4.0mA, VCC min
TTL outputs
2.4
VOL
ICCO
IL
Low-level output voltage @ IOL = 12.0mA, VCC min (Note 1) TTL outputs
Quiescent FPGA supply current (Note 2)
0.4
50
V
mA
µA
pF
Input or output leakage current
-10
+10
16
CIN
Input capacitance (sample tested)
IRIN*
IRLL*
Pad pull-up (when selected) @ VIN = 0V (sample tested)
Horizontal Longline pull-up (when selected) @ logic Low
-0.02
0.2
-0.25
2.5
mA
mA
Note 1:
Note 2:
With 50% of the outputs simultaneously sinking 12mA, up to a maximum of 64 pins.
With no output current loads, no active input or Longline pull-up resistors, all package pins at Vcc or GND, and the FPGA
configured with the development system Tie option.
Characterized Only.
*
XC4000E Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven
from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data, reflecting
the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System)
and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static
timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction
temperature)
Speed Grade
Device
-4
Units
Description
From pad through
Primary buffer,
to any clock K
Symbol
Max
TPG
XC4005E
XC4010E
XC4013E
XC4025E
7.0
ns
ns
ns
ns
11.0
11.5
12.5
From pad through
Secondary buffer,
to any clock K
TSG
XC4005E
XC4010E
XC4013E
XC4025E
7.5
ns
ns
ns
ns
11.5
12.0
13.0
November 21, 1997 (Version 1.3)
8-13
XC4000E High-Reliability Field Programmable Gate Arrays
XC4000E Horizontal Longline Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless
otherwise noted.
The following guidelines reflect worst-case values over the recommended operating conditions.
Speed Grade
Device
-4
Units
Description
Symbol
Max
TBUF driving a Horizontal Longline (LL):
XC4005E
XC4010E
XC4013E
XC4025E
5.0
8.0
9.0
ns
ns
ns
ns
I going High or Low to LL going High or Low, while T is Low.
Buffer is constantly active. (Note1)
TIO1
11.0
XC4005E
XC4010E
XC4013E
XC4025E
6.0
ns
ns
ns
ns
I going Low to LL going from resistive pull-up High to active Low.
TBUF configured as open-drain. (Note1)
TIO2
10.5
11.0
12.0
XC4005E
XC4010E
XC4013E
XC4025E
7.0
8.5
8.7
ns
ns
ns
ns
T going Low to LL going from resistive pull-up or floating High to active Low.
TBUF configured as open-drain or active buffer with I = Low.
(Note1)
TON
11.0
XC4005E
XC4010E
XC4013E
XC4025E
1.8
3.0
3.5
4.0
ns
ns
ns
ns
T going High to TBUF going inactive, not driving LL
TOFF
TPUS
TPUF
XC4005E
XC4010E
XC4013E
XC4025E
23.0
29.0
32.0
42.0
ns
ns
ns
ns
T going High to LL going from Low to High, pulled up by a single resistor.
(Note 1)
XC4005E
XC4010E
XC4013E
XC4025E
10.0
13.5
15.0
18.0
ns
ns
ns
ns
T going High to LL going from Low to High, pulled up by two resistors.
(Note1)
Note 1:
These values include a minimum load. Use the static timing analyzer to determine the delay for each destination.
8-14
November 21, 1997 (Version 1.3)
XC4000E Wide Decoder Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless
otherwise noted.
The following guidelines reflect worst-case values over the recommended operating conditions.
Speed Grade
Device
-4
Units
Description
Symbol
Max
Full length, both pull-ups,
inputs from IOB I-pins
TWAF
XC4005E
XC4010E
XC4013E
XC4025E
9.5
ns
ns
ns
ns
15.0
16.0
18.0
Full length, both pull-ups,
inputs from internal logic
TWAFL
XC4005E
XC4010E
XC4013E
XC4025E
12.5
18.0
19.0
21.0
ns
ns
ns
ns
Half length, one pull-up,
inputs from IOB I-pins
TWAO
XC4005E
XC4010E
XC4013E
XC4025E
10.5
16.0
17.0
19.0
ns
ns
ns
ns
Half length, one pull-up,
inputs from internal logic
TWAOL
XC4005E
XC4010E
XC4013E
XC4025E
12.5
18.0
19.0
21.0
ns
ns
ns
ns
Notes: These delays are specified from the decoder input to the decoder output.
Fewer than the specified number of pullup resistors can be used, if desired. Using fewer pullups reduces power consumption
but increases delays. Use the static timing analyzer to determine delays if fewer pullups are used.
November 21, 1997 (Version 1.3)
8-15
XC4000E High-Reliability Field Programmable Gate Arrays
XC4000E CLB Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless
otherwise noted.
Speed Grade
Symbol
-4
Units
Description
Min
Max
Combinatorial Delays
F/G inputs to X/Y outputs
F/G inputs via H to X/Y outputs
C inputs via H to X/Y outputs
TILO
TIHO
THH1O
3.9
5.9
4.9
ns
ns
ns
CLB Fast Carry Logic
Operand inputs (F1, F2, G1, G4) to COUT
Add/Subtract input (F3) to COUT
Initialization inputs (F1, F3) to COUT
CIN through function generators to X/Y outputs
CIN to COUT, bypass function generators
TOPCY
TASCY
TINCY
TSUM
TBYP
4.4
6.8
2.9
5.0
1.0
ns
ns
ns
ns
ns
Sequential Delays
Clock K to outputs Q
TCKO
5.0
ns
Setup Time before Clock K
F/G inputs
F/G inputs via H
C inputs via H1 through H
C inputs via H2 through H
C inputs via DIN
TICK
TIHCK
THH1CK
THH2CK
TDICK
4.0
6.1
5.0
4.8
3.0
4.0
4.2
ns
ns
ns
ns
ns
ns
ns
C inputs via EC
C inputs via S/R, going Low (inactive)
TECCK
TRCK
8-16
November 21, 1997 (Version 1.3)
XC4000E CLB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to-
date information, use the values provided by the static timing analyzer and used in the simulator.
The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units
of nanoseconds and apply to all XC4000E devices unless otherwise noted.
Speed Grade
Device
-4
Units
Description
Hold Time after Clock K
Symbol
Min
Max
F/G inputs
F/G inputs via H
C inputs via H1 through H
C inputs via DIN
C inputs via EC
TCKI
TCKIH
TCKHH1
TCKDI
TCKEC
TCKR
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
C inputs via SR, going Low (inactive)
Clock
Clock High time
Clock Low time
TCH
TCL
4.5
4.5
ns
ns
Set/Reset Direct
Width (High)
Delay from C inputs via S/R, going High to Q
TRPW
TRIO
5.5
ns
ns
6.5
Master Set/Reset
Width (High or Low)
TMRW
4005E
4010E
4013E
4025E
4005E
4010E
4013E
4025E
13.0
55.0
70.0
ns
ns
ns
ns
ns
ns
ns
ns
112.0
Delay from Global Set/Reset net to Q
TMRQ
23.0
60.0
77.0
134.0
November 21, 1997 (Version 1.3)
8-17
XC4000E High-Reliability Field Programmable Gate Arrays
XC4000E CLB Edge-Triggered (Synchronous) RAM Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested.
Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more
precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and
back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction
temperature). Values apply to all XC4000E devices unless otherwise noted.
Speed Grade
Size Symbol
-4
Single Port RAM
Units
Min
Max
Write Operation
Address write cycle time (clock K period)
16x2
32x1
TWCS
TWCTS
15.0
15.0
ns
ns
Clock K pulse width (active edge)
Address setup time before clock K
Address hold time after clock K
DIN setup time before clock K
DIN hold time after clock K
WE setup time before clock K
WE hold time after clock K
16x2
32x1
TWPS
TWPTS
7.5
7.5
1 ms
1 ms
ns
ns
16x2
32x1
TASS
TASTS
2.8
2.8
ns
ns
16x2
32x1
TAHS
TAHTS
0
0
ns
ns
16x2
32x1
TDSS
TDSTS
3.5
2.5
ns
ns
16x2
32x1
TDHS
TDHTS
0
0
ns
ns
16x2
32x1
TWSS
TWSTS
2.2
2.2
ns
ns
16x2
32x1
TWHS
TWHTS
0
0
ns
ns
Data valid after clock K
16x2
32x1
TWOS
TWOTS
10.3
11.6
ns
ns
Notes:
Timing for the 16x1 RAM option is identical to 16x2 RAM timing.
Applicable Read timing specifications are identical to Level-Sensitive Read timing.
Speed Grade
-4
Dual-Port RAM
Units
Size
Symbol
Min
Max
Write Operation
Address write cycle time (clock K period)
Clock K pulse width (active edge)
Address setup time before clock K
Address hold time after clock K
DIN setup time before clock K
DIN hold time after clock K
WE setup time before clock K
WE hold time after clock K
Data valid after clock K
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
TWCDS
15.0
7.5
2.8
0
2.2
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
TWPDS
TASDS
TAHDS
TDSDS
TDHDS
TWSDS
TWHDS
TWODS
1 ms
2.2
0.3
10.0
Note: Applicable Read timing specifications are identical to Level-Sensitive Read timing.
8-18
November 21, 1997 (Version 1.3)
XC4000E CLB RAM Synchronous (Edge-Triggered) Write Timing
TWPS
WCLK (K)
TWHS
TDHS
TAHS
TWSS
WE
TDSS
DATA IN
TASS
ADDRESS
DATA OUT
TILO
TILO
TWOS
OLD
NEW
X6461
XC4000E CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing
TWPDS
WCLK (K)
TWHDS
TWSDS
WE
TDHDS
TDSDS
DATA IN
TASDS
TAHDS
ADDRESS
DATA OUT
TILO
TILO
TWODS
OLD
NEW
X6474
November 21, 1997 (Version 1.3)
8-19
XC4000E High-Reliability Field Programmable Gate Arrays
XC4000E CLB Level-Sensitive RAM Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
XC4000E devices unless otherwise noted.
Speed Grade
Symbol
-4
Units
Description
Size
Min
Max
Write Operation
Address write cycle time
16x2
32x1
TWC
TWCT
8.0
8.0
ns
ns
Write Enable pulse width (High)
Address setup time before WE
Address hold time after end of WE
DIN setup time before end of WE
DIN hold time after end of WE
16x2
32x1
TWP
TWPT
4.0
4.0
ns
ns
16x2
32x1
TAS
TAST
2.0
2.0
ns
ns
16x2
32x1
TAH
TAHT
2.5
2.0
ns
ns
16x2
32x1
TDS
TDST
4.0
5.0
ns
ns
16x2
32x1
TDH
TDHT
2.0
2.0
ns
ns
Read Operation
Address read cycle time
16x2
32x1
TRC
TRCT
4.5
6.5
ns
ns
Data valid after address change
(no Write Enable)
16x2
32x1
TILO
TIHO
3.9
5.9
ns
ns
Read Operation, Clocking Data into Flip-Flop
Address setup time before clock K
16x2
32x1
TICK
TIHCK
4.0
6.1
ns
ns
Read During Write
Data valid after WE goes active (DIN stable before WE)
16x2
32x1
TWO
TWOT
10.0
12.0
ns
ns
Data valid after DIN
16x2
32x1
TDO
TDOT
9.0
11.0
ns
ns
(DIN changes during WE)
Read During Write, Clocking Data into Flip-Flop
WE setup time before clock K
16x2
32x1
TWCK
TWCKT
8.0
9.6
ns
ns
Data setup time before clock K
16x2
32x1
TDCK
TDCKT
7.0
8.0
ns
ns
Note: Timing for the 16x1 RAM option is identical to 16x2 RAM timing.
8-20
November 21, 1997 (Version 1.3)
XC4000E CLB Level-Sensitive RAM Timing Characteristics
T
WC
ADDRESS
WRITE
T
AS
T
T
WP
AH
T
WRITE ENABLE
DATA IN
T
DH
DS
REQUIRED
READ WITHOUT WRITE
T
ILO
X,Y OUTPUTS
VALID
VALID
READ, CLOCKING DATA INTO FLIP-FLOP
T
T
CH
ICK
CLOCK
T
CKO
VALID
(OLD)
VALID
(NEW)
XQ, YQ OUTPUTS
READ DURING WRITE
T
WP
WRITE ENABLE
T
DH
DATA IN
(stable during WE)
T
WO
X, Y OUTPUTS
VALID
VALID
DATA IN
(changing during WE)
OLD
NEW
T
T
DO
WO
VALID
VALID
(OLD)
VALID
(NEW)
X, Y OUTPUTS
(PREVIOUS)
READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP
T
WP
WRITE ENABLE
T
WCK
T
DCK
DATA IN
CLOCK
T
CKO
XQ, YQ OUTPUTS
X2640
November 21, 1997 (Version 1.3)
8-21
XC4000E High-Reliability Field Programmable Gate Arrays
XC4000E Guaranteed Input and Output Parameters (Pin-to-Pin, TTL I/O)
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report. Values apply to all XC4000E devices unless otherwise noted.
Speed Grade
Device
-4
Units
Description
Global Clock to Output
(fast) using OFF
Symbol
XC4005E
XC4010E
XC4013E
XC4025E
14.0
16.0
16.5
17.0
ns
ns
ns
ns
TICKOF
.
.
.
.
.
(Max)
T
OFF
PG
Global Clock-to-Output Delay
X3202
XC4005E
XC4010E
XC4013E
XC4025E
18.0
20.0
20.5
21.0
ns
ns
ns
ns
Global Clock to Output
(slew-limited) using OFF
TICKO
(Max)
.
.
.
.
.
T
OFF
PG
Global Clock-to-Output Delay
X3202
XC4005E
XC4010E
XC4013E
XC4025E
2.0
1.9
1.6
1.5
ns
ns
ns
ns
Input Setup Time, using IFF
(no delay)
TPSUF
(Min)
D
Input
Set - Up
IFF
IFF
IFF
IFF
&
Hold
Time
T
PG
X3201
XC4005E
XC4010E
XC4013E
XC4025E
4.6
6.0
7.0
8.0
ns
ns
ns
ns
Input Hold Time, using IFF
(no delay)
TPHF
(Min)
D
D
D
Input
Set - Up
&
Hold
Time
T
PG
X3201
X3201
X3201
XC4005E
XC4010E
XC4013E
XC4025E
8.5
8.5
8.5
9.5
ns
ns
ns
ns
ns
ns
ns
ns
Input Setup Time, using IFF
(with delay)
TPSU
(Min)
Input
Set - Up
&
Hold
Time
T
PG
XC4005E
XC4010E
XC4013E
XC4025E
0
0
0
0
ns
ns
ns
ns
Input Hold Time, using IFF
(with delay)
TPH
(Min)
Input
Set - Up
&
Hold
Time
T
PG
OFF = Output Flip-Flop
IFF = Input Flip-Flop or Latch
8-22
November 21, 1997 (Version 1.3)
XC4000E IOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report. Values apply to all XC4000E devices unless otherwise noted.
Speed Grade
Device
-4
Units
Description
Symbol
Min
Max
Propagation Delays (TTL Inputs)
Pad to I1, I2
Pad to I1, I2 via transparent latch, no delay
TPID
TPLI
TPDLI
All devices
All devices
XC4005E
XC4010E
XC4013E
XC4025E
3.0
6.0
12.0
12.2
12.6
15.0
ns
ns
ns
ns
ns
ns
with delay
Propagation Delays
Clock (IK) to I1, I2 (flip-flop)
Clock (IK) to I1, I2 (latch enable, active Low)
Hold Times (Note 1)
TIKRI
TIKLI
All devices
All devices
6.8
7.3
ns
ns
Pad to Clock (IK), no delay
with delay
TIKPI
TIKPID
All devices
All devices
0
0
ns
ns
Note 1:
Note 2:
Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to
the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-
up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
November 21, 1997 (Version 1.3)
8-23
XC4000E High-Reliability Field Programmable Gate Arrays
XC4000E IOB Input Switching Characteristic Guidelines (continued)
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless
otherwise noted.
Speed Grade
Device
-4
Units
Description
Symbol
Min
Max
Setup Times (TTL Inputs)
Pad to Clock (IK), no delay
with delay
TPICK
TPICKD
All devices
XC4005E
XC4010E
XC4013E
XC4025E
4.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
10.9
11.3
11.8
14.0
(TTL or CMOS)
Clock Enable (EC) to Clock (IK), no delay
with delay
TECIK
TECIKD
All devices
XC4005E
XC4010E
XC4013E
XC4025E
3.5
ns
ns
ns
ns
ns
10.4
10.7
11.1
14.0
Global Set/Reset (Note 3)
Delay from GSR net through Q to I1, I2
GSR width
GSR inactive to first active Clock (IK) edge
TRRI
TMRW
TRPO
XC4005E
XC4010E
XC4013E
XC4025E
XC4005E
XC4010E
XC4013E
XC4025E
XC4005E
XC4010E
XC4013E
XC4025E
12.0
21.0
23.0
29.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
13.0
55.0
70.0
112.0
15.0
20.3
22.0
28.0
Note 1:
Note 2:
Note 3:
Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to
the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-
up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
Timing is based on the XC4005E. For other devices see the static timing analyzer.
8-24
November 21, 1997 (Version 1.3)
XC4000E IOB Output Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless
otherwise noted.
Speed Grade
Symbol
-4
Units
Description
Min
Max
Propagation Delays (TTL Output Levels)
Clock (OK) to Pad, fast
slew-rate limited
Output (O) to Pad, fast
slew-rate limited
3-state to Pad hi-Z
(slew-rate independent)
3-state to Pad active
and valid, fast
TOKPOF
TOKPOS
TOPF
TOPS
TTSHZ
7.5
11.5
8.0
12.0
10.0
ns
ns
ns
ns
ns
TTSONF
TTSONS
10.0
13.7
ns
ns
slew-rate limited
Note 1:
Note 2:
Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test fixture). Slew-rate limited output
rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground
bounce, see the “Additional XC4000 Data” section of the Programmable Logic Data Book.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-
up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
November 21, 1997 (Version 1.3)
8-25
XC4000E High-Reliability Field Programmable Gate Arrays
XC4000E IOB Output Switching Characteristic Guidelines (continued)
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). For Propagation Delays, slew-rate = fast unless
otherwise noted. Values apply to all XC4000E devices unless otherwise noted.
Speed Grade
Device
-4
Units
Description
Setup and Hold
Symbol
Min
Max
Output (O) to clock (OK) setup time
Output (O) to clock (OK) hold time
TOOK
TOKO
5.0
0
ns
ns
Clock
Clock High
Clock Low
TCH
TCL
4.5
4.5
ns
ns
Note 1:
Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test fixture). Slew-rate limited output
rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground
bounce, see the “Additional XC4000 Data” section of the Programmable Logic Data Book.
Note 2:
Note 3:
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-
up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
Timing is based on the XC4005E. For other devices see the static timing analyzer.
8-26
November 21, 1997 (Version 1.3)
XC4000E High-Reliability Field Programmable Gate Arrays
November 21, 1997 (Version 1.3)
8
Device-Specific Pinout Tables
Pin Locations for XC4005E Devices
XC4005E
Pad Name
PG
156†
CB
164
Bndry
Scan
XC4005E
Pad Name
PG
156†
CB
164
Bndry
Scan
XC4005E
Pad Name
PG
156†
CB
164
Bndry
Scan
I/O (HDC)
D14
C15
D15
E14
C16
F14
F15
E16
F16
G14
G15
G16
H16
H15
H14
J14
J15
J16
K16
K15
K14
L16
M16
L15
L14
P16
M14
N15
P15
N14
R16
P14
R15
P13
R14
T16
T15
R13
P12
T14
T13
P11
R11
T11
T10
P10
R10
T9
P45
P46
P48
P49
P50
P53
P54
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
P66
P67
P68
P69
P70
P71
P72
P75
P76
P77
P78
P79
P80
P81
P82
P83
P84
P85
P86
P87
P89
P90
P91
P94
P95
P96
P97
P98
P99
P100
P101
P102
P103
P104
P105
P106
P107
P108
178
181
184
187
190
-
I/O (D2)
P7
T5
R6
T4
P6
T3
P5
P109
P110
P111
P112
P113
P115
P116
313
316
319
322
-
VCC
H3
H1
P145
P146
P147
P148
P149
P150
P151
P152
P153
P154
P157
P158
P160
P161
P162
P163
P164
P1
-
I/O
I/O
I/O (A8)
I/O (A9)
I/O
44
I/O
I/O
G1
G2
G3
F1
47
I/O
I/O
50
I/O (LDC)
GND
I/O
GND
I/O (D1)
I/O
53
325
328
I/O (A10)
I/O (A11)
I/O
56
193
196
199
202
205
208
211
214
-
I/O (RCLK,
RDY/BUSY)
F2
59
I/O
E1
62
I/O
R4
R3
P4
T2
P117
P119
P120
P121
331
334
337
340
I/O
I/O
E2
65
I/O
I/O
GND
F3
-
I/O (D0, DIN)
I/O
I/O (A12)
I/O (A13)
I/O
E3
68
I/O, SGCK4
(DOUT)
I/O
C1
71
I/O
C2
74
CCLK
R2
P3
T1
N3
R1
P2
N2
M3
P1
N1
L3
L2
L1
K3
K2
K1
J1
P122
P123
P124
P125
P126
P127
P128
P130
P131
P132
P135
P136
P137
P138
P139
P140
P141
P142
P143
P144
-
I/O (INIT)
VCC
GND
I/O
I/O
D3
77
VCC
-
I/O (A14)
I/O, SGCK1 (A15)
VCC
B1
80
O, TDO
GND
0
-
B2
83
-
217
220
223
226
229
232
235
238
-
C3
-
I/O (A0, WS)
I/O, PGCK4 (A1)
I/O
2
I/O
GND
C4
-
5
I/O
I/O, PGCK1 (A16)
I/O (A17)
I/O
B3
P2
86
8
I/O
A1
P3
89
I/O
11
14
17
-
I/O
A2
P4
92
I/O (CS1, A2)
I/O (A3)
GND
I/O
I/O
C5
P5
95
I/O
I/O, TDI
I/O, TCK
GND
B4
P7
98
I/O
A3
P8
101
-
I/O
20
23
26
29
32
35
38
41
-
GND
I/O
C6
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P26
P27
P28
P29
P30
P32
P33
P34
P35
P37
P38
P39
P40
P41
P42
P43
P44
I/O
241
244
247
250
253
256
-
I/O
B5
104
107
110
113
116
119
122
125
-
I/O (A4)
I/O (A5)
I/O
I/O
I/O
B6
I/O
I/O, TMS
I/O
A5
I/O
C7
I/O
I/O
I/O
B7
I/O (A6)
I/O (A7)
GND
J2
I/O, SGCK3
GND
DONE
VCC
PROGRAM
I/O (D7)
I/O, PGCK3
I/O
I/O
A6
J3
I/O
A7
H2
-
I/O
A8
8/13/97
-
GND
C8
-
VCC
B8
-
Additional XC4005E Package
Pins
259
262
265
268
271
274
-
I/O
C9
128
131
134
137
140
143
146
149
-
I/O
B9
PG156
I/O
A9
N.C. Pins
I/O
I/O
B10
C10
A10
A11
B11
C11
B12
A13
A14
C12
B13
B14
A15
C13
A16
C14
B15
B16
A4
D16
A12
E15
N16
-
D1
M1
R5
-
D2
M2
R12
-
I/O (D6)
I/O
I/O
I/O
M15
GND
I/O
I/O
T12
277
280
283
286
289
292
295
298
-
I/O
8/14/97
I/O
GND
I/O (D5)
I/O (CS0)
I/O
I/O
152
155
158
161
164
167
170
-
I/O
CB164
I/O
N.C. Pins
I/O
I/O
P6
P36
P9
P47
P74
P114
P134
-
P25
P51
P88
P118
P155
-
P31
P52
P92
P129
P156
-
I/O (D4)
I/O
R9
I/O
P9
I/O, SGCK2
O (M1)
GND
P73
VCC
GND
I/O (D3)
I/O (RS)
I/O
R8
P93
P8
-
P133
P159
8/14/97
T8
301
304
307
310
I (M0)
VCC
173
-
T7
T6
I (M2)
I/O, PGCK2
174
175
I/O
R7
November 21, 1997 (Version 1.3)
8-27
XC4000E High-Reliability Field Programmable Gate Arrays
Pin Locations for XC4010E Devices
XC4010E
Pad Name
PG
191†
CB
196
Bndry
Scan
XC4010E
Pad Name
PG
191†
CB
196
Bndry
Scan
XC4010E
Pad Name
PG
191†
CB
196
Bndry
Scan
I/O
I/O
I/O
I/O
I/O
B14
A16
B15
C14
A17
B16
C15
D15
A18
D16
C16
B17
E16
C17
D17
B18
E17
F16
C18
D18
F17
G16
E18
F18
G17
G18
H16
H17
H18
J18
P41
P42
P43
P44
P45
P46
P47
P48
P49
P50
P51
P52
P53
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
P66
P67
P68
P69
P70
P71
P72
P73
P74
P75
P76
P77
P78
P79
P80
P81
P82
P83
P84
P85
P86
P87
P88
P89
P90
P91
P92
P93
P94
P95
P96
P97
P98
P99
P100
P101
P102
P104
224
227
230
233
236
239
242
-
I/O
U15
V17
V16
T13
U14
V15
V14
T12
U13
V13
U12
V12
T11
U11
V11
V10
U10
T10
R10
R9
P105
P106
P107
P108
P109
P110
P111
P112
P113
P114
P115
P116
P117
P118
P119
P120
P121
P122
P123
P124
P125
P126
P127
P128
P129
P130
P131
P132
P133
P134
P135
P136
P137
P138
P139
P140
P141
376
379
382
385
388
391
394
-
VCC
J4
J3
P183
P184
P185
P186
P187
P188
P189
P190
P191
P192
P193
P194
P195
P196
P197
P198
P199
P200
P201
P202
P203
P204
P205
P1
-
I/O (D6)
I/O
I/O (A8)
62
I/O (A9)
J2
65
I/O
I/O (19)
J1
68
I/O
I/O (18)
H1
H2
H3
G1
G2
F1
71
I/O, SGCK2
O (M1)
GND
I (M0)
VCC
I (M2)
I/O, PGCK2
I/O (HDC)
I/O
I/O
I/O
74
I/O
I/O
77
GND
I/O
I/O (A10)
80
245
-
397
400
403
406
409
412
415
418
421
424
-
I/O (A11)
83
I/O
I/O
86
246
247
250
253
256
259
262
265
268
271
274
-
I/O (D5)
I/O (CS0)
I/O
I/O
E1
89
GND
G3
F2
-
I/O
92
I/O
I/O
D1
C1
E2
95
I/O
I/O
I/O
98
I/O
I/O
I/O
101
104
107
110
113
116
119
-
I/O (LDC)
I/O
I/O (D4)
I/O
I/O (A12)
F3
I/O (A13)
D2
B1
I/O
VCC
GND
I/O (D3)
I/O (RS)
I/O
I/O
I/O
-
I/O
E3
I/O
T9
427
430
433
436
439
442
445
448
451
454
-
I/O (A14)
C2
B2
GND
I/O
U9
I/O, SGCK1 (A15)
277
280
283
286
289
292
295
298
301
304
-
V9
VCC
D3
D4
C3
C4
B3
I/O
I/O
V8
GND
-
I/O
I/O
U8
I/O, PGCK1 (A16)
P2
122
125
128
131
134
137
140
143
146
149
-
I/O
I/O
T8
I/O (A17)
I/O
P3
I/O
I/O (D2)
I/O
V7
P4
I/O
U7
I/O
C5
A2
P6
I/O
I/O
V6
I/O, TDI
I/O, TCK
I/O
P7
I/O
I/O
U6
B4
P8
I/O
J17
GND
I/O
T7
C6
A3
P9
I/O (INIT)
VCC
GND
I/O
J16
V5
457
460
463
466
469
472
I/O
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P40
J15
I/O
V4
I/O
B5
K15
K16
K17
K18
L18
L17
L16
M18
M17
N18
P18
M16
N17
R18
T18
P17
N16
T17
R17
P16
U18
T16
R16
U17
R15
V18
T15
U16
T14
-
I/O
U5
I/O
B6
307
310
313
316
319
322
325
328
331
334
-
I/O
T6
GND
I/O
C7
A4
I/O
I/O (D1)
V3
152
155
158
161
164
167
170
173
176
179
-
I/O
I/O (RCLK,
RDY/BUSY)
V2
I/O
A5
I/O
I/O, TMS
I/O
B7
I/O
U4
T5
U3
T4
P142
P143
P144
P145
475
478
481
484
I/O
A6
I/O
I/O
I/O
C8
A7
I/O (D0, DIN)
I/O
I/O
I/O, SGCK4
(DOUT)
I/O
I/O
B8
I/O
I/O
A8
CCLK
V1
R4
U2
R3
T3
U1
P3
R2
T2
N3
P2
T1
R1
N2
M3
P1
N1
M2
M1
L3
P146
P147
P148
P149
P150
P151
P153
P154
P155
P156
P157
P158
P159
P160
P161
P162
P163
P164
P165
P166
-
I/O
I/O
B9
VCC
-
GND
I/O
I/O
C9
D9
D10
C10
B10
A9
O, TDO
0
337
340
343
346
349
352
355
358
361
364
-
GND
VCC
I/O
GND
-
I/O
-
I/O (A0, WS)
2
I/O
182
185
188
191
194
197
200
203
206
209
-
I/O, PGCK4 (A1)
5
I/O
I/O
I/O
8
I/O
I/O
I/O
11
14
17
20
23
26
29
-
I/O
I/O
A10
A11
C11
B11
A12
B12
A13
C12
B13
A14
A15
C13
I/O (CS1, A2)
I/O (A3)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O, SGCK3
GND
DONE
VCC
PROGRAM
I/O (D7)
I/O, PGCK3
I/O
I/O
I/O
I/O
I/O
-
I/O
GND
I/O
-
GND
I/O
32
35
38
41
44
-
212
215
218
221
I/O
367
370
373
I/O
I/O (A4)
I/O (A5)
I/O
I/O
I/O
8-28
November 21, 1997 (Version 1.3)
Additional XC4010E Package
Pins
XC4010E
Pad Name
PG
191†
CB
196
Bndry
Scan
I/O
I/O
I/O
L2
L1
K1
K2
K3
K4
P167
P168
P169
P170
P171
P172
47
50
53
56
59
-
CB196
N.C. Pins
P5
P192
P54
-
P103
-
P152
-
I/O (A6)
I/O (A7)
GND
8/14/97
8/14/97
Pin Locations for XC4013E Devices
XC4013E
Pad Name
PG
223†
CB
228
Bndry
XC4013E
Pad Name
PG
223†
CB
228
Bndry
Scan
XC4013E
Pad Name
PG
223†
CB
228
Bndry
Scan
Scan
209
212
215
-
I/O
I/O
I/O
A8
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
P66
P67
P68
P69
P70
P71
P72
P73
P74
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
G17
G18
H16
H17
G15
H15
H18
J18
J17
J16
J15
K15
K16
K17
K18
L18
L17
L16
L15
M15
-
P75
P76
337
340
343
346
349
352
355
358
361
364
-
VCC
J4
J3
P201
P202
P203
P204
P205
P206
P207
P208
P209
P210
P211
P212
P213
P214
P215
P216
P217
P218
P219
P220
P221
P222
P223
P224
P225
P226
P227
P228
P1
-
B9
I/O (A8)
74
C9
P77
I/O (A9)
J2
77
GND
VCC
I/O
D9
P78
I/O
J1
80
D10
C10
B10
A9
-
P79
I/O
H1
H2
H3
G1
G2
-
83
218
221
224
227
230
233
236
239
-
P80
I/O
86
I/O
P81
I/O
89
I/O
P82
I/O (A10)
92
I/O
A10
A11
C11
D11
D12
-
P83
I/O (A11)
95
I/O
I/O (INIT)
VCC
GND
I/O
P84
VCC
-
I/O
P85
I/O
H4
G4
F1
E1
G3
F2
D1
C1
E2
F3
D2
F4
E4
B1
E3
C2
B2
D3
D4
C3
C4
B3
C5
A2
B4
C6
A3
B5
B6
D5
D6
C7
A4
A5
B7
A6
D7
D8
C8
A7
B8
98
I/O
P86
-
I/O
101
104
107
-
I/O
P87
367
370
373
376
379
382
385
388
-
I/O
VCC
I/O
I/O
P88
I/O
B11
A12
B12
A13
C12
D13
D14
B13
A14
A15
C13
B14
A16
B15
C14
A17
B16
C15
D15
A18
D16
C16
B17
E16
C17
D17
B18
E17
F16
C18
D18
F17
E15
F15
G16
E18
F18
242
245
248
251
-
I/O
P89
GND
I/O
I/O
P90
I/O
110
113
116
119
122
125
128
131
134
137
140
143
-
I/O
I/O
P91
I/O
I/O
I/O
P92
I/O
GND
I/O
I/O
P93
I/O
254
257
260
263
266
269
272
275
278
281
284
287
290
-
I/O
P94
I/O (A12)
I/O
VCC
I/O
P95
I/O (A13)
I/O
M18
M17
N18
P18
M16
N15
P15
N17
R18
T18
P17
N16
T17
R17
P16
U18
T16
R16
U17
R15
V18
T15
U16
T14
U15
R14
R13
V17
V16
T13
P96
391
394
397
400
-
I/O
I/O
I/O
P97
I/O
I/O
I/O
P98
I/O
I/O
I/O
P99
I/O
I/O
GND
I/O
P100
P101
P102
P103
P104
P105
P106
P107
P108
P109
P110
P111
P112
P113
P114
P115
P116
P117
P118
P119
P120
P121
P122
P123
P124
P125
I/O (A14)
I/O
403
406
409
412
415
418
421
424
427
430
433
436
-
I/O, SGCK1 (A15)
I/O
I/O
VCC
I/O
I/O
GND
-
I/O
I/O
I/O, PGCK1(A16)
P2
146
149
152
155
158
161
164
167
170
173
176
179
-
I/O, SGCK2
O (M1)
GND
I (M0)
VCC
I (M2)
I/O, PGCK2
I/O (HDC)
I/O
I/O
I/O (A17)
I/O
P3
I/O
P4
I/O
I/O
P5
293
-
I/O
I/O, TDI
I/O, TCK
I/O
P6
I/O
P7
294
295
298
301
304
307
310
313
316
319
322
325
328
-
I/O
P8
I/O
I/O
P9
I/O, SGCK3
GND
DONE
VCC
PROGRAM
I/O (D7)
I/O, PGCK3
I/O
I/O
P10
I/O
P11
I/O
-
I/O
P12
I/O
-
I/O
P13
I/O (LDC)
I/O
-
GND
I/O
P14
439
442
445
448
451
454
457
460
463
P15
182
185
188
191
194
197
200
203
206
I/O
I/O
P16
I/O
I/O, TMS
I/O
P17
I/O
I/O
P18
I/O
I/O
I/O
P19
I/O
I/O
I/O
P20
GND
I/O
I/O (D6)
I/O
I/O
P21
331
334
I/O
P22
I/O
I/O
I/O
P23
November 21, 1997 (Version 1.3)
8-29
XC4000E High-Reliability Field Programmable Gate Arrays
XC4013E
Pad Name
PG
223†
CB
228
Bndry
Scan
XC4013E
Pad Name
PG
223†
CB
228
Bndry
Scan
XC4013E
Pad Name
PG
223†
CB
228
Bndry
Scan
I/O
I/O
I/O
U14
V15
V14
T12
R12
R11
U13
V13
U12
V12
T11
U11
V11
V10
U10
T10
R10
R9
P126
P127
P128
P129
P130
P131
P132
P133
P134
P135
P136
P137
P138
P139
P140
P141
P142
P143
P144
P145
P146
P147
P148
P149
P150
P151
P152
466
469
472
-
I/O
I/O
I/O
I/O
V6
U6
R8
R7
T7
R6
R5
V5
V4
U5
T6
V3
V2
P153
P154
P155
P156
P157
P158
P159
P160
P161
P162
P163
P164
P165
535
538
541
544
-
I/O (CS1, A2)
I/O (A3)
I/O
T2
N3
P4
N4
P2
T1
R1
N2
M3
P1
N1
M4
L4
-
P178
P179
P180
P181
P182
P183
P184
P185
P186
P187
P188
P189
P190
P191
P192
P193
P194
P195
P196
P197
P198
P199
P200
14
17
20
23
26
29
32
35
-
GND
I/O
I/O
475
478
481
484
487
490
493
496
499
502
505
508
-
GND
I/O
I/O
I/O
547
550
553
556
559
562
565
568
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O (D5)
I/O (CS0)
I/O
I/O
GND
I/O
I/O
38
41
44
47
-
I/O
I/O
I/O
I/O (D1)
I/O
I/O
I/O (RCLK,
RDY/BUSY)
I/O
I/O
VCC
I/O (A4)
I/O (A5)
I/O
I/O
U4
T5
U3
T4
P166
P167
P168
P169
571
574
577
580
I/O (D4)
I/O
M2
M1
L3
L2
L1
K1
K2
K3
K4
50
53
56
59
62
65
68
71
-
I/O
I/O (D0, DIN)
VCC
GND
I/O (D3)
I/O (RS)
I/O
I/O, SGCK4
(DOUT)
-
I/O
T9
511
514
517
520
523
526
529
532
-
I/O
CCLK
V1
R4
U2
R3
T3
U1
P3
R2
P170
P171
P172
P173
P174
P175
P176
P177
-
-
U9
I/O
VCC
V9
I/O (A6)
I/O (A7)
GND
8/14/97
O, TDO
GND
0
-
I/O
V8
I/O
U8
I/O (A0, WS)
I/O, PGCK4 (A1)
I/O
2
5
8
11
I/O
T8
I/O (D2)
I/O
V7
U7
I/O
VCC
-
Pin Locations for XC4025E Devices
XC4025E
Pad Name
CB
228
PG
299
Bndry
Scan
XC4025E
Pad Name
CB
228
PG
299
Bndry
Scan
XC4025E
Pad Name
CB
228
PG
299
Bndry
Scan
I/O
I/O
I/O
P223
P224
P225
P226
P227
P228
P1
C2
F5
E4
D3
C3
A2
B1
D4
B2
B3
E6
D5
C4
A3
D6
E7
B4
C5
A4
D7
C6
E8
B5
A5
B6
D8
C7
B7
A6
C8
179
182
185
188
191
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
-
E9
A7
257
260
263
266
269
272
275
278
281
284
287
-
VCC
P201
P202
P203
P204
P205
P206
P207
P208
P209
-
K1
K2
K3
K5
K4
J1
-
-
I/O (A8)
I/O (A9)
I/O
98
-
D9
101
104
107
110
113
116
119
122
125
128
131
-
I/O (A14)
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
-
B8
I/O, SGCK1 (A15)
A8
I/O
VCC
C9
I/O
GND
-
B9
I/O
J2
I/O, PGCK1 (A16)
P2
194
197
200
203
206
209
212
215
218
221
224
227
230
233
236
239
-
E10
A9
I/O (A10)
I/O (A11)
I/O
H1
J3
I/O (A17)
I/O
P3
P4
D10
C10
A10
A11
B10
B11
C11
E11
D11
A12
B12
A13
C12
D12
E12
B13
A16
A14
C13
B14
D13
J4
I/O
P5
I/O
-
J5
I/O, TDI
I/O, TCK
I/O
P6
I/O
-
H2
G1
E1
H3
G2
H4
F2
F1
H5
G3
D1
G4
E2
F3
G5
C1
F4
E3
D2
P7
-
I/O
-
-
290
293
296
299
302
305
308
311
314
317
320
323
-
VCC
I/O
P210
P211
P212
P213
P214
P215
-
I/O
-
134
137
140
143
-
I/O
P8
I/O
I/O
P9
I/O
I/O
P10
P11
P12
P13
-
I/O
I/O
GND
I/O
I/O
146
149
152
155
158
161
164
167
170
173
176
I/O
-
I/O
-
I/O
-
I/O
P216
P217
P218
P219
P220
P221
-
I/O
-
-
I/O
GND
I/O
P14
P15
P16
P17
P18
-
P35
P36
P37
P38
P39
P40
P41
I/O
242
245
248
251
-
I/O
I/O
I/O (A12)
I/O (A13)
I/O
I/O, TMS
I/O
326
329
332
335
VCC
I/O
I/O
-
-
254
I/O
P222
8-30
November 21, 1997 (Version 1.3)
XC4025E
Pad Name
CB
228
PG
299
Bndry
Scan
XC4025E
Pad Name
CB
228
PG
299
Bndry
Scan
XC4025E
Pad Name
CB
228
PG
299
Bndry
Scan
GND
P42
-
A15
B15
E13
C14
A17
D14
B16
C15
E14
A18
D15
C16
B17
B18
E15
D16
C17
A20
A19
C18
B20
D17
B19
C19
F16
E17
D18
C20
F17
G16
D19
E18
D20
G17
F18
H16
E19
F19
E20
H17
G18
G19
H18
VCC*
J16
-
I/O
I/O
I/O
I/O
I/O
I/O
-
N20
M18
M17
M16
N19
P20
T20
N18
P19
N17
R19
R20
N16
P18
U20
P17
T19
R18
P16
V20
R17
T18
U19
V19
R16
T17
U18
X20
W20
V18
X19
U17
W19
W18
T15
U16
V17
X18
U15
T14
W17
V16
X17
U14
V15
T13
W16
W15
X16
U13
V14
W14
V13
X15
T12
X14
U12
W13
X13
V12
W12
T11
X12
U11
505
508
511
514
517
520
-
I/O (D4)
P140
P141
P142
P143
P144
P145
P146
P147
P148
P149
-
V11
W11
X10
X11
W10
V10
T10
U10
X9
673
676
-
I/O
338
341
344
347
350
353
356
359
362
365
368
371
374
377
380
383
386
-
-
I/O
I/O
-
-
VCC
GND
I/O (D3)
I/O (RS)
I/O
I/O
P43
P44
P45
P46
P47
P48
-
-
-
I/O
P93
P94
P95
P96
P97
P98
P99
P100
-
679
682
685
688
691
694
697
700
703
706
709
712
-
I/O
I/O
VCC
I/O
I/O
523
526
529
532
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
W9
X8
I/O
-
I/O
I/O
I/O
P49
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
-
GND
I/O
I/O
-
V9
I/O
535
538
541
544
547
550
553
556
559
562
565
568
571
574
577
580
-
I/O
-
U9
I/O
I/O
-
I/O
-
T9
I/O
I/O
P101
P102
P103
P104
P105
P106
-
I/O (D2)
I/O
P150
P151
P152
P153
P154
P155
P156
P157
-
W8
X7
I/O
I/O
I/O, SGCK2
O (M1)
GND
I (M0)
VCC
I (M2)
I/O, PGCK2
I/O (HDC)
I/O
I/O
VCC
I/O
X5
I/O
V8
715
718
721
724
-
I/O
I/O
W7
U8
389
-
I/O
I/O
I/O
I/O
W6
X6
390
391
394
397
400
403
406
409
412
415
418
421
424
427
430
433
436
-
I/O
-
GND
I/O
I/O
P107
P108
P109
P110
P111
P112
P113
P114
P115
P116
P117
P118
P119
P120
P121
P122
-
T8
727
730
733
736
739
742
745
748
751
754
I/O
I/O
-
V7
I/O
I/O
P158
P159
P160
P161
P162
P163
P164
P165
X4
I/O
I/O
I/O
U7
I/O
I/O
I/O
W5
V6
I/O (LDC)
I/O
I/O, SGCK3
GND
DONE
VCC
PROGRAM
I/O (D7)
I/O, PGCK3
I/O
I/O
I/O
T7
I/O
-
-
I/O
X3
I/O
P66
P67
P68
P69
P70
P71
-
-
I/O (D1)
U6
I/O
-
I/O (RCLK,
RDY/BUSY)
V5
I/O
583
586
589
592
595
598
601
604
607
610
613
616
619
622
625
628
-
I/O
-
W4
W3
T6
757
760
763
766
769
772
I/O
I/O
-
I/O
I/O
P166
P167
P168
P169
I/O
I/O
I/O
U5
V4
X1
I/O
I/O
I/O (D0, DIN)
I/O
-
I/O
I/O, SGCK4
(DOUT)
GND
I/O
P72
P73
P74
P75
P76
-
I/O
439
442
445
448
-
I/O
-
CCLK
P170
P171
P172
P173
P174
P175
P176
P177
P178
P179
P180
P181
P182
P183
P184
P185
-
V3
VCC*
U4
GND*
W2
V2
-
I/O
I/O (D6)
I/O
P123
P124
P125
P126
P127
P128
-
VCC
-
I/O
O, TDO
0
I/O
I/O
GND
-
VCC
I/O
I/O
I/O (A0, WS)
2
P77
P78
-
451
454
457
460
463
466
469
472
475
478
481
484
-
I/O
I/O, PGCK4 (A1)
5
I/O
G20
J17
I/O
I/O
R5
T4
8
I/O
I/O
I/O
11
14
17
20
23
26
29
32
35
38
41
44
47
-
I/O
-
H19
H20
J18
I/O
-
I/O (CS1, A2)
U3
V1
I/O
-
GND
I/O
P129
P130
P131
P132
P133
-
I/O (A3)
I/O
I/O
-
631
634
637
640
-
R4
P5
I/O
P79
P80
P81
P82
P83
P84
P85
P86
P87
P88
P89
P90
P91
P92
J19
I/O
I/O
I/O
K16
J20
I/O
I/O
U2
T3
I/O
I/O
I/O
I/O
K17
K18
K19
L20
K20
L19
L18
L16
L17
M20
M19
VCC
I/O (D5)
I/O (CS0)
I/O
I/O
U1
P4
I/O
P134
P135
-
643
646
649
652
655
658
661
664
667
670
I/O
I/O (INIT)
VCC
GND
I/O
I/O
R3
N5
T2
I/O
-
-
I/O
-
I/O
-
487
490
493
496
499
502
I/O
-
I/O
-
R2
T1
I/O
I/O
-
GND
I/O
P186
P187
P188
P189
I/O
I/O
P136
P137
P138
P139
N4
P3
50
53
56
I/O
I/O
I/O
I/O
I/O
I/O
P2
I/O
I/O
November 21, 1997 (Version 1.3)
8-31
XC4000E High-Reliability Field Programmable Gate Arrays
XC4025E
Pad Name
CB
228
PG
299
Bndry
Scan
I/O
P190
P191
-
N3
R1
M5
P1
M4
N2
N1
M3
M2
L5
59
-
VCC
I/O
62
65
68
71
74
77
80
83
86
89
92
95
-
I/O
-
I/O
-
I/O
-
I/O (A4)
I/O (A5)
I/O
P192
P193
P194
P195
P196
P197
P198
P199
P200
I/O
I/O
M1
L4
I/O
I/O (A6)
I/O (A7)
GND
8/14/97
L3
L2
L1
8-32
November 21, 1997 (Version 1.3)
Ordering Information
Example for SMD Part:
5962-97523 01 Q X C
Lead Finish
C = Gold
Generic Standard
Microcircuit Drawing
(SMD) Prefix
Package Type
X = Pin Grid
Device Type
Y = Quad Flatpack
(Base Mark)
Z = Quad Flatpack
(Lid Mark)
XC4005E = 97522
XC4010E = 97523
XC4013E = 97524
XC4025E = 97525
QML Certified
Speed Grade
01 = -4
Example for
Military Tempeture Only Part:
XC4010E -4 PG 191 M
Temperature Range
Device Type
XC4005E
M = Military (TC = -55o C to +125o C)
XC4010E
XC4013E
XC4025E
Number of Pins
Speed Grade
Package Type
CB = Top Braxed Ceramic Quad Flat Pack
PG = Ceramic Pin Grid Array
November 21, 1997 (Version 1.3)
8-33
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