XC4044XL-09BGG432C [XILINX]
Field Programmable Gate Array, 1600 CLBs, 27000 Gates, 217MHz, CMOS, PBGA432;
| 型号： | XC4044XL-09BGG432C |
| 厂家： | 
XILINX, INC |
| 描述： | Field Programmable Gate Array, 1600 CLBs, 27000 Gates, 217MHz, CMOS, PBGA432 栅 |
| 文件： | 总124页 (文件大小：989K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0
R
XC4000E and XC4000X Series Field
Programmable Gate Arrays
0
0*
May 14, 1999 (Version 1.6)
Product Specification
XC4000E and XC4000X Series
Features
Low-Voltage Versions Available
•
•
Low-Voltage Devices Function at 3.0 - 3.6 Volts
XC4000XL: High Performance Low-Voltage Versions of
XC4000EX devices
Note: Information in this data sheet covers the XC4000E,
XC4000EX, and XC4000XL families. A separate data sheet
covers the XC4000XLA and XC4000XV families. Electrical
Specifications and package/pin information are covered in
separate sections for each family to make the information
easier to access, review, and print. For access to these sec-
tions, see the Xilinx WEBLINX web site at
Additional XC4000X Series Features
•
•
•
•
•
Highest Performance — 3.3 V XC4000XL
Highest Capacity — Over 180,000 Usable Gates
5 V tolerant I/Os on XC4000XL
0.35 µm SRAM process for XC4000XL
Additional Routing Over XC4000E
http://www.xilinx.com/partinfo/databook.htm#xc4000.
•
System featured Field-Programmable Gate Arrays
-
-
almost twice the routing capacity for high-density
designs
Select-RAMTM memory: on-chip ultra-fast RAM with
-
-
synchronous write option
dual-port RAM option
•
•
Buffered Interconnect for Maximum Speed Blocks
Improved VersaRingTM I/O Interconnect for Better Fixed
Pinout Flexibility
-
-
-
-
-
-
-
-
Fully PCI compliant (speed grades -2 and faster)
Abundant flip-flops
Flexible function generators
Dedicated high-speed carry logic
Wide edge decoders on each edge
Hierarchy of interconnect lines
Internal 3-state bus capability
Eight global low-skew clock or signal distribution
networks
6
•
•
12 mA Sink Current Per XC4000X Output
Flexible New High-Speed Clock Network
-
-
Eight additional Early Buffers for shorter clock delays
Virtually unlimited number of clock signals
•
•
•
Optional Multiplexer or 2-input Function Generator on
Device Outputs
Four Additional Address Bits in Master Parallel
Configuration Mode
XC4000XV Family offers the highest density with
0.25 µm 2.5 V technology
•
•
•
•
System Performance beyond 80 MHz
Flexible Array Architecture
Low Power Segmented Routing Architecture
Systems-Oriented Features
Introduction
-
IEEE 1149.1-compatible boundary scan logic
support
XC4000 Series high-performance, high-capacity Field Pro-
grammable Gate Arrays (FPGAs) provide the benefits of
custom CMOS VLSI, while avoiding the initial cost, long
development cycle, and inherent risk of a conventional
masked gate array.
-
-
-
Individually programmable output slew rate
Programmable input pull-up or pull-down resistors
12 mA sink current per XC4000E output
•
•
Configured by Loading Binary File
Unlimited re-programmability
Read Back Capability
-
The result of thirteen years of FPGA design experience and
feedback from thousands of customers, these FPGAs com-
bine architectural versatility, on-chip Select-RAM memory
with edge-triggered and dual-port modes, increased
speed, abundant routing resources, and new, sophisticated
software to achieve fully automated implementation of
complex, high-density, high-performance designs.
-
-
Program verification
Internal node observability
•
•
Backward Compatible with XC4000 Devices
Development System runs on most common computer
platforms
-
-
-
Interfaces to popular design environments
Fully automatic mapping, placement and routing
Interactive design editor for design optimization
The XC4000E and XC4000X Series currently have 20
members, as shown in Table 1.
May 14, 1999 (Version 1.6)
6-5
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XC4000E and XC4000X Series Field Programmable Gate Arrays
Table 1: XC4000E and XC4000X Series Field Programmable Gate Arrays
Max Logic Max. RAM
Gates Bits
(No RAM) (No Logic) (Logic and RAM)*
Typical
Gate Range
Number
of
CLBs Flip-Flops User I/O
Logic
Cells
CLB
Matrix
Total
Max.
Device
XC4002XL
XC4003E
152
238
1,600
3,000
2,048
3,200
1,000 - 3,000
2,000 - 5,000
8 x 8
64
256
360
64
10 x 10
14 x 14
16 x 16
18 x 18
20 x 20
24 x 24
28 x 28
32 x 32
32 x 32
36 x 36
40 x 40
44 x 44
48 x 48
56 x 56
100
80
XC4005E/XL
XC4006E
466
5,000
6,272
3,000 - 9,000
196
616
112
128
144
160
192
224
256
256
288
320
352
384
448
608
6,000
8,192
4,000 - 12,000
6,000 - 15,000
7,000 - 20,000
10,000 - 30,000
13,000 - 40,000
15,000 - 45,000
18,000 - 50,000
22,000 - 65,000
27,000 - 80,000
33,000 - 100,000
40,000 - 130,000
55,000 - 180,000
256
768
XC4008E
770
8,000
10,368
12,800
18,432
25,088
32,768
32,768
41,472
51,200
61,952
73,728
100,352
324
936
XC4010E/XL
XC4013E/XL
XC4020E/XL
XC4025E
950
10,000
13,000
20,000
25,000
28,000
36,000
44,000
52,000
62,000
85,000
400
1,120
1,536
2,016
2,560
2,560
3,168
3,840
4,576
5,376
7,168
1368
1862
2432
2432
3078
3800
4598
5472
7448
576
784
1,024
1,024
1,296
1,600
1,936
2,304
3,136
XC4028EX/XL
XC4036EX/XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
*
Max values of Typical Gate Range include 20-30% of CLBs used as RAM.
Note: All functionality in low-voltage families is the same as
in the corresponding 5-Volt family, except where numerical
references are made to timing or power.
where hardware is changed dynamically, or where hard-
ware must be adapted to different user applications.
FPGAs are ideal for shortening design and development
cycles, and also offer a cost-effective solution for produc-
tion rates well beyond 5,000 systems per month. For lowest
high-volume unit cost, a design can first be implemented in
the XC4000E or XC4000X, then migrated to one of Xilinx’
compatible HardWire mask-programmed devices.
Description
XC4000 Series devices are implemented with a regular,
flexible, programmable architecture of Configurable Logic
Blocks (CLBs), interconnected by a powerful hierarchy of
versatile routing resources, and surrounded by a perimeter
of programmable Input/Output Blocks (IOBs). They have
generous routing resources to accommodate the most
complex interconnect patterns.
Taking Advantage of Re-configuration
FPGA devices can be re-configured to change logic func-
tion while resident in the system. This capability gives the
system designer a new degree of freedom not available
with any other type of logic.
The devices are customized by loading configuration data
into internal memory cells. The FPGA can either actively
read its configuration data from an external serial or
byte-parallel PROM (master modes), or the configuration
data can be written into the FPGA from an external device
(slave and peripheral modes).
Hardware can be changed as easily as software. Design
updates or modifications are easy, and can be made to
products already in the field. An FPGA can even be re-con-
figured dynamically to perform different functions at differ-
ent times.
XC4000 Series FPGAs are supported by powerful and
sophisticated software, covering every aspect of design
from schematic or behavioral entry, floor planning, simula-
tion, automatic block placement and routing of intercon-
nects, to the creation, downloading, and readback of the
configuration bit stream.
Re-configurable logic can be used to implement system
self-diagnostics, create systems capable of being re-con-
figured for different environments or operations, or imple-
ment multi-purpose hardware for a given application. As an
added benefit, using re-configurable FPGA devices simpli-
fies hardware design and debugging and shortens product
time-to-market.
Because Xilinx FPGAs can be reprogrammed an unlimited
number of times, they can be used in innovative designs
6-6
May 14, 1999 (Version 1.6)
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XC4000E and XC4000X Series Field Programmable Gate Arrays
much as 50% from XC4000 values. See “Fast Carry Logic”
on page 18 for more information.
XC4000E and XC4000X Series
Compared to the XC4000
Select-RAM Memory: Edge-Triggered, Synchro-
nous RAM Modes
For readers already familiar with the XC4000 family of Xil-
inx Field Programmable Gate Arrays, the major new fea-
tures in the XC4000 Series devices are listed in this
section. The biggest advantages of XC4000E and
XC4000X devices are significantly increased system
speed, greater capacity, and new architectural features,
particularly Select-RAM memory. The XC4000X devices
also offer many new routing features, including special
high-speed clock buffers that can be used to capture input
data with minimal delay.
The RAM in any CLB can be configured for synchronous,
edge-triggered, write operation. The read operation is not
affected by this change to an edge-triggered write.
Dual-Port RAM
A separate option converts the 16x2 RAM in any CLB into a
16x1 dual-port RAM with simultaneous Read/Write.
The function generators in each CLB can be configured as
either level-sensitive (asynchronous) single-port RAM,
edge-triggered (synchronous) single-port RAM, edge-trig-
gered (synchronous) dual-port RAM, or as combinatorial
logic.
Any XC4000E device is pinout- and bitstream-compatible
with the corresponding XC4000 device. An existing
XC4000 bitstream can be used to program an XC4000E
device. However, since the XC4000E includes many new
features, an XC4000E bitstream cannot be loaded into an
XC4000 device.
Configurable RAM Content
XC4000X Series devices are not bitstream-compatible with
equivalent array size devices in the XC4000 or XC4000E
families. However, equivalent array size devices, such as
the XC4025, XC4025E, XC4028EX, and XC4028XL, are
pinout-compatible.
The RAM content can now be loaded at configuration time,
so that the RAM starts up with user-defined data.
H Function Generator
6
In current XC4000 Series devices, the H function generator
is more versatile than in the original XC4000. Its inputs can
come not only from the F and G function generators but
also from up to three of the four control input lines. The H
function generator can thus be totally or partially indepen-
dent of the other two function generators, increasing the
maximum capacity of the device.
Improvements in XC4000E and XC4000X
Increased System Speed
XC4000E and XC4000X devices can run at synchronous
system clock rates of up to 80 MHz, and internal perfor-
mance can exceed 150 MHz. This increase in performance
over the previous families stems from improvements in both
IOB Clock Enable
device processing and system architecture.
XC4000
The two flip-flops in each IOB have a common clock enable
input, which through configuration can be activated individ-
ually for the input or output flip-flop or both. This clock
enable operates exactly like the EC pin on the XC4000
CLB. This new feature makes the IOBs more versatile, and
avoids the need for clock gating.
Series devices use a sub-micron multi-layer metal process.
In addition, many architectural improvements have been
made, as described below.
The XC4000XL family is a high performance 3.3V family
based on 0.35µ SRAM technology and supports system
speeds to 80 MHz.
Output Drivers
PCI Compliance
The output pull-up structure defaults to a TTL-like
totem-pole. This driver is an n-channel pull-up transistor,
pulling to a voltage one transistor threshold below Vcc, just
like the XC4000 family outputs. Alternatively, XC4000
Series devices can be globally configured with CMOS out-
puts, with p-channel pull-up transistors pulling to Vcc. Also,
the configurable pull-up resistor in the XC4000 Series is a
p-channel transistor that pulls to Vcc, whereas in the origi-
nal XC4000 family it is an n-channel transistor that pulls to
a voltage one transistor threshold below Vcc.
XC4000 Series -2 and faster speed grades are fully PCI
compliant. XC4000E and XC4000X devices can be used to
implement a one-chip PCI solution.
Carry Logic
The speed of the carry logic chain has increased dramati-
cally. Some parameters, such as the delay on the carry
chain through a single CLB (TBYP), have improved by as
May 14, 1999 (Version 1.6)
6-7
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XC4000E and XC4000X Series Field Programmable Gate Arrays
Input Thresholds
Additional Improvements in XC4000X Only
Increased Routing
The input thresholds of 5V devices can be globally config-
ured for either TTL (1.2 V threshold) or CMOS (2.5 V
threshold), just like XC2000 and XC3000 inputs. The two
global adjustments of input threshold and output level are
independent of each other. The XC4000XL family has an
input threshold of 1.6V, compatible with both 3.3V CMOS
and TTL levels.
New interconnect in the XC4000X includes twenty-two
additional vertical lines in each column of CLBs and twelve
new horizontal lines in each row of CLBs. The twelve “Quad
Lines” in each CLB row and column include optional repow-
ering buffers for maximum speed. Additional high-perfor-
mance routing near the IOBs enhances pin flexibility.
Global Signal Access to Logic
Faster Input and Output
There is additional access from global clocks to the F and
G function generator inputs.
A fast, dedicated early clock sourced by global clock buffers
is available for the IOBs. To ensure synchronization with the
regular global clocks, a Fast Capture latch driven by the
early clock is available. The input data can be initially
loaded into the Fast Capture latch with the early clock, then
transferred to the input flip-flop or latch with the low-skew
global clock. A programmable delay on the input can be
used to avoid hold-time requirements. See “IOB Input Sig-
nals” on page 20 for more information.
Configuration Pin Pull-Up Resistors
During configuration, these pins have weak pull-up resis-
tors. For the most popular configuration mode, Slave
Serial, the mode pins can thus be left unconnected. The
three mode inputs can be individually configured with or
without weak pull-up or pull-down resistors. A pull-down
resistor value of 4.7 kΩ is recommended.
Latch Capability in CLBs
The three mode inputs can be individually configured with
or without weak pull-up or pull-down resistors after configu-
ration.
Storage elements in the XC4000X CLB can be configured
as either flip-flops or latches. This capability makes the
FPGA highly synthesis-compatible.
The PROGRAM input pin has a permanent weak pull-up.
Soft Start-up
IOB Output MUX From Output Clock
Like the XC3000A, XC4000 Series devices have “Soft
Start-up.” When the configuration process is finished and
the device starts up, the first activation of the outputs is
automatically slew-rate limited. This feature avoids poten-
tial ground bounce when all outputs are turned on simulta-
neously. Immediately after start-up, the slew rate of the
individual outputs is, as in the XC4000 family, determined
by the individual configuration option.
A multiplexer in the IOB allows the output clock to select
either the output data or the IOB clock enable as the output
to the pad. Thus, two different data signals can share a sin-
gle output pad, effectively doubling the number of device
outputs without requiring a larger, more expensive pack-
age. This multiplexer can also be configured as an
AND-gate to implement a very fast pin-to-pin path. See
“IOB Output Signals” on page 23 for more information.
XC4000 and XC4000A Compatibility
Additional Address Bits
Existing XC4000 bitstreams can be used to configure an
XC4000E device. XC4000A bitstreams must be recompiled
for use with the XC4000E due to improved routing
resources, although the devices are pin-for-pin compatible.
Larger devices require more bits of configuration data. A
daisy chain of several large XC4000X devices may require
a PROM that cannot be addressed by the eighteen address
bits supported in the XC4000E. The XC4000X Series
therefore extends the addressing in Master Parallel config-
uration mode to 22 bits.
6-8
May 14, 1999 (Version 1.6)
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XC4000E and XC4000X Series Field Programmable Gate Arrays
Each CLB contains two storage elements that can be used
Detailed Functional Description
to store the function generator outputs. However, the stor-
age elements and function generators can also be used
independently. These storage elements can be configured
as flip-flops in both XC4000E and XC4000X devices; in the
XC4000X they can optionally be configured as latches. DIN
can be used as a direct input to either of the two storage
elements. H1 can drive the other through the H function
generator. Function generator outputs can also drive two
outputs independent of the storage element outputs. This
versatility increases logic capacity and simplifies routing.
XC4000 Series devices achieve high speed through
advanced semiconductor technology and improved archi-
tecture. The XC4000E and XC4000X support system clock
rates of up to 80 MHz and internal performance in excess
of 150 MHz. Compared to older Xilinx FPGA families,
XC4000 Series devices are more powerful. They offer
on-chip edge-triggered and dual-port RAM, clock enables
on I/O flip-flops, and wide-input decoders. They are more
versatile in many applications, especially those involving
RAM. Design cycles are faster due to a combination of
increased routing resources and more sophisticated soft-
ware.
Thirteen CLB inputs and four CLB outputs provide access
to the function generators and storage elements. These
inputs and outputs connect to the programmable intercon-
nect resources outside the block.
Basic Building Blocks
Xilinx user-programmable gate arrays include two major
configurable elements: configurable logic blocks (CLBs)
and input/output blocks (IOBs).
Function Generators
Four independent inputs are provided to each of two func-
tion generators (F1 - F4 and G1 - G4). These function gen-
erators, with outputs labeled F’ and G’, are each capable of
implementing any arbitrarily defined Boolean function of
four inputs. The function generators are implemented as
memory look-up tables. The propagation delay is therefore
independent of the function implemented.
•
CLBs provide the functional elements for constructing
the user’s logic.
•
IOBs provide the interface between the package pins
and internal signal lines.
6
Three other types of circuits are also available:
A third function generator, labeled H’, can implement any
Boolean function of its three inputs. Two of these inputs can
optionally be the F’ and G’ functional generator outputs.
Alternatively, one or both of these inputs can come from
outside the CLB (H2, H0). The third input must come from
outside the block (H1).
•
•
•
3-State buffers (TBUFs) driving horizontal longlines are
associated with each CLB.
Wide edge decoders are available around the periphery
of each device.
An on-chip oscillator is provided.
Programmable interconnect resources provide routing
paths to connect the inputs and outputs of these config-
urable elements to the appropriate networks.
Signals from the function generators can exit the CLB on
two outputs. F’ or H’ can be connected to the X output. G’ or
H’ can be connected to the Y output.
The functionality of each circuit block is customized during
configuration by programming internal static memory cells.
The values stored in these memory cells determine the
logic functions and interconnections implemented in the
FPGA. Each of these available circuits is described in this
section.
A CLB can be used to implement any of the following func-
tions:
•
any function of up to four variables, plus any second
function of up to four unrelated variables, plus any third
function of up to three unrelated variables1
any single function of five variables
any function of four variables together with some
functions of six variables
•
•
Configurable Logic Blocks (CLBs)
Configurable Logic Blocks implement most of the logic in
an FPGA. The principal CLB elements are shown in
Figure 1. Two 4-input function generators (F and G) offer
unrestricted versatility. Most combinatorial logic functions
need four or fewer inputs. However, a third function gener-
ator (H) is provided. The H function generator has three
inputs. Either zero, one, or two of these inputs can be the
outputs of F and G; the other input(s) are from outside the
CLB. The CLB can, therefore, implement certain functions
of up to nine variables, like parity check or expand-
able-identity comparison of two sets of four inputs.
•
some functions of up to nine variables.
Implementing wide functions in a single block reduces both
the number of blocks required and the delay in the signal
path, achieving both increased capacity and speed.
The versatility of the CLB function generators significantly
improves system speed. In addition, the design-software
tools can deal with each function generator independently.
This flexibility improves cell usage.
1. When three separate functions are generated, one of the function outputs must be captured in a flip-flop internal to the CLB. Only two
unregistered function generator outputs are available from the CLB.
May 14, 1999 (Version 1.6)
6-9
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XC4000E and XC4000X Series Field Programmable Gate Arrays
4
C
• • • C
4
1
H
EC
D
/H
2
SR/H
1
IN
0
G
G
G
G
S/R
CONTROL
Bypass
4
3
2
1
DIN
F'
G'
YQ
LOGIC
FUNCTION
OF
SD
D
Q
G'
H'
G1-G4
LOGIC
FUNCTION
OF
F', G',
AND
H1
EC
RD
G'
H'
H'
1
Y
F
F
F
F
4
3
2
1
Bypass
S/R
CONTROL
DIN
F'
G'
H'
XQ
LOGIC
FUNCTION
OF
SD
D
Q
F'
F1-F4
EC
RD
K
(CLOCK)
1
H'
F'
X
Multiplexer Controlled
by Configuration Program
X6692
Figure 1: Simplified Block Diagram of XC4000 Series CLB (RAM and Carry Logic functions not shown)
Flip-Flops
Clock Enable
The CLB can pass the combinatorial output(s) to the inter-
connect network, but can also store the combinatorial
results or other incoming data in one or two flip-flops, and
connect their outputs to the interconnect network as well.
The clock enable signal (EC) is active High. The EC pin is
shared by both storage elements. If left unconnected for
either, the clock enable for that storage element defaults to
the active state. EC is not invertible within the CLB.
The two edge-triggered D-type flip-flops have common
clock (K) and clock enable (EC) inputs. Either or both clock
inputs can also be permanently enabled. Storage element
functionality is described in Table 2.
Table 2: CLB Storage Element Functionality
(active rising edge is shown)
Mode
K
EC
SR
D
Q
Power-Up or
GSR
Latches (XC4000X only)
X
X
X
X
SR
The CLB storage elements can also be configured as
latches. The two latches have common clock (K) and clock
enable (EC) inputs. Storage element functionality is
described in Table 2.
X
__/
0
X
1*
X
1
X
D
X
X
D
X
SR
D
Flip-Flop
0*
0*
0*
0*
0*
Q
1
1*
1*
0
Q
Clock Input
Latch
Both
0
D
Each flip-flop can be triggered on either the rising or falling
clock edge. The clock pin is shared by both storage ele-
ments. However, the clock is individually invertible for each
storage element. Any inverter placed on the clock input is
automatically absorbed into the CLB.
X
Q
Legend:
X
Don’t care
Rising edge
Set or Reset value. Reset is default.
Input is Low or unconnected (default value)
__/
SR
0*
1*
Input is High or unconnected (default value)
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May 14, 1999 (Version 1.6)
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XC4000E and XC4000X Series Field Programmable Gate Arrays
Two fast feed-through paths are available, as shown in
Figure 1. A two-to-one multiplexer on each of the XQ and
YQ outputs selects between a storage element output and
any of the control inputs. This bypass is sometimes used by
the automated router to repower internal signals.
Set/Reset
An asynchronous storage element input (SR) can be con-
figured as either set or reset. This configuration option
determines the state in which each flip-flop becomes oper-
ational after configuration. It also determines the effect of a
Global Set/Reset pulse during normal operation, and the
effect of a pulse on the SR pin of the CLB. All three
set/reset functions for any single flip-flop are controlled by
the same configuration data bit.
Control Signals
Multiplexers in the CLB map the four control inputs (C1 - C4
in Figure 1) into the four internal control signals (H1,
DIN/H2, SR/H0, and EC). Any of these inputs can drive any
of the four internal control signals.
The set/reset state can be independently specified for each
flip-flop. This input can also be independently disabled for
either flip-flop.
When the logic function is enabled, the four inputs are:
•
•
EC — Enable Clock
SR/H0 — Asynchronous Set/Reset or H function
generator Input 0
DIN/H2 — Direct In or H function generator Input 2
H1 — H function generator Input 1.
The set/reset state is specified by using the INIT attribute,
or by placing the appropriate set or reset flip-flop library
symbol.
•
•
SR is active High. It is not invertible within the CLB.
When the memory function is enabled, the four inputs are:
Global Set/Reset
•
•
•
•
EC — Enable Clock
WE — Write Enable
D0 — Data Input to F and/or G function generator
D1 — Data input to G function generator (16x1 and
16x2 modes) or 5th Address bit (32x1 mode).
A separate Global Set/Reset line (not shown in Figure 1)
sets or clears each storage element during power-up,
re-configuration, or when a dedicated Reset net is driven
active. This global net (GSR) does not compete with other
routing resources; it uses a dedicated distribution network.
6
Each flip-flop is configured as either globally set or reset in
the same way that the local set/reset (SR) is specified.
Therefore, if a flip-flop is set by SR, it is also set by GSR.
Similarly, a reset flip-flop is reset by both SR and GSR.
Using FPGA Flip-Flops and Latches
The abundance of flip-flops in the XC4000 Series invites
pipelined designs. This is a powerful way of increasing per-
formance by breaking the function into smaller subfunc-
tions and executing them in parallel, passing on the results
through pipeline flip-flops. This method should be seriously
considered wherever throughput is more important than
latency.
STARTUP
GSR
GTS
PAD
Q2
Q3
Q1Q4
IBUF
To include a CLB flip-flop, place the appropriate library
symbol. For example, FDCE is a D-type flip-flop with clock
enable and asynchronous clear. The corresponding latch
symbol (for the XC4000X only) is called LDCE.
DONEIN
CLK
X5260
Figure 2: Schematic Symbols for Global Set/Reset
In XC4000 Series devices, the flip flops can be used as reg-
isters or shift registers without blocking the function gener-
ators from performing a different, perhaps unrelated task.
This ability increases the functional capacity of the devices.
GSR can be driven from any user-programmable pin as a
global reset input. To use this global net, place an input pad
and input buffer in the schematic or HDL code, driving the
GSR pin of the STARTUP symbol. (See Figure 2.) A spe-
cific pin location can be assigned to this input using a LOC
attribute or property, just as with any other user-program-
mable pad. An inverter can optionally be inserted after the
input buffer to invert the sense of the Global Set/Reset sig-
nal.
The CLB setup time is specified between the function gen-
erator inputs and the clock input K. Therefore, the specified
CLB flip-flop setup time includes the delay through the
function generator.
Using Function Generators as RAM
Optional modes for each CLB make the memory look-up
tables in the F’ and G’ function generators usable as an
array of Read/Write memory cells. Available modes are
level-sensitive (similar to the XC4000/A/H families),
edge-triggered, and dual-port edge-triggered. Depending
on the selected mode, a single CLB can be configured as
either a 16x2, 32x1, or 16x1 bit array.
Alternatively, GSR can be driven from any internal node.
Data Inputs and Outputs
The source of a storage element data input is programma-
ble. It is driven by any of the functions F’, G’, and H’, or by
the Direct In (DIN) block input. The flip-flops or latches drive
the XQ and YQ CLB outputs.
May 14, 1999 (Version 1.6)
6-11
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Supported CLB memory configurations and timing modes
for single- and dual-port modes are shown in Table 3.
The selected timing mode applies to both function genera-
tors within a CLB when both are configured as RAM.
XC4000 Series devices are the first programmable logic
devices with edge-triggered (synchronous) and dual-port
RAM accessible to the user. Edge-triggered RAM simpli-
fies system timing. Dual-port RAM doubles the effective
throughput of FIFO applications. These features can be
individually programmed in any XC4000 Series CLB.
The number of read ports is also programmable:
•
Single Port: each function generator has a common
read and write port
•
Dual Port: both function generators are configured
together as a single 16x1 dual-port RAM with one write
port and two read ports. Simultaneous read and write
operations to the same or different addresses are
supported.
Advantages of On-Chip and Edge-Triggered RAM
The on-chip RAM is extremely fast. The read access time is
the same as the logic delay. The write access time is
slightly slower. Both access times are much faster than
any off-chip solution, because they avoid I/O delays.
RAM configuration options are selected by placing the
appropriate library symbol.
Choosing a RAM Configuration Mode
Edge-triggered RAM, also called synchronous RAM, is a
feature never before available in a Field Programmable
Gate Array. The simplicity of designing with edge-triggered
RAM, and the markedly higher achievable performance,
add up to a significant improvement over existing devices
with on-chip RAM.
The appropriate choice of RAM mode for a given design
should be based on timing and resource requirements,
desired functionality, and the simplicity of the design pro-
cess. Recommended usage is shown in Table 4.
The difference between level-sensitive, edge-triggered,
and dual-port RAM is only in the write operation. Read
operation and timing is identical for all modes of operation.
Three application notes are available from Xilinx that dis-
cuss edge-triggered RAM: “XC4000E Edge-Triggered and
Dual-Port RAM Capability,” “Implementing FIFOs in
XC4000E RAM,” and “Synchronous and Asynchronous
FIFO Designs.” All three application notes apply to both
XC4000E and XC4000X RAM.
Table 4: RAM Mode Selection
Dual-Port
Level-Sens Edge-Trigg Edge-Trigg
itive
ered
ered
Table 3: Supported RAM Modes
Use for New
Designs?
No
Yes
Yes
16
x
16
x
32
x
Edge-
Triggered Sensitive
Timing
Level-
Size (16x1,
Registered)
1/2 CLB
1/2 CLB
No
1 CLB
Yes
1
2
1
Timing
Simultaneous
Read/Write
Single-Port
Dual-Port
√
√
√
√
√
√
√
No
X
Relative
Performance
2X (4X
effective)
2X
RAM Configuration Options
The function generators in any CLB can be configured as
RAM arrays in the following sizes:
RAM Inputs and Outputs
The F1-F4 and G1-G4 inputs to the function generators act
as address lines, selecting a particular memory cell in each
look-up table.
•
Two 16x1 RAMs: two data inputs and two data outputs
with identical or, if preferred, different addressing for
each RAM
The functionality of the CLB control signals changes when
the function generators are configured as RAM. The
DIN/H2, H1, and SR/H0 lines become the two data inputs
(D0, D1) and the Write Enable (WE) input for the 16x2
memory. When the 32x1 configuration is selected, D1 acts
as the fifth address bit and D0 is the data input.
•
One 32x1 RAM: one data input and one data output.
One F or G function generator can be configured as a 16x1
RAM while the other function generators are used to imple-
ment any function of up to 5 inputs.
Additionally, the XC4000 Series RAM may have either of
two timing modes:
The contents of the memory cell(s) being addressed are
available at the F’ and G’ function-generator outputs. They
can exit the CLB through its X and Y outputs, or can be cap-
tured in the CLB flip-flop(s).
•
Edge-Triggered (Synchronous): data written by the
designated edge of the CLB clock. WE acts as a true
clock enable.
•
Level-Sensitive (Asynchronous): an external WE signal
acts as the write strobe.
Configuring the CLB function generators as Read/Write
memory does not affect the functionality of the other por-
6-12
May 14, 1999 (Version 1.6)
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
tions of the CLB, with the exception of the redefinition of the
control signals. In 16x2 and 16x1 modes, the H’ function
generator can be used to implement Boolean functions of
F’, G’, and D1, and the D flip-flops can latch the F’, G’, H’, or
D0 signals.
nals. An internal write pulse is generated that performs the
write. See Figure 4 and Figure 5 for block diagrams of a
CLB configured as 16x2 and 32x1 edge-triggered, sin-
gle-port RAM.
The relationships between CLB pins and RAM inputs and
outputs for single-port, edge-triggered mode are shown in
Table 5.
Single-Port Edge-Triggered Mode
Edge-triggered (synchronous) RAM simplifies timing
requirements. XC4000 Series edge-triggered RAM timing
operates like writing to a data register. Data and address
are presented. The register is enabled for writing by a logic
High on the write enable input, WE. Then a rising or falling
clock edge loads the data into the register, as shown in
Figure 3.
The Write Clock input (WCLK) can be configured as active
on either the rising edge (default) or the falling edge. It uses
the same CLB pin (K) used to clock the CLB flip-flops, but it
can be independently inverted. Consequently, the RAM
output can optionally be registered within the same CLB
either by the same clock edge as the RAM, or by the oppo-
site edge of this clock. The sense of WCLK applies to both
function generators in the CLB when both are configured
as RAM.
TWPS
WCLK (K)
TWHS
The WE pin is active-High and is not invertible within the
CLB.
TWSS
WE
Note: The pulse following the active edge of WCLK (TWPS
in Figure 3) must be less than one millisecond wide. For
most applications, this requirement is not overly restrictive;
however, it must not be forgotten. Stopping WCLK at this
point in the write cycle could result in excessive current and
even damage to the larger devices if many CLBs are con-
figured as edge-triggered RAM.
TDHS
TDSS
DATA IN
6
TASS
TAHS
ADDRESS
Table 5: Single-Port Edge-Triggered RAM Signals
TILO
TILO
RAM Signal
CLB Pin
Function
Data In
TWOS
D
D0 or D1 (16x2,
16x1), D0 (32x1)
DATA OUT
OLD
NEW
A[3:0]
A[4]
F1-F4 or G1-G4
Address
Address
Write Enable
Clock
X6461
D1 (32x1)
WE
Figure 3: Edge-Triggered RAM Write Timing
WE
Complex timing relationships between address, data, and
write enable signals are not required, and the external write
enable pulse becomes a simple clock enable. The active
edge of WCLK latches the address, input data, and WE sig-
WCLK
K
SPO
(Data Out)
F’ or G’
Single Port Out
(Data Out)
May 14, 1999 (Version 1.6)
6-13
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
4
C
• • • C
4
1
EC
D
D
0
WE
1
D
IN
WRITE
DECODER
16-LATCH
ARRAY
G'
MUX
4
4
G
• • • G
4
1
1 of 16
LATCH
ENABLE
READ
ADDRESS
WRITE PULSE
D
IN
WRITE
DECODER
16-LATCH
ARRAY
F'
MUX
4
4
F
• • • F
1
4
1 of 16
LATCH
ENABLE
K
READ
ADDRESS
(CLOCK)
WRITE PULSE
X6752
Figure 4: 16x2 (or 16x1) Edge-Triggered Single-Port RAM
4
C
• • • C
1
4
EC
EC
D /A
D
0
WE
1
4
D
IN
WRITE
DECODER
16-LATCH
ARRAY
G'
MUX
G
F
• • • G
• • • F
4
4
1
1
4
4
1 of 16
LATCH
ENABLE
READ
ADDRESS
WRITE PULSE
H'
D
IN
WRITE
DECODER
16-LATCH
ARRAY
F'
MUX
4
4
1 of 16
LATCH
ENABLE
K
READ
ADDRESS
(CLOCK)
WRITE PULSE
X6754
Figure 5: 32x1 Edge-Triggered Single-Port RAM (F and G addresses are identical)
6-14
May 14, 1999 (Version 1.6)
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Dual-Port Edge-Triggered Mode
Table 6: Dual-Port Edge-Triggered RAM Signals
In dual-port mode, both the F and G function generators
are used to create a single 16x1 RAM array with one write
port and two read ports. The resulting RAM array can be
read and written simultaneously at two independent
addresses. Simultaneous read and write operations at the
same address are also supported.
RAM Signal
D
A[3:0]
CLB Pin
D0
F1-F4
Function
Data In
Read Address for F,
Write Address for F and G
Read Address for G
Write Enable
DPRA[3:0]
WE
WCLK
SPO
G1-G4
WE
K
Clock
Dual-port mode always has edge-triggered write timing, as
shown in Figure 3.
F’
Single Port Out
(addressed by A[3:0])
Dual Port Out
Figure 6 shows a simple model of an XC4000 Series CLB
configured as dual-port RAM. One address port, labeled
A[3:0], supplies both the read and write address for the F
function generator. This function generator behaves the
same as a 16x1 single-port edge-triggered RAM array. The
RAM output, Single Port Out (SPO), appears at the F func-
tion generator output. SPO, therefore, reflects the data at
address A[3:0].
DPO
G’
(addressed by DPRA[3:0])
Note: The pulse following the active edge of WCLK (TWPS
in Figure 3) must be less than one millisecond wide. For
most applications, this requirement is not overly restrictive;
however, it must not be forgotten. Stopping WCLK at this
point in the write cycle could result in excessive current and
even damage to the larger devices if many CLBs are con-
figured as edge-triggered RAM.
The other address port, labeled DPRA[3:0] for Dual Port
Read Address, supplies the read address for the G function
generator. The write address for the G function generator,
however, comes from the address A[3:0]. The output from
this 16x1 RAM array, Dual Port Out (DPO), appears at the
G function generator output. DPO, therefore, reflects the
data at address DPRA[3:0].
Single-Port Level-Sensitive Timing Mode
Note: Edge-triggered mode is recommended for all new
designs. Level-sensitive mode, also called asynchronous
mode, is still supported for XC4000 Series backward-com-
patibility with the XC4000 family.
6
Therefore, by using A[3:0] for the write address and
DPRA[3:0] for the read address, and reading only the DPO
output, a FIFO that can read and write simultaneously is
easily generated. Simultaneous access doubles the effec-
tive throughput of the FIFO.
Level-sensitive RAM timing is simple in concept but can be
complicated in execution. Data and address signals are
presented, then a positive pulse on the write enable pin
(WE) performs a write into the RAM at the designated
address. As indicated by the “level-sensitive” label, this
RAM acts like a latch. During the WE High pulse, changing
the data lines results in new data written to the old address.
Changing the address lines while WE is High results in spu-
rious data written to the new address—and possibly at
other addresses as well, as the address lines inevitably do
not all change simultaneously.
The relationships between CLB pins and RAM inputs and
outputs for dual-port, edge-triggered mode are shown in
Table 6. See Figure 7 on page 16 for a block diagram of a
CLB configured in this mode.
RAM16X1D Primitive
DPO (Dual Port Out)
The user must generate a carefully timed WE signal. The
delay on the WE signal and the address lines must be care-
fully verified to ensure that WE does not become active
until after the address lines have settled, and that WE goes
inactive before the address lines change again. The data
must be stable before and after the falling edge of WE.
WE
WE
D
Registered DPO
D
D
Q
DPRA[3:0]
AR[3:0]
AW[3:0]
G Function Generator
SPO (Single Port Out)
Registered SPO
In practical terms, WE is usually generated by a 2X clock. If
a 2X clock is not available, the falling edge of the system
clock can be used. However, there are inherent risks in this
approach, since the WE pulse must be guaranteed inactive
before the next rising edge of the system clock. Several
older application notes are available from Xilinx that dis-
cuss the design of level-sensitive RAMs. These application
notes include XAPP031, “Using the XC4000 RAM Capabil-
ity,” and XAPP042, “High-Speed RAM Design in XC4000.”
However, the edge-triggered RAM available in the XC4000
Series is superior to level-sensitive RAM for almost every
application.
WE
D
Q
D
A[3:0]
AR[3:0]
AW[3:0]
F Function Generator
WCLK
X6755
Figure 6: XC4000 Series Dual-Port RAM, Simple
Model
May 14, 1999 (Version 1.6)
6-15
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
4
C
• • • C
4
1
EC
D
D
0
WE
1
D
IN
WRITE
DECODER
16-LATCH
ARRAY
G'
MUX
4
1 of 16
LATCH
ENABLE
READ
ADDRESS
WRITE PULSE
4
G
• • • G
4
1
D
IN
WRITE
DECODER
16-LATCH
ARRAY
F'
MUX
4
4
F
• • • F
4
1
1 of 16
LATCH
ENABLE
K
READ
ADDRESS
(CLOCK)
WRITE PULSE
X6748
Figure 7: 16x1 Edge-Triggered Dual-Port RAM
Figure 8 shows the write timing for level-sensitive, sin-
gle-port RAM.
attached to the RAM or ROM symbol, as described in the
schematic library guide. If not defined, all RAM contents
are initialized to all zeros, by default.
The relationships between CLB pins and RAM inputs and
outputs for single-port level-sensitive mode are shown in
Table 7.
RAM initialization occurs only during configuration. The
RAM content is not affected by Global Set/Reset.
Figure 9 and Figure 10 show block diagrams of a CLB con-
figured as 16x2 and 32x1 level-sensitive, single-port RAM.
Table 7: Single-Port Level-Sensitive RAM Signals
RAM Signal
CLB Pin
D0 or D1
Function
Data In
D
Initializing RAM at Configuration
A[3:0]
WE
O
F1-F4 or G1-G4
WE
F’ or G’
Address
Write Enable
Data Out
Both RAM and ROM implementations of the XC4000
Series devices are initialized during configuration. The ini-
tial contents are defined via an INIT attribute or property
T
WC
ADDRESS
T
AS
T
T
WP
AH
T
WRITE ENABLE
DATA IN
T
DH
DS
REQUIRED
X6462
Figure 8: Level-Sensitive RAM Write Timing
6-16
May 14, 1999 (Version 1.6)
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
4
C
• • • C
1
4
EC
D
WE
D
1
0
D
IN
Enable
WRITE
DECODER
16-LATCH
ARRAY
G'
MUX
4
G
• • • G
4
1
1 of 16
4
READ ADDRESS
D
IN
Enable
WRITE
DECODER
16-LATCH
ARRAY
F'
MUX
4
F
• • • F
4
1
1 of 16
4
READ ADDRESS
X6746
6
Figure 9: 16x2 (or 16x1) Level-Sensitive Single-Port RAM
4
C
• • • C
1
4
EC
D /A
D
0
WE
1
4
D
IN
Enable
WRITE
DECODER
16-LATCH
ARRAY
G'
MUX
G
F
• • • G
• • • F
4
1
1
4
4
1 of 16
4
READ ADDRESS
H'
D
IN
Enable
WRITE
DECODER
16-LATCH
ARRAY
F'
MUX
4
1 of 16
4
READ ADDRESS
X6749
Figure 10: 32x1 Level-Sensitive Single-Port RAM (F and G addresses are identical)
May 14, 1999 (Version 1.6)
6-17
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000.” This discussion also applies to XC4000E
devices, and to XC4000X devices when the minor logic
changes are taken into account.
Fast Carry Logic
Each CLB F and G function generator contains dedicated
arithmetic logic for the fast generation of carry and borrow
signals. This extra output is passed on to the function gen-
erator in the adjacent CLB. The carry chain is independent
of normal routing resources.
The fast carry logic can be accessed by placing special
library symbols, or by using Xilinx Relationally Placed Mac-
ros (RPMs) that already include these symbols.
Dedicated fast carry logic greatly increases the efficiency
and performance of adders, subtractors, accumulators,
comparators and counters. It also opens the door to many
new applications involving arithmetic operation, where the
previous generations of FPGAs were not fast enough or too
inefficient. High-speed address offset calculations in micro-
processor or graphics systems, and high-speed addition in
digital signal processing are two typical applications.
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
The two 4-input function generators can be configured as a
2-bit adder with built-in hidden carry that can be expanded
to any length. This dedicated carry circuitry is so fast and
efficient that conventional speed-up methods like carry
generate/propagate are meaningless even at the 16-bit
level, and of marginal benefit at the 32-bit level.
This fast carry logic is one of the more significant features
of the XC4000 Series, speeding up arithmetic and counting
into the 70 MHz range.
The carry chain in XC4000E devices can run either up or
down. At the top and bottom of the columns where there
are no CLBs above or below, the carry is propagated to the
right. (See Figure 11.) In order to improve speed in the
high-capacity XC4000X devices, which can potentially
have very long carry chains, the carry chain travels upward
only, as shown in Figure 12. Additionally, standard intercon-
nect can be used to route a carry signal in the downward
direction.
X6687
Figure 11: Available XC4000E Carry Propagation
Paths
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
Figure 13 on page 19 shows an XC4000E CLB with dedi-
cated fast carry logic. The carry logic in the XC4000X is
similar, except that COUT exits at the top only, and the sig-
nal CINDOWN does not exist. As shown in Figure 13, the
carry logic shares operand and control inputs with the func-
tion generators. The carry outputs connect to the function
generators, where they are combined with the operands to
form the sums.
Figure 14 on page 20 shows the details of the carry logic
for the XC4000E. This diagram shows the contents of the
box labeled “CARRY LOGIC” in Figure 13. The XC4000X
carry logic is very similar, but a multiplexer on the
pass-through carry chain has been eliminated to reduce
delay. Additionally, in the XC4000X the multiplexer on the
G4 path has a memory-programmable 0 input, which per-
mits G4 to directly connect to COUT. G4 thus becomes an
additional high-speed initialization path for carry-in.
X6610
Figure 12: Available XC4000X Carry Propagation
Paths (dotted lines use general interconnect)
The dedicated carry logic is discussed in detail in Xilinx
document XAPP 013: “Using the Dedicated Carry Logic in
6-18
May 14, 1999 (Version 1.6)
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
D
C
C
IN
IN
OUT
DOWN
CARRY
LOGIC
G
Y
H
G
CARRY
G4
G3
G2
G
DIN
S/R
EC
H
G
F
D
Q
YQ
G1
H1
C
OUT0
6
H
DIN
H
S/R
EC
F
CARRY
D
Q
XQ
G
F
F4
F3
F2
F1
F
H
F
X
K
S/R
EC
C
C
OUT
INUP
X6699
Figure 13: Fast Carry Logic in XC4000E CLB (shaded area not present in XC4000X)
May 14, 1999 (Version 1.6)
6-19
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
C
OUT
M
G1
M
1
0
1
G2
G3
0
I
G4
C
OUT0
TO
FUNCTION
GENERATORS
M
F2
F1
M
1
0
0
1
M
F4
M
M
0
1
3
1
0
F3
M
M
M
M
1
0
C
INUP
C
X2000
IN DOWN
Figure 14: Detail of XC4000E Dedicated Carry Logic
The choice is made by placing the appropriate library sym-
bol. For example, IFD is the basic input flip-flop (rising edge
triggered), and ILD is the basic input latch (transpar-
ent-High). Variations with inverted clocks are available, and
some combinations of latches and flip-flops can be imple-
mented in a single IOB, as described in the XACT Libraries
Guide.
Input/Output Blocks (IOBs)
User-configurable input/output blocks (IOBs) provide the
interface between external package pins and the internal
logic. Each IOB controls one package pin and can be con-
figured for input, output, or bidirectional signals.
Figure 15 shows a simplified block diagram of the
XC4000E IOB. A more complete diagram which includes
the boundary scan logic of the XC4000E IOB can be found
in Figure 40 on page 43, in the “Boundary Scan” section.
The XC4000E inputs can be globally configured for either
TTL (1.2V) or 5.0 volt CMOS thresholds, using an option in
the bitstream generation software. There is a slight input
hysteresis of about 300mV. The XC4000E output levels are
also configurable; the two global adjustments of input
threshold and output level are independent.
The XC4000X IOB contains some special features not
included in the XC4000E IOB. These features are high-
lighted in a simplified block diagram found in Figure 16, and
discussed throughout this section. When XC4000X special
features are discussed, they are clearly identified in the
text. Any feature not so identified is present in both
XC4000E and XC4000X devices.
Inputs on the XC4000XL are TTL compatible and 3.3V
CMOS compatible. Outputs on the XC4000XL are pulled to
the 3.3V positive supply.
The inputs of XC4000 Series 5-Volt devices can be driven
by the outputs of any 3.3-Volt device, if the 5-Volt inputs are
in TTL mode.
IOB Input Signals
Two paths, labeled I1 and I2 in Figure 15 and Figure 16,
bring input signals into the array. Inputs also connect to an
input register that can be programmed as either an
edge-triggered flip-flop or a level-sensitive latch.
Supported sources for XC4000 Series device inputs are
shown in Table 8.
6-20
May 14, 1999 (Version 1.6)
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Passive
Slew Rate
Control
Pull-Up/
Pull-Down
T
Flip-Flop
D
Q
Out
Output
Buffer
CE
Pad
Output
Clock
I
1
Input
Buffer
Flip-
Flop/
Latch
I
2
Q
D
Delay
Clock
Enable
CE
Input
Clock
6
X6704
Figure 15: Simplified Block Diagram of XC4000E IOB
Passive
Pull-Up/
Pull-Down
Slew Rate
Control
T
Output MUX
0
1
Flip-Flop
Out
D
Q
Output
Buffer
CE
Pad
Input
Buffer
Output Clock
I
I
1
2
Flip-Flop/
Latch
Delay
Q
Delay
Q
D
D
Latch
G
Clock Enable
Input Clock
CE
Fast
Capture
Latch
X5984
Figure 16: Simplified Block Diagram of XC4000X IOB (shaded areas indicate differences from XC4000E)
May 14, 1999 (Version 1.6)
6-21
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XC4000E and XC4000X Series Field Programmable Gate Arrays
Table 8: Supported Sources for XC4000 Series Device
Inputs
Optional Delay Guarantees Zero Hold Time
The data input to the register can optionally be delayed by
several nanoseconds. With the delay enabled, the setup
time of the input flip-flop is increased so that normal clock
routing does not result in a positive hold-time requirement.
A positive hold time requirement can lead to unreliable,
temperature- or processing-dependent operation.
XC4000E/EX XC4000XL
Series Inputs Series Inputs
Source
5 V,
5 V,
3.3 V
TTL CMOS
CMOS
Any device, Vcc = 3.3 V,
CMOS outputs
√
√
√
√
√
The input flip-flop setup time is defined between the data
measured at the device I/O pin and the clock input at the
IOB (not at the clock pin). Any routing delay from the device
clock pin to the clock input of the IOB must, therefore, be
subtracted from this setup time to arrive at the real setup
time requirement relative to the device pins. A short speci-
fied setup time might, therefore, result in a negative setup
time at the device pins, i.e., a positive hold-time require-
ment.
Unreli
-able
Data
XC4000 Series, Vcc = 5 V,
TTL outputs
√
√
√
Any device, Vcc = 5 V,
TTL outputs (Voh ≤ 3.7 V)
Any device, Vcc = 5 V,
CMOS outputs
√
XC4000XL 5-Volt Tolerant I/Os
When a delay is inserted on the data line, more clock delay
can be tolerated without causing a positive hold-time
requirement. Sufficient delay eliminates the possibility of a
data hold-time requirement at the external pin. The maxi-
mum delay is therefore inserted as the default.
The I/Os on the XC4000XL are fully 5-volt tolerant even
though the VCC is 3.3 volts. This allows 5 V signals to
directly connect to the XC4000XL inputs without damage,
as shown in Table 8. In addition, the 3.3 volt VCC can be
applied before or after 5 volt signals are applied to the I/Os.
This makes the XC4000XL immune to power supply
sequencing problems.
The XC4000E IOB has a one-tap delay element: either the
delay is inserted (default), or it is not. The delay guarantees
a zero hold time with respect to clocks routed through any
of the XC4000E global clock buffers. (See “Global Nets and
Buffers (XC4000E only)” on page 35 for a description of the
global clock buffers in the XC4000E.) For a shorter input
register setup time, with non-zero hold, attach a NODELAY
attribute or property to the flip-flop.
Registered Inputs
The I1 and I2 signals that exit the block can each carry
either the direct or registered input signal.
The input and output storage elements in each IOB have a
common clock enable input, which, through configuration,
can be activated individually for the input or output flip-flop,
or both. This clock enable operates exactly like the EC pin
on the XC4000 Series CLB. It cannot be inverted within the
IOB.
The XC4000X IOB has a two-tap delay element, with
choices of a full delay, a partial delay, or no delay. The
attributes or properties used to select the desired delay are
shown in Table 10. The choices are no added attribute,
MEDDELAY, and NODELAY. The default setting, with no
added attribute, ensures no hold time with respect to any of
the XC4000X clock buffers, including the Global Low-Skew
buffers. MEDDELAY ensures no hold time with respect to
the Global Early buffers. Inputs with NODELAY may have a
positive hold time with respect to all clock buffers. For a
description of each of these buffers, see “Global Nets and
Buffers (XC4000X only)” on page 37.
The storage element behavior is shown in Table 9.
Table 9: Input Register Functionality
(active rising edge is shown)
Clock
Enable
Mode
Clock
D
Q
Power-Up or
GSR
X
X
X
SR
Table 10: XC4000X IOB Input Delay Element
Flip-Flop
__/
0
1*
X
D
X
X
D
X
D
Q
Q
D
Q
Value
full delay
When to Use
Latch
1
1*
1*
0
Zero Hold with respect to Global
0
(default, no
Low-Skew Buffer, Global Early Buffer
attribute added)
Both
X
Legend:
MEDDELAY
Zero Hold with respect to Global Early
Buffer
X
Don’t care
Rising edge
Set or Reset value. Reset is default.
Input is Low or unconnected (default value)
Input is High or unconnected (default value)
__/
SR
0*
NODELAY
Short Setup, positive Hold time
1*
6-22
May 14, 1999 (Version 1.6)
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Additional Input Latch for Fast Capture (XC4000X only)
the desired delay based on the discussion in the previous
subsection.
The XC4000X IOB has an additional optional latch on the
input. This latch, as shown in Figure 16, is clocked by the
output clock — the clock used for the output flip-flop —
rather than the input clock. Therefore, two different clocks
can be used to clock the two input storage elements. This
additional latch allows the very fast capture of input data,
which is then synchronized to the internal clock by the IOB
flip-flop or latch.
IOB Output Signals
Output signals can be optionally inverted within the IOB,
and can pass directly to the pad or be stored in an
edge-triggered flip-flop. The functionality of this flip-flop is
shown in Table 11.
An active-High 3-state signal can be used to place the out-
put buffer in a high-impedance state, implementing 3-state
outputs or bidirectional I/O. Under configuration control, the
output (OUT) and output 3-state (T) signals can be
inverted. The polarity of these signals is independently con-
figured for each IOB.
To use this Fast Capture technique, drive the output clock
pin (the Fast Capture latching signal) from the output of one
of the Global Early buffers supplied in the XC4000X. The
second storage element should be clocked by a Global
Low-Skew buffer, to synchronize the incoming data to the
internal logic. (See Figure 17.) These special buffers are
described in “Global Nets and Buffers (XC4000X only)” on
page 37.
The 4-mA maximum output current specification of many
FPGAs often forces the user to add external buffers, which
are especially cumbersome on bidirectional I/O lines. The
XC4000E and XC4000EX/XL devices solve many of these
problems by providing a guaranteed output sink current of
12 mA. Two adjacent outputs can be interconnected exter-
nally to sink up to 24 mA. The XC4000E and XC4000EX/XL
FPGAs can thus directly drive buses on a printed circuit
board.
The Fast Capture latch (FCL) is designed primarily for use
with a Global Early buffer. For Fast Capture, a single clock
signal is routed through both a Global Early buffer and a
Global Low-Skew buffer. (The two buffers share an input
pad.) The Fast Capture latch is clocked by the Global Early
buffer, and the standard IOB flip-flop or latch is clocked by
the Global Low-Skew buffer. This mode is the safest way to
use the Fast Capture latch, because the clock buffers on
both storage elements are driven by the same pad. There is
no external skew between clock pads to create potential
problems.
6
By default, the output pull-up structure is configured as a
TTL-like totem-pole. The High driver is an n-channel pull-up
transistor, pulling to a voltage one transistor threshold
below Vcc. Alternatively, the outputs can be globally config-
ured as CMOS drivers, with p-channel pull-up transistors
pulling to Vcc. This option, applied using the bitstream gen-
eration software, applies to all outputs on the device. It is
not individually programmable. In the XC4000XL, all out-
puts are pulled to the positive supply rail.
To place the Fast Capture latch in a design, use one of the
special library symbols, ILFFX or ILFLX. ILFFX is a trans-
parent-Low Fast Capture latch followed by an active-High
input flip-flop. ILFLX is a transparent-Low Fast Capture
latch followed by a transparent-High input latch. Any of the
clock inputs can be inverted before driving the library ele-
ment, and the inverter is absorbed into the IOB. If a single
BUFG output is used to drive both clock inputs, the soft-
ware automatically runs the clock through both a Global
Low-Skew buffer and a Global Early buffer, and clocks the
Fast Capture latch appropriately.
Table 11: Output Flip-Flop Functionality (active rising
edge is shown)
Clock
Mode
Clock
Enable
T
D
Q
Power-Up
or GSR
X
X
0*
X
SR
Figure 16 on page 21 also shows a two-tap delay on the
input. By default, if the Fast Capture latch is used, the Xilinx
software assumes a Global Early buffer is driving the clock,
and selects MEDDELAY to ensure a zero hold time. Select
X
__/
X
0
1*
X
0*
0*
1
X
D
X
X
Q
D
Z
Flip-Flop
0
X
0*
Q
Legend:
ILFFX
X
__/
SR
0*
Don’t care
Rising edge
to internal
logic
IPAD
D
Q
Set or Reset value. Reset is default.
Input is Low or unconnected (default value)
Input is High or unconnected (default value)
3-state
GF
1*
Z
BUFGE
CE
C
IPAD
BUFGLS
X9013
Figure 17: Examples Using XC4000X FCL
May 14, 1999 (Version 1.6)
6-23
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XC4000E and XC4000X Series Field Programmable Gate Arrays
Any XC4000 Series 5-Volt device with its outputs config-
ured in TTL mode can drive the inputs of any typical
3.3-Volt device. (For a detailed discussion of how to inter-
face between 5 V and 3.3 V devices, see the 3V Products
section of The Programmable Logic Data Book.)
Power/Ground pin pairs are connected to special Power
and Ground planes within the packages, to reduce ground
bounce. Therefore, the maximum total capacitive load is
300 pF between each external Power/Ground pin pair.
Maximum loading may vary for the low-voltage devices.
Supported destinations for XC4000 Series device outputs
are shown in Table 12.
For slew-rate limited outputs this total is two times larger for
each device type: 400 pF for XC4000E devices and 600 pF
for XC4000X devices. This maximum capacitive load
should not be exceeded, as it can result in ground bounce
of greater than 1.5 V amplitude and more than 5 ns dura-
tion. This level of ground bounce may cause undesired
transient behavior on an output, or in the internal logic. This
restriction is common to all high-speed digital ICs, and is
not particular to Xilinx or the XC4000 Series.
An output can be configured as open-drain (open-collector)
by placing an OBUFT symbol in a schematic or HDL code,
then tying the 3-state pin (T) to the output signal, and the
input pin (I) to Ground. (See Figure 18.)
Table 12: Supported Destinations for XC4000 Series
Outputs
XC4000 Series devices have a feature called “Soft
Start-up,” designed to reduce ground bounce when all out-
puts are turned on simultaneously at the end of configura-
tion. When the configuration process is finished and the
device starts up, the first activation of the outputs is auto-
matically slew-rate limited. Immediately following the initial
activation of the I/O, the slew rate of the individual outputs
is determined by the individual configuration option for each
IOB.
XC4000 Series
Outputs
Destination
3.3 V,
5 V,
5 V,
CMOS TTL CMOS
Any typical device, Vcc = 3.3 V,
CMOS-threshold inputs
√
√
√
√
some1
Any device, Vcc = 5 V,
TTL-threshold inputs
√
√
Any device, Vcc = 5 V,
CMOS-threshold inputs
Unreliable
Data
Global Three-State
1. Only if destination device has 5-V tolerant inputs
A separate Global 3-State line (not shown in Figure 15 or
Figure 16) forces all FPGA outputs to the high-impedance
state, unless boundary scan is enabled and is executing an
EXTEST instruction. This global net (GTS) does not com-
pete with other routing resources; it uses a dedicated distri-
bution network.
OPAD
OBUFT
X6702
GTS can be driven from any user-programmable pin as a
global 3-state input. To use this global net, place an input
pad and input buffer in the schematic or HDL code, driving
the GTS pin of the STARTUP symbol. A specific pin loca-
tion can be assigned to this input using a LOC attribute or
property, just as with any other user-programmable pad. An
inverter can optionally be inserted after the input buffer to
invert the sense of the Global 3-State signal. Using GTS is
similar to GSR. See Figure 2 on page 11 for details.
Figure 18: Open-Drain Output
Output Slew Rate
The slew rate of each output buffer is, by default, reduced,
to minimize power bus transients when switching non-criti-
cal signals. For critical signals, attach a FAST attribute or
property to the output buffer or flip-flop.
For XC4000E devices, maximum total capacitive load for
simultaneous fast mode switching in the same direction is
200 pF for all package pins between each Power/Ground
pin pair. For XC4000X devices, additional internal
Alternatively, GTS can be driven from any internal node.
6-24
May 14, 1999 (Version 1.6)
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Output Multiplexer/2-Input Function Generator
(XC4000X only)
Other IOB Options
There are a number of other programmable options in the
XC4000 Series IOB.
As shown in Figure 16 on page 21, the output path in the
XC4000X IOB contains an additional multiplexer not avail-
able in the XC4000E IOB. The multiplexer can also be con-
figured as a 2-input function generator, implementing a
pass-gate, AND-gate, OR-gate, or XOR-gate, with 0, 1, or 2
inverted inputs. The logic used to implement these func-
tions is shown in the upper gray area of Figure 16.
Pull-up and Pull-down Resistors
Programmable pull-up and pull-down resistors are useful
for tying unused pins to Vcc or Ground to minimize power
consumption and reduce noise sensitivity. The configurable
pull-up resistor is a p-channel transistor that pulls to Vcc.
The configurable pull-down resistor is an n-channel transis-
tor that pulls to Ground.
When configured as a multiplexer, this feature allows two
output signals to time-share the same output pad; effec-
tively doubling the number of device outputs without requir-
ing a larger, more expensive package.
The value of these resistors is 50 kΩ − 100 kΩ. This high
value makes them unsuitable as wired-AND pull-up resis-
tors.
When the MUX is configured as a 2-input function genera-
tor, logic can be implemented within the IOB itself. Com-
bined with a Global Early buffer, this arrangement allows
very high-speed gating of a single signal. For example, a
wide decoder can be implemented in CLBs, and its output
gated with a Read or Write Strobe Driven by a BUFGE
buffer, as shown in Figure 19. The critical-path pin-to-pin
delay of this circuit is less than 6 nanoseconds.
The pull-up resistors for most user-programmable IOBs are
active during the configuration process. See Table 22 on
page 58 for a list of pins with pull-ups active before and dur-
ing configuration.
After configuration, voltage levels of unused pads, bonded
or un-bonded, must be valid logic levels, to reduce noise
sensitivity and avoid excess current. Therefore, by default,
unused pads are configured with the internal pull-up resis-
tor active. Alternatively, they can be individually configured
with the pull-down resistor, or as a driven output, or to be
driven by an external source. To activate the internal
pull-up, attach the PULLUP library component to the net
attached to the pad. To activate the internal pull-down,
attach the PULLDOWN library component to the net
attached to the pad.
As shown in Figure 16, the IOB input pins Out, Output
Clock, and Clock Enable have different delays and different
flexibilities regarding polarity. Additionally, Output Clock
sources are more limited than the other inputs. Therefore,
the Xilinx software does not move logic into the IOB func-
tion generators unless explicitly directed to do so.
6
The user can specify that the IOB function generator be
used, by placing special library symbols beginning with the
letter “O.” For example, a 2-input AND-gate in the IOB func-
tion generator is called OAND2. Use the symbol input pin
labelled “F” for the signal on the critical path. This signal is
placed on the OK pin — the IOB input with the shortest
delay to the function generator. Two examples are shown in
Figure 20.
Independent Clocks
Separate clock signals are provided for the input and output
flip-flops. The clock can be independently inverted for each
flip-flop within the IOB, generating either falling-edge or ris-
ing-edge triggered flip-flops. The clock inputs for each IOB
are independent, except that in the XC4000X, the Fast
Capture latch shares an IOB input with the output clock pin.
IPAD
Early Clock for IOBs (XC4000X only)
BUFGE
F
Special early clocks are available for IOBs. These clocks
are sourced by the same sources as the Global Low-Skew
buffers, but are separately buffered. They have fewer loads
and therefore less delay. The early clock can drive either
the IOB output clock or the IOB input clock, or both. The
early clock allows fast capture of input data, and fast
clock-to-output on output data. The Global Early buffers
that drive these clocks are described in “Global Nets and
Buffers (XC4000X only)” on page 37.
OPAD
from
internal
logic
FAST
OAND2
X9019
Figure 19: Fast Pin-to-Pin Path in XC4000X
OMUX2
D0
D1
S0
F
O
Global Set/Reset
OAND2
As with the CLB registers, the Global Set/Reset signal
(GSR) can be used to set or clear the input and output reg-
isters, depending on the value of the INIT attribute or prop-
erty. The two flip-flops can be individually configured to set
X6598
X6599
Figure 20: AND & MUX Symbols in XC4000X IOB
May 14, 1999 (Version 1.6)
6-25
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
or clear on reset and after configuration. Other than the glo-
bal GSR net, no user-controlled set/reset signal is available
to the I/O flip-flops. The choice of set or clear applies to
both the initial state of the flip-flop and the response to the
Global Set/Reset pulse. See “Global Set/Reset” on
page 11 for a description of how to use GSR.
Standard 3-State Buffer
All three pins are used. Place the library element BUFT.
Connect the input to the I pin and the output to the O pin.
The T pin is an active-High 3-state (i.e. an active-Low
enable). Tie the T pin to Ground to implement a standard
buffer.
JTAG Support
Wired-AND with Input on the I Pin
Embedded logic attached to the IOBs contains test struc-
tures compatible with IEEE Standard 1149.1 for boundary
scan testing, permitting easy chip and board-level testing.
More information is provided in “Boundary Scan” on
page 42.
The buffer can be used as a Wired-AND. Use the WAND1
library symbol, which is essentially an open-drain buffer.
WAND4, WAND8, and WAND16 are also available. See the
XACT Libraries Guide for further information.
The T pin is internally tied to the I pin. Connect the input to
the I pin and the output to the O pin. Connect the outputs of
all the WAND1s together and attach a PULLUP symbol.
Three-State Buffers
A pair of 3-state buffers is associated with each CLB in the
array. (See Figure 27 on page 30.) These 3-state buffers
can be used to drive signals onto the nearest horizontal
longlines above and below the CLB. They can therefore be
used to implement multiplexed or bidirectional buses on the
horizontal longlines, saving logic resources. Programmable
pull-up resistors attached to these longlines help to imple-
ment a wide wired-AND function.
Wired OR-AND
The buffer can be configured as a Wired OR-AND. A High
level on either input turns off the output. Use the
WOR2AND library symbol, which is essentially an
open-drain 2-input OR gate. The two input pins are func-
tionally equivalent. Attach the two inputs to the I0 and I1
pins and tie the output to the O pin. Tie the outputs of all the
WOR2ANDs together and attach a PULLUP symbol.
The buffer enable is an active-High 3-state (i.e. an
active-Low enable), as shown in Table 13.
Three-State Buffer Examples
Another 3-state buffer with similar access is located near
each I/O block along the right and left edges of the array.
(See Figure 33 on page 34.)
Figure 21 shows how to use the 3-state buffers to imple-
ment a wired-AND function. When all the buffer inputs are
High, the pull-up resistor(s) provide the High output.
The horizontal longlines driven by the 3-state buffers have
a weak keeper at each end. This circuit prevents undefined
floating levels. However, it is overridden by any driver, even
a pull-up resistor.
Figure 22 shows how to use the 3-state buffers to imple-
ment a multiplexer. The selection is accomplished by the
buffer 3-state signal.
Pay particular attention to the polarity of the T pin when
using these buffers in a design. Active-High 3-state (T) is
identical to an active-Low output enable, as shown in
Table 13.
Special longlines running along the perimeter of the array
can be used to wire-AND signals coming from nearby IOBs
or from internal longlines. These longlines form the wide
edge decoders discussed in “Wide Edge Decoders” on
page 27.
Table 13: Three-State Buffer Functionality
Three-State Buffer Modes
IN
X
T
1
0
OUT
Z
The 3-state buffers can be configured in three modes:
IN
IN
•
•
•
Standard 3-state buffer
Wired-AND with input on the I pin
Wired OR-AND
P
U
L
Z = D
●
D
●
(D +D
)
●
(D +D )
E F
A
B
C
D
U
P
L
D
D
D
D
C
D
E
F
D
A
D
B
WAND1
WAND1
WOR2AND
WOR2AND
X6465
Figure 21: Open-Drain Buffers Implement a Wired-AND Function
6-26
May 14, 1999 (Version 1.6)
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Z = D • A + D • B + D • C + D • N
A
B
C
N
~100 kΩ
D
D
D
D
N
A
B
C
BUFT
BUFT
BUFT
BUFT
A
B
C
N
X6466
"Weak Keeper"
Figure 22: 3-State Buffers Implement a Multiplexer
Wide Edge Decoders
Dedicated decoder circuitry boosts the performance of
wide decoding functions. When the address or data field is
wider than the function generator inputs, FPGAs need
multi-level decoding and are thus slower than PALs.
XC4000 Series CLBs have nine inputs. Any decoder of up
to nine inputs is, therefore, compact and fast. However,
there is also a need for much wider decoders, especially for
address decoding in large microprocessor systems.
LUP symbol. Location attributes or properties such as L
(left edge) or TR (right half of top edge) should also be used
to ensure the correct placement of the decoder inputs.
INTERCONNECT
IOB
.I1
IOB
.I1
A
C
B
An XC4000 Series FPGA has four programmable decoders
located on each edge of the device. The inputs to each
decoder are any of the IOB I1 signals on that edge plus one
local interconnect per CLB row or column. Each row or col-
umn of CLBs provides up to three variables or their compli-
ments., as shown in Figure 23. Each decoder generates a
High output (resistor pull-up) when the AND condition of
the selected inputs, or their complements, is true. This is
analogous to a product term in typical PAL devices.
6
(
C) .....
(A • B • C) .....
(A • B • C) .....
(A • B • C) .....
X2627
Each of these wired-AND gates is capable of accepting up
to 42 inputs on the XC4005E and 72 on the XC4013E.
There are up to 96 inputs for each decoder on the
XC4028X and 132 on the XC4052X. The decoders may
also be split in two when a larger number of narrower
decoders are required, for a maximum of 32 decoders per
device.
Figure 23: XC4000 Series Edge Decoding Example
OSC4
F8M
F500K
F16K
F490
F15
The decoder outputs can drive CLB inputs, so they can be
combined with other logic to form a PAL-like AND/OR struc-
ture. The decoder outputs can also be routed directly to the
chip outputs. For fastest speed, the output should be on the
same chip edge as the decoder. Very large PALs can be
emulated by ORing the decoder outputs in a CLB. This
decoding feature covers what has long been considered a
weakness of older FPGAs. Users often resorted to external
PALs for simple but fast decoding functions. Now, the dedi-
cated decoders in the XC4000 Series device can imple-
ment these functions fast and efficiently.
X6703
Figure 24: XC4000 Series Oscillator Symbol
On-Chip Oscillator
XC4000 Series devices include an internal oscillator. This
oscillator is used to clock the power-on time-out, for config-
uration memory clearing, and as the source of CCLK in
Master configuration modes. The oscillator runs at a nomi-
nal 8 MHz frequency that varies with process, Vcc, and
temperature. The output frequency falls between 4 and 10
MHz.
To use the wide edge decoders, place one or more of the
WAND library symbols (WAND1, WAND4, WAND8,
WAND16). Attach a DECODE attribute or property to each
WAND symbol. Tie the outputs together and attach a PUL-
May 14, 1999 (Version 1.6)
6-27
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XC4000E and XC4000X Series Field Programmable Gate Arrays
The oscillator output is optionally available after configura-
tion. Any two of four resynchronized taps of a built-in divider
are also available. These taps are at the fourth, ninth, four-
teenth and nineteenth bits of the divider. Therefore, if the
primary oscillator output is running at the nominal 8 MHz,
the user has access to an 8 MHz clock, plus any two of 500
kHz, 16kHz, 490Hz and 15Hz (up to 10% lower for low-volt-
age devices). These frequencies can vary by as much as
-50% or +25%.
• Global routing consists of dedicated networks primarily
designed to distribute clocks throughout the device with
minimum delay and skew. Global routing can also be
used for other high-fanout signals.
Five interconnect types are distinguished by the relative
length of their segments: single-length lines, double-length
lines, quad and octal lines (XC4000X only), and longlines.
In the XC4000X, direct connects allow fast data flow
between adjacent CLBs, and between IOBs and CLBs.
These signals can be accessed by placing the OSC4
library element in a schematic or in HDL code (see
Figure 24).
Extra routing is included in the IOB pad ring. The XC4000X
also includes a ring of octal interconnect lines near the
IOBs to improve pin-swapping and routing to locked pins.
The oscillator is automatically disabled after configuration if
the OSC4 symbol is not used in the design.
XC4000E/X devices include two types of global buffers.
These global buffers have different properties, and are
intended for different purposes. They are discussed in
detail later in this section.
Programmable Interconnect
All internal connections are composed of metal segments
with programmable switching points and switching matrices
to implement the desired routing. A structured, hierarchical
matrix of routing resources is provided to achieve efficient
automated routing.
CLB Routing Connections
A high-level diagram of the routing resources associated
with one CLB is shown in Figure 25. The shaded arrows
represent routing present only in XC4000X devices.
The XC4000E and XC4000X share a basic interconnect
structure. XC4000X devices, however, have additional rout-
ing not available in the XC4000E. The extra routing
resources allow high utilization in high-capacity devices. All
XC4000X-specific routing resources are clearly identified
throughout this section. Any resources not identified as
XC4000X-specific are present in all XC4000 Series
devices.
Table 14 shows how much routing of each type is available
in XC4000E and XC4000X CLB arrays. Clearly, very large
designs, or designs with a great deal of interconnect, will
route more easily in the XC4000X. Smaller XC4000E
designs, typically requiring significantly less interconnect,
do not require the additional routing.
Figure 27 on page 30 is a detailed diagram of both the
XC4000E and the XC4000X CLB, with associated routing.
The shaded square is the programmable switch matrix,
present in both the XC4000E and the XC4000X. The
L-shaped shaded area is present only in XC4000X devices.
As shown in the figure, the XC4000X block is essentially an
XC4000E block with additional routing.
This section describes the varied routing resources avail-
able in XC4000 Series devices. The implementation soft-
ware automatically assigns the appropriate resources
based on the density and timing requirements of the
design.
CLB inputs and outputs are distributed on all four sides,
providing maximum routing flexibility. In general, the entire
architecture is symmetrical and regular. It is well suited to
established placement and routing algorithms. Inputs, out-
puts, and function generators can freely swap positions
within a CLB to avoid routing congestion during the place-
ment and routing operation.
Interconnect Overview
There are several types of interconnect.
•
CLB routing is associated with each row and column of
the CLB array.
•
IOB routing forms a ring (called a VersaRing) around
the outside of the CLB array. It connects the I/O with the
internal logic blocks.
6-28
May 14, 1999 (Version 1.6)
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Quad
Single
Double
Long
Direct
Connect
CLB
Long
Quad
Long Global Long Double Single Global Carry Direct
Clock
Clock Chain Connect
x5994
Figure 25: High-Level Routing Diagram of XC4000 Series CLB (shaded arrows indicate XC4000X only)
6
Table 14: Routing per CLB in XC4000 Series Devices
XC4000E
XC4000X
Vertical Horizontal Vertical Horizontal
Singles
Doubles
Quads
8
4
0
6
0
8
4
0
6
0
8
4
8
4
Double
Singles
Double
12
10
2
12
6
Longlines
Six Pass Transistors
Per Switch Matrix
Interconnect Point
Direct
Connects
2
Globals
Carry Logic
Total
4
2
0
0
8
1
0
0
X6600
Figure 26: Programmable Switch Matrix (PSM)
24
18
45
32
Single-Length Lines
Programmable Switch Matrices
Single-length lines provide the greatest interconnect flexi-
bility and offer fast routing between adjacent blocks. There
are eight vertical and eight horizontal single-length lines
associated with each CLB. These lines connect the switch-
ing matrices that are located in every row and a column of
CLBs.
The horizontal and vertical single- and double-length lines
intersect at a box called a programmable switch matrix
(PSM). Each switch matrix consists of programmable pass
transistors used to establish connections between the lines
(see Figure 26).
For example, a single-length signal entering on the right
side of the switch matrix can be routed to a single-length
line on the top, left, or bottom sides, or any combination
thereof, if multiple branches are required. Similarly, a dou-
ble-length signal can be routed to a double-length line on
any or all of the other three edges of the programmable
switch matrix.
Single-length lines are connected by way of the program-
mable switch matrices, as shown in Figure 28. Routing
connectivity is shown in Figure 27.
Single-length lines incur a delay whenever they go through
a switching matrix. Therefore, they are not suitable for rout-
ing signals for long distances. They are normally used to
conduct signals within a localized area and to provide the
branching for nets with fanout greater than one.
May 14, 1999 (Version 1.6)
6-29
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
QUAD
DOUBLE
SINGLE
DOUBLE
LONG
F4 C4 G4
YQ
Y
DIRECT
G1
C1
F1
G3
C3
F3
CLB
FEEDBACK
K
X
XQ
F2 C2 G2
LONG
GLOBAL DIRECT
LONG
GLOBAL
LONG DOUBLE
DOUBLELONG
QUAD
SINGLE
FEEDBACK
Common to XC4000E and XC4000X
XC4000X only
Programmable Switch Matrix
Figure 27: Detail of Programmable Interconnect Associated with XC4000 Series CLB
6-30
May 14, 1999 (Version 1.6)
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
Doubles
Singles
Doubles
PSM
PSM
CLB
PSM
PSM
CLB
X6601
X9014
Figure 28: Single- and Double-Length Lines, with
Programmable Switch Matrices (PSMs)
Figure 29: Quad Lines (XC4000X only)
Double-Length Lines
and up to two independent outputs. Only one of the inde-
pendent inputs can be buffered.
The double-length lines consist of a grid of metal segments,
each twice as long as the single-length lines: they run past
two CLBs before entering a switch matrix. Double-length
lines are grouped in pairs with the switch matrices stag-
gered, so that each line goes through a switch matrix at
every other row or column of CLBs (see Figure 28).
6
The place and route software automatically uses the timing
requirements of the design to determine whether or not a
quad line signal should be buffered. A heavily loaded signal
is typically buffered, while a lightly loaded one is not. One
scenario is to alternate buffers and pass transistors. This
allows both vertical and horizontal quad lines to be buffered
at alternating buffered switch matrices.
There are four vertical and four horizontal double-length
lines associated with each CLB. These lines provide faster
signal routing over intermediate distances, while retaining
routing flexibility. Double-length lines are connected by way
of the programmable switch matrices. Routing connectivity
is shown in Figure 27.
Due to the buffered switch matrices, quad lines are very
fast. They provide the fastest available method of routing
heavily loaded signals for long distances across the device.
Longlines
Quad Lines (XC4000X only)
Longlines form a grid of metal interconnect segments that
run the entire length or width of the array. Longlines are
intended for high fan-out, time-critical signal nets, or nets
that are distributed over long distances. In XC4000X
devices, quad lines are preferred for critical nets, because
the buffered switch matrices make them faster for high
fan-out nets.
XC4000X devices also include twelve vertical and twelve
horizontal quad lines per CLB row and column. Quad lines
are four times as long as the single-length lines. They are
interconnected via buffered switch matrices (shown as dia-
monds in Figure 27 on page 30). Quad lines run past four
CLBs before entering a buffered switch matrix. They are
grouped in fours, with the buffered switch matrices stag-
gered, so that each line goes through a buffered switch
matrix at every fourth CLB location in that row or column.
(See Figure 29.)
Two horizontal longlines per CLB can be driven by 3-state
or open-drain drivers (TBUFs). They can therefore imple-
ment unidirectional or bidirectional buses, wide multiplex-
ers, or wired-AND functions. (See “Three-State Buffers” on
page 26 for more details.)
The buffered switch matrixes have four pins, one on each
edge. All of the pins are bidirectional. Any pin can drive any
or all of the other pins.
Each horizontal longline driven by TBUFs has either two
(XC4000E) or eight (XC4000X) pull-up resistors. To acti-
vate these resistors, attach a PULLUP symbol to the
long-line net. The software automatically activates the
appropriate number of pull-ups. There is also a weak
keeper at each end of these two horizontal longlines. This
Each buffered switch matrix contains one buffer and six
pass transistors. It resembles the programmable switch
matrix shown in Figure 26, with the addition of a program-
mable buffer. There can be up to two independent inputs
May 14, 1999 (Version 1.6)
6-31
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
circuit prevents undefined floating levels. However, it is
overridden by any driver, even a pull-up resistor.
I/O Routing
XC4000 Series devices have additional routing around the
IOB ring. This routing is called a VersaRing. The VersaRing
facilitates pin-swapping and redesign without affecting
board layout. Included are eight double-length lines span-
ning two CLBs (four IOBs), and four longlines. Global lines
and Wide Edge Decoder lines are provided. XC4000X
devices also include eight octal lines.
Each XC4000E longline has a programmable splitter switch
at its center, as does each XC4000X longline driven by
TBUFs. This switch can separate the line into two indepen-
dent routing channels, each running half the width or height
of the array.
Each XC4000X longline not driven by TBUFs has a buff-
ered programmable splitter switch at the 1/4, 1/2, and 3/4
points of the array. Due to the buffering, XC4000X longline
performance does not deteriorate with the larger array
sizes. If the longline is split, the resulting partial longlines
are independent.
A high-level diagram of the VersaRing is shown in
Figure 31. The shaded arrows represent routing present
only in XC4000X devices.
Figure 33 on page 34 is a detailed diagram of the XC4000E
and XC4000X VersaRing. The area shown includes two
IOBs. There are two IOBs per CLB row or column, there-
fore this diagram corresponds to the CLB routing diagram
shown in Figure 27 on page 30. The shaded areas repre-
sent routing and routing connections present only in
XC4000X devices.
Routing connectivity of the longlines is shown in Figure 27
on page 30.
Direct Interconnect (XC4000X only)
The XC4000X offers two direct, efficient and fast connec-
tions between adjacent CLBs. These nets facilitate a data
flow from the left to the right side of the device, or from the
top to the bottom, as shown in Figure 30. Signals routed on
the direct interconnect exhibit minimum interconnect prop-
agation delay and use no general routing resources.
Octal I/O Routing (XC4000X only)
Between the XC4000X CLB array and the pad ring, eight
interconnect tracks provide for versatility in pin assignment
and fixed pinout flexibility. (See Figure 32 on page 33.)
The direct interconnect is also present between CLBs and
adjacent IOBs. Each IOB on the left and top device edges
has a direct path to the nearest CLB. Each CLB on the right
and bottom edges of the array has a direct path to the near-
est two IOBs, since there are two IOBs for each row or col-
umn of CLBs.
These routing tracks are called octals, because they can be
broken every eight CLBs (sixteen IOBs) by a programma-
ble buffer that also functions as a splitter switch. The buffers
are staggered, so each line goes through a buffer at every
eighth CLB location around the device edge.
The octal lines bend around the corners of the device. The
lines cross at the corners in such a way that the segment
most recently buffered before the turn has the farthest dis-
tance to travel before the next buffer, as shown in
Figure 32.
The place and route software uses direct interconnect
whenever possible, to maximize routing resources and min-
imize interconnect delays.
IOB
IOB
IOB
IOB
CLB
CLB
CLB
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
IOB
IOB
IOB
IOB
CLB
CLB
CLB
X6603
Figure 30: XC4000X Direct Interconnect
6-32
May 14, 1999 (Version 1.6)
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
WED
IOB
Quad
WED
Single
Double
Long
INTERCONNECT
Direct
Connect
Long
IOB
WED
6
Direct
Edge Double Long Global Octal
Connect
Decode
Clock
X5995
Figure 31: High-Level Routing Diagram of XC4000 Series VersaRing (Left Edge)
WED = Wide Edge Decoder, IOB = I/O Block (shaded arrows indicate XC4000X only)
IOB
IOB
IOB
IOB
Segment with nearest buffer
connects to segment with furthest buffer
X9015
Figure 32: XC4000X Octal I/O Routing
May 14, 1999 (Version 1.6)
6-33
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
QUAD
T
O
DOUBLE
SINGLE
C
L
B
DOUBLE
LONG
A
R
R
A
Y
IOB
I1
I2
IK
OK
T
CE
O
DIRECT
IOB
T
O
OK
IK
I1
CE
I2
LONG
Common to XC4000E and XC4000X
XC4000X only
Figure 33: Detail of Programmable Interconnect Associated with XC4000 Series IOB (Left Edge)
6-34
May 14, 1999 (Version 1.6)
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
IOB inputs and outputs interface with the octal lines via the
single-length interconnect lines. Single-length lines are
also used for communication between the octals and dou-
ble-length lines, quads, and longlines within the CLB array.
Two different types of clock buffers are available in the
XC4000E:
•
•
Primary Global Buffers (BUFGP)
Secondary Global Buffers (BUFGS)
Segmentation into buffered octals was found to be optimal
for distributing signals over long distances around the
device.
Four Primary Global buffers offer the shortest delay and
negligible skew. Four Secondary Global buffers have
slightly longer delay and slightly more skew due to poten-
tially heavier loading, but offer greater flexibility when used
to drive non-clock CLB inputs.
Global Nets and Buffers
Both the XC4000E and the XC4000X have dedicated glo-
bal networks. These networks are designed to distribute
clocks and other high fanout control signals throughout the
devices with minimal skew. The global buffers are
described in detail in the following sections. The text
descriptions and diagrams are summarized in Table 15.
The table shows which CLB and IOB clock pins can be
sourced by which global buffers.
The Primary Global buffers must be driven by the
semi-dedicated pads. The Secondary Global buffers can
be sourced by either semi-dedicated pads or internal nets.
Each CLB column has four dedicated vertical Global lines.
Each of these lines can be accessed by one particular Pri-
mary Global buffer, or by any of the Secondary Global buff-
ers, as shown in Figure 34. Each corner of the device has
one Primary buffer and one Secondary buffer.
In both XC4000E and XC4000X devices, placement of a
library symbol called BUFG results in the software choos-
ing the appropriate clock buffer, based on the timing
requirements of the design. The detailed information in
these sections is included only for reference.
IOBs along the left and right edges have four vertical global
longlines. Top and bottom IOBs can be clocked from the
global lines in the adjacent CLB column.
A global buffer should be specified for all timing-sensitive
global signal distribution. To use a global buffer, place a
BUFGP (primary buffer), BUFGS (secondary buffer), or
BUFG (either primary or secondary buffer) element in a
schematic or in HDL code. If desired, attach a LOC
attribute or property to direct placement to the designated
location. For example, attach a LOC=L attribute or property
to a BUFGS symbol to direct that a buffer be placed in one
of the two Secondary Global buffers on the left edge of the
device, or a LOC=BL to indicate the Secondary Global
buffer on the bottom edge of the device, on the left.
6
Global Nets and Buffers (XC4000E only)
Four vertical longlines in each CLB column are driven
exclusively by special global buffers. These longlines are
in addition to the vertical longlines used for standard inter-
connect. The four global lines can be driven by either of two
types of global buffers. The clock pins of every CLB and
IOB can also be sourced from local interconnect.
Table 15: Clock Pin Access
XC4000E
XC4000X
Local
Inter-
connect
L & R
BUFGE
T & B
BUFGE
BUFGP
BUFGS
BUFGLS
All CLBs in Quadrant
All CLBs in Device
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
IOBs on Adjacent Vertical
Half Edge
√
√
√
√
IOBs on Adjacent Vertical
Full Edge
√
√
√
√
√
√
√
IOBs on Adjacent Horizontal
Half Edge (Direct)
IOBs on Adjacent Horizontal
Half Edge (through CLB globals)
√
√
√
√
√
√
√
IOBs on Adjacent Horizontal
Full Edge (through CLB globals)
L = Left, R = Right, T = Top, B = Bottom
May 14, 1999 (Version 1.6)
6-35
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
IOB
IOB
IOB
IOB
BUFGS
BUFGP
PGCK1
SGCK4
PGCK4
SGCK1
4
4
BUFGS
BUFGP
4
4
locals
locals
CLB
CLB
CLB
CLB
IOB
IOB
locals
locals
locals
locals
Any BUFGS
Any BUFGS
X4
X4
X4
X4
One BUFGP
per Global Line
One BUFGP
per Global Line
IOB
IOB
locals
locals
BUFGP
BUFGS
SGCK3
PGCK2
SGCK2
PGCK3
BUFGP
BUFGS
IOB
IOB
IOB
IOB
X6604
Figure 34: XC4000E Global Net Distribution
IOB
IOB
IOB
IOB
BUFGLS
BUFGLS
BUFGE
GCK1
GCK6
GCK8
GCK7
BUFGE
BUFGLS
BUFGLS
BUFGE
BUFGE
CLB
CLB
X8
X8
8
X4
8
X8
BUFGLS
locals
BUFGLS
locals
BUFGLS
8
locals
BUFGLS
locals
8
4
8
8
8
CLB CLOCKS
(PER COLUMN)
CLB CLOCKS
(PER COLUMN)
IOB
IOB
IOB
CLOCKS
IOB
CLOCKS
locals
locals
locals
locals
IOB
CLOCKS
IOB
CLOCKS
CLB CLOCKS
(PER COLUMN)
CLB CLOCKS
(PER COLUMN)
IOB
IOB
8
8
locals
locals
4
8
BUFGLS
8
8 BUFGLS
locals
BUFGLS
locals
BUFGLS
8
8
X4
X8
X8
X8
CLB
CLB
BUFGLS
BUFGLS
BUFGE
BUFGE
BUFGE
BUFGE
GCK4
GCK2
GCK5
GCK3
X9018
BUFGLS
BUFGLS
IOB
IOB
IOB
IOB
Figure 35: XC4000X Global Net Distribution
6-36
May 14, 1999 (Version 1.6)
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Early and Global Low-Skew buffers share a common input;
they cannot be driven by two different signals.
Global Nets and Buffers (XC4000X only)
Eight vertical longlines in each CLB column are driven by
special global buffers. These longlines are in addition to the
vertical longlines used for standard interconnect. The glo-
bal lines are broken in the center of the array, to allow faster
distribution and to minimize skew across the whole array.
Each half-column global line has its own buffered multi-
plexer, as shown in Figure 35. The top and bottom global
lines cannot be connected across the center of the device,
as this connection might introduce unacceptable skew. The
top and bottom halves of the global lines must be sepa-
rately driven — although they can be driven by the same
global buffer.
Choosing an XC4000X Clock Buffer
The clocking structure of the XC4000X provides a large
variety of features. However, it can be simple to use, with-
out understanding all the details. The software automati-
cally handles clocks, along with all other routing, when the
appropriate clock buffer is placed in the design. In fact, if a
buffer symbol called BUFG is placed, rather than a specific
type of buffer, the software even chooses the buffer most
appropriate for the design. The detailed information in this
section is provided for those users who want a finer level of
control over their designs.
The eight global lines in each CLB column can be driven by
either of two types of global buffers. They can also be
driven by internal logic, because they can be accessed by
single, double, and quad lines at the top, bottom, half, and
quarter points. Consequently, the number of different
clocks that can be used simultaneously in an XC4000X
device is very large.
If fine control is desired, use the following summary and
Table 15 on page 35 to choose an appropriate clock buffer.
•
The simplest thing to do is to use a Global Low-Skew
buffer.
•
If a faster clock path is needed, try a BUFG. The
software will first try to use a Global Low-Skew Buffer. If
timing requirements are not met, a faster buffer will
automatically be used.
There are four global lines feeding the IOBs at the left edge
of the device. IOBs along the right edge have eight global
lines. There is a single global line along the top and bottom
edges with access to the IOBs. All IOB global lines are bro-
ken at the center. They cannot be connected across the
center of the device, as this connection might introduce
unacceptable skew.
•
If a single quadrant of the chip is sufficient for the
clocked logic, and the timing requires a faster clock than
the Global Low-Skew buffer, use a Global Early buffer.
6
Global Low-Skew Buffers
Each corner of the XC4000X device has two Global
Low-Skew buffers. Any of the eight Global Low-Skew buff-
ers can drive any of the eight vertical Global lines in a col-
umn of CLBs. In addition, any of the buffers can drive any of
the four vertical lines accessing the IOBs on the left edge of
the device, and any of the eight vertical lines accessing the
IOBs on the right edge of the device. (See Figure 36 on
page 38.)
IOB global lines can be driven from two types of global buff-
ers, or from local interconnect. Alternatively, top and bottom
IOBs can be clocked from the global lines in the adjacent
CLB column.
Two different types of clock buffers are available in the
XC4000X:
•
•
Global Low-Skew Buffers (BUFGLS)
Global Early Buffers (BUFGE)
IOBs at the top and bottom edges of the device are
accessed through the vertical Global lines in the CLB array,
as in the XC4000E. Any Global Low-Skew buffer can,
therefore, access every IOB and CLB in the device.
Global Low-Skew Buffers are the standard clock buffers.
They should be used for most internal clocking, whenever a
large portion of the device must be driven.
The Global Low-Skew buffers can be driven by either
semi-dedicated pads or internal logic.
Global Early Buffers are designed to provide a faster clock
access, but CLB access is limited to one-fourth of the
device. They also facilitate a faster I/O interface.
To use a Global Low-Skew buffer, instantiate a BUFGLS
element in a schematic or in HDL code. If desired, attach a
LOC attribute or property to direct placement to the desig-
nated location. For example, attach a LOC=T attribute or
property to direct that a BUFGLS be placed in one of the
two Global Low-Skew buffers on the top edge of the device,
or a LOC=TR to indicate the Global Low-Skew buffer on the
top edge of the device, on the right.
Figure 35 is a conceptual diagram of the global net struc-
ture in the XC4000X.
Global Early buffers and Global Low-Skew buffers share a
single pad. Therefore, the same IPAD symbol can drive one
buffer of each type, in parallel. This configuration is particu-
larly useful when using the Fast Capture latches, as
described in “IOB Input Signals” on page 20. Paired Global
May 14, 1999 (Version 1.6)
6-37
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
8
7
8
7
IOB
IOB
IOB
IOB
1
6
1
6
I
O
B
I
O
B
I
O
B
I
O
B
CLB
CLB
CLB
CLB
I
O
B
I
O
B
I
O
B
I
O
B
CLB
CLB
CLB
CLB
2
5
2
5
IOB
IOB
IOB
IOB
3
4
X6751
3
4
X6753
Figure 37: Left and Right BUFGEs Can Drive Any or
All Clock Inputs in Same Quadrant or Edge (GCK1 is
shown. GCK2, GCK5 and GCK6 are similar.)
Figure 36: Any BUFGLS (GCK1 - GCK8) Can
Drive Any or All Clock Inputs on the Device
Global Early Buffers
The left-side Global Early buffers can each drive two of the
four vertical lines accessing the IOBs on the entire left edge
of the device. The right-side Global Early buffers can each
drive two of the eight vertical lines accessing the IOBs on
the entire right edge of the device. (See Figure 37.)
Each corner of the XC4000X device has two Global Early
buffers. The primary purpose of the Global Early buffers is
to provide an earlier clock access than the potentially
heavily-loaded Global Low-Skew buffers. A clock source
applied to both buffers will result in the Global Early clock
edge occurring several nanoseconds earlier than the Glo-
bal Low-Skew buffer clock edge, due to the lighter loading.
Each left and right Global Early buffer can also drive half of
the IOBs along either the top or bottom edge of the device,
using a dedicated line that can only be accessed through
the Global Early buffers.
Global Early buffers also facilitate the fast capture of device
inputs, using the Fast Capture latches described in “IOB
Input Signals” on page 20. For Fast Capture, take a single
clock signal, and route it through both a Global Early buffer
and a Global Low-Skew buffer. (The two buffers share an
input pad.) Use the Global Early buffer to clock the Fast
Capture latch, and the Global Low-Skew buffer to clock the
normal input flip-flop or latch, as shown in Figure 17 on
page 23.
The top and bottom Global Early buffers can drive half of
the IOBs along either the left or right edge of the device, as
shown in Figure 38. They can only access the top and bot-
tom IOBs via the CLB global lines.
8
7
IOB
IOB
1
6
The Global Early buffers can also be used to provide a fast
Clock-to-Out on device output pins. However, an early clock
in the output flip-flop IOB must be taken into consideration
when calculating the internal clock speed for the design.
I
I
O
B
O
B
CLB
CLB
The Global Early buffers at the left and right edges of the
chip have slightly different capabilities than the ones at the
top and bottom. Refer to Figure 37, Figure 38, and
Figure 35 on page 36 while reading the following explana-
tion.
I
O
B
I
O
B
CLB
CLB
Each Global Early buffer can access the eight vertical Glo-
bal lines for all CLBs in the quadrant. Therefore, only
one-fourth of the CLB clock pins can be accessed. This
restriction is in large part responsible for the faster speed of
the buffers, relative to the Global Low-Skew buffers.
2
5
IOB
IOB
3
4
X6747
Figure 38: Top and Bottom BUFGEs Can Drive Any
or All Clock Inputs in Same Quadrant (GCK8 is
shown. GCK3, GCK4 and GCK7 are similar.)
6-38
May 14, 1999 (Version 1.6)
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
The top and bottom Global Early buffers are about 1 ns
slower clock to out than the left and right Global Early buff-
ers.
GND
Ground and
Vcc Ring for
I/O Drivers
The Global Early buffers can be driven by either semi-ded-
icated pads or internal logic. They share pads with the Glo-
bal Low-Skew buffers, so a single net can drive both global
buffers, as described above.
Vcc
Vcc
To use a Global Early buffer, place a BUFGE element in a
schematic or in HDL code. If desired, attach a LOC
attribute or property to direct placement to the designated
location. For example, attach a LOC=T attribute or property
to direct that a BUFGE be placed in one of the two Global
Early buffers on the top edge of the device, or a LOC=TR to
indicate the Global Early buffer on the top edge of the
device, on the right.
Logic
Power Grid
GND
X5422
Figure 39: XC4000 Series Power Distribution
Power Distribution
Power for the FPGA is distributed through a grid to achieve
high noise immunity and isolation between logic and I/O.
Inside the FPGA, a dedicated Vcc and Ground ring sur-
rounding the logic array provides power to the I/O drivers,
as shown in Figure 39. An independent matrix of Vcc and
Ground lines supplies the interior logic of the device.
Pin Descriptions
There are three types of pins in the XC4000 Series
devices:
•
•
•
Permanently dedicated pins
User I/O pins that can have special functions
Unrestricted user-programmable I/O pins.
6
This power distribution grid provides a stable supply and
ground for all internal logic, providing the external package
power pins are all connected and appropriately de-coupled.
Typically, a 0.1 µF capacitor connected between each Vcc
pin and the board’s Ground plane will provide adequate
de-coupling.
Before and during configuration, all outputs not used for the
configuration process are 3-stated with a 50 kΩ - 100 kΩ
pull-up resistor.
After configuration, if an IOB is unused it is configured as
an input with a 50 kΩ - 100 kΩ pull-up resistor.
Output buffers capable of driving/sinking the specified 12
mA loads under specified worst-case conditions may be
capable of driving/sinking up to 10 times as much current
under best case conditions.
XC4000 Series devices have no dedicated Reset input.
Any user I/O can be configured to drive the Global
Set/Reset net, GSR. See “Global Set/Reset” on page 11
for more information on GSR.
Noise can be reduced by minimizing external load capaci-
tance and reducing simultaneous output transitions in the
same direction. It may also be beneficial to locate heavily
loaded output buffers near the Ground pads. The I/O Block
output buffers have a slew-rate limited mode (default) which
should be used where output rise and fall times are not
speed-critical.
XC4000 Series devices have no Powerdown control input,
as the XC3000 and XC2000 families do. The
XC3000/XC2000 Powerdown control also 3-stated all of the
device
I/O pins. For XC4000 Series devices, use the global 3-state
net, GTS, instead. This net 3-states all outputs, but does
not place the device in low-power mode. See “IOB Output
Signals” on page 23 for more information on GTS.
Device pins for XC4000 Series devices are described in
Table 16. Pin functions during configuration for each of the
seven configuration modes are summarized in Table 22 on
page 58, in the “Configuration Timing” section.
May 14, 1999 (Version 1.6)
6-39
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XC4000E and XC4000X Series Field Programmable Gate Arrays
Table 16: Pin Descriptions
I/O
I/O
During
After
Pin Name
Config. Config.
Pin Description
Permanently Dedicated Pins
Eight or more (depending on package) connections to the nominal +5 V supply voltage
(+3.3 V for low-voltage devices). All must be connected, and each must be decoupled
with a 0.01 - 0.1 µF capacitor to Ground.
VCC
GND
I
I
I
I
Eight or more (depending on package type) connections to Ground. All must be con-
nected.
During configuration, Configuration Clock (CCLK) is an output in Master modes or Asyn-
chronous Peripheral mode, but is an input in Slave mode and Synchronous Peripheral
mode. After configuration, CCLK has a weak pull-up resistor and can be selected as the
Readback Clock. There is no CCLK High or Low time restriction on XC4000 Series de-
vices, except during Readback. See “Violating the Maximum High and Low Time Spec-
ification for the Readback Clock” on page 56 for an explanation of this exception.
CCLK
DONE
I or O
I
O
I
DONE is a bidirectional signal with an optional internal pull-up resistor. As an output, it
indicates the completion of the configuration process. As an input, a Low level on DONE
can be configured to delay the global logic initialization and the enabling of outputs.
The optional pull-up resistor is selected as an option in the XACTstep program that cre-
ates the configuration bitstream. The resistor is included by default.
I/O
PROGRAM is an active Low input that forces the FPGA to clear its configuration mem-
ory. It is used to initiate a configuration cycle. When PROGRAM goes High, the FPGA
finishes the current clear cycle and executes another complete clear cycle, before it
goes into a WAIT state and releases INIT.
PROGRAM
I
The PROGRAM pin has a permanent weak pull-up, so it need not be externally pulled
up to Vcc.
User I/O Pins That Can Have Special Functions
During Peripheral mode configuration, this pin indicates when it is appropriate to write
another byte of data into the FPGA. The same status is also available on D7 in Asyn-
chronous Peripheral mode, if a read operation is performed when the device is selected.
After configuration, RDY/BUSY is a user-programmable I/O pin.
RDY/BUSY
O
I/O
RDY/BUSY is pulled High with a high-impedance pull-up prior to INIT going High.
During Master Parallel configuration, each change on the A0-A17 outputs (A0 - A21 for
XC4000X) is preceded by a rising edge on RCLK, a redundant output signal. RCLK is
useful for clocked PROMs. It is rarely used during configuration. After configuration,
RCLK is a user-programmable I/O pin.
RCLK
O
I/O
As Mode inputs, these pins are sampled after INIT goes High to determine the configu-
ration mode to be used. After configuration, M0 and M2 can be used as inputs, and M1
can be used as a 3-state output. These three pins have no associated input or output
registers.
I (M0), During configuration, these pins have weak pull-up resistors. For the most popular con-
O (M1), figuration mode, Slave Serial, the mode pins can thus be left unconnected. The three
I (M2) mode inputs can be individually configured with or without weak pull-up or pull-down re-
sistors. A pull-down resistor value of 4.7 kΩ is recommended.
M0, M1, M2
I
These pins can only be used as inputs or outputs when called out by special schematic
definitions. To use these pins, place the library components MD0, MD1, and MD2 in-
stead of the usual pad symbols. Input or output buffers must still be used.
If boundary scan is used, this pin is the Test Data Output. If boundary scan is not used,
this pin is a 3-state output without a register, after configuration is completed.
TDO
O
O
This pin can be user output only when called out by special schematic definitions. To
use this pin, place the library component TDO instead of the usual pad symbol. An out-
put buffer must still be used.
6-40
May 14, 1999 (Version 1.6)
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XC4000E and XC4000X Series Field Programmable Gate Arrays
Table 16: Pin Descriptions (Continued)
I/O
I/O
During
After
Pin Name
Config. Config.
Pin Description
If boundary scan is used, these pins are Test Data In, Test Clock, and Test Mode Select
inputs respectively. They come directly from the pads, bypassing the IOBs. These pins
can also be used as inputs to the CLB logic after configuration is completed.
If the BSCAN symbol is not placed in the design, all boundary scan functions are inhib-
ited once configuration is completed, and these pins become user-programmable I/O.
In this case, they must be called out by special schematic definitions. To use these pins,
place the library components TDI, TCK, and TMS instead of the usual pad symbols. In-
put or output buffers must still be used.
I/O
or I
(JTAG)
TDI, TCK,
TMS
I
High During Configuration (HDC) is driven High until the I/O go active. It is available as
a control output indicating that configuration is not yet completed. After configuration,
HDC is a user-programmable I/O pin.
HDC
LDC
O
O
I/O
I/O
Low During Configuration (LDC) is driven Low until the I/O go active. It is available as a
control output indicating that configuration is not yet completed. After configuration,
LDC is a user-programmable I/O pin.
Before and during configuration, INIT is a bidirectional signal. A 1 kΩ - 10 kΩ external
pull-up resistor is recommended.
As an active-Low open-drain output, INIT is held Low during the power stabilization and
internal clearing of the configuration memory. As an active-Low input, it can be used
to hold the FPGA in the internal WAIT state before the start of configuration. Master
mode devices stay in a WAIT state an additional 30 to 300 µs after INIT has gone High.
During configuration, a Low on this output indicates that a configuration data error has
occurred. After the I/O go active, INIT is a user-programmable I/O pin.
INIT
I/O
I/O
6
Four Primary Global inputs each drive a dedicated internal global net with short delay
and minimal skew. If not used to drive a global buffer, any of these pins is a user-pro-
grammable I/O.
The PGCK1-PGCK4 pins drive the four Primary Global Buffers. Any input pad symbol
connected directly to the input of a BUFGP symbol is automatically placed on one of
these pins.
PGCK1 -
PGCK4
(XC4000E
only)
Weak
Pull-up
I or I/O
I or I/O
I or I/O
I or I/O
Four Secondary Global inputs each drive a dedicated internal global net with short delay
and minimal skew. These internal global nets can also be driven from internal logic. If
not used to drive a global net, any of these pins is a user-programmable I/O pin.
The SGCK1-SGCK4 pins provide the shortest path to the four Secondary Global Buff-
ers. Any input pad symbol connected directly to the input of a BUFGS symbol is auto-
matically placed on one of these pins.
SGCK1 -
SGCK4
(XC4000E
only)
Weak
Pull-up
Eight inputs can each drive a Global Low-Skew buffer. In addition, each can drive a Glo-
bal Early buffer. Each pair of global buffers can also be driven from internal logic, but
must share an input signal. If not used to drive a global buffer, any of these pins is a
user-programmable I/O.
Any input pad symbol connected directly to the input of a BUFGLS or BUFGE symbol
is automatically placed on one of these pins.
GCK1 -
GCK8
(XC4000X
only)
Weak
Pull-up
FCLK1 -
FCLK4
(XC4000XLA Weak
and
XC4000XV
only)
Four inputs can each drive a Fast Clock (FCLK) buffer which can deliver a clock signal
to any IOB clock input in the octant of the die served by the Fast Clock buffer. Two Fast
Clock buffers serve the two IOB octants on the left side of the die and the other two Fast
Clock buffers serve the two IOB octants on the right side of the die. On each side of the
die, one Fast Clock buffer serves the upper octant and the other serves the lower octant.
If not used to drive a Fast Clock buffer, any of these pins is a user-programmable I/O.
Pull-up
May 14, 1999 (Version 1.6)
6-41
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XC4000E and XC4000X Series Field Programmable Gate Arrays
Table 16: Pin Descriptions (Continued)
I/O
I/O
During
After
Pin Name
Config. Config.
Pin Description
These four inputs are used in Asynchronous Peripheral mode. The chip is selected
when CS0 is Low and CS1 is High. While the chip is selected, a Low on Write Strobe
(WS) loads the data present on the D0 - D7 inputs into the internal data buffer. A Low
on Read Strobe (RS) changes D7 into a status output — High if Ready, Low if Busy —
and drives D0 - D6 High.
CS0, CS1,
WS, RS
I
I/O
In Express mode, CS1 is used as a serial-enable signal for daisy-chaining.
WS and RS should be mutually exclusive, but if both are Low simultaneously, the Write
Strobe overrides. After configuration, these are user-programmable I/O pins.
During Master Parallel configuration, these 18 output pins address the configuration
EPROM. After configuration, they are user-programmable I/O pins.
A0 - A17
O
O
I
I/O
I/O
I/O
I/O
A18 - A21
(XC4003XL to
XC4085XL)
During Master Parallel configuration with an XC4000X master, these 4 output pins add
4 more bits to address the configuration EPROM. After configuration, they are user-pro-
grammable I/O pins. (See Master Parallel Configuration section for additional details.)
During Master Parallel and Peripheral configuration, these eight input pins receive con-
figuration data. After configuration, they are user-programmable I/O pins.
D0 - D7
During Slave Serial or Master Serial configuration, DIN is the serial configuration data
input receiving data on the rising edge of CCLK. During Parallel configuration, DIN is
the D0 input. After configuration, DIN is a user-programmable I/O pin.
DIN
I
During configuration in any mode but Express mode, DOUT is the serial configuration
data output that can drive the DIN of daisy-chained slave FPGAs. DOUT data changes
on the falling edge of CCLK, one-and-a-half CCLK periods after it was received at the
DIN input.
DOUT
O
I/O
In Express modefor XC4000E and XC4000X only, DOUT is the status output that can
drive the CS1 of daisy-chained FPGAs, to enable and disable downstream devices.
After configuration, DOUT is a user-programmable I/O pin.
Unrestricted User-Programmable I/O Pins
These pins can be configured to be input and/or output after configuration is completed.
Before configuration is completed, these pins have an internal high-value pull-up resis-
tor (25 kΩ - 100 kΩ) that defines the logic level as High.
Weak
Pull-up
I/O
I/O
of how to enable this circuitry are covered later in this sec-
tion.
Boundary Scan
The ‘bed of nails’ has been the traditional method of testing
electronic assemblies. This approach has become less
appropriate, due to closer pin spacing and more sophisti-
cated assembly methods like surface-mount technology
and multi-layer boards. The IEEE Boundary Scan Standard
1149.1 was developed to facilitate board-level testing of
electronic assemblies. Design and test engineers can
imbed a standard test logic structure in their device to
achieve high fault coverage for I/O and internal logic. This
structure is easily implemented with a four-pin interface on
any boundary scan-compatible IC. IEEE 1149.1-compati-
ble devices may be serial daisy-chained together, con-
nected in parallel, or a combination of the two.
By exercising these input signals, the user can serially load
commands and data into these devices to control the driv-
ing of their outputs and to examine their inputs. This
method is an improvement over bed-of-nails testing. It
avoids the need to over-drive device outputs, and it reduces
the user interface to four pins. An optional fifth pin, a reset
for the control logic, is described in the standard but is not
implemented in Xilinx devices.
The dedicated on-chip logic implementing the IEEE 1149.1
functions includes a 16-state machine, an instruction regis-
ter and a number of data registers. The functional details
can be found in the IEEE 1149.1 specification and are also
discussed in the Xilinx application note XAPP 017: “Bound-
ary Scan in XC4000 Devices.”
The XC4000 Series implements IEEE 1149.1-compatible
BYPASS, PRELOAD/SAMPLE and EXTEST boundary
scan instructions. When the boundary scan configuration
option is selected, three normal user I/O pins become ded-
icated inputs for these functions. Another user output pin
becomes the dedicated boundary scan output. The details
Figure 40 on page 43 shows a simplified block diagram of
the XC4000E Input/Output Block with boundary scan
implemented. XC4000X boundary scan logic is identical.
6-42
May 14, 1999 (Version 1.6)
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Figure 41 on page 44 is a diagram of the XC4000 Series
boundary scan logic. It includes three bits of Data Register
per IOB, the IEEE 1149.1 Test Access Port controller, and
the Instruction Register with decodes.
data register, respectively, and BSCANT.UPD, which is
always the last bit of the data register. These three bound-
ary scan bits are special-purpose Xilinx test signals.
The other standard data register is the single flip-flop
BYPASS register. It synchronizes data being passed
through the FPGA to the next downstream boundary scan
device.
XC4000 Series devices can also be configured through the
boundary scan logic. See “Readback” on page 55.
Data Registers
The FPGA provides two additional data registers that can
be specified using the BSCAN macro. The FPGA provides
two user pins (BSCAN.SEL1 and BSCAN.SEL2) which are
the decodes of two user instructions. For these instructions,
The primary data register is the boundary scan register. For
each IOB pin in the FPGA, bonded or not, it includes three
bits for In, Out and 3-State Control. Non-IOB pins have
appropriate partial bit population for In or Out only. PRO-
GRAM, CCLK and DONE are not included in the boundary
scan register. Each EXTEST CAPTURE-DR state captures
all In, Out, and 3-state pins.
two
corresponding
pins
(BSCAN.TDO1
and
BSCAN.TDO2) allow user scan data to be shifted out on
TDO. The data register clock (BSCAN.DRCK) is available
for control of test logic which the user may wish to imple-
ment with CLBs. The NAND of TCK and RUN-TEST-IDLE
is also provided (BSCAN.IDLE).
The data register also includes the following non-pin bits:
TDO.T, and TDO.O, which are always bits 0 and 1 of the
EXTEST
SLEW
RATE
PULL
DOWN
PULL
UP
M
TS INV
TS/OE
3-State TS
V
CC
6
TS - capture
TS - update
Boundary
Scan
OUTPUT
INVERT
OUTPUT
M
sd
D
Q
Ouput Data O
EC
M
M
INVERT
PAD
M
Ouput Clock OK
rd
OUT
SEL
S/R
M
O - capture
Q - capture
Clock Enable
Boundary
Scan
O - update
M
I - capture
Boundary
Scan
Input Data 1 I1
Input Data 2 I2
I - update
M
M
M
M
sd
Q
D
EC
DELAY
Q
L
M
M
INVERT
M
FLIP-FLOP/LATCH
Input Clock IK
rd
S/R
INPUT
GLOBAL
S/R
X5792
Figure 40: Block Diagram of XC4000E IOB with Boundary Scan (some details not shown).
XC4000X Boundary Scan Logic is Identical.
May 14, 1999 (Version 1.6)
6-43
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
DATA IN
IOB.T
0
1
1
sd
D
Q
D
Q
0
LE
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
sd
1
0
D
Q
D
Q
LE
1
0
IOB.I
1
sd
D
Q
D
Q
0
LE
1
0
IOB.Q
IOB.T
BYPASS
REGISTER
0
1
M
U
X
TDO
1
sd
INSTRUCTION REGISTER
TDI
D
Q
D
Q
0
LE
1
sd
D
Q
D
Q
0
LE
1
0
IOB.I
DATAOUT
SHIFT/
CAPTURE
UPDATE
EXTEST
CLOCK DATA
REGISTER
X9016
Figure 41: XC4000 Series Boundary Scan Logic
BSDL (Boundary Scan Description Language) files for
XC4000 Series devices are available on the Xilinx FTP site.
Instruction Set
The XC4000 Series boundary scan instruction set also
includes instructions to configure the device and read back
the configuration data. The instruction set is coded as
shown in Table 17.
Including Boundary Scan in a Schematic
If boundary scan is only to be used during configuration, no
special schematic elements need be included in the sche-
matic or HDL code. In this case, the special boundary scan
pins TDI, TMS, TCK and TDO can be used for user func-
tions after configuration.
Bit Sequence
The bit sequence within each IOB is: In, Out, 3-State. The
input-only M0 and M2 mode pins contribute only the In bit
to the boundary scan I/O data register, while the out-
put-only M1 pin contributes all three bits.
To indicate that boundary scan remain enabled after config-
uration, place the BSCAN library symbol and connect the
TDI, TMS, TCK and TDO pad symbols to the appropriate
pins, as shown in Figure 43.
The first two bits in the I/O data register are TDO.T and
TDO.O, which can be used for the capture of internal sig-
nals. The final bit is BSCANT.UPD, which can be used to
drive an internal net. These locations are primarily used by
Xilinx for internal testing.
Even if the boundary scan symbol is used in a schematic,
the input pins TMS, TCK, and TDI can still be used as
inputs to be routed to internal logic. Care must be taken not
to force the chip into an undesired boundary scan state by
inadvertently applying boundary scan input patterns to
these pins. The simplest way to prevent this is to keep TMS
High, and then apply whatever signal is desired to TDI and
TCK.
From a cavity-up view of the chip (as shown in XDE or
Epic), starting in the upper right chip corner, the boundary
scan data-register bits are ordered as shown in Figure 42.
The device-specific pinout tables for the XC4000 Series
include the boundary scan locations for each IOB pin.
6-44
May 14, 1999 (Version 1.6)
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Table 17: Boundary Scan Instructions
Optional
To User
Logic
Instruction I2
I1 I0
Test
Selected
I/O Data
Source
TDO Source
IBUF
BSCAN
0
0
0
0
0
1
EXTEST
DR
DR
DR
TDO
TDI
TMS
TCK
TDI
TDO
SAMPLE/PR
ELOAD
Pin/Logic
TMS
TCK
DRCK
IDLE
To User
Logic
0
0
1
1
1
0
0
1
0
USER 1
BSCAN.
TDO1
User Logic
User Logic
Pin/Logic
TDO1
TDO2
SEL1
SEL2
From
User Logic
USER 2
BSCAN.
TDO2
X2675
Figure 43: Boundary Scan Schematic Example
READBACK Readback
Data
Configuration
1
1
1
0
1
1
1
0
1
CONFIGURE
Reserved
DOUT
—
Disabled
Configuration is the process of loading design-specific pro-
gramming data into one or more FPGAs to define the func-
tional operation of the internal blocks and their
interconnections. This is somewhat like loading the com-
mand registers of a programmable peripheral chip. XC4000
Series devices use several hundred bits of configuration
data per CLB and its associated interconnects. Each con-
figuration bit defines the state of a static memory cell that
controls either a function look-up table bit, a multiplexer
input, or an interconnect pass transistor. The XACTstep
development system translates the design into a netlist file.
It automatically partitions, places and routes the logic and
generates the configuration data in PROM format.
—
—
BYPASS
Bypass
Register
TDO.T
TDO.O
Bit 0 ( TDO end)
Bit 1
Bit 2
Top-edge IOBs (Right to Left)
Left-edge IOBs (Top to Bottom)
6
MD1.T
MD1.O
MD1.I
MD0.I
MD2.I
Special Purpose Pins
Bottom-edge IOBs (Left to Right)
Three configuration mode pins (M2, M1, M0) are sampled
prior to configuration to determine the configuration mode.
After configuration, these pins can be used as auxiliary
connections. M2 and M0 can be used as inputs, and M1
can be used as an output. The XACTstep development sys-
tem does not use these resources unless they are explicitly
specified in the design entry. This is done by placing a spe-
cial pad symbol called MD2, MD1, or MD0 instead of the
input or output pad symbol.
Right-edge IOBs (Bottom to Top)
B SCANT.UPD
(TDI end)
X6075
Figure 42: Boundary Scan Bit Sequence
Avoiding Inadvertent Boundary Scan
If TMS or TCK is used as user I/O, care must be taken to
ensure that at least one of these pins is held constant dur-
ing configuration. In some applications, a situation may
occur where TMS or TCK is driven during configuration.
This may cause the device to go into boundary scan mode
and disrupt the configuration process.
In XC4000 Series devices, the mode pins have weak
pull-up resistors during configuration. With all three mode
pins High, Slave Serial mode is selected, which is the most
popular configuration mode. Therefore, for the most com-
mon configuration mode, the mode pins can be left uncon-
nected. (Note, however, that the internal pull-up resistor
value can be as high as 100 kΩ.) After configuration, these
pins can individually have weak pull-up or pull-down resis-
tors, as specified in the design. A pull-down resistor value
of 4.7 kΩ is recommended.
To prevent activation of boundary scan during configura-
tion, do either of the following:
•
TMS: Tie High to put the Test Access Port controller
in a benign RESET state
•
TCK: Tie High or Low—don't toggle this clock input.
These pins are located in the lower left chip corner and are
near the readback nets. This location allows convenient
routing if compatibility with the XC2000 and XC3000 family
conventions of M0/RT, M1/RD is desired.
For more information regarding boundary scan, refer to the
Xilinx Application Note XAPP 017.001, “Boundary Scan in
XC4000E Devices.“
May 14, 1999 (Version 1.6)
6-45
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XC4000E and XC4000X Series Field Programmable Gate Arrays
Additional Address lines in XC4000 devices
Configuration Modes
The XC4000X devices have additional address lines
(A18-A21) allowing the additional address space required
to daisy-chain several large devices.
XC4000E devices have six configuration modes. XC4000X
devices have the same six modes, plus an additional con-
figuration mode. These modes are selected by a 3-bit input
code applied to the M2, M1, and M0 inputs. There are three
self-loading Master modes, two Peripheral modes, and a
Serial Slave mode, which is used primarily for
daisy-chained devices. The coding for mode selection is
shown in Table 18.
The extra address lines are programmable in XC4000EX
devices. By default these address lines are not activated. In
the default mode, the devices are compatible with existing
XC4000 and XC4000E products. If desired, the extra
address lines can be used by specifying the address lines
option in bitgen as 22 (bitgen -g AddressLines:22). The
lines (A18-A21) are driven when a master device detects,
via the bitstream, that it should be using all 22 address
lines. Because these pins will initially be pulled high by
internal pull-ups, designers using Master Parallel Up mode
should use external pull down resistors on pins A18-A21. If
Master Parallel Down mode is used external resistors are
not necessary.
Table 18: Configuration Modes
Mode
M2 M1 M0 CCLK
Data
Master Serial
Slave Serial
0
1
1
0
1
0
0
1
0
output
input
Bit-Serial
Bit-Serial
Master
Parallel Up
output
Byte-Wide,
increment
from 00000
Master
Parallel Down
1
1
0
output
Byte-Wide,
decrement
from 3FFFF
All 22 address lines are always active in Master Parallel
modes with XC4000XL devices. The additional address
lines behave identically to the lower order address lines. If
the Address Lines option in bitgen is set to 18, it will be
ignored by the XC4000XL device.
Peripheral
Synchronous*
0
1
1
0
1
1
input
Byte-Wide
Peripheral
Asynchronous
output
Byte-Wide
The additional address lines (A18-A21) are not available in
the PC84 package.
Reserved
Reserved
0
0
1
0
0
1
—
—
—
—
Peripheral Modes
The two Peripheral modes accept byte-wide data from a
bus. A RDY/BUSY status is available as a handshake sig-
nal. In Asynchronous Peripheral mode, the internal oscilla-
tor generates a CCLK burst signal that serializes the
byte-wide data. CCLK can also drive slave devices. In the
synchronous mode, an externally supplied clock input to
CCLK serializes the data.
* Can be considered byte-wide Slave Parallel
A detailed description of each configuration mode, with tim-
ing information, is included later in this data sheet. During
configuration, some of the I/O pins are used temporarily for
the configuration process. All pins used during configura-
tion are shown in Table 22 on page 58.
Master Modes
Slave Serial Mode
The three Master modes use an internal oscillator to gener-
ate a Configuration Clock (CCLK) for driving potential slave
devices. They also generate address and timing for exter-
nal PROM(s) containing the configuration data.
In Slave Serial mode, the FPGA receives serial configura-
tion data on the rising edge of CCLK and, after loading its
configuration, passes additional data out, resynchronized
on the next falling edge of CCLK.
Master Parallel (Up or Down) modes generate the CCLK
signal and PROM addresses and receive byte parallel data.
The data is internally serialized into the FPGA data-frame
format. The up and down selection generates starting
addresses at either zero or 3FFFF (3FFFFF when 22
address lines are used), for compatibility with different
microprocessor addressing conventions. The Master Serial
mode generates CCLK and receives the configuration data
in serial form from a Xilinx serial-configuration PROM.
Multiple slave devices with identical configurations can be
wired with parallel DIN inputs. In this way, multiple devices
can be configured simultaneously.
Serial Daisy Chain
Multiple devices with different configurations can be con-
nected together in a “daisy chain,” and a single combined
bitstream used to configure the chain of slave devices.
To configure a daisy chain of devices, wire the CCLK pins
of all devices in parallel, as shown in Figure 51 on page
60. Connect the DOUT of each device to the DIN of the
next. The lead or master FPGA and following slaves each
passes resynchronized configuration data coming from a
single source. The header data, including the length count,
CCLK speed is selectable as either 1 MHz (default) or 8
MHz. Configuration always starts at the default slow fre-
quency, then can switch to the higher frequency during the
first frame. Frequency tolerance is -50% to +25%.
6-46
May 14, 1999 (Version 1.6)
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
is passed through and is captured by each FPGA when it
recognizes the 0010 preamble. Following the length-count
data, each FPGA outputs a High on DOUT until it has
received its required number of data frames.
tiated and most boundary scan instructions cannot be
used.
The user has some control over the relative timing of these
events and can, therefore, make sure that they occur at the
proper time and the finish point F is reached. Timing is con-
trolled using options in the bitstream generation software.
After an FPGA has received its configuration data, it
passes on any additional frame start bits and configuration
data on DOUT. When the total number of configuration
clocks applied after memory initialization equals the value
of the 24-bit length count, the FPGAs begin the start-up
sequence and become operational together. FPGA I/O are
normally released two CCLK cycles after the last configura-
tion bit is received. Figure 47 on page 53 shows the
start-up timing for an XC4000 Series device.
XC3000 Master with an XC4000 Series Slave
Some designers want to use an inexpensive lead device in
peripheral mode and have the more precious I/O pins of the
XC4000 Series devices all available for user I/O. Figure 44
provides a solution for that case.
This solution requires one CLB, one IOB and pin, and an
internal oscillator with a frequency of up to 5 MHz as a
clock source. The XC3000 master device must be config-
ured with late Internal Reset, which is the default option.
The daisy-chained bitstream is not simply a concatenation
of the individual bitstreams. The PROM file formatter must
be used to combine the bitstreams for a daisy-chained con-
figuration.
One CLB and one IOB in the lead XC3000-family device
are used to generate the additional CCLK pulse required by
the XC4000 Series devices. When the lead device removes
the internal RESET signal, the 2-bit shift register responds
to its clock input and generates an active Low output signal
for the duration of the subsequent clock period. An external
connection between this output and CCLK thus creates the
extra CCLK pulse.
Multi-Family Daisy Chain
All Xilinx FPGAs of the XC2000, XC3000, and XC4000
Series use a compatible bitstream format and can, there-
fore, be connected in a daisy chain in an arbitrary
sequence. There is, however, one limitation. The lead
device must belong to the highest family in the chain. If the
chain contains XC4000 Series devices, the master nor-
mally cannot be an XC2000 or XC3000 device.
6
The reason for this rule is shown in Figure 47 on page 53.
Since all devices in the chain store the same length count
value and generate or receive one common sequence of
CCLK pulses, they all recognize length-count match on the
same CCLK edge, as indicated on the left edge of
Figure 47. The master device then generates additional
CCLK pulses until it reaches its finish point F. The different
families generate or require different numbers of additional
CCLK pulses until they reach F. Not reaching F means that
the device does not really finish its configuration, although
DONE may have gone High, the outputs became active,
and the internal reset was released. For the XC4000 Series
device, not reaching F means that readback cannot be ini-
OE/T
Output
Connected
to CCLK
Reset
0
1
1
0
0
0
0
1
1
1
Active Low Output
Active High Output
etc
.
.
.
.
X5223
Figure 44: CCLK Generation for XC3000 Master
Driving an XC4000 Series Slave
May 14, 1999 (Version 1.6)
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XC4000E and XC4000X Series Field Programmable Gate Arrays
Setting CCLK Frequency
Data Stream Format
For Master modes, CCLK can be generated in either of two
frequencies. In the default slow mode, the frequency
ranges from 0.5 MHz to 1.25 MHz for XC4000E and
XC4000EX devices and from 0.6 MHz to 1.8 MHz for
XC4000XL devices. In fast CCLK mode, the frequency
ranges from 4 MHz to 10 MHz for XC4000EX devices and
from 5 MHz to 15 MHz for XC4000XL devices. The fre-
quency is selected by an option when running the bitstream
generation software. If an XC4000 Series Master is driving
an XC3000- or XC2000-family slave, slow CCLK mode
must be used. In addition, an XC4000XL device driving a
XC4000E or XC4000EX should use slow mode. Slow mode
is the default.
The data stream (“bitstream”) format is identical for all con-
figuration modes.
The data stream formats are shown in Table 19. Bit-serial
data is read from left to right, and byte-parallel data is effec-
tively assembled from this serial bitstream, with the first bit
in each byte assigned to D0.
The configuration data stream begins with a string of eight
ones, a preamble code, followed by a 24-bit length count
and a separator field of ones. This header is followed by the
actual configuration data in frames. The length and number
of frames depends on the device type (see Table 20 and
Table 21). Each frame begins with a start field and ends
with an error check. A postamble code is required to signal
the end of data for a single device. In all cases, additional
start-up bytes of data are required to provide four clocks for
the startup sequence at the end of configuration. Long
daisy chains require additional startup bytes to shift the last
data through the chain. All startup bytes are don’t-cares;
these bytes are not included in bitstreams created by the
Xilinx software.
Table 19: XC4000 Series Data Stream Formats
All Other
Data Type
Modes (D0...)
Fill Byte
11111111b
0010b
Preamble Code
Length Count
Fill Bits
COUNT(23:0)
1111b
A selection of CRC or non-CRC error checking is allowed
by the bitstream generation software. The non-CRC error
checking tests for a designated end-of-frame field for each
frame. For CRC error checking, the software calculates a
running CRC and inserts a unique four-bit partial check at
the end of each frame. The 11-bit CRC check of the last
frame of an FPGA includes the last seven data bits.
Start Field
Data Frame
0b
DATA(n-1:0)
CRC or Constant
Field Check
xxxx (CRC)
or 0110b
Extend Write Cycle
Postamble
Start-Up Bytes
Legend:
—
01111111b
xxh
Detection of an error results in the suspension of data load-
ing and the pulling down of the INIT pin. In Master modes,
CCLK and address signals continue to operate externally.
The user must detect INIT and initialize a new configuration
by pulsing the PROGRAM pin Low or cycling Vcc.
Not shaded
Light
Once per bitstream
Once per data frame
Once per device
Dark
6-48
May 14, 1999 (Version 1.6)
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XC4000E and XC4000X Series Field Programmable Gate Arrays
Table 20: XC4000E Program Data
Device
XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E
Max Logic Gates
3,000
5,000
6,000
8,000
10,000
13,000
20,000
25,000
CLBs
100
196
256
324
400
576
784
1,024
(Row x Col.)
(10 x 10)
(14 x 14)
(16 x 16)
(18 x 18)
(20 x 20)
(24 x 24)
(28 x 28)
(32 x 32)
IOBs
80
360
112
616
128
768
144
936
160
1,120
226
192
1,536
266
224
2,016
256
2,560
Flip-Flops
Bits per Frame
Frames
126
166
186
206
306
346
428
572
644
716
788
932
1,076
1,220
Program Data
53,936
53,984
94,960
95,008
119,792
119,840
147,504
147,552
178,096
178,144
247,920
247,968
329,264
329,312
422,128
422,176
PROM Size
(bits)
Notes: 1. Bits per Frame = (10 x number of rows) + 7 for the top + 13 for the bottom + 1 + 1 start bit + 4 error check bits
Number of Frames = (36 x number of columns) + 26 for the left edge + 41 for the right edge + 1
Program Data = (Bits per Frame x Number of Frames) + 8 postamble bits
PROM Size = Program Data + 40 (header) + 8
2. The user can add more “one” bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end of
any frame, following the four error check bits. However, the Length Count value must be adjusted for all such extra “one”
bits, even for extra leading ones at the beginning of the header.
Table 21: XC4000EX/XL Program Data
Device
XC4002XL XC4005 XC4010 XC4013 XC4020 XC4028 XC4036 XC4044
XC4052
XC4062
XC4085
6
Max Logic
Gates
2,000
5,000
10,000
13,000
20,000
28,000
36,000
44,000
52,000
62,000
85,000
CLBs
64
196
400
576
784
1,024
1,296
1,600
1,936
2,304
3,136
(Row x
Column)
(8 x 8)
(14 x 14) (20 x 20) (24 x 24) (28 x 28) (32 x 32) (36 x 36) (40 x 40) (44 x 44) (48 x 48) (56 x 56)
IOBs
64
112
616
205
160
1,120
277
192
1,536
325
224
2,016
373
256
2,560
421
288
3,168
469
320
3,840
517
352
4,576
565
384
5,376
613
448
7,168
709
Flip-Flops
256
133
Bits per
Frame
Frames
459
741
1,023
1,211
1,399
1,587
1,775
1,963
2,151
2,339
2,715
Program Data
61,052
61,104
151,910 283,376 393,580 521,832 668,124 832,480 1,014,876 1,215,320 1,433,804 1,924,940
151,960 283,424 393,632 521,880 668,172 832,528 1,014,924 1,215,368 1,433,852 1,924,992
PROM Size
(bits)
Notes: 1. Bits per frame = (13 x number of rows) + 9 for the top + 17 for the bottom + 8 + 1 start bit + 4 error check bits.
Frames = (47 x number of columns) + 27 for the left edge + 52 for the right edge + 4.
Program data = (bits per frame x number of frames) + 5 postamble bits.
PROM size = (program data + 40 header bits + 8 start bits) rounded up to the nearest byte.
2. The user can add more “one” bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end
of any frame, following the four error check bits. However, the Length Count value must be adjusted for all such extra “one”
bits, even for extra leading “ones” at the beginning of the header.
figuration process with a potentially corrupted bitstream is
terminated. The FPGA pulls the INIT pin Low and goes into
a Wait state.
Cyclic Redundancy Check (CRC) for
Configuration and Readback
The Cyclic Redundancy Check is a method of error detec-
During Readback, 11 bits of the 16-bit checksum are added
tion in data transmission applications. Generally, the trans-
to the end of the Readback data stream. The checksum is
mitting system performs a calculation on the serial
computed using the CRC-16 CCITT polynomial, as shown
bitstream. The result of this calculation is tagged onto the
in Figure 45. The checksum consists of the 11 most signif-
data stream as additional check bits. The receiving system
icant bits of the 16-bit code. A change in the checksum indi-
performs an identical calculation on the bitstream and com-
cates a change in the Readback bitstream. A comparison
pares the result with the received checksum.
to a previous checksum is meaningful only if the readback
Each data frame of the configuration bitstream has four
error bits at the end, as shown in Table 19. If a frame data
error is detected during the loading of the FPGA, the con-
data is independent of the current device state. CLB out-
puts should not be included (Read Capture option not
May 14, 1999 (Version 1.6)
6-49
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
used), and if RAM is present, the RAM content must be
unchanged.
V
No
Statistically, one error out of 2048 might go undetected.
CC
>3.5 V
Boundary Scan
Instructions
Available:
Configuration Sequence
Yes
There are four major steps in the XC4000 Series power-up
configuration sequence.
Test M0 Generate
One Time-Out Pulse
of 16 or 64 ms
PROGRAM
= Low
•
•
•
•
Configuration Memory Clear
Initialization
Configuration
Yes
Keep Clearing
Configuration Memory
Start-Up
The full process is illustrated in Figure 46.
EXTEST*
SAMPLE/PRELOAD
BYPASS
Completely Clear
Configuration Memory
Once More
Configuration Memory Clear
~1.3 µs per Frame
CONFIGURE*
(* if PROGRAM = High)
When power is first applied or is reapplied to an FPGA, an
internal circuit forces initialization of the configuration logic.
When Vcc reaches an operational level, and the circuit
passes the write and read test of a sample pair of configu-
ration bits, a time delay is started. This time delay is nomi-
nally 16 ms, and up to 10% longer in the low-voltage
devices. The delay is four times as long when in Master
Modes (M0 Low), to allow ample time for all slaves to reach
a stable Vcc. When all INIT pins are tied together, as rec-
ommended, the longest delay takes precedence. There-
fore, devices with different time delays can easily be mixed
and matched in a daisy chain.
INIT
High? if
Master
No
Master Waits 50 to 250 µs
Before Sampling Mode Lines
Yes
Sample
Mode Lines
Master CCLK
Goes Active
Load One
Configuration
Data Frame
This delay is applied only on power-up. It is not applied
when re-configuring an FPGA by pulsing the PROGRAM
pin
Yes
Frame
Error
Pull INIT Low
and Stop
X2
X15
No
X16
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
15
SAMPLE/PRELOAD
Config-
uration
memory
Full
No
BYPASS
SERIAL DATA IN
Yes
Polynomial: X16 + X15 + X2 + 1
Pass
Configuration
Data to DOUT
1
1
1
1
1
0
15 14 13 12 11 10
9
8
7
6
5
LAST DATA FRAME
CRC – CHECKSUM
CCLK
Count Equals
Length
No
X1789
Readback Data Stream
Count
Yes
Figure 45: Circuit for Generating CRC-16
Start-Up
Sequence
F
Operational
EXTEST
SAMPLE PRELOAD
BYPASS
If Boundary Scan
is Selected
USER 1
USER 2
CONFIGURE
READBACK
X6076
Figure 46: Power-up Configuration Sequence
6-50
May 14, 1999 (Version 1.6)
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Low. During this time delay, or as long as the PROGRAM
input is asserted, the configuration logic is held in a Config-
uration Memory Clear state. The configuration-memory
frames are consecutively initialized, using the internal oscil-
lator.
rise time is excessive or poorly defined. As long as PRO-
GRAM is Low, the FPGA keeps clearing its configuration
memory. When PROGRAM goes High, the configuration
memory is cleared one more time, followed by the begin-
ning of configuration, provided the INIT input is not exter-
nally held Low. Note that a Low on the PROGRAM input
automatically forces a Low on the INIT output. The XC4000
Series PROGRAM pin has a permanent weak pull-up.
At the end of each complete pass through the frame
addressing, the power-on time-out delay circuitry and the
level of the PROGRAM pin are tested. If neither is asserted,
the logic initiates one additional clearing of the configura-
tion frames and then tests the INIT input.
Using an open-collector or open-drain driver to hold INIT
Low before the beginning of configuration causes the
FPGA to wait after completing the configuration memory
clear operation. When INIT is no longer held Low exter-
nally, the device determines its configuration mode by cap-
turing its mode pins, and is ready to start the configuration
process. A master device waits up to an additional 250 µs
to make sure that any slaves in the optional daisy chain
have seen that INIT is High.
Initialization
During initialization and configuration, user pins HDC, LDC,
INIT and DONE provide status outputs for the system inter-
face. The outputs LDC, INIT and DONE are held Low and
HDC is held High starting at the initial application of power.
The open drain INIT pin is released after the final initializa-
tion pass through the frame addresses. There is a deliber-
ate delay of 50 to 250 µs (up to 10% longer for low-voltage
devices) before a Master-mode device recognizes an inac-
tive INIT. Two internal clocks after the INIT pin is recognized
as High, the FPGA samples the three mode lines to deter-
mine the configuration mode. The appropriate interface
lines become active and the configuration preamble and
data can be loaded.Configuration
Start-Up
Start-up is the transition from the configuration process to
the intended user operation. This transition involves a
change from one clock source to another, and a change
from interfacing parallel or serial configuration data where
most outputs are 3-stated, to normal operation with I/O pins
active in the user-system. Start-up must make sure that the
user-logic ‘wakes up’ gracefully, that the outputs become
active without causing contention with the configuration sig-
nals, and that the internal flip-flops are released from the
global Reset or Set at the right time.
6
The 0010 preamble code indicates that the following 24 bits
represent the length count. The length count is the total
number of configuration clocks needed to load the com-
plete configuration data. (Four additional configuration
clocks are required to complete the configuration process,
as discussed below.) After the preamble and the length
count have been passed through to all devices in the daisy
chain, DOUT is held High to prevent frame start bits from
reaching any daisy-chained devices.
Figure 47 describes start-up timing for the three Xilinx fam-
ilies in detail. The configuration modes can use any of the
four timing sequences.
To access the internal start-up signals, place the STARTUP
library symbol.
A specific configuration bit, early in the first frame of a mas-
ter device, controls the configuration-clock rate and can
increase it by a factor of eight. Therefore, if a fast configu-
ration clock is selected by the bitstream, the slower clock
rate is used until this configuration bit is detected.
Start-up Timing
Different FPGA families have different start-up sequences.
The XC2000 family goes through a fixed sequence. DONE
goes High and the internal global Reset is de-activated one
CCLK period after the I/O become active.
Each frame has a start field followed by the frame-configu-
ration data bits and a frame error field. If a frame data error
is detected, the FPGA halts loading, and signals the error
by pulling the open-drain INIT pin Low. After all configura-
tion frames have been loaded into an FPGA, DOUT again
follows the input data so that the remaining data is passed
on to the next device.
The XC3000A family offers some flexibility. DONE can be
programmed to go High one CCLK period before or after
the I/O become active. Independent of DONE, the internal
global Reset is de-activated one CCLK period before or
after the I/O become active.
The XC4000 Series offers additional flexibility. The three
events — DONE going High, the internal Set/Reset being
de-activated, and the user I/O going active — can all occur
in any arbitrary sequence. Each of them can occur one
CCLK period before or after, or simultaneous with, any of
the others. This relative timing is selected by means of soft-
ware options in the bitstream generation software.
Delaying Configuration After Power-Up
There are two methods of delaying configuration after
power-up: put a logic Low on the PROGRAM input, or pull
the bidirectional INIT pin Low, using an open-collector
(open-drain) driver. (See Figure 46 on page 50.)
A Low on the PROGRAM input is the more radical
approach, and is recommended when the power-supply
May 14, 1999 (Version 1.6)
6-51
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XC4000E and XC4000X Series Field Programmable Gate Arrays
The default option, and the most practical one, is for DONE
to go High first, disconnecting the configuration data source
and avoiding any contention when the I/Os become active
one clock later. Reset/Set is then released another clock
period later to make sure that user-operation starts from
stable internal conditions. This is the most common
sequence, shown with heavy lines in Figure 47, but the
designer can modify it to meet particular requirements.
received since INIT went High equals the loaded value of
the length count.
The next rising clock edge sets a flip-flop Q0, shown in
Figure 48. Q0 is the leading bit of a 5-bit shift register. The
outputs of this register can be programmed to control three
events.
•
•
The release of the open-drain DONE output
The change of configuration-related pins to the user
function, activating all IOBs.
Normally, the start-up sequence is controlled by the internal
device oscillator output (CCLK), which is asynchronous to
the system clock.
•
The termination of the global Set/Reset initialization of
all CLB and IOB storage elements.
XC4000 Series offers another start-up clocking option,
UCLK_NOSYNC. The three events described above need
not be triggered by CCLK. They can, as a configuration
option, be triggered by a user clock. This means that the
device can wake up in synchronism with the user system.
The DONE pin can also be wire-ANDed with DONE pins of
other FPGAs or with other external signals, and can then
be used as input to bit Q3 of the start-up register. This is
called “Start-up Timing Synchronous to Done In” and is
selected by either CCLK_SYNC or UCLK_SYNC.
When the UCLK_SYNC option is enabled, the user can
externally hold the open-drain DONE output Low, and thus
stall all further progress in the start-up sequence until
DONE is released and has gone High. This option can be
used to force synchronization of several FPGAs to a com-
mon user clock, or to guarantee that all devices are suc-
cessfully configured before any I/Os go active.
When DONE is not used as an input, the operation is called
“Start-up Timing Not Synchronous to DONE In,” and is
selected by either CCLK_NOSYNC or UCLK_NOSYNC.
As a configuration option, the start-up control register
beyond Q0 can be clocked either by subsequent CCLK
pulses or from an on-chip user net called STARTUP.CLK.
These signals can be accessed by placing the STARTUP
library symbol.
If either of these two options is selected, and no user clock
is specified in the design or attached to the device, the chip
could reach a point where the configuration of the device is
complete and the Done pin is asserted, but the outputs do
not become active. The solution is either to recreate the bit-
stream specifying the start-up clock as CCLK, or to supply
the appropriate user clock.
Start-up from CCLK
If CCLK is used to drive the start-up, Q0 through Q3 pro-
vide the timing. Heavy lines in Figure 47 show the default
timing, which is compatible with XC2000 and XC3000
devices using early DONE and late Reset. The thin lines
indicate all other possible timing options.
Start-up Sequence
The Start-up sequence begins when the configuration
memory is full, and the total number of configuration clocks
6-52
May 14, 1999 (Version 1.6)
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Length Count Match
CCLK Period
CCLK
F
DONE
I/O
XC2000
Global Reset
F = Finished, no more
configuration clocks needed
Daisy-chain lead device
must have latest F
F
DONE
I/O
XC3000
Heavy lines describe
default timing
Global Reset
F
DONE
I/O
C1
C2
C2
C3
C3
C4
XC4000E/X
CCLK_NOSYNC
C4
6
GSR Active
C2
C3
C4
DONE IN
F
DONE
I/O
C1, C2 or C3
Di
XC4000E/X
CCLK_SYNC
Di+1
Di+1
GSR Active
Di
F
DONE
I/O
C1
U2
U2
U3
U3
U4
XC4000E/X
UCLK_NOSYNC
U4
GSR Active
U2
U3
U4
DONE IN
F
DONE
I/O
C1
U2
XC4000E/X
UCLK_SYNC
Di
Di+1
Di+2
Di+2
GSR Active
Di Di+1
Synchronization
Uncertainty
UCLK Period
X9024
Figure 47: Start-up Timing
May 14, 1999 (Version 1.6)
6-53
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XC4000E and XC4000X Series Field Programmable Gate Arrays
Start-up from a User Clock (STARTUP.CLK)
Release of User I/O After DONE Goes High
When, instead of CCLK, a user-supplied start-up clock is
selected, Q1 is used to bridge the unknown phase relation-
ship between CCLK and the user clock. This arbitration
causes an unavoidable one-cycle uncertainty in the timing
of the rest of the start-up sequence.
By default, the user I/O are released one CCLK cycle after
the DONE pin goes High. If CCLK is not clocked after
DONE goes High, the outputs remain in their initial state —
3-stated, with a 50 kΩ - 100 kΩ pull-up. The delay from
DONE High to active user I/O is controlled by an option to
the bitstream generation software.
DONE Goes High to Signal End of Configuration
Release of Global Set/Reset After DONE Goes
High
XC4000 Series devices read the expected length count
from the bitstream and store it in an internal register. The
length count varies according to the number of devices and
the composition of the daisy chain. Each device also counts
the number of CCLKs during configuration.
By default, Global Set/Reset (GSR) is released two CCLK
cycles after the DONE pin goes High. If CCLK is not
clocked twice after DONE goes High, all flip-flops are held
in their initial set or reset state. The delay from DONE High
to GSR inactive is controlled by an option to the bitstream
generation software.
Two conditions have to be met in order for the DONE pin to
go high:
•
•
the chip's internal memory must be full, and
the configuration length count must be met, exactly.
Configuration Complete After DONE Goes High
This is important because the counter that determines
when the length count is met begins with the very first
CCLK, not the first one after the preamble.
Three full CCLK cycles are required after the DONE pin
goes High, as shown in Figure 47 on page 53. If CCLK is
not clocked three times after DONE goes High, readback
cannot be initiated and most boundary scan instructions
cannot be used.
Therefore, if a stray bit is inserted before the preamble, or
the data source is not ready at the time of the first CCLK,
the internal counter that holds the number of CCLKs will be
one ahead of the actual number of data bits read. At the
end of configuration, the configuration memory will be full,
but the number of bits in the internal counter will not match
the expected length count.
Configuration Through the Boundary Scan
Pins
XC4000 Series devices can be configured through the
boundary scan pins. The basic procedure is as follows:
As a consequence, a Master mode device will continue to
send out CCLKs until the internal counter turns over to
zero, and then reaches the correct length count a second
time. This will take several seconds [224 CCLK period] —
which is sometimes interpreted as the device not configur-
ing at all.
•
Power up the FPGA with INIT held Low (or drive the
PROGRAM pin Low for more than 300 ns followed by a
High while holding INIT Low). Holding INIT Low allows
enough time to issue the CONFIG command to the
FPGA. The pin can be used as I/O after configuration if
a resistor is used to hold INIT Low.
•
•
•
Issue the CONFIG command to the TMS input
Wait for INIT to go High
Sequence the boundary scan Test Access Port to the
SHIFT-DR state
If it is not possible to have the data ready at the time of the
first CCLK, the problem can be avoided by increasing the
number in the length count by the appropriate value. The
XACT User Guide includes detailed information about man-
ually altering the length count.
•
Toggle TCK to clock data into TDI pin.
The user must account for all TCK clock cycles after INIT
goes High, as all of these cycles affect the Length Count
compare.
Note that DONE is an open-drain output and does not go
High unless an internal pull-up is activated or an external
pull-up is attached. The internal pull-up is activated as the
default by the bitstream generation software.
For more detailed information, refer to the Xilinx application
note XAPP017, “Boundary Scan in XC4000 Devices.” This
application note also applies to XC4000E and XC4000X
devices.
6-54
May 14, 1999 (Version 1.6)
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Q3
Q2
Q1/Q4
DONE
IN
STARTUP
IOBs OPERATIONAL PER CONFIGURATION
*
*
GLOBAL SET/RESET OF
ALL CLB AND IOB FLIP-FLOP
1
0
GSR ENABLE
GSR INVERT
STARTUP.GSR
CONTROLLED BY STARTUP SYMBOL
IN THE USER SCHEMATIC (SEE
LIBRARIES GUIDE)
STARTUP.GTS
GTS INVERT
GTS ENABLE
0
1
GLOBAL 3-STATE OF ALL IOBs
Q
S
R
DONE
" FINISHED "
ENABLES BOUNDARY
SCAN, READBACK AND
CONTROLS THE OSCILLATOR
*
1
0
1
0
Q0
Q1
Q2
Q3
Q4
1
FULL
LENGTH COUNT
6
S
Q
D
Q
D
Q
D
Q
D
Q
0
M
K
K
K
K
K
*
CLEAR MEMORY
CCLK
0
1
STARTUP.CLK
USER NET
M
CONFIGURATION BIT OPTIONS SELECTED BY USER IN "MAKEBITS"
X1528
*
*
Figure 48: Start-up Logic
BACK library symbol and attach the appropriate pad sym-
bols, as shown in Figure 49.
Readback
The user can read back the content of configuration mem-
ory and the level of certain internal nodes without interfer-
ing with the normal operation of the device.
After Readback has been initiated by a High level on
RDBK.TRIG after configuration, the RDBK.RIP (Read In
Progress) output goes High on the next rising edge of
RDBK.CLK. Subsequent rising edges of this clock shift out
Readback data on the RDBK.DATA net.
Readback not only reports the downloaded configuration
bits, but can also include the present state of the device,
represented by the content of all flip-flops and latches in
CLBs and IOBs, as well as the content of function genera-
tors used as RAMs.
Readback data does not include the preamble, but starts
with five dummy bits (all High) followed by the Start bit
(Low) of the first frame. The first two data bits of the first
frame are always High.
Note that in XC4000 Series devices, configuration data is
not inverted with respect to configuration as it is in XC2000
and XC3000 families.
Each frame ends with four error check bits. They are read
back as High. The last seven bits of the last frame are also
read back as High. An additional Start bit (Low) and an
11-bit Cyclic Redundancy Check (CRC) signature follow,
before RDBK.RIP returns Low.
XC4000 Series Readback does not use any dedicated
pins, but uses four internal nets (RDBK.TRIG, RDBK.DATA,
RDBK.RIP and RDBK.CLK) that can be routed to any IOB.
To access the internal Readback signals, place the READ-
May 14, 1999 (Version 1.6)
6-55
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
IF UNCONNECTED,
DEFAULT IS CCLK
DATA
RIP
READ_DATA
CLK
MD1
READBACK
OBUF
READ_TRIGGER
TRIG
MD0
X1786
IBUF
Figure 49: Readback Schematic Example
Readback Options
I/O
I/O
Readback options are: Read Capture, Read Abort, and
Clock Select. They are set with the bitstream generation
software.
PROGRAMMABLE
INTERCONNECT
Read Capture
When the Read Capture option is selected, the readback
data stream includes sampled values of CLB and IOB sig-
nals. The rising edge of RDBK.TRIG latches the inverted
values of the four CLB outputs, the IOB output flip-flops and
the input signals I1 and I2. Note that while the bits describ-
ing configuration (interconnect, function generators, and
RAM content) are not inverted, the CLB and IOB output sig-
nals are inverted.
rdbk
I/O
I/O
I/O
rdclk
X1787
Figure 50: READBACK Symbol in Graphical Editor
Violating the Maximum High and Low Time
Specification for the Readback Clock
When the Read Capture option is not selected, the values
of the capture bits reflect the configuration data originally
written to those memory locations.
The readback clock has a maximum High and Low time
specification. In some cases, this specification cannot be
met. For example, if a processor is controlling readback, an
interrupt may force it to stop in the middle of a readback.
This necessitates stopping the clock, and thus violating the
specification.
If the RAM capability of the CLBs is used, RAM data are
available in readback, since they directly overwrite the F
and G function-table configuration of the CLB.
The specification is mandatory only on clocking data at the
end of a frame prior to the next start bit. The transfer mech-
anism will load the data to a shift register during the last six
clock cycles of the frame, prior to the start bit of the follow-
ing frame. This loading process is dynamic, and is the
source of the maximum High and Low time requirements.
RDBK.TRIG is located in the lower-left corner of the device,
as shown in Figure 50.
Read Abort
When the Read Abort option is selected, a High-to-Low
transition on RDBK.TRIG terminates the readback opera-
tion and prepares the logic to accept another trigger.
Therefore, the specification only applies to the six clock
cycles prior to and including any start bit, including the
clocks before the first start bit in the readback data stream.
At other times, the frame data is already in the register and
the register is not dynamic. Thus, it can be shifted out just
like a regular shift register.
After an aborted readback, additional clocks (up to one
readback clock per configuration frame) may be required to
re-initialize the control logic. The status of readback is indi-
cated by the output control net RDBK.RIP. RDBK.RIP is
High whenever a readback is in progress.
The user must precisely calculate the location of the read-
back data relative to the frame. The system must keep track
of the position within a data frame, and disable interrupts
before frame boundaries. Frame lengths and data formats
are listed in Table 19, Table 20 and Table 21.
Clock Select
CCLK is the default clock. However, the user can insert
another clock on RDBK.CLK. Readback control and data
are clocked on rising edges of RDBK.CLK. If readback
must be inhibited for security reasons, the readback control
nets are simply not connected.
Readback with the XChecker Cable
The XChecker Universal Download/Readback Cable and
Logic Probe uses the readback feature for bitstream verifi-
cation. It can also display selected internal signals on the
PC or workstation screen, functioning as a low-cost in-cir-
cuit emulator.
RDBK.CLK is located in the lower right chip corner, as
shown in Figure 50.
6-56
May 14, 1999 (Version 1.6)
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000E/EX/XL Program Readback Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements.
The following guidelines reflect worst-case values over the recommended operating conditions.
Finished
Internal Net
rdbk.TRIG
T
RCRT
T
RCRT
2
T
RTRC
T
RTRC
2
1
1
rdclk.I
5
6
T
RCL
T
RCH
4
rdbk.RIP
T
RCRR
DUMMY
DUMMY
VALID
VALID
rdbk.DATA
T
RCRD
7
X1790
6
E/EX
Description
Symbol
Min
Max
Units
rdbk.TRIG
rdclk.1
rdbk.TRIG setup to initiate and abort Readback
rdbk.TRIG hold to initiate and abort Readback
1
2
TRTRC
TRCRT
200
50
-
-
ns
ns
rdbk.DATA delay
rdbk.RIP delay
High time
7
6
5
4
TRCRD
TRCRR
TRCH
-
-
250
250
500
500
ns
ns
ns
ns
250
250
Low time
TRCL
Note 1:
Note 2:
Timing parameters apply to all speed grades.
If rdbk.TRIG is High prior to Finished, Finished will trigger the first Readback.
XL
Description
Symbol
Min
Max
Units
rdbk.TRIG
rdclk.1
rdbk.TRIG setup to initiate and abort Readback
rdbk.TRIG hold to initiate and abort Readback
1
2
TRTRC
TRCRT
200
50
-
-
ns
ns
rdbk.DATA delay
rdbk.RIP delay
High time
7
6
5
4
TRCRD
TRCRR
TRCH
-
-
250
250
500
500
ns
ns
ns
ns
250
250
Low time
TRCL
Note 1:
Note 2:
Timing parameters apply to all speed grades.
If rdbk.TRIG is High prior to Finished, Finished will trigger the first Readback.
May 14, 1999 (Version 1.6)
6-57
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Table 22: Pin Functions During Configuration
CONFIGURATION MODE <M2:M1:M0>
SLAVE
SERIAL
<1:1:1>
M2(HIGH) (I)
M1(HIGH) (I)
M0(HIGH) (I)
HDC (HIGH)
LDC (LOW)
INIT
MASTER
SERIAL
<0:0:0>
M2(LOW) (I)
M1(LOW) (I)
M0(LOW) (I)
HDC (HIGH)
LDC (LOW)
INIT
SYNCH.
PERIPHERAL
<0:1:1>
M2(LOW) (I)
M1(HIGH) (I)
M0(HIGH) (I)
HDC (HIGH)
LDC (LOW)
INIT
ASYNCH.
MASTER
MASTER
USER
OPERATION
PERIPHERAL PARALLEL DOWN PARALLEL UP
<1:0:1>
M2(HIGH) (I)
M1(LOW) (I)
M0(HIGH) (I)
HDC (HIGH)
LDC (LOW)
INIT
<1:1:0>
M2(HIGH) (I)
M1(HIGH) (I)
M0(LOW) (I)
HDC (HIGH)
LDC (LOW)
INIT
<1:0:0>
M2(HIGH) (I)
M1(LOW) (I)
M0(LOW) (I)
HDC (HIGH)
LDC (LOW)
INIT
(I)
(O)
(I)
I/O
I/O
I/O
DONE
DONE
DONE
DONE
DONE
DONE
DONE
PROGRAM (I)
CCLK (I)
PROGRAM (I)
CCLK (O)
PROGRAM (I)
CCLK (I)
RDY/BUSY (O)
PROGRAM (I)
CCLK (O)
RDY/BUSY (O)
RS (I)
PROGRAM (I)
CCLK (O)
RCLK (O)
PROGRAM (I)
CCLK (O)
RCLK (O)
PROGRAM
CCLK (I)
I/O
I/O
CS0 (I)
I/O
DATA 7 (I)
DATA 6 (I)
DATA 5 (I)
DATA 4 (I)
DATA 3 (I)
DATA 2 (I)
DATA 1 (I)
DATA 0 (I)
DOUT
DATA 7 (I)
DATA 6 (I)
DATA 5 (I)
DATA 4 (I)
DATA 3 (I)
DATA 2 (I)
DATA 1 (I)
DATA 0 (I)
DOUT
DATA 7 (I)
DATA 6 (I)
DATA 5 (I)
DATA 4 (I)
DATA 3 (I)
DATA 2 (I)
DATA 1 (I)
DATA 0 (I)
DOUT
TDI
DATA 7 (I)
DATA 6 (I)
DATA 5 (I)
DATA 4 (I)
DATA 3 (I)
DATA 2 (I)
DATA 1 (I)
DATA 0 (I)
DOUT
TDI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DIN (I)
DOUT
TDI
DIN (I)
DOUT
TDI
SGCK4-GCK5-I/O
TDI
TDI
TDI-I/O
TCK
TCK
TCK
TCK
TCK
TCK
TCK-I/O
TMS
TDO
TMS
TDO
TMS
TDO
TMS
TDO
TMS
TDO
TMS
TDO
TMS-I/O
TDO-(O)
WS (I)
A0
A0
I/O
A1
A1
PGCK4-GCK6-I/O
CS1
A2
A2
I/O
A3
A3
I/O
A4
A4
I/O
A5
A5
I/O
A6
A6
I/O
A7
A7
I/O
A8
A8
I/O
A9
A9
I/O
A10
A10
I/O
A11
A11
I/O
A12
A12
I/O
A13
A13
I/O
A14
A14
I/O
A15
A15
SGCK1-GCK7-I/O
A16
A16
PGCK1-GCK8-I/O
A17
A17
I/O
A18*
A18*
I/O
A19*
A20*
A19*
A20*
I/O
I/O
A21*
A21*
I/O
ALL OTHERS
6-58
May 14, 1999 (Version 1.6)
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Table 23: Pin Functions During Configuration
CONFIGURATION MODE <M2:M1:M0>
SLAVE
SERIAL
<1:1:1>
M2(HIGH) (I)
M1(HIGH) (I)
M0(HIGH) (I)
HDC (HIGH)
LDC (LOW)
INIT
MASTER
SERIAL
<0:0:0>
M2(LOW) (I)
M1(LOW) (I)
M0(LOW) (I)
HDC (HIGH)
LDC (LOW)
INIT
SYNCH.
PERIPHERAL
<0:1:1>
M2(LOW) (I)
M1(HIGH) (I)
M0(HIGH) (I)
HDC (HIGH)
LDC (LOW)
INIT
ASYNCH.
MASTER
MASTER
USER
OPERATION
PERIPHERAL PARALLEL DOWN PARALLEL UP
<1:0:1>
M2(HIGH) (I)
M1(LOW) (I)
M0(HIGH) (I)
HDC (HIGH)
LDC (LOW)
INIT
<1:1:0>
M2(HIGH) (I)
M1(HIGH) (I)
M0(LOW) (I)
HDC (HIGH)
LDC (LOW)
INIT
<1:0:0>
M2(HIGH) (I)
M1(LOW) (I)
M0(LOW) (I)
HDC (HIGH)
LDC (LOW)
INIT
(I)
(O)
(I)
I/O
I/O
I/O
DONE
DONE
DONE
DONE
DONE
DONE
DONE
PROGRAM (I)
CCLK (I)
PROGRAM (I)
CCLK (O)
PROGRAM (I)
CCLK (I)
RDY/BUSY (O)
PROGRAM (I)
CCLK (O)
RDY/BUSY (O)
RS (I)
PROGRAM (I)
CCLK (O)
RCLK (O)
PROGRAM (I)
CCLK (O)
RCLK (O)
PROGRAM
CCLK (I)
I/O
I/O
CS0 (I)
I/O
DATA 7 (I)
DATA 6 (I)
DATA 5 (I)
DATA 4 (I)
DATA 3 (I)
DATA 2 (I)
DATA 1 (I)
DATA 0 (I)
DOUT
DATA 7 (I)
DATA 6 (I)
DATA 5 (I)
DATA 4 (I)
DATA 3 (I)
DATA 2 (I)
DATA 1 (I)
DATA 0 (I)
DOUT
DATA 7 (I)
DATA 6 (I)
DATA 5 (I)
DATA 4 (I)
DATA 3 (I)
DATA 2 (I)
DATA 1 (I)
DATA 0 (I)
DOUT
TDI
DATA 7 (I)
DATA 6 (I)
DATA 5 (I)
DATA 4 (I)
DATA 3 (I)
DATA 2 (I)
DATA 1 (I)
DATA 0 (I)
DOUT
TDI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
6
DIN (I)
DOUT
TDI
DIN (I)
DOUT
TDI
SGCK4-GCK5-I/O
TDI
TDI
TDI-I/O
TCK
TCK
TCK
TCK
TCK
TCK
TCK-I/O
TMS
TDO
TMS
TDO
TMS
TDO
TMS
TDO
TMS
TDO
TMS
TDO
TMS-I/O
TDO-(O)
WS (I)
A0
A0
I/O
A1
A1
PGCK4-GCK6-I/O
CS1
A2
A2
I/O
A3
A3
I/O
A4
A4
I/O
A5
A5
I/O
A6
A6
I/O
A7
A7
I/O
A8
A8
I/O
A9
A9
I/O
A10
A10
I/O
A11
A11
I/O
A12
A12
I/O
A13
A13
I/O
A14
A14
I/O
A15
A15
SGCK1-GCK7-I/O
A16
A16
PGCK1-GCK8-I/O
A17
A17
I/O
A18*
A18*
I/O
A19*
A20*
A19*
A20*
I/O
I/O
A21*
A21*
I/O
ALL OTHERS
* XC4000X only
Notes 1. A shaded table cell represents a 50 kΩ - 100 kΩ pull-up before and during configuration.
2. (I) represents an input; (O) represents an output.
3. INIT is an open-drain output during configuration.
May 14, 1999 (Version 1.6)
6-59
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
There is an internal delay of 0.5 CCLK periods, which
means that DOUT changes on the falling CCLK edge, and
the next FPGA in the daisy chain accepts data on the sub-
sequent rising CCLK edge.
Configuration Timing
The seven configuration modes are discussed in detail in
this section. Timing specifications are included.
Figure 51 shows a full master/slave system. An XC4000
Series device in Slave Serial mode should be connected as
shown in the third device from the left.
Slave Serial Mode
In Slave Serial mode, an external signal drives the CCLK
input of the FPGA. The serial configuration bitstream must
be available at the DIN input of the lead FPGA a short
setup time before each rising CCLK edge.
Slave Serial mode is selected by a <111> on the mode pins
(M2, M1, M0). Slave Serial is the default mode if the mode
pins are left unconnected, as they have weak pull-up resis-
tors during configuration.
The lead FPGA then presents the preamble data—and all
data that overflows the lead device—on its DOUT pin.
NOTE:
NOTE:
M2, M1, M0 can be shorted
to VCC if not used as I/O
M2, M1, M0 can be shorted
to Ground if not used as I/O
VCC
4.7 KΩ
N/C
4.7 KΩ
4.7 KΩ
4.7 KΩ
4.7 KΩ
4.7 KΩ
M0 M1
M2
M0 M1
M2
M0 M1
M2
PWRDN
N/C
DOUT
DIN
DOUT
DIN
DOUT
CCLK
CCLK
VCC
XC4000E/X
MASTER
SERIAL
XC4000E/X,
XC1700D
+5 V
XC3100A
4.7 KΩ
XC5200
SLAVE
CCLK
CLK
VPP
CEO
SLAVE
DATA
DIN
LDC
INIT
CE
PROGRAM
DONE
PROGRAM
RESET
D/P
RESET/OE
DONE
INIT
INIT
(Low Reset Option Used)
PROGRAM
X9025
Figure 51: Master/Slave Serial Mode Circuit Diagram
DIN
Bit n
Bit n + 1
1
2
5
T
T
T
CCL
DCC
CCD
CCLK
4
3
T
T
CCH
CCO
DOUT
(Output)
Bit n - 1
Bit n
X5379
Description
DIN setup
Symbol
Min
20
0
Max
Units
1
2
3
4
5
TDCC
TCCD
TCCO
TCCH
TCCL
FCC
ns
ns
DIN hold
DIN to DOUT
High time
Low time
30
10
ns
CCLK
45
45
ns
ns
Frequency
MHz
Note: Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High.
Figure 52: Slave Serial Mode Programming Switching Characteristics
6-60
May 14, 1999 (Version 1.6)
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
For actual timing values please refer to “Configuration
Switching Characteristics” on page 68. Be sure that the
serial PROM and slaves are fast enough to support this
data rate. XC2000, XC3000/A, and XC3100A devices do
not support the Fast ConfigRate option.
Master Serial Mode
In Master Serial mode, the CCLK output of the lead FPGA
drives a Xilinx Serial PROM that feeds the FPGA DIN input.
Each rising edge of the CCLK output increments the Serial
PROM internal address counter. The next data bit is put on
the SPROM data output, connected to the FPGA DIN pin.
The lead FPGA accepts this data on the subsequent rising
CCLK edge.
The SPROM CE input can be driven from either LDC or
DONE. Using LDC avoids potential contention on the DIN
pin, if this pin is configured as user-I/O, but LDC is then
restricted to be a permanently High user output after con-
figuration. Using DONE can also avoid contention on DIN,
provided the early DONE option is invoked.
The lead FPGA then presents the preamble data—and all
data that overflows the lead device—on its DOUT pin.
There is an internal pipeline delay of 1.5 CCLK periods,
which means that DOUT changes on the falling CCLK
edge, and the next FPGA in the daisy chain accepts data
on the subsequent rising CCLK edge.
Figure 51 on page 60 shows a full master/slave system.
The leftmost device is in Master Serial mode.
Master Serial mode is selected by a <000> on the mode
pins (M2, M1, M0).
In the bitstream generation software, the user can specify
Fast ConfigRate, which, starting several bits into the first
frame, increases the CCLK frequency by a factor of eight.
CCLK
(Output)
T
2
CKDS
T
DSCK
1
6
Serial Data In
n
n + 1
n + 2
Serial DOUT
(Output)
n – 3
n – 2
n – 1
n
X3223
Description
DIN setup
DIN hold
Symbol
TDSCK
TCKDS
Min
20
0
Max
Units
ns
1
CCLK
2
ns
Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay configuration by pulling PROGRAM
Low until Vcc is valid.
2. Master Serial mode timing is based on testing in slave mode.
Figure 53: Master Serial Mode Programming Switching Characteristics
May 14, 1999 (Version 1.6)
6-61
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Master Parallel Down mode is selected by a <110> on the
mode pins. The EPROM addresses start at 3FFFF and
decrement.
Master Parallel Modes
In the two Master Parallel modes, the lead FPGA directly
addresses an industry-standard byte-wide EPROM, and
accepts eight data bits just before incrementing or decre-
menting the address outputs.
Additional Address lines in XC4000 devices
The XC4000X devices have additional address lines
(A18-A21) allowing the additional address space required
to daisy-chain several large devices.
The eight data bits are serialized in the lead FPGA, which
then presents the preamble data—and all data that over-
flows the lead device—on its DOUT pin. There is an inter-
nal delay of 1.5 CCLK periods, after the rising CCLK edge
that accepts a byte of data (and also changes the EPROM
address) until the falling CCLK edge that makes the LSB
(D0) of this byte appear at DOUT. This means that DOUT
changes on the falling CCLK edge, and the next FPGA in
the daisy chain accepts data on the subsequent rising
CCLK edge.
The extra address lines are programmable in XC4000EX
devices. By default these address lines are not activated. In
the default mode, the devices are compatible with existing
XC4000 and XC4000E products. If desired, the extra
address lines can be used by specifying the address lines
option in bitgen as 22 (bitgen -g AddressLines:22). The
lines (A18-A21) are driven when a master device detects,
via the bitstream, that it should be using all 22 address
lines. Because these pins will initially be pulled high by
internal pull-ups, designers using Master Parallel Up mode
should use external pull down resistors on pins A18-A21. If
Master Parallel Down mode is used external resistors are
not necessary.
The PROM address pins can be incremented or decre-
mented, depending on the mode pin settings. This option
allows the FPGA to share the PROM with a wide variety of
microprocessors and micro controllers. Some processors
must boot from the bottom of memory (all zeros) while oth-
ers must boot from the top. The FPGA is flexible and can
load its configuration bitstream from either end of the mem-
ory.
All 22 address lines are always active in Master Parallel
modes with XC4000XL devices. The additional address
lines behave identically to the lower order address lines. If
the Address Lines option in bitgen is set to 18, it will be
ignored by the XC4000XL device.
Master Parallel Up mode is selected by a <100> on the
mode pins (M2, M1, M0). The EPROM addresses start at
00000 and increment.
The additional address lines (A18-A21) are not available in
the PC84 package.
TO DIN OF OPTIONAL
DAISY-CHAINED FPGAS
HIGH
or
LOW
4.7KΩ
N/C
M2
N/C
M0 M1
TO CCLK OF OPTIONAL
DAISY-CHAINED FPGAS
CCLK
DOUT
NOTE:M0 can be shorted
to Ground if not used
as I/O.
M0 M1 M2
. . .
. . .
. . .
. . .
. . .
A17
A16
A15
A14
A13
A12
A11
A10
A9
DIN
DOUT
VCC
EPROM
(8K x 8)
(OR LARGER)
CCLK
4.7KΩ
USER CONTROL OF HIGHER
ORDER PROM ADDRESS BITS
CAN BE USED TO SELECT BETWEEN
ALTERNATIVE CONFIGURATIONS
INIT
XC4000E/X
SLAVE
A12
A11
A10
A9
PROGRAM
DONE
PROGRAM
INIT
D7
D6
D5
D4
D3
D2
D1
D0
A8
A8
A7
A7
D7
D6
D5
D4
D3
D2
D1
D0
A6
A6
A5
A5
A4
A4
A3
A3
A2
A2
A1
A1
A0
A0
DONE
OE
CE
DATA BUS
8
PROGRAM
X9026
Figure 54: Master Parallel Mode Circuit Diagram
6-62
May 14, 1999 (Version 1.6)
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
A0-A17
(output)
Address for Byte n
Address for Byte n + 1
1
T
RAC
D0-D7
Byte
3
T
2
T
RCD
DRC
RCLK
(output)
7 CCLKs
CCLK
CCLK
(output)
DOUT
(output)
D6
D7
Byte n - 1
X6078
Description
Delay to Address valid
Data setup time
Symbol
Min
Max
200
Units
6
1
2
3
TRAC
TDRC
TRCD
0
60
0
ns
ns
ns
RCLK
Data hold time
Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay configuration by pulling PROGRAM
Low until Vcc is valid.
2. The first Data byte is loaded and CCLK starts at the end of the first RCLK active cycle (rising edge).
This timing diagram shows that the EPROM requirements are extremely relaxed. EPROM access time can be longer than
500 ns. EPROM data output has no hold-time requirements.
Figure 55: Master Parallel Mode Programming Switching Characteristics
May 14, 1999 (Version 1.6)
6-63
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
The lead FPGA serializes the data and presents the pre-
amble data (and all data that overflows the lead device) on
its DOUT pin. There is an internal delay of 1.5 CCLK peri-
ods, which means that DOUT changes on the falling CCLK
edge, and the next FPGA in the daisy chain accepts data
on the subsequent rising CCLK edge.
Synchronous Peripheral Mode
Synchronous Peripheral mode can also be considered
Slave Parallel mode. An external signal drives the CCLK
input(s) of the FPGA(s). The first byte of parallel configura-
tion data must be available at the Data inputs of the lead
FPGA a short setup time before the rising CCLK edge.
Subsequent data bytes are clocked in on every eighth con-
secutive rising CCLK edge.
In order to complete the serial shift operation, 10 additional
CCLK rising edges are required after the last data byte has
been loaded, plus one more CCLK cycle for each
daisy-chained device.
The same CCLK edge that accepts data, also causes the
RDY/BUSY output to go High for one CCLK period. The pin
name is a misnomer. In Synchronous Peripheral mode it is
really an ACKNOWLEDGE signal. Synchronous operation
does not require this response, but it is a meaningful signal
for test purposes. Note that RDY/BUSY is pulled High with
a high-impedance pullup prior to INIT going High.
Synchronous Peripheral mode is selected by a <011> on
the mode pins (M2, M1, M0).
NOTE:
M2 can be shorted to Ground
if not used as I/O
N/C
N/C
4.7 kΩ
M0 M1
M2
M0 M1
CCLK
M2
CCLK
CLOCK
OPTIONAL
DAISY-CHAINED
FPGAs
8
DATA BUS
D
0-7
DIN
DOUT
DOUT
VCC
XC4000E/X
SYNCHRO-
NOUS
XC4000E/X
SLAVE
4.7 kΩ
PERIPHERAL
RDY/BUSY
INIT
CONTROL
SIGNALS
DONE
DONE
INIT
4.7 kΩ
PROGRAM
PROGRAM
PROGRAM
X9027
Figure 56: Synchronous Peripheral Mode Circuit Diagram
6-64
May 14, 1999 (Version 1.6)
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
CCLK
INIT
BYTE
0
BYTE
1
BYTE 0 OUT
BYTE 1 OUT
1
0
0
1
2
3
4
5
6
7
DOUT
RDY/BUSY
X6096
Description
INIT (High) setup time
D0 - D7 setup time
D0 - D7 hold time
CCLK High time
Symbol
TIC
Min
5
Max
Units
µs
TDC
60
0
ns
6
TCD
ns
CCLK
TCCH
TCCL
FCC
50
60
ns
CCLK Low time
ns
CCLK Frequency
8
MHz
Notes: 1. Peripheral Synchronous mode can be considered Slave Parallel mode. An external CCLK provides timing, clocking in the
first data byte on the second rising edge of CCLK after INIT goes High. Subsequent data bytes are clocked in on every
eighth consecutive rising edge of CCLK.
2. The RDY/BUSY line goes High for one CCLK period after data has been clocked in, although synchronous operation does
not require such a response.
3. The pin name RDY/BUSY is a misnomer. In Synchronous Peripheral mode this is really an ACKNOWLEDGE signal.
4. Note that data starts to shift out serially on the DOUT pin 0.5 CCLK periods after it was loaded in parallel. Therefore,
additional CCLK pulses are clearly required after the last byte has been loaded.
Figure 57: Synchronous Peripheral Mode Programming Switching Characteristics
May 14, 1999 (Version 1.6)
6-65
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
The READY/BUSY handshake can be ignored if the delay
from any one Write to the end of the next Write is guaran-
teed to be longer than 10 CCLK periods.
Asynchronous Peripheral Mode
Write to FPGA
Asynchronous Peripheral mode uses the trailing edge of
the logic AND condition of WS and CS0 being Low and RS
and CS1 being High to accept byte-wide data from a micro-
processor bus. In the lead FPGA, this data is loaded into a
double-buffered UART-like parallel-to-serial converter and
is serially shifted into the internal logic.
Status Read
The logic AND condition of the CS0, CS1and RS inputs
puts the device status on the Data bus.
•
•
•
D7 High indicates Ready
D7 Low indicates Busy
D0 through D6 go unconditionally High
The lead FPGA presents the preamble data (and all data
that overflows the lead device) on its DOUT pin. The
RDY/BUSY output from the lead FPGA acts as a hand-
shake signal to the microprocessor. RDY/BUSY goes Low
when a byte has been received, and goes High again when
the byte-wide input buffer has transferred its information
into the shift register, and the buffer is ready to receive new
data. A new write may be started immediately, as soon as
the RDY/BUSY output has gone Low, acknowledging
receipt of the previous data. Write may not be terminated
until RDY/BUSY is High again for one CCLK period. Note
that RDY/BUSY is pulled High with a high-impedance
pull-up prior to INIT going High.
It is mandatory that the whole start-up sequence be started
and completed by one byte-wide input. Otherwise, the pins
used as Write Strobe or Chip Enable might become active
outputs and interfere with the final byte transfer. If this
transfer does not occur, the start-up sequence is not com-
pleted all the way to the finish (point F in Figure 47 on page
53).
In this case, at worst, the internal reset is not released. At
best, Readback and Boundary Scan are inhibited. The
length-count value, as generated by the XACTstep soft-
ware, ensures that these problems never occur.
Although RDY/BUSY is brought out as a separate signal,
microprocessors can more easily read this information on
one of the data lines. For this purpose, D7 represents the
RDY/BUSY status when RS is Low, WS is High, and the
two chip select lines are both active.
The length of the BUSY signal depends on the activity in
the UART. If the shift register was empty when the new byte
was received, the BUSY signal lasts for only two CCLK
periods. If the shift register was still full when the new byte
was received, the BUSY signal can be as long as nine
CCLK periods.
Asynchronous Peripheral mode is selected by a <101> on
the mode pins (M2, M1, M0).
Note that after the last byte has been entered, only seven of
its bits are shifted out. CCLK remains High with DOUT
equal to bit 6 (the next-to-last bit) of the last byte entered.
N/C
N/C
N/C
4.7 kΩ
M0
M1
M0
CCLK
DIN
M1
M2
M2
8
DATA
BUS
CCLK
D0–7
OPTIONAL
DAISY-CHAINED
FPGAs
DOUT
DOUT
VCC
ADDRESS
DECODE
LOGIC
CS0
XC4000E/X
ADDRESS
BUS
ASYNCHRO-
NOUS
XC4000E/X
SLAVE
PERIPHERAL
4.7 kΩ
4.7 kΩ
CS1
RS
WS
CONTROL
SIGNALS
RDY/BUSY
INIT
INIT
DONE
DONE
REPROGRAM
PROGRAM
PROGRAM
4.7 kΩ
X9028
Figure 58: Asynchronous Peripheral Mode Circuit Diagram
6-66
May 14, 1999 (Version 1.6)
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Write to LCA
Read Status
RS, CS0
WS/CS0
RS, CS1
WS, CS1
1
T
CA
3
T
4
7
CD
2
T
DC
READY
BUSY
D7
D0-D7
CCLK
4
T
WTRB
6
T
BUSY
RDY/BUSY
DOUT
Previous Byte D6
D7
D0
D1
D2
X6097
Description
Effective Write time
Symbol
TCA
Min
Max
Units
6
1
100
ns
(CS0, WS=Low; RS, CS1=High)
Write
RDY
DIN setup time
2
3
4
TDC
TCD
60
0
ns
ns
ns
DIN hold time
RDY/BUSY delay after end of
Write or Read
TWTRB
60
60
9
RDY/BUSY active after beginning
of Read
7
6
ns
RDY/BUSY Low output (Note 4)
TBUSY
2
CCLK
periods
Notes: 1. Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High.
2. The time from the end of WS to CCLK cycle for the new byte of data depends on the completion of previous byte
processing and the phase of the internal timing generator for CCLK.
3. CCLK and DOUT timing is tested in slave mode.
4. T
T
indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest
BUSY
occurs when a byte is loaded into an empty parallel-to-serial converter. The longest T
occurs when a new word
BUSY
BUSY
is loaded into the input register before the second-level buffer has started shifting out data
This timing diagram shows very relaxed requirements. Data need not be held beyond the rising edge of WS. RDY/BUSY will
go active within 60 ns after the end of WS. A new write may be asserted immediately after RDY/BUSY goes Low, but write
may not be terminated until RDY/BUSY has been High for one CCLK period.
Figure 59: Asynchronous Peripheral Mode Programming Switching Characteristics
May 14, 1999 (Version 1.6)
6-67
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Configuration Switching Characteristics
T
Vcc
PROGRAM
INIT
POR
RE-PROGRAM
>300 ns
T
PI
T
T
ICCK
CCLK
CCLK OUTPUT or INPUT
<300 ns
M0, M1, M2
(Required)
DONE RESPONSE
I/O
VALID
X1532
<300 ns
Master Modes (XC4000E/EX)
Description
Symbol
TPOR
TPOR
TPI
Min
10
Max
40
Units
ms
M0 = High
M0 = Low
Power-On Reset
Program Latency
40
130
200
ms
30
µs per
CLB column
CCLK (output) Delay
TICCK
TCCLK
TCCLK
40
640
80
250
2000
250
µs
ns
ns
CCLK (output) Period, slow
CCLK (output) Period, fast
Master Modes (XC4000XL)
Description
Symbol
TPOR
TPOR
TPI
Min
10
Max
40
Units
ms
M0 = High
M0 = Low
Power-On Reset
Program Latency
40
130
200
ms
30
µs per
CLB column
CCLK (output) Delay
TICCK
TCCLK
TCCLK
40
540
67
250
1600
200
µs
ns
ns
CCLK (output) Period, slow
CCLK (output) Period, fast
Slave and Peripheral Modes (All)
Description
Power-On Reset
Symbol
TPOR
TPI
Min
10
Max
33
Units
ms
Program Latency
30
200
µs per
CLB column
CCLK (input) Delay (required)
CCLK (input) Period (required)
TICCK
TCCLK
4
µs
100
ns
6-68
May 14, 1999 (Version 1.6)
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Product Availability
Table 24, Table 25, and Table 26 show the planned packages and speed grades for XC4000-Series devices. Call your local
sales office for the latest availability information, or see the Xilinx WEBLINX at http://www.xilinx.com for the latest revision of
the specifications.
Table 24: Component Availability Chart for XC4000XL FPGAs
PINS
84
100
100
144
144
160
160
176
176
208
208
240
240
256
299
304
352
411
432
475
559
560
TYPE
CODE
-3
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
-2
-1
XC4002XL
-09C
-3
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C
C I
C I
C I
C
C I
C I
C I
C
-2
-1
XC4005XL
XC4010XL
C I
C
-09C
-3
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
-2
-1
-09C
-3
6
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
-2
-1
XC4013XL
-09C
-08C
C
C
C
C
C
C
-3
-2
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
XC4020XL
XC4028XL
-1
-09C
-3
-2
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
-1
-09C
-3
-2
C I
C I
C I
C
C I
C I
C I
C
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
-1
C I
C
XC4036XL
-09C
-08C
C
C
C
C
C
C
C
-3
-2
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
XC4044XL
XC4052XL
-1
-09C
-3
-2
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
-1
-09C
-3
-2
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
-1
XC4062XL
-09C
-08C
C
C
C
C
C
-3
-2
-1
C I
C I
C I
C I
C I
C I
C I
C I
C I
XC4085XL
-09C
C
C
C
1/29/99
C = Commercial T = 0° to +85°C
J
I= Industrial T = -40°C to +100°C
J
May 14, 1999 (Version 1.6)
6-69
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Table 25: Component Availability Chart for XC4000E FPGAs
PINS
84
100
100
120
144
156
160
191
208
208
223
225
240
240
299
304
TYPE
CODE
-4
C I
C I
C I
C I
C I
C I
C I
C I
-3
-2
XC4003E
C I
C
C I
C
C I
C
C I
C
-1
-4
-3
-2
-1
-4
-3
-2
-1
-4
-3
-2
-1
-4
-3
-2
-1
-4
-3
-2
-1
-4
-3
-2
-1
-4
-3
-2
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C I
C
C I
C I
C
C I
C I
C
C I
C I
C
C I
C I
C
XC4025E
1/29/99
C = Commercial T = 0° to +85°C
J
I= Industrial T = -40°C to +100°C
J
Table 26: Component Availability Chart for XC4000EX FPGAs
PINS
TYPE
CODE
208
240
299
304
352
411
432
High-Perf.
QFP
High-Perf.
QFP
Ceram.
PGA
High-Perf.
QFP
Plast.
BGA
Ceram.
PGA
Plast.
BGA
HQ208
HQ240
PG299
HQ304
BG352
PG411
BG432
-4
C I
C I
C
C I
C I
C
C I
C I
C
C I
C I
C
C I
C I
C
XC4028EX -3
-2
-4
C I
C I
C
C I
C I
C
C I
C I
C
C I
C I
C
C I
C I
C
-3
XC4036EX
-2
1/29/99
C = Commercial T = 0° to +85°C
J
I= Industrial T = -40°C to +100°C
J
6-70
May 14, 1999 (Version 1.6)
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
User I/O Per Package
Table 27, Table 28, and Table 29 show the number of user I/Os available in each package for XC4000-Series devices. Call
your local sales office for the latest availability information, or see the Xilinx WEBLINX at http://www.xilinx.com for the latest
revision of the specifications.
Table 27: User I/O Chart for XC4000XL FPGAs
Maximum User Accessible I/O by Package Type
Max
Device
I/O
64
61
61
61
64
77
77
64
77
XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
112
160
192
224
256
288
320
352
384
448
112
129
129
129
112
113
112
160
160
160
145
160
192
205
205
113
113
145
145
192
192
129
129
129
160
160
160
193
193
193
193
193
256
256
256
256
256
256
256
288
289
288
320
352
288
320
352
352
352
352
384
448
384
6
448
XC4085XL
1/29/99
Table 28: User I/O Chart for XC4000E FPGAs
Maximum User Accessible I/O by Package Type
Max
Device
I/O
80
61
61
61
61
61
77
77
77
80
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
112
128
144
160
192
224
256
112
113
112
125
112
128
129
129
129
112
128
144
160
160
144
160
160
160
160
160
192
192
192
192
192
192
193
193
256
256
XC4025E
1/29/99
Table 29: User I/O Chart for XC4000EX FPGAs
Maximum User Accessible I/O by Package Type
Max
I/O
256
Device
HQ208
HQ240
193
PG299
HQ304
256
BG352
256
PG411
BG432
160
256
XC4028EX
193
256
288
288
288
288
XC4036EX
1/29/99
May 14, 1999 (Version 1.6)
6-71
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000 Series Electrical Characteristics and Device-Specific Pinout Table
For the latest Electrical Characteristics and package/pinout information for each XC4000 Family, see the Xilinx web site at
http://www.xilinx.com/partinfo/databook.htm#xc4000
Ordering Information
Example:
XC4013E-3HQ240C
Device Type
Temperature Range
C = Commercial (T = 0 to +85°C)
Speed Grade
J
I = Industrial (T = -40 to +100°C)
-6
-5
-4
-3
-2
-1
J
M = Military (T = -55 to+125°C)
C
Number of Pins
Package Type
PC = Plastic Lead Chip Carrier
BG = Ball Grid Array
PQ = Plastic Quad Flat Pack
VQ = Very Thin Quad Flat Pack
TQ = Thin Quad Flat Pack
PG = Ceramic Pin Grid Array
HQ = High Heat Dissipation Quad Flat Pack
MQ = Metal Quad Flat Pack
CB = Top Brazed Ceramic Quad Flat Pack
X9020
Revision Control
Version
Description
3/30/98 (1.5) Updated XC4000XL timing and added XC4002XL
1/29/99 (1.5) Updated pin diagrams
5/14/99 (1.6) Replaced Electrical Specification and pinout pages for E, EX, and XL families with separate updates and
added URL link for electrical specifications/pinouts for WebLINX users
6-72
May 14, 1999 (Version 1.6)
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000XL Electrical Specifications
Definition of Terms
In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as
follows:
Advance:
Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or
devicefamilies. Values are subject to change. Use as estimates, not for production.
Preliminary:
Unmarked:
Based on preliminary characterization. Further changes are not expected.
Specifications not identified as either Advance or Preliminary are to be considered Final.
Except for pin-to-pin input and output parameters, the a.c. parameter delay specifications included in this document are
derived from measuring internal test patterns. All specifications are representative of worst-case supply voltage and junction
temperature conditions.
All specifications subject to change without notice.
XC4000XL D.C. Characteristics
Absolute Maximum Ratings
Description
Supply voltage relative to Ground
Units
V
VCC
VIN
-0.5 to 4.0
-0.5 to 5.5
-0.5 to 5.5
50
Input voltage relative to Ground (Note 1)
V
6
VTS
Voltage applied to 3-state output (Note 1)
Longest Supply Voltage Rise Time from 1 V to 3V
Storage temperature (ambient)
V
VCCt
TSTG
TSOL
ms
°C
°C
°C
°C
-65 to +150
+260
Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm)
Ceramic packages
Plastic packages
+150
TJ
Junction Temperature
+125
Note 1: Maximum DC excursion above V or below Ground must be limited to either 0.5 V or 10 mA, whichever is easier to
cc
achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot toV +2.0 V, provided this over or
CC
undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA.
Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended
periods of time may affect device reliability.
Recommended Operating Conditions
Symbol
Description
Min
Max
3.6
Units
V
Supply voltage relative to Gnd, TJ = 0 °C to +85°C
Commercial
3.0
VCC
Supply voltage relative to Gnd, TJ = -40°C to +100°C Industrial
High-level input voltage
3.0
50% of VCC
0
3.6
V
VIH
VIL
5.5
V
Low-level input voltage
30% of VCC
250
V
TIN
Input signal transition time
ns
Notes:
At junction temperatures above those listed above, all delay parameters increase by 0.35% per °C.
Input and output measurement threshold is ~50% of V
.
CC
DS005 (v. 1.8 October 18, 1999 - Product Specification
6-73
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
D.C. Characteristics Over Recommended Operating Conditions
Symbol
Description
Min
2.4
Max
Units
V
High-level output voltage @ IOH = -4.0 mA, VCC min (LVTTL)
High-level output voltage @ IOH = -500 µA, (LVCMOS)
Low-level output voltage @ IOL = 12.0 mA, VCC min (LVTTL) (Note 1)
Low-level output voltage @ IOL = 1500 µA, (LVCMOS)
Data Retention Supply Voltage (below which configuration data may be lost)
Quiescent FPGA supply current (Note 2)
VOH
90% VCC
V
0.4
V
VOL
10% VCC
V
VDR
ICCO
IL
2.5
-10
V
5
mA
µA
pF
Input or output leakage current
+10
10
Input capacitance (sample tested)
BGA, SBGA, PQ, HQ, MQ
packages
CIN
PGA packages
16
pF
mA
mA
mA
IRPU
IRPD
IRLL
Pad pull-up (when selected) @ Vin = 0 V (sample tested)
Pad pull-down (when selected) @ Vin = 3.6 V (sample tested)
Horizontal Longline pull-up (when selected) @ logic Low
With up to 64 pins simultaneously sinking 12 mA.
0.02
0.02
0.3
0.25
0.15
2.0
Note 1:
Note 2:
With no output current loads, no active input or Longline pull-up resistors, all I/O pins Tri-stated and floating.
Power-0n Power Supply Requirements
Xilinx FPGAs require a minimum rated power supply current capacity to insure proper initialization, and the power supply
ramp-up time does affect the current required. A fast ramp-up time requires more current than a slow ramp-up time. The
slowest ramp-up time is 50 ms. Current capacity is not specified for a ramp-up time faster than 2ms. The current capacity
varies linealy with ramp-up time, e.g., an XC4036XL with a ramp-up time of 25 ms would require a capacity predicted by the
point on the straight line drawn from 1A at 120 µs to 500 mA at 50 ms at the 25 ms time mark. This point is approximately
750 mA .
Ramp-up Time
Product
Description
Fast (120 µs)
Slow (50 ms)
500 mA
XC4005 - 36XL
XC4044- 62XL
XC4085XL1
Minimum required current supply
Minimum required current supply
Minimum required current supply
1 A
2 A
2 A1
500 mA
500 mA
Notes: 1. The XC4085XL fast ramp-up time is 5 ms.
Devices are guaranteed to initialize properly with the minimum current listed above. A larger capacity power supply may
result in a larger initialization current.
This specification applies to Commercial and Industrial grade products only.
Ramp-up Time is measured from 0 V to 3.6 V . Peak current required lasts less than 3 ms, and occurs near the
DC
DC
internal power on reset threshold voltage. After initialization and before configuration, I max is less than 10 mA.
CC
6-74
DS005 (v. 1.8 October 18, 1999 - Product Specification
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000XL A.C. Characteristics
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven
from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data, reflecting
the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System)
and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static
timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction
temperature. Values apply to all XC4000XL devices and are expressed in nanoseconds unless otherwise noted.
Global Low Skew Buffer to Clock K
Speed Grade
Device
All
-3
-2
-1
-09
-08
Units
Description
Symbol
Min
Max
Max
Max
Max
Max
Delay from pad through GLS buffer to
any clock input, K
TGLS
XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
0.3
0.4
0.5
0.6
0.7
0.9
1.1
1.2
1.3
1.4
1.6
2.1
2.7
3.2
3.6
4.0
4.4
4.8
5.3
5.7
6.3
7.2
1.8
2.3
2.8
3.1
3.5
3.8
4.2
4.6
5.0
5.4
6.2
1.6
2.0
2.4
2.7
3.0
3.3
3.6
4.0
4.5
4.7
5.7
1.5
1.9
2.3
2.6
2.9
3.2
3.5
3.9
4.4
4.6
5.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.3
3.1
4.0
6
DS005 (v. 1.8 October 18, 1999 - Product Specification
6-75
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Global Early BUFGEs 1, 2, 5, and 6 to IOB Clock
Speed Grade
Device
All
-3
-2
-1
-09
-08
Units
Description
Symbol
Min
Max
Max
Max
Max
Max
Delay from pad through GE buffer to any
IOB clock input.
TGE
XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
0.1
0.3
0.3
0.4
0.4
0.3
0.3
0.2
0.3
0.3
0.4
1.6
1.9
2.2
2.4
2.6
2.8
3.1
3.5
4.0
4.9
5.8
1.4
1.8
1.9
2.1
2.2
2.4
2.7
3.0
3.5
4.3
5.1
1.3
1.7
1.7
1.8
2.1
2.1
2.3
2.6
3.0
3.7
4.7
1.2
1.6
1.7
1.7
2.0
2.0
2.2
2.4
3.0
3.4
4.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.5
1.9
3.0
Global Early BUFGEs 3, 4, 7, and 8 to IOB Clock
Speed Grade
All
-3
-2
-1
-09
-08
Units
Description
Symbol
Device
Min
Max
Max
Max
Max
Max
Delay from pad through GE buffer to any
IOB clock input.
TGE
XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
0.5
0.7
0.7
0.7
0.8
0.9
0.9
1.0
1.1
1.2
1.3
2.8
3.1
3.5
3.8
4.1
4.4
4.7
5.1
5.5
5.9
6.8
2.5
2.8
3.1
3.3
3.6
3.9
4.2
4.5
4.8
5.2
6.0
2.1
2.7
2.8
2.9
3.4
3.4
3.7
4.0
4.3
4.8
5.5
1.7
2.5
2.7
2.8
3.2
3.3
3.6
3.7
4.3
4.5
5.2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.4
3.1
4.0
6-76
DS005 (v. 1.8 October 18, 1999 - Product Specification
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000XL CLB Characteristics
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
XC4000XL devices and are expressed in nanoseconds unless otherwise noted.
CLB Switching Characteristic Guidelines
Speed Grade
Symbol
-3
-2
-1
-09
-08
Description
Combinatorial Delays
Min Max Min Max Min Max Min Max Min Max
F/G inputs to X/Y outputs
F/G inputs via H’ to X/Y outputs
T
T
T
T
T
T
T
1.6
2.7
2.9
2.5
2.4
2.5
1.5
1.5
2.4
2.6
2.2
2.1
2.2
1.3
1.3
2.2
2.2
2.0
1.9
2.0
1.1
1.2
2.0
2.0
1.8
1.6
1.8
1.0
1.1
1.9
1.8
1.8
1.5
1.8
0.9
ILO
IHO
F/G inputs via transparent latch to Q outputs
C inputs via SR/H0 via H to X/Y outputs
C inputs via H1 via H to X/Y outputs
C inputs via DIN/H2 via H to X/Y outputs
C inputs via EC, DIN/H2 to YQ, XQ output (bypass)
ITO
HH0O
HH1O
HH2O
CBYP
CLB Fast Carry Logic
Operand inputs (F1, F2, G1, G4) to C
T
T
T
T
T
T
2.7
3.3
2.0
2.8
0.26
0.32
2.3
2.9
1.8
2.6
0.23
0.28
2.0
2.5
1.5
2.4
0.20
0.25
1.6
1.8
1.0
1.7
0.14
0.24
1.6
1.8
0.9
1.5
0.14
0.24
OUT
OPCY
ASCY
INCY
SUM
BYP
Add/Subtract input (F3) to C
OUT
Initialization inputs (F1, F3) to C
OUT
C
C
through function generators to X/Y outputs
IN
to C
, bypass function generators
IN
OUT
Carry Net Delay, C
to C
6
OUT
IN
NET
Sequential Delays
Clock K to Flip-Flop outputs Q
Clock K to Latch outputs Q
T
T
2.1
2.1
1.9
1.9
1.6
1.6
1.5
1.5
1.4
1.4
CKO
CKLO
Setup Time before Clock K
F/G inputs
F/G inputs via H
C inputs via H0 through H
C inputs via H1 through H
C inputs via H2 through H
C inputs via DIN
C inputs via EC
C inputs via S/R, going Low (inactive)
CIN input via F/G
T
T
T
T
T
T
T
T
T
T
1.1
2.2
2.0
1.9
2.0
0.9
1.0
0.6
2.3
3.4
1.0
1.9
1.7
1.6
1.7
0.8
0.9
0.5
2.1
3.0
0.9
1.7
1.6
1.4
1.6
0.7
0.8
0.5
1.9
2.7
0.8
1.6
1.4
1.2
1.4
0.6
0.7
0.4
1.3
2.1
0.8
1.5
1.4
1.1
1.4
0.6
0.7
0.4
1.2
2.0
ICK
IHCK
HH0CK
HH1CK
HH2CK
DICK
ECCK
RCK
CCK
CIN input via F/G and H
CHCK
Hold Time after Clock K
F/G inputs
F/G inputs via H
C inputs via SR/H0 through H
C inputs via H1 through H
C inputs via DIN/H2 through H
C inputs via DIN/H2
T
T
T
T
T
T
T
T
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CKI
CKIH
CKHH0
CKHH1
CKHH2
CKDI
C inputs via EC
C inputs via SR, going Low (inactive)
CKEC
CKR
Clock
Clock High time
Clock Low time
T
T
3.0
3.0
2.8
2.8
2.5
2.5
2.3
2.3
2.1
2.1
CH
CL
Set/Reset Direct
Width (High)
Delay from C inputs via S/R, going High to Q
T
T
3.0
2.8
2.5
2.3
2.3
RPW
RIO
3.7
3.2
2.8
2.7
2.6
14.0
238
Global Set/Reset
T
T
F
19.8
17.3
15.0
14.0
Minimum GSR Pulse Width
Delay from GSR input to any Q
Toggle Frequency (MHz) (for export control)
MRW
MRQ
See Table on page 85 for T
values per device.
RRI
(MHz)
166
179
200
217
TOG
DS005 (v. 1.8 October 18, 1999 - Product Specification
6-77
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
CLB Single-Port RAM Synchronous (Edge-Triggered) Write Operation Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
XC4000XL devices and are expressed in nanoseconds unless otherwise noted.
Speed Grade
-3
-2
-1
-09
-08
Single Port RAM
Size Symbol Min Max Min Max Min Max Min Max Min Max
Write Operation
Address write cycle time (clock K period) 16x2 TWCS
32x1 TWCTS
9.0
9.0
8.4
8.4
7.7
7.7
7.4
7.4
7.4
7.4
Clock K pulse width (active edge)
Address setup time before clock K
Address hold time after clock K
DIN setup time before clock K
DIN hold time after clock K
WE setup time before clock K
WE hold time after clock K
16x2 TWPS
32x1 TWPTS
4.5
4.5
4.2
4.2
3.9
3.9
3.7
3.7
3.7
3.7
16x2 TASS
32x1 TASTS
2.2
2.2
2.0
2.0
1.7
1.7
1.7
1.7
1.6
1.7
16x2 TAHS
32x1 TAHTS
0
0
0
0
0
0
0
0
0
0
16x2 TDSS
32x1 TDSTS
2.0
2.5
1.9
2.3
1.7
2.1
1.7
2.1
1.7
2.1
16x2 TDHS
32x1 TDHTS
0
0
0
0
0
0
0
0
0
0
16x2 TWSS
32x1 TWSTS
2.0
1.8
1.8
1.7
1.6
1.5
1.6
1.5
1.6
1.5
16x2 TWHS
32x1 TWHTS
0
0
0
0
0
0
0
0
0
0
Data valid after clock K
16x2 TWOS
32x1 TWOTS
6.8
8.1
6.3
7.5
5.8
6.9
5.8
6.7
5.7
6.7
Read Operation
Address read cycle time
16x2 TRC
32x1 TRCT
4.5
6.5
3.1
5.5
2.6
3.8
2.6
3.8
2.6
3.8
Data Valid after address change (no
Write Enable)
16x2 TILO
32x1 TIHO
1.6
2.7
1.5
2.4
1.3
2.2
1.2
2.0
1.1
1.9
Address setup time before clock K
16x2 TICK
32x1 TIHCK
1.1
2.2
1.0
1.9
0.9
1.7
0.8
1.6
0.8
1.5
6-78
DS005 (v. 1.8 October 18, 1999 - Product Specification
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Operation Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
XC4000XL devices and are expressed in nanoseconds unless otherwise noted.
Speed Grade
-3
-2
--1
-09
-08
Dual Port RAM
Size Symbol Min Max Min Max Min Max Min Max Min Max
Address write cycle time (clock K period) 16x1 TWCDS
9.0
4.5
2.5
0
2.5
0
8.4
4.2
2.0
0
2.3
0
7.7
3.9
1.7
0
2.0
0
7.4
3.7
1.7
0
2.0
0
7.4
3.7
1.6
0
2.0
0
Clock K pulse width (active edge)
Address setup time before clock K
Address hold time after clock K
DIN setup time before clock K
DIN hold time after clock K
WE setup time before clock K
WE hold time after clock K
16x1 TWPDS
16x1 TASDS
16x1 TAHDS
16x1 TDSDS
16x1 TDHDS
16x1 TWSDS
16x1 TWHDS
16x1 TWODS
1.8
0
1.7
0
1.6
0
1.6
0
1.6
0
Data valid after clock K
7.8
7.3
6.7
6.7
6.6
CLB RAM Synchronous (Edge-Triggered) Write Timing Waveforms
6
TWPS
TWPDS
WCLK (K)
WE
WCLK (K)
WE
TWHS
TDHS
TAHS
TWSS
TWHDS
TWSDS
TDSS
TDHDS
TDSDS
DATA IN
DATA IN
TASS
TASDS
TAHDS
ADDRESS
ADDRESS
TILO
TILO
TILO
TILO
TWOS
TWODS
DATA OUT
OLD
NEW
DATA OUT
OLD
NEW
X6461
X6474
Single-Port RAM
Dual-Port RAM
DS005 (v. 1.8 October 18, 1999 - Product Specification
6-79
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000XL Pin-to-Pin Output Parameter Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted.
Output Flip-Flop, Clock to Out
Speed Grade
Device
All
-3
-2
-1
-09
-08
Units
Description
Symbol
Min
Max
Max
Max
Max
Max
Global Low Skew Clock to Output us- TICKOF
ing Output Flip Flop
XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
1.2
1.3
1.4
1.5
1.6
1.8
2.0
2.1
2.2
2.3
2.5
7.1
7.7
8.2
8.6
9.0
9.4
9.8
10.3
10.7
11.3
12.2
6.1
6.6
7.1
7.4
7.8
8.1
8.5
8.9
9.3
9.7
10.5
5.4
5.8
6.2
6.5
6.8
7.1
7.4
7.8
8.3
8.5
9.5
5.1
5.4
5.8
6.1
6.4
6.7
7.0
7.4
7.9
8.1
9.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5.6
6.4
7.3
1.6
For output SLOW option add
TSLOW All Devices
0.5
3.0
2.5
2.0
1.7
ns
Notes: Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is
measured using the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all
accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined
by the static timing analyzer (TRCE) can be added to the AC parameter Tokpof and used as a worst-case pin-to-pin
clock-to-out delay for clocked outputs for FAST mode configurations.
Output timing is measured at ~50% V threshold with 50 pF external capacitive load. For different loads, see Figure 1.
CC
Capacitive Load Factor
3
2
Figure 60 shows the relationship between I/O output delay
and load capacitance. It allows a user to adjust the speci-
fied output delay if the load capacitance is different than
50 pF. For example, if the actual load capacitance is
120 pF, add 2.5 ns to the specified delay. If the load capac-
itance is 20 pF, subtract 0.8 ns from the specified output
delay.
1
0
-1
-2
Figure 60 is usable over the specified operating conditions
of voltage and temperature and is independent of the out-
put slew rate control.
0
20 40 60 80 100 120 140
Capacitance (pF)
X8257
Figure 60: Delay Factor at Various Capacitive Loads
6-80
DS005 (v. 1.8 October 18, 1999 - Product Specification
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Output Flip-Flop, Clock to Out, BUFGE #s 1, 2, 5, and 6
Speed Grade
Device
All
-3
-2
-1
-09
-08
Units
Description
Symbol
Min
Max
Max
Max
Max
Max
Global Early Clock to Output using
Output Flip Flop. Values are for BUF-
GE #s 1, 2, 5, and 6.
TICKEOF XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
1.0
1.2
1.2
1.3
1.3
1.2
1.2
1.1
1.2
1.2
1.3
6.6
6.9
7.2
7.4
7.6
7.8
8.1
8.5
9.0
9.9
10.8
5.7
6.1
6.2
6.4
6.5
6.7
7.0
7.3
7.8
8.6
9.4
5.1
5.5
5.5
5.6
5.9
5.9
6.1
6.4
6.8
7.5
8.5
4.8
5.2
5.3
5.3
5.6
5.6
5.8
6.0
6.6
7.0
7.9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.8
5.2
6.3
Notes: Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is
measured using the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all
accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined
by the static timing analyzer (TRCE) can be added to the AC parameter Tokpof and used as a worst-case pin-to-pin
clock-to-out delay for clocked outputs for FAST mode configurations.
Output timing is measured at ~50% V threshold with 50 pF external capacitive load. For different loads, see Figure 1.
CC
Output Flip-Flop, Clock to Out, BUFGE #s 3, 4, 7, and 8
Speed Grade
Device
All
-3
-2
-1
-09
-08
6
Units
Description
Symbol
Min
Max
Max
Max
Max
Max
Global Early Clock to Output using
Output Flip Flop. Values are for BUF-
GE #s 3, 4, 7, and 8.
TICKEOF XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
1.3
1.5
1.6
1.6
1.7
1.7
1.8
1.9
2.0
2.0
2.2
7.8
8.1
8.5
8.8
9.1
9.4
9.7
10.1
10.5
10.9
11.8
6.8
7.1
7.4
7.6
7.9
8.2
8.5
8.8
9.1
9.5
10.3
5.9
6.5
6.6
6.7
7.2
7.2
7.5
7.8
8.1
8.6
9.3
5.3
6.1
6.3
6.4
6.8
6.9
7.2
7.3
7.9
8.1
8.8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5.7
6.4
7.3
Notes: Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is
measured using the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all
accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined
by the static timing analyzer (TRCE) can be added to the AC parameter Tokpof and used as a worst-case pin-to-pin
clock-to-out delay for clocked outputs for FAST mode configurations.
Output timing is measured at ~50% V threshold with 50 pF external capacitive load. For different loads, see Figure 1.
CC
DS005 (v. 1.8 October 18, 1999 - Product Specification
6-81
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000XL Pin-to-Pin Input Parameter Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted
Global Low Skew Clock, Set-Up and Hold
Speed Grade
Device
-3
-2
-1
-09
-08
Units
Description
Input Setup and Hold Times
No Delay
Global Low Skew Clock and IFF
Global Low Skew Clock and FCL
Symbol
Min
Min
Min
Min
Min
TPSN/TPHN XC4002XL
XC4005XL
2.5 / 1.5 2.2 / 1.3 1.9 / 1.2 1.7 / 1.0
1.2 / 2.6 1.1 / 2.2 0.9 / 2.0 0.8 / 1.7
1.2 / 3.0 1.1 / 2.6 0.9 / 2.3 0.8 / 2.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
1.2 / 3.2 1.1 / 2.8 0.9 / 2.4 0.8 / 2.1 0.8 / 2.1
1.2 / 3.7 1.1 / 3.2 0.9 / 2.8 0.8 / 2.4
1.2 / 4.4 1.1 / 3.8 0.9 / 3.3 0.8 / 2.9
1.2 / 5.5 1.1 / 4.8 0.9 / 4.1 0.8 / 3.6 0.8 / 3.6
1.2 / 5.8 1.1 / 5.0 0.9 / 4.4 0.8 / 3.8
1.2 / 7.1 1.1 / 6.2 0.9 / 5.4 0.8 / 4.7
1.2 / 7.0 1.1 / 6.1 0.9 / 5.3 0.8 / 4.6 0.8 / 4.6
1.2 / 9.4 1.1 / 8.2 0.9 / 7.1 0.8 / 6.2
8.4 / 0.0 7.3 / 0.0 6.3 / 0.0 5.5 / 0.0
XC4085XL
Partial Delay
Global Low Skew Clock and IFF
Global Low Skew Clock and FCL
TPSP/TPHP XC4002XL
XC4005XL 10. 5 / 0.0 9.1 / 0.0 7.9 / 0.0 6.9 / 0.0
XC4010XL 11.1 / 0.0 9.7 / 0.0 8.4 / 0.0 7.3 / 0.0
XC4013XL*
XC4020XL 11.9 / 1.0 10.3 / 1.0 9.0 / 1.0 7.8 / 1.0
XC4028XL 12.3 / 1.0 10.7 / 1.0 9.3 / 1.0 8.1 / 1.0
XC4036XL*
XC4044XL 13.1 / 1.0 11.4 / 1.0 9.9 / 1.0 8.6 / 1.0
XC4052XL 11.9 / 1.0 10.3 / 1.0 9.0 / 1.0 7.8 / 1.0
XC4062XL*
6.1 / 1.0 5.3 / 1.0 4.6 / 1.0 4.0 / 1.0 3.7 / 0.5
6.4 / 1.0 5.6 / 1.0 4.8 / 1.0 4.2 / 1.0 4.0/ 0.8
6.7 / 1.2 5.8 / 1.2 5.1 / 1.2 4.4 / 1.2 4.2/ 1.0
XC4085XL 12.9 / 1.2 11.2 / 1.2 9.8 / 1.2 8.5 / 1.2
Full Delay
Global Low Skew Clock and IFF
T
PSD/TPHD XC4002XL
6.8 / 0.0 6.0 / 0.0 5.2 / 0.0 4.5 / 0.0
8.8 / 0.0 7.6 / 0.0 6.6 / 0.0 5.6 / 0.0
9.0 / 0.0 7.8 / 0.0 6.8 / 0.0 5.8 / 0.0
6.4 / 0.0 6.0 / 0.0 5.6 / 0.0 4.8 / 0.0 4.8 / 0.0
8.8 / 0.0 7.6 / 0.0 6.6 / 0.0 6.2 / 0.0
9.3 / 0.0 8.1 / 0.0 7.0 / 0.0 6.4 / 0.0
6.6 / 0.0 6.2 / 0.0 5.8 / 0.0 5.3 / 0.0 5.3 / 0.0
XC4005XL
XC4010XL
XC4013XL*
XC4020XL
XC4028XL
XC4036XL*
XC4044XL 10.6 / 0.0 9.2 / 0.0 8.0 / 0.0 6.8 / 0.0
XC4052XL 11.2 / 0.0 9.7 / 0.0 8.4 / 0.0 7.0 / 0.0
XC4062XL*
6.8 / 0.0 6.4 / 0.0 6.0 / 0.0 5.5 / 0.0 5.5 / 0.0
XC4085XL 12.7 / 0.0 11.0 / 0.0 9.6 / 0.0 8.4 / 0.0
IFF = Input Flip-Flop or Latch
* The XC4013XL, XC4036XL, and 4062XL have significantly faster partial and full delay setup times than other devices.
Notes: Input setup time is measured with the fastest route and the lightest load.
Input hold time is measured using the furthest distance and a reference load of one clock pin per IOB as well as driving all
accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined
by the static timing analyzer (TRCE) can be used as a worst-case pin-to-pin no-delay input hold specification.
6-82
DS005 (v. 1.8 October 18, 1999 - Product Specification
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Global Early Clock BUFGEs 1, 2, 5, and 6 Set-up and Hold for IFF and FCL
Speed Grade
Device
-3
-2
-1
-09
-08
Units
Description
Input Setup and Hold
Times
Symbol
Min
Min
Min
Min
Min
No Delay
XC4002XL 2.8 / 1.5 2.5 / 1.3 2.2 / 1.2 1.9 / 1.0
XC4005XL 1.2 / 4.1 1.1 / 3.6 0.9 / 3.1 0.8 / 2.7
TPFSEN/TPFHEN XC4010XL 1.2 / 4.4 1.1 / 3.8 0.9 / 3.3 0.8 / 2.9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Global Early Clock and IFF TPSEN/TPHEN
Global Early Clock and
FCL
XC4013XL 1.2 / 4.7 1.1 / 4.1 0.9 / 3.6 0.8 / 3.1 0.5 / 2.7
XC4020XL 1.2 / 4.6 1.1 / 4.0 0.9 / 3.5 0.8 / 3.0
XC4028XL 1.2 / 5.3 1.1 / 4.6 0.9 / 4.0 0.8 / 3.5
XC4036XL 1.2 / 6.7 1.1 / 5.8 0.9 / 5.1 0.8 / 4.4 0.5 / 3.7
XC4044XL 1.2 / 6.5 1.1 / 5.7 0.9 / 4.9 0.8 / 4.3
XC4052XL 1.2 / 6.7 1.1 / 5.8 0.9 / 5.1 0.8 / 4.4
XC4062XL 1.2 / 8.4 1.1 / 7.3 0.9 / 6.3 0.8 / 5.5 0.5 / 4.7
XC4085XL 1.2 / 8.7 1.1 / 7.5 0.9 / 6.6 0.8 / 5.7
XC4002XL 8.1 / 0.9 7.0 / 0.8 6.1 / 0.7 5.3 / 0.6
XC4005XL 9.0 / 0.0 8.5 / 0.0 8.0 / 0.0 7.5 / 0.0
Partial Delay
Global Early Clock and IFF TPSEP/TPHEP
Global Early Clock and
FCL
TPFSEP/TPFHEP XC4010XL 11.9 / 0.0 10.4 / 0.0 9.0 / 0.0 8.0 / 0.0
XC4013XL* 6.4 / 0.0 5.9 / 0.0 5.4 / 0.0 4.9 / 0.0 4.4 / 0.0
XC4020XL 10.8 / 0.0 10.3 / 0.0 9.8 / 0.0 9.0 / 0.0
XC4028XL 14.0 / 0.0 12.2 / 0.0 10.6 / 0.0 9.8 / 0.0
XC4036XL* 7.0 / 0.0 6.6 / 0.0 6.2 / 0.0 5.2 / 0.0 4.7 / 0.0
XC4044XL 14.6 / 0.0 12.7 / 0.0 11.0 / 0.0 10.8 / 0.0
XC4052XL 16.4 / 0.0 14.3 / 0.0 12.4 / 0.0 11.4 / 0.0
XC4062XL* 9.0 / 0.8 8.6 / 0.8 8.2 / 0.8 7.0 / 0.8 6.3 / 0.5
XC4085XL 16.7 / 0.0 14.5 / 0.0 12.6 / 0.0 11.6 / 0.0
XC4002XL 6.7 / 0.0 5.8 / 0.0 5.1 / 0.0 4.4 / 0.0
6
Full Delay
Global Early Clock and IFF TPSED/TPHED
XC4005XL 10.8 / 0.0 9.4 / 0.0 8.2 / 0.0 7.1 / 0.0
XC4010XL 10.3 / 0.0 9.0 / 0.0 7.8 / 0.0 6.8 / 0.0
XC4013XL* 10.0 / 0.0 8.7 / 0.0 7.6 / 0.0 6.6 / 0.0 6.0 / 0.0
XC4020XL 12.0 / 0.0 10.4 / 0.0 9.1 / 0.0 7.9 / 0.0
XC4028XL 12.6 / 0.0 11.0 / 0.0 9.5 / 0.0 8.3 / 0.0
XC4036XL* 12.2 / 0.0 10.6 / 0.0 9.2 / 0.0 8.0 / 0.0 7.2 / 0.0
XC4044XL 13.8 / 0.0 12.0 / 0.0 10.5 / 0.0 9.1 / 0.0
XC4052XL 14.1 / 0.0 12.3 / 0.0 10.7 / 0.0 9.3 / 0.0
XC4062XL* 13.1 / 0.0 11.4 / 0.0 9.9 / 0.0 8.6 / 0.0 7.8 / 0.0
XC4085XL 17.9 / 0.0 15.6 / 0.0 13.6 / 0.0 11.8 / 0.0
IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch
* The XC4013XL, XC4036XL, and 4062XL have significantly faster partial and full delay setup times than other devices.
Notes: Input setup time is measured with the fastest route and the lightest load.
Input hold time is measured using the furthest distance and a reference load of one clock pin per IOB as well as driving all
accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined
by the static timing analyzer (TRCE) can be used as a worst-case pin-to-pin no-delay input hold specification.
DS005 (v. 1.8 October 18, 1999 - Product Specification
6-83
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Global Early Clock BUFGEs 3, 4, 7, and 8 Set-up and Hold for IFF and FCL
Speed Grade
Device
-3
-2
-1
-09
-08
Units
Description
Input Setup & Hold Times
No Delay
Global Early Clock and
IFF
Symbol
Min
Min
Min
Min
Min
XC4002XL 3.0 / 2.0 2.6 / 1.7 2.3 / 1.5 2.0 / 1.3
XC4005XL 1.2 / 4.1 1.1 / 3.6 0.9 / 3.1 0.8 / 2.7
TPFSEN/TPFHEN XC4010XL 1.2 / 4.4 1.1 / 3.8 0.9 / 3.3 0.8 / 2.9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TPSEN/TPHEN
Global Early Clock and
FCL
XC4013XL 1.2 / 4.7 1.1 / 4.1 0.9 / 3.6 0.8 / 3.1 0.5 / 2.7
XC4020XL 1.2 / 4.6 1.1 / 4.0 0.9 / 3.5 0.8 / 3.0
XC4028XL 1.2 / 5.3 1.1 / 4.6 0.9 / 4.0 0.8 / 3.5
XC4036XL 1.2 / 6.7 1.1 / 5.8 0.9 / 5.1 0.8 / 4.4 0.5 / 3.7
XC4044XL 1.2 / 6.5 1.1 / 5.7 0.9 / 4.9 0.8 / 4.3
XC4052XL 1.2 / 6.7 1.1 / 5.8 0.9 / 5.1 0.8 / 4.4
XC4062XL 1.2 / 8.4 1.1 / 7.3 0.9 / 6.3 0.8 / 5.5 0.5 / 4.7
XC4085XL 1.2 / 8.7 1.1 / 7.5 0.9 / 6.6 0.8 / 5.7
XC4002XL 7.3 / 1.5 6.4 / 1.3 5.5 / 1.2 4.8 / 1.0
XC4005XL 8.4 / 0.0 7.9 / 0.0 7.4 / 0.0 7.2 / 0.0
Partial Delay
Global Early Clock and
IFF
Global Early Clock and
FCL
TPSEP/TPHEP
TPFSEP/TPFHEP XC4010XL 10.3 / 0.0 9.0 / 0.0 7.8 / 0.0 7.4 / 0.0
XC4013XL* 5.4 / 0.0 4.9 / 0.0 4.4 / 0.0 4.3 / 0.0 4.0 / 0.0
XC4020XL 9.8 / 0.0 9.3 / 0.0 8.8 / 0.0 8.5 / 0.0
XC4028XL 12.7 / 0.0 11.0 / 0.0 9.6 / 0.0 9.3 / 0.0
XC4036XL* 6.4 / 0.8 5.9 / 0.8 5.4 / 0.8 5.0 / 0.8 4.6 / 0.2
XC4044XL 13.8 / 0.0 12.0 / 0.0 10.4 / 0.0 10.2 / 0.0
XC4052XL 14.5 / 0.0 12.7 / 0.0 11.0 / 0.0 10.7 / 0.0
XC4062XL* 8.4 / 1.5 7.9 / 1.5 7.4 / 1.5 6.8 / 1.5 6.2 / 0.0
XC4085XL 14.5 / 0.0 12.7 / 0.0 11.0 / 0.0 10.8 / 0.0
XC4002XL 5.9 / 0.0 5.2 / 0.0 4.5 / 0.0 3.9 / 0.0
Full Delay
Global Early Clock and
IFF
T
PSED/TPHED
XC4005XL 10.8 / 0.0 9.4 / 0.0 8.2 / 0.0 7.1 / 0.0
XC4010XL 10.3 / 0.0 9.0 / 0.0 7.8 / 0.0 6.8 / 0.0
XC4013XL* 10.0 / 0.0 8.7 / 0.0 7.6 / 0.0 6.6 / 0.0 6.0 / 0.0
XC4020XL 12.0 / 0.0 10.4 / 0.0 9.1 / 0.0 7.9 / 0.0
XC4028XL 12.6 / 0.0 11.0 / 0.0 9.5 / 0.0 8.3 / 0.0
XC4036XL* 12.2 / 0.0 10.6 / 0.0 9.2 / 0.0 8.0 / 0.0 7.2 / 0.0
XC4044XL 13.8 / 0.0 12.0 / 0.0 10.5 / 0.0 9.1 / 0.0
XC4052XL 14.1 / 0.0 12.3 / 0.0 10.7 / 0.0 9.3 / 0.0
XC4062XL* 13.1 / 0.0 11.4 / 0.0 9.9 / 0.0 8.6 / 0.0 7.8 / 0.0
XC4085XL 17.9 / 0.0 15.6 / 0.0 13.6 / 0.0 11.8 / 0.0
* The XC4013XL, XC4036XL, and 4062XL have significantly faster partial and full delay setup times than other devices.
IFF = Input Flip Flop or Latch. FCL = Fast Capture Latch
Notes: Input setup time is measured with the fastest route and the lightest load.
Input hold time is measured using the furthest distance and a reference load of one clock pin per IOB as well as driving all
accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined
by the static timing analyzer (TRCE) can be used as a worst-case pin-to-pin no-delay input hold specification.
6-84
DS005 (v. 1.8 October 18, 1999 - Product Specification
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000XL IOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature).
Speed Grade
Device
-3
-2
-1
-09
-08
Units
Description
Symbol
Min
Min
Min
Min
Min
Clocks
Clock Enable (EC) to Clock (IK)
T
T
All devices
0.1
0.1
0.1
0.1
0.1
1.6
ns
ECIK
Delay from FCL enable (OK) active edge to
IFF clock (IK) active edge
XC4002XL
XC4013, 36, 62XL
Balance of Family
3.0
2.2
2.2
2.7
1.9
1.9
2.3
1.6
1.6
2.3
1.6
1.6
ns
ns
ns
OKIK
Setup Times
Pad to Clock (IK), no delay
T
XC4002XL
XC4013, 36, 62XL
Balance of Family
2.6
1.7
1.7
2.3
1.5
1.5
2.0
1.3
1.3
2.0
1.3
1.3
ns
ns
ns
PICK
1.2
Pad to Clock (IK), via transparent Fast Cap-
ture Latch, no delay
T
XC4002XL
XC4013, 36, 62XL
Balance of Family
3.2
2.3
2.3
2.9
2.0
2.0
2.5
1.8
1.8
2.4
1.7
1.7
ns
ns
ns
PICKF
1.6
0.9
Pad to Fast Capture Latch Enable (OK), no
delay
T
XC4013, 36, 62XL
Balance of Family
1.2
1.2
1.0
1.0
0.9
0.9
0.9
0.9
ns
ns
POCK
Hold Times
All Hold Times
All Devices
All devices
0
0
0
0
0
6
Global Set/Reset
Minimum GSR Pulse Width
Global Set/Reset
T
19.8
Max
17.3
Max
15.0
Max
14.0
Max
14.0
Max
ns
MRW
Delay from GSR input to any Q
T
XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
9.8
8.5
9.8
7.4
8.5
7.0
8.1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RRI*
11.3
13.9
15.9
18.6
20.5
22.5
25.1
27.2
29.1
34.4
12.1
13.8
16.1
17.9
19.6
21.9
23.6
25.3
29.9
10.5
12.0
14.0
15.5
17.0
19.0
20.5
22.0
26.0
10.0
11.4
13.3
14.3
16.2
18.1
19.5
20.9
24.7
10.9
16.2
20.4
Propagation Delays
Pad to I1, I2
TPID
TPLI
All devices
XC4002XL
XC4013, 36, 62XL
Balance of Family
X4002XL
XC4013, 36, 62XL
Balance of Family
All devices
All devices
XC4002XL
XC4013, 36, 62XL
Balance of Family
1.6
4.7
3.1
3.1
5.4
3.7
3.7
1.7
1.8
5.2
3.6
3.6
1.4
4.2
2.7
2.7
4.7
3.3
3.3
1.5
1.6
4.6
3.1
3.1
1.2
3.6
2.4
2.4
4.1
2.8
2.8
1.3
1.4
4.0
2.7
2.7
1.1
3.5
2.2
2.2
3.9
2.7
2.7
1.2
1.3
3.8
2.6
2.6
1.0
2.1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Pad to I1, I2 via transparent input latch,
no delay
Pad to I1, I2 via transparent FCL and in- TPFLI
put latch, no delay
2.5
Clock (IK) to I1, I2 (flip-flop)
Clock (IK) to I1, I2 (latch enable, active
Low)
FCL Enable (OK) active edge to I1, I2
(via transparent standard input latch)
TIKRI
TIKLI
TOKLI
1.2
1.3
2.5
IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch
* Indicates Minimum Amount of Time to Assure Valid Data.
DS005 (v. 1.8 October 18, 1999 - Product Specification
6-85
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000XL IOB Output Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). For Propagation Delays, slew-rate = fast unless
otherwise noted. Values are expressed in nanoseconds unless otherwise noted.
-3
-2
-1
-09
-08
Description
Symbol Min Max Min Max Min Max Min Max Min Max
Clocks
Clock High
Clock Low
TCH
TCL
3.0
3.0
2.8
2.8
2.5
2.5
2.3
2.3
2.1
2.1
Propagation Delays
Clock (OK) to Pad
Output (O) to Pad
3-state to Pad hi-Z (slew-rate independent) TTSHZ
3-state to Pad active and valid
Output (O) to Pad via Fast Output MUX
Select (OK) to Pad via Fast MUX
TOKPOF
TOPF
5.0
4.1
4.0
4.4
5.5
5.1
4.3
3.6
3.5
3.8
4.8
4.5
3.8
3.1
3.0
3.3
4.2
3.9
3.5
3.0
2.9
3.3
4.0
3.7
3.3
2.8
2.9
3.3
3.7
3.4
TTSONF
TOFPF
TOKFPF
Setup and Hold Times
Output (O) to clock (OK) setup time
Output (O) to clock (OK) hold time
Clock Enable (EC) to clock (OK) setup time TECOK
Clock Enable (EC) to clock (OK) hold time TOKEC
TOOK
TOKO
0.5
0.0
0.0
0.3
0.4
0.0
0.0
0.2
0.3
0.0
0.0
0.1
0.3
0.0
0.0
0.0
0.3
0.0
0.0
0.0
Global Set/Reset
Minimum GSR pulse width
Delay from GSR input to any Pad
XC4002XL
TMRW
TRPO*
19.8
17.3
15.0
14.0
14.0
14.3
15.9
18.5
20.5
23.2
25.1
27.1
29.7
31.7
33.7
39.0
12.5
13.8
16.1
17.8
20.1
21.9
23.6
25.9
27.6
29.3
33.9
10.9
12.0
14.0
15.5
17.5
19.0
20.5
22.5
24.0
25.5
29.5
10.3
11.4
13.3
14.7
16.6
17.6
19.4
21.4
22.8
24.2
28.0
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
14.0
19.3
23.5
XC4062XL
XC4085XL
Slew Rate Adjustment
For output SLOW option add
TSLOW
3.0
2.5
2.0
1.7
1.6
Note: Output timing is measured at ~50% V threshold, with 50 pF external capacitive loads.
CC
* Indicates Minimum Amount of Time to Assure Valid Data.
6-86
DS005 (v. 1.8 October 18, 1999 - Product Specification
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Revision Control
Version
Nature of Changes
2/1/99 (1.5) Release included in the 1999 data book, section 6
5/14/99 (1.6) Replaced Electrical Specification and pinout pages for E, EX, and XL families with separate updates and
added URL link on placeholder page for electrical specifications/pinouts for WebLINX users
9/30/99 (1.7) Added Power-on specification.
10/18/99 (1.8) Corrected posted file to include missing page (IOB Output Parameters).
6
DS005 (v. 1.8 October 18, 1999 - Product Specification
6-87
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-88
DS005 (v. 1.8 October 18, 1999 - Product Specification
0
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Device-Specific Pinout Tables
Device-specific tables include all packages for each XC4000 and XC4000X Series device. They follow the pad locations
around the die, and include boundary scan register locations..
XC4002XL
Pad Names
Boundary
Scan
XC4002XL Device Pinout Tables
PC84
PQ100 VQ100 PG120
I/O
-
P59
P60
P61
P64
P65
P66
P67
P68
P69
P71
P72
P73
P74
P56
P57
P58
P61
P62
P63
P64
P65
P66
P68
P69
P70
P71
N11
M9
N10
M8
N8
M7
L7
N7
N6
L6
160
163
166
169
172
XC4002XL
Pad Names
Boundary
Scan
PC84
PQ100 VQ100 PG120
I/O (D5)
I/O (CS0)
I/O (D4)
I/O
VCC
GND
I/O (D3)
I/O (RS)
I/O (D2)
I/O
I/O (D1)
I/O (RCLK,
RDY/BUSY)
I/O (D0, DIN)
I/O, GCK6 (DOUT)
CCLK
P59
P60
P61
P62
P63
P64
P65
P66
P67
P68
P69
P70
VCC
P2
P3
P4
P5
P6
P7
P8
P9
P92
P93
P94
P97
P98
P99
P100
P1
P89
P90
P91
P94
P95
P96
P97
P98
P99
P100
P1
G3
G1
F1
F3
D1
C1
D2
C2
D3
I/O (A8)
I/O (A9)
I/O (A10)
I/O (A11)
I/O (A12)
I/O (A13)
I/O (A14)
I/O,GCK8 (A15)
VCC
26
29
32
35
38
41
44
47
175
178
181
184
187
190
N4
M5
N3
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
-
P28
P29
P30
P31
P32
P33
P34
P35
P36
-
P37
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55
P56
P57
P58
P2
P3
P4
C3
C4
GND
I/O, GCK1(A16)
I/O (A17)
I/O, TDI
I/O, TCK
I/O, TMS
I/O
P5
P2
B2
50
53
56
59
62
65
68
71
P71
P72
P73
P74
P75
P76
P77
P78
P79
P80
P81
P82
P83
P84
P1
P75
P76
P77
P78
P79
P80
P81
P82
P83
P84
P85
P86
P89
P90
P91
P72
P73
P74
P75
P76
P77
P78
P79
P80
P81
P82
P83
P86
P87
P88
N2
M3
L4
193
196
P6
P3
B3
P7
P4
C5
P8
P5
B4
VCC
O, TDO
GND
L3
P9
P6
B5
M2
K3
L2
N1
K2
L1
P10
P12
P13
P14
P15
P16
P17
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P38
P39
P40
P41
P42
P43
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55
P56
P57
P58
P7
P9
A4
B6
A6
B7
C7
A7
A8
C8
A10
B9
A11
C9
I/O
I/O
I/O (A0, WS)
I/O, GCK7(A1)
I/O (CS1, A2)
I/O (A3)
I/O (A4)
I/O (A5)
I/O (A6)
I/O (A7)
GND
2
5
8
11
14
17
20
23
P10
P11
P12
P13
P14
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P35
P36
P37
P38
P39
P40
P43
P44
P45
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
74
77
80
83
86
89
92
95
98
J2
K1
H2
H1
G2
1/22/99
I/O, GCK2
O (M1)
GND
I (M0)
VCC
I (M2)
I/O, GCK3
I/O (HDC)
I/O
I/O (LDC)
I/O
A12
B11
C10
C11
D11
B12
C12
A13
D12
C13
E12
D13
F12
F13
G12
G11
G13
H13
H11
K13
J12
L13
M13
L12
K11
L11
L10
M12
M11
N13
M10
Additional XC4002XL Package Pins
PG120
101
102
103
106
109
112
115
118
121
124
N.C. Pins
E1
A2
B10
K12
N5
F2
A3
B13
J11
M6
J1
E2
C6
E11
N12
M4
E3
A5
E13
L9
B1
A9
J13
L8
A1
B8
H12
N9
J3
L5
M1
I/O
I/O
H3
1/22/99
I/O (INIT)
VCC
GND
•
PQ100
I/O
I/O
I/O
I/O
I/O
I/O
I/O
127
130
133
136
139
142
145
148
N.C. Pins
P11
P62
P96
P18
P63
P36
P70
P37
P87
P44
P88
P45
P95
1/22//99
•
I/O, GCK4
GND
DONE
VCC
PROGRAM
I/O (D7)
I/O, GCK5
I/O (D6)
VQ100
N.C. Pins
P8
P59
P93
P15
P60
P33
P67
P34
P84
P41
P85
P42
P92
151
154
157
1/22//99
DS006 (v. 1.7) October 4, 1999 - Product Specification
6-117
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4003E
Pad Name
XC4003E Device Pinout Tables
PC84
PQ100 VQ100 PG120 Bndry Scan
I/O
I/O
I/O
I/O
I/O
I/O, SGCK3
GND
DONE
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55
P56
P57
P58
-
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
P66
P67
P68
P69
P70
-
P43
P44
P45
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
P66
P67
-
H11
K13
J12
L13
M13
L12
K11
L11
L10
M12
M11
N13
M10
N11
M9
N10
L8
N9
M8
N8
M7
L7
N7
N6
169
172
175
178
181
184
-
-
-
-
187
190
193
196
199
202
205
208
211
214
-
XC4003E
Pad Name
PC84
PQ100 VQ100 PG120 Bndry Scan
VCC
P2
P3
P4
-
-
P5
P6
P7
P8
P92
P93
P94
P95
P96
P97
P98
P99
P100
P1
P89
P90
P91
P92
P93
P94
P95
P96
P97
P98
P99
P100
P1
G3
G1
F1
E1
F2
F3
D1
C1
D2
C2
D3
C3
C4
-
32
35
38
41
44
47
50
53
56
59
-
I/O (A8)
I/O (A9)
I/O
I/O
I/O (A10)
I/O (A11)
I/O (A12)
I/O (A13)
I/O (A14)
I/O, SGCK1 (A15)
VCC
VCC
PROGRAM
I/O (D7)
I/O, PGCK3
I/O (D6)
I/O
I/O (D5)
I/O (CS0)
I/O
I/O
I/O (D4)
I/O
VCC
GND
I/O (D3)
I/O (RS)
I/O
I/O
I/O (D2)
I/O
I/O (D1)
I/O (RCLK,
RDY/BUSY)
I/O (D0, DIN)
I/O, SGCK4 (DOUT)
CCLK
VCC
O, TDO
GND
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
-
P2
P3
P4
P59
P60
-
GND
-
I/O, PGCK1 (A16)
I/O (A17)
I/O, TDI
I/O, TCK
I/O, TMS
I/O
P5
P2
B2
62
P6
P3
B3
65
-
P7
P4
C5
68
P61
P62
P63
P64
P65
P66
-
P8
P5
B4
71
P9
P6
B5
74
P10
-
P7
-
A4
C6
77
80
-
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
217
220
223
226
229
232
235
238
-
P11
P12
P13
P14
P15
P16
P17
P18
-
P8
P9
A5
B6
A6
B7
C7
A7
A8
A9
B8
C8
A10
B9
A11
C9
A12
B11
C10
C11
D11
B12
C12
A13
D12
C13
E12
D13
F11
E13
F12
F13
G12
G11
G13
H13
J13
H12
83
86
89
-
-
92
95
98
101
104
107
110
113
116
119
122
-
P19
P20
P21
P22
P23
P24
-
N5
M6
L6
N4
M5
N3
P10
P11
P12
P13
P14
P15
-
-
P67
P68
P69
P70
P71
P72
P73
P74
P68
P69
P70
P71
-
P71
P72
P73
P74
P75
P76
P77
P78
P79
P80
P81
P82
-
P75
P76
P77
P78
P79
P80
P81
P82
P83
P84
P85
P86
P87
P88
P89
P90
P91
P72
P73
P74
P75
P76
P77
P78
P79
P80
P81
P82
P83
P84
P85
P86
P87
P88
N2
M3
L4
L3
M2
K3
L2
N1
K2
L1
J2
K1
H3
J1
H2
H1
G2
241
244
-
-
0
-
2
5
8
11
14
17
20
23
26
29
-
P25
P26
P27
-
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P40
P41
P42
P43
P44
P45
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P40
P41
P42
P28
P29
P30
P31
P32
P33
P34
P35
P36
-
I/O, SGCK2
O (M1)
GND
I (M0)
VCC
I (M2)
I/O, PGCK2
I/O (HDC)
I/O
I/O (LDC)
I/O
I/O (A0, WS)
I/O, PGCK4 (A1)
I/O (CS1, A2)
I/O (A3)
I/O (A4)
I/O (A5)
I/O
125
-
126
127
130
133
136
139
142
145
148
151
154
-
I/O
-
I/O (A6)
I/O (A7)
GND
P83
P84
P1
P37
P38
P39
-
I/O
I/O
I/O
I/O
5/5/97
-
Additional XC4003E Package Pins
PG120
P40
P41
P42
P43
P44
P45
-
I/O (INIT)
VCC
Not Connected Pins
GND
I/O
I/O
I/O
-
A1
E2
L5
A2
E3
L9
A3
E11
M1
B1
J3
M4
B10
J11
N12
B13
K12
-
157
160
163
166
5/5/97
I/O
-
6-118
DS006 (v. 1.7) October 4, 1999 - Product Specification
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4005E/XL Device Pnout Tables
The following table may contain pinout information for unsupported device/package combinations. Please see the availability
charts elsewhere in the XC4000 Series data sheet for availability information.
XC4005E/XL
Pad Name
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O (INIT)
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O, SGCK3 †,
GCK4 ††
GND
DONE
VCC
PROGRAM
I/O (D7)
I/O, PGCK3†,
GCK5††
I/O
I/O
I/O (D6)
I/O
GND
I/O
I/O
PC
84
-
-
PQ
VQ
TQ
PG
PQ
PQ Bndry
208 Scan
XC4005E/XL
Pad Name
VCC
I/O (A8)
I/O (A9)
I/O (A19) ††
I/O (A18) ††
I/O (A10)
I/O (A11)
I/O
I/O
GND
I/O (A12)
I/O (A13)
I/O
PC
84
PQ
VQ
TQ
PG
PQ
PQ Bndry
208 Scan
100 100†† 144 156† 160
100 100†† 144 156† 160
-
-
-
-
-
-
P45
P46
P47
P48
F14
F15
E16
F16
P51 P67
-
P2 P92 P89 P128 H3 P142 P183
P3 P93 P90 P129 H1 P143 P184
P4 P94 P91 P130 G1 P144 P185
-
-
P5 P97 P94 P133
P6 P98 P95 P134
-
-
-
P7 P99 P96 P138
P8 P100 P97 P139 C1 P155 P200
-
-
P9
-
P52 P68
P53 P69
P54 P70
193
196
199
202
205
208
211
214
-
44
47
50
53
56
59
62
65
-
68
71
74
77
80
83
-
P38 P34 P31
P39 P35 P32
-
-
P40 P38 P35
P41 P39 P36
P42 P40 P37
P43 P41 P38
P44 P42 P39
P45 P43 P40
P95 P92 P131 G2 P145 P186
P96 P93 P132 G3 P146 P187
P49 G14 P55 P71
P50 G15 P56 P74
P51 G16 P57 P75
P52 H16 P58 P76
P53 H15 P59 P77
P54 H14 P60 P78
P55
P56
P57
P58
P59
P60
P61
P36 P33
P37 P34
F1
F2
E1
E2
F3
E3
P147 P190
P148 P191
P149 P192
P150 P193
P151 P194
P154 P199
-
-
-
-
-
-
P135
P136
P137
J14
J15
J16
K16
K15
K14
L16
P61 P79
P62 P80
P63 P81
P64 P82
P65 P83
P66 P86
P67 P87
-
217
220
223
226
229
232
235
238
-
241
244
247
250
253
-
-
P1
-
-
P140 C2 P156 P201
P141 D3 P157 P202
-
-
P44 P41
P45 P42
I/O
I/O (A14)
I/O, SGCK1 †,
GCK8 †† (A15)
VCC
P98 P142
P99 P143
B1
B2
P158 P203
P159 P204
P46 P46 P43
P47 P47 P44
-
-
-
P48 P48 P45
P49 P49 P46
-
-
P10 P2
-
-
-
-
-
-
P62 M16 P68 P88
P11 P3 P100 P144 C3 P160 P205
P12 P4
P13 P5
-
-
86
P63
P64
P65
L15
L14
P16
P69 P89
P70 P90
P73 P95
GND
P1
P2
P1
P2
C4
B3
P1
P2
P2
P4
I/O, PGCK1†,
GCK1†† (A16)
I/O (A17)
I/O
P66 M14 P74 P96
P67 N15 P75 P97
P68
P69 N14 P77 P99
P70 R16 P78 P100 256
P14 P6
-
-
P15 P7
P16 P8
-
-
-
P17 P9
P18 P10
-
-
P3
-
-
P4
P5
-
P3
P4
P5
P6
P7
A1
A2
C5
B4
A3
C6
B5
B6
A5
C7
B7
A6
A7
A8
C8
B8
C9
B9
A9
B10
P3
P4
P5
P6
P7
P5
P6
P7
P8
P9
89
92
95
98
101
-
-
-
-
-
-
-
P15
P76 P98
I/O
P50 P50 P47
P51 P51 P48
I/O, TDI
I/O, TCK
GND
I/O
I/O
I/O, TMS
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
-
-
-
P8
P9
P10 P14
P11 P15
P12 P16
P13 P17
P14 P18
P15 P21
P16 P22
P17 P23
P18 P24
P19 P25
P20 P26
P21 P27
P22 P28
P23 P29
P24 P30
P52 P52 P49
P53 P53 P50
P54 P54 P51
P55 P55 P52
P56 P56 P53
P57 P57 P54
P71
P72 R15 P80 P103
P73 P13 P81 P106
P74 R14 P82 P108
P75
P76
P14
P79 P101
-
-
-
-
-
-
104
107
110
113
116
119
122
125
-
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P6
P7
-
P8
P9
T16
T15
P83 P109 259
P84 P110 262
-
P11
P19 P12
-
-
-
-
-
-
P77 R13 P85 P111 265
P20 P13 P10
P21 P14 P11
P22 P15 P12
P23 P16 P13
P24 P17 P14
P78
P79
P80
P81
P12
T14
T13
P11
P86 P112 268
P87 P113 271
P88 P114 274
P58 P58 P55
-
-
-
-
-
P59 P56
128
131
134
137
140
143
146
149
-
152
155
158
161
164
167
-
-
-
-
-
-
P91 P119
-
P82 R11 P92 P120 277
-
-
P18 P15
-
P83
P84
P85
T11
T10
P10
P93 P121 280
P94 P122 283
P95 P123 286
-
I/O (D5)
I/O (CS0)
I/O
I/O
I/O (D4)
I/O
P59 P60 P57
P60 P61 P58
-
-
P61 P64 P61
P62 P65 P62
P63 P66 P63
P64 P67 P64
P65 P68 P65
P66 P69 P66
P25 P19 P16
P26 P20 P17
-
-
-
P23 C10 P25 P33
P24
P25
P26
A10
A11
B11
P26 P34
P27 P35
P28 P36
P62 P59
P63 P60
P86 R10 P96 P126 289
-
-
-
-
-
-
P87
P88
P89
P90
P91
P92
P93
P94
P95
P96
P97
P98
P99
P100
T9
R9
P9
P97 P127 292
P98 P128 295
P99 P129 298
P27 C11 P29 P37
P27 P21 P18
P28
P29
P30
B12
A13
A14
P32 P42
P33 P43
P34 P44
VCC
R8 P100 P130
-
-
-
-
-
P22 P19
-
-
GND
I/O (D3)
I/O (RS)
I/O
I/O
I/O (D2)
I/O
P8
T8
T7
T6
P101 P131
-
-
P102 P132 301
P103 P133 304
P104 P134 307
P31 C12 P35 P45
P32
P33
I/O
P28 P23 P20
P29 P24 P21
B13
B14
P36 P46
P37 P47
-
-
P70 P67
-
I/O, SGCK2 †,
GCK2 ††
O (M1)
GND
I (M0)
VCC
I (M2)
I/O, PGCK2 †,
GCK3 ††
I/O (HDC)
I/O
-
R7 P105 P135 310
P7
T5
P67 P71 P68
P68 P72 P69
-
-
-
P106 P138 313
P107 P139 316
P30 P25 P22
P31 P26 P23
P32 P27 P24
P33 P28 P25
P34 P29 P26
P35 P30 P27
P34
A15
P38 P48
170
-
173
-
174
175
P35 C13 P39 P49
P36 A16 P40 P50
P37 C14 P41 P55
P38
P39
I/O
I/O
-
-
-
-
-
-
R6 P108 P140 319
T4
P6
T3
P5
P109 P141 322
P110 P142
P113 P147 325
P114 P148 328
GND
I/O (D1)
I/O (RCLK,
RDY/BUSY)
I/O
-
B15
B16
P42 P56
P43 P57
P69 P73 P70 P101
P70 P74 P71 P102
P36 P31 P28
P40 D14 P44 P58
P41 C15 P45 P59
P42 D15 P46 P60
178
181
184
187
190
-
-
-
-
-
-
P103 R4 P115 P149 331
P104 R3 P116 P150 334
-
-
-
-
-
-
-
I/O
I/O
I/O
I/O (LDC)
I/O (D0, DIN)
P71 P75 P72 P105
P4
P117 P151 337
P32 P29
P43
E14
P47 P61
P37 P33 P30
P44 C16 P48 P62
DS006 (v. 1.7) October 4, 1999 - Product Specification
6-119
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4005E/XL
Pad Name
I/O, SGCK4 †,
GCK6 †† (DOUT)
CCLK
VCC
O, TDO
GND
I/O (A0, WS)
I/O, PGCK4 †,
GCK7 †† (A1)
I/O
PC
84
PQ
VQ
TQ
PG
PQ
PQ Bndry
208 Scan
PG156
100 100†† 144 156† 160
Not Connected Pins
P72 P76 P73 P106
T2
P118 P152 340
A4
M1
T12
A12
M2
-
D1
M15
-
D2
N16
-
D16
R5
-
E15
R12
-
P73 P77 P74 P107 R2 P119 P153
P74 P78 P75 P108
P75 P79 P76 P109
P76 P80 P77 P110 N3 P122 P160
P77 P81 P78 P111 R1 P123 P161
P78 P82 P79 P112
-
-
0
-
2
5
P3
T1
P120 P154
P121 P159
5/5/97
PQ160
P2
P124 P162
Not Connected Pins
P8
P71
P129
P9
P72
P130
P30
P89
P31
P90
P49
P111
P153
P50
P112
-
-
-
-
-
-
-
P113 N2 P125 P163
P114 M3 P126 P164
8
I/O
11
14
17
-
20
23
26
29
32
35
38
41
-
P136
P152
I/O (CS1, A2)
I/O (A3)
GND
I/O
I/O
I/O (A4)
I/O (A5)
I/O (A21) ††
I/O (A20) ††
I/O (A6)
P79 P83 P80 P115
P80 P84 P81 P116 N1 P128 P166
-
-
-
P81 P85 P82 P121
P82 P86 P83 P122
-
-
P83 P89 P86 P125
P84 P90 P87 P126
P1 P91 P88 P127 H2 P141 P182
P1
P127 P165
6/16/97
-
-
-
-
-
-
P118
P119
P120
L3
L2
L1
K3
K2
K1
J1
J2
J3
P131 P171
P132 P172
P133 P173
P134 P174
P135 P175
P137 P178
P138 P179
P139 P180
P140 P181
PQ208
Not Connected Pins
P1
P19
P40
P63
P84
P3
P20
P41
P64
P10
P31
P11
P32
P12
P38
P53
P72
P93
P115
P136
P155
P169
P195
P208
P13
P39
P54
P73
P94
P116
P137
P156
P170
P196
-
P87 P84 P123
P88 P85 P124
P51
P52
P65
P66
P85
P91
P92
I/O (A7)
GND
6/10/97
P102
P117
P143
P157
P176
P197
6/5/97
P104
P118
P144
P158
P177
P198
P105
P124
P145
P167
P188
P206
P107
P125
P146
P168
P189
P207
† = E only
†† = XL only
Additional XC4005E/XL Package Pins
TQ144
Not Connected Pins
P117
5/5/97
-
-
-
-
-
XC4006E Device Pinout Tables
XC4006E
Pad Name
PC
84
-
-
P17
P18
-
TQ
144
P9
PG
156
B5
B6
A5
C7
B7
A6
A7
A8
C8
B8
C9
B9
A9
B10
C10
A10
A11
B11
C11
A12
-
B12
A13
A14
C12
B13
B14
A15
C13
PQ
160
PQ
Bndry
Scan
XC4006E
Pad Name
PC
84
P2
P3
P4
-
TQ
144
P128
P129
P130
P131
P132
P133
P134
P135
P136
P137
-
PG
156
H3
H1
G1
G2
G3
F1
F2
E1
E2
F3
D1
D2
E3
C1
C2
D3
B1
B2
C3
C4
B3
A1
A2
C5
B4
A3
A4
-
PQ
160
PQ
208
Bndry
Scan
-
208
P15
P16
P17
P18
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P33
P34
P35
P36
P37
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
I/O
I/O
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
122
125
128
131
134
137
140
143
-
VCC
P142 P183
P143 P184
P144 P185
P145 P186
P146 P187
P147 P190
P148 P191
P149 P192
P150 P193
P151 P194
P152 P197
P153 P198
P154 P199
P155 P200
P156 P201
P157 P202
P158 P203
P159 P204
P160 P205
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
-
I/O (A8)
I/O (A9)
I/O
50
53
56
59
62
65
68
71
-
74
77
80
83
86
89
92
95
-
I/O, TMS
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
-
-
I/O (A10)
I/O (A11)
I/O
P5
P6
-
-
-
-
-
P7
P8
-
P19
P20
P21
P22
P23
P24
-
I/O
GND
I/O
I/O
-
146
149
152
155
158
161
164
167
-
170
173
176
179
182
185
188
191
194
-
-
I/O (A12)
I/O (A13)
I/O
P138
P139
P140
P141
P142
P143
P144
P1
P2
P3
P4
P5
-
P25
P26
-
-
-
I/O
-
I/O (A14)
I/O, SGCK1 (A15)
VCC
P9
P10
P11
P12
P13
P14
-
-
-
GND
P2
P4
P5
P6
P7
P8
P9
P10
P11
P14
-
-
I/O, PGCK1 (A16)
I/O (A17)
I/O
98
101
104
107
110
113
116
119
-
P27
-
-
P28
P29
P30
P31
P32
P33
P34
P35
I/O
I/O
I/O
I/O
I/O
-
-
I/O, TDI
I/O, TCK
I/O
P15
P16
-
-
-
P6
P7
-
-
P28
P29
P30
P31
I/O, SGCK2
O (M1)
GND
I/O
GND
P8
C6
6-120
DS006 (v. 1.7) October 4, 1999 - Product Specification
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4006E
Pad Name
I (M0)
VCC
I (M2)
I/O, PGCK2
I/O (HDC)
I/O
PC
84
P32
P33
P34
P35
P36
-
TQ
144
P36
P37
P38
P39
P40
P41
P42
P43
P44
-
PG
156
A16
C14
B15
B16
D14
C15
D15
E14
C16
E15
D16
F14
F15
E16
F16
G14
G15
G16
H16
H15
H14
J14
J15
J16
K16
K15
K14
L16
M16
L15
L14
N16
M15
P16
M14
N15
P15
N14
R16
P14
R15
P13
R14
T16
T15
R13
P12
T14
T13
R12
T12
P11
R11
T11
T10
P10
R10
T9
PQ
160
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
P66
P67
P68
P69
P70
P71
P72
P73
P74
P75
P76
P77
P78
P79
P80
P81
P82
P83
P84
P85
P86
P87
P88
P89
P90
P91
P92
P93
P94
P95
P96
P97
P98
P99
PQ
208
P50
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
P67
P68
P69
P70
P71
P74
P75
P76
P77
P78
P79
P80
P81
P82
P83
P86
P87
P88
P89
P90
Bndry
Scan
197
-
XC4006E
Pad Name
PC
84
-
TQ
144
PG
156
PQ
160
PQ
208
Bndry
Scan
I/O
I/O
P94
P95
P96
P97
P98
P99
P100
-
T6
R7
P7
T5
R6
T4
P6
R5
-
P104 P134
P105 P135
P106 P138
P107 P139
P108 P140
P109 P141
P110 P142
P111 P145
P112 P146
P113 P147
P114 P148
349
352
355
358
361
364
-
367
370
373
376
-
198
199
202
205
208
211
214
217
220
-
223
226
229
232
235
238
241
244
-
I/O (D2)
I/O
P67
P68
-
-
-
-
-
I/O
I/O
GND
I/O
I/O
I/O
-
-
I/O (LDC)
I/O
P37
-
-
-
-
I/O
-
I/O (D1)
I/O (RCLK,
RDY/BUSY)
I/O
P69
P70
P101
P102
T3
P5
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
P45
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
-
-
-
P103
P104
P105
P106
P107
P108
P109
P110
P111
P112
P113
P114
P115
P116
P117
-
P118
P119
P120
P121
P122
P123
P124
P125
P126
P127
R4
R3
P4
T2
R2
P3
T1
N3
R1
P2
N2
M3
P1
N1
M2
M1
L3
L2
L1
K3
K2
K1
J1
J2
J3
H2
P115 P149
P116 P150
P117 P151
P118 P152
P119 P153
P120 P154
P121 P159
P122 P160
P123 P161
P124 P162
P125 P163
P126 P164
P127 P165
P128 P166
P129 P167
P130 P168
P131 P171
P132 P172
P133 P173
P134 P174
P135 P175
P137 P178
P138 P179
P139 P180
P140 P181
P141 P182
379
382
385
388
-
-
0
-
2
I/O
-
I/O (D0, DIN)
I/O, SGCK4 (DOUT) P72
CCLK
VCC
O, TDO
GND
I/O (A0, WS)
I/O, PGCK4 (A1)
I/O
P71
P38
P39
-
P73
P74
P75
P76
P77
P78
-
-
P40
P41
P42
P43
P44
P45
-
I/O (INIT)
VCC
GND
I/O
5
8
-
247
250
253
256
259
262
265
268
-
271
274
277
280
283
286
289
292
-
I/O
-
11
14
17
20
23
-
26
29
32
35
38
41
44
47
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O (CS1, A2)
I/O (A3)
I/O
P79
P80
-
-
-
-
P46
P47
-
-
-
I/O
GND
I/O
I/O
-
-
I/O (A4)
I/O (A5)
I/O
P81
P82
-
-
-
P93
P94
P95
P96
P97
P98
P99
-
P48
P49
-
P65
P66
P67
P68
P69
P70
P71
P72
P73
P74
P75
P76
P77
P78
P79
P80
-
I/O
-
I/O (A6)
I/O (A7)
GND
P83
P84
P1
-
P50
P51
P52
P53
P54
P55
P56
P57
-
5/5/97
I/O, SGCK3
GND
DONE
VCC
PROGRAM
I/O (D7)
I/O, PGCK3
I/O
P100
P101
P103
P106
P108
P109
P110
P111
P112
P113
P114
P115
P116
P119
P120
P121
P122
P123
P126
P127
P128
P129
-
-
-
Additional XC4006E Package Pins
PQ160
295
298
301
304
307
310
313
316
-
319
322
325
328
331
334
337
340
-
Not Connected Pins
P136
5/5/97
-
-
-
-
I/O
-
I/O (D6)
I/O
P58
-
-
-
-
PQ208
P1
I/O
I/O
GND
I/O
I/O
Not Connected Pins
-
P3
P31
P52
P72
P12
P32
P53
P13
P38
P54
P19
P39
P65
P85
P105
P125
P155
P170
P195
-
P81
P82
P83
P84
P85
P86
P87
P88
P89
P90
P91
P92
P93
P20
P51
P66
-
-
P73
P84
I/O (D5)
I/O (CS0)
I/O
P59
P60
-
P91
P92
P102
P118
P143
P158
P188
P207
P104
P124
P144
P169
P189
P208
P107
P136
P156
P176
P196
P117
P137
P157
P177
P206
I/O
-
I/O (D4)
I/O
VCC
GND
I/O (D3)
I/O (RS)
P61
P62
P63
P64
P65
P66
R9
P9
R8
P8
T8
T7
P100 P130
P101 P131
P102 P132
P103 P133
6/5/97
-
343
346
DS006 (v. 1.7) October 4, 1999 - Product Specification
6-121
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4008E Device Pinout Tables
XC4008E Pad Name
I/O (HDC)
I/O
PC84 PQ160 PG191 PQ208 Bndry Scan
XC4008E Pad Name
VCC
I/O (A8)
I/O (A9)
I/O
I/O
I/O
I/O
I/O (A10)
I/O (A11)
I/O
I/O
GND
I/O
I/O
I/O (A12)
I/O (A13)
PC84 PQ160 PG191 PQ208 Bndry Scan
P36
-
-
-
P37
-
-
-
P44
P45
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55
-
E16
C17
D17
B18
E17
F16
C18
G16
E18
F18
G17
G18
H16
H17
H18
J18
J17
J16
J15
K15
K16
K17
K18
L18
L17
L16
M18
M17
N18
P18
M16
T18
P17
N16
T17
R17
P16
U18
T16
R16
U17
R15
V18
T15
U16
T14
U15
V17
V16
T13
U14
T12
U13
V13
U12
V12
T11
U11
V11
V10
U10
T10
R10
R9
P58
P59
P60
P61
P62
P63
P64
P67
P68
P69
P70
P71
P72
P73
P74
P75
P76
P77
P78
P79
P80
P81
P82
P83
P84
P85
P86
P87
P88
P89
P90
P93
P94
226
229
232
235
238
241
244
-
247
250
253
256
259
262
265
268
271
274
-
P2
P3
P4
-
-
-
-
P5
P6
-
-
-
P142
P143
P144
P145
P146
-
J4
J3
J2
J1
H1
H2
H3
G1
G2
F1
E1
G3
C1
E2
F3
D2
B1
E3
C2
B2
D3
D4
C3
C4
B3
C5
A2
B4
C6
A3
C7
P183
P184
P185
P186
P187
P188
P189
P190
P191
P192
P193
P194
P197
P198
P199
P200
P201
P202
P203
P204
P205
P2
-
56
59
62
65
68
71
74
77
80
83
-
86
89
92
95
I/O
I/O
I/O (LDC)
I/O
I/O
-
GND
I/O
P147
P148
P149
P150
P151
P152
P153
P154
P155
P156
P157
P158
P159
P160
P1
P2
P3
P4
P5
P6
P7
P8
P9
-
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P38
P39
-
-
-
-
P40
P41
P42
P43
P44
P45
-
-
-
-
-
P7
P8
-
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
-
I/O
I/O
98
I/O (INIT)
VCC
GND
I/O
-
101
104
107
-
I/O (A14)
I/O, SGCK1 (A15)
P9
P10
P11
P12
P13
P14
-
-
277
280
283
286
289
292
295
298
301
304
-
307
310
313
316
319
322
325
328
-
VCC
GND
I/O, PGCK1 (A16)
I/O (A17)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
P4
P5
P6
P7
P8
P9
110
113
116
119
122
125
128
131
-
-
-
-
I/O
-
P46
P47
-
-
-
-
-
P48
P49
-
-
P50
P51
P52
P53
P54
P55
P56
P57
-
P66
P67
P68
P69
P70
P71
P72
P73
P74
P75
P76
P77
P78
P79
P80
P81
P82
P83
P84
P85
P86
P87
P88
P89
P90
P91
P92
P93
P94
P95
-
I/O, TDI
I/O, TCK
I/O
I/O
GND
I/O
I/O
I/O, TMS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P15
P16
-
-
-
P10
P11
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
P37
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P50
P55
P56
P57
I/O
GND
I/O
P10
P11
P12
P13
P14
-
-
-
A4
A5
B7
A6
C8
A7
B8
A8
B9
C9
D9
D10
C10
B10
A9
A10
A11
C11
B11
A12
B12
A13
C12
A15
C13
B14
A16
B15
C14
A17
B16
C15
D15
A18
D16
C16
B17
134
137
140
143
146
149
152
155
158
161
-
I/O
I/O
I/O
I/O
I/O
I/O
P95
P96
P97
P98
P17
P18
-
-
-
-
P99
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
-
I/O, SGCK3
GND
DONE
VCC
PROGRAM
I/O (D7)
I/O, PGCK3
I/O
P100
P101
P103
P106
P108
P109
P110
P111
P112
P113
P114
P115
P116
P119
P120
P121
P122
P123
P124
P125
P126
P127
P128
P129
P130
P131
P132
P133
P134
P135
P136
-
P19
P20
P21
P22
P23
P24
-
-
-
-
P25
P26
-
-
-
-
-
-
-
331
334
337
340
343
346
349
352
-
355
358
361
364
367
370
373
376
379
382
-
164
167
170
173
176
179
182
185
188
191
-
194
197
200
203
206
209
212
215
218
-
I/O
-
I/O (D6)
I/O
P58
-
-
-
-
-
I/O
I/O
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P40
P41
P42
P43
GND
I/O
-
-
I/O
I/O (D5)
I/O (CS0)
I/O
P59
P60
-
-
-
-
-
P27
-
-
I/O
I/O
I/O
-
P96
P97
P98
P99
P100
P101
P102
P103
P104
P105
-
-
-
I/O (D4)
I/O
P61
P62
P63
P64
P65
P66
-
P28
P29
P30
P31
P32
P33
P34
P35
I/O, SGCK2
O (M1)
GND
I (M0)
VCC
I (M2)
I/O, PGCK2
VCC
GND
I/O (D3)
I/O (RS)
I/O
-
T9
U9
V9
V8
385
388
391
394
397
221
-
222
223
I/O
I/O
-
-
U8
6-122
DS006 (v. 1.7) October 4, 1999 - Product Specification
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4008E Pad Name
PC84 PQ160 PG191 PQ208 Bndry Scan
XC4008E Pad Name
I/O (A4)
I/O (A5)
I/O
I/O
I/O
PC84 PQ160 PG191 PQ208 Bndry Scan
I/O
-
-
T8
V7
U7
V6
U6
T7
U5
T6
V3
V2
U4
T5
U3
T4
V1
R4
U2
R3
T3
U1
P3
R2
T2
N3
P2
T1
M3
P1
N1
P137
P138
P139
P140
P141
P142
P145
P146
P147
P148
P149
P150
P151
P152
P153
P154
P159
P160
P161
P162
P163
P164
P165
P166
P167
P168
P171
P172
P173
400
403
406
409
412
-
P81
P82
-
-
-
P134
P135
-
P136
P137
P138
P139
P140
P141
M2
M1
L3
L2
L1
K1
K2
K3
K4
P174
P175
P176
P177
P178
P179
P180
P181
P182
32
35
38
41
44
47
50
53
-
I/O (D2)
P67
P68
-
-
-
-
-
P69
P70
-
P106
P107
P108
P109
P110
P111
P112
P113
P114
P115
P116
P117
P118
P119
P120
P121
P122
P123
P124
P125
P126
P127
P128
P129
P130
P131
P132
P133
I/O
I/O
I/O
GND
I/O
-
I/O
I/O
415
418
421
424
427
430
433
436
-
-
0
-
2
I/O (A6)
I/O (A7)
GND
5/5/97
P83
P84
P1
I/O (D1)
I/O (RCLK, RDY/BUSY)
I/O
I/O
-
I/O (D0, DIN)
I/O, SGCK4 (DOUT)
CCLK
VCC
O, TDO
GND
I/O (A0, WS)
I/O, PGCK4 (A1)
P71
P72
P73
P74
P75
P76
P77
P78
-
Additional XC4008E Package Pins
PG191
Not Connected Pins
A14
F2
V4
B5
F17
V5
B6
N2
V14
B13
N17
V15
D1
R1
-
D18
R18
-
5
8
6/3/97
I/O
I/O
-
11
14
17
20
23
-
I/O (CS1, A2)
I/O (A3)
I/O
P79
P80
-
-
-
PQ208
Not Connected Pins
P1
P3
P12
P53
P102
P143
P169
P208
P13
P54
P104
P144
P170
-
P38
P65
P105
P155
P195
-
P39
P66
P107
P156
P196
-
I/O
P51
P52
GND
I/O
P91
P92
-
-
26
29
P117
P157
P206
P118
P158
P207
I/O
DS006 (v. 1.7) October 4, 1999 - Product Specification
6-123
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4010E/XL Device Pinout Tables
The following table may contain pinout information for unsupported device/package combinations. Please see the availability
charts elsewhere in the XC4000 Series data sheet for availability information.
PQ/H
Q
208
PQ/H
Q
208
XC4010E/XL
Pad Name
PC
PQ
TQ
PQ
TQ
PG
BG
BG
Bndry
XC4010E/XL
Pad Name
PC
PQ
TQ
PQ
TQ
PG
BG
BG
Bndry
84 100†† 144†† 160 176†† 191†
225† 256†† Scan
84 100†† 144†† 160 176†† 191†
225† 256†† Scan
I/O
P27 P21 P28 P32 P36 B14 P42
L4
N1
M3
N2
K6
P1
V1
T4
U3
V2
W1
V3
224
227
230
233
236
239
VCC
P2 P92 P128 P142 P155 VCC* P183 VCC* VCC*
-
I/O
I/O
I/O
I/O
-
-
-
P22 P29 P33 P37 A16 P43
I/O (A8)
I/O (A9)
I/O (19)
I/O (18)
I/O
P3 P93 P129 P143 P156
P4 P94 P130 P144 P157
-
-
-
-
J3
J2
J1
P184
P185
P186
E8
B7
A7
C10
D10
A9
62
65
68
71
74
77
80
83
-
-
-
P30 P34 P38 B15 P44
P31 P35 P39 C14 P45
P28 P23 P32 P36 P40 A17 P46
P95 P131 P145 P158
P96 P132 P146 P159 H1 P187 C7
B9
I/O, SGCK2 †, P29 P24 P33 P37 P41 B16 P47
GCK2 ††
-
-
-
-
-
-
P160 H2 P188 D7
P161 H3 P189
P5 P97 P133 P147 P162 G1 P190
P6 P98 P134 P148 P163 G2 P191
C9
D9
A8
I/O
E7
A6
B6
O (M1)
GND
I (M0)
VCC
P30 P25 P34 P38 P42 C15 P48
N3
W2
242
-
245
-
246
247
I/O (A10)
I/O (A11)
VCC
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O (A12)
I/O (A13)
I/O
I/O
I/O (A14)
P31 P26 P35 P39 P43 GND* P49 GND* GND*
P32 P27 P36 P40 P44 A18 P50 P2 Y1
P33 P28 P37 P41 P45 VCC* P55 VCC* VCC*
B8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VCC*
-
VCC* VCC*
A5
B5
P135 P149 P164 F1 P192
P136 P150 P165 E1 P193
P137 P151 P166 GND* P194 GND* GND*
B6
A5
86
89
-
I (M2)
P34 P29 P38 P42 P46 C16 P56
M4
R2
W3
Y2
I/O, PGCK2 †, P35 P30 P39 P43 P47 B17 P57
GCK3 ††
-
-
-
-
-
-
-
F2 P195 D6
P167 D1 P196 C5
P152 P168 C1 P197
P153 P169 E2 P198
P7 P99 P138 P154 P170 F3 P199
C6
B5
A4
C5
B4
A3
B3
B2
A2
C3
92
95
98
101
104
107
110
113
116
119
I/O (HDC)
I/O
I/O
I/O
I/O (LDC)
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O (INIT)
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
P36 P31 P40 P44 P48 E16 P58
P3
L5
W4
V4
U5
Y3
Y4
V5
W5
Y5
V6
250
253
256
259
262
265
268
271
274
-
277
280
283
286
-
289
292
295
298
301
304
-
-
-
-
-
-
P41 P45 P49 C17 P59
P42 P46 P50 D17 P60
P32 P43 P47 P51 B18 P61
A4
E6
B4
N4
R3
P4
K7
M5
R4
N5
P37 P33 P44 P48 P52 E17 P62
P8 P100 P139 P155 P171 D2 P200 D5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P49 P53 F16 P63
P50 P54 C18 P64
-
-
P9
-
-
P140 P156 P172 B1 P201
P141 P157 P173 E3 P202
P1 P142 P158 P174 C2 P203
B3
F6
A2
-
-
-
-
D18 P65
F17 P66
I/O, SGCK1 †, P10 P2 P143 P159 P175 B2 P204 C3
P45 P51 P55 GND* P67 GND* GND*
P46 P52 P56 E18 P68
P47 P53 P57 F18 P69
GCK8 ††
(A15)
VCC
GND
I/O, PGCK1†, P13 P5
GCK1††
(A16)
I/O (A17)
I/O
I/O
I/O, TDI
I/O, TCK
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O, TMS
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
R5
M6
N6
P6
W7
Y7
V8
P11 P3 P144 P160 P176 VCC* P205 VCC* VCC*
-
-
P38 P34 P48 P54 P58 G17 P70
P39 P35 P49 P55 P59 G18 P71
P12 P4
P1
P2
P1
P2
P1 GND* P2 GND* GND*
W8
P2
C3
P4
D4
B1
122
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VCC*
-
VCC* VCC*
P60 H16 P72
P61 H17 P73
P36 P50 P56 P62 H18 P74
P37 P51 P57 P63 J18 P75
R6
M7
R7
L7
N8
P8
Y8
U9
V10
Y10
Y11
W11
P14 P6
-
-
P15 P7
P16 P8
-
-
-
-
-
-
-
P3
P4
P5
P6
P7
-
-
-
-
P8
P9
P3
P4
P5
P6
P7
P8
P9
-
P3
P4
P5
P6
P7
P8
P9
-
C4
B3
C5
A2
B4
C6
A3
B5
B6
P5
P6
P7
P8
P9
P10
P11
P12
P13
B1
C2
E5
D3
C1
D2
G6
E4
D1
C2
D2
D3
E4
C1
D1
E3
E2
E1
125
128
131
134
137
140
143
146
149
-
152
155
158
161
-
164
167
170
173
176
179
-
-
-
P40 P38 P52 P58 P64 J17 P76
P41 P39 P53 P59 P65 J16 P77
P42 P40 P54 P60 P66 VCC* P78 VCC* VCC*
P43 P41 P55 P61 P67 GND* P79 GND* GND*
P44 P42 P56 P62 P68 K16 P80
P45 P43 P57 P63 P69 K17 P81
-
-
-
-
-
-
-
-
L8
P9
R9
N9
M9
L9
V11
U11
Y12
W12
V12
U12
307
310
313
316
319
322
-
325
328
331
334
-
337
340
343
346
349
352
355
358
361
364
-
-
-
-
-
-
-
P44 P58 P64 P70 K18 P82
P45 P59 P65 P71 L18 P83
P10 P10 GND* P14 GND* GND*
P11 P11
A4
A5
B7
P15
P16
P17
P18
-
P19
P20
P21
P22
P23
P24
F5
E1
F4
F3
G3
G2
G1
H3
-
-
-
-
-
-
-
-
-
P72 L17 P84
P73 L16 P85
P10 P12 P12
P11 P13 P13
P17 P9
P18 P10 P12 P14 P14
-
VCC*
-
VCC* VCC*
A6
P46 P46 P60 P66 P74 M18 P86 N10
P47 P47 P61 P67 P75 M17 P87 K9
Y15
V14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VCC*
C8
A7
B8
A8
VCC* VCC*
P15
P16
G4
G3
G2
G1
G5
H3
J2
J1
K2
K3
K1
L1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P62 P68 P76 N18 P88 R11 W15
P63 P69 P77 P18 P89 P11 Y16
P64 P70 P78 GND* P90 GND* GND*
P13 P15 P17
P11 P14 P16 P18
-
-
-
-
-
-
-
-
N17 P91 R12
R18 P92 L10
P71 P79 T18 P93 P12 W17
P72 P80 P17 P94 M11 Y18
Y17
V16
P19 P12 P15 P17 P19
P20 P13 P16 P18 P20
B9
C9
P21 P14 P17 P19 P21 GND* P25 GND* GND*
P22 P15 P18 P20 P22 VCC* P26 VCC* VCC*
P23 P16 P19 P21 P23 C10 P27
P24 P17 P20 P22 P24 B10 P28
-
P48 P48 P65 P73 P81 N16 P95 R13
P49 P49 P66 P74 P82 T17 P96 N12
U16
V17
H4
H5
J2
J1
J3
J4
L2
L3
L4
M1
M2
M3
182
185
188
191
194
197
-
200
203
206
209
-
I/O
I/O
I/O
I/O
-
-
-
-
P67 P75 P83 R17 P97 P13 W18
P68 P76 P84 P16 P98 K10
P50 P50 P69 P77 P85 U18 P99 R14
I/O, SGCK3 †, P51 P51 P70 P78 P86 T16 P100 N13 W19
GCK4 ††
-
-
-
-
-
P18 P21 P23 P25
A9
P29
Y19
V18
-
-
-
-
P22 P24 P26 A10 P30
-
-
-
-
-
-
P27 A11 P31
P28 C11 P32
-
VCC*
-
VCC* VCC*
GND
DONE
VCC
PROGRAM
I/O (D7)
P52 P52 P71 P79 P87 GND* P101 GND* GND*
P53 P53 P72 P80 P88 U17 P103 P14 Y20
P54 P54 P73 P81 P89 VCC* P106 VCC* VCC*
P55 P55 P74 P82 P90 V18 P108 M12 V19
-
-
-
P25 P19 P23 P25 P29 B11 P33
P26 P20 P24 P26 P30 A12 P34
K2
K3
J6
L1
P1
P2
R1
P3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P25 P27 P31 B12 P35
P26 P28 P32 A13 P36
P27 P29 P33 GND* P37 GND* GND*
-
P56 P56 P75 P83 P91 T15 P109 P15
U19
U18
367
370
I/O, PGCK3 †, P57 P57 P76 P84 P92 U16 P110 N14
GCK5 ††
-
-
-
-
-
-
-
-
B13 P38
A14 P39
P30 P34 A15 P40
P31 P35 C13 P41
L3
M1
K5
M2
T2
U1
T3
U2
212
215
218
221
I/O
I/O
I/O
I/O
I/O
-
-
-
-
P77 P85 P93 T14 P111 L11
P78 P86 P94 U15 P112 M13 V20
T17
373
376
6-124
DS006 (v. 1.7) October 4, 1999 - Product Specification
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
* Pads labelled GND* or VCC* are internally bonded to Ground or
VCC planes within the package. They have no direct connection to
any specific package pin.
† = E only
†† = XL only
PQ/H
Q
208
XC4010E/XL
Pad Name
PC
PQ
TQ
PQ
TQ
PG
BG
BG
Bndry
84 100†† 144†† 160 176†† 191†
225† 256†† Scan
I/O (D6)
I/O
I/O
I/O
I/O
I/O
GND
I/O
P58 P58 P79 P87 P95 V17 P113 J10
T19
T20
379
382
385
388
391
394
-
397
400
-
403
406
409
412
415
418
421
424
-
-
-
-
-
-
-
-
-
-
P59 P80 P88 P96 V16 P114 L12
-
-
-
-
-
-
-
-
-
-
-
-
P89 P97 T13 P115 M15 R18
P90 P98 U14 P116 L13
V15 P117 L14
V14 P118 K11
P81 P91 P99 GND* P119 GND* GND*
R19
R20
P18
-
-
-
-
Additional XC4010E/XL Package Pins
PQ/HQ208
Not Connected Pins
P82 P92 P100 U13 P120 K13
P83 P93 P101 V13 P121 K14
N19
N20
P1
P104
P206
P3
P105
P207
P51
P107
P208
P52
P155
-
P53
P156
-
P54
P157
-
P102
P158
-
I/O
VCC
I/O (D5)
I/O (CS0)
I/O
I/O
I/O
I/O
I/O (D4)
I/O
VCC
GND
I/O (D3)
I/O (RS)
I/O
I/O
I/O
I/O
I/O (D2)
I/O
VCC
I/O
I/O
GND
I/O
-
-
-
VCC*
-
VCC* VCC*
P59 P60 P84 P94 P102 U12 P122 K15 M17
P60 P61 P85 P95 P103 V12 P123 J12
5/27/97
M18
M20
L19
L18
L20
K20
K19
-
-
-
-
-
-
-
-
-
-
P104 T11 P124 J13
P105 U11 P125 J14
P62 P86 P96 P106 V11 P126 J15
P63 P87 P97 P107 V10 P127 J11
PG191
VCC Pins
P61 P64 P88 P98 P108 U10 P128 H13
P62 P65 P89 P99 P109 T10 P129 H14
P63 P66 P90 P100 P110 VCC* P130 VCC* VCC*
P64 P67 P91 P101 P111 GND* P131 GND* GND*
P65 P68 P92 P102 P112 T9 P132 H12
P66 P69 P93 P103 P113 U9 P133 H11
D3
R15
D10
-
D16
-
J4
-
J15
-
R4
-
R10
-
GND Pins
-
C7
K4
T7
C12
K15
T12
D4
M3
-
D9
M16
-
D15
R3
-
G3
R9
-
G16
R16
-
K18
K17
J20
J19
J18
J17
427
430
433
436
439
442
445
448
-
451
454
-
457
460
463
466
469
472
-
-
-
-
P70 P94 P104 P114 V9 P134 G14
-
-
-
P95 P105 P115 V8 P135 G15
5/27/97
-
-
-
-
P116 U8 P136 G13
P117 T8 P137 G12
P67 P71 P96 P106 P118 V7 P138 G11 H19
P68 P72 P97 P107 P119 U7 P139 F15 H18
VCC* VCC*
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VCC*
-
P98 P108 P120 V6 P140 F14
P99 P109 P121 U6 P141 F13
P100 P110 P122 GND* P142 GND* GND*
G19
F20
-
-
-
-
-
-
-
-
V5 P143 E13
V4 P144 D15
P111 P123 U5 P145 F11
P112 P124 T6 P146 D14
D20
E18
D19
C20
E17
D18
I/O
I/O
I/O
I/O (D1)
I/O (RCLK,
RDY/BUSY)
I/O
P69 P73 P101 P113 P125 V3 P147 E12
P70 P74 P102 P114 P126 V2 P148 C15
-
-
-
-
P103 P115 P127 U4 P149 D13
P104 P116 P128 T5 P150 C14
I/O (D0, DIN) P71 P75 P105 P117 P129 U3 P151 F10
C19
B20
C18
B19
475
478
481
484
I/O
I/O, SGCK4 †, P72 P76 P106 P118 P130 T4 P152 B15
GCK6 ††
(DOUT)
CCLK
VCC
O, TDO
GND
P73 P77 P107 P119 P131 V1 P153 C13
A20
-
-
0
-
P74 P78 P108 P120 P132 VCC* P154 VCC* VCC*
P75 P79 P109 P121 P133 U2 P159 A15 A19
P76 P80 P110 P122 P134 GND* P160 GND* GND*
I/O (A0, WS) P77 P81 P111 P123 P135 T3 P161 A14
I/O, PGCK4 †, P78 P82 P112 P124 P136 U1 P162 B13
GCK7 †† (A1)
B18
B17
2
5
I/O
I/O
-
-
-
-
P113 P125 P137 P3 P163 E11
P114 P126 P138 R2 P164 C12
C17
D16
A18
A17
A16
C15
B15
A15
8
11
14
17
20
23
26
29
-
I/O (CS1, A2) P79 P83 P115 P127 P139 T2 P165 A13
I/O (A3)
I/O
I/O
I/O
I/O
GND
I/O
I/O
P80 P84 P116 P128 P140 N3 P166 B12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P117 P129 P141 P2 P167 A12
-
-
-
P130 P142 T1 P168 C11
-
-
-
-
R1 P169 B11
N2 P170 E10
P118 P131 P143 GND* P171 GND* GND*
P119 P132 P144 P1 P172 A11
P120 P133 P145 N1 P173 D10
B14
A14
32
35
-
VCC
-
-
-
VCC*
-
VCC* VCC*
I/O (A4)
I/O (A5)
I/O
P81 P85 P121 P134 P146 M2 P174 A10
P82 P86 P122 P135 P147 M1 P175 D9
C12
B12
A12
B11
C11
A11
A10
B10
38
41
44
47
50
53
56
59
-
-
-
-
-
-
-
-
-
-
P148 L3 P176 C9
I/O
P136 P149 L2 P177 B9
I/O (A21)††
I/O (A20)††
I/O (A6)
I/O (A7)
GND
P87 P123 P137 P150 L1 P178 A9
P88 P124 P138 P151 K1 P179 E9
P83 P89 P125 P139 P152 K2 P180 C8
P84 P90 P126 P140 P153 K3 P181 B8
P1 P91 P127 P141 P154 GND* P182 GND* GND*
6/19/97
DS006 (v. 1.7) October 4, 1999 - Product Specification
6-125
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
BG225
VCC Pins
VCC Pins
C14
F1
P4
D6
F4
P17
U10
D7
D11
G4
R2
U15
D14
G17
R4
D15
K4
R17
W20
E20
L17
U6
-
B2
R15
B14
-
D8
-
H1
H15
-
R1
-
R8
-
F17
P19
U14
-
GND Pins
F8
U7
V7
A1
H2
J8
A8
H6
J9
D12
H7
K8
G7
H9
-
G8
H10
-
G9
J7
-
GND Pins
H8
M8
A1
H4
U13
B7
H17
U17
D4
N3
W14
D8
N4
-
D13
N17
-
D17
U4
-
G20
U8
-
Not Connected Pins
A3
E3
F12
L6
P5
B10
E14
G10
L15
P7
C4
E15
J5
M10
P10
C6
F1
K1
M14
R10
C10
D11
F7
K12
N11
-
E2
F9
L2
N15
-
Not Connected Pins
F2
K4
N7
-
A6
C8
F3
A7
C13
F18
J4
R3
W6
Y13
A13
B13
D5
B16
D12
H1
C4
E19
H2
N2
V9
C7
F2
H20
N18
V13
Y6
C16
F19
M4
G18
M19
T18
W10
-
J3
N1
6/16/97
P20
V15
Y9
T1
W9
Y14
U20
W13
-
W16
-
-
5/27/97
BG256
XC4013E/XL Device Pinout Tables
The following table may contain pinout information for unsupported device/package combinations. Please see the availability
charts elsewhere in the XC4000 Series data sheet for availability information.
XC4013E
/XL
Pad Name
I/O
I/O
I/O
GND
I/O
I/O
I/O, TMS
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
PQ/H
Q
240
P11
P12
P13
XC4013E
/XL
Pad Name
VCC
I/O (A8)
I/O (A9)
I/O
(A19) ††
I/O
(A18) ††
I/O
I/O
I/O (A10)
I/O (A11)
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O (A12)
I/O (A13)
I/O
I/O
I/O
I/O
I/O (A14)
I/O,
SGCK1 †,
GCK8 ††
(A15)
VCC
GND
PQ/H
Q
240
HT
PQ
HT
PQ/HQ PG
BG
BG
Bndry
HT
PQ
HT
PQ/HQ PG
208 223† 225†
BG
BG
Bndry
144†† 160 176††
208
223† 225†
256†† Scan
144†† 160 176††
256†† Scan
-
-
-
-
-
-
-
-
-
P13
-
-
B6
D5
D6
D1
E3
E2
E1
F3
F2
GND*
G3
G2
G1
H3
VCC*
H2
H1
J2
J1
K2
K3
K1
L1
GND*
VCC*
L2
L3
L4
M1
M2
M3
N1
N2
VCC*
P1
P2
R1
P3
GND*
T1
R3
T2
U1
T3
U2
V1
T4
U3
173
176
179
-
182
185
188
191
-
194
197
200
203
206
209
212
215
-
P128 P142 P155
P129 P143 P156
P130 P144 P157
P131 P145 P158
P183 VCC* VCC* P212 VCC*
-
P184
P185
P186
J3
J2
J1
E8
B7
A7
P213
P214
P215
C10
D10
A9
74
77
80
P8
P9
P10
P11
P12
-
-
-
-
-
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
-
P10
P11
P12
P13
P14
-
-
-
-
-
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
-
P10
P11
P12
P13
P14
-
P14 GND* GND* P14
P15
P16
P17
P18
-
A4
A5
B7
A6
F5
E1
F4
F3
P15
P16
P17
P18
P132 P146 P159
P187
H1
C7
P216
B9
83
-
-
-
-
P160
P161
P188
P189
P190
P191
-
H2
H3
G1
G2
D7
E7
A6
B6
P217
P218
P220
P221
C9
D9
A8
B8
86
89
92
95
-
VCC* VCC* P19
-
-
-
-
D7
D8
C8
A7
B8
A8
B9
C9
F2
F1
P20
P21
P23
P24
P25
P26
P27
P28
P133 P147 P162
P134 P148 P163
-
-
-
P135 P149 P164
P136 P150 P165
P137 P151 P166
-
-
-
-
P138 P154 P170
P139 P155 P171
-
-
P140 P156 P172
P141 P157 P173
P142 P158 P174
P143 P159 P175
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
-
P19
P20
P21
P22
P23
P24
G4
G3
G2
G1
G5
H3
-
-
-
-
-
-
VCC* VCC* P222 VCC*
-
-
H4
G4
F1
E1
C6
F7
A5
B5
P223
P224
P225
P226
A6
C7
B6
A5
98
101
104
107
-
P192
P193
P194 GND* GND* P227 GND*
P25 GND* GND* P29
-
-
-
P195
P196
P197
P198
P199
P200
-
F2
D1
C1
E2
F3
D2
F4
E4
B1
E3
C2
B2
D6
C5
A4
E6
B4
D5
A3
C4
B3
F6
A2
C3
P228
P229
P230
P231
P232
P233
P234
P235
P236
P237
P238
P239
C6
B5
A4
C5
B4
A3
D5
C4
B3
B2
A2
C3
110
113
116
119
122
125
128
131
134
137
140
143
P26
P27
P28
P29
P30
P31
P32
-
VCC* VCC* P30
-
P167
C10
B10
A9
A10
A11
C11
D11
D12
H4
H5
J2
J1
J3
J4
J5
K1
P31
P32
P33
P34
P35
P36
P38
P39
218
221
224
227
230
233
236
239
-
242
245
248
251
-
254
257
260
263
266
269
272
275
278
281
284
P152 P168
P153 P169
-
-
-
-
-
-
-
-
-
-
-
-
-
P201
P202
P203
P204
-
-
-
-
VCC* VCC* P40
P23
P24
P25
P26
P27
-
-
-
-
-
P25
P26
P27
P28
P29
-
-
-
-
P30
P31
P32
P33
P34
P35
P36
P29
P30
P31
P32
P33
-
-
-
-
P34
P35
P36
P37
P38
P39
P40
P33
P34
P35
P36
B11
A12
B12
A13
K2
K3
J6
L1
P41
P42
P43
P44
P144 P160 P176
P1
P2
P205 VCC* VCC* P240 VCC*
-
-
P37 GND* GND* P45
P1
P2
P1
P2
P2
P4
GND* GND*
C3
P1
P2
GND*
B1
-
-
D13
D14
B13
A14
A15
C13
B14
A16
B15
C14
A17
L2
K4
L3
M1
K5
M2
L4
N1
M3
N2
K6
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55
P56
I/O,
D4
146
PGCK1 †,
GCK1 ††
(A16)
I/O (A17)
I/O
P38
P39
P40
P41
P42
P43
P44
P45
P46
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P3
P4
P5
P6
P7
-
P3
P4
P5
P6
P7
P8
P9
-
P3
P4
P5
P6
P7
P8
P9
-
P5
P6
P7
P8
P9
P10
P11
P12
C4
B3
C5
A2
B4
C6
A3
B5
B1
C2
E5
D3
C1
D2
G6
E4
P3
P4
P5
P6
P7
P8
P9
P10
C2
D2
D3
E4
C1
D1
E3
E2
149
152
155
158
161
164
167
170
-
P28
P29
P30
P31
P32
I/O
I/O, TDI
I/O, TCK
I/O
I/O
I/O
V2
W1
-
-
6-126
DS006 (v. 1.7) October 4, 1999 - Product Specification
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4013E
/XL
Pad Name
PQ/H
Q
240
XC4013E
/XL
Pad Name
PQ/H
Q
240
HT
PQ
HT
PQ/HQ PG
BG
BG
Bndry
HT
PQ
HT
PQ/HQ PG
BG
BG
Bndry
144†† 160 176††
208
223† 225†
256†† Scan
144†† 160 176††
208
223† 225†
256†† Scan
I/O,
SGCK2 †,
GCK2 ††
O (M1)
GND
I (M0)
VCC
I (M2)
I/O,
PGCK2 †,
GCK3 ††
I/O (HDC)
I/O
I/O
I/O
I/O (LDC)
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O (INIT)
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O,
SGCK3 †,
GCK4 ††
GND
DONE
VCC
PRO-
GRAM
I/O (D7)
I/O,
PGCK3 †,
GCK5 ††
P33
P37
P41
P47
B16
P1
N3
P57
V3
287
I/O
I/O
I/O
I/O
I/O (D6)
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
P77
P78
-
P85
P86
-
P93
P94
-
P111
P112
-
T14
U15 M13 P126
R14 N15 P127
R13 M14 P128
L11 P125
T17
V20
U20
T18
T19
T20
R18
R19
R20
P18
445
448
451
454
457
460
463
466
469
472
-
475
478
481
484
-
487
490
493
496
499
502
505
508
-
P34
P35
P36
P37
P38
P39
P38
P39
P40
P41
P42
P43
P42
P43
P44
P45
P46
P47
P48
C15
P58
W2
GND*
Y1
VCC*
W3
290
-
293
-
294
295
-
-
-
-
P49 GND* GND* P59
P79
P80
-
-
-
P87
P88
P89
P90
-
P95
P96
P97
P98
-
P113
P114
P115
P116
P117
P118
V17
V16
T13
U14
V15
V14
J10
P129
P50
P55
P56
P57
A18
P2
P60
L12 P130
M15 P131
L13 P132
L14 P133
K11 P134
VCC* VCC* P61
C16
B17
M4
R2
P62
P63
Y2
-
-
-
P81
-
-
P82
P83
-
P84
P85
-
P91
-
-
P92 P100
P93 P101
-
P94 P102
P95 P103
-
-
P96 P106
P97 P107
P98 P108
P99 P109
P99
-
-
P119 GND* GND* P135 GND*
-
-
P120
P121
-
P122
P123
P124
P125
P126
P127
P128
P129
P40
P41
P42
P43
P44
-
-
-
-
-
P44
P45
P46
P47
P48
P49
P50
-
P48
P49
P50
P51
P52
P53
P54
-
P58
P59
P60
P61
P62
P63
P64
P65
P66
-
E16
C17
D17
B18
E17
F16
C18
D18
F17
E15
F15
P3
L5
P64
P65
P66
P67
P68
P69
P70
P71
P72
P73
P74
W4
V4
U5
Y3
Y4
V5
W5
Y5
V6
W6
Y6
GND*
W7
Y7
V8
W8
VCC*
Y8
U9
298
301
304
307
310
313
316
319
322
325
328
-
331
334
337
340
-
343
346
349
352
355
358
361
364
-
R12
R11
U13
V13
L15 P136
K12 P137
K13 P138
K14 P139
P20
N18
N19
N20
N4
R3
P4
K7
M5
R4
N5
P5
L6
I/O
VCC
I/O (D5)
I/O (CS0)
I/O
I/O
I/O
I/O
I/O (D4)
I/O
VCC
GND
I/O (D3)
I/O (RS)
I/O
I/O
I/O
I/O
I/O (D2)
I/O
VCC
I/O
I/O
I/O
I/O
-
VCC* VCC* P140 VCC*
U12
V12
T11
U11
V11
V10
U10
T10
K15 P141
M17
M18
M20
L19
L18
L20
K20
K19
J12
J13
J14
J15
J11
P142
P144
P145
P146
P147
P104
P105
-
-
-
-
-
-
-
P86
P87
P88
P89
-
-
P45
P46
P47
P48
P49
-
-
-
-
-
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
-
P51
P52
P53
P54
P55
-
-
-
-
-
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
-
P55
P56
P57
P58
P59
-
P60
P61
-
P67 GND* GND* P75
H13 P148
H14 P149
P68
P69
P70
P71
-
P72
P73
-
E18
F18
G17
G18
R5
M6
N6
P6
P76
P77
P78
P79
P90 P100 P110
P91 P101 P111
P92 P102 P112
P93 P103 P113
P94 P104 P114
P95 P105 P115
P130 VCC* VCC* P150 VCC*
P131 GND* GND* P151 GND*
-
P132
P133
P134
P135
P136
P137
P138
P139
-
T9
U9
V9
V8
U8
T8
V7
U7
H12 P152
H11 P153
G14 P154
G15 P155
G13 P156
G12 P157
G11 P159
F15 P160
K18
K17
J20
J19
J18
J17
H19
H18
511
514
517
520
523
526
529
532
-
535
538
541
544
-
547
550
553
556
559
562
565
568
VCC* VCC* P80
H16
H17
G15
H15
H18
J18
J17
J16
R6
M7
N7
P7
R7
L7
P81
P82
P84
P85
P86
P87
P88
P89
Y9
-
-
-
-
P116
P117
-
-
W10
V10
Y10
Y11
W11
VCC*
GND*
V11
U11
Y12
W12
V12
U12
V13
Y14
P62
P63
P64
P65
P66
P67
P68
P69
P70
P71
P72
P73
-
P74
P75
P76
P77
P78
P96 P106 P118
P97 P107 P119
-
P98 P108 P120
P99 P109 P121
-
-
N8
P8
-
-
VCC* VCC* P161 VCC*
P140
P141
-
V6
U6
R8
R7
F14 P162
F13 P163
G10 P164
E15 P165
G19
F20
G18
F19
VCC* VCC* P90
P79 GND* GND* P91
-
-
-
-
-
P80
P81
P82
P83
P84
P85
-
K16
K17
K18
L18
L17
L16
L15
M15
L8
P9
R9
N9
M9
L9
P92
P93
P94
P95
P96
P97
P99
367
370
373
376
379
382
385
388
-
391
394
397
400
-
403
406
409
412
415
418
421
424
427
430
433
436
-
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O (D1)
P100 P110 P122
P142 GND* GND* P166 GND*
-
-
P143
P144
P145
P146
P147
P148
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R6
R5
V5
V4
U5
T6
V3
V2
E14 P167
F12 P168
E13 P169
D15 P170
F11 P171
D14 P172
E12 P173
C15 P174
F18
E19
D20
E18
D19
C20
E17
D18
-
-
-
-
-
-
-
-
R10
P10 P100
P111 P123
P112 P124
-
-
-
-
VCC* VCC* P101 VCC*
M18 N10 P102
M17
N18
P18
P101 P113 P125
P60
P61
P62
P63
P64
-
-
-
-
-
P66
P67
P68
P69
P70
-
-
-
-
P71
P72
P73
P74
P75
P76
P77
P78
P74
P75
P76
P77
P78
-
-
-
-
P79
P80
P81
P82
P83
P84
P85
P86
P86
P87
P88
P89
Y15
V14
W15
Y16
I/O (RCLK, P102 P114 P126
RDY/BUS
Y)
I/O
I/O
I/O (D0,
DIN)
K9
P103
R11 P104
P11 P105
P103 P115 P127
P104 P116 P128
P105 P117 P129
P149
P150
P151
U4
T5
U3
D13 P175
C14 P176
F10 P177
C19
B20
C18
571
574
577
P90 GND* GND* P106 GND*
-
-
N15 M10 P107
V15
W16
Y17
V16
W17
Y18
U16
V17
W18
Y19
V18
W19
P15
N17
R18
T18
P17
N16
T17
R17
P16
U18
T16
N11 P108
R12 P109
L10 P110
P12 P111
M11 P112
R13 P113
N12 P114
P13 P115
K10 P116
R14 P117
N13 P118
P91
P92
P93
P94
P95
P96
P97
P98
P99
P100
I/O,
P106 P118 P130
P152
T4
B15 P178
B19
580
SGCK4 †,
GCK6 ††
(DOUT)
CCLK
VCC
O, TDO
GND
I/O (A0,
WS)
-
P107 P119 P131
P108 P120 P132
P109 P121 P133
P110 P122 P134
P111 P123 P135
P153
V1
C13 P179
A20
-
-
0
-
P65
P66
P67
P68
P69
P70
P154 VCC* VCC* P180 VCC*
P159 U2 A15 P181 A19
P160 GND* GND* P182 GND*
P161
T3
A14 P183
B18
2
I/O,
P112 P124 P136
P162
U1
B13 P184
B17
5
PGCK4 †,
GCK7 ††
(A1)
I/O
I/O
I/O (CS1,
A2)
I/O (A3)
I/O
P71
P72
P73
P74
P79
P80
P81
P82
P87
P88
P89
P90
P101 GND* GND* P119 GND*
P103 U17 P14 P120 Y20
P106 VCC* VCC* P121 VCC*
-
-
-
-
P113 P125 P137
P114 P126 P138
P115 P127 P139
P163
P164
P165
P3
R2
T2
E11 P185
C12 P186
A13 P187
C17
D16
A18
8
11
14
P108
V18
M12 P122
V19
P75
P76
P83
P84
P91
P92
P109
P110
T15
U16
P15 P123
N14 P124
U19
U18
439
442
P116 P128 P140
-
-
P166
-
-
N3
P4
N4
B12 P188
A17
C16
B16
17
20
23
-
-
-
-
F9
P189
I/O
D11 P190
DS006 (v. 1.7) October 4, 1999 - Product Specification
6-127
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4013E
/XL
Pad Name
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O (A4)
I/O (A5)
I/O
I/O
I/O
(A21) ††
I/O
PQ/H
Q
240
HT
PQ
HT
PQ/HQ PG
BG
BG
Bndry
144†† 160 176††
208
223† 225†
256†† Scan
BG225
B2
VCC Pins
D8
R15
GND Pins
D12
H2
H10
M8
P117 P129 P141
P167
P168
P169
P170
P2
T1
R1
N2
A12 P191
C11 P192
B11 P193
E10 P194
A16
C15
B15
A15
26
29
32
35
-
38
41
44
47
-
50
53
56
59
62
-
-
-
P130 P142
-
-
B14
R8
H1
-
H15
-
-
-
R1
P118 P131 P143
P119 P132 P144
P120 P133 P145
-
-
-
P121 P134 P146
P122 P135 P147
-
-
P171 GND* GND* P196 GND*
A1
G8
H8
J9
A8
G9
H9
K8
F8
H6
J7
-
G7
H7
J8
-
P172
P173
-
P1
N1
M4
L4
A11 P197
D10 P198
C10 P199
B10 P200
B14
A14
C13
B13
-
-
-
-
-
-
-
5/5/97
-
VCC* VCC* P201 VCC*
P174
P175
P176
P177
P178
M2
M1
L3
L2
L1
A10 P202
C12
B12
A12
B11
C11
The BG225 package pins in this table are bonded to an internal
Ground plane on the XC4013E die. They must all be externally con-
nected to Ground.
D9
C9
B9
A9
P203
P205
P206
P207
-
P148
P136 P149
P123 P137 P150
PQ/HQ240
GND Pins
P124 P138 P151
P179
K1
E9
P208
A11
65
(A20) ††
P22‡
P204‡
P37‡
P219‡
P83‡
-
P98‡
-
P143‡
-
P158‡
-
I/O (A6)
I/O (A7)
GND
P125 P139 P152
P126 P140 P153
P127 P141 P154
P180
P181
K2
K3
C8
B8
P209
P210
A10
B10
68
71
-
Not Connected Pins
P182 GND* GND* P211 GND*
P195
6/9/97
-
-
-
-
-
6/9/97
* Pads labelled GND* or VCC* are internally bonded to Ground or
VCC planes within the package. They have no direct connection to
any specific package pin.
‡ Pins marked with this symbol are used for Ground connections on
some revisions of the device. These pins may not physically con-
nect to anything on the current device revision. However, they
should be externally connected to Ground, if possible.
† = E only, †† = XL only
Additional XC4013E/XL Package Pins
BG256
VCC Pins
PQ/HQ208
C14
E20
K4
R4
U15
D6
F1
L17
R17
V7
D7
F4
P4
U6
W20
D11
F17
P17
U7
-
D14
G4
P19
U10
-
D15
G17
R2
U14
-
Not Connected Pins
P1
P102
P157
P3
P104
P158
P51
P105
P206
P52
P107
P207
P53
P155
P208
P54
P156
-
5/5/97
GND Pins
A1
G20
U4
B7
H4
U8
D4
H17
U13
D8
N3
U17
D13
N4
W14
D17
N17
-
PG223
VCC Pins
D16
-
Not Connected Pins
D3
R10
D10
R15
J4
-
J15
-
R4
-
A7
J4
Y13
A13
M4
-
C8
M19
-
D12
V9
-
H20
W9
-
J3
W13
-
GND Pins
C7
G16
R9
C12
K4
R16
D4
K15
T7
D9
M3
T12
D15
M16
-
G3
R3
-
6/4/97
5/5/97
6-128
DS006 (v. 1.7) October 4, 1999 - Product Specification
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4020E/XL Device Pinout Tables
The following table may contain pinout information for unsupported device/package combinations. Please see the availability
charts elsewhere in the XC4000 Series data sheet for availability information.
XC4020E/XL
Pad Name
HT
PQ
HT
HQ208†
PG
HQ240†
BG
Bndry
XC4020E/XL
Pad Name
HT
PQ
HT
HQ208†
PG
HQ240†
BG
Bndry
144†† 160†† 176†† PQ208†† 223† PQ240†† 256†† Scan
144†† 160†† 176†† PQ208†† 223† PQ240†† 256†† Scan
I/O
P24
P25
P26
P27
-
P26
P27
P28
P29
-
P30
P31
P32
P33
-
P34
P35
P36
P37
-
A12
B12
A13
GND*
D13
D14
B13
A14
A15
C13
B14
A16
B15
C14
A17
B16
P42
P43
P44
P45
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55
P56
P57
P2
R1
P3
287
290
293
-
VCC
P128 P142 P155
P129 P143 P156
P130 P144 P157
P131 P145 P158
P132 P146 P159
P183
P184
P185
P186
P187
P188
P189
P190
P191
-
VCC*
J3
P212
P213
P214
P215
P216
P217
P218
P220
P221
-
VCC*
C10
D10
A9
-
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O (A8)
I/O (A9)
I/O (A19) ††
I/O (A18) ††
I/O
86
J2
89
GND*
T1
J1
92
296
299
302
305
308
311
320
323
326
329
332
335
H1
H2
H3
G1
G2
-
B9
95
-
-
-
-
R3
T2
-
-
-
-
P160
P161
C9
98
-
-
-
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
I/O
D9
101
104
107
110
113
-
-
-
-
U1
T3
I/O (A10)
I/O (A11)
I/O
P133 P147 P162
P134 P148 P163
A8
-
P30
P31
P32
P33
P34
P35
P36
P37
P34
P35
P36
P37
P38
P39
P40
P41
B8
-
U2
V1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C8
P28
P29
P30
P31
P32
P33
I/O
-
-
-
A7
T4
VCC
-
VCC*
H4
G4
F1
P222
P223
P224
P225
P226
P227
P228
P229
P230
P231
P232
P233
P234
P235
P236
P237
P238
P239
VCC*
A6
U3
V2
I/O
-
116
119
122
125
-
I/O
-
C7
W1
V3
I/O
P135 P149 P164
P136 P150 P165
P137 P151 P166
P192
P193
P194
P195
P196
P197
P198
P199
P200
-
B6
I/O, SGCK2 †,
GCK2 ††
I/O
E1
GND*
F2
A5
GND
I/O
GND*
C6
O (M1)
GND
P34
P35
P36
P37
P38
P39
P38
P39
P40
P41
P42
P43
P42
P43
P44
P45
P46
P47
P48
P49
P50
P55
P56
P57
C15
GND*
A18
P58
P59
P60
P61
P62
P63
W2
GND*
Y1
338
-
-
-
-
-
-
-
-
128
131
134
137
140
143
152
155
158
161
164
167
I/O
P167
D1
C1
E2
F3
B5
I (M0)
VCC
341
-
I/O
P152 P168
P153 P169
A4
VCC*
C16
VCC*
W3
I/O
C5
I (M2)
342
343
I/O (A12)
I/O (A13)
I/O
P138 P154 P170
P139 P155 P171
B4
I/O PGCK2 †,
GCK3 ††
B17
Y2
D2
F4
A3
-
-
-
-
-
-
D5
I/O (HDC)
I/O
P40
P44
P45
P46
P47
P48
P49
P50
-
P48
P49
P50
P51
P52
P53
P54
-
P58
P59
P60
P61
P62
P63
P64
P65
P66
-
E16
C17
D17
B18
E17
F16
C18
D18
F17
E15
F15
GND*
E18
F18
G17
G18
VCC*
H16
H17
-
P64
P65
P66
P67
P68
P69
P70
P71
P72
P73
P74
P75
P76
P77
P78
P79
P80
P81
P82
-
W4
V4
346
349
352
355
358
367
370
373
376
379
382
-
I/O
-
E4
B1
E3
C2
B2
C4
P41
I/O
P140 P156 P172
P141 P157 P173
P142 P158 P174
P143 P159 P175
P201
P202
P203
P204
B3
I/O
P42
U5
I/O
B2
I/O
P43
Y3
I/O (A14)
A2
I/O (LDC)
I/O
P44
Y4
I/O, SGCK1 †,
GCK8 †† (A15)
C3
-
V5
I/O
-
W5
VCC
GND
P144 P160 P176
P205
P2
VCC*
GND*
C3
P240
P1
VCC*
GND*
B1
-
-
I/O
-
Y5
P1
P2
P1
P2
P1
P2
I/O
-
-
-
V6
I/O, PGCK1 †,
GCK1 †† (A16)
P4
P2
170
I/O
-
-
-
W6
I/O
-
-
-
-
Y6
I/O (A17)
I/O
P3
P3
P4
P5
P6
P7
P8
P9
-
P3
P4
P5
P6
P7
P8
P9
-
P5
P6
P7
P8
P9
P10
P11
P12
P13
-
C4
B3
P3
P4
C2
D2
173
176
179
182
185
194
197
200
203
206
209
-
GND
I/O
P45
P51
P52
P53
P54
P55
-
P55
P56
P57
P58
P59
-
P67
P68
P69
P70
P71
-
GND*
W7
P4
P46
385
388
391
394
-
I/O
P5
C5
P5
D3
I/O
P47
Y7
I/O, TDI
I/O, TCK
I/O
P6
A2
P6
E4
I/O
P48
V8
P7
B4
P7
C1
I/O
P49
W8
-
C6
P8
D1
VCC
I/O
-
VCC*
Y8
I/O
-
A3
P9
E3
-
-
P60
P61
-
P72
P73
-
397
400
403
406
409
412
415
418
421
424
-
I/O
-
B5
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
-
E2
I/O
-
-
U9
I/O
-
-
-
B6
E1
I/O
-
-
V9
I/O
-
-
-
-
D5
F3
I/O
-
-
-
-
-
-
W9
I/O
-
-
-
D6
F2
I/O
-
-
-
-
G15
H15
H18
J18
J17
J16
VCC*
GND*
K16
K17
K18
L18
L17
L16
-
P84
P85
P86
P87
P88
P89
P90
P91
P92
P93
P94
P95
P96
P97
-
Y9
GND
I/O
P8
P9
P10
P11
P12
-
P10
P11
P12
P13
P14
-
P10
P11
P12
P13
P14
-
P14
P15
P16
P17
P18
-
GND*
A4
GND*
G3
G2
G1
H3
I/O
-
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
-
-
-
-
W10
V10
Y10
Y11
W11
VCC*
GND*
V11
U11
Y12
W12
V12
U12
Y13
W13
V13
Y14
VCC*
Y15
V14
W15
Y16
GND*
V15
W16
Y17
V16
W17
Y18
212
215
218
221
-
I/O
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
-
P62
P63
P64
P65
P66
P67
P68
P69
P70
P71
P72
P73
-
P74
P75
P76
P77
P78
P79
P80
P81
P82
P83
P84
P85
-
I/O
A5
I/O
I/O, TMS
I/O
B7
I/O
A6
I/O (INIT)
VCC
GND
I/O
VCC
I/O
VCC*
D7
VCC*
H2
-
-
-
-
224
227
230
233
236
239
242
245
248
251
-
-
I/O
-
-
-
-
D8
H1
427
430
433
436
439
442
445
448
451
454
-
I/O
-
-
-
-
-
J4
I/O
I/O
-
-
-
-
-
-
J3
I/O
I/O
-
-
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
-
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
-
C8
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
-
J2
I/O
I/O
-
-
A7
J1
I/O
I/O
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
-
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
-
B8
K2
I/O
-
-
I/O
A8
K3
I/O
-
-
I/O
B9
K1
I/O
-
-
-
-
-
-
I/O
C9
L1
I/O
-
-
-
-
L15
M15
VCC*
M18
M17
N18
P18
GND*
N15
P15
N17
R18
T18
P17
P99
P100
P101
P102
P103
P104
P105
P106
P107
P108
P109
P110
P111
P112
GND
VCC
I/O
GND*
VCC*
C10
B10
A9
GND*
VCC*
L2
I/O
-
-
-
-
-
VCC
I/O
-
-
-
-
254
257
260
263
266
269
272
278
281
-
P60
P61
P62
P63
P64
-
P66
P67
P68
P69
P70
-
P74
P75
P76
P77
P78
-
P86
P87
P88
P89
P90
-
457
460
463
466
-
I/O
L3
I/O
I/O
L4
I/O
I/O
A10
A11
C11
-
M1
M2
M3
M4
N1
I/O
I/O
GND
I/O
I/O
-
-
469
472
475
478
481
484
I/O
-
-
I/O
-
-
-
-
I/O
-
-
-
-
D11
D12
VCC*
B11
P38
P39
P40
P41
I/O
-
-
-
P91
P92
P93
P94
I/O
-
-
-
-
N2
I/O
-
-
-
VCC
I/O
-
-
-
-
VCC*
P1
I/O
-
P71
P72
P79
P80
P23
P25
P29
P33
284
I/O
-
DS006 (v. 1.7) October 4, 1999 - Product Specification
6-129
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4020E/XL
Pad Name
HT
PQ
HT
HQ208†
PG
HQ240†
BG
Bndry
XC4020E/XL
Pad Name
HT
PQ
HT
HQ208†
PG
HQ240†
BG
Bndry
144†† 160†† 176†† PQ208†† 223† PQ240†† 256†† Scan
144†† 160†† 176†† PQ208†† 223† PQ240†† 256†† Scan
I/O
P65
P66
P67
P68
P69
P70
P73
P74
P75
P76
P77
P78
P81
P82
P83
P84
P85
P86
P95
P96
P97
P98
P99
P100
N16
T17
R17
P16
U18
T16
P113
P114
P115
P116
P117
P118
U16
V17
W18
Y19
V18
W19
493
496
499
502
505
508
I/O
-
-
-
-
-
-
-
P4
N4
P2
P189
P190
P191
P192
P193
P194
P196
P197
P198
P199
P200
P201
-
C16
B16
A16
C15
B15
A15
GND*
B14
A14
C13
B13
VCC*
A13
D12
C12
B12
A12
B11
C11
A11
A10
B10
GND*
26
29
32
35
38
41
-
I/O
I/O
I/O
I/O
I/O
-
I/O
P117 P129 P141
P167
P168
P169
P170
P171
P172
P173
-
I/O
-
-
-
P130 P142
T1
I/O
-
-
-
-
R1
N2
GND*
P1
I/O, SGCK3 †,
GCK4 ††
I/O
GND
I/O
P118 P131 P143
P119 P132 P144
P120 P133 P145
GND
P71
P72
P73
P74
P75
P76
P79
P80
P81
P82
P83
P84
P87
P88
P89
P90
P91
P92
P101
P103
P106
P108
P109
P110
GND*
U17
P119
P120
P121
P122
P123
P124
GND*
Y20
-
44
47
50
53
-
DONE
-
-
I/O
N1
M4
L4
VCC
VCC*
V18
VCC*
V19
I/O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PROGRAM
I/O (D7)
-
I/O
-
T15
U19
511
514
VCC
I/O
-
VCC*
-
I/O, PGCK3 †,
GCK5 ††
U16
U18
-
56
59
62
65
68
71
74
77
80
83
-
I/O
-
-
-
I/O
P77
P85
P86
-
P93
P94
-
P111
P112
-
T14
U15
R14
R13
V17
V16
T13
U14
V15
V14
GND*
R12
R11
U13
V13
VCC*
U12
V12
-
P125
P126
P127
P128
P129
P130
P131
P132
P133
P134
P135
P136
P137
P138
P139
P140
P141
P142
-
T17
V20
U20
T18
517
520
523
526
535
538
541
544
547
550
-
I/O (A4)
I/O (A5)
I/O
P121 P134 P146
P122 P135 P147
P174
P175
P176
P177
P178
P179
P180
P181
P182
M2
M1
L3
P202
P203
P205
P206
P207
P208
P209
P210
P211
I/O
P78
I/O
-
-
-
-
P148
I/O
-
P79
P80
-
-
-
-
I/O
P136 P149
L2
I/O (D6)
I/O
P87
P88
P89
P90
-
P95
P96
P97
P98
-
P113
P114
P115
P116
P117
P118
P119
-
T19
I/O (A21) ††
I/O (A20) ††
I/O (A6)
I/O (A7)
GND
6/24/97
P123 P137 P150
P124 P138 P151
P125 P139 P152
P126 P140 P153
P127 P141 P154
L1
T20
K1
I/O
R18
R19
R20
P18
GND*
P20
N18
N19
N20
VCC*
M17
M18
M19
M20
L19
K2
I/O
-
K3
I/O
-
GND*
I/O
-
-
-
GND
I/O
P81
-
P91
-
P99
-
† = E only
†† = XL only
553
556
559
562
-
I/O
-
-
-
-
I/O
P82
P83
-
P92 P100
P93 P101
P120
P121
-
I/O
Additional XC4020E/XL Package Pins
PQ/HQ208
VCC
I/O (D5)
I/O (CS0)
I/O
-
-
P84
P85
-
P94 P102
P95 P103
P122
P123
-
565
568
574
577
580
583
586
589
592
-
Not Connected Pins
-
-
-
-
P1
P102
P157
P3
P104
P158
P51
P105
P206
P52
P107
P207
P53
P155
P208
P54
P156
-
I/O
-
P104
P105
P124
P125
P126
P127
P128
P129
P130
P131
P132
P133
P134
P135
P136
P137
-
T11
U11
V11
V10
U10
T10
VCC*
GND*
T9
P144
P145
P146
P147
P148
P149
P150
P151
P152
P153
P154
P155
P156
P157
-
I/O
-
I/O
P86
P87
P88
P89
P96 P106
P97 P107
P98 P108
P99 P109
L18
5/5/97
I/O
L20
I/O (D4)
I/O
K20
K19
VCC*
GND*
K18
K17
J20
VCC
GND
I/O (D3)
I/O (RS)
I/O
P90 P100 P110
P91 P101 P111
P92 P102 P112
P93 P103 P113
P94 P104 P114
P95 P105 P115
PG223
-
VCC Pins
595
598
601
604
607
610
613
619
622
-
D3
R10
D10
R15
D16
-
J4
-
J15
-
R4
-
U9
V9
I/O
V8
J19
GND Pins
I/O
-
-
-
-
-
-
P116
P117
-
U8
J18
C7
G16
R9
C12
K4
R16
D4
K15
T7
D9
M3
T12
D15
M16
-
G3
R3
-
I/O
T8
J17
I/O
-
H20
H19
H18
VCC*
G19
F20
I/O (D2)
I/O
P96 P106 P118
P97 P107 P119
P138
P139
-
V7
P159
P160
P161
P162
P163
P164
P165
P166
P167
P168
P169
P170
P171
P172
P173
P174
5/5/97
U7
VCC
I/O
-
-
VCC*
V6
P98 P108 P120
P99 P109 P121
P140
P141
-
625
628
631
634
-
PQ/HQ240
I/O
U6
I/O
-
-
-
-
-
-
R8
G18
F19
GND Pins
I/O
-
R7
P22‡
P204‡
P37‡
P219‡
P83‡
-
P98‡
-
P143‡
-
P158‡
-
GND
I/O
P100 P110 P122
P142
-
GND*
R6
GND*
F18
-
-
-
-
-
-
-
-
-
-
-
-
-
-
637
640
643
646
649
652
655
658
Not Connected Pins
I/O
-
R5
E19
D20
E18
D19
C20
E17
D18
P195
-
-
-
-
-
I/O
P143
P144
P145
P146
P147
P148
V5
6/9/97
I/O
V4
I/O
P111 P123
P112 P124
U5
‡ Pins marked with this symbol are used for Ground connections on
some revisions of the device. These pins may not physically con-
nect to anything on the current device revision. However, they
should be externally connected to Ground, if possible.
I/O
T6
I/O (D1)
P101 P113 P125
P102 P114 P126
V3
I/O (RCLK,
RDY/BUSY)
V2
I/O
P103 P115 P127
P104 P116 P128
P105 P117 P129
P106 P118 P130
P149
P150
P151
P152
U4
T5
U3
T4
P175
P176
P177
P178
C19
B20
C18
B19
667
670
673
676
I/O
BG256
I/O (D0, DIN)
VCC Pins
I/O, SGCK4 †,
GCK6 †† (DOUT)
C14
E20
K4
R4
U15
D6
F1
L17
R17
V7
D7
F4
P4
U6
W20
D11
F17
P17
U7
-
D14
G4
P19
U10
-
D15
G17
R2
U14
-
CCLK
P107 P119 P131
P108 P120 P132
P109 P121 P133
P110 P122 P134
P111 P123 P135
P112 P124 P136
P153
P154
P159
P160
P161
P162
V1
VCC*
U2
P179
P180
P181
P182
P183
P184
A20
VCC*
A19
-
-
VCC
O, TDO
GND
0
-
GND*
T3
GND*
B18
I/O (A0, WS)
2
5
GND Pins
I/O, PGCK4 †,
GCK7 †† (A1)
U1
B17
A1
G20
U4
B7
H4
U8
D4
H17
U13
D8
N3
U17
D13
N4
W14
D17
N17
-
I/O
P113 P125 P137
P114 P126 P138
P115 P127 P139
P116 P128 P140
P163
P164
P165
P166
P3
R2
T2
N3
P185
P186
P187
P188
C17
D16
A18
A17
8
I/O
11
14
17
I/O (CS1, A2)
I/O (A3)
6/17/97
6-130
DS006 (v. 1.7) October 4, 1999 - Product Specification
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4025E, XC4028EX/XL Device Pinout Tables
The following table may contain pinout information for unsupported device/package combinations. Please see the availability
charts elsewhere in the XC4000 Series data sheet for availability information.
XC4025E,
XC4028** HQ
XC4025E,
XC4028** HQ
HQ
PG
HQ
BG
PG
HQ
BG Bndry
HQ
PG
HQ
BG
PG
HQ
BG Bndry
EX/XL
160†† 208‡ 223† 240 256†† 299
304 352‡ Scan
EX/XL
Pad Name
VCC
160†† 208‡ 223† 240 256†† 299
304 352‡ Scan
Pad Name
I/O
-
-
-
-
-
B5 P288 G26
239
-
P142 P183 VCC* P212 VCC* VCC* P38 VCC*
-
98
GND
I/O
I/O
I/O, TMS
I/O
P10 P14 GND* P14 GND* GND* P287 GND*
I/O (A8)
I/O (A9)
P143 P184 J3 P213 C10
P144 P185 J2 P214 D10
K2
K3
K5
K4
J1
J2
H1
J3
P37 D14
P36 C14
P35 A15
P34 B15
P33 C15
P32 D15
P31 A16
P30 B16
P11 P15
P12 P16
P13 P17
P14 P18
A4
A5
B7
A6
P15
P16
P17
P18
G3
G2
G1
H3
B6 P286 J23
D8 P285 J24
C7 P284 H25
B7 P283 K23
242
245
248
251
-
101
104
107
110
113
116
119
-
I/O (A19) ‡ P145 P186 J1 P215
I/O (A18) ‡ P146 P187 H1 P216
A9
B9
C9
D9
A8
B8
I/O
I/O
-
-
P188 H2 P217
P189 H3 P218
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VCC* P19 VCC* VCC* P282 VCC*
D7
D8
-
-
-
P20
P21
-
-
H2
H1
-
C8 P280 K24
E9 P279 J25
A7 P278 L24
D9 P277 K25
254
257
260
263
-
I/O (A10)
I/O (A11)
GND
I/O
I/O
I/O
I/O
VCC
I/O
P147 P190 G1 P220
P148 P191 G2 P221
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
GND* GND*
-
-
C8
A7
-
GND*
-
J4
J5
H2
G1
P29 C16
P28 B17
P27 C17
P26 B18
122
125
128
131
-
134
137
140
143
-
P22 GND* GND*
-
-
P23
P24
P25
P26
P27
P28
-
GND*
-
-
J4
J3
J2
J1
K2
K3
K1
L1
B8 P276 L25
A8 P275 L26
C9 P274 M23
B9 P273 M24
E10 P272 M25
A9 P271 M26
D10 P270 N24
C10 P269 N25
266
269
272
275
278
281
284
287
-
-
P19
P20
C8
A7
B8
A8
B9
C9
VCC* P222 VCC* VCC* P25 VCC*
H4 P223
G4 P224
A6
C7
B6
A5
H3
G2
H4
F2
P23 C18
P22 D17
P21 A20
P20 B19
I/O
I/O
I/O
I/O
P15 P21
P16 P22
P17 P23
P18 P24
I/O
I/O
I/O
P149 P192 F1 P225
P150 P193 E1 P226
GND
I/O
I/O
I/O
I/O
P151 P194 GND* P227 GND* GND* P19 GND*
GND
VCC
I/O
P19 P25 GND* P29 GND* GND* P268 GND*
P20 P26 VCC* P30 VCC* VCC* P267 VCC*
P21 P27 C10 P31
P22 P28 B10 P32
-
-
-
-
-
-
-
-
-
-
-
-
H5
G3
D1
G4
E2
F3
G5
C1
P18 C19
P17 D18
P16 A21
P15 B20
P14 C20
P13 B21
P12 B22
P10 C21
146
149
152
155
158
161
164
167
-
-
L2
L3
L4
M1
M2
M3
M4
-
B10 P266 N26
B11 P265 P25
C11 P264 P23
E11 P263 P24
D11 P262 R26
A12 P261 R25
B12 P260 R24
A13 P259 R23
290
293
296
299
302
305
308
311
-
P195 F2 P228
P196 D1 P229
C6
B5
A4
C5
B4
A3
I/O
I/O
P23 P29
A9
P33
I/O
I/O
P152 P197 C1 P230
P153 P198 E2 P231
P154 P199 F3 P232
P155 P200 D2 P233
-
-
-
-
-
-
I/O
P24 P30 A10 P34
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
-
-
-
-
-
-
-
-
-
-
P31 A11 P35
P32 C11 P36
I/O (A12)
I/O (A13)
GND
VCC
I/O
I/O
I/O
I/O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
GND* GND*
VCC* VCC*
-
-
-
GND*
VCC*
D20
A23
D21
C22
B24
C23
D22
C24
-
P37 GND* GND*
-
-
-
GND*
F4
E3
D2
C2
F5
E4
D3
C3
P9
P8
P7
P6
P5
P4
P3
P2
170
173
176
179
182
185
188
191
-
-
N1
N2
C12 P258 T26
D12 P257 T25
E12 P256 T23
B13 P255 V26
314
317
320
323
-
326
329
332
335
-
-
F4 P234
E4 P235
D5
C4
B3
B2
A2
C3
D11 P38
D12 P39
VCC* P40 VCC* VCC* P253 VCC*
I/O
I/O
I/O (A14)
I/O,
P156 P201 B1 P236
P157 P202 E3 P237
P158 P203 C2 P238
P159 P204 B2 P239
VCC
I/O
P25 P33 B11 P41
P26 P34 A12 P42
P27 P35 B12 P43
P28 P36 A13 P44
P1
P2
R1
P3
A14 P252 U24
C13 P251 V25
B14 P250 V24
D13 P249 U23
I/O
I/O
I/O
SGCK1 †,
GCK8 ‡
(A15)
VCC
GND
I/O,
GND
I/O
I/O
I/O
I/O
P29 P37 GND* P45 GND* GND* P248 GND*
P160 P205 VCC* P240 VCC* VCC* P1 VCC*
P1
P2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B15 P247 Y26
E13 P246 W25 341
C14 P245 W24 344
A17 P244 V23
D14 P243 AA26 350
B16 P242 Y25
C15 P241 Y24
E14 P240 AA25 359
338
P2 GND* P1 GND* GND* P304 GND*
P4
C3
P2
B1
D4 P303 D23
194
D13 P46
D14 P47
T1
R3
T2
U1
T3
U2
PGCK1 †,
GCK1 ‡
(A16)
I/O (A17)
I/O
347
I/O
I/O
P38 B13 P48
P39 A14 P49
353
356
P3
P4
P5
P6
P7
-
P5
P6
P7
P8
P9
-
-
-
-
P10
P11
P12
P13
-
C4
B3
C5
A2
B4
-
-
-
-
C6
A3
B5
B6
D5
D6
-
P3
P4
P5
P6
P7
-
-
-
-
P8
P9
P10
P11
P12
P13
-
C2
D2
D3
E4
C1
-
B2 P302 C25
B3 P301 D24
E6 P300 E23
D5 P299 C26
C4 P298 E24
A3 P297 F24
D6 P296 E25
197
200
203
206
209
212
215
-
I/O
I/O
P30 P40 A15 P50
P31 P41 C13 P51
I/O
GND
VCC
I/O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
GND* GND*
VCC* VCC*
-
-
-
GND*
VCC*
-
-
I/O, TDI
I/O, TCK
I/O
A18 P239 AB25 362
D15 P238 AA24 365
C16 P237 Y23
B17 P236 AC26 371
B18 P235 AA23 374
E15 P234 AB24 377
D16 P233 AD25 380
C17 P232 AC24 383
I/O
-
I/O
-
-
I/O
I/O
I/O
I/O
P32 P42 B14 P52
P33 P43 A16 P53
P34 P44 B15 P54
P35 P45 C14 P55
P36 P46 A17 P56
P37 P47 B16 P57
V1
T4
U3
V2
W1
V3
368
VCC
GND
I/O
I/O
I/O
-
-
P8
P9
-
VCC* VCC*
GND* GND*
-
-
VCC*
GND*
-
D1
E3
E2
E1
F3
F2
-
E7 P295 D26
B4 P294 G24
C5 P293 F25
A4 P292 F26
D7 P291 H23
C6 P290 H24
E8 P289 G25
218
221
224
227
230
233
236
I/O
I/O,
SGCK2 †,
GCK2 ‡
O (M1)
GND
I/O
-
I/O
-
I/O
-
-
-
P38 P48 C15 P58
P39 P49 GND* P59 GND* GND* P230 GND*
W2
A20 P231 AB23 386
I/O
-
-
DS006 (v. 1.7) October 4, 1999 - Product Specification
6-131
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4025E,
XC4025E,
XC4028** HQ
HQ
PG
HQ
BG
PG
HQ
BG Bndry
XC4028** HQ
HQ
PG
HQ
BG
PG
HQ
BG Bndry
EX/XL
Pad Name
I (M0)
VCC
I (M2)
I/O,
PGCK2 †,
GCK3 ‡
I/O (HDC) P44 P58 E16 P64
I/O
I/O
I/O
I/O (LDC)
I/O
I/O
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O (INIT)
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
160†† 208‡ 223† 240 256†† 299
304 352‡ Scan
EX/XL
Pad Name
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
160†† 208‡ 223† 240 256†† 299
304 352‡ Scan
P40 P50 A18 P60
Y1
C18 P229 AD24 389
-
P92 R18 P110 V16
P71 P93 T18 P111 W17 P16 P164 AE6
P72 P94 P17 P112 Y18 V20 P163 AE5
R18 P165 AD7
550
553
556
-
P41 P55 VCC* P61 VCC* VCC* P228 VCC*
-
P42 P56 C16 P62
P43 P57 B17 P63
W3
Y2
D17 P227 AC23 390
B19 P226 AE24 391
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
GND* GND*
VCC* VCC*
-
-
GND*
VCC*
-
-
-
R17 P162 AD6
T18 P161 AC7
U19 P160 AF4
V19 P159 AF3
559
562
565
568
571
574
577
580
W4
V4
U5
Y3
Y4
-
C19 P225 AD23 394
F16 P224 AC22 397
E17 P223 AF24 400
D18 P222 AD22 403
C20 P221 AE23 406
F17 P220 AE22 409
G16 P219 AF23 412
P45 P59 C17 P65
P46 P60 D17 P66
P47 P61 B18 P67
P48 P62 E17 P68
P73 P95 N16 P113 U16
P74 P96 T17 P114 V17
I/O
I/O
I/O
I/O
P75 P97 R17 P115 W18 R16 P158 AD5
P76 P98 P16 P116 Y19
P77 P99 U18 P117 V18
T17 P157 AE3
U18 P156 AD4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I/O,
P78 P100 T16 P118 W19 X20 P155 AC5
VCC* VCC*
GND* GND*
-
-
VCC*
GND*
-
-
SGCK3 †,
GCK4 ‡
GND
DONE
VCC
PRO-
GRAM
I/O (D7)
I/O,
PGCK3 †,
GCK5 ‡
I/O
I/O
I/O
I/O
I/O
I/O
VCC
GND
I/O (D6)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O (D5)
I/O (CS0)
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
P49 P63 F16 P69
P50 P64 C18 P70
V5
W5
Y5
V6
W6
Y6
-
D19 P218 AD20 415
E18 P217 AE21 418
D20 P216 AF21 421
G17 P215 AC19 424
F18 P214 AD19 427
H16 P213 AE20 430
E19 P212 AF20 433
F19 P211 AC18 436
P79 P101 GND* P119 GND* GND* P154 GND*
-
-
-
-
P80 P103 U17 P120 Y20
P81 P106 VCC* P121 VCC* VCC* P152 VCC*
P82 P108 V18 P122 V19 U17 P151 AC4
V18 P153 AD3
-
-
-
-
-
-
P65 D18 P71
P66 F17 P72
-
-
-
-
E15 P73
F15 P74
P83 P109 T15 P123 U19 W19 P150 AD2
P84 P110 U16 P124 U18 W18 P149 AC3
583
586
-
-
-
-
-
P51 P67 GND* P75 GND* GND* P210 GND*
-
P85 P111 T14 P125 T17
P86 P112 U15 P126 V20
T15 P148 AB4
U16 P147 AD1
V17 P146 AA4
X18 P145 AA3
U15 P144 AB2
T14 P143 AC1
589
592
595
598
601
604
-
P52 P68 E18 P76
P53 P69 F18 P77
P54 P70 G17 P78
P55 P71 G18 P79
W7
Y7
V8
H17 P209 AD18 439
G18 P208 AE19 442
G19 P207 AC17 445
H18 P206 AD17 448
-
-
-
-
-
-
-
-
-
-
-
-
R14 P127 U20
R13 P128 T18
W8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VCC* P80 VCC* VCC* P204 VCC*
-
J16 P203 AE18 451
G20 P202 AF18 454
J17 P201 AE17 457
H19 P200 AE16 460
P72 H16 P81
P73 H17 P82
Y8
U9
-
VCC* VCC*
GND* GND*
-
-
VCC*
GND*
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P87 P113 V17 P129 T19
P88 P114 V16 P130 T20
P89 P115 T13 P131 R18
P90 P116 U14 P132 R19
W17 P142 Y3
V16 P141 AA2
X17 P140 AA1
U14 P139 W4
V15 P138 W3
T13 P137 Y2
W16 P136 Y1
W15 P135 V4
607
610
613
616
619
622
625
628
-
631
634
637
640
-
-
P83 GND* GND*
-
GND*
-
-
-
V9
W9
Y9
H20 P199 AF16 463
J18 P198 AC15 466
J19 P197 AD15 469
-
-
-
-
P117 V15 P133 R20
P118 V14 P134 P18
G15 P84
H15 P85 W10 K16 P196 AE15 472
-
-
-
-
-
-
-
-
P56 P74 H18 P86
P57 P75 J18 P87
P58 P76 J17 P88
V10
Y10
Y11
J20 P195 AF15 475
K17 P194 AD14 478
K18 P193 AE14 481
P91 P119 GND* P135 GND* GND* P134 GND*
-
-
-
-
R12 P136 P20
R11 P137 N18
U13 P133 V3
V14 P132 W2
P59 P77 J16 P89 W11 K19 P192 AF14 484
P60 P78 VCC* P90 VCC* VCC* P191 VCC*
P61 P79 GND* P91 GND* GND* P190 GND*
-
-
P92 P120 U13 P138 N19 W14 P131 U4
P93 P121 V13 P139 N20 V13 P130 U3
VCC* P140 VCC* VCC* P129 VCC*
P62 P80 K16 P92
P63 P81 K17 P93
P64 P82 K18 P94
V11
U11
Y12
L19 P189 AE13 487
-
-
L18 P188 AC13 490
L16 P187 AD13 493
L17 P186 AF12 496
M20 P185 AE12 499
M19 P184 AD12 502
N20 P183 AC12 505
P94 P122 U12 P141 M17
P95 P123 V12 P142 M18
T12 P127 V2
X14 P126 V1
U12 P125 U2
W13 P124 T2
643
646
649
652
-
P65 P83 L18 P95 W12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P84 L17 P96
P85 L16 P97
V12
U12
Y13
P143 GND* GND*
-
-
-
GND*
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X13 P123 T1
V12 P122 R4
655
658
661
664
667
670
673
676
-
W13 M18 P182 AF11 508
GND*
-
-
M19
P98 GND* GND*
-
-
-
-
P124 T11 P144 M20 W12 P121 R3
P125 U11 P145 L19
M17 P181 AE11 511
M16 P180 AD11 514
N19 P179 AF9
T11 P120 R2
X12 P119 R1
U11 P118 P3
V11 P117 P2
P96 P126 V11 P146 L18
P97 P127 V10 P147 L20
P98 P128 U10 P148 K20
L15 P99
M15 P100 Y14
VCC* P101 VCC* VCC* P177 VCC*
V13
517
I/O
I/O (D4)
I/O
VCC
GND
I/O (D3)
I/O (RS)
I/O
I/O
I/O
I/O
I/O
P20 P178 AD10 520
-
P99 P129 T10 P149 K19 W11 P116 P1
P100 P130 VCC* P150 VCC* VCC* P115 VCC*
P101 P131 GND* P151 GND* GND* P114 GND*
P102 P132 T9 P152 K18 W10 P113 N2
P66 P86 M18 P102 Y15
P67 P87 M17 P103 V14
N18 P175 AE9
P19 P174 AD9
523
526
-
P68 P88 N18 P104 W15 N17 P173 AC10 529
679
682
685
688
691
694
697
P69 P89 P18 P105 Y16
R19 P172 AF7
532
-
P103 P133 U9 P153 K17
P104 P134 V9 P154 J20
P105 P135 V8 P155 J19
V10 P112 N4
T10 P111 N3
U10 P110 M1
X9 P109 M2
W9 P108 M3
X8 P107 M4
P70 P90 GND* P106 GND* GND* P171 GND*
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
N16 P170 AE8
P18 P169 AD8
U20 P168 AC9
535
538
541
544
547
-
-
-
P136 U8 P156 J18
P137 T8 P157 J17
N15 P107 V15
P15 P108 W16 P17 P167 AF6
T19 P166 AE7
I/O
I/O
-
-
-
H20
P91 N17 P109 Y17
6-132
DS006 (v. 1.7) October 4, 1999 - Product Specification
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4025E,
XC4025E,
XC4028** HQ
HQ
PG
HQ
BG
PG
HQ
BG Bndry
XC4028** HQ
HQ
PG
HQ
BG
PG
HQ
BG Bndry
EX/XL
Pad Name
I/O
GND
I/O
I/O
I/O (D2)
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
160†† 208‡ 223† 240 256†† 299
304 352‡ Scan
EX/XL
Pad Name
I/O
I/O
I/O
160†† 208‡ 223† 240 256†† 299
304 352‡ Scan
-
-
-
-
-
-
-
-
-
-
-
-
-
V9 P106 L1
700
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
A13
D12
-
-
M5
P1
M4
N2
P51
A9
62
65
68
71
-
P158 GND* GND* GND*
-
-
-
P50 D11
P49 B11
P48 A11
-
-
U9 P105 L2
T9 P104 L3
703
706
709
712
-
-
I/O
P106 P138
P107 P139
V7 P159 H19
U7 P160 H18
W8 P103
X7 P102 K3
J1
GND
I/O (A4)
I/O (A5)
I/O
-
-
-
GND* GND*
-
GND*
P134 P174 M2 P202 C12
P135 P175 M1 P203 B12
N1
M3
M2
L5
M1
L4
P47 D12
P46 C12
P45 B12
P44 A12
P43 C13
P42 B13
P41 A13
P40 B14
74
77
80
83
86
89
92
95
-
-
-
VCC* P161 VCC* VCC* P101 VCC*
P108 P140
P109 P141
V6 P162 G19
U6 P163 F20
R8 P164 G18
R7 P165 F19
V8
W7
U8
P99
P98
P97
P96
J2
J3
K4
G1
715
718
721
724
-
-
P176
L3 P205 A12
L2 P206 B11
L1 P207 C11
K1 P208 A11
K2 P209 A10
K3 P210 B10
I/O
P136 P177
-
-
-
-
I/O (A21) ‡ P137 P178
I/O (A20) ‡ P138 P179
I/O (A6)
I/O (A7)
GND
W6
P110 P142 GND* P166 GND* GND* P95 GND*
P139 P180
P140 P181
L3
L2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
T8
V7
X4
U7
W5
V6
T7
X3
P94
P93
P92
P91
P90
P89
P88
P87
-
H2
H3
J4
F1
G2
G3
F2
E2
727
730
733
736
739
742
745
748
-
P141 P182 GND* P211 GND* GND* P39 GND*
R6 P167 F18
R5 P168 E19
V5 P169 D20
V4 P170 E18
U5 P171 D19
T6 P172 C20
6/19/97
* Pads labelled GND* or VCC* are internally bonded to Ground or
VCC planes within the associated package. They have no direct
connection to any specific package pin.
P143
P144
P111 P145
P112 P146
** XC4028XL in the BG256 package has 16 extra GND balls in cen-
ter of package.
GND
VCC
I/O (D1)
I/O (RCLK, P114 P148
RDY/BUS
Y)
-
-
-
-
-
-
-
-
GND* GND*
VCC* VCC*
GND*
VCC*
F3
-
-
† = E only
†† = XL only
‡ = EX, XL only
P113 P147
V3 P173 E17
V2 P174 D18
U6
V5
P86
P85
751
754
G4
Additional XC4025E, XC4028EX/XL Package
Pins
I/O
I/O
I/O
I/O
I/O (D0,
DIN)
I/O,
SGCK4 †,
GCK6 ‡
(DOUT)
CCLK
VCC
-
-
-
-
-
-
-
-
-
-
W4
W3
T6
U5
V4
P84
P83
P82
P81
P80
D2
F4
E3
C2
D3
757
760
763
766
769
P115 P149
P116 P150
P117 P151
U4 P175 C19
T5 P176 B20
U3 P177 C18
HQ208
Not Connected Pins
P1
P3
P51
P52
P53
P54
P102
P104
P105
P107
P155
P156
P157
P158
P206
P207
P208
P118 P152
T4 P178 B19
X1
P79
E4
772
5/9/97
P119 P153
V1 P179 A20
V3
P78
C3
-
-
0
-
P120 P154 VCC* P180 VCC* VCC* P77 VCC*
P121 P159 U2 P181 A19 U4 P76 D4
P122 P160 GND* P182 GND* GND* P75 GND*
PG223
O, TDO
GND
I/O (A0,
WS)
VCC Pins
D3
D10
D16
J4
P123 P161
T3 P183 B18
W2
P74
B3
2
J15
R4
R10
R15
GND Pins
I/O,
P124 P162
U1 P184 B17
V2
P73
C4
5
C7
D15
K15
R9
C12
G3
M3
D4
G16
M16
T7
D9
K4
R3
PGCK4 †,
GCK7 ‡
(A1)
I/O
I/O
P125 P163
P126 P164
P3 P185 C17
R2 P186 D16
T2 P187 A18
R5
T4
U3
P72
P71
P70
D5
A3
D6
8
11
14
R16
T12
5/9/97
I/O (CS1, P127 P165
A2)
I/O (A3)
I/O
I/O
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
P128 P166
N3 P188 A17
V1
R4
P5
P69
P68
P67
-
C6
B5
A4
VCC*
GND*
C7
B6
A6
D8
B7
17
20
23
-
HQ240
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
GND Pins
P204
P219
-
-
-
-
VCC* VCC*
GND* GND*
5/9/97
-
-
Note: These pins may be Not Connected for this device revision,
however for compatability with other devices in this package, these
pins should be tied to GND.
P4 P189 C16
N4 P190 B16
P2 P191 A16
T1 P192 C15
R1 P193 B15
N2 P194 A15
U2
T3
U1
P4
R3
N5
T2
R2
P66
P65
P64
P63
P62
P61
P60
P59
26
29
32
35
38
41
44
47
-
50
53
56
59
-
-
P129 P167
P130 P168
-
-
-
-
P169
P170
-
-
A7
D9
C9
-
-
P195
-
-
-
P131 P171 GND* P196 GND* GND* P58 GND*
P132 P172
P133 P173
P1 P197 B14
N1 P198 A14
M4 P199 C13
L4 P200 B13
N4
P3
P2
N3
P57
P56 D10
P55 C10
B8
-
-
-
-
-
-
P54
B9
VCC* P201 VCC* VCC* P52 VCC*
DS006 (v. 1.7) October 4, 1999 - Product Specification
6-133
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
BG256
HQ304
VCC Pins
Not Connected Pins
C14
D14
F4
K4
P19
U6
D6
D15
F17
L17
R2
D7
E20
G4
P4
R4
D11
F1
P11
P24
5/15/97
P53
P100
P128
P176
P205
P254
P281
-
G17
P17
R17
U14
-
Note: In XC4025 (no extension) devices in the HQ304 package,
P101 is a No Connect (N.C.) pin. P101 is Vcc in XC4025E and
XC4028EX/XL devices. Where necessary for compatibility, this pin
can be left unconnected.
U7
V7
U10
W20
U15
GND Pins
A1
D13
H17
U4
B7
D17
N3
U8
-
D4
G20
N4
U13
-
D8
H4
N17
U17
-
BG352
VCC Pins
A10
D19
P4
A17
G23
U1
B2
H4
B25
K1
D7
K26
Y4
D13
N23
AC8
AF17
W14
5/9/97
U26
AE2
W23
AE25
AC14
AC20
AF10
GND Pins
PG299
A1
A22
E26
W26
AF2
AF25
A2
A25
H1
AB1
AF5
AF26
A5
A26
H26
AB26
AF8
-
A8
B1
N1
AE1
AF13
-
A14
B26
P26
AE26
AF19
-
A19
E1
W1
AF1
AF22
-
VCC Pins
A2
B20
K1
T20
X15
A6
E1
L20
W1
X19
A11
E5
R1
X5
-
A16
F20
T16
X10
-
Not Connected Pins
GND Pins
A18
C5
F23
T4
A24
C8
J26
T24
AC16
AE4
B4
C11
K2
B10
D1
B23
D16
L23
AC2
AD16
-
C1
D25
T3
AC6
AD21
-
A5
B1
K20
T5
A10
E16
L1
W20
X16
A15
E20
R20
X2
A19
F1
T1
X6
-
L4
U25
AC21
AE10
AB3
AC25
-
AC11
AD26
5/9/97
X11
-
6/18/97
XC4036EX/XLDevice Pinout Tables
The following table may contain pinout information for unsupported device/package combinations. Please see the availability
charts elsewhere in the XC4000 Series data sheet for availability information.
XC4036EX/XL
Pad Name
I/O (A13)
GND
VCC
I/O
I/O
I/O
I/O
I/O
PQ
HQ
HQ
HQ
304
P10
-
-
P9
P8
-
BG
352
C21
PG
411
G3
BG
432
B26
Bndry
Scan
185
-
XC4036EX/XL
Pad Name
VCC
I/O (A8)
I/O (A9)
I/O (A19)
I/O (A18)
I/O
PQ
HQ
HQ
HQ
304
BG
352
PG
411
BG
432
Bndry
Scan
-
160†† 208†† 240
P155 P200 P233
160†† 208†† 240
P142 P183 P212
P143 P184 P213
P144 P185 P214
P145 P186 P215
P146 P187 P216
P38
P37
P36
P35
P34
P33
P32
P31
P30
-
VCC* VCC* VCC*
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
GND* GND* GND*
VCC* VCC* VCC*
D14
C14
A15
B15
C15
D15
A16
B16
W3
Y2
V4
T2
U1
V6
U3
R1
D17
A17
C18
D18
B18
A19
B19
C19
110
113
116
119
122
125
128
131
-
-
D20
A23
A24
B23
D21
C22
B24
C23
D22
C24
K6
G1
E1
E3
J7
H6
C3
D2
E5
G7
A27
D25
C26
B27
C27
B28
D27
B29
C28
D28
188
191
194
197
200
203
206
209
212
215
-
-
-
P188 P217
P189 P218
-
I/O
P234
P235
P7
P6
P5
P4
P3
P2
P1
I/O (A10)
I/O (A11)
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
P147 P190 P220
P148 P191 P221
I/O
I/O
I/O
I/O (A14)
P156 P201 P236
P157 P202 P237
P158 P203 P238
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VCC* VCC* VCC*
GND* GND* GND*
-
-
P29
P28
-
C16
B17
D16
A18
C17
B18
U5
T4
P2
N1
R5
M2
D19
A20
B20
C20
C21
A22
134
137
140
143
146
149
-
152
155
158
161
-
164
167
170
173
176
179
182
I/O, GCK8 (A15) P159 P204 P239
VCC
GND
I/O, GCK1 (A16)
I/O (A17)
I/O
I/O
I/O, TDI
I/O, TCK
I/O
I/O
I/O
I/O
VCC
GND
I/O
I/O
I/O
P160 P205 P240
VCC* VCC* VCC*
P1
P2
P3
P4
P5
P6
P7
-
-
-
-
-
P2
P4
P5
P6
P7
P8
P9
-
-
-
-
-
P1
P2
P3
P4
P5
P6
P7
-
-
-
-
-
P304 GND* GND* GND*
-
-
P303
P302
P301
P300
P299
P298
-
D23
C25
D24
E23
C26
E24
D25
F23
F24
E25
H8
F6
B4
D4
B2
G9
F8
C5
A7
A5
D29
C30
E28
E29
D30
D31
E30
E31
G28
G29
218
221
224
227
230
233
236
239
242
245
-
P27
P26
P25
P23
P22
P21
P20
P222
P223
P224
VCC* VCC* VCC*
C18
D17
A20
B19
L3
T6
N5
M4
B22
C22
B23
A24
P149 P192 P225
P150 P193 P226
P151 P194 P227
-
-
-
-
P152 P197 P230
P153 P198 P231
P154 P199 P232
-
P19 GND* GND* GND*
P297
P296
-
-
-
-
-
P18
P17
P16
P15
P14
P13
P12
C19
D18
A21
B20
C20
B21
B22
K2
K4
P6
M6
J3
D22
C23
B24
C24
A26
C25
D24
VCC* VCC* VCC*
GND* GND* GND*
D26
G24
F25
P195 P228
P196 P229
-
-
-
-
-
I/O
I/O
I/O
I/O (A12)
P8
P9
-
P10
P11
P12
P8
P9
P10
P295
P294
P293
B8
C9
E9
H28
H29
G30
248
251
254
H2
H4
6-134
DS006 (v. 1.7) October 4, 1999 - Product Specification
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4036EX/XL
Pad Name
PQ
HQ
HQ
HQ
304
BG
352
PG
411
BG
432
Bndry
Scan
XC4036EX/XL
Pad Name
PQ
HQ
HQ
HQ
304
BG
352
PG
411
BG
432
Bndry
Scan
160†† 208†† 240
160†† 208†† 240
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O, TMS
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
-
-
-
P13
-
-
-
-
P14
P15
P16
P17
P18
-
-
-
-
-
-
-
-
-
P11
P12
P13
-
P292
P291
P290
P289
P288
F26
H23
H24
G25
G26
F12
D10
B10
F10
F14
H30
J28
J29
H31
J30
257
260
263
266
269
-
272
275
278
281
-
284
287
290
293
296
299
-
I (M2)
P42
P43
P44
P45
P46
P47
P48
-
-
-
-
-
P56
P57
P58
P59
P60
P61
P62
-
-
-
-
-
P62
P63
P64
P65
P66
P67
P68
-
-
-
-
-
P227 AC23
P226 AE24
P225 AD23
P224 AC22
P223 AF24
P222 AD22
P221 AE23
G33
D36 AK29
C37 AH27
AJ28
438
439
442
445
448
451
454
457
460
463
466
-
I/O, GCK3
I/O (HDC)
I/O
I/O
I/O
I/O (LDC)
I/O
I/O
I/O
I/O
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
F34
J33
D38
G35 AH26
E39 AL27
K34 AH25
F38 AK26
G37 AL26
AK28
AJ27
AL28
-
-
P10
P11
P12
P13
P14
-
-
-
-
-
-
-
-
-
-
-
P14
P15
P16
P17
P18
P19
P20
P21
-
P287 GND* GND* GND*
P286
P285
P284
P283
J23
J24
H25
K23
C11
B12
E11
E15
K28
K29
K30
K31
-
-
AC21
AD21
P220 AE22
P219 AF23
P282 VCC* VCC* VCC*
P280
P279
-
K24
J25
J26
L23
L24
K25
F16
C13
B14
E17
E13
A15
L29
L30
M29
M31
N31
N28
-
-
VCC* VCC* VCC*
GND* GND* GND*
-
-
-
-
P49
P50
-
-
-
-
-
-
P51
P52
P53
P54
P55
-
-
-
-
-
-
-
-
-
-
-
P63
P64
P65
P66
-
-
-
-
P67
P68
P69
P70
P71
-
P72
P73
-
-
-
-
-
-
-
-
-
P69
P70
P71
P72
P73
P74
-
P218 AD20
P217 AE21
P216 AF21
H38 AH24
J37 AJ25
G39 AK25
469
472
475
478
481
484
487
490
-
493
496
499
502
-
505
508
511
514
517
520
-
-
-
-
-
P278
P277
-
P215 AC19 M34 AJ24
P22
-
-
GND* GND* GND*
VCC* VCC* VCC*
L25
L26
M23
M24
M25
M26
N24
N25
P214 AD19
P213 AE20
P212 AF20
P211 AC18
P210 GND* GND* GND*
P209 AD18 M38 AJ22
P208 AE19
P207 AC17
P206 AD17
N35
P34 AH22
J35
L37
AL24
-
-
-
-
P276
P275
P274
P273
P272
P271
P270
P269
B16
D16
D18
A17
E19
B18
C17
C19
P30
P28
P29
R31
R30
R28
R29
T31
302
305
308
311
314
317
320
323
-
AJ23
AK23
-
-
-
-
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
-
-
-
-
-
-
-
-
-
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
-
P75
P76
P77
P78
P79
P80
P81
P82
-
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
-
-
-
-
-
-
R35 AK22
H36
T34
AL22
AJ21
P204 VCC* VCC* VCC*
P203 AE18
P202 AF18
P268 GND* GND* GND*
P267 VCC* VCC* VCC*
N37 AH20
N39 AK21
U35 AK20
R39
M36 AL20
V34 AH18
-
P266
P265
P264
P263
P262
P261
P260
P259
-
N26
P25
P23
P24
R26
R25
R24
R23
F20
B20
C21
B22
E21
D22
A23
B24
T30
T29
U31
U30
U28
U29
V30
V29
326
329
332
335
338
341
344
347
-
-
-
AC16
AD16
-
-
-
AJ19
P201 AE17
P200 AE16
P83
-
-
-
-
GND* GND* GND*
VCC* VCC* VCC*
-
P199 AF16
P198 AC15
P197 AD15
P196 AE15
P195 AF15
P194 AD14
P193 AE14
P192 AF14 W37 AK16
P191 VCC* VCC* VCC*
P190 GND* GND* GND*
R37 AK19
T38
T36
V36 AK18
U37 AH17
U39
V38
523
526
529
532
535
538
541
544
-
I/O
-
-
-
AJ18
AL19
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC* VCC* VCC*
GND* GND* GND*
-
-
P84
P85
P86
P87
P88
P89
P90
P91
P92
P93
P94
P95
P96
P97
-
P37
-
-
-
-
P38
P39
P40
P41
P42
P43
P44
P45
-
-
-
I/O
I/O
I/O
I/O
I/O (INIT)
VCC
GND
I/O
I/O
I/O
-
-
-
-
-
-
P258
P257
-
T26
T25
T24
U25
T23
V26
A25
D24
B26
A27
C27
F24
W30
W29
Y30
Y29
Y28
350
353
356
359
362
365
-
368
371
374
377
-
380
383
386
389
392
395
398
401
-
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
-
-
-
-
-
-
P74
P75
P76
P77
P78
P79
P80
P81
P82
P83
P84
P85
-
-
-
-
-
-
-
-
-
AJ17
AJ16
-
P256
P255
-
-
-
-
AA30
-
P253 VCC* VCC* VCC*
P189 AE13
Y34
AL16
547
550
553
556
559
562
565
568
-
P25
P26
P27
P28
P29
-
-
-
-
-
P33
P34
P35
P36
P37
-
-
-
-
P38
P39
P40
P41
-
-
-
-
P252
P251
P250
P249
U24
V25
V24
U23
E25 AA29
E27 AB31
B28 AB30
C29 AB29
P188 AC13 AC37 AH15
P187 AD13 AB38 AK15
P186 AF12 AD36 AJ14
P185 AE12 AA35 AH14
P184 AD12 AE37 AK14
P183 AC12 AB36 AL13
P182 AF11 AD38 AK13
I/O
I/O
I/O
I/O
P248 GND* GND* GND*
P247 Y26 F26 AB28
P246 W25
P245 W24
P244
P243 AA26
P242
P241
P240 AA25
-
-
P239 AB25
P238 AA24
P237
P236 AC26
-
-
P235 AA23
P234 AB24
P233 AD25
P232 AC24
P231 AB23
P230 GND* GND* GND*
P229 AD24 E35 AH28
P228 VCC* VCC* VCC*
-
D28 AC30
B30 AC29
E29 AC28
F28 AD29
F30 AD28
C31 AE30
E31 AE29
I/O
-
-
P46
P47
P48
P49
P50
P51
-
-
-
-
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
-
-
VCC* VCC* VCC*
GND* GND* GND*
V23
P98
-
-
-
-
-
-
-
-
-
-
-
P181 AE11 AB34 AJ13
P180 AD11 AE39 AH13
571
574
577
580
583
586
-
589
592
595
598
-
601
604
607
610
613
616
619
622
-
Y25
Y24
P30
P31
-
-
-
-
-
AE10 AM36 AL12
AC11 AC35 AK12
GND* GND* GND*
VCC* VCC* VCC*
P99
P179
AF9
AG39 AH12
-
-
-
P100 P178 AD10 AG37 AJ11
P101 P177 VCC* VCC* VCC*
P102 P175
P103 P174
P104 P173 AC10 AE35 AJ10
P105 P172 AF7 AH38 AK9
P106 P171 GND* GND* GND*
-
-
P107 P168
P108 P167
P109 P166
P110 P165
P111 P164
P112 P163
B32
A33 AE28
A35 AG31
AF31
404
407
410
413
416
419
422
425
428
431
434
-
-
P66
P67
P68
P69
P70
-
-
-
-
-
-
P86
P87
P88
P89
P90
-
-
-
-
P91
P92
P93
P94
AE9
AD34 AL10
P32
P33
-
P42
P43
-
P52
P53
-
Y23
AD9 AN39 AK10
F32
AF28
AD26
AC25
C35 AG30
B38 AG29
E33 AH31
G31 AG28
H32 AH30
-
-
-
P34
P35
P36
P37
P38
P39
P40
P41
P44
P45
P46
P47
P48
P49
P50
P55
P54
P55
P56
P57
P58
P59
P60
P61
P170
P169
AE8
AJ37
AL8
AD8 AG35 AH10
AC9
AF6
AE7
AF34
AH36 AK8
AK36 AK7
AJ9
I/O, GCK2
O (M1)
GND
I (M0)
VCC
B36
A39 AH29
AJ30
I/O
I/O
I/O
-
AD7 AM34 AL6
AE6
AE5
437
-
P71
P72
AH34 AJ7
AJ35 AH8
DS006 (v. 1.7) October 4, 1999 - Product Specification
6-135
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4036EX/XL
Pad Name
PQ
HQ
HQ
HQ
304
BG
352
PG
411
BG
432
Bndry
Scan
XC4036EX/XL
Pad Name
PQ
HQ
HQ
HQ
304
BG
352
PG
411
BG
432
Bndry
Scan
160†† 208†† 240
160†† 208†† 240
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
-
-
-
-
-
-
-
-
-
-
-
GND* GND* GND*
VCC* VCC* VCC*
-
-
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
P107 P139 P160 P102
K3
AP16
L3
802
-
-
-
P161 P101 VCC* VCC* VCC*
P162
P161
AD6
AC7
AL37 AK6
AT38 AL5
625
628
631
634
637
640
643
646
649
652
-
P108 P140 P162
P109 P141 P163
P99
P98
P97
P96
J2
J3
K4
G1
AV12
AR13
AU11
AT12
K1
K2
K3
K4
805
808
811
814
-
817
820
823
826
829
832
835
838
-
-
-
P73
P74
-
P95
P96
-
P113 P160
P114 P159
-
-
P115 P158
P116 P157
P117 P156
AF4 AM38 AH7
-
-
-
-
P164
P165
AF3
AE4
AN37 AJ6
AK34 AK5
-
-
P110 P142 P166
P95 GND* GND* GND*
-
-
AC6 AR39 AL4
AD5 AN35 AK4
-
-
-
-
-
-
-
-
-
-
-
-
P94
P93
P92
P91
P90
P89
P88
P87
-
H2
H3
J4
F1
G2
G3
F2
E2
AP14
AR11
AV10
AT8
AT10
AP10
AP12
AR9
J2
J3
J4
H1
H2
H3
H4
G2
P75
P76
P77
P97
P98
P99
I/O
I/O
AE3
AD4
AC5
AL33 AH5
AV38 AK3
P167
P168
I/O
I/O
I/O
I/O
I/O, GCK4
GND
DONE
VCC
PROGRAM
I/O (D7)
I/O, GCK5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
GND
I/O (D6)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O (D5)
I/O (CS0)
I/O
I/O
I/O
P78 P100 P118 P155
AT36
AJ4
P143 P169
P144 P170
P79 P101 P119 P154 GND* GND* GND*
P80 P103 P120 P153 AD3 AR35 AH4
P81 P106 P121 P152 VCC* VCC* VCC*
P82 P108 P122 P151
P83 P109 P123 P150
P84 P110 P124 P149
P85 P111 P125 P148
P86 P112 P126 P147
-
-
-
-
-
-
-
-
P87 P113 P129 P142
P88 P114 P130 P141
P89 P115 P131 P140
P90 P116 P132 P139
-
-
-
-
-
-
-
P111 P145 P171
P112 P146 P172
-
-
I/O
AC4 AN33 AH3
AD2 AM32 AJ2
GND
VCC
I/O (D1)
I/O (RCLK,
RDY/BUSY)
I/O
I/O
I/O
I/O
-
-
-
-
GND* GND* GND*
VCC* VCC* VCC*
F3
655
658
661
664
667
670
673
676
679
682
-
-
-
AC3
AP34 AG4
P113 P147 P173
P114 P148 P174
P86
P85
AU7
AW7
G4
F2
841
844
AB4 AW39 AG3
AD1 AN31 AH2
G4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
D1
C1
D2
F4
E3
C2
D3
E4
AW5
AV6
AR7
AV4
AN9
AW1
AP6
AU3
F3
E1
E3
D1
E4
D2
C2
D3
847
850
853
856
859
862
865
868
-
-
-
-
-
-
-
-
-
-
-
-
AB3
AV36 AH1
AC2 AR33 AF4
P84
P83
P82
P81
P80
P79
P127 P146
P128 P145
-
-
-
-
AA4
AA3
AP32 AF3
AU35 AG2
I/O
I/O
P115 P149 P175
P116 P150 P176
P117 P151 P177
P118 P152 P178
P144
P143
-
-
AB2 AW33 AE3
AC1 AU33 AF2
VCC* VCC* VCC*
GND* GND* GND*
I/O (D0, DIN)
I/O, GCK6
(DOUT)
-
Y3
AA2
AA1
W4
W3
Y2
AV32 AF1
AU31 AD4
AR31 AD3
AP28 AE2
AT32 AC3
AV30 AD1
AR29 AC2
AP26 AB4
685
688
691
694
697
700
703
706
-
709
712
715
718
-
721
724
727
730
733
736
-
CCLK
VCC
O, TDO
GND
I/O (A0, WS)
I/O, GCK7 (A1)
I/O
I/O
I/O
I/O
P119 P153 P179
P120 P154 P180
P121 P159 P181
P122 P160 P182
P123 P161 P183
P124 P162 P184
P125 P163 P185
P126 P164 P186
P78
P77
P76
C3
AR5
D4
-
-
0
-
2
VCC* VCC* VCC*
D4 AN7 C4
P75 GND* GND* GND*
P117 P133 P138
P118 P134 P137
-
-
P74
P73
P72
P71
-
B3
C4
D5
A3
C5
B4
D6
C6
B5
A4
AT4
AV2
AM8
AL7
AR3
AR1
AK6
AN3
AM6
AM2
B3
D5
B4
C5
B5
C6
A5
D7
B6
A6
5
8
-
-
P136
P135
Y1
V4
11
14
17
20
23
26
29
-
P91 P119 P135 P134 GND* GND* GND*
-
-
P92 P120 P138 P131
P93 P121 P139 P130
-
-
-
-
-
-
-
-
-
P136 P133
P137 P132
V3
W2
U4
U3
AU29 AB3
AV28 AB2
AT28 AB1
AR25 AA3
-
I/O (CS1, A2)
I/O (A3)
I/O
P127 P165 P187
P128 P166 P188
P70
P69
P68
P67
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P140 P129 VCC* VCC* VCC*
I/O
P94 P122 P141 P127
P95 P123 P142 P126
V2
V1
T4
T3
U2
T2
AP24 AA2
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O (A4)
I/O (A5)
I/O
VCC* VCC* VCC*
GND* GND* GND*
AU27
AR27
AW27
AT24
AR23
Y2
Y4
Y3
W4
W3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P189
P190
P66
P65
P64
P63
P62
P61
P60
P59
C7
B6
A6
D8
B7
A7
D9
C9
AL3
AH6
AP2
AK4
AG5
AF6
AL5
AJ3
D8
C7
B7
D9
D10
C9
32
35
38
41
44
47
50
53
-
56
59
62
65
-
68
71
74
77
80
83
-
P125
P124
-
P129 P167 P191
P130 P168 P192
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O (D4)
I/O
VCC
GND
I/O (D3)
I/O (RS)
I/O
I/O
I/O
I/O
I/O
P143
GND* GND* GND*
VCC* VCC* VCC*
-
-
-
-
P169 P193
P170 P194
-
-
-
-
-
P123
P122
T1
R4
R3
R2
R1
P3
P2
P1
AP22
AV24
AU23
AT22
AR21
AV22
AP20
AU21
V4
V3
U1
U2
U4
U3
T1
T2
739
742
745
748
751
754
757
760
-
-
-
P195
-
B9
C10
P124 P144 P121
P125 P145 P120
P131 P171 P196
P132 P172 P197
P133 P173 P198
P58 GND* GND* GND*
P57
P56
P55
P54
P52
P51
P50
-
B8
D10
C10
B9
AH2
AE5
AM4
AD6
B10
A10
C11
D12
P96 P126 P146 P119
P97 P127 P147 P118
P98 P128 P148 P117
P99 P129 P149 P116
P100 P130 P150 P115 VCC* VCC* VCC*
P101 P131 P151 P114 GND* GND* GND*
P102 P132 P152 P113
P103 P133 P153 P112
P104 P134 P154 P111
P105 P135 P155 P110
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P199
P200
P201
VCC* VCC* VCC*
A9
-
-
-
-
-
-
-
-
AG3
AG1
AC5
AE1
AH4
AB6
B11
C12
C13
A12
D14
B13
-
D11
C11
B10
B11
A11
N2
N4
N3
M1
M2
M3
M4
L1
AU19
AV20
AV18
AR19
AT18
AW17
AV16
AP18
T3
R1
R2
R4
R3
P2
P3
P4
763
766
769
772
775
778
781
784
-
-
P49
P48
-
P136 P156 P109
P137 P157 P108
GND* GND* GND*
VCC* VCC* VCC*
-
-
-
-
-
-
-
-
-
-
-
-
-
P107
P106
-
-
P105
P104
-
-
P134 P174 P202
P135 P175 P203
P47
P46
P45
P44
P43
P42
P41
P40
D12
C12
B12
A12
C13
B13
A13
B14
AD2
AB4
AE3
AC1
AD4
AA5
AA3
Y6
C14
A13
B14
D15
C15
B15
B16
A16
86
89
92
95
98
101
104
107
I/O
VCC
GND
I/O
I/O
I/O
VCC* VCC* VCC*
GND* GND* GND*
-
P176 P205
P158
-
I/O
P136 P177 P206
P137 P178 P207
P138 P179 P208
P139 P180 P209
P140 P181 P210
-
-
-
-
L2
L3
K2
L4
J1
AR17
AT16
AV14
AW13
AR15
N3
N4
M1
M2
L2
787
790
793
796
799
I/O (A21)
I/O (A20)
I/O (A6)
I/O (A7)
I/O
I/O (D2)
P106 P138 P159 P103
6-136
DS006 (v. 1.7) October 4, 1999 - Product Specification
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4036EX/XL
Pad Name
PQ
HQ
HQ
HQ
304
BG
352
PG
411
BG
432
Bndry
Scan
PG411
160†† 208†† 240
VCC Pins
GND
6/17/97
P141 P182 P211
P39 GND* GND* GND*
-
A3
F36
AL39
AW29
A11
J1
AP4
AW37
A21
L39
AT34
-
A31
W1
AU1
-
C39
AA39
AW9
-
D6
AJ1
AW19
-
* Pads labelled GND* or VCC* are internally bonded to Ground or VCC
planes within the associated package. They have no direct connection to
any specific package pin.
GND Pins
A9
D20
P4
AF4
AT14
AW21
A19
D26
P36
AF36
AT20
AW31
A29
D34
W39
AJ39
AT26
-
A37
F4
Y4
AL1
AU39
-
C1
J39
Y36
AP36
AW3
-
D14
L1
AA1
AT6
AW11
-
†† = XL only
Additional XC4036EX/XL Package Pins
HQ208
Not Connected Pins
Not Connected Pins
A13
C25
E7
G5
L35
W35
AF2
AN1
B6
C33
E23
H34
N3
B34
D8
E37
J5
P38
AA37
AJ5
AP8
AU5
AU37
AW25
C7
D12
F2
K36
R3
AB2
AK2
AP30
AU9
AV8
AW35
C15
D30
F18
K38
V2
AC3
AK38
AP38
AU13
AV26
-
C23
D32
F22
L5
W5
AC39
AL35
AR37
AU15
AV34
-
P1
P54
P155
P3
P51
P104
P157
-
P52
P105
P158
-
P53
P107
P206
-
P102
P156
P208
P207
5/15/97
Y38
AF38
AN5
AT30
AU25
AW23
AT2
HQ240
AU17
AW15
6/16/97
GND Pins
P204
P219
-
-
-
6/17/97
The Ground (GND) package pins in the above table should be
externally connected to Ground if possible; however, they can be
left unconnected if necessary for compatibility with other devices.
BG432
VCC Pins
A1
A11
D21
AA4
AJ29
A21
L1
A31
L4
C3
L28
AH11
AL21
C29
L31
AH21
AL31
D11
AA1
AJ3
AA28
AL1
AA31
AL11
HQ304
Not Connected Pins
GND Pins
P11
P176
P24
P205
P53
P254
P100
P281
P128
-
A2
A23
B30
G31
T28
AE31
AK30
AL14
A3
A25
B31
J1
A7
A29
C1
A9
A30
C31
P1
AC1
AJ31
AL3
AL25
A14
B1
A18
B2
G1
5/15/97
D16
P31
AC31
AK1
AL7
AL29
J31
V31
AJ1
AL2
AL23
T4
V1
AE1
AK2
AL9
AL30
AH16
AK31
AL18
BG352
VCC Pins
A10
D19
P4
A17
G23
U1
B2
H4
U26
AE2
B25
K1
W23
D7
K26
Y4
D13
N23
AC8
AF17
Not Connected Pins
A4
B17
D6
F1
G3
N2
W2
AD2
AG1
AJ8
A8
B21
D13
F4
A15
B25
A28
C8
B8
C16
D26
F30
M30
V28
B12
C17
E2
F31
N1
AC14
AC20
AE25
AF10
D20
F28
D23
F29
M28
V2
GND Pins
A1
A22
E26
W26
AF2
AF25
A2
A25
H1
AB1
AF5
AF26
A5
A26
H26
AB26
AF8
-
A8
B1
N1
AE1
AF13
-
A14
B26
P26
AE26
AF19
-
A19
E1
W1
AF1
AF22
-
M3
M4
N29
W28
AD30
AH6
AJ12
AK24
N30
W31
AD31
AH9
AJ15
AK27
W1
Y1
Y31
AC4
AF30
AJ5
AK11
-
AE4
AH19
AJ20
AL15
AF29
AH23
AJ26
AL17
Not Connected Pins
AK17
5/15/97
C8
-
-
-
-
6/16/97
XC4044XL Device Pinout Tables
(Note: XC4044XL is also available in the HQ304 package.
The pinout is identical to the XC4036XL in the HQ304. )
XC4044XL
Pad Name
I/O (A18)
I/O
HQ
160
P146
-
HQ
208
P187
P188
P189
P190
P191
-
-
-
-
HQ
BG
352
B15
C15
D15
A16
PG
411
BG
240
P216
P217
P218
P220
P221
-
-
-
-
432
D18
B18
A19
B19
C19
T2
U1
V6
U3
R1
XC4044XL
Pad Name
HQ
160
HQ
208
HQ
240
BG
352
PG
411
BG
432
I/O
-
I/O (A10)
I/O (A11)
VCC
P147
P148
-
-
-
-
VCC
P142
P143
P144
-
P183
P184
P185
-
P212
P213
P214
-
VCC*
D14
C14
-
VCC* VCC*
B16
I/O (A8)
I/O (A9)
I/O
I/O
I/O (A19)
W3
Y2
V2
W5
V4
D17
A17
C17
B17
C18
VCC*
GND*
C16
B17
VCC* VCC*
GND* GND*
U5
T4
GND
I/O
I/O
D19
A20
-
-
-
-
P145
P186
P215
A15
DS006 (v. 1.7) October 4, 1999 - Product Specification
6-137
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4044XL
Pad Name
HQ
160
HQ
208
HQ
240
BG
352
PG
411
BG
432
XC4044XL
Pad Name
HQ
160
HQ
208
HQ
240
BG
352
PG
411
BG
432
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O (A12)
I/O (A13)
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O (A14)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
D16
A18
C17
B18
VCC*
C18
D17
A20
B19
GND*
C19
D18
A21
B20
-
P2
N1
R5
M2
B20
C20
C21
A22
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O, GCK2
O (M1)
GND
I (M0)
VCC
I (M2)
I/O, GCK3
I/O (HDC)
I/O
I/O
I/O
I/O (LDC)
I/O
I/O
I/O
I/O
VCC
GND
I/O
I/O
I/O
I/O
I/O
-
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
-
-
-
-
-
-
-
-
-
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
-
M24
M25
M26
N24
A17
E19
B18
C17
C19
R31
R30
R28
R29
T31
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P25
P26
P27
P28
P29
-
-
-
-
-
P222
P223
P224
P225
P226
P227
-
-
P228
P229
-
-
P230
P231
P232
P233
VCC* VCC*
N25
L3
T6
N5
M4
B22
C22
B23
A24
GND*
VCC*
N26
P25
P23
P24
R26
R25
R24
R23
-
-
VCC*
GND*
T26
T25
T24
U25
T23
V26
VCC*
U24
V25
V24
U23
GND*
Y26
W25
W24
V23
-
-
AA26
Y25
Y24
AA25
GND*
VCC*
AB25
AA24
Y23
AC26
AD26
AC25
AA23
AB24
AD25
AC24
AB23
GND*
AD24
VCC*
AC23
AE24
AD23
AC22
AF24
AD22
AE23
AC21
AD21
AE22
AF23
VCC*
GND*
AD20
AE21
AF21
AC19
-
GND* GND*
VCC* VCC*
P149
P150
P151
-
-
-
-
-
P192
P193
P194
-
F20
B20
C21
B22
E21
D22
A23
B24
C23
F22
T30
T29
U31
U30
U28
U29
V30
V29
V28
W31
GND* GND*
K2
K4
P6
M6
L5
J5
J3
H2
H4
G3
D22
C23
B24
C24
D23
B25
A26
C25
D24
B26
-
P195
P196
-
-
P197
P198
P199
P200
-
-
-
-
-
-
-
-
P201
P202
P203
P204
P205
P2
P4
P5
P6
P7
P8
P9
-
-
-
-
-
-
-
-
-
-
P152
P153
P154
P155
-
-
-
-
-
-
-
-
P156
P157
P158
P159
P160
P1
P2
P3
P4
P5
P6
P7
-
-
-
-
-
-
-
-
P8
P9
-
-
-
-
-
-
C20
B21
B22
C21
GND*
VCC*
D20
A23
A24
B23
D21
C22
B24
C23
D22
C24
VCC*
GND*
D23
C25
D24
E23
C26
E24
D25
F23
F24
E25
VCC*
GND*
-
VCC* VCC*
GND* GND*
P37
-
-
-
-
P38
P39
P40
P41
P42
P43
P44
P45
-
A25
D24
B26
A27
C27
F24
W30
W29
Y30
Y29
Y28
-
-
-
-
-
GND* GND*
VCC* VCC*
K6
G1
E1
E3
J7
H6
C3
D2
E5
G7
A27
D25
C26
B27
C27
B28
D27
B29
C28
D28
-
-
-
-
AA30
-
VCC* VCC*
P234
P235
P236
P237
P238
P239
P240
P1
P2
P3
P4
P5
P6
P7
-
-
-
-
-
-
-
-
P33
P34
P35
P36
P37
-
-
-
-
-
E25
E27
B28
C29
AA29
AB31
AB30
AB29
GND* GND*
I/O, GCK8 (A15)
F26
D28
B30
E29
D30
D32
F28
F30
C31
E31
AB28
AC30
AC29
AC28
AD31
AD30
AD29
AD28
AE30
AE29
VCC
GND
I/O, GCK1 (A16)
I/O (A17)
I/O
VCC* VCC*
GND* GND*
-
P46
P47
-
H8
F6
B4
D4
B2
G9
F8
C5
A7
A5
D29
C30
E28
E29
D30
D31
E30
E31
G28
G29
-
-
-
-
-
I/O
P38
P39
P40
P41
-
-
-
-
P48
P49
P50
P51
-
-
-
-
I/O, TDI
I/O, TCK
I/O
I/O
I/O
P30
P31
-
-
-
GND* GND*
VCC* VCC*
I/O
B32
A33
A35
F32
C35
B38
E33
G31
H32
B36
A39
GND* GND*
E35 AH28
VCC* VCC*
G33
D36
C37
F34
J33
D38
G35
E39
K34
F38
G37
VCC* VCC*
GND* GND*
H38
J37
AF31
AE28
AG31
AF28
AG30
AG29
AH31
AG28
AH30
AJ30
AH29
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O, TMS
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
-
-
-
-
VCC* VCC*
GND* GND*
C7
D8
B8
C9
-
P32
P33
-
P42
P43
-
P52
P53
-
F30
F31
H28
H29
G30
H30
J28
J29
H31
J30
-
P10
P11
P12
P13
-
-
-
-
P14
P15
P16
P17
P18
-
-
-
-
-
-
-
-
-
-
-
P8
P9
P10
P11
P12
P13
-
D26
G24
F25
F26
H23
H24
G25
G26
GND*
J23
-
-
-
P34
P35
P36
P37
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
P48
-
P44
P45
P46
P47
P48
P49
P50
P55
P56
P57
P58
P59
P60
P61
P62
-
P54
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
P66
P67
P68
-
E9
F12
D10
B10
F10
F14
-
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
-
GND* GND*
C11
B12
E11
E15
K28
K29
K30
K31
AJ28
AK29
AH27
AK28
AJ27
AL28
AH26
AL27
AH25
AK26
AL26
J24
H25
K23
VCC*
K24
J25
P14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VCC* VCC*
F16
C13
B14
E17
E13
A15
L29
L30
M29
M31
N31
N28
J26
-
-
-
L23
L24
K25
GND*
VCC*
-
-
-
-
-
-
-
-
-
-
-
-
-
P22
-
-
-
-
GND* GND*
VCC* VCC*
-
-
-
F18
C15
B16
D16
D18
N29
N30
P30
P28
P29
P49
P50
-
-
-
P63
P64
P65
P66
-
P69
P70
P71
P72
-
AH24
AJ25
AK25
AJ24
AH23
-
-
-
L25
L26
M23
G39
M34
K36
I/O
I/O
-
P19
P23
6-138
DS006 (v. 1.7) October 4, 1999 - Product Specification
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4044XL
Pad Name
HQ
160
HQ
208
HQ
240
BG
352
PG
411
BG
432
XC4044XL
Pad Name
HQ
160
HQ
208
HQ
240
BG
352
PG
411
BG
432
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O (INIT)
VCC
GND
I/O
I/O
I/O
I/O
I/O
-
-
-
-
-
-
-
-
-
P73
P74
-
-
K38
N35
P34
J35
L37
AK24
AL24
AH22
AJ23
AK23
I/O
P77
P78
P79
P80
P81
P82
P83
P84
P85
P86
-
-
-
-
-
-
P99
P100
P101
P103
P106
P108
P109
P110
P111
P112
-
-
-
-
-
-
P117
P118
P119
P120
P121
P122
P123
P124
P125
P126
-
AD4
AC5
GND*
AD3
VCC*
AC4
AD2
AC3
AB4
AD1
AB3
AC2
AA4
AA3
AB2
AC1
VCC*
GND*
Y3
AV38
AT36
GND* GND*
AR35 AH4
VCC* VCC*
AN33
AM32
AP34
AW39
AN31
AV36
AR33
AP32
AU35
AW33
AU33
AK3
AJ4
AD19
AE20
AF20
AC18
GND*
AD18
AE19
AC17
AD17
VCC*
AE18
AF18
AC16
AD16
AE17
AE16
GND*
VCC*
AF16
AC15
AD15
AE15
AF15
AD14
-
I/O, GCK4
GND
DONE
VCC
PROGRAM
I/O (D7)
I/O, GCK5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
GND
I/O (D6)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O (D5)
I/O (CS0)
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O (D4)
I/O
VCC
GND
I/O (D3)
I/O (RS)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
GND
I/O
I/O
I/O
I/O
I/O (D2)
I/O
VCC
I/O
I/O
-
-
-
P51
P52
P53
P54
P55
-
-
-
-
-
-
-
-
-
-
-
P67
P68
P69
P70
P71
-
P72
P73
-
-
-
-
-
-
-
-
P75
P76
P77
P78
P79
P80
P81
P82
-
GND* GND*
AH3
AJ2
M38
R35
H36
T34
AJ22
AK22
AL22
AJ21
AG4
AG3
AH2
AH1
AF4
AF3
AG2
AE3
AF2
VCC* VCC*
N37
N39
U35
R39
M36
V34
GND* GND*
VCC* VCC*
R37
T38
AH20
AK21
AK20
AJ19
AL20
AH18
-
P127
P128
-
-
-
-
-
-
-
-
-
-
VCC* VCC*
GND* GND*
P83
-
-
-
P87
P88
P89
P90
-
-
-
-
P113
P114
P115
P116
-
-
P117
P118
-
-
P119
-
-
P120
P121
-
P122
P123
-
-
-
-
-
-
-
-
-
-
P124
P125
P126
P127
P128
P129
P130
P131
P132
P133
P134
P135
P136
P137
-
-
-
-
-
-
-
-
-
P129
P130
P131
P132
-
AV32
AU31
AR31
AP28
AP30
AT30
AT32
AV30
AR29
AP26
AF1
AD4
AD3
AE2
AD2
AC4
AC3
AD1
AC2
AB4
AK19
AJ18
AL19
AK18
AH17
AJ17
AK17
AL17
AJ16
AK16
AA2
AA1
W4
-
-
-
-
-
-
P84
P85
P86
P87
-
T36
V36
U37
U39
W35
AC39
V38
W37
VCC* VCC*
GND* GND*
Y34
P56
P57
-
-
P58
P59
P60
P61
P62
P63
-
-
P64
P65
-
-
-
-
-
-
-
-
-
-
P74
P75
-
-
P76
P77
P78
P79
P80
P81
-
-
P82
P83
P84
P85
-
-
-
-
-
-
-
-
-
-
P133
P134
-
W3
Y2
Y1
V4
GND*
V3
W2
U4
U3
VCC*
V2
V1
T4
T3
U2
T2
GND*
VCC*
-
-
T1
R4
R3
R2
R1
P3
P2
P1
VCC*
GND*
N2
N4
N3
M1
M2
M3
M4
-
-
-
-
P88
P89
P90
P91
P92
P93
-
AE14
AF14
VCC*
GND*
AE13
AC13
-
-
P91
-
-
P92
P93
-
P94
P95
-
-
-
-
-
-
-
-
-
-
-
-
P96
P97
P98
P99
P100
P101
P102
P103
P104
P105
-
-
-
-
-
-
P135
P136
P137
P138
P139
P140
P141
P142
-
GND* GND*
AU29
AV28
AT28
AR25
AB3
AB2
AB1
AA3
AL16
AC37 AH15
Y38
AL15
AJ15
AK15
AJ14
AH14
AK14
AL13
AK13
VCC* VCC*
-
-
AA37
AB38
AD36
AA35
AE37
AB36
AD38
VCC* VCC*
GND* GND*
AB34
AE39
AM36
AC35
AG39 AH12
AG37 AJ11
VCC* VCC*
AD34
AN39
AE35
AH38
GND* GND*
AJ37 AL8
AG35 AH10
AP24
AU27
AR27
AW27
AT24
AR23
AA2
Y2
Y4
Y3
W4
W3
P94
P95
P96
P97
-
AD13
AF12
AE12
AD12
AC12
AF11
VCC*
GND*
AE11
AD11
AE10
AC11
AF9
AD10
VCC*
AE9
AD9
AC10
AF7
I/O
I/O
I/O
I/O
-
-
-
I/O
-
-
P143
-
-
-
-
GND* GND*
VCC* VCC*
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
P98
-
-
-
-
P99
P100
P101
P102
P103
P104
P105
P106
-
AW25
AW23
AP22
AV24
AU23
AT22
AR21
AV22
AP20
AU21
W2
V2
V4
V3
U1
U2
U4
U3
T1
T2
AJ13
AH13
AL12
AK12
-
P144
P145
P146
P147
P148
P149
P150
P151
P152
P153
P154
P155
P156
P157
-
-
-
-
-
-
-
P66
P67
P68
P69
P70
-
-
-
-
-
-
-
P86
P87
P88
P89
P90
-
-
-
AL10
AK10
AJ10
AK9
VCC* VCC*
GND* GND*
GND*
AE8
AD8
AC9
AF6
AU19
AV20
AV18
AR19
AT18
AW17
AV16
AP18
AU17
AW15
T3
R1
R2
R4
R3
P2
P3
P4
N1
N2
-
P107
P108
-
AF34
AH36
AK38
AP38
AK36
AM34
AH34
AJ35
AJ9
AK8
AJ8
AH9
AK7
AL6
AJ7
AH8
-
-
-
-
-
I/O
I/O
I/O
I/O
-
P91
P92
P93
P94
-
-
-
-
P109
P110
P111
P112
-
-
-
-
AE7
AD7
AE6
AE5
GND*
VCC*
AD6
AC7
AF4
AF3
AE4
AC6
AD5
-
-
-
-
L1
-
-
VCC*
GND*
L2
L3
K2
L4
J1
K3
VCC*
J2
-
P71
P72
-
-
-
I/O
-
-
-
-
-
VCC* VCC*
GND* GND*
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND* GND*
VCC* VCC*
P158
-
-
-
-
P159
P160
P161
P162
P163
AR17
AT16
AV14
AW13
AR15
AP16
VCC* VCC*
AV12
AR13
N3
N4
M1
M2
L2
AL37
AT38
AM38
AN37
AK34
AR39
AN35
AL33
AK6
AL5
AH7
AJ6
AK5
AL4
AK4
AH5
-
P73
P74
-
P95
P96
-
P113
P114
-
-
-
P106
P107
-
P108
P109
P138
P139
-
P140
P141
L3
-
-
-
P75
P76
P97
P98
P115
P116
K1
K2
I/O
AE3
J3
DS006 (v. 1.7) October 4, 1999 - Product Specification
6-139
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4044XL
Pad Name
HQ
160
HQ
208
HQ
240
BG
352
PG
411
BG
432
XC4044XL
Pad Name
HQ
160
HQ
208
HQ
240
BG
352
PG
411
BG
432
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
-
-
-
P164
P165
P166
-
K4
G1
GND*
H2
H3
J4
F1
G2
G3
F2
E2
-
-
GND*
VCC*
F3
G4
D1
C1
D2
F4
E3
C2
D3
E4
C3
VCC*
D4
GND*
B3
C4
D5
A3
C5
B4
D6
C6
B5
A4
VCC*
GND*
C7
B6
A6
D8
C8
-
B7
A7
D9
C9
GND*
B8
AU11
AT12
GND* GND*
K3
K4
GND
6/18//97
P141
P182
P211
GND*
GND* GND*
P110
-
-
-
-
-
-
P111
P112
-
-
-
-
P113
P114
-
-
-
-
P115
P116
P117
P118
P119
P120
P121
P122
P123
P124
P125
P126
-
-
P127
P128
-
-
-
-
-
-
P129
P130
-
-
-
-
-
-
P131
P132
P133
-
-
-
-
-
P142
-
-
-
* Pads labelled GND* or VCC* are internally bonded to Ground or
VCC planes within the associated package. They have no direct
connection to any specific package pin.
AP14
AR11
AV10
AT8
AT10
AP10
AP12
AR9
AU9
AV8
GND* GND*
VCC* VCC*
AU7
AW7
AW5
AV6
AR7
AV4
AN9
AW1
AP6
AU3
AR5
J2
J3
J4
H1
H2
H3
H4
G2
G3
F1
-
P167
P168
P169
P170
P171
P172
-
-
-
-
P173
P174
-
-
-
-
P143
P144
P145
P146
-
-
-
-
P147
P148
-
-
-
-
P149
P150
P151
P152
P153
P154
P159
P160
P161
P162
P163
P164
-
-
P165
P166
-
-
-
-
-
-
P167
P168
-
-
P169
P170
-
-
P171
P172
P173
-
-
-
-
-
-
-
-
-
-
-
Additional XC4044XL Package Pins
HQ208
Not Connected Pins
P1
P104
P206
P3
P105
P207
P51
P107
P208
P52
P155
-
P53
P156
-
P54
P157
-
P102
P158
-
GND
VCC
I/O (D1)
I/O (RCLK, RDY/BUSY)
I/O
I/O
I/O
I/O
I/O
5/29/97
G4
F2
F3
E1
E3
D1
E4
D2
C2
D3
D4
HQ240
GND Pins
-
P204
P219
-
-
-
-
-
P175
P176
P177
P178
P179
P180
P181
P182
P183
P184
P185
P186
-
5/29/97
I/O
Note: These pins may be Not Connected for this device revision,
however for compatability with other devices in this package, these
pins should be tied to GND.
I/O (D0, DIN)
I/O, GCK6 (DOUT)
CCLK
VCC
O, TDO
GND
I/O (A0, WS)
I/O, GCK7 (A1)
I/O
I/O
I/O
I/O
VCC* VCC*
AN7 C4
GND* GND*
BG352
AT4
AV2
AM8
AL7
AR3
AR1
AK6
AN3
AM6
AM2
B3
D5
B4
C5
B5
C6
A5
D7
B6
A6
VCC Pins
A10
G23
U26
A17
H4
W23
AF10
B2
K1
Y4
B25
K26
AC8
-
D7
N23
AC14
-
D13
P4
AC20
-
D19
U1
AE2
-
AE25
AF17
-
GND Pins
A8
I/O (CS1,A2)
I/O (A3)
I/O
P187
P188
-
-
-
A1
A25
H26
AE1
AF19
6/13/97
A2
A26
N1
AE26
AF22
A5
B1
A14
E1
W26
AF5
-
A19
E26
AB1
AF8
-
A22
H1
AB26
AF13
-
B26
W1
AF2
AF26
P26
AF1
AF25
I/O
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
VCC* VCC*
GND* GND*
-
P189
P190
P191
P192
-
AL3
AH6
AP2
AK4
AN1
AK2
AG5
AF6
AL5
AJ3
D8
C7
B7
D9
B8
PG411
VCC Pins
A31
AA39
AW19
GND Pins
A37
-
A8
A3
J1
AT34
A11
L39
AU1
A21
W1
AW9
C39
AJ1
AW29
D6
AL39
AW37
F36
AP4
-
P193
P194
P195
-
P196
P197
P198
P199
P200
P201
-
-
-
-
-
-
-
-
D10
C9
B9
A9
A19
D34
Y4
AP36
AW11
A29
F4
C1
L1
AF4
AT20
-
D14
P4
AF36
AT26
-
D20
P36
AJ39
AU39
-
C10
D26
W39
AL1
AW3
J39
AA1
AT14
AW31
GND* GND*
Y36
AT6
AW21
AH2
AE5
AM4
AD6
B10
A10
C11
D12
D10
C10
B9
VCC*
A9
Not Connected Pins
A13
E23
P38
AP8
AU37
6/2/97
B6
E37
R3
AR37
AV26
B34
F2
C25
G5
AF38
AU5
AW35
C33
D12
L35
AL35
AU15
-
E7
N3
AN5
AU25
-
H34
AJ5
AU13
-
VCC* VCC*
AF2
AT2
AV34
AG3
AG1
AC5
AE1
AH4
AB6
B11
C12
C13
A12
D14
B13
I/O
I/O
I/O
I/O
D11
C11
B10
B11
A11
GND*
VCC*
D12
C12
B12
A12
C13
B13
-
-
-
-
-
-
-
I/O
GND
VCC
I/O (A4)
I/O (A5)
I/O
GND* GND*
VCC* VCC*
P134
P135
-
P136
P137
P138
-
P174
P175
P176
P177
P178
P179
-
P202
P203
P205
P206
P207
P208
-
AD2
AB4
AE3
AC1
AD4
AA5
AB2
AC3
AA3
Y6
C14
A13
B14
D15
C15
B15
A15
C16
B16
A16
I/O
I/O (A21)
I/O (A20)
I/O
I/O
I/O (A6)
I/O (A7)
-
-
-
-
P139
P140
P180
P181
P209
P210
A13
B14
6-140
DS006 (v. 1.7) October 4, 1999 - Product Specification
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
BG432
VCC Pins
A31
L28
AH21
-
A1
D21
AA28
AL11
A11
L1
AA31
AL21
A21
L4
AH11
AL31
C3
L31
AJ3
-
C29
AA1
AJ29
-
D11
AA4
AL1
-
GND Pins
A9
B1
G1
T28
AH16
AL2
AL25
A2
A25
C1
A3
A29
C31
P31
AE1
AK30
AL18
A7
A30
D16
T4
AE31
AK31
AL23
A14
B2
G31
V1
AJ1
AL3
AL29
A18
B30
J1
V31
AJ31
AL7
AL30
A23
B31
J31
AC1
AK1
AL9
-
P1
AC31
AK2
AL14
Not Connected Pins
A4
D20
M4
AE4
AJ12
5/29/97
A28
D26
M28
AF29
AJ20
B12
E2
M30
AF30
AJ26
B21
F4
W1
AG1
AK11
C8
D6
F29
Y1
AH19
-
D13
M3
Y31
AJ5
-
F28
W28
AH6
AK27
XC4052XL Device Pinout Tables
(Note: XC4052XL is also available in the HQ304 package.
The pinout is identical to the XC4036XL in HQ304.)
XC4052XL
Pad Name
HQ
240
-
-
-
-
-
-
PG
411
GND*
VCC*
K6
G1
E1
E3
F2
G5
GND*
J7
H6
C3
D2
E5
G7
VCC*
GND*
H8
F6
B4
D4
B2
G9
GND*
E7
BG
432
BG
560
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND*
VCC*
A27
D25
C26
B27
GND*
VCC*
C28
D27
B30
C29
E27
A31
GND*
D28
C30
D29
E28
D30
E29
VCC*
GND*
B33
XC4052XL
Pad Name
HQ
240
P212
P213
P214
-
-
-
P215
P216
P217
P218
P220
P221
-
-
-
-
-
-
-
-
-
-
PG
411
VCC*
W3
Y2
BG
432
BG
560
VCC
I/O (A8)
I/O (A9)
I/O
VCC*
D17
A17
C17
B17
GND*
C18
D18
B18
A19
B19
C19
VCC*
GND*
D19
A20
B20
C20
B21
D20
GND*
C21
A22
VCC*
B22
C22
B23
A24
GND*
D22
C23
B24
C24
GND*
D23
B25
A26
C25
D24
B26
VCC*
A17
B18
C18
E18
GND*
C19
D19
E19
B20
C20
D20
VCC*
GND*
A21
E20
B21
C21
D21
B22
GND*
C23
E22
VCC*
B24
D23
C24
A25
GND*
E23
B25
D24
C25
GND*
E25
C27
D26
B28
B29
E26
-
-
A28
D26
GND*
C27
B28
D27
B29
C28
D28
VCC*
GND*
D29
C30
E28
-
P234
P235
P236
P237
P238
P239
P240
P1
P2
P3
P4
P5
P6
P7
-
-
-
-
-
-
-
-
-
V2
I/O
W5
GND*
V4
T2
U1
V6
U3
R1
VCC*
GND*
U5
T4
P2
N1
R3
N3
GND*
R5
M2
VCC*
L3
T6
N5
M4
GND*
K2
K4
P6
M6
GND*
L5
J5
J3
H2
H4
G3
I/O
I/O
I/O
I/O (A14)
GND
I/O (A19)
I/O (A18)
I/O
I/O, GCK8 (A15)
I/O
VCC
GND
I/O, GCK1 (A16)
I/O (A17)
I/O
I/O (A10)
I/O (A11)
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O (A12)
I/O (A13)
F29
E30
I/O
E29
D31
F30
C33
GND*
G29
E31
D32
G30
F31
H29
VCC*
GND*
H30
G31
J29
F33
G32
J30
GND*
K30
H33
L29
I/O, TDI
I/O, TCK
GND
I/O
I/O
I/O
I/O
I/O
I/O
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
D30
D31
GND*
F28
F29
E30
B6
F8
C5
A7
E31
-
G28
G29
VCC*
GND*
F30
P222
P223
P224
P225
P226
P227
-
A5
VCC*
GND*
C7
D8
B8
-
-
F31
P8
P9
P10
P11
-
P12
P13
-
H28
H29
G30
H30
GND*
J28
J29
H31
J30
C9
E9
-
P228
P229
-
-
-
P230
P231
P232
P233
F12
GND*
D10
B10
F10
F14
GND*
C11
I/O
I/O
I/O
GND
I/O
-
K31
GND*
L30
P14
P15
GND*
K28
DS006 (v. 1.7) October 4, 1999 - Product Specification
6-141
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4052XL
Pad Name
HQ
240
PG
411
BG
432
BG
560
XC4052XL
Pad Name
HQ
240
PG
411
BG
432
BG
560
I/O
I/O, TMS
I/O
VCC
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
P16
P17
P18
P19
P20
P21
-
-
-
-
-
-
B12
E11
E15
VCC*
F16
C13
GND*
A13
D12
B14
E17
E13
A15
GND*
VCC*
F18
C15
B16
D16
D18
A17
GND*
E19
K29
K30
K31
VCC*
L29
L30
GND*
M30
M28
M29
M31
N31
N28
GND*
VCC*
N29
N30
P30
P28
P29
K32
J33
M29
VCC*
L32
M31
GND*
N29
L33
M32
P29
P30
N33
GND*
VCC*
P31
P32
R29
R30
R31
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
-
-
-
A33
C33
B34
A35
F32
GND*
C35
B38
AE28
AF30
AF29
AG31
AF28
GND*
AG30
AG29
AH31
AG28
AH30
AJ30
AH29
GND*
AH28
VCC*
AJ28
AK29
AH27
AK28
AJ27
AL28
AH26
GND*
AK27
AJ26
AL27
AH25
AK26
AL26
VCC*
GND*
AH24
AJ25
AK25
AJ24
AH23
AK24
GND*
AL24
AH22
AJ23
AK23
GND*
AJ22
AK22
AL22
AJ21
VCC*
AH20
AK21
GND*
AJ20
AH19
AK20
AJ19
AL20
AH18
GND*
VCC*
AK19
AJ18
AL19
AK18
AH17
AJ17
GND*
AK17
AL17
AJ16
AF29
AH31
AG30
AK32
AJ31
GND*
AG29
AL33
AH30
AK31
AJ30
AH29
AK30
GND*
AJ29
VCC*
AN32
AJ28
AK29
AL30
AK28
AM31
AJ27
GND*
AN31
AL29
AK27
AL28
AJ26
AM30
VCC*
GND*
AM29
AK26
AL27
AJ25
AN29
AN28
GND*
AL25
AJ23
AN26
AL24
GND*
AK23
AN25
AJ22
AL23
VCC*
AM24
AK22
GND*
AK21
AM22
AJ20
AL21
AN21
AK20
GND*
VCC*
AL20
AJ19
AM20
AK19
AL19
AN19
GND*
AL18
AM18
AK17
P52
P53
-
-
-
P54
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
P66
P67
P68
-
-
-
-
-
-
-
-
-
E33
I/O
I/O
G31
H32
B36
A39
GND*
E35
VCC*
G33
D36
C37
F34
I/O, GCK2
O (M1)
GND
I (M0)
VCC
I (M2)
I/O, GCK3
I/O (HDC)
I/O
I/O
I/O
I/O (LDC)
GND
I/O
-
P22
-
-
-
-
-
P23
P24
-
I/O
GND
I/O
I/O
I/O
R31
GND*
R30
R28
R29
R33
GND*
T31
T29
U32
J33
D38
G35
GND*
E37
H34
E39
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
-
P35
P36
-
-
-
B18
C17
C19
GND*
VCC*
F20
B20
C21
B22
GND*
E21
D22
A23
B24
C23
F22
VCC*
GND*
A25
D24
E23
C25
B26
A27
GND*
C27
F24
VCC*
E25
I/O
T31
U31
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
GND*
VCC*
T30
T29
U31
U30
GND*
U28
U29
V30
GND*
VCC*
U29
U30
V31
V29
GND*
V30
W33
W31
W30
W29
Y32
VCC*
GND*
Y31
K34
F38
I/O
G37
VCC*
GND*
H38
J37
G39
M34
K36
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
P69
P70
P71
P72
-
V29
V28
-
-
K38
-
-
W31
VCC*
GND*
W30
W29
W28
Y31
Y30
Y29
GND*
Y28
AA30
VCC*
AA29
AB31
AB30
AB29
GND*
AB28
AC30
AC29
AC28
GND*
AD31
AD30
AD29
AD28
AE30
AE29
GND*
VCC*
AF31
GND*
N35
P34
J35
L37
GND*
M38
R35
H36
T34
VCC*
N37
N39
GND*
P38
P73
P74
-
P37
-
-
-
-
-
-
-
P38
P39
P40
P41
P42
P43
P44
P45
-
Y30
-
AA32
AA31
AA30
AB32
GND*
AA29
AB31
VCC*
AC31
AB29
AD32
AC30
GND*
AD31
AE33
AC29
AE32
GND*
AG33
AH33
AE29
AG31
AF30
AH32
GND*
VCC*
AJ32
P75
P76
P77
P78
P79
P80
P81
P82
-
-
-
-
-
E27
B28
L35
C29
GND*
F26
D28
B30
U35
R39
M36
V34
GND*
VCC*
R37
T38
-
-
-
P46
P47
-
-
-
P48
P49
P50
P51
-
P83
-
-
E29
GND*
D30
D32
F28
F30
C31
E31
GND*
VCC*
B32
-
P84
P85
P86
P87
-
T36
V36
I/O
I/O
I/O
GND
VCC
I/O
U37
U39
GND*
W35
AC39
V38
-
-
-
-
I/O
I/O
P88
6-142
DS006 (v. 1.7) October 4, 1999 - Product Specification
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4052XL
Pad Name
HQ
240
P89
P90
P91
P92
P93
-
PG
411
W37
VCC*
GND*
Y34
AC37
Y38
BG
432
BG
560
XC4052XL
Pad Name
HQ
240
-
-
-
-
-
-
P129
P130
P131
P132
-
-
-
P133
P134
-
-
P135
P136
P137
P138
P139
P140
P141
P142
-
-
-
-
PG
411
BG
432
AG1
AE4
AE3
AF2
VCC*
GND*
AF1
AD4
AD3
AE2
AD2
AC4
GND*
AC3
AD1
AC2
AB4
GND*
AB3
AB2
AB1
AA3
VCC*
AA2
Y2
GND*
Y4
Y3
Y1
W1
W4
W3
GND*
VCC*
W2
V2
V4
V3
U1
U2
GND*
U4
U3
T1
BG
560
I/O (INIT)
VCC
GND
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
AK16
VCC*
GND*
AL16
AH15
AL15
AJ15
GND*
AK15
AJ14
AH14
AK14
AL13
AK13
VCC*
GND*
AJ13
AH13
AL12
AK12
AJ12
AK11
GND*
AH12
AJ11
VCC*
AL10
AK10
AJ10
AK9
AJ17
VCC*
GND*
AL17
AM17
AN17
AK16
GND*
AM16
AL15
AK15
AJ15
AN15
AM14
VCC*
GND*
AL14
AK14
AJ14
AN13
AM13
AL13
GND*
AK12
AN11
VCC*
AJ12
AL11
AK11
AM10
GND*
AL10
AJ11
AN9
I/O
I/O
I/O
I/O
VCC
GND
I/O (D6)
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
GND
I/O
I/O
AV34
AW35
AW33
AU33
VCC*
GND*
AV32
AU31
AR31
AP28
AP30
AT30
GND*
AT32
AV30
AR29
AP26
GND*
AU29
AV28
AT28
AR25
VCC*
AP24
AU27
GND*
AR27
AW27
AU25
AV26
AT24
AR23
GND*
VCC*
AW25
AW23
AP22
AV24
AU23
AT22
GND*
AR21
AV22
AP20
AU21
VCC*
GND*
AU19
AV20
AV18
AR19
GND*
AT18
AW17
AV16
AP18
AU17
AW15
VCC*
GND*
AR17
AT16
AV14
AW13
AU15
AU13
GND*
AR15
AP16
VCC*
AG4
AH3
AF5
AJ2
VCC*
GND*
AJ1
AF4
AG3
AE5
AH1
AF3
GND*
AE3
AC5
AE1
AD3
GND*
AC4
AD2
AB5
AC3
VCC*
AA5
AB3
GND*
AB2
AA4
AA3
Y5
Y3
Y2
GND*
VCC*
W5
W4
W3
W1
V3
V5
GND*
V4
V2
U5
-
-
AA37
GND*
AB38
AD36
AA35
AE37
AB36
AD38
VCC*
GND*
AB34
AE39
AM36
AC35
AL35
AF38
GND*
AG39
AG37
VCC*
AD34
AN39
AE35
AH38
GND*
AJ37
AG35
AF34
AH36
GND*
AK38
AP38
AK36
AM34
AH34
AJ35
GND*
VCC*
AL37
AT38
AM38
AN37
AK34
AR39
GND*
AR37
AU37
AN35
AL33
AV38
AT36
GND*
AR35
VCC*
P94
P95
P96
P97
-
-
-
P98
-
-
-
-
-
-
-
P99
P100
P101
P102
P103
P104
P105
P106
-
I/O
I/O
VCC
I/O (D5)
I/O (CS0)
GND
I/O
I/O
I/O
I/O
I/O
-
-
-
GND*
AL8
AH10
AJ9
AK8
GND*
AJ8
AH9
AK7
AL6
AJ7
I/O
-
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O (D4)
I/O
VCC
GND
I/O (D3)
I/O (RS)
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O (D2)
I/O
P143
-
-
-
-
P107
P108
-
-
-
P109
P110
P111
P112
-
AK10
GND*
AN7
AJ9
AL7
AK8
AN6
AM6
GND*
VCC*
AJ8
-
P144
P145
-
P146
P147
P148
P149
P150
P151
P152
P153
P154
P155
-
P156
P157
-
-
AH8
GND*
VCC*
AK6
AL5
AH7
AJ6
AK5
AL4
GND*
AH6
AJ5
AK4
AH5
AK3
AJ4
GND*
AH4
VCC*
AH3
AJ2
-
-
-
T2
U4
AL6
AK7
VCC*
GND*
T3
R1
R2
R4
GND*
R3
P2
P3
P4
N1
VCC*
GND*
U3
T2
T4
R1
GND*
R3
R4
R5
P2
P3
P113
P114
-
-
-
AM5
AM4
AJ7
GND*
AL5
AK6
AN3
AK5
AJ6
-
-
P115
P116
P117
P118
P119
P120
P121
P122
P123
P124
P125
P126
-
I/O, GCK4
GND
DONE
VCC
PROGRAM
I/O (D7)
I/O, GCK5
I/O
AL4
GND*
AJ5
-
-
-
N2
P4
VCC*
GND*
N3
N4
M1
M2
M3
M4
GND*
L2
VCC*
GND*
N1
P5
N2
N3
N5
M3
GND*
M4
VCC*
P158
-
-
-
-
-
-
-
AN33
AM32
AP34
AW39
AN31
AV36
AR33
GND*
AP32
AU35
AM1
AH5
AJ4
AK3
AH4
AL1
AG5
GND*
AJ3
AG4
AG3
AH2
AH1
AF4
GND*
AF3
AG2
I/O
I/O
I/O
GND
I/O
-
-
P159
P160
P161
P127
P128
L3
VCC*
L1
VCC*
I/O
AK2
VCC
DS006 (v. 1.7) October 4, 1999 - Product Specification
6-143
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4052XL
Pad Name
HQ
240
PG
411
BG
432
BG
560
XC4052XL
Pad Name
HQ
240
PG
411
BG
432
BG
560
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O (D1)
I/O (RCLK, RDY/BUSY)
I/O
I/O
I/O
I/O
GND
I/O
I/O
P162
P163
P164
P165
P166
-
-
P167
P168
-
P169
P170
P171
P172
AV12
AR13
AU11
AT12
GND*
AP14
AR11
AV10
AT8
GND*
AT10
AP10
AP12
AR9
AU9
AV8
GND*
VCC*
AU7
AW7
AW5
AV6
AU5
AP8
GND*
AR7
AV4
K1
K2
K3
K4
GND*
J2
J3
J4
H1
GND*
H2
K2
L4
J1
K3
GND*
L5
J2
K4
J3
GND*
G1
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O (A4)
I/O (A5)
I/O
-
-
-
-
-
-
-
-
AF2
AJ5
D13
B12
C13
A12
D14
B13
GND*
VCC*
C14
A13
B14
D15
C15
B15
GND*
A15
C16
B16
A16
GND*
C13
E14
A13
D14
C14
B14
GND*
VCC*
E15
D15
C15
A15
C16
E16
GND*
B17
C17
E17
D17
GND*
AC5
AE1
AH4
AB6
GND*
VCC*
AD2
AB4
AE3
AC1
AD4
AA5
GND*
AB2
AC3
AA3
Y6
P202
P203
P205
P206
P207
P208
-
H3
H4
G2
G3
F1
J5
G3
H4
I/O
I/O (A21)
I/O (A20)
GND
I/O
-
-
-
-
F1
F2
-
-
GND*
VCC*
G4
F2
F3
E1
F4
E2
GND*
E3
GND*
VCC*
F3
G4
D2
E3
G5
C1
GND*
F4
I/O
I/O (A6)
I/O (A7)
GND
6/20/97
P209
P210
P211
P173
P174
-
-
-
-
-
-
GND*
* Pads labelled GND* or VCC* are internally bonded to Ground or
VCC planes within the associated package. They have no direct
connection to any specific package pin.
Additional XC4052XL Package Pins
-
D1
D3
HQ240
I/O
I/O
P175
P176
P177
P178
P179
P180
P181
P182
P183
P184
P185
P186
-
AN9
AW1
AP6
AU3
AR5
VCC*
AN7
GND*
AT4
E4
D2
C2
D3
D4
VCC*
C4
GND*
B3
D5
B4
C5
A4
D6
GND*
B5
C6
A5
D7
B6
A6
VCC*
GND*
D8
C7
B7
D9
B8
B3
F5
E4
D4
C4
VCC*
E6
GND*
D5
A2
D6
A3
E7
C5
GND*
B4
D7
C6
E8
B5
A5
VCC*
GND*
D8
C7
E9
A6
B7
GND Pins
P204
6/3/97
P219
-
-
-
-
-
I/O (D0, DIN)
I/O, GCK6 (DOUT)
CCLK
VCC
O, TDO
GND
I/O (A0, WS)
I/O, GCK7 (A1)
I/O
I/O
I/O
I/O
GND
I/O
Note: These pins may be Not Connected for this device revision,
however for compatability with other devices in this package, these
pins should be tied to GND.
PG411
AV2
AM8
AL7
VCC Pins
A3
J1
AT34
A11
L39
AU1
A21
W1
AW9
A31
AA39
AW19
GND Pins
A37
J39
AA1
AT14
AW31
C39
AJ1
AW29
D6
AL39
AW37
F36
AP4
-
AT2
-
-
-
-
AN5
GND*
AR3
AR1
AK6
AN3
AM6
AM2
VCC*
GND*
AL3
AH6
AP2
AK4
AN1
AK2
GND*
AG5
AF6
A9
A19
D34
Y4
AP36
AW11
A29
F4
Y36
AT6
AW21
C1
LI
AF4
AT20
-
D14
P4
AF36
AT26
-
D20
P36
AJ39
AU39
-
D26
W39
AL1
AW3
I/O
I/O (CS1, A2)
I/O (A3)
I/O
P187
P188
-
-
-
6/3/97
I/O
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
BG432
-
VCC Pins
A31
L28
AH21
-
GND Pins
A9
B1
G1
T28
AH16
AL2
P189
P190
P191
P192
-
A1
D21
AA28
AL11
A11
L1
AA31
AL21
A21
L4
AH11
AL31
C3
L31
AJ3
-
C29
AA1
AJ29
-
D11
AA4
AL1
-
-
-
A8
D9
A2
A25
C1
A3
A29
C31
P31
AE1
AK30
AL18
A7
A30
D16
T4
AE31
AK31
AL23
A14
B2
G31
V1
AJ1
AL3
AL29
A18
B30
J1
V31
AJ31
AL7
AL30
A23
B31
J31
AC1
AK1
AL9
-
GND*
D10
C9
GND*
E11
A9
P193
P194
P195
-
P196
P197
P198
P199
P200
P201
-
P1
AL5
AJ3
B9
C10
D11
GND*
B10
E12
C11
B11
VCC*
D12
A11
GND*
AC31
AK2
AL14
C10
GND*
B10
A10
C11
D12
VCC*
B11
C12
GND*
GND*
AH2
AE5
AM4
AD6
VCC*
AG3
AG1
GND*
AL25
Not Connected Pins
C8
6/3/97
-
-
-
-
-
-
I/O
GND
-
-
6-144
DS006 (v. 1.7) October 4, 1999 - Product Specification
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
PG560
VCC Pins
A22
C3
K33
AA2
AL2
A4
B13
D33
A10
B19
E5
A16
B32
H1
W32
AK33
AM32
-
A26
C31
M1
AB33
AL3
AN8
-
A30
C32
N32
AD1
AL31
AN12
-
B2
D1
R2
AF33
AM2
AN18
-
T33
V1
AK1
AM15
AN24
AK4
AM21
AN30
AN4
-
GND Pins
A18
B9
F32
P1
A7
A32
B31
K1
V33
AE2
AM7
AN5
A12
B1
C2
L2
W2
AG1
AM11
AN10
A14
B6
E1
M33
Y1
AG32
AM19
AN14
A20
B15
G2
A24
B23
G33
A29
B27
J32
P33
R32
T1
Y33
AB1
AJ33
AM28
AN20
AC32
AL32
AM33
AN22
AD33
AM3
AN2
AN27
AH2
AM25
AN16
Not Connected Pins
A1
B8
C22
D25
E33
J31
M30
T32
AA1
AD4
AF1
AJ16
AK24
AL26
AN1
6/20/97
A8
B12
C26
E2
H2
K5
A19
A23
B26
D13
E13
H5
A27
A28
C9
D18
E24
H32
M2
A33
C12
D22
E32
J4
B16
D10
E10
H3
K29
N30
U2
AB4
AD29
AF31
AJ21
AL8
AM9
AN33
C8
D16
E21
H31
L31
T3
V32
AC1
AE4
AG2
AK9
AL12
AM23
-
L3
M5
T30
N4
U1
N31
U33
AB30
AD30
AF32
AJ24
AL9
AM12
-
T5
Y4
Y29
AC33
AE31
AJ13
AK18
AL22
AM27
-
AA33
AD5
AF2
AJ18
AK25
AM8
AN23
AC2
AE30
AJ10
AK13
AL16
AM26
-
XC4062XL Device Pinout Tables
(Note: XC4062XL is also available in the HQ304 package.
The pinout is identical to the XC4036XL in HQ304.)
XC4062XL
Pad Name
HQ240
BG432
PG475
BG560
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
P224
P225
P226
P227
-
-
P228
P229
-
-
-
-
-
P230
P231
P232
P233
-
-
-
-
-
-
-
-
-
C22
B23
A24
GND*
D22
C23
B24
C24
-
P4
R7
M2
GND*
M4
L3
N5
K2
L5
J1
GND*
M6
K4
J3
J5
H2
G1
GND*
VCC*
L7
K6
E1
H4
G5
F2
GND*
H6
C3
F4
D23
C24
A25
GND*
E23
B25
D24
C25
B26
E24
GND*
E25
C27
D26
B28
B29
E26
GND*
VCC*
C28
D27
B30
C29
E27
A31
GND*
D28
C30
D29
E28
XC4062XL
Pad Name
HQ240
BG432
PG475
BG560
VCC
I/O (A8)
I/O (A9)
I/O
I/O
I/O
I/O
GND
I/O (A19)
I/O (A18)
I/O
P212
P213
P214
-
-
-
-
-
P215
P216
P217
P218
P220
P221
-
-
-
-
-
-
-
-
-
-
VCC*
D17
A17
C17
B17
-
VCC*
Y2
Y4
W5
Y6
U3
W3
GND*
W1
U5
W7
U7
V2
V4
VCC*
GND*
V6
R1
T6
R3
R5
VCC*
A17
B18
C18
E18
D18
A19
GND*
C19
D19
E19
-
-
GND*
D23
B25
A26
C25
D24
B26
GND*
VCC*
A27
D25
C26
B27
A28
D26
GND*
C27
B28
D27
B29
GND*
C18
D18
B18
A19
B19
C19
VCC*
GND*
D19
A20
B20
C20
B21
D20
GND*
C21
A22
VCC*
B22
I/O
B20
I/O (A12)
I/O (A13)
GND
VCC
I/O
I/O (A10)
I/O (A11)
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
VCC
I/O
C20
D20
VCC*
GND*
A21
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
E20
B21
C21
D21
B22
GND*
C23
E22
T4
GND*
P2
N1
VCC*
N3
P234
P235
P236
P237
-
P222
P223
VCC*
B24
I/O
C5
DS006 (v. 1.7) October 4, 1999 - Product Specification
6-145
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4062XL
Pad Name
XC4062XL
Pad Name
HQ240
BG432
PG475
BG560
HQ240
BG432
PG475
BG560
I/O (A14)
P238
P239
P240
P1
P2
P3
P4
P5
P6
P7
-
-
-
-
-
-
C28
D28
VCC*
GND*
D29
C30
E28
E29
D30
D31
GND*
F28
F29
E30
E31
G28
G29
VCC*
GND*
F30
F31
H28
H29
G30
H30
GND*
-
E3
E5
VCC*
GND*
G7
D4
A5
B4
D6
F8
GND*
B6
E7
D8
G9
E9
A7
D30
E29
VCC*
GND*
B33
F29
E30
D31
F30
C33
GND*
G29
E31
D32
G30
F31
H29
VCC*
GND*
H30
G31
J29
F33
G32
J30
GND*
H32
J31
K30
H33
L29
K31
GND*
L30
K32
J33
M29
VCC*
L32
M31
GND*
N29
L33
M32
P29
P30
N33
GND*
VCC*
P31
P32
R29
R30
R31
R33
GND*
T31
GND
I/O
I/O
I/O
I/O
I/O
I/O
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O, GCK2
O (M1)
GND
I (M0)
VCC
I (M2)
I/O, GCK3
I/O (HDC)
I/O
-
GND*
U28
U29
V30
V29
V28
W31
VCC*
GND*
W30
W29
W28
Y31
Y30
Y29
GND*
Y28
AA30
VCC*
AA29
AB31
AB30
AB29
GND*
AB28
AC30
AC29
AC28
-
GND*
C23
F24
GND*
V30
W33
W31
W30
W29
Y32
VCC*
GND*
Y31
I/O GCK8 (A15)
VCC
GND
I/O, GCK1 (A16)
I/O (A17)
I/O
P35
P36
-
-
-
-
-
P37
-
-
-
-
-
-
-
P38
P39
P40
P41
P42
P43
P44
P45
-
A23
E25
G23
B24
VCC*
GND*
D24
C25
D28
A27
E29
C27
GND*
G25
D26
VCC*
F26
B28
D30
A29
GND*
C29
G27
F30
I/O
I/O, TDI
I/O, TCK
GND
I/O
I/O
I/O
I/O
I/O
I/O
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O, TMS
I/O
VCC
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
Y30
AA32
AA31
AA30
AB32
GND*
AA29
AB31
VCC*
AC31
AB29
AD32
AC30
GND*
AD31
AE33
AC29
AE32
AD30
AE31
GND*
AG33
AH33
AE29
AG31
AF30
AH32
GND*
VCC*
AJ32
AF29
AH31
AG30
AK32
AJ31
GND*
AG29
AL33
AH30
AK31
AJ30
AH29
AK30
GND*
AJ29
VCC*
AN32
AJ28
AK29
AL30
AK28
AM31
AJ27
GND*
AN31
AL29
AK27
AL28
AJ26
AM30
-
-
-
-
-
VCC*
GND*
B8
C9
P8
P9
P10
P11
-
G11
D10
E11
A9
GND*
B10
C11
F12
D12
A11
G15
GND*
B12
E13
C13
A13
VCC*
B14
C15
GND*
G17
F14
D16
D14
A15
C17
GND*
VCC*
D18
B18
F16
G19
E17
E19
GND*
A19
F18
C19
D20
F20
B20
GND*
VCC*
C21
A21
D22
B22
E23
F22
-
-
-
P46
P47
-
-
-
-
B30
E31
C31
GND*
F28
P12
P13
-
J28
J29
H31
J30
-
GND*
AD31
AD30
AD29
AD28
AE30
AE29
GND*
VCC*
AF31
AE28
AF30
AF29
AG31
AF28
GND*
AG30
AG29
AH31
AG28
AH30
AJ30
AH29
GND*
AH28
VCC*
AJ28
AK29
AH27
AK28
AJ27
AL28
AH26
GND*
AK27
AJ26
AL27
AH25
AK26
AL26
-
-
-
P14
P15
P16
P17
P18
P19
P20
P21
-
-
-
-
-
GND*
K28
K29
K30
K31
VCC*
L29
L30
GND*
M30
M28
M29
M31
N31
N28
GND*
VCC*
N29
N30
P30
P28
P29
R31
GND*
R30
R28
-
D32
B32
G31
A33
C33
GND*
VCC*
B34
A35
E33
D34
D36
B36
GND*
F34
D38
C37
G37
B38
F38
A39
GND*
E35
VCC*
G33
J37
P48
P49
P50
P51
-
-
-
-
-
-
P52
P53
-
-
-
-
-
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
P22
-
-
-
-
P54
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
P66
P67
P68
-
-
P23
P24
-
P25
P26
-
I/O
I/O
I/O
I/O
T29
T30
T32
G35
K36
C39
K38
C41
GND*
D40
L37
-
-
P27
P28
P29
P30
P31
P32
-
R29
T31
GND*
VCC*
T30
T29
-
U32
U31
GND*
VCC*
U29
U30
U33
V32
V31
V29
I/O
I/O
I/O (LDC)
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
-
-
-
-
-
-
H36
M36
J35
-
-
P33
P34
U31
U30
I/O
E41
6-146
DS006 (v. 1.7) October 4, 1999 - Product Specification
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4062XL
Pad Name
XC4062XL
Pad Name
HQ240
BG432
PG475
BG560
HQ240
BG432
PG475
BG560
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
-
-
VCC*
GND*
AH24
AJ25
AK25
AJ24
AH23
AK24
GND*
-
VCC*
GND*
F40
H38
N37
L35
R35
G41
GND*
H40
P38
J39
R37
J41
K40
GND*
L39
M38
T36
M40
VCC*
N39
N41
GND*
P40
T38
U35
U37
R39
VCC*
GND*
AM29
AK26
AL27
AJ25
AN29
AN28
GND*
AM26
AK24
AL25
AJ23
AN26
AL24
GND*
AK23
AN25
AJ22
AL23
VCC*
AM24
AK22
GND*
AK21
AM22
AJ20
AL21
AN21
AK20
GND*
VCC*
AL20
AJ19
AM20
AK19
AL19
AN19
GND*
AJ18
AK18
AL18
AM18
AK17
AJ17
VCC*
GND*
AL17
AM17
AN17
AK16
AJ16
AL16
GND*
AM16
AL15
AK15
AJ15
AN15
AM14
VCC*
GND*
AL14
AK14
AJ14
AN13
AM13
AL13
GND*
AK12
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
P100
P101
P102
P103
P104
P105
P106
-
AJ11
VCC*
AL10
AK10
AJ10
AK9
GND*
AL8
AH10
AJ9
AK8
-
AH40
VCC*
AJ41
AJ39
AJ37
AG35
GND*
AK40
AK38
AL37
AL39
AM38
AM40
GND*
AN41
AM36
AK36
AU41
AN39
AP40
GND*
VCC*
AR41
AL35
AV40
AN37
AT38
AP38
GND*
AT40
AW39
AP36
AU37
AR37
AU39
GND*
AR35
VCC*
AN35
AU35
AV38
AT34
BA39
AU33
AY38
GND*
AV36
AR31
AR33
AV32
BA37
AY36
VCC*
GND*
AV34
BA35
AU31
AY34
AT30
AW33
GND*
BA33
AV30
AY32
AU29
AW31
BA31
GND*
AR27
AT28
AN11
VCC*
AJ12
AL11
AK11
AM10
GND*
AL10
AJ11
AN9
AK10
AM9
AL9
P69
P70
P71
P72
-
-
-
-
-
P107
P108
-
-
-
-
-
P109
P110
P111
P112
-
-
-
-
P113
P114
-
-
-
-
-
P115
P116
P117
P118
P119
P120
P121
P122
P123
P124
P125
P126
-
-
-
P73
P74
-
-
P75
P76
P77
P78
P79
P80
P81
P82
-
-
-
-
AL24
AH22
AJ23
AK23
GND*
AJ22
AK22
AL22
AJ21
VCC*
AH20
AK21
GND*
AJ20
AH19
AK20
AJ19
AL20
AH18
GND*
VCC*
AK19
AJ18
AL19
AK18
AH17
AJ17
GND*
-
-
GND*
AJ8
AH9
AK7
AL6
GND*
AN7
AJ9
AL7
AK8
AN6
AM6
GND*
VCC*
AJ8
AJ7
I/O
AH8
GND*
VCC*
AK6
AL5
AH7
AJ6
AK5
AL4
GND*
AH6
AJ5
AK4
AH5
AK3
AJ4
GND*
AH4
VCC*
AH3
AJ2
AG4
AG3
AH2
AH1
AF4
GND*
AF3
AG2
AG1
AE4
AE3
AF2
VCC*
GND*
AF1
AD4
AD3
AE2
AD2
AC4
GND*
-
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O, GCK4
GND
DONE
VCC
PROGRAM
I/O (D7)
I/O, GCK5
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
AL6
AK7
AM5
AM4
AJ7
GND*
AL5
AK6
AN3
AK5
AJ6
AL4
GND*
AJ5
VCC*
AM1
AH5
AJ4
AK3
AH4
AL1
-
-
-
I/O
R41
GND
VCC
I/O
I//O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O (INIT)
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
P83
-
-
-
P84
P85
P86
P87
-
-
-
-
GND*
VCC*
V36
U39
V38
V40
W37
W35
GND*
W41
Y36
W39
AB36
Y40
-
AK17
AL17
AJ16
AK16
VCC*
GND*
AL16
AH15
AL15
AJ15
-
-
P88
P89
P90
P91
P92
P93
-
-
Y38
-
-
AG5
GND*
AJ3
AK2
AG4
AH3
AF5
VCC*
GND*
AA39
AB38
AB40
AC37
AC39
AC41
GND*
AD36
AC35
AE37
AD40
AD38
AE39
VCC*
GND*
AG41
AG39
AG37
AE35
AH38
AF38
GND*
AF36
P127
P128
-
-
-
-
-
-
P129
P130
P131
P132
-
-
-
-
-
-
-
-
I/O
AJ2
-
VCC
GND
I/O (D6)
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
VCC*
GND*
AJ1
GND*
AK15
AJ14
AH14
AK14
AL13
AK13
VCC*
GND*
AJ13
AH13
AL12
AK12
AJ12
AK11
GND*
AH12
P94
P95
P96
P97
-
-
-
P98
-
-
-
-
-
-
-
AF4
AG3
AE5
AH1
AF3
GND*
AF1
AD4
AE3
AC5
AE1
AD3
GND*
AC4
AD2
I/O
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
-
P133
P134
-
AC3
AD1
AC2
AB4
GND*
AB3
AB2
-
P135
P136
P137
P99
DS006 (v. 1.7) October 4, 1999 - Product Specification
6-147
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4062XL
Pad Name
XC4062XL
Pad Name
HQ240
BG432
PG475
BG560
HQ240
BG432
PG475
BG560
I/O
I/O
P138
P139
P140
P141
P142
P143
-
-
-
-
-
-
-
-
-
-
AB1
AA3
VCC*
AA2
Y2
GND*
Y4
Y3
AY30
AW29
VCC*
BA29
AY28
GND*
AR25
AV28
AW27
AT26
AV26
BA27
GND*
VCC*
AW25
AV24
AU25
AR23
AT24
AY24
GND*
BA23
AU23
AW23
AV20
AY22
AV22
VCC*
GND*
AW21
BA21
AU19
AY20
AU17
AW19
GND*
BA19
AT16
AR19
AV14
AY18
AV18
VCC*
GND*
AT18
AW17
AR15
BA15
AT14
AR17
GND*
AW15
AV16
VCC*
AY14
BA13
AU13
AW13
GND*
AY12
BA11
AV12
AT12
AW11
AY10
GND*
BA9
AB5
AC3
VCC*
AA5
AB3
GND*
AB2
AA4
AA3
Y5
I/O
I/O
GND
VCC
I/O (D1)
I/O (RCLK, RDY/BUSY)
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
-
-
-
-
G3
F1
GND*
VCC*
G4
F2
F3
E1
F4
E2
GND*
E3
D1
E4
D2
C2
D3
D4
VCC*
C4
GND*
B3
D5
B4
C5
A4
D6
GND*
B5
AY8
BA7
GND*
VCC*
AV8
AY6
AR11
AT8
H4
F2
GND*
VCC*
F3
G4
D2
E3
G5
C1
GND*
F4
D3
B3
F5
E4
D4
C4
VCC*
E6
GND*
D5
A2
D6
A3
E7
C5
GND*
B4
VCC
I/O (D5)
I/O (CS0)
GND
I/O
I/O
I/O
I/O
I/O
P173
P174
-
-
-
-
-
-
Y1
AU9
AW5
GND*
AY4
BA5
AV4
AR9
AU5
AV6
AR5
VCC*
AN7
GND*
AR7
AW3
AU3
AW1
AP6
AV2
GND*
AT4
W1
W4
W3
GND*
VCC*
W2
V2
V4
V3
U1
U2
GND*
U4
U3
-
-
T1
T2
VCC*
GND*
T3
R1
-
-
R2
R4
GND*
R3
P2
P3
P4
N1
N2
VCC*
GND*
N3
Y3
Y2
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O (D4)
I/O
VCC
GND
I/O (D3)
I/O (RS)
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
GND*
VCC*
W5
W4
W3
W1
V3
V5
GND*
V4
-
P175
P176
P177
P178
P179
P180
P181
P182
P183
P184
P185
P186
-
-
-
-
I/O (D0, DIN)
I/O, GCK6 (DOUT)
-
-
CCLK
VCC
O, TDO
GND
I/O (A0, WS)
I/O, GCK7 (A1)
I/O
I/O
I/O
I/O
GND
I/O
P144
P145
-
P146
P147
-
-
P148
P149
P150
P151
P152
P153
-
-
P154
P155
-
P156
P157
-
-
-
-
-
P158
-
-
-
-
-
-
-
P159
P160
P161
P162
P163
P164
P165
P166
-
V2
U2
U1
U5
U4
VCC*
GND*
U3
T2
T3
T5
T4
R1
GND*
R3
I/O
-
C6
A5
D7
B6
AN5
AU1
AM6
AT2
D7
C6
E8
B5
I/O (CS1, A2)
I/O (A3)
I/O
P187
P188
-
-
-
-
P189
P190
P191
P192
-
-
-
-
I/O
A6
AL7
A5
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
VCC*
GND*
D8
C7
B7
D9
B8
A8
GND*
-
VCC*
GND*
AR1
AP2
AM4
AN3
AL5
AK6
GND*
AN1
AJ5
AM2
AH4
AL3
AK4
GND*
AG7
AG5
AK2
AJ3
VCC*
AJ1
AF6
GND*
AH2
AF4
AE7
AE5
AG3
AG1
GND*
VCC*
AD6
AD4
AE3
AC5
VCC*
GND*
D8
C7
E9
A6
B7
D9
GND*
D10
C9
E11
A9
C10
D11
GND*
B10
E12
C11
B11
VCC*
D12
A11
GND*
C13
E14
A13
D14
C14
B14
GND*
VCC*
E15
D15
C15
A15
R4
R5
P2
P3
I/O
P4
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O (D2)
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
VCC*
GND*
N1
P5
N2
N3
N5
M3
GND*
M4
L1
VCC*
K2
L4
J1
K3
GND*
L5
J2
K4
-
-
N4
P193
P194
P195
-
P196
P197
P198
P199
P200
P201
-
-
-
-
-
-
D10
C9
B9
M1
M2
M3
M4
GND*
L2
L3
VCC*
K1
K2
K3
K4
GND*
J2
C10
GND*
B10
A10
C11
D12
VCC*
B11
C12
GND*
D13
B12
C13
A12
D14
B13
GND*
VCC*
C14
A13
B14
D15
-
J3
J4
H1
-
P167
P168
-
-
-
P169
P170
P171
P172
-
-
-
-
-
J3
H2
K5
GND*
G1
F1
J5
G3
I/O
-
GND
VCC
I/O (A4)
I/O (A5)
I/O
GND*
H2
H3
H4
G2
P202
P203
P205
P206
AU11
AW9
AV10
I/O
I/O
6-148
DS006 (v. 1.7) October 4, 1999 - Product Specification
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4062XL
Pad Name
I/O (A21)
I/O (A20)
GND
I/O
PG475
HQ240
BG432
PG475
BG560
VCC Pins
B26
P207
P208
-
-
-
-
-
P209
P210
P211
C15
B15
GND*
-
AD2
AC7
GND*
AC1
AC3
AB6
AB2
AB4
AA3
GND*
C16
E16
GND*
D16
B16
B17
C17
E17
A37
E21
N35
AA41
AR29
AW41
B2
F6
T2
AF2
AT6
AY2
B16
F36
B40
G29
D2
N7
G13
AA1
T40
AA5
AA37
AR13
AW37
BA3
AF40
AT22
AY16
AJ7
AT36
AY26
AJ35
AU21
AY40
I/O
I/O
I/O
-
A15
C16
B16
A16
GND*
GND Pins
I/O (A6)
I/O (A7)
GND
6/16/97
A3
U1
AH6
E15
L41
AL41
AU15
E37
C1
A17
AL1
E27
P36
AR21
AU27
E39
C7
A25
G3
A41
L1
P6
D17
GND*
AA7
BA1
G21
AE41
AT20
BA25
AP4
AE1
C35
G39
AH36
AT32
BA41
AU7
AR3
F10
AW7
F32
U41
AA35
AT10
BA17
J7
* Pads labelled GND* or VCC* are internally bonded to Ground or
VCC planes within the package. They have no direct connection to
any specific package pin.
AR39
AW35
A31
5/5/97
Additional XC4062XL Package Pins
HQ240
GND Pins
BG560
P204
5/5/97
P219
-
-
-
-
VCC Pins
A4
B13
D33
A10
B19
E5
A16
B32
H1
W32
AK33
AM32
-
A22
C3
K33
AA2
AL2
AN4
-
A26
C31
M1
AB33
AL3
AN8
-
A30
C32
N32
AD1
AL31
AN12
-
B2
D1
R2
AF33
AM2
AN18
-
Note: These pins may be Not Connected for this device revision,
however for compatability with other devices in this package, these
pins should be tied to GND.
T33
V1
AK1
AM15
AN24
AK4
AM21
AN30
BG432
GND Pins
A18
VCC Pins
A7
A32
B31
K1
V33
AE2
AM11
AN5
A12
B1
C2
L2
W2
AG1
AM19
AN10
A14
B6
E1
M33
Y1
AG32
AM25
AN14
A20
B15
G2
A24
B23
G33
A29
B27
J32
A1
D21
AA28
AL11
A11
L1
AA31
AL21
A21
L4
AH11
AL31
A31
L28
AH21
-
GND Pins
A9
B1
G1
T28
AH16
AL2
C3
L31
AJ3
-
C29
AA1
AJ29
-
D11
AA4
AL1
-
B9
F32
P1
Y33
AH2
AM28
AN16
P33
R32
T1
AB1
AJ33
AM33
AN20
AC32
AL32
AM7
AN22
AD33
AM3
AN2
AN27
A2
A25
C1
A3
A29
C31
P31
AE1
AK30
AL18
A7
A30
D16
T4
AE31
AK31
AL23
A14
B2
G31
V1
AJ1
AL3
AL29
A18
B30
J1
A23
B31
J31
AC1
AK1
AL9
-
Not Connected Pins
P1
V31
AJ31
AL7
AL30
A1
B12
D25
H3
M2
A8
C8
E2
H5
M5
AA1
AD5
AG2
AK25
AM23
A23
C12
E10
H31
M30
AA33
AD29
AJ10
AL8
A27
C22
E13
J4
A28
C26
E21
K29
N30
AB30
AE30
AJ21
AL22
AN23
A33
D13
E32
B8
D22
E33
L31
Y4
AC2
AF31
AK9
AM8
-
AC31
AK2
AL14
AL25
L3
Not Connected Pins
N4
N31
AC1
AF2
AJ24
AL26
AN33
C8
5/5/97
-
-
-
-
-
-
Y29
AB4
AE4
AJ13
AL12
AN1
AC33
AF32
AK13
AM12
5/5/97
AM27
XC4085XL Device Pinout Tables
XC4085XL
Pad Name
I/O (A11)
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
XC4085XL
Pad Name
VCC
I/O (A8)
I/O (A9)
I/O
I/O
I/O
I/O
GND
I/O (A19)
I/O (A18)
I/O
BG432
BG560
PG559
BG432
BG560
PG559
C19
VCC*
GND*
D19
A20
B20
C20
B21
D20
-
D20
VCC*
GND*
A21
E20
B21
C21
D21
B22
W7
VCC*
GND*
W5
V6
V4
Y2
U3
U7
V2
U5
GND*
T4
VCC
D17
A17
C17
B17
-
VCC*
A17
B18
C18
E18
D18
A19
GND*
C19
D19
E19
B20
C20
VCC*
AB6
AB4
AA7
AC1
AA5
AA3
GND*
Y8
AB2
Y6
AA1
Y4
-
GND*
C18
D18
B18
A19
B19
E21
-
C22
GND*
D22
GND*
-
I/O
I/O (A10)
DS006 (v. 1.7) October 4, 1999 - Product Specification
6-149
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4085XL
Pad Name
XC4085XL
Pad Name
BG432
BG560
PG559
BG432
BG560
PG559
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O (A12)
I/O (A13)
GND
VCC
I/O
I/O
I/O
I/O
I/O
-
A23
C23
E22
VCC*
B24
D23
C24
A25
GND*
E23
B25
D24
C25
B26
E24
C26
D25
GND*
VCC*
A27
A28
E25
C27
D26
B28
B29
E26
GND*
VCC*
C28
D27
B30
C29
E27
A31
GND*
D28
C30
D29
E28
D30
E29
U1
R3
R5
VCC*
T8
T2
P4
R7
GND*
N3
R1
N5
P2
M4
L1
L3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O (TMS)
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
E33
H30
G31
J29
F33
G32
J30
VCC*
GND*
H31
K29
H32
J31
K30
H33
L29
K31
GND*
L30
K32
J33
M29
VCC*
L31
M30
L32
M31
GND*
N29
L33
N30
N31
M32
P29
P30
N33
GND*
VCC*
P31
P32
R29
R30
R31
R33
GND*
T31
D8
B6
E9
C21
A22
VCC
B22
C22
B23
A24
GND*
D22
C23
B24
C24
-
F30
F31
H28
H29
G30
H30
VCC*
GND*
-
A7
G11
H14
F12
VCC*
GND*
G13
E11
B8
-
-
-
D10
A9
J28
J29
H31
J30
GND*
K28
K29
K30
K31
VCC*
-
-
-
-
G15
B10
H16
GND*
C9
P8
GND*
VCC*
-
GND*
VCC*
N7
K2
M6
J1
L5
H2
K4
J3
GND*
VCC*
L7
J5
G1
H4
E13
A11
D12
VCC*
C11
B14
G17
E15
GND*
D14
A15
C13
B16
E17
F18
A17
G19
GND*
VCC*
D16
C15
B18
H20
B20
E19
GND*
D18
F20
G21
C17
D20
E21
GND*
VCC*
C21
F22
A21
D22
B22
G23
GND*
E23
-
D23
B25
A26
C25
D24
B26
GND*
VCC*
A27
D25
C26
B27
A28
D26
GND*
C27
B28
D27
B29
C28
D28
-
L29
L30
GND*
M30
M28
-
-
M29
M31
N31
N28
GND*
VCC*
N29
N30
P30
P28
P29
R31
GND*
R30
R28
-
F2
I/O
GND
I/O
I/O
I/O
G5
GND*
H6
K8
D2
J7
F4
E3
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O (A14)
I/O, GCK8
(A15)
VCC
GND
I/O, GCK1
(A16)
I/O (A17)
I/O
VCC*
GND*
D29
VCC*
GND*
B33
VCC*
GND*
C1
I/O
I/O
I/O
I/O
T29
T30
T32
C30
E28
E29
D30
D31
GND*
F28
F29
E30
E31
G28
G29
VCC*
GND*
-
F29
E30
D31
F30
C33
GND*
G29
E31
D32
G30
F31
C3
F6
A3
H8
D4
GND*
D6
C5
E7
B4
H10
G9
VCC*
GND*
F8
-
I/O
R29
T31
GND*
VCC*
T30
T29
-
U32
U31
GND*
VCC*
U29
U30
U33
V32
V31
V29
GND*
V30
I/O (TDI)
I/O (TCK)
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
-
U31
U30
GND*
U28
H29
VCC*
GND*
E32
VCC
GND
I/O
6-150
DS006 (v. 1.7) October 4, 1999 - Product Specification
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4085XL
Pad Name
XC4085XL
Pad Name
BG432
BG560
PG559
BG432
BG560
PG559
I/O
I/O
I/O
I/O
U29
V30
V29
W33
W31
W30
W29
Y32
VCC*
GND*
Y31
Y30
AA33
Y29
C23
A23
D24
B24
H24
VCC*
GND*
F24
E25
B26
D26
A27
G25
B28
C27
GND*
F26
E27
A29
D28
VCC*
G27
B30
C29
E29
GND*
D30
A33
C31
B34
H28
A35
G29
E31
GND*
VCC*
D32
C35
C33
B36
H30
A37
G31
F32
GND*
VCC*
E33
D34
B38
G33
A41
E35
GND*
D36
F36
I (M0)
AH28
VCC*
AJ28
AK29
AH27
AK28
AJ27
AL28
AH26
GND*
AK27
AJ26
AL27
AH25
AK26
AL26
VCC*
GND*
AH24
AJ25
AK25
AJ24
AH23
AK24
-
AJ29
VCC*
AN32
AJ28
AK29
AL30
AK28
AM31
AJ27
GND*
AN31
AL29
AK27
AL28
AJ26
AM30
VCC*
GND*
AM29
AK26
AL27
AJ25
AN29
AN28
AK25
AL26
VCC*
GND*
AJ24
AM27
AM26
AK24
AL25
AJ23
AN26
AL24
GND*
AK23
AN25
AJ22
AL23
VCC*
AM24
AK22
AM23
AJ21
GND*
AL22
AN23
AK21
AM22
AJ20
AL21
AN21
AK20
GND*
VCC*
AL20
AJ19
AM20
AK19
C39
VCC*
H36
F38
C41
D40
B42
J37
K36
GND*
H38
D42
G39
C43
F40
E41
VCC*
GND*
L37
VCC
I (M2)
I/O, GCK3
I/O (HDC)
I/O
I/O
I/O
I/O (LDC)
GND
I/O
V28
I/O
W31
VCC*
GND*
W30
W29
-
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
W28
Y31
Y30
Y29
GND*
Y28
AA30
-
-
VCC*
AA29
AB31
AB30
AB29
GND*
AB28
AC30
AC29
AC28
-
AA32
AA31
AA30
AB32
GND*
AA29
AB31
AB30
AC33
VCC*
AC31
AB29
AD32
AC30
GND*
AD31
AE33
AC29
AE32
AD30
AE31
AF32
AD29
GND*
VCC*
AF31
AE30
AG33
AH33
AE29
AG31
AF30
AH32
GND*
VCC*
AJ32
AF29
AH31
AG30
AK32
AJ31
GND*
AG29
AL33
AH30
AK31
AJ30
AH29
AK30
GND*
I/O
I/O
I/O
I/O
I/O
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
J39
F42
H40
G43
J41
H42
N37
VCC*
GND*
P36
M38
J43
I/O
-
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC*
GND*
-
-
-
-
-
-
-
L39
AL24
AH22
AJ23
AK23
GND*
AJ22
AK22
AL22
AJ21
VCC*
AH20
AK21
-
K42
K40
L43
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND*
VCC*
-
L41
GND*
R37
P42
T36
N39
VCC*
M40
R43
N41
R39
GND*
U37
T42
P40
U43
R41
V42
U39
V38
GND*
VCC*
W37
T40
-
AD31
AD30
AD29
AD28
AE30
AE29
GND*
VCC*
AF31
AE28
AF30
AF29
AG31
AF28
GND*
AG30
AG29
AH31
AG28
AH30
AJ30
AH29
GND*
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O, GCK2
O (M1)
GND
-
GND*
-
-
AJ20
AH19
AK20
AJ19
AL20
AH18
GND*
VCC*
AK19
AJ18
AL19
AK18
I/O
G35
H34
B40
E37
D38
GND*
GND
VCC
I/O
I/O
I/O
Y42
U41
I/O
DS006 (v. 1.7) October 4, 1999 - Product Specification
6-151
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4085XL
Pad Name
XC4085XL
Pad Name
BG432
BG560
PG559
BG432
BG560
PG559
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O (INIT)
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
AH17
AJ17
GND*
-
AL19
AN19
GND*
AJ18
AK18
AL18
AM18
AK17
AJ17
VCC*
GND*
AL17
AM17
AN17
AK16
AJ16
AL16
GND*
AM16
AL15
AK15
AJ15
AN15
AM14
VCC*
GND*
AL14
AK14
AJ14
AN13
AM13
AL13
AK13
AJ13
GND*
AM12
AL12
AK12
AN11
VCC*
AJ12
AL11
AK11
AM10
GND*
AL10
AJ11
AN9
Y36
V40
GND*
W39
AA43
Y38
I/O
I/O
GND
VCC
I/O
I.O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
AJ7
AH8
GND*
VCC*
AK6
AL5
AH7
AJ6
AK5
AL4
GND*
AH6
AJ5
AK4
AH5
AK3
AJ4
GND*
AH4
VCC*
AH3
AJ2
AG4
AG3
AH2
AH1
AF4
GND*
AF3
AG2
AG1
AE4
AE3
AF2
VCC*
GND*
AF1
AD4
AD3
AE2
AD2
AC4
-
AN6
AM6
GND*
VCC*
AJ8
AP40
AT40
GND*
VCC*
AN37
AR39
AT42
BA43
AU43
AU39
GND*
AT38
AP36
AR37
AV42
AV40
AW41
GND*
AY42
VCC*
BB42
BC41
AV38
BA39
AT36
BB40
AY40
GND*
BA41
BB38
AY38
BC37
AW37
AT34
VCC*
GND*
AU35
AV36
BB36
AY36
BC35
AW35
AU33
AT30
VCC*
GND*
AV32
AU31
AW33
BB34
AY34
BC33
AU29
AT28
GND*
BA35
BB30
AW31
AY32
VCC*
BA33
-
AK17
AL17
AJ16
AK16
VCC*
GND*
AL16
AH15
AL15
AJ15
-
AL6
Y40
AK7
AM5
AM4
AJ7
GND*
AL5
AK6
AN3
AK5
AJ6
AL4
GND*
AJ5
VCC*
AM1
AH5
AJ4
AK3
AH4
AL1
AA37
AA39
VCC*
GND*
AA41
AB38
AB42
AB40
AC37
AC39
GND*
AD36
AC41
AD38
AC43
AD40
AE39
VCC*
GND*
AE37
AF40
AD42
AF42
AF38
AG39
AG43
AG37
GND*
AH40
AJ41
AG41
AK40
VCC*
AJ39
AH42
AH36
AL39
GND*
AJ37
AJ43
AM40
AK42
AN41
AL41
AR41
AK36
GND*
VCC*
AL37
AN43
AM38
AP42
AN39
AR43
I/O
I/O
-
I/O, GCK4
GND
DONE
VCC
PROGRAM
I/O (D7)
I/O, GCK5
I/O
I/O
I/O
I/O
GND
I/O
GND*
AK15
AJ14
AH14
AK14
AL13
AK13
VCC*
GND*
AJ13
AH13
AL12
AK12
AJ12
AK11
-
I/O
I/O
I/O
I/O
I/O
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AG5
GND*
AJ3
AK2
AG4
AH3
AF5
I/O
I/O
I/O
I/O
-
I/O
AJ2
GND*
-
-
VCC
GND
I/O (D6)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
VCC*
GND*
AJ1
AH12
AJ11
VCC*
AL10
AK10
AJ10
AK9
GND*
AL8
AH10
AJ9
AK8
-
AF4
AG3
AE5
AH1
AF3
AE4
AG2
VCC*
GND*
AD5
AF2
-
VCC*
GND*
-
-
-
AK10
AM9
AL9
AJ10
AM8
GND*
VCC*
AK9
AL8
AN7
AJ9
AL7
AF1
-
AD4
AE3
AC5
AE1
AD3
GND*
AC4
AD2
AB5
AC3
VCC*
AB4
-
-
-
AC3
AD1
AC2
AB4
GND*
AB3
AB2
AB1
AA3
VCC*
-
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
GND*
VCC*
-
-
AJ8
AH9
AK7
AL6
AK8
6-152
DS006 (v. 1.7) October 4, 1999 - Product Specification
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4085XL
Pad Name
XC4085XL
Pad Name
BG432
BG560
PG559
BG432
BG560
PG559
I/O
-
AA2
Y2
GND*
Y4
Y3
Y1
W1
-
-
W4
W3
GND*
VCC*
W2
V2
AC1
AA5
AB3
GND*
AB2
AA4
AA3
Y5
AU27
BC29
AW29
GND*
AY30
BA31
BB28
AW27
BC27
AV26
AU25
AY28
GND*
VCC*
BA29
AT24
BB26
AW25
BB24
AY26
GND*
AV24
AU23
BA27
BC23
AY24
AW23
VCC*
GND*
BA23
AV22
AY22
BB22
AU21
AW21
GND*
BA21
BC21
AY20
BB20
AT20
AV20
VCC*
GND*
AW19
AY18
BB18
AU19
BC17
BA17
AV18
AW17
GND*
AY16
BB16
AU17
BA15
VCC*
AW15
BC15
AY14
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
K4
GND*
J2
J3
J4
H1
-
-
-
-
GND*
VCC*
H2
H3
H4
G2
G3
F1
K3
GND*
L5
J2
K4
J3
H2
K5
H3
BA13
GND*
AT16
BB14
AU15
BC11
AW13
BB10
AY12
BA11
GND*
VCC*
AT14
AU13
AV12
BC9
I/O (D5)
I/O (CS0)
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AA1
Y4
Y3
J4
GND*
VCC*
G1
F1
J5
G3
H4
F2
E2
I/O
Y2
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O (D4)
I/O
VCC
GND
I/O (D3)
I/O (RS)
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
GND*
VCC*
W5
W4
W3
W1
V3
V5
GND*
V4
V4
V3
I/O
I/O
I/O
I/O
AW11
BB8
U1
U2
GND*
U4
U3
-
-
T1
T2
VCC*
GND*
T3
R1
-
-
-
AY10
AU11
GND*
VCC*
BA9
H5
GND
VCC
I/O (D1)
I/O (RCLK
RDY/BUSY)
I/O
I/O
I/O
I/O
GND
I/O
GND*
VCC*
G4
F2
GND*
VCC*
F3
V2
U2
U1
U5
G4
AW9
F3
E1
F4
E2
GND*
E3
D1
E4
D2
C2
D2
E3
G5
C1
GND*
F4
D3
B3
F5
E4
D4
BC7
AY8
AV8
AT10
GND*
AU9
BB6
AW7
BC3
AY6
BB4
U4
VCC*
GND*
U3
T2
T3
T5
T4
R1
GND*
R3
I/O
I/O
I/O
-
R2
R4
GND*
R3
P2
I/O (D0, DIN)
I/O, GCK6
(DOUT)
CCLK
VCC
O, TDO
GND
I/O (A0, WS)
I/O, GCK7 (A1)
I/O
I/O
I/O
I/O
GND
I/O
D3
D4
VCC*
C4
GND*
B3
D5
B4
C5
A4
D6
GND*
B5
C6
A5
D7
B6
A6
VCC*
GND*
D8
C7
B7
D9
B8
A8
C4
VCC*
E6
GND*
D5
A2
D6
A3
E7
C5
GND*
B4
D7
C6
E8
B5
A5
VCC*
GND*
D8
C7
E9
A6
B7
D9
BA5
VCC*
BA3
GND*
AT8
AV6
BB2
AY4
AR7
AP8
GND*
AT6
AY2
AU5
BA1
AV4
AW3
VCC*
GND*
AN7
AR5
AV2
AT4
R4
R5
P2
P3
P3
P4
N1
N2
VCC*
GND*
N3
N4
M1
M2
-
I/O
P4
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC*
GND*
N1
P5
N2
N3
N4
M2
N5
M3
GND*
M4
L1
L3
M5
VCC*
K2
L4
J1
I/O
-
I/O (CS1, A2)
I/O (A3)
I/O
I/O
VCC
GND
I/O
I/O
I/O
I/O
M3
M4
GND*
L2
L3
-
I/O
GND
I/O (D2)
I/O
I/O
I/O
VCC
I/O
I/O
-
VCC*
K1
K2
I/O
I/O
AU1
AR3
I/O
K3
DS006 (v. 1.7) October 4, 1999 - Product Specification
6-153
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4085XL
Pad Name
I/O
I/O
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
Additional XC4085XL Package Pins
BG560
BG432
BG560
PG559
-
-
C8
E10
VCC*
GND*
B8
A8
D10
C9
AT2
AL7
VCC Pins
A4
B13
D33
A10
B19
E5
A16
B32
H1
W32
AK33
AM32
-
A22
C3
K33
AA2
AL2
AN4
-
A26
C31
M1
AB33
AL3
AN8
-
A30
C32
N32
AD1
AL31
AN12
-
B2
D1
R2
AF33
AM2
AN18
-
VCC*
GND*
-
-
-
VCC*
GND*
AK8
AM6
AN5
AR1
AP4
AN3
AP2
AJ7
GND*
AH8
AL5
AN1
AM4
VCC*
AL3
T33
V1
AK1
AM15
AN24
AK4
AM21
AN30
-
D10
C9
B9
E11
A9
GND Pins
A18
A7
A32
B31
K1
V33
AE2
AM11
AN5
A12
B1
C2
L2
W2
AG1
AM19
AN10
A14
B6
E1
M33
Y1
AG32
AM25
AN14
A20
B15
G2
A24
B23
G33
A29
B27
J32
C10
D11
GND*
B10
E12
C11
B11
VCC*
D12
A11
E13
C12
GND*
B12
D13
C13
E14
A13
D14
C14
B14
GND*
VCC*
E15
D15
C15
A15
C16
E16
GND*
D16
B16
B17
C17
E17
D17
GND*
B9
F32
P1
Y33
AH2
AM28
AN16
C10
GND*
B10
A10
C11
D12
VCC*
B11
C12
-
P33
R32
T1
AB1
AJ33
AM33
AN20
AC32
AL32
AM7
AN22
AD33
AM3
AN2
AN27
Not Connected Pins
A1
A33
AC2
AN1
AN33
-
-
AJ5
6/4/97
AK2
AG7
GND*
AK4
AJ3
AG5
AJ1
AF6
AH2
AE7
AH4
GND*
VCC*
AG3
AD8
AG1
AF4
AE5
AD6
GND*
AD4
AF2
-
GND*
-
-
PG559
VCC Pins
B2
A13
C37
A31
F14
A43
F30
C7
G7
C19
G37
C25
G41
N1
W41
AL1
AT32
BA7
BC43
D13
B12
C13
A12
D14
B13
GND*
VCC*
C14
A13
B14
D15
C15
B15
GND*
-
G3
I/O
I/O
I/O
I/O
H12
N43
AE3
AL43
AU3
BA19
H18
P6
AE41
AM8
AU7
BA25
H26
P38
AF8
AM36
AU37
BA37
H32
V8
AF36
AT12
AU41
BC1
M8
M36
W3
AK38
AT26
AV30
BC31
V36
AK6
AT18
AV14
BC13
I/O
GND
VCC
I/O (A4)
I/O (A5)
I/O
GND Pins
A39
A5
E5
A19
E39
A25
E43
B12
F16
B32
F28
E1
F34
T38
AH6
AV10
AW43
-
F10
H22
W1
AH38
AV16
BB12
5/8/97
K6
K38
AB8
AM42
AV34
BC5
M2
AB36
AP6
AW1
BC19
M42
AE1
AP38
AW5
BC25
T6
I/O
W43
AM2
AV28
BB32
AE43
AT22
AW39
BC39
I/O (A21)
I/O (A20)
GND
I/O
I/O
I/O
-
A15
C16
B16
A16
GND*
AC7
AD2
AC5
AC3
GND*
I/O
I/O (A6)
I/O (A7)
GND
6/13/97
*Pads labelled GND* or VCC* are internally bonded to Ground or
VCC planes within the package. They have no direct connection to
any specific package pin.
6-154
DS006 (v. 1.7) October 4, 1999 - Product Specification
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
VG432
VCC Pins
A31
AA1
AL11
A1
L4
AH11
C29
A11
A21
L31
AL1
AJ29
D11
AA4
AL21
D21
AA28
AL31
L1
AA31
C3
L28
AH21
AJ3
GND Pins
A9
A2
A25
C1
A3
A29
C31
P31
AE1
AK30
AL18
A7
A30
D16
T4
AE31
AK31
AL23
A14
B2
G31
V1
AJ1
AL3
AL29
A18
B30
J1
V31
AJ31
AL7
AL30
A23
B31
J31
AC1
AK1
AL9
B1
G1
T28
AH16
AL2
P1
AC31
AK2
AL14
AL25
Not Connected Pins
C8
3/3/98
DS006 (v. 1.7) October 4, 1999 - Product Specification
6-155
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Revision Control
Version
Description
3/30/98 (1.5) Added XC4002XL
1/29/99 (1.5) Updated pin diagrams
5/14/99 (1.6) Replaced Electrical Specification and pinout pages for E, EX, and XL families with separate updates and
added URL link on placeholder page for electrical specifications/pinouts for WebLINX users
10/4/99 (1.7) Added Note about extra grounds in center of BG256 package for XC4028XL (page 6-133).
6-156
DS006 (v. 1.7) October 4, 1999 - Product Specification
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