XC4062XL-1HQG304C_技术文档

Product Obsolete or Under Obsolescence

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XC4000E and XC4000X Series Field

Programmable Gate Arrays

0

0*

May 14, 1999 (Version 1.6)

Product Specification

XC4000E and XC4000X Series

Features

Low-Voltage Versions Available

•

Low-Voltage Devices Function at 3.0 - 3.6 Volts

XC4000XL: High Performance Low-Voltage Versions of

XC4000EX devices

Note: Information in this data sheet covers the XC4000E,

XC4000EX, and XC4000XL families. A separate data sheet

covers the XC4000XLA and XC4000XV families. Electrical

Speciﬁcations and package/pin information are covered in

separate sections for each family to make the information

easier to access, review, and print. For access to these sec-

tions, see the Xilinx web site at

Additional XC4000X Series Features

•

High Performance — 3.3 V XC4000XL

High Capacity — Over 180,000 Usable Gates

5 V tolerant I/Os on XC4000XL

0.35 µm SRAM process for XC4000XL

Additional Routing Over XC4000E

http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp

•

System featured Field-Programmable Gate Arrays

-

almost twice the routing capacity for high-density

designs

SelectRAM^TMmemory: on-chip ultra-fast RAM with

-

synchronous write option

dual-port RAM option

•

Buffered Interconnect for Maximum Speed Blocks

Improved VersaRing^TMI/O Interconnect for Better Fixed

Pinout Flexibility

-

Fully PCI compliant (speed grades -2 and faster)

Abundant ﬂip-ﬂops

Flexible function generators

Dedicated high-speed carry logic

Wide edge decoders on each edge

Hierarchy of interconnect lines

Internal 3-state bus capability

Eight global low-skew clock or signal distribution

networks

6

•

12 mA Sink Current Per XC4000X Output

Flexible New High-Speed Clock Network

-

Eight additional Early Buffers for shorter clock delays

Virtually unlimited number of clock signals

•

Optional Multiplexer or 2-input Function Generator on

Device Outputs

Four Additional Address Bits in Master Parallel

Conﬁguration Mode

•

System Performance beyond 80 MHz

Flexible Array Architecture

Low Power Segmented Routing Architecture

Systems-Oriented Features

Introduction

-

IEEE 1149.1-compatible boundary scan logic

support

XC4000 Series high-performance, high-capacity Field Pro-

grammable Gate Arrays (FPGAs) provide the beneﬁts of

custom CMOS VLSI, while avoiding the initial cost, long

development cycle, and inherent risk of a conventional

masked gate array.

-

Individually programmable output slew rate

Programmable input pull-up or pull-down resistors

12 mA sink current per XC4000E output

•

Conﬁgured by Loading Binary File

Unlimited re-programmability

Read Back Capability

-

The result of thirteen years of FPGA design experience and

feedback from thousands of customers, these FPGAs com-

bine architectural versatility, on-chip Select-RAM memory

with edge-triggered and dual-port modes, increased

speed, abundant routing resources, and new, sophisticated

software to achieve fully automated implementation of

complex, high-density, high-performance designs.

-

Program veriﬁcation

Internal node observability

•

Backward Compatible with XC4000 Devices

Development System runs on most common computer

platforms

-

Interfaces to popular design environments

Fully automatic mapping, placement and routing

Interactive design editor for design optimization

The XC4000E and XC4000X Series currently have 20

members, as shown in Table 1.

May 14, 1999 (Version 1.6)

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XC4000E and XC4000X Series Field Programmable Gate Arrays

much as 50% from XC4000 values. See “Fast Carry Logic”

on page 18 for more information.

XC4000E and XC4000X Series

Compared to the XC4000

Select-RAM Memory: Edge-Triggered, Synchro-

nous RAM Modes

For readers already familiar with the XC4000 family of Xil-

inx Field Programmable Gate Arrays, the major new fea-

tures in the XC4000 Series devices are listed in this

section. The biggest advantages of XC4000E and

XC4000X devices are signiﬁcantly increased system

speed, greater capacity, and new architectural features,

particularly Select-RAM memory. The XC4000X devices

also offer many new routing features, including special

high-speed clock buffers that can be used to capture input

data with minimal delay.

The RAM in any CLB can be conﬁgured for synchronous,

edge-triggered, write operation. The read operation is not

affected by this change to an edge-triggered write.

Dual-Port RAM

A separate option converts the 16x2 RAM in any CLB into a

16x1 dual-port RAM with simultaneous Read/Write.

The function generators in each CLB can be conﬁgured as

either level-sensitive (asynchronous) single-port RAM,

edge-triggered (synchronous) single-port RAM, edge-trig-

gered (synchronous) dual-port RAM, or as combinatorial

logic.

Any XC4000E device is pinout- and bitstream-compatible

with the corresponding XC4000 device. An existing

XC4000 bitstream can be used to program an XC4000E

device. However, since the XC4000E includes many new

features, an XC4000E bitstream cannot be loaded into an

XC4000 device.

Conﬁgurable RAM Content

XC4000X Series devices are not bitstream-compatible with

equivalent array size devices in the XC4000 or XC4000E

families. However, equivalent array size devices, such as

the XC4025, XC4025E, XC4028EX, and XC4028XL, are

pinout-compatible.

The RAM content can now be loaded at conﬁguration time,

so that the RAM starts up with user-deﬁned data.

H Function Generator

6

In current XC4000 Series devices, the H function generator

is more versatile than in the original XC4000. Its inputs can

come not only from the F and G function generators but

also from up to three of the four control input lines. The H

function generator can thus be totally or partially indepen-

dent of the other two function generators, increasing the

maximum capacity of the device.

Improvements in XC4000E and XC4000X

Increased System Speed

XC4000E and XC4000X devices can run at synchronous

system clock rates of up to 80 MHz, and internal perfor-

mance can exceed 150 MHz. This increase in performance

over the previous families stems from improvements in both

IOB Clock Enable

device processing and system architecture.

XC4000

The two ﬂip-ﬂops in each IOB have a common clock enable

input, which through conﬁguration can be activated individ-

ually for the input or output ﬂip-ﬂop or both. This clock

enable operates exactly like the EC pin on the XC4000

CLB. This new feature makes the IOBs more versatile, and

avoids the need for clock gating.

Series devices use a sub-micron multi-layer metal process.

In addition, many architectural improvements have been

made, as described below.

The XC4000XL family is a high performance 3.3V family

based on 0.35µ SRAM technology and supports system

speeds to 80 MHz.

Output Drivers

PCI Compliance

The output pull-up structure defaults to a TTL-like

totem-pole. This driver is an n-channel pull-up transistor,

pulling to a voltage one transistor threshold below Vcc, just

like the XC4000 family outputs. Alternatively, XC4000

Series devices can be globally conﬁgured with CMOS out-

puts, with p-channel pull-up transistors pulling to Vcc. Also,

the conﬁgurable pull-up resistor in the XC4000 Series is a

p-channel transistor that pulls to Vcc, whereas in the origi-

nal XC4000 family it is an n-channel transistor that pulls to

a voltage one transistor threshold below Vcc.

XC4000 Series -2 and faster speed grades are fully PCI

compliant. XC4000E and XC4000X devices can be used to

implement a one-chip PCI solution.

Carry Logic

The speed of the carry logic chain has increased dramati-

cally. Some parameters, such as the delay on the carry

chain through a single CLB (TBYP), have improved by as

May 14, 1999 (Version 1.6)

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Table 1: XC4000E and XC4000X Series Field Programmable Gate Arrays

Max Logic Max. RAM

Gates Bits

(No RAM) (No Logic) (Logic and RAM)*

Typical

Gate Range

Number

of

CLBs Flip-Flops User I/O

Logic

Cells

CLB

Matrix

Total

Max.

Device

XC4002XL

XC4003E

152

238

1,600

3,000

2,048

3,200

1,000 - 3,000

2,000 - 5,000

8 x 8

64

256

360

64

10 x 10

14 x 14

16 x 16

18 x 18

20 x 20

24 x 24

28 x 28

32 x 32

36 x 36

40 x 40

44 x 44

48 x 48

56 x 56

100

80

XC4005E/XL

XC4006E

466

5,000

6,272

3,000 - 9,000

196

616

112

128

144

160

192

224

256

288

320

352

384

448

608

6,000

8,192

4,000 - 12,000

6,000 - 15,000

7,000 - 20,000

10,000 - 30,000

13,000 - 40,000

15,000 - 45,000

18,000 - 50,000

22,000 - 65,000

27,000 - 80,000

33,000 - 100,000

40,000 - 130,000

55,000 - 180,000

256

768

XC4008E

770

8,000

10,368

12,800

18,432

25,088

32,768

41,472

51,200

61,952

73,728

100,352

324

936

XC4010E/XL

XC4013E/XL

XC4020E/XL

XC4025E

950

10,000

13,000

20,000

25,000

28,000

36,000

44,000

52,000

62,000

85,000

400

1,120

1,536

2,016

2,560

3,168

3,840

4,576

5,376

7,168

1368

1862

2432

3078

3800

4598

5472

7448

576

784

1,024

1,296

1,600

1,936

2,304

3,136

XC4028EX/XL

XC4036EX/XL

XC4044XL

XC4052XL

XC4062XL

XC4085XL

*

Max values of Typical Gate Range include 20-30% of CLBs used as RAM.

Note: All functionality in low-voltage families is the same as

in the corresponding 5-Volt family, except where numerical

references are made to timing or power.

where hardware is changed dynamically, or where hard-

ware must be adapted to different user applications.

FPGAs are ideal for shortening design and development

cycles, and also offer a cost-effective solution for produc-

tion rates well beyond 5,000 systems per month.

Description

XC4000 Series devices are implemented with a regular,

ﬂexible, programmable architecture of Conﬁgurable Logic

Blocks (CLBs), interconnected by a powerful hierarchy of

versatile routing resources, and surrounded by a perimeter

of programmable Input/Output Blocks (IOBs). They have

generous routing resources to accommodate the most

complex interconnect patterns.

Taking Advantage of Re-conﬁguration

FPGA devices can be re-conﬁgured to change logic func-

tion while resident in the system. This capability gives the

system designer a new degree of freedom not available

with any other type of logic.

The devices are customized by loading conﬁguration data

into internal memory cells. The FPGA can either actively

read its conﬁguration data from an external serial or

byte-parallel PROM (master modes), or the conﬁguration

data can be written into the FPGA from an external device

(slave and peripheral modes).

Hardware can be changed as easily as software. Design

updates or modiﬁcations are easy, and can be made to

products already in the ﬁeld. An FPGA can even be re-con-

ﬁgured dynamically to perform different functions at differ-

ent times.

XC4000 Series FPGAs are supported by powerful and

sophisticated software, covering every aspect of design

from schematic or behavioral entry, ﬂoor planning, simula-

tion, automatic block placement and routing of intercon-

nects, to the creation, downloading, and readback of the

conﬁguration bit stream.

Re-conﬁgurable logic can be used to implement system

self-diagnostics, create systems capable of being re-con-

ﬁgured for different environments or operations, or imple-

ment multi-purpose hardware for a given application. As an

added beneﬁt, using re-conﬁgurable FPGA devices simpli-

ﬁes hardware design and debugging and shortens product

time-to-market.

Because Xilinx FPGAs can be reprogrammed an unlimited

number of times, they can be used in innovative designs

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Input Thresholds

Additional Improvements in XC4000X Only

Increased Routing

The input thresholds of 5V devices can be globally conﬁg-

ured for either TTL (1.2 V threshold) or CMOS (2.5 V

threshold), just like XC2000 and XC3000 inputs. The two

global adjustments of input threshold and output level are

independent of each other. The XC4000XL family has an

input threshold of 1.6V, compatible with both 3.3V CMOS

and TTL levels.

New interconnect in the XC4000X includes twenty-two

additional vertical lines in each column of CLBs and twelve

new horizontal lines in each row of CLBs. The twelve “Quad

Lines” in each CLB row and column include optional repow-

ering buffers for maximum speed. Additional high-perfor-

mance routing near the IOBs enhances pin ﬂexibility.

Global Signal Access to Logic

Faster Input and Output

There is additional access from global clocks to the F and

G function generator inputs.

A fast, dedicated early clock sourced by global clock buffers

is available for the IOBs. To ensure synchronization with the

regular global clocks, a Fast Capture latch driven by the

early clock is available. The input data can be initially

loaded into the Fast Capture latch with the early clock, then

transferred to the input ﬂip-ﬂop or latch with the low-skew

global clock. A programmable delay on the input can be

used to avoid hold-time requirements. See “IOB Input Sig-

nals” on page 20 for more information.

Conﬁguration Pin Pull-Up Resistors

During configuration, these pins have weak pull-up resis-

tors. For the most popular configuration mode, Slave

Serial, the mode pins can thus be left unconnected. The

three mode inputs can be individually configured with or

without weak pull-up or pull-down resistors. A pull-down

resistor value of 4.7 kΩ is recommended.

Latch Capability in CLBs

The three mode inputs can be individually conﬁgured with

or without weak pull-up or pull-down resistors after conﬁgu-

ration.

Storage elements in the XC4000X CLB can be conﬁgured

as either ﬂip-ﬂops or latches. This capability makes the

FPGA highly synthesis-compatible.

The PROGRAM input pin has a permanent weak pull-up.

Soft Start-up

IOB Output MUX From Output Clock

Like the XC3000A, XC4000 Series devices have “Soft

Start-up.” When the conﬁguration process is ﬁnished and

the device starts up, the ﬁrst activation of the outputs is

automatically slew-rate limited. This feature avoids poten-

tial ground bounce when all outputs are turned on simulta-

neously. Immediately after start-up, the slew rate of the

individual outputs is, as in the XC4000 family, determined

by the individual conﬁguration option.

A multiplexer in the IOB allows the output clock to select

either the output data or the IOB clock enable as the output

to the pad. Thus, two different data signals can share a sin-

gle output pad, effectively doubling the number of device

outputs without requiring a larger, more expensive pack-

age. This multiplexer can also be conﬁgured as an

AND-gate to implement a very fast pin-to-pin path. See

“IOB Output Signals” on page 23 for more information.

XC4000 and XC4000A Compatibility

Additional Address Bits

Existing XC4000 bitstreams can be used to conﬁgure an

XC4000E device. XC4000A bitstreams must be recompiled

for use with the XC4000E due to improved routing

resources, although the devices are pin-for-pin compatible.

Larger devices require more bits of conﬁguration data. A

daisy chain of several large XC4000X devices may require

a PROM that cannot be addressed by the eighteen address

bits supported in the XC4000E. The XC4000X Series

therefore extends the addressing in Master Parallel conﬁg-

uration mode to 22 bits.

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Each CLB contains two storage elements that can be used

Detailed Functional Description

to store the function generator outputs. However, the stor-

age elements and function generators can also be used

independently. These storage elements can be conﬁgured

as ﬂip-ﬂops in both XC4000E and XC4000X devices; in the

XC4000X they can optionally be conﬁgured as latches. DIN

can be used as a direct input to either of the two storage

elements. H1 can drive the other through the H function

generator. Function generator outputs can also drive two

outputs independent of the storage element outputs. This

versatility increases logic capacity and simpliﬁes routing.

XC4000 Series devices achieve high speed through

advanced semiconductor technology and improved archi-

tecture. The XC4000E and XC4000X support system clock

rates of up to 80 MHz and internal performance in excess

of 150 MHz. Compared to older Xilinx FPGA families,

XC4000 Series devices are more powerful. They offer

on-chip edge-triggered and dual-port RAM, clock enables

on I/O ﬂip-ﬂops, and wide-input decoders. They are more

versatile in many applications, especially those involving

RAM. Design cycles are faster due to a combination of

increased routing resources and more sophisticated soft-

ware.

Thirteen CLB inputs and four CLB outputs provide access

to the function generators and storage elements. These

inputs and outputs connect to the programmable intercon-

nect resources outside the block.

Basic Building Blocks

Xilinx user-programmable gate arrays include two major

conﬁgurable elements: conﬁgurable logic blocks (CLBs)

and input/output blocks (IOBs).

Function Generators

Four independent inputs are provided to each of two func-

tion generators (F1 - F4 and G1 - G4). These function gen-

erators, with outputs labeled F’ and G’, are each capable of

implementing any arbitrarily deﬁned Boolean function of

four inputs. The function generators are implemented as

memory look-up tables. The propagation delay is therefore

independent of the function implemented.

•

CLBs provide the functional elements for constructing

the user’s logic.

•

IOBs provide the interface between the package pins

and internal signal lines.

6

Three other types of circuits are also available:

A third function generator, labeled H’, can implement any

Boolean function of its three inputs. Two of these inputs can

optionally be the F’ and G’ functional generator outputs.

Alternatively, one or both of these inputs can come from

outside the CLB (H2, H0). The third input must come from

outside the block (H1).

•

3-State buffers (TBUFs) driving horizontal longlines are

associated with each CLB.

Wide edge decoders are available around the periphery

of each device.

An on-chip oscillator is provided.

Programmable interconnect resources provide routing

paths to connect the inputs and outputs of these conﬁg-

urable elements to the appropriate networks.

Signals from the function generators can exit the CLB on

two outputs. F’ or H’ can be connected to the X output. G’ or

H’ can be connected to the Y output.

The functionality of each circuit block is customized during

conﬁguration by programming internal static memory cells.

The values stored in these memory cells determine the

logic functions and interconnections implemented in the

FPGA. Each of these available circuits is described in this

section.

A CLB can be used to implement any of the following func-

tions:

•

any function of up to four variables, plus any second

function of up to four unrelated variables, plus any third

function of up to three unrelated variables¹

any single function of ﬁve variables

any function of four variables together with some

functions of six variables

•

Conﬁgurable Logic Blocks (CLBs)

Conﬁgurable Logic Blocks implement most of the logic in

an FPGA. The principal CLB elements are shown in

Figure 1. Two 4-input function generators (F and G) offer

unrestricted versatility. Most combinatorial logic functions

need four or fewer inputs. However, a third function gener-

ator (H) is provided. The H function generator has three

inputs. Either zero, one, or two of these inputs can be the

outputs of F and G; the other input(s) are from outside the

CLB. The CLB can, therefore, implement certain functions

of up to nine variables, like parity check or expand-

able-identity comparison of two sets of four inputs.

•

some functions of up to nine variables.

Implementing wide functions in a single block reduces both

the number of blocks required and the delay in the signal

path, achieving both increased capacity and speed.

The versatility of the CLB function generators signiﬁcantly

improves system speed. In addition, the design-software

tools can deal with each function generator independently.

This ﬂexibility improves cell usage.

1. When three separate functions are generated, one of the function outputs must be captured in a ﬂip-ﬂop internal to the CLB. Only two

unregistered function generator outputs are available from the CLB.

May 14, 1999 (Version 1.6)

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XC4000E and XC4000X Series Field Programmable Gate Arrays

4

C

• • • C

4

1

H

EC

D

/H

2

SR/H

1

IN

0

G

S/R

CONTROL

Bypass

4

3

2

1

DIN

F'

G'

YQ

LOGIC

FUNCTION

OF

SD

D

Q

G'

H'

G1-G4

LOGIC

FUNCTION

OF

F', G',

AND

H1

EC

RD

G'

H'

1

Y

F

4

3

2

1

Bypass

S/R

CONTROL

DIN

F'

G'

H'

XQ

LOGIC

FUNCTION

OF

SD

D

Q

F'

F1-F4

EC

RD

K

(CLOCK)

1

H'

F'

X

Multiplexer Controlled

by Configuration Program

X6692

Figure 1: Simpliﬁed Block Diagram of XC4000 Series CLB (RAM and Carry Logic functions not shown)

Flip-Flops

Clock Enable

The CLB can pass the combinatorial output(s) to the inter-

connect network, but can also store the combinatorial

results or other incoming data in one or two ﬂip-ﬂops, and

connect their outputs to the interconnect network as well.

The clock enable signal (EC) is active High. The EC pin is

shared by both storage elements. If left unconnected for

either, the clock enable for that storage element defaults to

the active state. EC is not invertible within the CLB.

The two edge-triggered D-type ﬂip-ﬂops have common

clock (K) and clock enable (EC) inputs. Either or both clock

inputs can also be permanently enabled. Storage element

functionality is described in Table 2.

Table 2: CLB Storage Element Functionality

(active rising edge is shown)

Mode

K

EC

SR

D

Q

Power-Up or

GSR

Latches (XC4000X only)

X

SR

The CLB storage elements can also be conﬁgured as

latches. The two latches have common clock (K) and clock

enable (EC) inputs. Storage element functionality is

described in Table 2.

X

__/

0

X

1*

X

1

X

D

X

D

X

SR

D

Flip-Flop

0*

Q

1

1*

0

Q

Clock Input

Latch

Both

0

D

Each ﬂip-ﬂop can be triggered on either the rising or falling

clock edge. The clock pin is shared by both storage ele-

ments. However, the clock is individually invertible for each

storage element. Any inverter placed on the clock input is

automatically absorbed into the CLB.

X

Q

Legend:

X

Don’t care

Rising edge

Set or Reset value. Reset is default.

Input is Low or unconnected (default value)

__/

SR

0*

1*

Input is High or unconnected (default value)

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Two fast feed-through paths are available, as shown in

Figure 1. A two-to-one multiplexer on each of the XQ and

YQ outputs selects between a storage element output and

any of the control inputs. This bypass is sometimes used by

the automated router to repower internal signals.

Set/Reset

An asynchronous storage element input (SR) can be con-

ﬁgured as either set or reset. This conﬁguration option

determines the state in which each ﬂip-ﬂop becomes oper-

ational after conﬁguration. It also determines the effect of a

Global Set/Reset pulse during normal operation, and the

effect of a pulse on the SR pin of the CLB. All three

set/reset functions for any single ﬂip-ﬂop are controlled by

the same conﬁguration data bit.

Control Signals

Multiplexers in the CLB map the four control inputs (C1 - C4

in Figure 1) into the four internal control signals (H1,

DIN/H2, SR/H0, and EC). Any of these inputs can drive any

of the four internal control signals.

The set/reset state can be independently speciﬁed for each

ﬂip-ﬂop. This input can also be independently disabled for

either ﬂip-ﬂop.

When the logic function is enabled, the four inputs are:

•

EC — Enable Clock

SR/H0 — Asynchronous Set/Reset or H function

generator Input 0

DIN/H2 — Direct In or H function generator Input 2

H1 — H function generator Input 1.

The set/reset state is speciﬁed by using the INIT attribute,

or by placing the appropriate set or reset ﬂip-ﬂop library

symbol.

•

SR is active High. It is not invertible within the CLB.

When the memory function is enabled, the four inputs are:

Global Set/Reset

•

EC — Enable Clock

WE — Write Enable

D0 — Data Input to F and/or G function generator

D1 — Data input to G function generator (16x1 and

16x2 modes) or 5th Address bit (32x1 mode).

A separate Global Set/Reset line (not shown in Figure 1)

sets or clears each storage element during power-up,

re-conﬁguration, or when a dedicated Reset net is driven

active. This global net (GSR) does not compete with other

routing resources; it uses a dedicated distribution network.

6

Each ﬂip-ﬂop is conﬁgured as either globally set or reset in

the same way that the local set/reset (SR) is speciﬁed.

Therefore, if a ﬂip-ﬂop is set by SR, it is also set by GSR.

Similarly, a reset ﬂip-ﬂop is reset by both SR and GSR.

Using FPGA Flip-Flops and Latches

The abundance of ﬂip-ﬂops in the XC4000 Series invites

pipelined designs. This is a powerful way of increasing per-

formance by breaking the function into smaller subfunc-

tions and executing them in parallel, passing on the results

through pipeline ﬂip-ﬂops. This method should be seriously

considered wherever throughput is more important than

latency.

STARTUP

GSR

GTS

PAD

Q2

Q3

Q1Q4

IBUF

To include a CLB ﬂip-ﬂop, place the appropriate library

symbol. For example, FDCE is a D-type ﬂip-ﬂop with clock

enable and asynchronous clear. The corresponding latch

symbol (for the XC4000X only) is called LDCE.

DONEIN

CLK

X5260

Figure 2: Schematic Symbols for Global Set/Reset

In XC4000 Series devices, the ﬂip ﬂops can be used as reg-

isters or shift registers without blocking the function gener-

ators from performing a different, perhaps unrelated task.

This ability increases the functional capacity of the devices.

GSR can be driven from any user-programmable pin as a

global reset input. To use this global net, place an input pad

and input buffer in the schematic or HDL code, driving the

GSR pin of the STARTUP symbol. (See Figure 2.) A spe-

ciﬁc pin location can be assigned to this input using a LOC

attribute or property, just as with any other user-program-

mable pad. An inverter can optionally be inserted after the

input buffer to invert the sense of the Global Set/Reset sig-

nal.

The CLB setup time is speciﬁed between the function gen-

erator inputs and the clock input K. Therefore, the speciﬁed

CLB ﬂip-ﬂop setup time includes the delay through the

function generator.

Using Function Generators as RAM

Optional modes for each CLB make the memory look-up

tables in the F’ and G’ function generators usable as an

array of Read/Write memory cells. Available modes are

level-sensitive (similar to the XC4000/A/H families),

edge-triggered, and dual-port edge-triggered. Depending

on the selected mode, a single CLB can be conﬁgured as

either a 16x2, 32x1, or 16x1 bit array.

Alternatively, GSR can be driven from any internal node.

Data Inputs and Outputs

The source of a storage element data input is programma-

ble. It is driven by any of the functions F’, G’, and H’, or by

the Direct In (DIN) block input. The ﬂip-ﬂops or latches drive

the XQ and YQ CLB outputs.

May 14, 1999 (Version 1.6)

6-11

Product Obsolete or Under Obsolescence

R

XC4000E and XC4000X Series Field Programmable Gate Arrays

Supported CLB memory conﬁgurations and timing modes

for single- and dual-port modes are shown in Table 3.

The selected timing mode applies to both function genera-

tors within a CLB when both are conﬁgured as RAM.

XC4000 Series devices are the ﬁrst programmable logic

devices with edge-triggered (synchronous) and dual-port

RAM accessible to the user. Edge-triggered RAM simpli-

ﬁes system timing. Dual-port RAM doubles the effective

throughput of FIFO applications. These features can be

individually programmed in any XC4000 Series CLB.

The number of read ports is also programmable:

•

Single Port: each function generator has a common

read and write port

•

Dual Port: both function generators are conﬁgured

together as a single 16x1 dual-port RAM with one write

port and two read ports. Simultaneous read and write

operations to the same or different addresses are

supported.

Advantages of On-Chip and Edge-Triggered RAM

The on-chip RAM is extremely fast. The read access time is

the same as the logic delay. The write access time is

slightly slower. Both access times are much faster than

any off-chip solution, because they avoid I/O delays.

RAM conﬁguration options are selected by placing the

appropriate library symbol.

Choosing a RAM Conﬁguration Mode

Edge-triggered RAM, also called synchronous RAM, is a

feature never before available in a Field Programmable

Gate Array. The simplicity of designing with edge-triggered

RAM, and the markedly higher achievable performance,

add up to a signiﬁcant improvement over existing devices

with on-chip RAM.

The appropriate choice of RAM mode for a given design

should be based on timing and resource requirements,

desired functionality, and the simplicity of the design pro-

cess. Recommended usage is shown in Table 4.

The difference between level-sensitive, edge-triggered,

and dual-port RAM is only in the write operation. Read

operation and timing is identical for all modes of operation.

Three application notes are available from Xilinx that dis-

cuss edge-triggered RAM: “XC4000E Edge-Triggered and

Dual-Port RAM Capability,” “Implementing FIFOs in

XC4000E RAM,” and “Synchronous and Asynchronous

FIFO Designs.” All three application notes apply to both

XC4000E and XC4000X RAM.

Table 4: RAM Mode Selection

Dual-Port

Level-Sens Edge-Trigg Edge-Trigg

itive

ered

Table 3: Supported RAM Modes

Use for New

Designs?

No

Yes

16

x

16

x

32

x

Edge-

Triggered Sensitive

Timing

Level-

Size (16x1,

Registered)

1/2 CLB

No

1 CLB

Yes

1

2

1

Timing

Simultaneous

Read/Write

Single-Port

Dual-Port

√

No

X

Relative

Performance

2X (4X

effective)

2X

RAM Conﬁguration Options

The function generators in any CLB can be conﬁgured as

RAM arrays in the following sizes:

RAM Inputs and Outputs

The F1-F4 and G1-G4 inputs to the function generators act

as address lines, selecting a particular memory cell in each

look-up table.

•

Two 16x1 RAMs: two data inputs and two data outputs

with identical or, if preferred, different addressing for

each RAM

The functionality of the CLB control signals changes when

the function generators are conﬁgured as RAM. The

DIN/H2, H1, and SR/H0 lines become the two data inputs

(D0, D1) and the Write Enable (WE) input for the 16x2

memory. When the 32x1 conﬁguration is selected, D1 acts

as the ﬁfth address bit and D0 is the data input.

•

One 32x1 RAM: one data input and one data output.

One F or G function generator can be conﬁgured as a 16x1

RAM while the other function generators are used to imple-

ment any function of up to 5 inputs.

Additionally, the XC4000 Series RAM may have either of

two timing modes:

The contents of the memory cell(s) being addressed are

available at the F’ and G’ function-generator outputs. They

can exit the CLB through its X and Y outputs, or can be cap-

tured in the CLB ﬂip-ﬂop(s).

•

Edge-Triggered (Synchronous): data written by the

designated edge of the CLB clock. WE acts as a true

clock enable.

•

Level-Sensitive (Asynchronous): an external WE signal

acts as the write strobe.

Conﬁguring the CLB function generators as Read/Write

memory does not affect the functionality of the other por-

6-12

May 14, 1999 (Version 1.6)

Product Obsolete or Under Obsolescence

R

XC4000E and XC4000X Series Field Programmable Gate Arrays

tions of the CLB, with the exception of the redeﬁnition of the

control signals. In 16x2 and 16x1 modes, the H’ function

generator can be used to implement Boolean functions of

F’, G’, and D1, and the D ﬂip-ﬂops can latch the F’, G’, H’, or

D0 signals.

nals. An internal write pulse is generated that performs the

write. See Figure 4 and Figure 5 for block diagrams of a

CLB conﬁgured as 16x2 and 32x1 edge-triggered, sin-

gle-port RAM.

The relationships between CLB pins and RAM inputs and

outputs for single-port, edge-triggered mode are shown in

Table 5.

Single-Port Edge-Triggered Mode

Edge-triggered (synchronous) RAM simpliﬁes timing

requirements. XC4000 Series edge-triggered RAM timing

operates like writing to a data register. Data and address

are presented. The register is enabled for writing by a logic

High on the write enable input, WE. Then a rising or falling

clock edge loads the data into the register, as shown in

Figure 3.

The Write Clock input (WCLK) can be conﬁgured as active

on either the rising edge (default) or the falling edge. It uses

the same CLB pin (K) used to clock the CLB ﬂip-ﬂops, but it

can be independently inverted. Consequently, the RAM

output can optionally be registered within the same CLB

either by the same clock edge as the RAM, or by the oppo-

site edge of this clock. The sense of WCLK applies to both

function generators in the CLB when both are conﬁgured

as RAM.

T_WPS

WCLK (K)

T_WHS

The WE pin is active-High and is not invertible within the

CLB.

T_WSS

WE

Note: The pulse following the active edge of WCLK (T_WPS

in Figure 3) must be less than one millisecond wide. For

most applications, this requirement is not overly restrictive;

however, it must not be forgotten. Stopping WCLK at this

point in the write cycle could result in excessive current and

even damage to the larger devices if many CLBs are con-

ﬁgured as edge-triggered RAM.

T_DHS

T_DSS

DATA IN

6

T_ASS

T_AHS

ADDRESS

Table 5: Single-Port Edge-Triggered RAM Signals

T_ILO

RAM Signal

CLB Pin

Function

Data In

T_WOS

D

D0 or D1 (16x2,

16x1), D0 (32x1)

DATA OUT

OLD

NEW

A[3:0]

A[4]

F1-F4 or G1-G4

Address

Write Enable

Clock

X6461

D1 (32x1)

WE

Figure 3: Edge-Triggered RAM Write Timing

WE

Complex timing relationships between address, data, and

write enable signals are not required, and the external write

enable pulse becomes a simple clock enable. The active

edge of WCLK latches the address, input data, and WE sig-

WCLK

K

SPO

(Data Out)

F’ or G’

Single Port Out

(Data Out)

May 14, 1999 (Version 1.6)

6-13

Product Obsolete or Under Obsolescence

R

XC4000E and XC4000X Series Field Programmable Gate Arrays

4

C

• • • C

4

1

EC

D

0

WE

1

D

IN

WRITE

DECODER

16-LATCH

ARRAY

G'

MUX

4

G

• • • G

4

1

1 of 16

LATCH

ENABLE

READ

ADDRESS

WRITE PULSE

D

IN

WRITE

DECODER

16-LATCH

ARRAY

F'

MUX

4

F

• • • F

1

4

1 of 16

LATCH

ENABLE

K

READ

ADDRESS

(CLOCK)

WRITE PULSE

X6752

Figure 4: 16x2 (or 16x1) Edge-Triggered Single-Port RAM

4

C

• • • C

1

4

EC

D /A

D

0

WE

1

4

D

IN

WRITE

DECODER

16-LATCH

ARRAY

G'

MUX

G

F

• • • G

• • • F

4

1

4

1 of 16

LATCH

ENABLE

READ

ADDRESS

WRITE PULSE

H'

D

IN

WRITE

DECODER

16-LATCH

ARRAY

F'

MUX

4

1 of 16

LATCH

ENABLE

K

READ

ADDRESS

(CLOCK)

WRITE PULSE

X6754

Figure 5: 32x1 Edge-Triggered Single-Port RAM (F and G addresses are identical)

6-14

May 14, 1999 (Version 1.6)

Product Obsolete or Under Obsolescence

R

XC4000E and XC4000X Series Field Programmable Gate Arrays

Dual-Port Edge-Triggered Mode

Table 6: Dual-Port Edge-Triggered RAM Signals

RAM Signal CLB Pin Function

In dual-port mode, both the F and G function generators

are used to create a single 16x1 RAM array with one write

port and two read ports. The resulting RAM array can be

read and written simultaneously at two independent

addresses. Simultaneous read and write operations at the

same address are also supported.

D

D0

Data In

A[3:0]

F1-F4

Read Address for F,

Write Address for F and G

Read Address for G

Write Enable

Clock

Single Port Out

DPRA[3:0]

WE

WCLK

SPO

G1-G4

WE

K

Dual-port mode always has edge-triggered write timing, as

shown in Figure 3.

F’

(addressed by A[3:0])

Dual Port Out

Figure 6 shows a simple model of an XC4000 Series CLB

conﬁgured as dual-port RAM. One address port, labeled

A[3:0], supplies both the read and write address for the F

function generator. This function generator behaves the

same as a 16x1 single-port edge-triggered RAM array. The

RAM output, Single Port Out (SPO), appears at the F func-

tion generator output. SPO, therefore, reﬂects the data at

address A[3:0].

DPO

G’

(addressed by DPRA[3:0])

Note: The pulse following the active edge of WCLK (T_WPS

in Figure 3) must be less than one millisecond wide. For

most applications, this requirement is not overly restrictive;

however, it must not be forgotten. Stopping WCLK at this

point in the write cycle could result in excessive current and

even damage to the larger devices if many CLBs are con-

ﬁgured as edge-triggered RAM.

The other address port, labeled DPRA[3:0] for Dual Port

Read Address, supplies the read address for the G function

generator. The write address for the G function generator,

however, comes from the address A[3:0]. The output from

this 16x1 RAM array, Dual Port Out (DPO), appears at the

G function generator output. DPO, therefore, reﬂects the

data at address DPRA[3:0].

Single-Port Level-Sensitive Timing Mode

Note: Edge-triggered mode is recommended for all new

designs. Level-sensitive mode, also called asynchronous

mode, is still supported for XC4000 Series backward-com-

patibility with the XC4000 family.

6

Therefore, by using A[3:0] for the write address and

DPRA[3:0] for the read address, and reading only the DPO

output, a FIFO that can read and write simultaneously is

easily generated. Simultaneous access doubles the effec-

tive throughput of the FIFO.

Level-sensitive RAM timing is simple in concept but can be

complicated in execution. Data and address signals are

presented, then a positive pulse on the write enable pin

(WE) performs a write into the RAM at the designated

address. As indicated by the “level-sensitive” label, this

RAM acts like a latch. During the WE High pulse, changing

the data lines results in new data written to the old address.

Changing the address lines while WE is High results in spu-

rious data written to the new address—and possibly at

other addresses as well, as the address lines inevitably do

not all change simultaneously.

The relationships between CLB pins and RAM inputs and

outputs for dual-port, edge-triggered mode are shown in

Table 6. See Figure 7 on page 16 for a block diagram of a

CLB conﬁgured in this mode.

RAM16X1D Primitive

DPO (Dual Port Out)

The user must generate a carefully timed WE signal. The

delay on the WE signal and the address lines must be care-

fully veriﬁed to ensure that WE does not become active

until after the address lines have settled, and that WE goes

inactive before the address lines change again. The data

must be stable before and after the falling edge of WE.

WE

D

Registered DPO

D

Q

DPRA[3:0]

AR[3:0]

AW[3:0]

G Function Generator

SPO (Single Port Out)

Registered SPO

In practical terms, WE is usually generated by a 2X clock. If

a 2X clock is not available, the falling edge of the system

clock can be used. However, there are inherent risks in this

approach, since the WE pulse must be guaranteed inactive

before the next rising edge of the system clock. Several

older application notes are available from Xilinx that dis-

cuss the design of level-sensitive RAMs.

WE

D

Q

D

A[3:0]

AR[3:0]

AW[3:0]

F Function Generator

WCLK

X6755

Figure 6: XC4000 Series Dual-Port RAM, Simple

Model

However, the edge-triggered RAM available in the XC4000

Series is superior to level-sensitive RAM for almost every

application.

May 14, 1999 (Version 1.6)

6-15

Product Obsolete or Under Obsolescence

R

XC4000E and XC4000X Series Field Programmable Gate Arrays

4

C

• • • C

4

1

EC

D

0

WE

1

D

IN

WRITE

DECODER

16-LATCH

ARRAY

G'

MUX

4

1 of 16

LATCH

ENABLE

READ

ADDRESS

WRITE PULSE

4

G

• • • G

4

1

D

IN

WRITE

DECODER

16-LATCH

ARRAY

F'

MUX

4

F

• • • F

4

1

1 of 16

LATCH

ENABLE

K

READ

ADDRESS

(CLOCK)

WRITE PULSE

X6748

Figure 7: 16x1 Edge-Triggered Dual-Port RAM

Figure 8 shows the write timing for level-sensitive, sin-

gle-port RAM.

attached to the RAM or ROM symbol, as described in the

schematic library guide. If not deﬁned, all RAM contents

are initialized to all zeros, by default.

The relationships between CLB pins and RAM inputs and

outputs for single-port level-sensitive mode are shown in

Table 7.

RAM initialization occurs only during conﬁguration. The

RAM content is not affected by Global Set/Reset.

Figure 9 and Figure 10 show block diagrams of a CLB con-

ﬁgured as 16x2 and 32x1 level-sensitive, single-port RAM.

Table 7: Single-Port Level-Sensitive RAM Signals

RAM Signal

CLB Pin

D0 or D1

Function

Data In

D

Initializing RAM at Conﬁguration

A[3:0]

WE

O

F1-F4 or G1-G4

WE

F’ or G’

Address

Write Enable

Data Out

Both RAM and ROM implementations of the XC4000

Series devices are initialized during conﬁguration. The ini-

tial contents are deﬁned via an INIT attribute or property

T

WC

ADDRESS

T

AS

T

WP

AH

T

WRITE ENABLE

DATA IN

T

DH

DS

REQUIRED

X6462

Figure 8: Level-Sensitive RAM Write Timing

6-16

May 14, 1999 (Version 1.6)

Product Obsolete or Under Obsolescence

R

XC4000E and XC4000X Series Field Programmable Gate Arrays

4

C

• • • C

1

4

EC

WE

D

0

1

D

IN

Enable

WRITE

DECODER

16-LATCH

ARRAY

G'

MUX

4

G

• • • G

4

1

1 of 16

4

READ ADDRESS

D

IN

Enable

WRITE

DECODER

16-LATCH

ARRAY

F'

MUX

4

F

• • • F

4

1

1 of 16

4

READ ADDRESS

X6746

6

Figure 9: 16x2 (or 16x1) Level-Sensitive Single-Port RAM

4

C

• • • C

1

4

EC

D /A

D

0

WE

1

4

D

IN

Enable

WRITE

DECODER

16-LATCH

ARRAY

G'

MUX

G

F

• • • G

• • • F

4

1

4

1 of 16

4

READ ADDRESS

H'

D

IN

Enable

WRITE

DECODER

16-LATCH

ARRAY

F'

MUX

4

1 of 16

4

READ ADDRESS

X6749

Figure 10: 32x1 Level-Sensitive Single-Port RAM (F and G addresses are identical)

May 14, 1999 (Version 1.6)

6-17

Product Obsolete or Under Obsolescence

R

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000.” This discussion also applies to XC4000E

devices, and to XC4000X devices when the minor logic

changes are taken into account.

Fast Carry Logic

Each CLB F and G function generator contains dedicated

arithmetic logic for the fast generation of carry and borrow

signals. This extra output is passed on to the function gen-

erator in the adjacent CLB. The carry chain is independent

of normal routing resources.

The fast carry logic can be accessed by placing special

library symbols, or by using Xilinx Relationally Placed Mac-

ros (RPMs) that already include these symbols.

Dedicated fast carry logic greatly increases the efﬁciency

and performance of adders, subtractors, accumulators,

comparators and counters. It also opens the door to many

new applications involving arithmetic operation, where the

previous generations of FPGAs were not fast enough or too

inefﬁcient. High-speed address offset calculations in micro-

processor or graphics systems, and high-speed addition in

digital signal processing are two typical applications.

CLB

The two 4-input function generators can be conﬁgured as a

2-bit adder with built-in hidden carry that can be expanded

to any length. This dedicated carry circuitry is so fast and

efﬁcient that conventional speed-up methods like carry

generate/propagate are meaningless even at the 16-bit

level, and of marginal beneﬁt at the 32-bit level.

This fast carry logic is one of the more signiﬁcant features

of the XC4000 Series, speeding up arithmetic and counting

into the 70 MHz range.

The carry chain in XC4000E devices can run either up or

down. At the top and bottom of the columns where there

are no CLBs above or below, the carry is propagated to the

right. (See Figure 11.) In order to improve speed in the

high-capacity XC4000X devices, which can potentially

have very long carry chains, the carry chain travels upward

only, as shown in Figure 12. Additionally, standard intercon-

nect can be used to route a carry signal in the downward

direction.

X6687

Figure 11: Available XC4000E Carry Propagation

Paths

CLB

Figure 13 on page 19 shows an XC4000E CLB with dedi-

cated fast carry logic. The carry logic in the XC4000X is

similar, except that COUT exits at the top only, and the sig-

nal CINDOWN does not exist. As shown in Figure 13, the

carry logic shares operand and control inputs with the func-

tion generators. The carry outputs connect to the function

generators, where they are combined with the operands to

form the sums.

Figure 14 on page 20 shows the details of the carry logic

for the XC4000E. This diagram shows the contents of the

box labeled “CARRY LOGIC” in Figure 13. The XC4000X

carry logic is very similar, but a multiplexer on the

pass-through carry chain has been eliminated to reduce

delay. Additionally, in the XC4000X the multiplexer on the

G4 path has a memory-programmable 0 input, which per-

mits G4 to directly connect to COUT. G4 thus becomes an

additional high-speed initialization path for carry-in.

X6610

Figure 12: Available XC4000X Carry Propagation

Paths (dotted lines use general interconnect)

The dedicated carry logic is discussed in detail in Xilinx

document XAPP 013: “Using the Dedicated Carry Logic in

6-18

May 14, 1999 (Version 1.6)

Product Obsolete or Under Obsolescence

R

XC4000E and XC4000X Series Field Programmable Gate Arrays

D

C

IN

OUT

DOWN

CARRY

LOGIC

G

H

Y

G

CARRY

G4

G3

G2

G

DIN

H

S/R

EC

D

Q

YQ

G

F

G1

H1

C

OUT0

6

H

DIN

H

S/R

EC

F

CARRY

D

Q

XQ

G

F

F4

F3

F2

F1

F

H

F

X

K

S/R

EC

C

INUP

OUT

X6699

Figure 13: Fast Carry Logic in XC4000E CLB (shaded area not present in XC4000X)

May 14, 1999 (Version 1.6)

6-19

Product Obsolete or Under Obsolescence

R

XC4000E and XC4000X Series Field Programmable Gate Arrays

C

OUT

M

G1

M

1

0

1

G2

G3

0

I

G4

C

OUT0

TO

FUNCTION

GENERATORS

M

F2

F1

M

1

0

1

M

F4

M

0

1

3

1

0

F3

M

1

0

C

INUP

C

X2000

IN DOWN

Figure 14: Detail of XC4000E Dedicated Carry Logic

The choice is made by placing the appropriate library sym-

bol. For example, IFD is the basic input ﬂip-ﬂop (rising edge

triggered), and ILD is the basic input latch (transpar-

ent-High). Variations with inverted clocks are available, and

some combinations of latches and ﬂip-ﬂops can be imple-

mented in a single IOB, as described in the XACT Libraries

Guide.

Input/Output Blocks (IOBs)

User-conﬁgurable input/output blocks (IOBs) provide the

interface between external package pins and the internal

logic. Each IOB controls one package pin and can be con-

ﬁgured for input, output, or bidirectional signals.

Figure 15 shows a simpliﬁed block diagram of the

XC4000E IOB. A more complete diagram which includes

the boundary scan logic of the XC4000E IOB can be found

in Figure 40 on page 43, in the “Boundary Scan” section.

The XC4000E inputs can be globally conﬁgured for either

TTL (1.2V) or 5.0 volt CMOS thresholds, using an option in

the bitstream generation software. There is a slight input

hysteresis of about 300mV. The XC4000E output levels are

also conﬁgurable; the two global adjustments of input

threshold and output level are independent.

The XC4000X IOB contains some special features not

included in the XC4000E IOB. These features are high-

lighted in a simpliﬁed block diagram found in Figure 16, and

discussed throughout this section. When XC4000X special

features are discussed, they are clearly identiﬁed in the

text. Any feature not so identiﬁed is present in both

XC4000E and XC4000X devices.

Inputs on the XC4000XL are TTL compatible and 3.3V

CMOS compatible. Outputs on the XC4000XL are pulled to

the 3.3V positive supply.

The inputs of XC4000 Series 5-Volt devices can be driven

by the outputs of any 3.3-Volt device, if the 5-Volt inputs are

in TTL mode.

IOB Input Signals

Two paths, labeled I1 and I2 in Figure 15 and Figure 16,

bring input signals into the array. Inputs also connect to an

input register that can be programmed as either an

edge-triggered ﬂip-ﬂop or a level-sensitive latch.

Supported sources for XC4000 Series device inputs are

shown in Table 8.

6-20

May 14, 1999 (Version 1.6)

Product Obsolete or Under Obsolescence

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Passive

Slew Rate

Control

Pull-Up/

Pull-Down

T

Flip-Flop

D

Q

Out

Output

Buffer

CE

Pad

Output

Clock

I

1

Input

Buffer

Flip-

Flop/

Latch

I

2

Q

D

Delay

Clock

Enable

CE

Input

Clock

6

X6704

Figure 15: Simpliﬁed Block Diagram of XC4000E IOB

Passive

Pull-Up/

Pull-Down

Slew Rate

Control

T

Output MUX

0

1

Flip-Flop

Out

D

Q

Output

Buffer

CE

Pad

Input

Buffer

Output Clock

I

1

2

Flip-Flop/

Latch

Delay

Q

Delay

Q

D

Latch

G

Clock Enable

Input Clock

CE

Fast

Capture

Latch

X5984

Figure 16: Simpliﬁed Block Diagram of XC4000X IOB (shaded areas indicate differences from XC4000E)

May 14, 1999 (Version 1.6)

6-21

Product Obsolete or Under Obsolescence

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Table 8: Supported Sources for XC4000 Series Device

Inputs

Optional Delay Guarantees Zero Hold Time

The data input to the register can optionally be delayed by

several nanoseconds. With the delay enabled, the setup

time of the input ﬂip-ﬂop is increased so that normal clock

routing does not result in a positive hold-time requirement.

A positive hold time requirement can lead to unreliable,

temperature- or processing-dependent operation.

XC4000E/EX XC4000XL

Series Inputs Series Inputs

Source

5 V,

3.3 V

TTL CMOS

CMOS

Any device, Vcc = 3.3 V,

CMOS outputs

√

The input ﬂip-ﬂop setup time is deﬁned between the data

measured at the device I/O pin and the clock input at the

IOB (not at the clock pin). Any routing delay from the device

clock pin to the clock input of the IOB must, therefore, be

subtracted from this setup time to arrive at the real setup

time requirement relative to the device pins. A short speci-

ﬁed setup time might, therefore, result in a negative setup

time at the device pins, i.e., a positive hold-time require-

ment.

Unreli

-able

Data

XC4000 Series, Vcc = 5 V,

TTL outputs

√

Any device, Vcc = 5 V,

TTL outputs (Voh ≤ 3.7 V)

Any device, Vcc = 5 V,

CMOS outputs

√

XC4000XL 5-Volt Tolerant I/Os

When a delay is inserted on the data line, more clock delay

can be tolerated without causing a positive hold-time

requirement. Sufﬁcient delay eliminates the possibility of a

data hold-time requirement at the external pin. The maxi-

mum delay is therefore inserted as the default.

The I/Os on the XC4000XL are fully 5-volt tolerant even

though the V_CCis 3.3 volts. This allows 5 V signals to

directly connect to the XC4000XL inputs without damage,

as shown in Table 8. In addition, the 3.3 volt V_CCcan be

applied before or after 5 volt signals are applied to the I/Os.

This makes the XC4000XL immune to power supply

sequencing problems.

The XC4000E IOB has a one-tap delay element: either the

delay is inserted (default), or it is not. The delay guarantees

a zero hold time with respect to clocks routed through any

of the XC4000E global clock buffers. (See “Global Nets and

Buffers (XC4000E only)” on page 35 for a description of the

global clock buffers in the XC4000E.) For a shorter input

register setup time, with non-zero hold, attach a NODELAY

attribute or property to the ﬂip-ﬂop.

Registered Inputs

The I1 and I2 signals that exit the block can each carry

either the direct or registered input signal.

The input and output storage elements in each IOB have a

common clock enable input, which, through conﬁguration,

can be activated individually for the input or output ﬂip-ﬂop,

or both. This clock enable operates exactly like the EC pin

on the XC4000 Series CLB. It cannot be inverted within the

IOB.

The XC4000X IOB has a two-tap delay element, with

choices of a full delay, a partial delay, or no delay. The

attributes or properties used to select the desired delay are

shown in Table 10. The choices are no added attribute,

MEDDELAY, and NODELAY. The default setting, with no

added attribute, ensures no hold time with respect to any of

the XC4000X clock buffers, including the Global Low-Skew

buffers. MEDDELAY ensures no hold time with respect to

the Global Early buffers. Inputs with NODELAY may have a

positive hold time with respect to all clock buffers. For a

description of each of these buffers, see “Global Nets and

Buffers (XC4000X only)” on page 37.

The storage element behavior is shown in Table 9.

Table 9: Input Register Functionality

(active rising edge is shown)

Clock

Enable

Mode

Clock

D

Q

Power-Up or

GSR

X

SR

Table 10: XC4000X IOB Input Delay Element

Flip-Flop

__/

0

1*

X

D

X

D

X

D

Q

D

Q

Value

full delay

When to Use

Latch

1

1*

0

Zero Hold with respect to Global

0

(default, no

Low-Skew Buffer, Global Early Buffer

attribute added)

Both

X

Legend:

MEDDELAY

Zero Hold with respect to Global Early

Buffer

X

Don’t care

Rising edge

Set or Reset value. Reset is default.

Input is Low or unconnected (default value)

Input is High or unconnected (default value)

__/

SR

0*

NODELAY

Short Setup, positive Hold time

1*

6-22

May 14, 1999 (Version 1.6)

Product Obsolete or Under Obsolescence

R

XC4000E and XC4000X Series Field Programmable Gate Arrays

Additional Input Latch for Fast Capture (XC4000X only)

the desired delay based on the discussion in the previous

subsection.

The XC4000X IOB has an additional optional latch on the

input. This latch, as shown in Figure 16, is clocked by the

output clock — the clock used for the output ﬂip-ﬂop —

rather than the input clock. Therefore, two different clocks

can be used to clock the two input storage elements. This

additional latch allows the very fast capture of input data,

which is then synchronized to the internal clock by the IOB

ﬂip-ﬂop or latch.

IOB Output Signals

Output signals can be optionally inverted within the IOB,

and can pass directly to the pad or be stored in an

edge-triggered ﬂip-ﬂop. The functionality of this ﬂip-ﬂop is

shown in Table 11.

An active-High 3-state signal can be used to place the out-

put buffer in a high-impedance state, implementing 3-state

outputs or bidirectional I/O. Under conﬁguration control, the

output (OUT) and output 3-state (T) signals can be

inverted. The polarity of these signals is independently con-

ﬁgured for each IOB.

To use this Fast Capture technique, drive the output clock

pin (the Fast Capture latching signal) from the output of one

of the Global Early buffers supplied in the XC4000X. The

second storage element should be clocked by a Global

Low-Skew buffer, to synchronize the incoming data to the

internal logic. (See Figure 17.) These special buffers are

described in “Global Nets and Buffers (XC4000X only)” on

page 37.

The 4-mA maximum output current speciﬁcation of many

FPGAs often forces the user to add external buffers, which

are especially cumbersome on bidirectional I/O lines. The

XC4000E and XC4000EX/XL devices solve many of these

problems by providing a guaranteed output sink current of

12 mA. Two adjacent outputs can be interconnected exter-

nally to sink up to 24 mA. The XC4000E and XC4000EX/XL

FPGAs can thus directly drive buses on a printed circuit

board.

The Fast Capture latch (FCL) is designed primarily for use

with a Global Early buffer. For Fast Capture, a single clock

signal is routed through both a Global Early buffer and a

Global Low-Skew buffer. (The two buffers share an input

pad.) The Fast Capture latch is clocked by the Global Early

buffer, and the standard IOB ﬂip-ﬂop or latch is clocked by

the Global Low-Skew buffer. This mode is the safest way to

use the Fast Capture latch, because the clock buffers on

both storage elements are driven by the same pad. There is

no external skew between clock pads to create potential

problems.

6

By default, the output pull-up structure is conﬁgured as a

TTL-like totem-pole. The High driver is an n-channel pull-up

transistor, pulling to a voltage one transistor threshold

below Vcc. Alternatively, the outputs can be globally conﬁg-

ured as CMOS drivers, with p-channel pull-up transistors

pulling to Vcc. This option, applied using the bitstream gen-

eration software, applies to all outputs on the device. It is

not individually programmable. In the XC4000XL, all out-

puts are pulled to the positive supply rail.

To place the Fast Capture latch in a design, use one of the

special library symbols, ILFFX or ILFLX. ILFFX is a trans-

parent-Low Fast Capture latch followed by an active-High

input ﬂip-ﬂop. ILFLX is a transparent-Low Fast Capture

latch followed by a transparent-High input latch. Any of the

clock inputs can be inverted before driving the library ele-

ment, and the inverter is absorbed into the IOB. If a single

BUFG output is used to drive both clock inputs, the soft-

ware automatically runs the clock through both a Global

Low-Skew buffer and a Global Early buffer, and clocks the

Fast Capture latch appropriately.

Table 11: Output Flip-Flop Functionality (active rising

edge is shown)

Clock

Mode

Clock

Enable

T

D

Q

Power-Up

or GSR

X

0*

X

SR

Figure 16 on page 21 also shows a two-tap delay on the

input. By default, if the Fast Capture latch is used, the Xilinx

software assumes a Global Early buffer is driving the clock,

and selects MEDDELAY to ensure a zero hold time. Select

X

__/

X

0

1*

X

0*

1

X

D

X

Q

D

Z

Flip-Flop

0

X

0*

Q

Legend:

ILFFX

X

__/

SR

0*

Don’t care

Rising edge

to internal

logic

IPAD

D

Q

Set or Reset value. Reset is default.

Input is Low or unconnected (default value)

Input is High or unconnected (default value)

3-state

GF

1*

Z

BUFGE

CE

C

IPAD

BUFGLS

X9013

Figure 17: Examples Using XC4000X FCL

May 14, 1999 (Version 1.6)

6-23

Product Obsolete or Under Obsolescence

R

XC4000E and XC4000X Series Field Programmable Gate Arrays

Any XC4000 Series 5-Volt device with its outputs conﬁg-

ured in TTL mode can drive the inputs of any typical

3.3-Volt device. (For a detailed discussion of how to inter-

face between 5 V and 3.3 V devices, see the 3V Products

section of The Programmable Logic Data Book.)

Power/Ground pin pairs are connected to special Power

and Ground planes within the packages, to reduce ground

bounce. Therefore, the maximum total capacitive load is

300 pF between each external Power/Ground pin pair.

Maximum loading may vary for the low-voltage devices.

Supported destinations for XC4000 Series device outputs

are shown in Table 12.

For slew-rate limited outputs this total is two times larger for

each device type: 400 pF for XC4000E devices and 600 pF

for XC4000X devices. This maximum capacitive load

should not be exceeded, as it can result in ground bounce

of greater than 1.5 V amplitude and more than 5 ns dura-

tion. This level of ground bounce may cause undesired

transient behavior on an output, or in the internal logic. This

restriction is common to all high-speed digital ICs, and is

not particular to Xilinx or the XC4000 Series.

An output can be conﬁgured as open-drain (open-collector)

by placing an OBUFT symbol in a schematic or HDL code,

then tying the 3-state pin (T) to the output signal, and the

input pin (I) to Ground. (See Figure 18.)

Table 12: Supported Destinations for XC4000 Series

Outputs

XC4000 Series devices have a feature called “Soft

Start-up,” designed to reduce ground bounce when all out-

puts are turned on simultaneously at the end of conﬁgura-

tion. When the conﬁguration process is ﬁnished and the

device starts up, the ﬁrst activation of the outputs is auto-

matically slew-rate limited. Immediately following the initial

activation of the I/O, the slew rate of the individual outputs

is determined by the individual conﬁguration option for each

IOB.

XC4000 Series

Outputs

Destination

3.3 V,

5 V,

CMOS TTL CMOS

Any typical device, Vcc = 3.3 V,

CMOS-threshold inputs

√

some¹

Any device, Vcc = 5 V,

TTL-threshold inputs

√

Any device, Vcc = 5 V,

CMOS-threshold inputs

Unreliable

Data

Global Three-State

1. Only if destination device has 5-V tolerant inputs

A separate Global 3-State line (not shown in Figure 15 or

Figure 16) forces all FPGA outputs to the high-impedance

state, unless boundary scan is enabled and is executing an

EXTEST instruction. This global net (GTS) does not com-

pete with other routing resources; it uses a dedicated distri-

bution network.

OPAD

OBUFT

X6702

GTS can be driven from any user-programmable pin as a

global 3-state input. To use this global net, place an input

pad and input buffer in the schematic or HDL code, driving

the GTS pin of the STARTUP symbol. A speciﬁc pin loca-

tion can be assigned to this input using a LOC attribute or

property, just as with any other user-programmable pad. An

inverter can optionally be inserted after the input buffer to

invert the sense of the Global 3-State signal. Using GTS is

similar to GSR. See Figure 2 on page 11 for details.

Figure 18: Open-Drain Output

Output Slew Rate

The slew rate of each output buffer is, by default, reduced,

to minimize power bus transients when switching non-criti-

cal signals. For critical signals, attach a FAST attribute or

property to the output buffer or ﬂip-ﬂop.

For XC4000E devices, maximum total capacitive load for

simultaneous fast mode switching in the same direction is

200 pF for all package pins between each Power/Ground

pin pair. For XC4000X devices, additional internal

Alternatively, GTS can be driven from any internal node.

6-24

May 14, 1999 (Version 1.6)

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R

XC4000E and XC4000X Series Field Programmable Gate Arrays

Output Multiplexer/2-Input Function Generator

(XC4000X only)

Other IOB Options

There are a number of other programmable options in the

XC4000 Series IOB.

As shown in Figure 16 on page 21, the output path in the

XC4000X IOB contains an additional multiplexer not avail-

able in the XC4000E IOB. The multiplexer can also be con-

ﬁgured as a 2-input function generator, implementing a

pass-gate, AND-gate, OR-gate, or XOR-gate, with 0, 1, or 2

inverted inputs. The logic used to implement these func-

tions is shown in the upper gray area of Figure 16.

Pull-up and Pull-down Resistors

Programmable pull-up and pull-down resistors are useful

for tying unused pins to Vcc or Ground to minimize power

consumption and reduce noise sensitivity. The conﬁgurable

pull-up resistor is a p-channel transistor that pulls to Vcc.

The conﬁgurable pull-down resistor is an n-channel transis-

tor that pulls to Ground.

When conﬁgured as a multiplexer, this feature allows two

output signals to time-share the same output pad; effec-

tively doubling the number of device outputs without requir-

ing a larger, more expensive package.

The value of these resistors is 50 kΩ − 100 kΩ. This high

value makes them unsuitable as wired-AND pull-up resis-

tors.

When the MUX is conﬁgured as a 2-input function genera-

tor, logic can be implemented within the IOB itself. Com-

bined with a Global Early buffer, this arrangement allows

very high-speed gating of a single signal. For example, a

wide decoder can be implemented in CLBs, and its output

gated with a Read or Write Strobe Driven by a BUFGE

buffer, as shown in Figure 19. The critical-path pin-to-pin

delay of this circuit is less than 6 nanoseconds.

The pull-up resistors for most user-programmable IOBs are

active during the conﬁguration process. See Table 22 on

page 58 for a list of pins with pull-ups active before and dur-

ing conﬁguration.

After conﬁguration, voltage levels of unused pads, bonded

or un-bonded, must be valid logic levels, to reduce noise

sensitivity and avoid excess current. Therefore, by default,

unused pads are conﬁgured with the internal pull-up resis-

tor active. Alternatively, they can be individually conﬁgured

with the pull-down resistor, or as a driven output, or to be

driven by an external source. To activate the internal

pull-up, attach the PULLUP library component to the net

attached to the pad. To activate the internal pull-down,

attach the PULLDOWN library component to the net

attached to the pad.

As shown in Figure 16, the IOB input pins Out, Output

Clock, and Clock Enable have different delays and different

ﬂexibilities regarding polarity. Additionally, Output Clock

sources are more limited than the other inputs. Therefore,

the Xilinx software does not move logic into the IOB func-

tion generators unless explicitly directed to do so.

6

The user can specify that the IOB function generator be

used, by placing special library symbols beginning with the

letter “O.” For example, a 2-input AND-gate in the IOB func-

tion generator is called OAND2. Use the symbol input pin

labelled “F” for the signal on the critical path. This signal is

placed on the OK pin — the IOB input with the shortest

delay to the function generator. Two examples are shown in

Figure 20.

Independent Clocks

Separate clock signals are provided for the input and output

ﬂip-ﬂops. The clock can be independently inverted for each

ﬂip-ﬂop within the IOB, generating either falling-edge or ris-

ing-edge triggered ﬂip-ﬂops. The clock inputs for each IOB

are independent, except that in the XC4000X, the Fast

Capture latch shares an IOB input with the output clock pin.

IPAD

Early Clock for IOBs (XC4000X only)

BUFGE

F

Special early clocks are available for IOBs. These clocks

are sourced by the same sources as the Global Low-Skew

buffers, but are separately buffered. They have fewer loads

and therefore less delay. The early clock can drive either

the IOB output clock or the IOB input clock, or both. The

early clock allows fast capture of input data, and fast

clock-to-output on output data. The Global Early buffers

that drive these clocks are described in “Global Nets and

Buffers (XC4000X only)” on page 37.

OPAD

from

internal

logic

FAST

OAND2

X9019

Figure 19: Fast Pin-to-Pin Path in XC4000X

OMUX2

D0

D1

S0

F

O

Global Set/Reset

OAND2

As with the CLB registers, the Global Set/Reset signal

(GSR) can be used to set or clear the input and output reg-

isters, depending on the value of the INIT attribute or prop-

erty. The two ﬂip-ﬂops can be individually conﬁgured to set

X6598

X6599

Figure 20: AND & MUX Symbols in XC4000X IOB

May 14, 1999 (Version 1.6)

6-25

Product Obsolete or Under Obsolescence

R

XC4000E and XC4000X Series Field Programmable Gate Arrays

or clear on reset and after conﬁguration. Other than the glo-

bal GSR net, no user-controlled set/reset signal is available

to the I/O ﬂip-ﬂops. The choice of set or clear applies to

both the initial state of the ﬂip-ﬂop and the response to the

Global Set/Reset pulse. See “Global Set/Reset” on

page 11 for a description of how to use GSR.

Standard 3-State Buffer

All three pins are used. Place the library element BUFT.

Connect the input to the I pin and the output to the O pin.

The T pin is an active-High 3-state (i.e. an active-Low

enable). Tie the T pin to Ground to implement a standard

buffer.

JTAG Support

Wired-AND with Input on the I Pin

Embedded logic attached to the IOBs contains test struc-

tures compatible with IEEE Standard 1149.1 for boundary

scan testing, permitting easy chip and board-level testing.

More information is provided in “Boundary Scan” on

page 42.

The buffer can be used as a Wired-AND. Use the WAND1

library symbol, which is essentially an open-drain buffer.

WAND4, WAND8, and WAND16 are also available. See the

XACT Libraries Guide for further information.

The T pin is internally tied to the I pin. Connect the input to

the I pin and the output to the O pin. Connect the outputs of

all the WAND1s together and attach a PULLUP symbol.

Three-State Buffers

A pair of 3-state buffers is associated with each CLB in the

array. (See Figure 27 on page 30.) These 3-state buffers

can be used to drive signals onto the nearest horizontal

longlines above and below the CLB. They can therefore be

used to implement multiplexed or bidirectional buses on the

horizontal longlines, saving logic resources. Programmable

pull-up resistors attached to these longlines help to imple-

ment a wide wired-AND function.

Wired OR-AND

The buffer can be conﬁgured as a Wired OR-AND. A High

level on either input turns off the output. Use the

WOR2AND library symbol, which is essentially an

open-drain 2-input OR gate. The two input pins are func-

tionally equivalent. Attach the two inputs to the I0 and I1

pins and tie the output to the O pin. Tie the outputs of all the

WOR2ANDs together and attach a PULLUP symbol.

The buffer enable is an active-High 3-state (i.e. an

active-Low enable), as shown in Table 13.

Three-State Buffer Examples

Another 3-state buffer with similar access is located near

each I/O block along the right and left edges of the array.

(See Figure 33 on page 34.)

Figure 21 shows how to use the 3-state buffers to imple-

ment a wired-AND function. When all the buffer inputs are

High, the pull-up resistor(s) provide the High output.

The horizontal longlines driven by the 3-state buffers have

a weak keeper at each end. This circuit prevents undeﬁned

ﬂoating levels. However, it is overridden by any driver, even

a pull-up resistor.

Figure 22 shows how to use the 3-state buffers to imple-

ment a multiplexer. The selection is accomplished by the

buffer 3-state signal.

Pay particular attention to the polarity of the T pin when

using these buffers in a design. Active-High 3-state (T) is

identical to an active-Low output enable, as shown in

Table 13.

Special longlines running along the perimeter of the array

can be used to wire-AND signals coming from nearby IOBs

or from internal longlines. These longlines form the wide

edge decoders discussed in “Wide Edge Decoders” on

page 27.

Table 13: Three-State Buffer Functionality

Three-State Buffer Modes

IN

X

T

1

0

OUT

Z

The 3-state buffers can be conﬁgured in three modes:

IN

•

Standard 3-state buffer

Wired-AND with input on the I pin

Wired OR-AND

P

U

L

Z = D

●

D

●

(D +D

)

●

(D +D )

E F

A

B

C

D

U

P

L

D

C

D

E

F

D

A

D

B

WAND1

WOR2AND

X6465

Figure 21: Open-Drain Buffers Implement a Wired-AND Function

6-26

May 14, 1999 (Version 1.6)

Product Obsolete or Under Obsolescence

R

XC4000E and XC4000X Series Field Programmable Gate Arrays

Z = D • A + D • B + D • C + D • N

A

B

C

N

~100 kΩ

D

N

A

B

C

BUFT

A

B

C

N

X6466

"Weak Keeper"

Figure 22: 3-State Buffers Implement a Multiplexer

Wide Edge Decoders

Dedicated decoder circuitry boosts the performance of

wide decoding functions. When the address or data ﬁeld is

wider than the function generator inputs, FPGAs need

multi-level decoding and are thus slower than PALs.

XC4000 Series CLBs have nine inputs. Any decoder of up

to nine inputs is, therefore, compact and fast. However,

there is also a need for much wider decoders, especially for

address decoding in large microprocessor systems.

LUP symbol. Location attributes or properties such as L

(left edge) or TR (right half of top edge) should also be used

to ensure the correct placement of the decoder inputs.

INTERCONNECT

IOB

.I1

IOB

.I1

A

C

B

An XC4000 Series FPGA has four programmable decoders

located on each edge of the device. The inputs to each

decoder are any of the IOB I1 signals on that edge plus one

local interconnect per CLB row or column. Each row or col-

umn of CLBs provides up to three variables or their compli-

ments., as shown in Figure 23. Each decoder generates a

High output (resistor pull-up) when the AND condition of

the selected inputs, or their complements, is true. This is

analogous to a product term in typical PAL devices.

6

(

C) .....

(A • B • C) .....

X2627

Each of these wired-AND gates is capable of accepting up

to 42 inputs on the XC4005E and 72 on the XC4013E.

There are up to 96 inputs for each decoder on the

XC4028X and 132 on the XC4052X. The decoders may

also be split in two when a larger number of narrower

decoders are required, for a maximum of 32 decoders per

device.

Figure 23: XC4000 Series Edge Decoding Example

OSC4

F8M

F500K

F16K

F490

F15

The decoder outputs can drive CLB inputs, so they can be

combined with other logic to form a PAL-like AND/OR struc-

ture. The decoder outputs can also be routed directly to the

chip outputs. For fastest speed, the output should be on the

same chip edge as the decoder. Very large PALs can be

emulated by ORing the decoder outputs in a CLB. This

decoding feature covers what has long been considered a

weakness of older FPGAs. Users often resorted to external

PALs for simple but fast decoding functions. Now, the dedi-

cated decoders in the XC4000 Series device can imple-

ment these functions fast and efﬁciently.

X6703

Figure 24: XC4000 Series Oscillator Symbol

On-Chip Oscillator

XC4000 Series devices include an internal oscillator. This

oscillator is used to clock the power-on time-out, for conﬁg-

uration memory clearing, and as the source of CCLK in

Master conﬁguration modes. The oscillator runs at a nomi-

nal 8 MHz frequency that varies with process, Vcc, and

temperature. The output frequency falls between 4 and 10

MHz.

To use the wide edge decoders, place one or more of the

WAND library symbols (WAND1, WAND4, WAND8,

WAND16). Attach a DECODE attribute or property to each

WAND symbol. Tie the outputs together and attach a PUL-

May 14, 1999 (Version 1.6)

6-27

Product Obsolete or Under Obsolescence

R

XC4000E and XC4000X Series Field Programmable Gate Arrays

The oscillator output is optionally available after conﬁgura-

tion. Any two of four resynchronized taps of a built-in divider

are also available. These taps are at the fourth, ninth, four-

teenth and nineteenth bits of the divider. Therefore, if the

primary oscillator output is running at the nominal 8 MHz,

the user has access to an 8 MHz clock, plus any two of 500

kHz, 16kHz, 490Hz and 15Hz (up to 10% lower for low-volt-

age devices). These frequencies can vary by as much as

-50% or +25%.

• Global routing consists of dedicated networks primarily

designed to distribute clocks throughout the device with

minimum delay and skew. Global routing can also be

used for other high-fanout signals.

Five interconnect types are distinguished by the relative

length of their segments: single-length lines, double-length

lines, quad and octal lines (XC4000X only), and longlines.

In the XC4000X, direct connects allow fast data ﬂow

between adjacent CLBs, and between IOBs and CLBs.

These signals can be accessed by placing the OSC4

library element in a schematic or in HDL code (see

Figure 24).

Extra routing is included in the IOB pad ring. The XC4000X

also includes a ring of octal interconnect lines near the

IOBs to improve pin-swapping and routing to locked pins.

The oscillator is automatically disabled after conﬁguration if

the OSC4 symbol is not used in the design.

XC4000E/X devices include two types of global buffers.

These global buffers have different properties, and are

intended for different purposes. They are discussed in

detail later in this section.

Programmable Interconnect

All internal connections are composed of metal segments

with programmable switching points and switching matrices

to implement the desired routing. A structured, hierarchical

matrix of routing resources is provided to achieve efﬁcient

automated routing.

CLB Routing Connections

A high-level diagram of the routing resources associated

with one CLB is shown in Figure 25. The shaded arrows

represent routing present only in XC4000X devices.

The XC4000E and XC4000X share a basic interconnect

structure. XC4000X devices, however, have additional rout-

ing not available in the XC4000E. The extra routing

resources allow high utilization in high-capacity devices. All

XC4000X-speciﬁc routing resources are clearly identiﬁed

throughout this section. Any resources not identiﬁed as

XC4000X-speciﬁc are present in all XC4000 Series

devices.

Table 14 shows how much routing of each type is available

in XC4000E and XC4000X CLB arrays. Clearly, very large

designs, or designs with a great deal of interconnect, will

route more easily in the XC4000X. Smaller XC4000E

designs, typically requiring signiﬁcantly less interconnect,

do not require the additional routing.

Figure 27 on page 30 is a detailed diagram of both the

XC4000E and the XC4000X CLB, with associated routing.

The shaded square is the programmable switch matrix,

present in both the XC4000E and the XC4000X. The

L-shaped shaded area is present only in XC4000X devices.

As shown in the ﬁgure, the XC4000X block is essentially an

XC4000E block with additional routing.

This section describes the varied routing resources avail-

able in XC4000 Series devices. The implementation soft-

ware automatically assigns the appropriate resources

based on the density and timing requirements of the

design.

CLB inputs and outputs are distributed on all four sides,

providing maximum routing ﬂexibility. In general, the entire

architecture is symmetrical and regular. It is well suited to

established placement and routing algorithms. Inputs, out-

puts, and function generators can freely swap positions

within a CLB to avoid routing congestion during the place-

ment and routing operation.

Interconnect Overview

There are several types of interconnect.

•

CLB routing is associated with each row and column of

the CLB array.

•

IOB routing forms a ring (called a VersaRing) around

the outside of the CLB array. It connects the I/O with the

internal logic blocks.

6-28

May 14, 1999 (Version 1.6)

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Quad

Single

Double

Long

Direct

Connect

CLB

Long

Quad

Long Global Long Double Single Global Carry Direct

Clock

Clock Chain Connect

x5994

Figure 25: High-Level Routing Diagram of XC4000 Series CLB (shaded arrows indicate XC4000X only)

6

Table 14: Routing per CLB in XC4000 Series Devices

XC4000E

XC4000X

Vertical Horizontal Vertical Horizontal

Singles

Doubles

Quads

8

4

0

6

0

8

4

0

6

0

8

4

8

4

Double

Singles

Double

12

10

2

12

6

Longlines

Six Pass Transistors

Per Switch Matrix

Interconnect Point

Direct

Connects

2

Globals

Carry Logic

Total

4

2

0

8

1

0

X6600

Figure 26: Programmable Switch Matrix (PSM)

24

18

45

32

Single-Length Lines

Programmable Switch Matrices

Single-length lines provide the greatest interconnect ﬂexi-

bility and offer fast routing between adjacent blocks. There

are eight vertical and eight horizontal single-length lines

associated with each CLB. These lines connect the switch-

ing matrices that are located in every row and a column of

CLBs.

The horizontal and vertical single- and double-length lines

intersect at a box called a programmable switch matrix

(PSM). Each switch matrix consists of programmable pass

transistors used to establish connections between the lines

(see Figure 26).

For example, a single-length signal entering on the right

side of the switch matrix can be routed to a single-length

line on the top, left, or bottom sides, or any combination

thereof, if multiple branches are required. Similarly, a dou-

ble-length signal can be routed to a double-length line on

any or all of the other three edges of the programmable

switch matrix.

Single-length lines are connected by way of the program-

mable switch matrices, as shown in Figure 28. Routing

connectivity is shown in Figure 27.

Single-length lines incur a delay whenever they go through

a switching matrix. Therefore, they are not suitable for rout-

ing signals for long distances. They are normally used to

conduct signals within a localized area and to provide the

branching for nets with fanout greater than one.

May 14, 1999 (Version 1.6)

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XC4000E and XC4000X Series Field Programmable Gate Arrays

QUAD

DOUBLE

SINGLE

DOUBLE

LONG

F4 C4 G4

YQ

DIRECT

Y

G1

C1

F1

G3

CLB

C3

FEEDBACK

F3

K

X

XQ

F2 C2 G2

LONG

GLOBAL DIRECT

LONG

GLOBAL

LONG DOUBLE

DOUBLELONG

QUAD

SINGLE

FEEDBACK

Common to XC4000E and XC4000X

XC4000X only

Programmable Switch Matrix

Figure 27: Detail of Programmable Interconnect Associated with XC4000 Series CLB

6-30

May 14, 1999 (Version 1.6)

Product Obsolete or Under Obsolescence

R

XC4000E and XC4000X Series Field Programmable Gate Arrays

CLB

Doubles

Singles

Doubles

PSM

X6601

X9014

Figure 28: Single- and Double-Length Lines, with

Programmable Switch Matrices (PSMs)

Figure 29: Quad Lines (XC4000X only)

Double-Length Lines

and up to two independent outputs. Only one of the inde-

pendent inputs can be buffered.

The double-length lines consist of a grid of metal segments,

each twice as long as the single-length lines: they run past

two CLBs before entering a switch matrix. Double-length

lines are grouped in pairs with the switch matrices stag-

gered, so that each line goes through a switch matrix at

every other row or column of CLBs (see Figure 28).

6

The place and route software automatically uses the timing

requirements of the design to determine whether or not a

quad line signal should be buffered. A heavily loaded signal

is typically buffered, while a lightly loaded one is not. One

scenario is to alternate buffers and pass transistors. This

allows both vertical and horizontal quad lines to be buffered

at alternating buffered switch matrices.

There are four vertical and four horizontal double-length

lines associated with each CLB. These lines provide faster

signal routing over intermediate distances, while retaining

routing ﬂexibility. Double-length lines are connected by way

of the programmable switch matrices. Routing connectivity

is shown in Figure 27.

Due to the buffered switch matrices, quad lines are very

fast. They provide the fastest available method of routing

heavily loaded signals for long distances across the device.

Longlines

Quad Lines (XC4000X only)

Longlines form a grid of metal interconnect segments that

run the entire length or width of the array. Longlines are

intended for high fan-out, time-critical signal nets, or nets

that are distributed over long distances. In XC4000X

devices, quad lines are preferred for critical nets, because

the buffered switch matrices make them faster for high

fan-out nets.

XC4000X devices also include twelve vertical and twelve

horizontal quad lines per CLB row and column. Quad lines

are four times as long as the single-length lines. They are

interconnected via buffered switch matrices (shown as dia-

monds in Figure 27 on page 30). Quad lines run past four

CLBs before entering a buffered switch matrix. They are

grouped in fours, with the buffered switch matrices stag-

gered, so that each line goes through a buffered switch

matrix at every fourth CLB location in that row or column.

(See Figure 29.)

Two horizontal longlines per CLB can be driven by 3-state

or open-drain drivers (TBUFs). They can therefore imple-

ment unidirectional or bidirectional buses, wide multiplex-

ers, or wired-AND functions. (See “Three-State Buffers” on

page 26 for more details.)

The buffered switch matrixes have four pins, one on each

edge. All of the pins are bidirectional. Any pin can drive any

or all of the other pins.

Each horizontal longline driven by TBUFs has either two

(XC4000E) or eight (XC4000X) pull-up resistors. To acti-

vate these resistors, attach a PULLUP symbol to the

long-line net. The software automatically activates the

appropriate number of pull-ups. There is also a weak

keeper at each end of these two horizontal longlines. This

Each buffered switch matrix contains one buffer and six

pass transistors. It resembles the programmable switch

matrix shown in Figure 26, with the addition of a program-

mable buffer. There can be up to two independent inputs

May 14, 1999 (Version 1.6)

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XC4000E and XC4000X Series Field Programmable Gate Arrays

circuit prevents undeﬁned ﬂoating levels. However, it is

overridden by any driver, even a pull-up resistor.

I/O Routing

XC4000 Series devices have additional routing around the

IOB ring. This routing is called a VersaRing. The VersaRing

facilitates pin-swapping and redesign without affecting

board layout. Included are eight double-length lines span-

ning two CLBs (four IOBs), and four longlines. Global lines

and Wide Edge Decoder lines are provided. XC4000X

devices also include eight octal lines.

Each XC4000E longline has a programmable splitter switch

at its center, as does each XC4000X longline driven by

TBUFs. This switch can separate the line into two indepen-

dent routing channels, each running half the width or height

of the array.

Each XC4000X longline not driven by TBUFs has a buff-

ered programmable splitter switch at the 1/4, 1/2, and 3/4

points of the array. Due to the buffering, XC4000X longline

performance does not deteriorate with the larger array

sizes. If the longline is split, the resulting partial longlines

are independent.

A high-level diagram of the VersaRing is shown in

Figure 31. The shaded arrows represent routing present

only in XC4000X devices.

Figure 33 on page 34 is a detailed diagram of the XC4000E

and XC4000X VersaRing. The area shown includes two

IOBs. There are two IOBs per CLB row or column, there-

fore this diagram corresponds to the CLB routing diagram

shown in Figure 27 on page 30. The shaded areas repre-

sent routing and routing connections present only in

XC4000X devices.

Routing connectivity of the longlines is shown in Figure 27

on page 30.

Direct Interconnect (XC4000X only)

The XC4000X offers two direct, efﬁcient and fast connec-

tions between adjacent CLBs. These nets facilitate a data

ﬂow from the left to the right side of the device, or from the

top to the bottom, as shown in Figure 30. Signals routed on

the direct interconnect exhibit minimum interconnect prop-

agation delay and use no general routing resources.

Octal I/O Routing (XC4000X only)

Between the XC4000X CLB array and the pad ring, eight

interconnect tracks provide for versatility in pin assignment

and ﬁxed pinout ﬂexibility. (See Figure 32 on page 33.)

The direct interconnect is also present between CLBs and

adjacent IOBs. Each IOB on the left and top device edges

has a direct path to the nearest CLB. Each CLB on the right

and bottom edges of the array has a direct path to the near-

est two IOBs, since there are two IOBs for each row or col-

umn of CLBs.

These routing tracks are called octals, because they can be

broken every eight CLBs (sixteen IOBs) by a programma-

ble buffer that also functions as a splitter switch. The buffers

are staggered, so each line goes through a buffer at every

eighth CLB location around the device edge.

The octal lines bend around the corners of the device. The

lines cross at the corners in such a way that the segment

most recently buffered before the turn has the farthest dis-

tance to travel before the next buffer, as shown in

Figure 32.

The place and route software uses direct interconnect

whenever possible, to maximize routing resources and min-

imize interconnect delays.

IOB

CLB

~ ~

IOB

CLB

X6603

Figure 30: XC4000X Direct Interconnect

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XC4000E and XC4000X Series Field Programmable Gate Arrays

WED

IOB

Quad

WED

Single

Double

INTERCONNECT

Long

Direct

Connect

Long

IOB

WED

6

Direct

Edge Double Long Global Octal

Connect

Decode

Clock

X5995

Figure 31: High-Level Routing Diagram of XC4000 Series VersaRing (Left Edge)

WED = Wide Edge Decoder, IOB = I/O Block (shaded arrows indicate XC4000X only)

IOB

Segment with nearest buffer

connects to segment with furthest buffer

X9015

Figure 32: XC4000X Octal I/O Routing

May 14, 1999 (Version 1.6)

6-33

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XC4000E and XC4000X Series Field Programmable Gate Arrays

QUAD

T

O

DOUBLE

SINGLE

C

L

B

DOUBLE

LONG

A

R

A

Y

IOB

I1

I2

IK

OK

T

CE

O

DIRECT

IOB

T

O

OK

IK

I1

CE

I2

LONG

Common to XC4000E and XC4000X

XC4000X only

Figure 33: Detail of Programmable Interconnect Associated with XC4000 Series IOB (Left Edge)

6-34

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XC4000E and XC4000X Series Field Programmable Gate Arrays

IOB inputs and outputs interface with the octal lines via the

single-length interconnect lines. Single-length lines are

also used for communication between the octals and dou-

ble-length lines, quads, and longlines within the CLB array.

Two different types of clock buffers are available in the

XC4000E:

•

Primary Global Buffers (BUFGP)

Secondary Global Buffers (BUFGS)

Segmentation into buffered octals was found to be optimal

for distributing signals over long distances around the

device.

Four Primary Global buffers offer the shortest delay and

negligible skew. Four Secondary Global buffers have

slightly longer delay and slightly more skew due to poten-

tially heavier loading, but offer greater ﬂexibility when used

to drive non-clock CLB inputs.

Global Nets and Buffers

Both the XC4000E and the XC4000X have dedicated glo-

bal networks. These networks are designed to distribute

clocks and other high fanout control signals throughout the

devices with minimal skew. The global buffers are

described in detail in the following sections. The text

descriptions and diagrams are summarized in Table 15.

The table shows which CLB and IOB clock pins can be

sourced by which global buffers.

The Primary Global buffers must be driven by the

semi-dedicated pads. The Secondary Global buffers can

be sourced by either semi-dedicated pads or internal nets.

Each CLB column has four dedicated vertical Global lines.

Each of these lines can be accessed by one particular Pri-

mary Global buffer, or by any of the Secondary Global buff-

ers, as shown in Figure 34. Each corner of the device has

one Primary buffer and one Secondary buffer.

In both XC4000E and XC4000X devices, placement of a

library symbol called BUFG results in the software choos-

ing the appropriate clock buffer, based on the timing

requirements of the design. The detailed information in

these sections is included only for reference.

IOBs along the left and right edges have four vertical global

longlines. Top and bottom IOBs can be clocked from the

global lines in the adjacent CLB column.

A global buffer should be speciﬁed for all timing-sensitive

global signal distribution. To use a global buffer, place a

BUFGP (primary buffer), BUFGS (secondary buffer), or

BUFG (either primary or secondary buffer) element in a

schematic or in HDL code. If desired, attach a LOC

attribute or property to direct placement to the designated

location. For example, attach a LOC=L attribute or property

to a BUFGS symbol to direct that a buffer be placed in one

of the two Secondary Global buffers on the left edge of the

device, or a LOC=BL to indicate the Secondary Global

buffer on the bottom edge of the device, on the left.

6

Global Nets and Buffers (XC4000E only)

Four vertical longlines in each CLB column are driven

exclusively by special global buffers. These longlines are

in addition to the vertical longlines used for standard inter-

connect. The four global lines can be driven by either of two

types of global buffers. The clock pins of every CLB and

IOB can also be sourced from local interconnect.

Table 15: Clock Pin Access

XC4000E

XC4000X

Local

Inter-

connect

L & R

BUFGE

T & B

BUFGE

BUFGP

BUFGS

BUFGLS

All CLBs in Quadrant

All CLBs in Device

√

IOBs on Adjacent Vertical

Half Edge

√

IOBs on Adjacent Vertical

Full Edge

√

IOBs on Adjacent Horizontal

Half Edge (Direct)

IOBs on Adjacent Horizontal

Half Edge (through CLB globals)

√

IOBs on Adjacent Horizontal

Full Edge (through CLB globals)

L = Left, R = Right, T = Top, B = Bottom

May 14, 1999 (Version 1.6)

6-35

Product Obsolete or Under Obsolescence

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XC4000E and XC4000X Series Field Programmable Gate Arrays

IOB

BUFGS

BUFGP

PGCK1

SGCK4

PGCK4

SGCK1

4

BUFGS

BUFGP

4

locals

CLB

IOB

locals

Any BUFGS

X4

One BUFGP

per Global Line

One BUFGP

per Global Line

IOB

locals

BUFGP

BUFGS

SGCK3

PGCK2

SGCK2

PGCK3

BUFGP

BUFGS

IOB

X6604

Figure 34: XC4000E Global Net Distribution

IOB

BUFGLS

BUFGE

GCK1

GCK6

GCK8

GCK7

BUFGE

BUFGLS

BUFGE

CLB

X8

8

X4

8

X8

BUFGLS

locals

BUFGLS

locals

BUFGLS

8

locals

BUFGLS

locals

8

4

8

CLB CLOCKS

(PER COLUMN)

CLB CLOCKS

(PER COLUMN)

IOB

CLOCKS

IOB

CLOCKS

locals

IOB

CLOCKS

IOB

CLOCKS

CLB CLOCKS

(PER COLUMN)

CLB CLOCKS

(PER COLUMN)

IOB

8

locals

4

8

BUFGLS

8

8 BUFGLS

locals

BUFGLS

locals

BUFGLS

8

X4

X8

CLB

BUFGLS

BUFGE

GCK4

GCK2

GCK5

GCK3

X9018

BUFGLS

IOB

Figure 35: XC4000X Global Net Distribution

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Early and Global Low-Skew buffers share a common input;

they cannot be driven by two different signals.

Global Nets and Buffers (XC4000X only)

Eight vertical longlines in each CLB column are driven by

special global buffers. These longlines are in addition to the

vertical longlines used for standard interconnect. The glo-

bal lines are broken in the center of the array, to allow faster

distribution and to minimize skew across the whole array.

Each half-column global line has its own buffered multi-

plexer, as shown in Figure 35. The top and bottom global

lines cannot be connected across the center of the device,

as this connection might introduce unacceptable skew. The

top and bottom halves of the global lines must be sepa-

rately driven — although they can be driven by the same

global buffer.

Choosing an XC4000X Clock Buffer

The clocking structure of the XC4000X provides a large

variety of features. However, it can be simple to use, with-

out understanding all the details. The software automati-

cally handles clocks, along with all other routing, when the

appropriate clock buffer is placed in the design. In fact, if a

buffer symbol called BUFG is placed, rather than a speciﬁc

type of buffer, the software even chooses the buffer most

appropriate for the design. The detailed information in this

section is provided for those users who want a ﬁner level of

control over their designs.

The eight global lines in each CLB column can be driven by

either of two types of global buffers. They can also be

driven by internal logic, because they can be accessed by

single, double, and quad lines at the top, bottom, half, and

quarter points. Consequently, the number of different

clocks that can be used simultaneously in an XC4000X

device is very large.

If ﬁne control is desired, use the following summary and

Table 15 on page 35 to choose an appropriate clock buffer.

•

The simplest thing to do is to use a Global Low-Skew

buffer.

•

If a faster clock path is needed, try a BUFG. The

software will ﬁrst try to use a Global Low-Skew Buffer. If

timing requirements are not met, a faster buffer will

automatically be used.

There are four global lines feeding the IOBs at the left edge

of the device. IOBs along the right edge have eight global

lines. There is a single global line along the top and bottom

edges with access to the IOBs. All IOB global lines are bro-

ken at the center. They cannot be connected across the

center of the device, as this connection might introduce

unacceptable skew.

•

If a single quadrant of the chip is sufﬁcient for the

clocked logic, and the timing requires a faster clock than

the Global Low-Skew buffer, use a Global Early buffer.

6

Global Low-Skew Buffers

Each corner of the XC4000X device has two Global

Low-Skew buffers. Any of the eight Global Low-Skew buff-

ers can drive any of the eight vertical Global lines in a col-

umn of CLBs. In addition, any of the buffers can drive any of

the four vertical lines accessing the IOBs on the left edge of

the device, and any of the eight vertical lines accessing the

IOBs on the right edge of the device. (See Figure 36 on

page 38.)

IOB global lines can be driven from two types of global buff-

ers, or from local interconnect. Alternatively, top and bottom

IOBs can be clocked from the global lines in the adjacent

CLB column.

Two different types of clock buffers are available in the

XC4000X:

•

Global Low-Skew Buffers (BUFGLS)

Global Early Buffers (BUFGE)

IOBs at the top and bottom edges of the device are

accessed through the vertical Global lines in the CLB array,

as in the XC4000E. Any Global Low-Skew buffer can,

therefore, access every IOB and CLB in the device.

Global Low-Skew Buffers are the standard clock buffers.

They should be used for most internal clocking, whenever a

large portion of the device must be driven.

The Global Low-Skew buffers can be driven by either

semi-dedicated pads or internal logic.

Global Early Buffers are designed to provide a faster clock

access, but CLB access is limited to one-fourth of the

device. They also facilitate a faster I/O interface.

To use a Global Low-Skew buffer, instantiate a BUFGLS

element in a schematic or in HDL code. If desired, attach a

LOC attribute or property to direct placement to the desig-

nated location. For example, attach a LOC=T attribute or

property to direct that a BUFGLS be placed in one of the

two Global Low-Skew buffers on the top edge of the device,

or a LOC=TR to indicate the Global Low-Skew buffer on the

top edge of the device, on the right.

Figure 35 is a conceptual diagram of the global net struc-

ture in the XC4000X.

Global Early buffers and Global Low-Skew buffers share a

single pad. Therefore, the same IPAD symbol can drive one

buffer of each type, in parallel. This conﬁguration is particu-

larly useful when using the Fast Capture latches, as

described in “IOB Input Signals” on page 20. Paired Global

May 14, 1999 (Version 1.6)

6-37

Product Obsolete or Under Obsolescence

R

XC4000E and XC4000X Series Field Programmable Gate Arrays

8

7

8

7

IOB

1

6

1

6

I

O

B

I

O

B

I

O

B

I

O

B

CLB

I

O

B

I

O

B

I

O

B

I

O

B

CLB

2

5

2

5

IOB

3

4

X6751

3

4

X6753

Figure 37: Left and Right BUFGEs Can Drive Any or

All Clock Inputs in Same Quadrant or Edge (GCK1 is

shown. GCK2, GCK5 and GCK6 are similar.)

Figure 36: Any BUFGLS (GCK1 - GCK8) Can

Drive Any or All Clock Inputs on the Device

Global Early Buffers

The left-side Global Early buffers can each drive two of the

four vertical lines accessing the IOBs on the entire left edge

of the device. The right-side Global Early buffers can each

drive two of the eight vertical lines accessing the IOBs on

the entire right edge of the device. (See Figure 37.)

Each corner of the XC4000X device has two Global Early

buffers. The primary purpose of the Global Early buffers is

to provide an earlier clock access than the potentially

heavily-loaded Global Low-Skew buffers. A clock source

applied to both buffers will result in the Global Early clock

edge occurring several nanoseconds earlier than the Glo-

bal Low-Skew buffer clock edge, due to the lighter loading.

Each left and right Global Early buffer can also drive half of

the IOBs along either the top or bottom edge of the device,

using a dedicated line that can only be accessed through

the Global Early buffers.

Global Early buffers also facilitate the fast capture of device

inputs, using the Fast Capture latches described in “IOB

Input Signals” on page 20. For Fast Capture, take a single

clock signal, and route it through both a Global Early buffer

and a Global Low-Skew buffer. (The two buffers share an

input pad.) Use the Global Early buffer to clock the Fast

Capture latch, and the Global Low-Skew buffer to clock the

normal input ﬂip-ﬂop or latch, as shown in Figure 17 on

page 23.

The top and bottom Global Early buffers can drive half of

the IOBs along either the left or right edge of the device, as

shown in Figure 38. They can only access the top and bot-

tom IOBs via the CLB global lines.

8

7

IOB

1

6

The Global Early buffers can also be used to provide a fast

Clock-to-Out on device output pins. However, an early clock

in the output ﬂip-ﬂop IOB must be taken into consideration

when calculating the internal clock speed for the design.

I

O

B

O

B

CLB

The Global Early buffers at the left and right edges of the

chip have slightly different capabilities than the ones at the

top and bottom. Refer to Figure 37, Figure 38, and

Figure 35 on page 36 while reading the following explana-

tion.

I

O

B

I

O

B

CLB

Each Global Early buffer can access the eight vertical Glo-

bal lines for all CLBs in the quadrant. Therefore, only

one-fourth of the CLB clock pins can be accessed. This

restriction is in large part responsible for the faster speed of

the buffers, relative to the Global Low-Skew buffers.

2

5

IOB

3

4

X6747

Figure 38: Top and Bottom BUFGEs Can Drive Any

or All Clock Inputs in Same Quadrant (GCK8 is

shown. GCK3, GCK4 and GCK7 are similar.)

6-38

May 14, 1999 (Version 1.6)

Product Obsolete or Under Obsolescence

R

XC4000E and XC4000X Series Field Programmable Gate Arrays

The top and bottom Global Early buffers are about 1 ns

slower clock to out than the left and right Global Early buff-

ers.

GND

Ground and

Vcc Ring for

I/O Drivers

The Global Early buffers can be driven by either semi-ded-

icated pads or internal logic. They share pads with the Glo-

bal Low-Skew buffers, so a single net can drive both global

buffers, as described above.

Vcc

To use a Global Early buffer, place a BUFGE element in a

schematic or in HDL code. If desired, attach a LOC

attribute or property to direct placement to the designated

location. For example, attach a LOC=T attribute or property

to direct that a BUFGE be placed in one of the two Global

Early buffers on the top edge of the device, or a LOC=TR to

indicate the Global Early buffer on the top edge of the

device, on the right.

Logic

Power Grid

GND

X5422

Figure 39: XC4000 Series Power Distribution

Power Distribution

Power for the FPGA is distributed through a grid to achieve

high noise immunity and isolation between logic and I/O.

Inside the FPGA, a dedicated Vcc and Ground ring sur-

rounding the logic array provides power to the I/O drivers,

as shown in Figure 39. An independent matrix of Vcc and

Ground lines supplies the interior logic of the device.

Pin Descriptions

There are three types of pins in the XC4000 Series

devices:

•

Permanently dedicated pins

User I/O pins that can have special functions

Unrestricted user-programmable I/O pins.

6

This power distribution grid provides a stable supply and

ground for all internal logic, providing the external package

power pins are all connected and appropriately de-coupled.

Typically, a 0.1 µF capacitor connected between each Vcc

pin and the board’s Ground plane will provide adequate

de-coupling.

Before and during conﬁguration, all outputs not used for the

conﬁguration process are 3-stated with a 50 kΩ - 100 kΩ

pull-up resistor.

After conﬁguration, if an IOB is unused it is conﬁgured as

an input with a 50 kΩ - 100 kΩ pull-up resistor.

Output buffers capable of driving/sinking the speciﬁed 12

mA loads under speciﬁed worst-case conditions may be

capable of driving/sinking up to 10 times as much current

under best case conditions.

XC4000 Series devices have no dedicated Reset input.

Any user I/O can be conﬁgured to drive the Global

Set/Reset net, GSR. See “Global Set/Reset” on page 11

for more information on GSR.

Noise can be reduced by minimizing external load capaci-

tance and reducing simultaneous output transitions in the

same direction. It may also be beneﬁcial to locate heavily

loaded output buffers near the Ground pads. The I/O Block

output buffers have a slew-rate limited mode (default) which

should be used where output rise and fall times are not

speed-critical.

XC4000 Series devices have no Powerdown control input,

as the XC3000 and XC2000 families do. The

XC3000/XC2000 Powerdown control also 3-stated all of the

device

I/O pins. For XC4000 Series devices, use the global 3-state

net, GTS, instead. This net 3-states all outputs, but does

not place the device in low-power mode. See “IOB Output

Signals” on page 23 for more information on GTS.

Device pins for XC4000 Series devices are described in

Table 16. Pin functions during conﬁguration for each of the

seven conﬁguration modes are summarized in Table 22 on

page 58, in the “Conﬁguration Timing” section.

May 14, 1999 (Version 1.6)

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Table 16: Pin Descriptions

I/O

During

After

Pin Name

Conﬁg. Conﬁg.

Pin Description

Permanently Dedicated Pins

Eight or more (depending on package) connections to the nominal +5 V supply voltage

(+3.3 V for low-voltage devices). All must be connected, and each must be decoupled

with a 0.01 - 0.1 µF capacitor to Ground.

VCC

GND

I

Eight or more (depending on package type) connections to Ground. All must be con-

nected.

During configuration, Configuration Clock (CCLK) is an output in Master modes or Asyn-

chronous Peripheral mode, but is an input in Slave mode and Synchronous Peripheral

mode. After configuration, CCLK has a weak pull-up resistor and can be selected as the

Readback Clock. There is no CCLK High or Low time restriction on XC4000 Series de-

vices, except during Readback. See “Violating the Maximum High and Low Time Spec-

ification for the Readback Clock” on page 56 for an explanation of this exception.

CCLK

DONE

I or O

I

O

I

DONE is a bidirectional signal with an optional internal pull-up resistor. As an output, it

indicates the completion of the configuration process. As an input, a Low level on DONE

can be configured to delay the global logic initialization and the enabling of outputs.

The optional pull-up resistor is selected as an option in the XACTstep program that cre-

ates the configuration bitstream. The resistor is included by default.

I/O

PROGRAM is an active Low input that forces the FPGA to clear its configuration mem-

ory. It is used to initiate a configuration cycle. When PROGRAM goes High, the FPGA

finishes the current clear cycle and executes another complete clear cycle, before it

goes into a WAIT state and releases INIT.

PROGRAM

I

The PROGRAM pin has a permanent weak pull-up, so it need not be externally pulled

up to Vcc.

User I/O Pins That Can Have Special Functions

During Peripheral mode configuration, this pin indicates when it is appropriate to write

another byte of data into the FPGA. The same status is also available on D7 in Asyn-

chronous Peripheral mode, if a read operation is performed when the device is selected.

After configuration, RDY/BUSY is a user-programmable I/O pin.

RDY/BUSY

O

I/O

RDY/BUSY is pulled High with a high-impedance pull-up prior to INIT going High.

During Master Parallel configuration, each change on the A0-A17 outputs (A0 - A21 for

XC4000X) is preceded by a rising edge on RCLK, a redundant output signal. RCLK is

useful for clocked PROMs. It is rarely used during configuration. After configuration,

RCLK is a user-programmable I/O pin.

RCLK

O

I/O

As Mode inputs, these pins are sampled after INIT goes High to determine the configu-

ration mode to be used. After configuration, M0 and M2 can be used as inputs, and M1

can be used as a 3-state output. These three pins have no associated input or output

registers.

I (M0), During configuration, these pins have weak pull-up resistors. For the most popular con-

O (M1), figuration mode, Slave Serial, the mode pins can thus be left unconnected. The three

I (M2) mode inputs can be individually configured with or without weak pull-up or pull-down re-

sistors. A pull-down resistor value of 4.7 kΩ is recommended.

M0, M1, M2

I

These pins can only be used as inputs or outputs when called out by special schematic

definitions. To use these pins, place the library components MD0, MD1, and MD2 in-

stead of the usual pad symbols. Input or output buffers must still be used.

If boundary scan is used, this pin is the Test Data Output. If boundary scan is not used,

this pin is a 3-state output without a register, after configuration is completed.

TDO

O

This pin can be user output only when called out by special schematic definitions. To

use this pin, place the library component TDO instead of the usual pad symbol. An out-

put buffer must still be used.

6-40

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Table 16: Pin Descriptions (Continued)

I/O

During

After

Pin Name

Conﬁg. Conﬁg.

Pin Description

If boundary scan is used, these pins are Test Data In, Test Clock, and Test Mode Select

inputs respectively. They come directly from the pads, bypassing the IOBs. These pins

can also be used as inputs to the CLB logic after configuration is completed.

If the BSCAN symbol is not placed in the design, all boundary scan functions are inhib-

ited once configuration is completed, and these pins become user-programmable I/O.

The pins can be used automatically or user-constrained. To use them, use "LOC=" or

place the library components TDI, TCK, and TMS instead of the usual pad symbols. In-

put or output buffers must still be used.

I/O

or I

(JTAG)

TDI, TCK,

TMS

I

High During Configuration (HDC) is driven High until the I/O go active. It is available as

a control output indicating that configuration is not yet completed. After configuration,

HDC is a user-programmable I/O pin.

HDC

LDC

O

I/O

Low During Configuration (LDC) is driven Low until the I/O go active. It is available as a

control output indicating that configuration is not yet completed. After configuration,

LDC is a user-programmable I/O pin.

Before and during configuration, INIT is a bidirectional signal. A 1 kΩ - 10 kΩ external

pull-up resistor is recommended.

As an active-Low open-drain output, INIT is held Low during the power stabilization and

internal clearing of the configuration memory. As an active-Low input, it can be used

to hold the FPGA in the internal WAIT state before the start of configuration. Master

mode devices stay in a WAIT state an additional 30 to 300 µs after INIT has gone High.

During configuration, a Low on this output indicates that a configuration data error has

occurred. After the I/O go active, INIT is a user-programmable I/O pin.

INIT

I/O

6

Four Primary Global inputs each drive a dedicated internal global net with short delay

and minimal skew. If not used to drive a global buffer, any of these pins is a user-pro-

grammable I/O.

The PGCK1-PGCK4 pins drive the four Primary Global Buffers. Any input pad symbol

connected directly to the input of a BUFGP symbol is automatically placed on one of

these pins.

PGCK1 -

PGCK4

(XC4000E

only)

Weak

Pull-up

I or I/O

Four Secondary Global inputs each drive a dedicated internal global net with short delay

and minimal skew. These internal global nets can also be driven from internal logic. If

not used to drive a global net, any of these pins is a user-programmable I/O pin.

The SGCK1-SGCK4 pins provide the shortest path to the four Secondary Global Buff-

ers. Any input pad symbol connected directly to the input of a BUFGS symbol is auto-

matically placed on one of these pins.

SGCK1 -

SGCK4

(XC4000E

only)

Weak

Pull-up

Eight inputs can each drive a Global Low-Skew buffer. In addition, each can drive a Glo-

bal Early buffer. Each pair of global buffers can also be driven from internal logic, but

must share an input signal. If not used to drive a global buffer, any of these pins is a

user-programmable I/O.

Any input pad symbol connected directly to the input of a BUFGLS or BUFGE symbol

is automatically placed on one of these pins.

GCK1 -

GCK8

(XC4000X

only)

Weak

Pull-up

FCLK1 -

FCLK4

(XC4000XLA Weak

and

XC4000XV

only)

Four inputs can each drive a Fast Clock (FCLK) buffer which can deliver a clock signal

to any IOB clock input in the octant of the die served by the Fast Clock buffer. Two Fast

Clock buffers serve the two IOB octants on the left side of the die and the other two Fast

Clock buffers serve the two IOB octants on the right side of the die. On each side of the

die, one Fast Clock buffer serves the upper octant and the other serves the lower octant.

If not used to drive a Fast Clock buffer, any of these pins is a user-programmable I/O.

Pull-up

May 14, 1999 (Version 1.6)

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Table 16: Pin Descriptions (Continued)

I/O

During

After

Pin Name

Conﬁg. Conﬁg.

Pin Description

These four inputs are used in Asynchronous Peripheral mode. The chip is selected

when CS0 is Low and CS1 is High. While the chip is selected, a Low on Write Strobe

(WS) loads the data present on the D0 - D7 inputs into the internal data buffer. A Low

on Read Strobe (RS) changes D7 into a status output — High if Ready, Low if Busy —

and drives D0 - D6 High.

CS0, CS1,

WS, RS

I

I/O

In Express mode, CS1 is used as a serial-enable signal for daisy-chaining.

WS and RS should be mutually exclusive, but if both are Low simultaneously, the Write

Strobe overrides. After configuration, these are user-programmable I/O pins.

During Master Parallel configuration, these 18 output pins address the configuration

EPROM. After configuration, they are user-programmable I/O pins.

A0 - A17

O

I

I/O

A18 - A21

(XC4003XL to

XC4085XL)

During Master Parallel configuration with an XC4000X master, these 4 output pins add

4 more bits to address the configuration EPROM. After configuration, they are user-pro-

grammable I/O pins. (See Master Parallel Configuration section for additional details.)

During Master Parallel and Peripheral configuration, these eight input pins receive con-

figuration data. After configuration, they are user-programmable I/O pins.

D0 - D7

During Slave Serial or Master Serial configuration, DIN is the serial configuration data

input receiving data on the rising edge of CCLK. During Parallel configuration, DIN is

the D0 input. After configuration, DIN is a user-programmable I/O pin.

DIN

I

During configuration in any mode but Express mode, DOUT is the serial configuration

data output that can drive the DIN of daisy-chained slave FPGAs. DOUT data changes

on the falling edge of CCLK, one-and-a-half CCLK periods after it was received at the

DIN input.

DOUT

O

I/O

In Express modefor XC4000E and XC4000X only, DOUT is the status output that can

drive the CS1 of daisy-chained FPGAs, to enable and disable downstream devices.

After configuration, DOUT is a user-programmable I/O pin.

Unrestricted User-Programmable I/O Pins

These pins can be configured to be input and/or output after configuration is completed.

Before configuration is completed, these pins have an internal high-value pull-up resis-

tor (25 kΩ - 100 kΩ) that defines the logic level as High.

Weak

Pull-up

I/O

of how to enable this circuitry are covered later in this sec-

tion.

Boundary Scan

The ‘bed of nails’ has been the traditional method of testing

electronic assemblies. This approach has become less

appropriate, due to closer pin spacing and more sophisti-

cated assembly methods like surface-mount technology

and multi-layer boards. The IEEE Boundary Scan Standard

1149.1 was developed to facilitate board-level testing of

electronic assemblies. Design and test engineers can

imbed a standard test logic structure in their device to

achieve high fault coverage for I/O and internal logic. This

structure is easily implemented with a four-pin interface on

any boundary scan-compatible IC. IEEE 1149.1-compati-

ble devices may be serial daisy-chained together, con-

nected in parallel, or a combination of the two.

By exercising these input signals, the user can serially load

commands and data into these devices to control the driv-

ing of their outputs and to examine their inputs. This

method is an improvement over bed-of-nails testing. It

avoids the need to over-drive device outputs, and it reduces

the user interface to four pins. An optional ﬁfth pin, a reset

for the control logic, is described in the standard but is not

implemented in Xilinx devices.

The dedicated on-chip logic implementing the IEEE 1149.1

functions includes a 16-state machine, an instruction regis-

ter and a number of data registers. The functional details

can be found in the IEEE 1149.1 speciﬁcation and are also

discussed in the Xilinx application note XAPP 017: “Bound-

ary Scan in XC4000 Devices.”

The XC4000 Series implements IEEE 1149.1-compatible

BYPASS, PRELOAD/SAMPLE and EXTEST boundary

scan instructions. When the boundary scan conﬁguration

option is selected, three normal user I/O pins become ded-

icated inputs for these functions. Another user output pin

becomes the dedicated boundary scan output. The details

Figure 40 on page 43 shows a simpliﬁed block diagram of

the XC4000E Input/Output Block with boundary scan

implemented. XC4000X boundary scan logic is identical.

6-42

May 14, 1999 (Version 1.6)

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Figure 41 on page 44 is a diagram of the XC4000 Series

boundary scan logic. It includes three bits of Data Register

per IOB, the IEEE 1149.1 Test Access Port controller, and

the Instruction Register with decodes.

data register, respectively, and BSCANT.UPD, which is

always the last bit of the data register. These three bound-

ary scan bits are special-purpose Xilinx test signals.

The other standard data register is the single ﬂip-ﬂop

BYPASS register. It synchronizes data being passed

through the FPGA to the next downstream boundary scan

device.

XC4000 Series devices can also be conﬁgured through the

boundary scan logic. See “Readback” on page 55.

Data Registers

The FPGA provides two additional data registers that can

be speciﬁed using the BSCAN macro. The FPGA provides

two user pins (BSCAN.SEL1 and BSCAN.SEL2) which are

the decodes of two user instructions. For these instructions,

The primary data register is the boundary scan register. For

each IOB pin in the FPGA, bonded or not, it includes three

bits for In, Out and 3-State Control. Non-IOB pins have

appropriate partial bit population for In or Out only. PRO-

GRAM, CCLK and DONE are not included in the boundary

scan register. Each EXTEST CAPTURE-DR state captures

all In, Out, and 3-state pins.

two

corresponding

pins

(BSCAN.TDO1

and

BSCAN.TDO2) allow user scan data to be shifted out on

TDO. The data register clock (BSCAN.DRCK) is available

for control of test logic which the user may wish to imple-

ment with CLBs. The NAND of TCK and RUN-TEST-IDLE

is also provided (BSCAN.IDLE).

The data register also includes the following non-pin bits:

TDO.T, and TDO.O, which are always bits 0 and 1 of the

EXTEST

SLEW

RATE

PULL

DOWN

PULL

UP

M

TS INV

TS/OE

3-State TS

V

CC

6

TS - capture

TS - update

Boundary

Scan

OUTPUT

INVERT

OUTPUT

M

sd

D

Q

Ouput Data O

EC

M

INVERT

PAD

M

Ouput Clock OK

rd

OUT

SEL

S/R

M

O - capture

Q - capture

Clock Enable

Boundary

Scan

O - update

M

I - capture

Boundary

Scan

Input Data 1 I1

Input Data 2 I2

I - update

M

sd

Q

D

EC

DELAY

Q

L

M

INVERT

M

FLIP-FLOP/LATCH

Input Clock IK

rd

S/R

INPUT

GLOBAL

S/R

X5792

Figure 40: Block Diagram of XC4000E IOB with Boundary Scan (some details not shown).

XC4000X Boundary Scan Logic is Identical.

May 14, 1999 (Version 1.6)

6-43

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XC4000E and XC4000X Series Field Programmable Gate Arrays

DATA IN

IOB.T

0

1

0

sd

1

D

Q

D

Q

LE

IOB

sd

1

0

D

Q

D

Q

LE

1

0

IOB.I

1

sd

D

Q

D

Q

0

LE

1

0

IOB.Q

IOB.T

BYPASS

REGISTER

0

1

M

U

X

TDO

1

sd

INSTRUCTION REGISTER

TDI

D

Q

D

Q

0

LE

1

sd

D

Q

D

Q

0

LE

1

0

IOB.I

DATAOUT

SHIFT/

CAPTURE

UPDATE

EXTEST

CLOCK DATA

REGISTER

X9016

Figure 41: XC4000 Series Boundary Scan Logic

BSDL (Boundary Scan Description Language) ﬁles for

XC4000 Series devices are available on the Xilinx FTP site.

Instruction Set

The XC4000 Series boundary scan instruction set also

includes instructions to conﬁgure the device and read back

the conﬁguration data. The instruction set is coded as

shown in Table 17.

Including Boundary Scan in a Schematic

If boundary scan is only to be used during conﬁguration, no

special schematic elements need be included in the sche-

matic or HDL code. In this case, the special boundary scan

pins TDI, TMS, TCK and TDO can be used for user func-

tions after conﬁguration.

Bit Sequence

The bit sequence within each IOB is: In, Out, 3-State. The

input-only M0 and M2 mode pins contribute only the In bit

to the boundary scan I/O data register, while the out-

put-only M1 pin contributes all three bits.

To indicate that boundary scan remain enabled after conﬁg-

uration, place the BSCAN library symbol and connect the

TDI, TMS, TCK and TDO pad symbols to the appropriate

pins, as shown in Figure 43.

The ﬁrst two bits in the I/O data register are TDO.T and

TDO.O, which can be used for the capture of internal sig-

nals. The ﬁnal bit is BSCANT.UPD, which can be used to

drive an internal net. These locations are primarily used by

Xilinx for internal testing.

Even if the boundary scan symbol is used in a schematic,

the input pins TMS, TCK, and TDI can still be used as

inputs to be routed to internal logic. Care must be taken not

to force the chip into an undesired boundary scan state by

inadvertently applying boundary scan input patterns to

these pins. The simplest way to prevent this is to keep TMS

High, and then apply whatever signal is desired to TDI and

TCK.

From a cavity-up view of the chip (as shown in XDE or

Epic), starting in the upper right chip corner, the boundary

scan data-register bits are ordered as shown in Figure 42.

The device-speciﬁc pinout tables for the XC4000 Series

include the boundary scan locations for each IOB pin.

6-44

May 14, 1999 (Version 1.6)

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Table 17: Boundary Scan Instructions

Optional

To User

Logic

Instruction I2

I1 I0

Test

Selected

I/O Data

Source

TDO Source

IBUF

BSCAN

0

1

EXTEST

DR

TDO

TDI

TMS

TCK

TDI

TDO

SAMPLE/PR

ELOAD

Pin/Logic

TMS

TCK

DRCK

IDLE

To User

Logic

0

1

0

1

0

USER 1

BSCAN.

TDO1

User Logic

Pin/Logic

TDO1

TDO2

SEL1

SEL2

From

User Logic

USER 2

BSCAN.

TDO2

X2675

Figure 43: Boundary Scan Schematic Example

READBACK Readback

Data

Conﬁguration

1

0

1

0

1

CONFIGURE

Reserved

DOUT

—

Disabled

Conﬁguration is the process of loading design-speciﬁc pro-

gramming data into one or more FPGAs to deﬁne the func-

tional operation of the internal blocks and their

interconnections. This is somewhat like loading the com-

mand registers of a programmable peripheral chip. XC4000

Series devices use several hundred bits of conﬁguration

data per CLB and its associated interconnects. Each con-

ﬁguration bit deﬁnes the state of a static memory cell that

controls either a function look-up table bit, a multiplexer

input, or an interconnect pass transistor. The XACTstep

development system translates the design into a netlist ﬁle.

It automatically partitions, places and routes the logic and

generates the conﬁguration data in PROM format.

—

BYPASS

Bypass

Register

TDO.T

TDO.O

Bit 0 ( TDO end)

Bit 1

Bit 2

Top-edge IOBs (Right to Left)

Left-edge IOBs (Top to Bottom)

6

MD1.T

MD1.O

MD1.I

MD0.I

MD2.I

Special Purpose Pins

Bottom-edge IOBs (Left to Right)

Three conﬁguration mode pins (M2, M1, M0) are sampled

prior to conﬁguration to determine the conﬁguration mode.

After conﬁguration, these pins can be used as auxiliary

connections. M2 and M0 can be used as inputs, and M1

can be used as an output. The XACTstep development sys-

tem does not use these resources unless they are explicitly

speciﬁed in the design entry. This is done by placing a spe-

cial pad symbol called MD2, MD1, or MD0 instead of the

input or output pad symbol.

Right-edge IOBs (Bottom to Top)

B SCANT.UPD

(TDI end)

X6075

Figure 42: Boundary Scan Bit Sequence

Avoiding Inadvertent Boundary Scan

If TMS or TCK is used as user I/O, care must be taken to

ensure that at least one of these pins is held constant dur-

ing conﬁguration. In some applications, a situation may

occur where TMS or TCK is driven during conﬁguration.

This may cause the device to go into boundary scan mode

and disrupt the conﬁguration process.

In XC4000 Series devices, the mode pins have weak

pull-up resistors during conﬁguration. With all three mode

pins High, Slave Serial mode is selected, which is the most

popular conﬁguration mode. Therefore, for the most com-

mon conﬁguration mode, the mode pins can be left uncon-

nected. (Note, however, that the internal pull-up resistor

value can be as high as 100 kΩ.) After conﬁguration, these

pins can individually have weak pull-up or pull-down resis-

tors, as speciﬁed in the design. A pull-down resistor value

of 4.7 kΩ is recommended.

To prevent activation of boundary scan during conﬁgura-

tion, do either of the following:

•

TMS: Tie High to put the Test Access Port controller

in a benign RESET state

•

TCK: Tie High or Low—don't toggle this clock input.

These pins are located in the lower left chip corner and are

near the readback nets. This location allows convenient

routing if compatibility with the XC2000 and XC3000 family

conventions of M0/RT, M1/RD is desired.

For more information regarding boundary scan, refer to the

Xilinx Application Note XAPP 017.001, “Boundary Scan in

XC4000E Devices.“

May 14, 1999 (Version 1.6)

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Additional Address lines in XC4000 devices

Conﬁguration Modes

The XC4000X devices have additional address lines

(A18-A21) allowing the additional address space required

to daisy-chain several large devices.

XC4000E devices have six conﬁguration modes. XC4000X

devices have the same six modes, plus an additional con-

ﬁguration mode. These modes are selected by a 3-bit input

code applied to the M2, M1, and M0 inputs. There are three

self-loading Master modes, two Peripheral modes, and a

Serial Slave mode, which is used primarily for

daisy-chained devices. The coding for mode selection is

shown in Table 18.

The extra address lines are programmable in XC4000EX

devices. By default these address lines are not activated. In

the default mode, the devices are compatible with existing

XC4000 and XC4000E products. If desired, the extra

address lines can be used by specifying the address lines

option in bitgen as 22 (bitgen -g AddressLines:22). The

lines (A18-A21) are driven when a master device detects,

via the bitstream, that it should be using all 22 address

lines. Because these pins will initially be pulled high by

internal pull-ups, designers using Master Parallel Up mode

should use external pull down resistors on pins A18-A21. If

Master Parallel Down mode is used external resistors are

not necessary.

Table 18: Conﬁguration Modes

Mode

M2 M1 M0 CCLK

Data

Master Serial

Slave Serial

0

1

0

1

0

1

0

output

input

Bit-Serial

Master

Parallel Up

output

Byte-Wide,

increment

from 00000

Master

Parallel Down

1

0

output

Byte-Wide,

decrement

from 3FFFF

All 22 address lines are always active in Master Parallel

modes with XC4000XL devices. The additional address

lines behave identically to the lower order address lines. If

the Address Lines option in bitgen is set to 18, it will be

ignored by the XC4000XL device.

Peripheral

Synchronous*

0

1

0

1

input

Byte-Wide

Peripheral

Asynchronous

output

Byte-Wide

The additional address lines (A18-A21) are not available in

the PC84 package.

Reserved

0

1

0

1

—

Peripheral Modes

The two Peripheral modes accept byte-wide data from a

bus. A RDY/BUSY status is available as a handshake sig-

nal. In Asynchronous Peripheral mode, the internal oscilla-

tor generates a CCLK burst signal that serializes the

byte-wide data. CCLK can also drive slave devices. In the

synchronous mode, an externally supplied clock input to

CCLK serializes the data.

* Can be considered byte-wide Slave Parallel

A detailed description of each conﬁguration mode, with tim-

ing information, is included later in this data sheet. During

conﬁguration, some of the I/O pins are used temporarily for

the conﬁguration process. All pins used during conﬁgura-

tion are shown in Table 22 on page 58.

Master Modes

Slave Serial Mode

The three Master modes use an internal oscillator to gener-

ate a Conﬁguration Clock (CCLK) for driving potential slave

devices. They also generate address and timing for exter-

nal PROM(s) containing the conﬁguration data.

In Slave Serial mode, the FPGA receives serial conﬁgura-

tion data on the rising edge of CCLK and, after loading its

conﬁguration, passes additional data out, resynchronized

on the next falling edge of CCLK.

Master Parallel (Up or Down) modes generate the CCLK

signal and PROM addresses and receive byte parallel data.

The data is internally serialized into the FPGA data-frame

format. The up and down selection generates starting

addresses at either zero or 3FFFF (3FFFFF when 22

address lines are used), for compatibility with different

microprocessor addressing conventions. The Master Serial

mode generates CCLK and receives the conﬁguration data

in serial form from a Xilinx serial-conﬁguration PROM.

Multiple slave devices with identical conﬁgurations can be

wired with parallel DIN inputs. In this way, multiple devices

can be conﬁgured simultaneously.

Serial Daisy Chain

Multiple devices with different conﬁgurations can be con-

nected together in a “daisy chain,” and a single combined

bitstream used to conﬁgure the chain of slave devices.

To conﬁgure a daisy chain of devices, wire the CCLK pins

of all devices in parallel, as shown in Figure 51 on page

60. Connect the DOUT of each device to the DIN of the

next. The lead or master FPGA and following slaves each

passes resynchronized conﬁguration data coming from a

single source. The header data, including the length count,

CCLK speed is selectable as either 1 MHz (default) or 8

MHz. Conﬁguration always starts at the default slow fre-

quency, then can switch to the higher frequency during the

ﬁrst frame. Frequency tolerance is -50% to +25%.

6-46

May 14, 1999 (Version 1.6)

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XC4000E and XC4000X Series Field Programmable Gate Arrays

is passed through and is captured by each FPGA when it

recognizes the 0010 preamble. Following the length-count

data, each FPGA outputs a High on DOUT until it has

received its required number of data frames.

tiated and most boundary scan instructions cannot be

used.

The user has some control over the relative timing of these

events and can, therefore, make sure that they occur at the

proper time and the ﬁnish point F is reached. Timing is con-

trolled using options in the bitstream generation software.

After an FPGA has received its conﬁguration data, it

passes on any additional frame start bits and conﬁguration

data on DOUT. When the total number of conﬁguration

clocks applied after memory initialization equals the value

of the 24-bit length count, the FPGAs begin the start-up

sequence and become operational together. FPGA I/O are

normally released two CCLK cycles after the last conﬁgura-

tion bit is received. Figure 47 on page 53 shows the

start-up timing for an XC4000 Series device.

XC3000 Master with an XC4000 Series Slave

Some designers want to use an inexpensive lead device in

peripheral mode and have the more precious I/O pins of the

XC4000 Series devices all available for user I/O. Figure 44

provides a solution for that case.

This solution requires one CLB, one IOB and pin, and an

internal oscillator with a frequency of up to 5 MHz as a

clock source. The XC3000 master device must be conﬁg-

ured with late Internal Reset, which is the default option.

The daisy-chained bitstream is not simply a concatenation

of the individual bitstreams. The PROM ﬁle formatter must

be used to combine the bitstreams for a daisy-chained con-

ﬁguration.

One CLB and one IOB in the lead XC3000-family device

are used to generate the additional CCLK pulse required by

the XC4000 Series devices. When the lead device removes

the internal RESET signal, the 2-bit shift register responds

to its clock input and generates an active Low output signal

for the duration of the subsequent clock period. An external

connection between this output and CCLK thus creates the

extra CCLK pulse.

Multi-Family Daisy Chain

All Xilinx FPGAs of the XC2000, XC3000, and XC4000

Series use a compatible bitstream format and can, there-

fore, be connected in a daisy chain in an arbitrary

sequence. There is, however, one limitation. The lead

device must belong to the highest family in the chain. If the

chain contains XC4000 Series devices, the master nor-

mally cannot be an XC2000 or XC3000 device.

6

The reason for this rule is shown in Figure 47 on page 53.

Since all devices in the chain store the same length count

value and generate or receive one common sequence of

CCLK pulses, they all recognize length-count match on the

same CCLK edge, as indicated on the left edge of

Figure 47. The master device then generates additional

CCLK pulses until it reaches its ﬁnish point F. The different

families generate or require different numbers of additional

CCLK pulses until they reach F. Not reaching F means that

the device does not really ﬁnish its conﬁguration, although

DONE may have gone High, the outputs became active,

and the internal reset was released. For the XC4000 Series

device, not reaching F means that readback cannot be ini-

OE/T

Output

Connected

to CCLK

Reset

0

1

0

1

Active Low Output

Active High Output

etc

.

X5223

Figure 44: CCLK Generation for XC3000 Master

Driving an XC4000 Series Slave

May 14, 1999 (Version 1.6)

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Setting CCLK Frequency

Data Stream Format

For Master modes, CCLK can be generated in either of two

frequencies. In the default slow mode, the frequency

ranges from 0.5 MHz to 1.25 MHz for XC4000E and

XC4000EX devices and from 0.6 MHz to 1.8 MHz for

XC4000XL devices. In fast CCLK mode, the frequency

ranges from 4 MHz to 10 MHz for XC4000E/EX devices and

from 5 MHz to 15 MHz for XC4000XL devices. The fre-

quency is selected by an option when running the bitstream

generation software. If an XC4000 Series Master is driving

an XC3000- or XC2000-family slave, slow CCLK mode

must be used. In addition, an XC4000XL device driving a

XC4000E or XC4000EX should use slow mode. Slow mode

is the default.

The data stream (“bitstream”) format is identical for all con-

ﬁguration modes.

The data stream formats are shown in Table 19. Bit-serial

data is read from left to right, and byte-parallel data is effec-

tively assembled from this serial bitstream, with the ﬁrst bit

in each byte assigned to D0.

The conﬁguration data stream begins with a string of eight

ones, a preamble code, followed by a 24-bit length count

and a separator ﬁeld of ones. This header is followed by the

actual conﬁguration data in frames. The length and number

of frames depends on the device type (see Table 20 and

Table 21). Each frame begins with a start ﬁeld and ends

with an error check. A postamble code is required to signal

the end of data for a single device. In all cases, additional

start-up bytes of data are required to provide four clocks for

the startup sequence at the end of conﬁguration. Long

daisy chains require additional startup bytes to shift the last

data through the chain. All startup bytes are don’t-cares;

these bytes are not included in bitstreams created by the

Xilinx software.

Table 19: XC4000 Series Data Stream Formats

All Other

Data Type

Modes (D0...)

Fill Byte

11111111b

0010b

Preamble Code

Length Count

Fill Bits

COUNT(23:0)

1111b

A selection of CRC or non-CRC error checking is allowed

by the bitstream generation software. The non-CRC error

checking tests for a designated end-of-frame ﬁeld for each

frame. For CRC error checking, the software calculates a

running CRC and inserts a unique four-bit partial check at

the end of each frame. The 11-bit CRC check of the last

frame of an FPGA includes the last seven data bits.

Start Field

Data Frame

0b

DATA(n-1:0)

CRC or Constant

Field Check

xxxx (CRC)

or 0110b

Extend Write Cycle

Postamble

Start-Up Bytes

Legend:

—

01111111b

xxh

Detection of an error results in the suspension of data load-

ing and the pulling down of the INIT pin. In Master modes,

CCLK and address signals continue to operate externally.

The user must detect INIT and initialize a new conﬁguration

by pulsing the PROGRAM pin Low or cycling Vcc.

Not shaded

Light

Once per bitstream

Once per data frame

Once per device

Dark

6-48

May 14, 1999 (Version 1.6)

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Table 20: XC4000E Program Data

Device

XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E

Max Logic Gates

3,000

5,000

6,000

8,000

10,000

13,000

20,000

25,000

CLBs

100

196

256

324

400

576

784

1,024

(Row x Col.)

(10 x 10)

(14 x 14)

(16 x 16)

(18 x 18)

(20 x 20)

(24 x 24)

(28 x 28)

(32 x 32)

IOBs

80

360

112

616

128

768

144

936

160

1,120

226

192

1,536

266

224

2,016

256

2,560

Flip-Flops

Bits per Frame

Frames

126

166

186

206

306

346

428

572

644

716

788

932

1,076

1,220

Program Data

53,936

53,984

94,960

95,008

119,792

119,840

147,504

147,552

178,096

178,144

247,920

247,968

329,264

329,312

422,128

422,176

PROM Size

(bits)

Notes: 1. Bits per Frame = (10 x number of rows) + 7 for the top + 13 for the bottom + 1 + 1 start bit + 4 error check bits

Number of Frames = (36 x number of columns) + 26 for the left edge + 41 for the right edge + 1

Program Data = (Bits per Frame x Number of Frames) + 8 postamble bits

PROM Size = Program Data + 40 (header) + 8

2. The user can add more “one” bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end of

any frame, following the four error check bits. However, the Length Count value must be adjusted for all such extra “one”

bits, even for extra leading ones at the beginning of the header.

Table 21: XC4000EX/XL Program Data

Device

XC4002XL XC4005 XC4010 XC4013 XC4020 XC4028 XC4036 XC4044

XC4052

XC4062

XC4085

6

Max Logic

Gates

2,000

5,000

10,000

13,000

20,000

28,000

36,000

44,000

52,000

62,000

85,000

CLBs

64

196

400

576

784

1,024

1,296

1,600

1,936

2,304

3,136

(Row x

Column)

(8 x 8)

(14 x 14) (20 x 20) (24 x 24) (28 x 28) (32 x 32) (36 x 36) (40 x 40) (44 x 44) (48 x 48) (56 x 56)

IOBs

64

112

616

205

160

1,120

277

192

1,536

325

224

2,016

373

256

2,560

421

288

3,168

469

320

3,840

517

352

4,576

565

384

5,376

613

448

7,168

709

Flip-Flops

256

133

Bits per

Frame

Frames

459

741

1,023

1,211

1,399

1,587

1,775

1,963

2,151

2,339

2,715

Program Data

61,052

61,104

151,910 283,376 393,580 521,832 668,124 832,480 1,014,876 1,215,320 1,433,804 1,924,940

151,960 283,424 393,632 521,880 668,172 832,528 1,014,924 1,215,368 1,433,852 1,924,992

PROM Size

(bits)

Notes: 1. Bits per frame = (13 x number of rows) + 9 for the top + 17 for the bottom + 8 + 1 start bit + 4 error check bits.

Frames = (47 x number of columns) + 27 for the left edge + 52 for the right edge + 4.

Program data = (bits per frame x number of frames) + 5 postamble bits.

PROM size = (program data + 40 header bits + 8 start bits) rounded up to the nearest byte.

2. The user can add more “one” bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end

of any frame, following the four error check bits. However, the Length Count value must be adjusted for all such extra “one”

bits, even for extra leading “ones” at the beginning of the header.

ﬁguration process with a potentially corrupted bitstream is

terminated. The FPGA pulls the INIT pin Low and goes into

a Wait state.

Cyclic Redundancy Check (CRC) for

Conﬁguration and Readback

The Cyclic Redundancy Check is a method of error detec-

During Readback, 11 bits of the 16-bit checksum are added

tion in data transmission applications. Generally, the trans-

to the end of the Readback data stream. The checksum is

mitting system performs a calculation on the serial

computed using the CRC-16 CCITT polynomial, as shown

bitstream. The result of this calculation is tagged onto the

in Figure 45. The checksum consists of the 11 most signif-

data stream as additional check bits. The receiving system

icant bits of the 16-bit code. A change in the checksum indi-

performs an identical calculation on the bitstream and com-

cates a change in the Readback bitstream. A comparison

pares the result with the received checksum.

to a previous checksum is meaningful only if the readback

Each data frame of the conﬁguration bitstream has four

error bits at the end, as shown in Table 19. If a frame data

error is detected during the loading of the FPGA, the con-

data is independent of the current device state. CLB out-

puts should not be included (Read Capture option not

May 14, 1999 (Version 1.6)

6-49

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XC4000E and XC4000X Series Field Programmable Gate Arrays

used), and if RAM is present, the RAM content must be

unchanged.

V

No

Statistically, one error out of 2048 might go undetected.

CC

>3.5 V

Boundary Scan

Instructions

Available:

Conﬁguration Sequence

Yes

There are four major steps in the XC4000 Series power-up

conﬁguration sequence.

Test M0 Generate

One Time-Out Pulse

of 16 or 64 ms

PROGRAM

= Low

•

Conﬁguration Memory Clear

Initialization

Conﬁguration

Yes

Keep Clearing

Configuration Memory

Start-Up

The full process is illustrated in Figure 46.

EXTEST*

SAMPLE/PRELOAD

BYPASS

Completely Clear

Configuration Memory

Once More

Conﬁguration Memory Clear

~1.3 µs per Frame

CONFIGURE*

(* if PROGRAM = High)

When power is ﬁrst applied or is reapplied to an FPGA, an

internal circuit forces initialization of the conﬁguration logic.

When Vcc reaches an operational level, and the circuit

passes the write and read test of a sample pair of conﬁgu-

ration bits, a time delay is started. This time delay is nomi-

nally 16 ms, and up to 10% longer in the low-voltage

devices. The delay is four times as long when in Master

Modes (M0 Low), to allow ample time for all slaves to reach

a stable Vcc. When all INIT pins are tied together, as rec-

ommended, the longest delay takes precedence. There-

fore, devices with different time delays can easily be mixed

and matched in a daisy chain.

INIT

High? if

Master

No

Master Waits 50 to 250 µs

Before Sampling Mode Lines

Yes

Sample

Mode Lines

Master CCLK

Goes Active

Load One

Configuration

Data Frame

This delay is applied only on power-up. It is not applied

when re-conﬁguring an FPGA by pulsing the PROGRAM

Yes

Frame

Error

Pull INIT Low

and Stop

X2

X15

No

X16

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14

15

SAMPLE/PRELOAD

Config-

uration

memory

Full

No

BYPASS

SERIAL DATA IN

Yes

Polynomial: X16 + X15 + X2 + 1

Pass

Configuration

Data to DOUT

1

0

15 14 13 12 11 10

9

8

7

6

5

LAST DATA FRAME

CRC – CHECKSUM

CCLK

Count Equals

Length

No

X1789

Readback Data Stream

Count

Yes

Figure 45: Circuit for Generating CRC-16

Start-Up

Sequence

F

Operational

EXTEST

SAMPLE PRELOAD

BYPASS

If Boundary Scan

is Selected

USER 1

USER 2

CONFIGURE

READBACK

X6076

Figure 46: Power-up Conﬁguration Sequence

6-50

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Low. During this time delay, or as long as the PROGRAM

input is asserted, the conﬁguration logic is held in a Conﬁg-

uration Memory Clear state. The conﬁguration-memory

frames are consecutively initialized, using the internal oscil-

lator.

rise time is excessive or poorly deﬁned. As long as PRO-

GRAM is Low, the FPGA keeps clearing its conﬁguration

memory. When PROGRAM goes High, the conﬁguration

memory is cleared one more time, followed by the begin-

ning of conﬁguration, provided the INIT input is not exter-

nally held Low. Note that a Low on the PROGRAM input

automatically forces a Low on the INIT output. The XC4000

Series PROGRAM pin has a permanent weak pull-up.

At the end of each complete pass through the frame

addressing, the power-on time-out delay circuitry and the

level of the PROGRAM pin are tested. If neither is asserted,

the logic initiates one additional clearing of the conﬁgura-

tion frames and then tests the INIT input.

Using an open-collector or open-drain driver to hold INIT

Low before the beginning of conﬁguration causes the

FPGA to wait after completing the conﬁguration memory

clear operation. When INIT is no longer held Low exter-

nally, the device determines its conﬁguration mode by cap-

turing its mode pins, and is ready to start the conﬁguration

process. A master device waits up to an additional 250 µs

to make sure that any slaves in the optional daisy chain

have seen that INIT is High.

Initialization

During initialization and conﬁguration, user pins HDC, LDC,

INIT and DONE provide status outputs for the system inter-

face. The outputs LDC, INIT and DONE are held Low and

HDC is held High starting at the initial application of power.

The open drain INIT pin is released after the ﬁnal initializa-

tion pass through the frame addresses. There is a deliber-

ate delay of 50 to 250 µs (up to 10% longer for low-voltage

devices) before a Master-mode device recognizes an inac-

tive INIT. Two internal clocks after the INIT pin is recognized

as High, the FPGA samples the three mode lines to deter-

mine the conﬁguration mode. The appropriate interface

lines become active and the conﬁguration preamble and

data can be loaded.Conﬁguration

Start-Up

Start-up is the transition from the conﬁguration process to

the intended user operation. This transition involves a

change from one clock source to another, and a change

from interfacing parallel or serial conﬁguration data where

most outputs are 3-stated, to normal operation with I/O pins

active in the user-system. Start-up must make sure that the

user-logic ‘wakes up’ gracefully, that the outputs become

active without causing contention with the conﬁguration sig-

nals, and that the internal ﬂip-ﬂops are released from the

global Reset or Set at the right time.

6

The 0010 preamble code indicates that the following 24 bits

represent the length count. The length count is the total

number of conﬁguration clocks needed to load the com-

plete conﬁguration data. (Four additional conﬁguration

clocks are required to complete the conﬁguration process,

as discussed below.) After the preamble and the length

count have been passed through to all devices in the daisy

chain, DOUT is held High to prevent frame start bits from

reaching any daisy-chained devices.

Figure 47 describes start-up timing for the three Xilinx fam-

ilies in detail. The conﬁguration modes can use any of the

four timing sequences.

To access the internal start-up signals, place the STARTUP

library symbol.

A speciﬁc conﬁguration bit, early in the ﬁrst frame of a mas-

ter device, controls the conﬁguration-clock rate and can

increase it by a factor of eight. Therefore, if a fast conﬁgu-

ration clock is selected by the bitstream, the slower clock

rate is used until this conﬁguration bit is detected.

Start-up Timing

Different FPGA families have different start-up sequences.

The XC2000 family goes through a ﬁxed sequence. DONE

goes High and the internal global Reset is de-activated one

CCLK period after the I/O become active.

Each frame has a start ﬁeld followed by the frame-conﬁgu-

ration data bits and a frame error ﬁeld. If a frame data error

is detected, the FPGA halts loading, and signals the error

by pulling the open-drain INIT pin Low. After all conﬁgura-

tion frames have been loaded into an FPGA, DOUT again

follows the input data so that the remaining data is passed

on to the next device.

The XC3000A family offers some ﬂexibility. DONE can be

programmed to go High one CCLK period before or after

the I/O become active. Independent of DONE, the internal

global Reset is de-activated one CCLK period before or

after the I/O become active.

The XC4000 Series offers additional ﬂexibility. The three

events — DONE going High, the internal Set/Reset being

de-activated, and the user I/O going active — can all occur

in any arbitrary sequence. Each of them can occur one

CCLK period before or after, or simultaneous with, any of

the others. This relative timing is selected by means of soft-

ware options in the bitstream generation software.

Delaying Conﬁguration After Power-Up

There are two methods of delaying conﬁguration after

power-up: put a logic Low on the PROGRAM input, or pull

the bidirectional INIT pin Low, using an open-collector

(open-drain) driver. (See Figure 46 on page 50.)

A Low on the PROGRAM input is the more radical

approach, and is recommended when the power-supply

May 14, 1999 (Version 1.6)

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XC4000E and XC4000X Series Field Programmable Gate Arrays

The default option, and the most practical one, is for DONE

to go High ﬁrst, disconnecting the conﬁguration data source

and avoiding any contention when the I/Os become active

one clock later. Reset/Set is then released another clock

period later to make sure that user-operation starts from

stable internal conditions. This is the most common

sequence, shown with heavy lines in Figure 47, but the

designer can modify it to meet particular requirements.

received since INIT went High equals the loaded value of

the length count.

The next rising clock edge sets a ﬂip-ﬂop Q0, shown in

Figure 48. Q0 is the leading bit of a 5-bit shift register. The

outputs of this register can be programmed to control three

events.

•

The release of the open-drain DONE output

The change of conﬁguration-related pins to the user

function, activating all IOBs.

Normally, the start-up sequence is controlled by the internal

device oscillator output (CCLK), which is asynchronous to

the system clock.

•

The termination of the global Set/Reset initialization of

all CLB and IOB storage elements.

XC4000 Series offers another start-up clocking option,

UCLK_NOSYNC. The three events described above need

not be triggered by CCLK. They can, as a conﬁguration

option, be triggered by a user clock. This means that the

device can wake up in synchronism with the user system.

The DONE pin can also be wire-ANDed with DONE pins of

other FPGAs or with other external signals, and can then

be used as input to bit Q3 of the start-up register. This is

called “Start-up Timing Synchronous to Done In” and is

selected by either CCLK_SYNC or UCLK_SYNC.

When the UCLK_SYNC option is enabled, the user can

externally hold the open-drain DONE output Low, and thus

stall all further progress in the start-up sequence until

DONE is released and has gone High. This option can be

used to force synchronization of several FPGAs to a com-

mon user clock, or to guarantee that all devices are suc-

cessfully conﬁgured before any I/Os go active.

When DONE is not used as an input, the operation is called

“Start-up Timing Not Synchronous to DONE In,” and is

selected by either CCLK_NOSYNC or UCLK_NOSYNC.

As a conﬁguration option, the start-up control register

beyond Q0 can be clocked either by subsequent CCLK

pulses or from an on-chip user net called STARTUP.CLK.

These signals can be accessed by placing the STARTUP

library symbol.

If either of these two options is selected, and no user clock

is speciﬁed in the design or attached to the device, the chip

could reach a point where the conﬁguration of the device is

complete and the Done pin is asserted, but the outputs do

not become active. The solution is either to recreate the bit-

stream specifying the start-up clock as CCLK, or to supply

the appropriate user clock.

Start-up from CCLK

If CCLK is used to drive the start-up, Q0 through Q3 pro-

vide the timing. Heavy lines in Figure 47 show the default

timing, which is compatible with XC2000 and XC3000

devices using early DONE and late Reset. The thin lines

indicate all other possible timing options.

Start-up Sequence

The Start-up sequence begins when the conﬁguration

memory is full, and the total number of conﬁguration clocks

6-52

May 14, 1999 (Version 1.6)

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R

XC4000E and XC4000X Series Field Programmable Gate Arrays

Length Count Match

CCLK Period

CCLK

F

DONE

I/O

XC2000

XC3000

Global Reset

F = Finished, no more

configuration clocks needed

Daisy-chain lead device

must have latest F

F

DONE

I/O

Heavy lines describe

default timing

Global Reset

F

DONE

I/O

C1

C2

C3

C4

XC4000E/X

CCLK_NOSYNC

C4

6

GSR Active

C2

C3

C4

DONE IN

F

DONE

I/O

C1, C2 or C3

Di

XC4000E/X

CCLK_SYNC

Di+1

GSR Active

Di

F

DONE

I/O

C1

U2

U3

U4

XC4000E/X

UCLK_NOSYNC

U4

GSR Active

U2

U3

U4

DONE IN

F

DONE

I/O

C1

U2

XC4000E/X

UCLK_SYNC

Di

Di+1

Di+2

GSR Active

Di Di+1

Synchronization

Uncertainty

UCLK Period

X9024

Figure 47: Start-up Timing

May 14, 1999 (Version 1.6)

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Start-up from a User Clock (STARTUP.CLK)

Release of User I/O After DONE Goes High

When, instead of CCLK, a user-supplied start-up clock is

selected, Q1 is used to bridge the unknown phase relation-

ship between CCLK and the user clock. This arbitration

causes an unavoidable one-cycle uncertainty in the timing

of the rest of the start-up sequence.

By default, the user I/O are released one CCLK cycle after

the DONE pin goes High. If CCLK is not clocked after

DONE goes High, the outputs remain in their initial state —

3-stated, with a 50 kΩ - 100 kΩ pull-up. The delay from

DONE High to active user I/O is controlled by an option to

the bitstream generation software.

DONE Goes High to Signal End of Conﬁguration

Release of Global Set/Reset After DONE Goes

High

XC4000 Series devices read the expected length count

from the bitstream and store it in an internal register. The

length count varies according to the number of devices and

the composition of the daisy chain. Each device also counts

the number of CCLKs during conﬁguration.

By default, Global Set/Reset (GSR) is released two CCLK

cycles after the DONE pin goes High. If CCLK is not

clocked twice after DONE goes High, all ﬂip-ﬂops are held

in their initial set or reset state. The delay from DONE High

to GSR inactive is controlled by an option to the bitstream

generation software.

Two conditions have to be met in order for the DONE pin to

go high:

•

the chip's internal memory must be full, and

the conﬁguration length count must be met, exactly.

Conﬁguration Complete After DONE Goes High

This is important because the counter that determines

when the length count is met begins with the very ﬁrst

CCLK, not the ﬁrst one after the preamble.

Three full CCLK cycles are required after the DONE pin

goes High, as shown in Figure 47 on page 53. If CCLK is

not clocked three times after DONE goes High, readback

cannot be initiated and most boundary scan instructions

cannot be used.

Therefore, if a stray bit is inserted before the preamble, or

the data source is not ready at the time of the ﬁrst CCLK,

the internal counter that holds the number of CCLKs will be

one ahead of the actual number of data bits read. At the

end of conﬁguration, the conﬁguration memory will be full,

but the number of bits in the internal counter will not match

the expected length count.

Conﬁguration Through the Boundary Scan

Pins

XC4000 Series devices can be conﬁgured through the

boundary scan pins. The basic procedure is as follows:

As a consequence, a Master mode device will continue to

send out CCLKs until the internal counter turns over to

zero, and then reaches the correct length count a second

time. This will take several seconds [2²⁴CCLK period] —

which is sometimes interpreted as the device not conﬁgur-

ing at all.

•

Power up the FPGA with INIT held Low (or drive the

PROGRAM pin Low for more than 300 ns followed by a

High while holding INIT Low). Holding INIT Low allows

enough time to issue the CONFIG command to the

FPGA. The pin can be used as I/O after conﬁguration if

a resistor is used to hold INIT Low.

•

Issue the CONFIG command to the TMS input

Wait for INIT to go High

Sequence the boundary scan Test Access Port to the

SHIFT-DR state

If it is not possible to have the data ready at the time of the

ﬁrst CCLK, the problem can be avoided by increasing the

number in the length count by the appropriate value. The

XACT User Guide includes detailed information about man-

ually altering the length count.

•

Toggle TCK to clock data into TDI pin.

The user must account for all TCK clock cycles after INIT

goes High, as all of these cycles affect the Length Count

compare.

Note that DONE is an open-drain output and does not go

High unless an internal pull-up is activated or an external

pull-up is attached. The internal pull-up is activated as the

default by the bitstream generation software.

For more detailed information, refer to the Xilinx application

note XAPP017, “Boundary Scan in XC4000 Devices.” This

application note also applies to XC4000E and XC4000X

devices.

6-54

May 14, 1999 (Version 1.6)

Product Obsolete or Under Obsolescence

R

XC4000E and XC4000X Series Field Programmable Gate Arrays

Q3

Q2

Q1/Q4

DONE

IN

STARTUP

IOBs OPERATIONAL PER CONFIGURATION

*

GLOBAL SET/RESET OF

ALL CLB AND IOB FLIP-FLOP

1

0

GSR ENABLE

GSR INVERT

CONTROLLED BY STARTUP SYMBOL

STARTUP.GSR

IN THE USER SCHEMATIC (SEE

STARTUP.GTS

GTS INVERT

GTS ENABLE

LIBRARIES GUIDE)

0

1

GLOBAL 3-STATE OF ALL IOBs

Q

S

R

DONE

" FINISHED "

ENABLES BOUNDARY

SCAN, READBACK AND

CONTROLS THE OSCILLATOR

*

1

0

1

0

Q0

Q1

Q2

Q3

Q4

1

0

FULL

LENGTH COUNT

6

S

Q

D

Q

D

Q

D

Q

D

Q

M

K

*

CLEAR MEMORY

CCLK

0

1

STARTUP.CLK

USER NET

M

CONFIGURATION BIT OPTIONS SELECTED BY USER IN "MAKEBITS"

X1528

*

Figure 48: Start-up Logic

BACK library symbol and attach the appropriate pad sym-

bols, as shown in Figure 49.

Readback

The user can read back the content of conﬁguration mem-

ory and the level of certain internal nodes without interfer-

ing with the normal operation of the device.

After Readback has been initiated by a High level on

RDBK.TRIG after conﬁguration, the RDBK.RIP (Read In

Progress) output goes High on the next rising edge of

RDBK.CLK. Subsequent rising edges of this clock shift out

Readback data on the RDBK.DATA net.

Readback not only reports the downloaded conﬁguration

bits, but can also include the present state of the device,

represented by the content of all ﬂip-ﬂops and latches in

CLBs and IOBs, as well as the content of function genera-

tors used as RAMs.

Readback data does not include the preamble, but starts

with ﬁve dummy bits (all High) followed by the Start bit

(Low) of the ﬁrst frame. The ﬁrst two data bits of the ﬁrst

frame are always High.

Note that in XC4000 Series devices, conﬁguration data is

not inverted with respect to conﬁguration as it is in XC2000

and XC3000 families.

Each frame ends with four error check bits. They are read

back as High. The last seven bits of the last frame are also

read back as High. An additional Start bit (Low) and an

11-bit Cyclic Redundancy Check (CRC) signature follow,

before RDBK.RIP returns Low.

XC4000 Series Readback does not use any dedicated

pins, but uses four internal nets (RDBK.TRIG, RDBK.DATA,

RDBK.RIP and RDBK.CLK) that can be routed to any IOB.

To access the internal Readback signals, place the READ-

May 14, 1999 (Version 1.6)

6-55

Product Obsolete or Under Obsolescence

R

XC4000E and XC4000X Series Field Programmable Gate Arrays

IF UNCONNECTED,

DEFAULT IS CCLK

DATA

RIP

READ_DATA

CLK

MD1

READBACK

OBUF

READ_TRIGGER

TRIG

MD0

X1786

IBUF

Figure 49: Readback Schematic Example

Readback Options

I/O

Readback options are: Read Capture, Read Abort, and

Clock Select. They are set with the bitstream generation

software.

PROGRAMMABLE

INTERCONNECT

Read Capture

When the Read Capture option is selected, the readback

data stream includes sampled values of CLB and IOB sig-

nals. The rising edge of RDBK.TRIG latches the inverted

values of the four CLB outputs, the IOB output ﬂip-ﬂops and

the input signals I1 and I2. Note that while the bits describ-

ing conﬁguration (interconnect, function generators, and

RAM content) are not inverted, the CLB and IOB output sig-

nals are inverted.

rdbk

I/O

rdclk

X1787

Figure 50: READBACK Symbol in Graphical Editor

Violating the Maximum High and Low Time

Speciﬁcation for the Readback Clock

When the Read Capture option is not selected, the values

of the capture bits reﬂect the conﬁguration data originally

written to those memory locations.

The readback clock has a maximum High and Low time

speciﬁcation. In some cases, this speciﬁcation cannot be

met. For example, if a processor is controlling readback, an

interrupt may force it to stop in the middle of a readback.

This necessitates stopping the clock, and thus violating the

speciﬁcation.

If the RAM capability of the CLBs is used, RAM data are

available in readback, since they directly overwrite the F

and G function-table conﬁguration of the CLB.

The speciﬁcation is mandatory only on clocking data at the

end of a frame prior to the next start bit. The transfer mech-

anism will load the data to a shift register during the last six

clock cycles of the frame, prior to the start bit of the follow-

ing frame. This loading process is dynamic, and is the

source of the maximum High and Low time requirements.

RDBK.TRIG is located in the lower-left corner of the device,

as shown in Figure 50.

Read Abort

When the Read Abort option is selected, a High-to-Low

transition on RDBK.TRIG terminates the readback opera-

tion and prepares the logic to accept another trigger.

Therefore, the speciﬁcation only applies to the six clock

cycles prior to and including any start bit, including the

clocks before the ﬁrst start bit in the readback data stream.

At other times, the frame data is already in the register and

the register is not dynamic. Thus, it can be shifted out just

like a regular shift register.

After an aborted readback, additional clocks (up to one

readback clock per conﬁguration frame) may be required to

re-initialize the control logic. The status of readback is indi-

cated by the output control net RDBK.RIP. RDBK.RIP is

High whenever a readback is in progress.

The user must precisely calculate the location of the read-

back data relative to the frame. The system must keep track

of the position within a data frame, and disable interrupts

before frame boundaries. Frame lengths and data formats

are listed in Table 19, Table 20 and Table 21.

Clock Select

CCLK is the default clock. However, the user can insert

another clock on RDBK.CLK. Readback control and data

are clocked on rising edges of RDBK.CLK. If readback

must be inhibited for security reasons, the readback control

nets are simply not connected.

Readback with the XChecker Cable

The XChecker Universal Download/Readback Cable and

Logic Probe uses the readback feature for bitstream veriﬁ-

cation. It can also display selected internal signals on the

PC or workstation screen, functioning as a low-cost in-cir-

cuit emulator.

RDBK.CLK is located in the lower right chip corner, as

shown in Figure 50.

6-56

May 14, 1999 (Version 1.6)

Product Obsolete or Under Obsolescence

R

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000E/EX/XL Program Readback Switching Characteristic Guidelines

Testing of the switching parameters is modeled after testing methods speciﬁed by MIL-M-38510/605. All devices are 100%

functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns

that are taken at device introduction, prior to any process improvements.

The following guidelines reﬂect worst-case values over the recommended operating conditions.

Finished

Internal Net

rdbk.TRIG

T

RCRT

T

RCRT

2

T

RTRC

T

RTRC

2

1

rdclk.I

5

6

T

RCL

T

RCH

4

rdbk.RIP

T

RCRR

DUMMY

VALID

rdbk.DATA

T

RCRD

7

X1790

6

E/EX

Description

Symbol

Min

Max

Units

rdbk.TRIG

rdclk.1

rdbk.TRIG setup to initiate and abort Readback

rdbk.TRIG hold to initiate and abort Readback

1

2

T_RTRC

T_RCRT

200

50

-

ns

rdbk.DATA delay

rdbk.RIP delay

High time

7

6

5

4

T_RCRD

T_RCRR

T_RCH

-

250

500

ns

250

Low time

T_RCL

Note 1:

Note 2:

Timing parameters apply to all speed grades.

If rdbk.TRIG is High prior to Finished, Finished will trigger the ﬁrst Readback.

XL

Description

Symbol

Min

Max

Units

rdbk.TRIG

rdclk.1

rdbk.TRIG setup to initiate and abort Readback

rdbk.TRIG hold to initiate and abort Readback

1

2

T_RTRC

T_RCRT

200

50

-

ns

rdbk.DATA delay

rdbk.RIP delay

High time

7

6

5

4

T_RCRD

T_RCRR

T_RCH

-

250

500

ns

250

Low time

T_RCL

Note 1:

Note 2:

Timing parameters apply to all speed grades.

If rdbk.TRIG is High prior to Finished, Finished will trigger the ﬁrst Readback.

May 14, 1999 (Version 1.6)

6-57

Product Obsolete or Under Obsolescence

R

XC4000E and XC4000X Series Field Programmable Gate Arrays

Table 22: Pin Functions During Conﬁguration

CONFIGURATION MODE <M2:M1:M0>

SLAVE

SERIAL

<1:1:1>

M2(HIGH) (I)

M1(HIGH) (I)

M0(HIGH) (I)

HDC (HIGH)

LDC (LOW)

INIT

MASTER

SERIAL

<0:0:0>

M2(LOW) (I)

M1(LOW) (I)

M0(LOW) (I)

HDC (HIGH)

LDC (LOW)

INIT

SYNCH.

PERIPHERAL

<0:1:1>

M2(LOW) (I)

M1(HIGH) (I)

M0(HIGH) (I)

HDC (HIGH)

LDC (LOW)

INIT

ASYNCH.

MASTER

USER

OPERATION

PERIPHERAL PARALLEL DOWN PARALLEL UP

<1:0:1>

M2(HIGH) (I)

M1(LOW) (I)

M0(HIGH) (I)

HDC (HIGH)

LDC (LOW)

INIT

<1:1:0>

M2(HIGH) (I)

M1(HIGH) (I)

M0(LOW) (I)

HDC (HIGH)

LDC (LOW)

INIT

<1:0:0>

M2(HIGH) (I)

M1(LOW) (I)

M0(LOW) (I)

HDC (HIGH)

LDC (LOW)

INIT

(I)

(O)

(I)

I/O

DONE

PROGRAM (I)

CCLK (I)

PROGRAM (I)

CCLK (O)

PROGRAM (I)

CCLK (I)

RDY/BUSY (O)

PROGRAM (I)

CCLK (O)

RDY/BUSY (O)

RS (I)

PROGRAM (I)

CCLK (O)

RCLK (O)

PROGRAM (I)

CCLK (O)

RCLK (O)

PROGRAM

CCLK (I)

I/O

CS0 (I)

I/O

DATA 7 (I)

DATA 6 (I)

DATA 5 (I)

DATA 4 (I)

DATA 3 (I)

DATA 2 (I)

DATA 1 (I)

DATA 0 (I)

DOUT

DATA 7 (I)

DATA 6 (I)

DATA 5 (I)

DATA 4 (I)

DATA 3 (I)

DATA 2 (I)

DATA 1 (I)

DATA 0 (I)

DOUT

DATA 7 (I)

DATA 6 (I)

DATA 5 (I)

DATA 4 (I)

DATA 3 (I)

DATA 2 (I)

DATA 1 (I)

DATA 0 (I)

DOUT

TDI

DATA 7 (I)

DATA 6 (I)

DATA 5 (I)

DATA 4 (I)

DATA 3 (I)

DATA 2 (I)

DATA 1 (I)

DATA 0 (I)

DOUT

TDI

I/O

DIN (I)

DOUT

TDI

DIN (I)

DOUT

TDI

SGCK4-GCK6-I/O

TDI

TDI-I/O

TCK

TCK-I/O

TMS

TDO

TMS

TDO

TMS

TDO

TMS

TDO

TMS

TDO

TMS

TDO

TMS-I/O

TDO-(O)

WS (I)

A0

I/O

A1

PGCK4-GCK7-I/O

CS1

A2

I/O

A3

I/O

A4

I/O

A5

I/O

A6

I/O

A7

I/O

A8

I/O

A9

I/O

A10

I/O

A11

I/O

A12

I/O

A13

I/O

A14

I/O

A15

SGCK1-GCK8-I/O

A16

PGCK1-GCK1-I/O

A17

I/O

A18*

I/O

A19*

A20*

A19*

A20*

I/O

A21*

I/O

ALL OTHERS

6-58

May 14, 1999 (Version 1.6)

Product Obsolete or Under Obsolescence

R

XC4000E and XC4000X Series Field Programmable Gate Arrays

Table 23: Pin Functions During Conﬁguration

CONFIGURATION MODE <M2:M1:M0>

SLAVE

SERIAL

<1:1:1>

M2(HIGH) (I)

M1(HIGH) (I)

M0(HIGH) (I)

HDC (HIGH)

LDC (LOW)

INIT

MASTER

SERIAL

<0:0:0>

M2(LOW) (I)

M1(LOW) (I)

M0(LOW) (I)

HDC (HIGH)

LDC (LOW)

INIT

SYNCH.

PERIPHERAL

<0:1:1>

M2(LOW) (I)

M1(HIGH) (I)

M0(HIGH) (I)

HDC (HIGH)

LDC (LOW)

INIT

ASYNCH.

MASTER

USER

OPERATION

PERIPHERAL PARALLEL DOWN PARALLEL UP

<1:0:1>

M2(HIGH) (I)

M1(LOW) (I)

M0(HIGH) (I)

HDC (HIGH)

LDC (LOW)

INIT

<1:1:0>

M2(HIGH) (I)

M1(HIGH) (I)

M0(LOW) (I)

HDC (HIGH)

LDC (LOW)

INIT

<1:0:0>

M2(HIGH) (I)

M1(LOW) (I)

M0(LOW) (I)

HDC (HIGH)

LDC (LOW)

INIT

(I)

(O)

(I)

I/O

DONE

PROGRAM (I)

CCLK (I)

PROGRAM (I)

CCLK (O)

PROGRAM (I)

CCLK (I)

RDY/BUSY (O)

PROGRAM (I)

CCLK (O)

RDY/BUSY (O)

RS (I)

PROGRAM (I)

CCLK (O)

RCLK (O)

PROGRAM (I)

CCLK (O)

RCLK (O)

PROGRAM

CCLK (I)

I/O

CS0 (I)

I/O

DATA 7 (I)

DATA 6 (I)

DATA 5 (I)

DATA 4 (I)

DATA 3 (I)

DATA 2 (I)

DATA 1 (I)

DATA 0 (I)

DOUT

DATA 7 (I)

DATA 6 (I)

DATA 5 (I)

DATA 4 (I)

DATA 3 (I)

DATA 2 (I)

DATA 1 (I)

DATA 0 (I)

DOUT

DATA 7 (I)

DATA 6 (I)

DATA 5 (I)

DATA 4 (I)

DATA 3 (I)

DATA 2 (I)

DATA 1 (I)

DATA 0 (I)

DOUT

TDI

DATA 7 (I)

DATA 6 (I)

DATA 5 (I)

DATA 4 (I)

DATA 3 (I)

DATA 2 (I)

DATA 1 (I)

DATA 0 (I)

DOUT

TDI

I/O

6

DIN (I)

DOUT

TDI

DIN (I)

DOUT

TDI

SGCK4-GCK6-I/O

TDI

TDI-I/O

TCK

TCK-I/O

TMS

TDO

TMS

TDO

TMS

TDO

TMS

TDO

TMS

TDO

TMS

TDO

TMS-I/O

TDO-(O)

WS (I)

A0

I/O

A1

PGCK4-GCK7-I/O

CS1

A2

I/O

A3

I/O

A4

I/O

A5

I/O

A6

I/O

A7

I/O

A8

I/O

A9

I/O

A10

I/O

A11

I/O

A12

I/O

A13

I/O

A14

I/O

A15

SGCK1-GCK8-I/O

A16

PGCK1-GCK1-I/O

A17

I/O

A18*

I/O

A19*

A20*

A19*

A20*

I/O

A21*

I/O

ALL OTHERS

* XC4000X only

Notes 1. A shaded table cell represents a 50 kΩ - 100 kΩ pull-up before and during conﬁguration.

2. (I) represents an input; (O) represents an output.

3. INIT is an open-drain output during conﬁguration.

May 14, 1999 (Version 1.6)

6-59

Product Obsolete or Under Obsolescence

R

XC4000E and XC4000X Series Field Programmable Gate Arrays

There is an internal delay of 0.5 CCLK periods, which

means that DOUT changes on the falling CCLK edge, and

the next FPGA in the daisy chain accepts data on the sub-

sequent rising CCLK edge.

Conﬁguration Timing

The seven conﬁguration modes are discussed in detail in

this section. Timing speciﬁcations are included.

Figure 51 shows a full master/slave system. An XC4000

Series device in Slave Serial mode should be connected as

shown in the third device from the left.

Slave Serial Mode

In Slave Serial mode, an external signal drives the CCLK

input of the FPGA. The serial conﬁguration bitstream must

be available at the DIN input of the lead FPGA a short

setup time before each rising CCLK edge.

Slave Serial mode is selected by a <111> on the mode pins

(M2, M1, M0). Slave Serial is the default mode if the mode

pins are left unconnected, as they have weak pull-up resis-

tors during conﬁguration.

The lead FPGA then presents the preamble data—and all

data that overﬂows the lead device—on its DOUT pin.

NOTE:

M2, M1, M0 can be shorted

to VCC if not used as I/O

M2, M1, M0 can be shorted

to Ground if not used as I/O

VCC

4.7 KΩ

N/C

4.7 KΩ

M0 M1

M2

M0 M1

M2

M0 M1

M2

PWRDN

N/C

DOUT

DIN

DOUT

DIN

DOUT

CCLK

VCC

XC4000E/X

MASTER

SERIAL

XC4000E/X,

XC1700D

+5 V

XC3100A

4.7 KΩ

XC5200

SLAVE

CCLK

CLK

VPP

CEO

SLAVE

DATA

DIN

LDC

INIT

CE

PROGRAM

DONE

PROGRAM

RESET

D/P

RESET/OE

DONE

INIT

(Low Reset Option Used)

PROGRAM

X9025

Figure 51: Master/Slave Serial Mode Circuit Diagram

DIN

Bit n

Bit n + 1

1

2

5

T

CCL

DCC

CCD

CCLK

4

3

T

CCH

CCO

DOUT

(Output)

Bit n - 1

Bit n

X5379

Description

DIN setup

Symbol

Min

20

0

Max

Units

1

2

3

4

5

T_DCC

T_CCD

T_CCO

T_CCH

T_CCL

F_CC

ns

DIN hold

DIN to DOUT

High time

Low time

30

10

ns

CCLK

45

ns

Frequency

MHz

Note: Conﬁguration must be delayed until the INIT pins of all daisy-chained FPGAs are High.

Figure 52: Slave Serial Mode Programming Switching Characteristics

6-60

May 14, 1999 (Version 1.6)

Product Obsolete or Under Obsolescence

R

XC4000E and XC4000X Series Field Programmable Gate Arrays

For actual timing values please refer to “Conﬁguration

Switching Characteristics” on page 68. Be sure that the

serial PROM and slaves are fast enough to support this

data rate. XC2000, XC3000/A, and XC3100A devices do

not support the Fast ConﬁgRate option.

Master Serial Mode

In Master Serial mode, the CCLK output of the lead FPGA

drives a Xilinx Serial PROM that feeds the FPGA DIN input.

Each rising edge of the CCLK output increments the Serial

PROM internal address counter. The next data bit is put on

the SPROM data output, connected to the FPGA DIN pin.

The lead FPGA accepts this data on the subsequent rising

CCLK edge.

The SPROM CE input can be driven from either LDC or

DONE. Using LDC avoids potential contention on the DIN

pin, if this pin is conﬁgured as user-I/O, but LDC is then

restricted to be a permanently High user output after con-

ﬁguration. Using DONE can also avoid contention on DIN,

provided the early DONE option is invoked.

The lead FPGA then presents the preamble data—and all

data that overﬂows the lead device—on its DOUT pin.

There is an internal pipeline delay of 1.5 CCLK periods,

which means that DOUT changes on the falling CCLK

edge, and the next FPGA in the daisy chain accepts data

on the subsequent rising CCLK edge.

Figure 51 on page 60 shows a full master/slave system.

The leftmost device is in Master Serial mode.

Master Serial mode is selected by a <000> on the mode

pins (M2, M1, M0).

In the bitstream generation software, the user can specify

Fast ConﬁgRate, which, starting several bits into the ﬁrst

frame, increases the CCLK frequency by a factor of eight.

CCLK

(Output)

T

2

CKDS

T

DSCK

1

6

Serial Data In

n

n + 1

n + 2

Serial DOUT

(Output)

n – 3

n – 2

n – 1

n

X3223

Description

DIN setup

DIN hold

Symbol

T_DSCK

T_CKDS

Min

20

0

Max

Units

ns

1

CCLK

2

ns

Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay conﬁguration by pulling PROGRAM

Low until Vcc is valid.

2. Master Serial mode timing is based on testing in slave mode.

Figure 53: Master Serial Mode Programming Switching Characteristics

May 14, 1999 (Version 1.6)

6-61

Product Obsolete or Under Obsolescence

R

XC4000E and XC4000X Series Field Programmable Gate Arrays

Master Parallel Down mode is selected by a <110> on the

mode pins. The EPROM addresses start at 3FFFF and

decrement.

Master Parallel Modes

In the two Master Parallel modes, the lead FPGA directly

addresses an industry-standard byte-wide EPROM, and

accepts eight data bits just before incrementing or decre-

menting the address outputs.

Additional Address lines in XC4000 devices

The XC4000X devices have additional address lines

(A18-A21) allowing the additional address space required

to daisy-chain several large devices.

The eight data bits are serialized in the lead FPGA, which

then presents the preamble data—and all data that over-

ﬂows the lead device—on its DOUT pin. There is an inter-

nal delay of 1.5 CCLK periods, after the rising CCLK edge

that accepts a byte of data (and also changes the EPROM

address) until the falling CCLK edge that makes the LSB

(D0) of this byte appear at DOUT. This means that DOUT

changes on the falling CCLK edge, and the next FPGA in

the daisy chain accepts data on the subsequent rising

CCLK edge.

The extra address lines are programmable in XC4000EX

devices. By default these address lines are not activated. In

the default mode, the devices are compatible with existing

XC4000 and XC4000E products. If desired, the extra

address lines can be used by specifying the address lines

option in bitgen as 22 (bitgen -g AddressLines:22). The

lines (A18-A21) are driven when a master device detects,

via the bitstream, that it should be using all 22 address

lines. Because these pins will initially be pulled high by

internal pull-ups, designers using Master Parallel Up mode

should use external pull down resistors on pins A18-A21. If

Master Parallel Down mode is used external resistors are

not necessary.

The PROM address pins can be incremented or decre-

mented, depending on the mode pin settings. This option

allows the FPGA to share the PROM with a wide variety of

microprocessors and micro controllers. Some processors

must boot from the bottom of memory (all zeros) while oth-

ers must boot from the top. The FPGA is ﬂexible and can

load its conﬁguration bitstream from either end of the mem-

ory.

All 22 address lines are always active in Master Parallel

modes with XC4000XL devices. The additional address

lines behave identically to the lower order address lines. If

the Address Lines option in bitgen is set to 18, it will be

ignored by the XC4000XL device.

Master Parallel Up mode is selected by a <100> on the

mode pins (M2, M1, M0). The EPROM addresses start at

00000 and increment.

The additional address lines (A18-A21) are not available in

the PC84 package.

TO DIN OF OPTIONAL

DAISY-CHAINED FPGAS

HIGH

or

LOW

4.7KΩ

N/C

M2

N/C

M0 M1

TO CCLK OF OPTIONAL

DAISY-CHAINED FPGAS

CCLK

DOUT

NOTE:M0 can be shorted

to Ground if not used

as I/O.

M0 M1 M2

. . .

A17

A16

A15

A14

A13

A12

A11

A10

A9

DIN

DOUT

VCC

EPROM

(8K x 8)

(OR LARGER)

CCLK

4.7KΩ

USER CONTROL OF HIGHER

ORDER PROM ADDRESS BITS

CAN BE USED TO SELECT BETWEEN

ALTERNATIVE CONFIGURATIONS

INIT

XC4000E/X

SLAVE

A12

A11

A10

A9

PROGRAM

DONE

PROGRAM

INIT

D7

D6

D5

D4

D3

D2

D1

D0

A8

A7

D7

D6

D5

D4

D3

D2

D1

D0

A6

A5

A4

A3

A2

A1

A0

DONE

OE

CE

DATA BUS

8

PROGRAM

X9026

Figure 54: Master Parallel Mode Circuit Diagram

6-62

May 14, 1999 (Version 1.6)

Product Obsolete or Under Obsolescence

R

XC4000E and XC4000X Series Field Programmable Gate Arrays

A0-A17

(output)

Address for Byte n

Address for Byte n + 1

1

T

RAC

D0-D7

Byte

3

T

2

T

RCD

DRC

RCLK

(output)

7 CCLKs

CCLK

(output)

DOUT

(output)

D6

D7

Byte n - 1

X6078

Description

Delay to Address valid

Data setup time

Symbol

Min

Max

200

Units

6

1

2

3

T_RAC

T_DRC

T_RCD

0

60

0

ns

RCLK

Data hold time

Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay conﬁguration by pulling PROGRAM

Low until Vcc is valid.

2. The ﬁrst Data byte is loaded and CCLK starts at the end of the ﬁrst RCLK active cycle (rising edge).

This timing diagram shows that the EPROM requirements are extremely relaxed. EPROM access time can be longer than

500 ns. EPROM data output has no hold-time requirements.

Figure 55: Master Parallel Mode Programming Switching Characteristics

May 14, 1999 (Version 1.6)

6-63

Product Obsolete or Under Obsolescence

R

XC4000E and XC4000X Series Field Programmable Gate Arrays

The lead FPGA serializes the data and presents the pre-

amble data (and all data that overﬂows the lead device) on

its DOUT pin. There is an internal delay of 1.5 CCLK peri-

ods, which means that DOUT changes on the falling CCLK

edge, and the next FPGA in the daisy chain accepts data

on the subsequent rising CCLK edge.

Synchronous Peripheral Mode

Synchronous Peripheral mode can also be considered

Slave Parallel mode. An external signal drives the CCLK

input(s) of the FPGA(s). The ﬁrst byte of parallel conﬁgura-

tion data must be available at the Data inputs of the lead

FPGA a short setup time before the rising CCLK edge.

Subsequent data bytes are clocked in on every eighth con-

secutive rising CCLK edge.

In order to complete the serial shift operation, 10 additional

CCLK rising edges are required after the last data byte has

been loaded, plus one more CCLK cycle for each

daisy-chained device.

The same CCLK edge that accepts data, also causes the

RDY/BUSY output to go High for one CCLK period. The pin

name is a misnomer. In Synchronous Peripheral mode it is

really an ACKNOWLEDGE signal. Synchronous operation

does not require this response, but it is a meaningful signal

for test purposes. Note that RDY/BUSY is pulled High with

a high-impedance pullup prior to INIT going High.

Synchronous Peripheral mode is selected by a <011> on

the mode pins (M2, M1, M0).

NOTE:

M2 can be shorted to Ground

if not used as I/O

N/C

4.7 kΩ

M0 M1

M2

M0 M1

CCLK

M2

CCLK

CLOCK

OPTIONAL

DAISY-CHAINED

FPGAs

8

DATA BUS

D

0-7

DIN

DOUT

VCC

XC4000E/X

SYNCHRO-

NOUS

XC4000E/X

SLAVE

4.7 kΩ

PERIPHERAL

RDY/BUSY

INIT

CONTROL

SIGNALS

DONE

INIT

4.7 kΩ

PROGRAM

X9027

Figure 56: Synchronous Peripheral Mode Circuit Diagram

6-64

May 14, 1999 (Version 1.6)

Product Obsolete or Under Obsolescence

R

XC4000E and XC4000X Series Field Programmable Gate Arrays

CCLK

INIT

BYTE

0

BYTE

1

BYTE 0 OUT

BYTE 1 OUT

1

0

1

2

3

4

5

6

7

DOUT

RDY/BUSY

X6096

Description

INIT (High) setup time

D0 - D7 setup time

D0 - D7 hold time

CCLK High time

Symbol

T_IC

Min

5

Max

Units

µs

T_DC

60

0

ns

6

T_CD

ns

CCLK

T_CCH

T_CCL

F_CC

50

60

ns

CCLK Low time

ns

CCLK Frequency

8

MHz

Notes: 1. Peripheral Synchronous mode can be considered Slave Parallel mode. An external CCLK provides timing, clocking in the

ﬁrst data byte on the second rising edge of CCLK after INIT goes High. Subsequent data bytes are clocked in on every

eighth consecutive rising edge of CCLK.

2. The RDY/BUSY line goes High for one CCLK period after data has been clocked in, although synchronous operation does

not require such a response.

3. The pin name RDY/BUSY is a misnomer. In Synchronous Peripheral mode this is really an ACKNOWLEDGE signal.

4. Note that data starts to shift out serially on the DOUT pin 0.5 CCLK periods after it was loaded in parallel. Therefore,

additional CCLK pulses are clearly required after the last byte has been loaded.

Figure 57: Synchronous Peripheral Mode Programming Switching Characteristics

May 14, 1999 (Version 1.6)

6-65

Product Obsolete or Under Obsolescence

R

XC4000E and XC4000X Series Field Programmable Gate Arrays

The READY/BUSY handshake can be ignored if the delay

from any one Write to the end of the next Write is guaran-

teed to be longer than 10 CCLK periods.

Asynchronous Peripheral Mode

Write to FPGA

Asynchronous Peripheral mode uses the trailing edge of

the logic AND condition of WS and CS0 being Low and RS

and CS1 being High to accept byte-wide data from a micro-

processor bus. In the lead FPGA, this data is loaded into a

double-buffered UART-like parallel-to-serial converter and

is serially shifted into the internal logic.

Status Read

The logic AND condition of the CS0, CS1and RS inputs

puts the device status on the Data bus.

•

D7 High indicates Ready

D7 Low indicates Busy

D0 through D6 go unconditionally High

The lead FPGA presents the preamble data (and all data

that overﬂows the lead device) on its DOUT pin. The

RDY/BUSY output from the lead FPGA acts as a hand-

shake signal to the microprocessor. RDY/BUSY goes Low

when a byte has been received, and goes High again when

the byte-wide input buffer has transferred its information

into the shift register, and the buffer is ready to receive new

data. A new write may be started immediately, as soon as

the RDY/BUSY output has gone Low, acknowledging

receipt of the previous data. Write may not be terminated

until RDY/BUSY is High again for one CCLK period. Note

that RDY/BUSY is pulled High with a high-impedance

pull-up prior to INIT going High.

It is mandatory that the whole start-up sequence be started

and completed by one byte-wide input. Otherwise, the pins

used as Write Strobe or Chip Enable might become active

outputs and interfere with the ﬁnal byte transfer. If this

transfer does not occur, the start-up sequence is not com-

pleted all the way to the ﬁnish (point F in Figure 47 on page

53).

In this case, at worst, the internal reset is not released. At

best, Readback and Boundary Scan are inhibited. The

length-count value, as generated by the XACTstep soft-

ware, ensures that these problems never occur.

Although RDY/BUSY is brought out as a separate signal,

microprocessors can more easily read this information on

one of the data lines. For this purpose, D7 represents the

RDY/BUSY status when RS is Low, WS is High, and the

two chip select lines are both active.

The length of the BUSY signal depends on the activity in

the UART. If the shift register was empty when the new byte

was received, the BUSY signal lasts for only two CCLK

periods. If the shift register was still full when the new byte

was received, the BUSY signal can be as long as nine

CCLK periods.

Asynchronous Peripheral mode is selected by a <101> on

the mode pins (M2, M1, M0).

Note that after the last byte has been entered, only seven of

its bits are shifted out. CCLK remains High with DOUT

equal to bit 6 (the next-to-last bit) of the last byte entered.

N/C

4.7 kΩ

M0

M1

M0

CCLK

DIN

M1

M2

8

DATA

BUS

CCLK

D0–7

OPTIONAL

DAISY-CHAINED

FPGAs

DOUT

VCC

ADDRESS

DECODE

LOGIC

CS0

XC4000E/X

ADDRESS

BUS

ASYNCHRO-

NOUS

XC4000E/X

SLAVE

PERIPHERAL

4.7 kΩ

CS1

RS

WS

CONTROL

SIGNALS

RDY/BUSY

INIT

DONE

REPROGRAM

PROGRAM

4.7 kΩ

X9028

Figure 58: Asynchronous Peripheral Mode Circuit Diagram

6-66

May 14, 1999 (Version 1.6)

Product Obsolete or Under Obsolescence

R

XC4000E and XC4000X Series Field Programmable Gate Arrays

Write to LCA

Read Status

RS, CS0

WS, CS1

WS/CS0

RS, CS1

1

T

CA

3

T

4

7

CD

2

T

DC

READY

BUSY

D7

D0-D7

CCLK

4

T

WTRB

6

T

BUSY

RDY/BUSY

DOUT

Previous Byte D6

D7

D0

D1

D2

X6097

Description

Effective Write time

Symbol

T_CA

Min

Max

Units

6

1

100

ns

(CS0, WS=Low; RS, CS1=High)

Write

RDY

DIN setup time

2

3

4

T_DC

T_CD

60

0

ns

DIN hold time

RDY/BUSY delay after end of

Write or Read

T_WTRB

60

9

RDY/BUSY active after beginning

of Read

7

6

ns

RDY/BUSY Low output (Note 4)

T_BUSY

2

CCLK

periods

Notes: 1. Conﬁguration must be delayed until the INIT pins of all daisy-chained FPGAs are High.

2. The time from the end of WS to CCLK cycle for the new byte of data depends on the completion of previous byte

processing and the phase of the internal timing generator for CCLK.

3. CCLK and DOUT timing is tested in slave mode.

4. T

T

indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest

BUSY

occurs when a byte is loaded into an empty parallel-to-serial converter. The longest T

occurs when a new word

BUSY

is loaded into the input register before the second-level buffer has started shifting out data

This timing diagram shows very relaxed requirements. Data need not be held beyond the rising edge of WS. RDY/BUSY will

go active within 60 ns after the end of WS. A new write may be asserted immediately after RDY/BUSY goes Low, but write

may not be terminated until RDY/BUSY has been High for one CCLK period.

Figure 59: Asynchronous Peripheral Mode Programming Switching Characteristics

May 14, 1999 (Version 1.6)

6-67

Product Obsolete or Under Obsolescence

R

XC4000E and XC4000X Series Field Programmable Gate Arrays

Conﬁguration Switching Characteristics

T

Vcc

PROGRAM

INIT

POR

RE-PROGRAM

>300 ns

T

PI

T

ICCK

CCLK

CCLK OUTPUT or INPUT

<300 ns

M0, M1, M2

(Required)

DONE RESPONSE

I/O

VALID

X1532

<300 ns

Master Modes (XC4000E/EX)

Description

Symbol

T_POR

T_PI

Min

10

Max

40

Units

ms

M0 = High

M0 = Low

Power-On Reset

Program Latency

40

130

200

ms

30

µs per

CLB column

CCLK (output) Delay

T_ICCK

T_CCLK

40

640

80

250

2000

250

µs

ns

CCLK (output) Period, slow

CCLK (output) Period, fast

Master Modes (XC4000XL)

Description

Symbol

T_POR

T_PI

Min

10

Max

40

Units

ms

M0 = High

M0 = Low

Power-On Reset

Program Latency

40

130

200

ms

30

µs per

CLB column

CCLK (output) Delay

T_ICCK

T_CCLK

40

540

67

250

1600

200

µs

ns

CCLK (output) Period, slow

CCLK (output) Period, fast

Slave and Peripheral Modes (All)

Description

Power-On Reset

Symbol

T_POR

T_PI

Min

10

Max

33

Units

ms

Program Latency

30

200

µs per

CLB column

CCLK (input) Delay (required)

CCLK (input) Period (required)

T_ICCK

T_CCLK

4

µs

100

ns

6-68

May 14, 1999 (Version 1.6)

Product Obsolete or Under Obsolescence

R

XC4000E and XC4000X Series Field Programmable Gate Arrays

Product Availability

Table 24, Table 25, and Table 26 show the planned packages and speed grades for XC4000-Series devices. Call your local

sales ofﬁce for the latest availability information, or see the Xilinx website at http://www.xilinx.com for the latest revision of

the speciﬁcations.

Table 24: Component Availability Chart for XC4000XL FPGAs

PINS

84

100

144

160

176

208

240

256

299

304

352

411

432

475

559

560

TYPE

CODE

-3

C I

C

C I

C

C I

C

-2

-1

XC4002XL

-09C

-3

C I

C

C I

C

C I

C

C I

C

C I

C

C I

C

-2

-1

XC4005XL

XC4010XL

C I

C

-09C

-3

C I

C

C I

C

C I

C

C I

C

C I

C

C I

C

C I

C

-2

-1

-09C

-3

6

C I

C

C I

C

C I

C

C I

C

C I

C

C I

C

-2

-1

XC4013XL

-09C

-08C

C

-3

-2

C I

C

C I

C

C I

C

C I

C

C I

C

C I

C

XC4020XL

XC4028XL

-1

-09C

-3

-2

C I

C

C I

C

C I

C

C I

C

C I

C

C I

C

C I

C

-1

-09C

-3

-2

C I

C

C I

C

C I

C

C I

C

C I

C

C I

C

C I

C

-1

C I

C

XC4036XL

-09C

-08C

C

-3

-2

C I

C

C I

C

C I

C

C I

C

C I

C

C I

C

C I

C

XC4044XL

XC4052XL

-1

-09C

-3

-2

C I

C

C I

C

C I

C

C I

C

C I

C

-1

-09C

-3

-2

C I

C

C I

C

C I

C

C I

C

C I

C

-1

XC4062XL

-09C

-08C

C

-3

-2

-1

C I

XC4085XL

-09C

C

1/29/99

C = Commercial T_J= 0° to +85°C

I= Industrial T_J= -40°C to +100°C

May 14, 1999 (Version 1.6)

6-69

Product Obsolete or Under Obsolescence

R

XC4000E and XC4000X Series Field Programmable Gate Arrays

Table 25: Component Availability Chart for XC4000E FPGAs

PINS

84

100

120

144

156

160

191

208

223

225

240

299

304

TYPE

CODE

-4

C I

-3

-2

XC4003E

C I

C

C I

C

C I

C

C I

C

-1

-4

-3

-2

-1

-4

-3

-2

-1

-4

-3

-2

-1

-4

-3

-2

-1

-4

-3

-2

-1

-4

-3

-2

-1

-4

-3

-2

C I

C

C I

C

C I

C

C I

C

C I

C

C I

C

XC4005E

XC4006E

XC4008E

XC4010E

XC4013E

XC4020E

C I

C

C I

C

C I

C

C I

C

C I

C

C I

C

C I

C

C I

C

C I

C

C I

C

C I

C

C I

C

C I

C

C I

C

C I

C

C I

C

C I

C

C I

C

C I

C

C I

C

C I

C

C I

C

C I

C

C I

C

C I

C

C I

C

C I

C

C I

C

C I

C

XC4025E

1/29/99

C = Commercial T = 0° to +85°C

J

I= Industrial T = -40°C to +100°C

J

Table 26: Component Availability Chart for XC4000EX FPGAs

PINS

TYPE

CODE

208

240

299

304

352

411

432

High-Perf.

QFP

High-Perf.

QFP

Ceram.

PGA

High-Perf.

QFP

Plast.

BGA

Ceram.

PGA

Plast.

BGA

HQ208

HQ240

PG299

HQ304

BG352

PG411

BG432

-4

C I

C

C I

C

C I

C

C I

C

C I

C

XC4028EX -3

-2

-4

C I

C

C I

C

C I

C

C I

C

C I

C

-3

XC4036EX

-2

1/29/99

C = Commercial T = 0° to +85°C

J

I= Industrial T = -40°C to +100°C

J

6-70

May 14, 1999 (Version 1.6)

Product Obsolete or Under Obsolescence

R

XC4000E and XC4000X Series Field Programmable Gate Arrays

User I/O Per Package

Table 27, Table 28, and Table 29 show the number of user I/Os available in each package for XC4000-Series devices. Call

your local sales ofﬁce for the latest availability information, or see the Xilinx website at http://www.xilinx.com for the latest

revision of the speciﬁcations.

Table 27: User I/O Chart for XC4000XL FPGAs

Maximum User Accessible I/O by Package Type

Max

Device

I/O

64

61

64

77

64

77

XC4002XL

XC4005XL

XC4010XL

XC4013XL

XC4020XL

XC4028XL

XC4036XL

XC4044XL

XC4052XL

XC4062XL

112

160

192

224

256

288

320

352

384

448

112

129

112

113

112

160

145

160

192

205

113

145

192

129

160

193

256

288

289

288

320

352

288

320

352

384

448

384

6

448

XC4085XL

1/29/99

Table 28: User I/O Chart for XC4000E FPGAs

Maximum User Accessible I/O by Package Type

Max

Device

I/O

80

61

77

80

XC4003E

XC4005E

XC4006E

XC4008E

XC4010E

XC4013E

XC4020E

112

128

144

160

192

224

256

112

113

112

125

112

128

129

112

128

144

160

144

160

192

193

256

XC4025E

1/29/99

Table 29: User I/O Chart for XC4000EX FPGAs

Maximum User Accessible I/O by Package Type

Max

I/O

256

Device

HQ208

HQ240

193

PG299

HQ304

256

BG352

256

PG411

BG432

160

256

XC4028EX

193

256

288

XC4036EX

1/29/99

May 14, 1999 (Version 1.6)

6-71

Product Obsolete or Under Obsolescence

R

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000 Series Electrical Characteristics and Device-Speciﬁc Pinout Table

For the latest Electrical Characteristics and package/pinout information for each XC4000 Family, see the Xilinx web site at

http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp

Ordering Information

Example:

XC4013E-3HQ240C

Device Type

Temperature Range

C = Commercial (T = 0 to +85°C)

Speed Grade

J

I = Industrial (T = -40 to +100°C)

-6

-5

-4

-3

-2

-1

J

M = Military (T = -55 to+125°C)

C

Number of Pins

Package Type

PC = Plastic Lead Chip Carrier

BG = Ball Grid Array

PQ = Plastic Quad Flat Pack

VQ = Very Thin Quad Flat Pack

TQ = Thin Quad Flat Pack

PG = Ceramic Pin Grid Array

HQ = High Heat Dissipation Quad Flat Pack

MQ = Metal Quad Flat Pack

CB = Top Brazed Ceramic Quad Flat Pack

X9020

Revision Control

Version

Description

3/30/98 (1.5) Updated XC4000XL timing and added XC4002XL

1/29/99 (1.5) Updated pin diagrams

5/14/99 (1.6) Replaced Electrical Specification and pinout pages for E, EX, and XL families with separate updates and

added URL link for electrical specifications/pinouts for Web users

6-72

May 14, 1999 (Version 1.6)


型号：	XC4062XL-1HQG304C
厂家：	XILINX, INC
描述：	Field Programmable Gate Array, 2304 CLBs, 40000 Gates, 200MHz, CMOS, PQFP304, HQFP-304 栅
文件：	总68页 (文件大小：982K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

XC4062XL-1HQG304C [XILINX]

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XC4062XL-1PG475C

XC4062XL-1PG475I

XC4062XL-2BG432C

XC4062XL-2BG432I

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XC4062XL-2HQ240C

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