XC4085XLA-09HQ208C [XILINX]
Field Programmable Gate Array, 3136 CLBs, 55000 Gates, 227MHz, 7448-Cell, CMOS, PQFP208, QFP-208;型号: | XC4085XLA-09HQ208C |
厂家: | XILINX, INC |
描述: | Field Programmable Gate Array, 3136 CLBs, 55000 Gates, 227MHz, 7448-Cell, CMOS, PQFP208, QFP-208 时钟 栅 可编程逻辑 |
文件: | 总14页 (文件大小:134K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
0
XC4000XLA/XV Field Programmable
Gate Arrays
R
0
0*
DS015 (v1.3) October 18, 1999
Product Specification
XC4000XLA/XV Family Features
Electrical Features
Note: XC4000XLA devices are improved versions of
XC4000XL devices. The XC4000XV devices have the
same features as XLA devices, incorporate additional inter-
connect resources and extend gate capacity to 500,000
system gates. The XC4000XV devices require a separate
2.5V power supply for internal logic but maintain 5V I/O
compatibility via a separate 3.3V I/O power supply. For
additional information about the XC4000XLA/XV device
architecture, refer to the XC4000E/X FPGA Series general
and functional descriptions.
•
•
XLA Devices Require 3.0 - 3.6 V (VCC)
XV Devices Require 2.3- 2.7 V (VCCINT)
and 3.0 - 3.6 V (VCCIO)
•
•
•
•
•
•
•
•
5.0 V TTL compatible I/O
3.3 V LVTTL, LVCMOS compliant I/O
5.0 V and 3.0 V PCI Compliant I/O
12 mA or 24 mA Current Sink Capability
Safe under All Power-up Sequences
XLA Consumes 40% Less Power than XL
XV Consumes 65% Less Power than XL
Optional Input Clamping to VCC (XLA) or VCCIO (XV)
•
System-featured Field-Programmable Gate Arrays
-
Select-RAMTM memory: on-chip ultra-fast RAM with
Additional Features
-
-
Synchronous write option
Dual-port RAM option
•
•
•
•
•
•
Footprint Compatible with XC4000XL FPGAs - Lower
cost with improved performance and lower power
Advanced Technology — 5 layer metal, 0.25 µm CMOS
process (XV) or 0.35 µm CMOS process (XLA)
Highest Performance — System erformance beyond
100 MHz
High Capacity — Up to 500,000 system gates and
270,000 synchronous SRAM bits
Low Power — 3.3 V/2.5 V technology plus segmented
routing architecture
-
-
-
-
Flexible function generators and abundant flip-flops
Dedicated high-speed carry logic
Internal 3-state bus capability
Eight global low-skew clock or signal distribution
networks
6
•
•
•
Flexible Array Architecture
Low-power Segmented Routing Architecture
Systems-oriented Features
-
-
-
-
IEEE 1149.1-compatible boundary scan
Individually programmable output slew rate
Programmable input pull-up or pull-down resistors
Unlimited reprogrammability
Safe and Easy to Use — Interfaces to any combination
of 3.3 V and 5.0 V TTL compatible devices
•
Read Back Capability
Program verification and internal node observability
-
*
Table 1: XC4000XLA Series Field Programmable Gate Arrays
Max Logic Max. RAM
Typical
Gate Range
Number
of
Required
Configur-
Logic
Cells
Gates
Bits
CLB
Total
Max.
Device
(No RAM) (No Logic) (Logic and RAM)*
Matrix
CLBs
Flip-Flops User I/O ation Bits
XC4013XLA
XC4020XLA
XC4028XLA
XC4036XLA
XC4044XLA
XC4052XLA
XC4062XLA
XC4085XLA
XC40110XV
XC40150XV
XC40200XV
XC40250XV
1,368
1,862
2,432
3,078
3,800
4,598
5,472
7,448
9,728
12,312
16,758
20,102
13,000
20,000
28,000
36,000
44,000
52,000
62,000
85,000
110,000
150,000
200,000
250,000
18,432
25,088
32,768
41,472
51,200
61,952
73,728
100,352
131,072
165,888
225,792
270,848
10,000 - 30,000
13,000 - 40,000
18,000 - 50,000
22,000 - 65,000
27,000 - 80,000
33,000 - 100,000
40,000 - 130,000
55,000 - 180,000
75,000 - 235,000
100,000 - 300,000
130,000 - 400,000
180,000 - 500,000
24 x 24
28 x 28
32 x 32
36 x 36
40 x 40
44 x 44
48 x 48
56 x 56
64 x 64
72 x 72
84 x 84
92 x 92
576
1,536
2,016
2,560
3,168
3,840
4,576
5,376
7,168
9,216
11,520
15,456
18,400
192
224
256
288
320
352
384
448
448
448
448
448
393,632
521,880
784
1,024
1,296
1,600
1,936
2,304
3,136
4,096
5,184
7,056
8,464
668,184
832,528
1,014,928
1,215,368
1,433,864
1,924,992
2,686,136
3,373,448
4,551,056
5,433,888
* Maximum values of gate range assume 20-30% of CLBs used as RAM
DS015 (v1.3) October 18, 1999 - Product Specification
6-157
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XC4000XLA/XV Field Programmable Gate Arrays
The XV devices also incorporate additional routing
resources in the form of 8 octal-length segmented routing
channels vertically and horizontally per row and column.
General Description
XC4000 Series high-performance, high-capacity Field Pro-
grammable Gate Arrays (FPGAs) provide the benefits of
custom CMOS VLSI, while avoiding the initial cost, long
development cycle, and inherent risk of a conventional
masked gate array.
XLA/XV and XL Family Differences
The XC4000XLA/XV families of FPGAs are logically identi-
cal to XC4000EX and XC4000XL FPGAs, however I/O,
configuration logic, JTAG functionality, and performance
have been enhanced. In addition, they deliver:
The result of fifteen years of FPGA design experience and
feedback from thousands of customers, these FPGAs com-
bine architectural versatility, increased speed, abundant
routing resources, and new, sophisticated software to
achieve fully automated implementation of complex,
high-density, high-performance designs.
•
Improved Performance
XLA/XV devices benefit from advance processing
technology and a reduction in interconnect capacitance
which improves performance over XL devices by more
than 30%.
•
•
Lower Power
XLA/XV devices have reduced power requirements
compared to equivalent XL devices.
Shorter routing delays
The smaller die of XLA/XV devices directly reduces
clock delays and the delay of high-fanout signals. The
reduction in clock delay allows improved pin-to-pin I/O
specifications.
•
•
Lower Cost
XLA/XV device cost is directly related to the die size
and has been reduced significantly from that of
equivalent XL devices.
Express mode configuration
Express mode configuration is available on the XLA and
XV devices.
IOB Enhancements
Figure 1: Cross Section of Xilinx 0.25 micron, 5 layer
metal XC4000XV FPGA. Visible features are five layers of
metallization, tungsten plug vias and trench isolation. The
small gaps above the lowest layer are 0.25 micron
polysilicon MOSFET gates. The excellent planarity of each
metal layer is due to the use of “chemical-mechanical
polishing” or CMP. In effect, each layer is ground flat before
a new layer is added.
•
12/24 mA Output Drive
The XLA/XV family of FPGAs allow individual IOBs to
be configured as high drive outputs. Each output can be
configured to have 24 mA drive strength as opposed to
the standard default strength of 12 mA.
•
VCC Clamping Diode
XLA and XV FPGAs have an optional clamping diode
connected from each output to VCC (VCCIO for XV).
When enabled they clamp ringing transients back to the
3.3V supply rail. This clamping action is required in
3.3V PCI applications. VCC clamping is a global option
affecting all I/O pins. If enabled, TTL I/O compatibility is
maintained, but full 5.0 Volt I/O tolerance is sacrificed.
Enhanced ESD protection
An improved ESD structure allows XV devices to safely
pass the stringent 5V PCI (4.2.1.3) ringing test. This
test applies an 11V pulse to each IOB for 11 ns via a 55
ohm resistor.
Technology Advantage
XC4000XLA/XV FPGAs use 5 layer metal silicon technol-
ogy to improve performance while reducing device cost and
power. In addition, IOB enhancements provide full PCI
compliance and the JTAG functionality is expanded.
•
•
Low Power Internal Logic
XC4000XV FPGAs incorporate all the features of the XLA
devices but require a separate 2.5V power supply for inter-
nal logic. I/O pads are still driven from a 3.3V power supply.
The 2.5V logic supply is named VCCINT and the 3.3 V IO
supply is named VCCIO.
Full 3.3V and 5.0V PCI compliance
The addition of 12/24 mA drive, optional 3.3V clamping
and improved ESD provides full compliance with either
3.3V or 5.0V PCI specifications.
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XC4000XLA/XV Field Programmable Gate Arrays
Table 2: K-Factor and Relative Power.
Three-State Register
Power
Relative To Relative To
Power
XC4000XLA/XV devices incorporate an optional register
controlling the three-state enable in the IOBs.The use of
the three-state control register can significantly improve
output enable and disable time.
FPGA Family
XC4000XL
K-Factor
XL
XLA
1.65
1.00
0.58
28
17
13
1.00
0.60
0.35
XC4000XLA
XC4000XV
FastCLK Clock Buffers
The XLA/XV devices incorporate FastCLK clock buffers.
Two FastCLK buffers are available on each of the right and
left edges of the die. Each FastCLK buffer can provide a
fast clock signal (typically < 1.5 ns clock delay) to all the
IOBs within the IOB octant containing the buffer. The Fast-
CLK buffers can be instantiated by use of the BUFFCLK
symbols. (In addition to FastCLK buffers, the Global Early
BUFGE clock buffers #1, #2, #5, and #6 can also provide
fast clock signals (typically < 1.5 ns clock delay) to IOBs on
the top and bottom of the die.
XLA/XV Logic Performance
XC4000XLA/XV devices feature 30% faster device speed
than XL devices, and consistent performance is achieved
across all family members. Table 3 illustrates the perfor-
mance of the XLA devices. For details regarding the imple-
mentation of these benchmarks refer to XBRF15 “Speed
Metrics for High Performance FPGAs”.
Table 3: XLA/XV Estimated Benchmark Performance
Register - Register
Benchmarks
Maximum
Frequency
Size
XLA/XV Power Requirements
XC4000XLA devices require 40% less power per CLB than
equivalent XL devices. XC4000XV devices require 42%
less power per CLB than equivalent XLA devices and 65%
less power than XL devices The representative K-Factor for
the following families can be found in Table 2. The K-Factor
predicts device current for typical user designs and is
based on filling the FPGA with active 16-Bit counters and
measuring the device current at 1 MHz. This technique is
described in XBRF14 “A Simple Method of Estimating
Power in XC4000XL/EX/E FPGAs”. To predict device
power (P) using the K-Factor use the following formula:
8-Bit
16-Bit
172 MHz
144 MHz
108 MHz
94 MHz
Adder
32-Bit
6
2 Cascaded Adders
4 Cascaded Adders
16-Bit
16-Bit
57 MHz
1 Level
314 MHz
193 MHz
108 MHz
75 MHz
2 Level
Cascaded 4LUTs
4 Level
6 Level
1 CLBs
4 CLBs
16 CLBs
64 CLBs
128 CLBs
8-Bits by 16
8-Bits by 256
325 MHz
260 MHz
185 MHz
108 MHz
81 MHz
Interconnect
(Manhattan Distance)
P=V*K*N*F; where:
P= Device Power
V= Power supply voltage
K= the Device K-Factor
N = number of active registers
F = Frequency in MHz
Dual Port RAM
(Pipelined)
172 MHz
172 MHz
DS015 (v1.3) October 18, 1999 - Product Specification
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XC4000XLA/XV Field Programmable Gate Arrays
•
•
•
•
BUFGE (I,O) - The Global Early Buffer
BUFGLS (I,O)- The Global Low Skew Buffer
BUFFCLK (I,O) - The FastCLK Buffer
ILFFX (D, GF, CE, C, Q) - The Fast Capture Latch
Macro
Using Fast I/O CLKS
There are several issues associated with implementing fast
I/O clocks by using multiple FastCLK and BUFGE clock
buffers for I/O transfers and a BUFGLS clock buffer for
internal logic.
Locating I/O elements - It is necessary to connect these
elements to a particular I/O pad in order to select which
buffer or fast capture latch will be used.
Reduced Clock to Out Period - When transferring data
from a BUFGLS clocked register to an IOB output register
which is clocked with a fast I/O clock, the total amount of
time available for the transfer is reduced.
Restricted Clock Loading - Because the input hold
requirement is a function of internal clock delay, it may be
necessary to restrict the routing of BUFGE to IOBs along
the top and bottom of the die to obtain sub-ns clock delays.
Using Fast Capture Latch in IOB input - It is necessary to
transfer data captured with the fast I/O clock edge to a
delayed BUFGLS clock without error. The use of the Fast
Capture Latch in the IOBs provides this functionality.
BUFGE 6
BUFGE 1
Driving multiple clock inputs - Since each FastCLK input
can only reach one octant of IOBs it will usually be neces-
sary to drive multiple FastCLK and BUFGE input pads with
a copy of the system clock. Xilinx recommends that sys-
tems which use multiple FastCLK and BUFGE input buffers
use a “Zero Delay” clock buffer such as the Cypress
CY2308 to drive up to 8 input pins. These devices contain a
Phase locked loop to eliminate clock delay, and specify less
than 250ps output jitter.
FCLK 4
FCLK 1
FCLK 3
FCLK 2
PCB layout - The recommended layout is to place the PLL
underneath the FPGA on the reverse side of the PCB. All 8
clock lines should be of equal length. This arrangement will
allow all the clock line to be less than 2 cm in length which
will generally eliminate the need for clock termination.
BUFGLS 2
BUFGE 2
BUFGE 5
Figure 2: Location of FastCLK, BUFGE and BUFGLS
Clock Buffers in XC4000XLA/XV FPGAs
Advancing the FPGAs clock - An additional advantage to
using a PLL-equipped clock buffer is that it can advance the
FPGA clocks relative to the system clock by incorporating
additional board delay in the feedback path. Approximately
6 inches of trace length are necessary to delay the signal
by 1 ns.
PLL
Clock
Buffer
XC4000XLA
XC4000XV
BUFGE1
BUFGE2
O0
O1
O2
O3
O4
O5
O6
O7
BUFGE5
BUFGE6
Advancing the FPGA’s clock directly reduces input hold
requirements and improves clock to out delay. FPGA clocks
should not be advanced more than the guaranteed mini-
mum Output Hold Time (minus any associated clock jitter)
or the outputs may change state before the system clock
edge. For XLA and XV FPGAs the Output Hold Time is
specified as a minimum Clock to Output Delay in the tables
in the respective family Electrical Specification sections.
The maximum recommended clock advance equals this
value minus any clock jitter.
FCLK1
FCLK2
FCLK3
FCLK4
FB
Ref
SysClk
Figure 3: Diagram of XC4000XLA/XV FPGA
Connected to PLL Clock Buffer Driving 4 BUFGE and
4 FastCLK Clock Buffers.
Instantiating I/O elements- Depending on the design
environment, it may be necessary to instantiate the fast I/O
elements. They are found in the libraries as:
6-160
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XC4000XLA/XV Field Programmable Gate Arrays
•
Bypass FF - Bypass FF and IOB is modified to provide
DRCLOCK only during BYPASS for the bypass flip-flop
and during EXTEST or SAMPLE/PRELOAD for the IOB
register.
JTAG Enhancements
XC4000XLA/XV devices have improved JTAG functionality
and performance in the following areas:
•
IDCODE - The IDCODE register in JTAG is now
supported. All future Xilinx FPGAs will support the
IDCODE register. By using the IDCODE, the device
connected to the JTAG port can be determined. The
use of the IDCODE enables selective configuration
dependent upon the FPGA found. The IDCODE register
has the following binary format:
vvvv:ffff:fffa:aaaa:aaaa:cccc:cccc:ccc1
Where:
c = the company code;
XV and XLA Family Differences
The high density of the XC4000XV family FPGAs is
achieved by using advanced 0.25 micron silicon technol-
ogy. A 2.5 Volt power supply (VCCINT) is necessary to pro-
vide the reduced supply voltage required by 0.25 micron
internal logic, however to maintain TTL compatibility a 3.3V
power supply (VCCIO) is required by the I/O.
To accommodate the higher gate capacity of XV devices,
additional interconnect has been added. These differences
are detailed below.
a = the array dimension in CLBs;
f = the Family code;
v = the die version number
•
VCCINT (2.5 Volt) Power Supply Pins
The XV family of FPGAs requires a 2.5V power supply
for internal logic, which is named VCCINT. The pins
assigned to the VCCINT supply are named in the pinout
guide for the XC4000XV FPGAs and in Table 5 on page
162.
Family Codes = 01 for XLA;
= 02 for SpartanXL;
= 03 for Virtex;
= 07 for XV.
•
•
VCCIO (3.3 Volt) Power Supply Pins
Xilinx company code = 49 (hex)
Both the XV and XLA FPGAs use a 3.3V power supply
to power the I/O pins. The I/O supply is named VCCIO
in the XV family.
6
Table 4: IDCODEs assigned to XC4000XLA/XV FPGAs
FPGA
IDCODE
Octal-Length Interconnect Channels
XC4013XLA
XC4020XLA
XC4028XLA
XC4036XLA
XC4044XLA
XC4052XLA
XC4062XLA
XC4085XLA
XC40110XV
XC40150XV
XC40200XV
XC40250XV
0x00218093
0x0021c093
0x00220093
0x00224093
0x00228093
0x0022c093
0x00230093
0x00238093
0x00e40093
0x00e48093
0x00e54093
0x00e5c093
The XC40110XV, XC40150XV, XC40200XV, and
XC40250XV have enhanced routing. Eight routing
channels of octal length have been added to each CLB
in both vertical and horizontal dimensions.
XLA-to-XL Socket Compatibility
The XC4000XLA devices are generally available in the
same packages as equivalent XL devices, however the
range of packages available for the XC4085XLA has been
extended to include smaller packages such as the HQ240.
XV-to-XL/XLA Socket Compatibility
XC4000XV devices are available in five package options,
pin-grid PG599 and ball-grid BG560, BG432, and BG352
and quad-flatpack HQ240. With the exception of the
VCCINT power pins, XC4000XV FPGAs are compatible
with XL and XLA devices in these packages if the following
guidelines are followed:
•
•
•
•
Configuration State - The configuration state is
available to JTAG controllers.
Configure Disable - The JTAG port can be prevented
from reconfiguring the FPGA
TCK Startup - TCK can now be used to clock the
start-up block in addition to other user clocks.
CCLK holdoff - Changed the requirement for Boundary
Scan Configure or EXTEST to be issued prior to the
release of INIT pin and CCLK cycling.
Reissue configure - The Boundary Scan Configure
can be reissued to recover from an unfinished attempt
to configure the device.
•
•
Lay out the PCB for the XV pinout.
When an XL or XLA device is installed disconnect the
VCCINT (2.5 V) supply. For the PG599, VCCINT should
be connected to 3.3V. For BG560, BG432 and BG352
and HQ240 packages, the VCCINT voltage source
should be left unconnected. The unused I/O pins in the
XL/XLA devices connected to VCCINT will be pulled up
to 3.3V. Care must be taken to insure that these pins
are not driven when the XL/XLA device is operative.
When an XC4000XV is installed, the VCCINT pins must
•
•
DS015 (v1.3) October 18, 1999 - Product Specification
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XC4000XLA/XV Field Programmable Gate Arrays
be connected to a 2.5V power supply.
Table 5: VCCINT (2.5 V) Pins in XV Packages
The differences between the XL and XV packages are
detailed below:
HQ240
P198
P185
P164
P154
P137
P116
P104
P93
BG352
D10
D5
BG432
A10
BG560
E12
PG559
H12
PG559 - XLA and XL devices in the PG599 package have
56 VCC pins.The XC4000XV devices allocate 16 of these
I/O pins to VCCINT (2.5V).
AB2
AB30
AG28
AH15
AH5
AJ10
AK22
B23
AD2
AD32
AK31
AM17
AK5
AK11
AN25
C24
D6
H18
K4
H26
N3
H32
BG560 - XLA and XL devices in the BG560 package have
448 I/O pins.The XC4000XV devices allocate 16 of these
I/O pins to VCCINT (2.5V).
W2
M8
AE3
AC10
AC13
AE19
AB24
V24
N24
J24
M36
V8
BG432- XLA and XL devices in the BG432 package have
352 I/O pins. The XC4000XV devices allocate 16 of these
I/O pins to VCCINT (2.5V).
V36
P77
AF8
P55
B4
AF36
AM8
AM36
AT12
AT18
AT26
AT32
BG352 - XLA and XL devices in the BG352 package have
289 I/O pins.The XC4000XV devices allocate 15 of these
I/O pins to VCCINT (2.5V).
P43
C16
E28
C17
E30
P27
P16
K29
K32
HQ240- XLA and XL devices in the HQ240 package have
193 I/O pins.The XC4000XV devices allocate 15 of these
I/O pins to VCCINT (2.5V).
P4
D24
A20
-
K3
J1
P225
-
R2
T3
R29
U32
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XC4000XLA/XV Field Programmable Gate Arrays
XLA/XV devices maintain LVTTL I/O compatibility when
VCC clamping is enabled, however full 5.0V TTL I/O com-
patibility is sacrificed.
I/O Signalling Standards
XLA and XV devices are compatible with TTL, LVTTL, PCI
3V, PCI 5V and LVCMOS signalling. The various standards
are illustrated in Table 6 and the signaling environment is
illustrated in Figure 4.
Overshoot and Undershoot
Ringing wave forms are allowed on XLA/XV inputs as long
as undershoot is limited to -2.0V and overshoot is limited to
+7.0V and current is limited to 100 mA for less than 10 ns.
If VCC clamping is enabled then overshoot will begin to be
clamped at VCC/VCCIO plus one diode voltage drop and
undershoot will be clamped to ground minus one diode volt-
age drop. In either case the current must be limited to 100
mA per pin for less than 10 ns.
VCC Clamping
XLA/XV devices are fully 5V TTL I/O compatible if VCC
clamping is not enabled. The I/O pins can withstand input
voltages up to 7V. With VCC clamping enabled, the XLA/XV
devices will begin to clamp input voltages to one diode volt-
age drop above VCC. In both cases negative voltage is
clamped to one diode voltage drop below ground.
Table 6: I/O Standards supported by XC4000XLA and XV FPGAs
Signaling
Standard
VCC
VIH_MAX
VIH MIN
VIL MAX
VOH MIN
VOL MAX
Clamping Output Drive
TTL
Not allowed
OK
12/24 mA
12/24 mA
24 mA
5.5
3.6
5.5
3.6
2.0
2.0
0.8
0.8
2.4
2.4
0.4
0.4
LVTTL
PCI5V
PCI3V
Not allowed
Required
2.0
0.8
2.4
0.4
12 mA
50% of
30% of
90% of
10% of
VCC/VCCIO VCC/VCCIO VCC/VCCIO VCC/VCCIO
50% of 30% of 90% of 10% of
VCC/VCCIO VCC/VCCIO VCC/VCCIO VCC/VCCIO
6
LVCMOS 3V
OK
12/24 mA
3.6
5.0 V Power
3.3 V Power
2.5 V Power
V
(5 V)
V
V
(3.3 V)
CC
V
CC
CCIO
CCINT
TTL
LVTTL
5 Volt Device
XC4000XV
3.3 Volt Device
LVTTL
Ground
X7147
Figure 4: The Signalling Environment for XLA/XV FPGAS. For XLA devices the VCCIO and VCCINT supplies are
replaced by a single 3.3 Volt VCC supply, however, all indicated I/O signalling is still supported.
port CRC error checking, but does support constant-field
Express Configuration Mode
error checking. A length count is not used in Express mode.
Express configuration mode is similar to Slave Serial con-
Express mode must be specified as an option to the BitGen
figuration mode, except that data is processed one byte per
program, which generates the bitstream. The Express
CCLK cycle instead of one bit per CCLK cycle. An external
mode bitstream is not compatible with the other configura-
source is used to drive CCLK, while byte-wide data is
tion modes. Express mode is selected by a <010> on the
mode pins (M2, M1, M0).
loaded directly into the configuration data shift registers
The first byte of parallel configuration data must be avail-
(Figure 5). A CCLK frequency of 10 MHz is equivalent to a
able at the D inputs of the FPGA a short setup time before
80 MHz serial rate, because eight bits of configuration data
the second rising CCLK edge. Subsequent data bytes are
are loaded per CCLK cycle. Express mode does not sup-
DS015 (v1.3) October 18, 1999 - Product Specification
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XC4000XLA/XV Field Programmable Gate Arrays
clocked in on each consecutive rising CCLK edge
(Figure 6).
becomes active as soon as that device has been config-
ured.
Table 7: Pin Functions During Configuration
(4000XLA/XV Express mode only)
Pseudo Daisy Chain
As illustrated in Figures 5 and 6, multiple devices with dif-
ferent configurations can be configured in a pseudo daisy
chain provided that all of the devices are in Express mode.
A single combined byte-wide data stream is used to config-
ure the chain of Express mode devices. CCLK pins are tied
together and D0-D7 pins are tied together as a data buss
for all devices along the chain. A status signal is passed
from DOUT of each device to the CS1 input of the device
which follows it in the chain. Frame data is accepted only
when CS1 is High and the device’s configuration memory is
not already full. The lead device in the chain has its CS1
input tied High (or floating, since there is an internal pullup).
The status pin DOUT is initially High for all devices in the
chain until the data stream header of seven bytes is loaded.
This allows header data to be loaded into all devices in the
chain simultaneously. After the header is loaded in all
devices, their DOUT pins are pulled Low disabling configu-
ration of all devices in the chain except the first device. As
each device in the chain is filled, its DOUT goes High driv-
ing High the CS1 input of the next device, thereby enabling
configuration of the next device in the pseudo daisy chain.
CONFIGURATION MODE
<M2:M1:M0>
USER
OPERATION
EXPRESS MODE
<0:1:0>
PIN FUNCTION
M2(LOW) (I)
M1(HIGH) (I)
M0(LOW) (I)
HDC (HIGH)
LDC (LOW)
INIT
M2
M1
M0
I/O
I/O
I/O
DONE
DONE
PROGRAM
CCLK (I)
I/O
PROGRAM (I)
CCLK (I)
DATA 7 (I)
DATA 6 (I)
DATA 5 (I)
DATA 4 (I)
DATA 3 (I)
DATA 2 (I)
DATA 1 (I)
DATA 0 (I)
DOUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SGCK4-I/O
TDI-I/O
TCK-I/O
TMS-I/O
TDO-(O)
I/O
TDI
TCK
TMS
TDO
The requirement that all DONE pins in a daisy chain be
wired together applies only to Express mode, and only if all
devices in the chain are to become active simultaneously.
All 4000XLA/XV devices in Express mode are synchro-
nized to the DONE pin. User I/O for each device becomes
active after the DONE pin for that device goes High (The
exact timing is determined by BitGen options.)
CS1
Notes 1. A shaded table cell represents the internal
pull-up used before and during
configuration.
2. (I) represents an input; (O) represents an
output.
3. INIT is an open-drain output during
configuration.
Since the DONE pin is open-drain and does not drive a
High value, tying the DONE pins of all devices together pre-
vents all devices in the chain from going High until the last
device in the chain has completed its configuration cycle. If
the DONE pin of a device is left unconnected, the device
Because only XC4000XLA/XV, SpartanXL, and XC5200
devices support Express mode, only these devices can be
used to form an Express mode pseudo daisy chain.
6-164
DS015 (v1.3) October 18, 1999 - Product Specification
R
XC4000XLA/XV Field Programmable Gate Arrays
VCC
8
To Additional
Optional
Daisy-Chained
Devices
M1
M1
M0
M2
M0
M2
CS1
D0-D7
CS1
D0-D7
DOUT
DOUT
8
8
DATA BUS
Optional
Daisy-Chained
4000XLA/XV
VCC
4000XLA/XV
4.7K
PROGRAM
INIT
PROGRAM
INIT
PROGRAM
INIT
DONE
DONE
CCLK
CCLK
To Additional
Optional
Daisy-Chained
Devices
6
CCLK
99010800
Figure 5: Express Mode Circuit Diagram
Table 8: Express Mode Programming Switching Characteristic
Description
INIT (High) setup time
D0 - D7 setup time
D0 - D7 hold time
CCLK High time
Symbol
TIC
Min
5
Max
Units
µs
TDC
20
0
ns
TCD
ns
CCLK
TCCH
TCCL
FCC
45
45
ns
CCLK Low time
ns
CCLK Frequency
10
MHz
Preliminary
DS015 (v1.3) October 18, 1999 - Product Specification
6-165
R
XC4000XLA/XV Field Programmable Gate Arrays
CCLK
INIT
1
T
IC
T
3
CD
2
T
DC
BYTE
6
BYTE
B
BYTE
C
BYTE
5
BYTE
A
BYTE
0
BYTE
1
BYTE
2
BYTE
3
BYTE
4
D0-D7
DOUT
Header
Header Loaded
First FPGA Filled
CS1
First
FPGA
CS1
Second
FPGA
CS1 all
downstream
FPGAs
Byte A is first frame byte for first FPGA
Byte B is last frame byte for first FPGA
Byte C is first frame byte for second FPGA
99012600
Note: CS1 must remain High throughout loading of the configuration data stream. In the pseudo daisy chain of Figure 5, the 7 byte
data stream header is loaded into all devices simultaneously. Each device’s data frames are then loaded in turn when its
CS1 pin is driven High by the DOUT of the preceding device in the chain.
Figure 6: Express Mode Configuration Switching Waveforms
Table 9: 4000XLA/XV Express Mode Data Stream
Format
Data Stream Format
The data stream (“bitstream”) format is identical for all
serial configuration modes, but different for the
4000XLA/XV Express mode. In Express mode, the device
becomes active when DONE goes High, therefore no
length count is required. Additionally, CRC error checking is
not supported in Express mode. The data stream format is
shown in Table 9. Express mode data is shown with D0 at
the left and D7 at the right.
Express Mode
(D0-D7)
(4000XLA only)
Data Type
Fill Byte
FFFFh
Preamble Code
Fill Byte
11110010b
FFFFFFh
End-of-Header
11010010b
The configuration data stream begins with two bytes of
eight ones each, a preamble code of one byte, followed by
three bytes of eight ones each, and finally an end-of-
header field check byte. This header of seven bytes is fol-
lowed by the actual configuration data in frames. The
length and number of frames depends on the device type.
Each frame begins with a start field and ends with an
end-of-frame field check byte. In all cases, additional
start-up bytes of data are required to provide six, or more,
clocks for the start-up sequence at the end of configuration.
Long daisy chains require additional startup bytes to shift
the last data through the chain. All startup bytes are
don’t-cares; these bytes are not included in bitstreams cre-
ated by the Xilinx software.
Field Check Byte
Start Field
11111110b
DATA(n-1:0)
11010010b
Data Frame
End-of-Frame
Field Check Byte
Extend Write Cycle
Start-Up Bytes
FFD2FFFFFFh
FFFFFFFFFFFFh
LEGEND:
Unshaded
Light
Once per data stream
Once per data frame
Detection of an error results in the suspension of data load-
ing and the pulling down of the INIT pin. The user must
detect INIT and initialize a new configuration by pulsing the
PROGRAM pin Low or cycling VCC.
A selection of CRC or non-CRC error checking is allowed
by the bitstream generation software. The 4000XLA
Express mode only supports non-CRC error checking. The
non-CRC error checking tests for
a
designated
end-of-frame field check byte for each frame. non-CRC
error checking tests for a designated end-of-frame field
check byte for each frame.
6-166
DS015 (v1.3) October 18, 1999 - Product Specification
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XC4000XLA/XV Field Programmable Gate Arrays
Serial PROM Recommendation
Table 10 shows the physical characteristics of each XLA/XV family member and the recommended Xilinx Serial PROM
recommended for use as configuration storage.
Table 10: Physical Characteristics and Recommended Serial PROM
Number Max. RAM Required
Max.
User I/O
CLB
Matrix
Total
CLBs
Logic
Cells
Device
of
Bits
Configur-
Serial PROM
Flip-Flops (No Logic) ation Bits
XC4013XLA
XC4020XLA
XC4028XLA
XC4036XLA
XC4044XLA
XC4052XLA
XC4062XLA
XC4085XLA
XC40110XV
XC40150XV
XC40200XV
XC40250XV
192
224
256
288
320
352
384
448
448
448
448
448
24 x 24
28 x 28
32 x 32
36 x 36
40 x 40
44 x 44
48 x 48
56 x 56
64 x 64
72 x 72
84 x 84
92 x 92
576
1,368
1,862
2,432
3,078
3,800
4,598
5,472
7,448
9,728
12,312
16,758
20,102
1,536
2,016
2,560
3,168
3,840
4,576
5,376
7,168
9,216
11,520
15,456
18,400
18,432
25,088
32,768
41,472
51,200
61,952
73,728
100,352
131,072
165,888
225,792
270,848
393,632
521,880
XC17512L
XC17512L
XC1701L
XC1701L
XC1701L
XC1702L
XC1702L
XC1702L
XC1704L
XC1704L
784
1,024
1,296
1,600
1,936
2,304
3,136
4,096
5,184
7,056
8,464
668,184
832,528
1,014,928
1,215,368
1,433,864
1,924,992
2,686,136
3,373,448
4,551,056 XC1704L+XC17512L
5,433,888 XC1704L+XC1702L
User I/O Per Package
Table 11 shows the number of user I/Os available in each package for XC4000XLA/XV-Series devices. Call your local sales
office for the latest availability information.
6
Table 11: User I/O Pins Available by Device and Package
Maximum I/O Accessible per Package
Max
I/O
Device
192
224
256
288
320
352
384
448
448
448
448
448
129
129
160
160
192
193
192
205
205
XC4013XLA
XC4020XLA
XC4028XLA
XC4036XLA
XC4044XLA
XC4052XLA
XC4062XLA
XC4085XLA
XC40110XV
XC40150XV
XC40200XV
XC40250XV
129
129
129
129
129
129
160
160
160
160
160
160
193
193
193
193
193
193
178
178
256
288
289
289
289
289
274
274
288
320
352
352
352
336
336
336
336
256
256
256
256
352
384
448
432
432
432
432
448
448
DS015 (v1.3) October 18, 1999 - Product Specification
6-167
R
XC4000XLA/XV Field Programmable Gate Arrays
Product Availability
XLA Family
Table 12 shows the current available package and speed grade combinations for XC4000XLA Series devices. Call your local
sales office for the latest availability information, or see the Xilinx WEBLINX at http://www.xilinx.com for the latest revision of
the specifications.
Table 12: Component Availability Chart for XC4000XLA FPGAs
PINS
84
100
100
144
144
160
160
176
176
208
208
240
240
256
299
304
352
411
432
475
559
560
TYPE
CODE
-09
C I
C I
C
C I
C I
C
C I
C I
C
C I
C I
C
-08
-07
-09
-08
-07
XC4013XLA
C I
C I
C
C I
C I
C
C I
C I
C
C I
C I
XC4020XLA
XC4028XLA
XC4036XLA
XC4044XLA
XC4052XLA
XC4062XLA
C
C I
C I
C
-09
-08
-07
C I
C I
C
C I
C I
C
C I
C I
C I
C I
C
C
-09
-08
-07
C I
C I
C
C I
C I
C
C I
C I
C I
C I
C
C I
C I
C
C
-09
-08
-07
C I
C I
C
C I
C I
C
C I
C I
C I
C I
C
C I
C I
C
C I
C I
C
C
C I
C I
C
-09
-08
-07
C I
C I
C
C I
C I
C
C I
C I
C I
C I
C
C I
C I
C
C I
C I
C
C
-09
-08
-07
C I
C I
C
C I
C I
C
C I
C I
C I
C I
C
C I
C I
C
C I
C I
C
C I
C I
C
C
-09
-08
-07
C I
C I
C
C I
C I
C
C I
C I
C I
C I
C
C I
C I
C
C I
C I
C
C I
C I
C
XC4085XLA
C
1/25/99
C = Commercial T = 0° to +85°C
J
I= Industrial T = -40°C to +100°C
J
6-168
DS015 (v1.3) October 18, 1999 - Product Specification
R
XC4000XLA/XV Field Programmable Gate Arrays
XV Family
Table 13 show the current available package and speed grade combinations for the XC4000XV Series devices. Call your
local sales office for the latest availability information, or see the Xilinx WEBLINX at http://www.xilinx.com for the latest
revision of the specifications.
Table 13: Component Availability Chart for XC4000XV FPGAs
PINS
84
100
100
144
144
160
160
176
176
208
208
240
240
256
299
304
352
411
432
475
559
560
TYPE
CODE
-09
C I
C I
C
C I
C I
C
C I
C I
C
C I
C I
C
-08
-07
-09
-08
-07
-09
-08
-07
-09
-08
-07
XC40110XV
XC40150XV
XC40200XV
C I
C I
C
C I
C I
C
C I
C I
C
C I
C I
C
C I
C I
C
C I
C I
C
C I
C I
C
C I
C I
C
C I
C I
C
C I
C I
C
XC40250XV
6
11/24/98
C = Commercial T = 0° to +85°C
J
I= Industrial T = -40°C to +100°C
J
DS015 (v1.3) October 18, 1999 - Product Specification
6-169
R
XC4000XLA/XV Field Programmable Gate Arrays
XC4000 Series Electrical Characteristics and Device-Specific Pinout Tables
For the latest Electrical Characteristics and pinout information for each XC4000 Family, see the Xilinx web site at
http://www.xilinx.com/partinfo/databook.htm#xc4000
Revision Control
Version
2/1/99 (1.0)
2/19/99 (1.1)
5/14/99 (1.2)
Description
Release included in 1999 data book, section 6
Updated Switching Characteristics Tables
Replaced Electrical Specification pages for XLA and XV families with separate updates and added
URL link on placeholder page for electrical specifications/pinouts for WebLINX users.
10/18/99 (1.3)
Deleted HQ304 package/XC4028XLA and XC4036XLA entries from Table 11, page 6-168. Changed
do DS015.
6-170
DS015 (v1.3) October 18, 1999 - Product Specification
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