XC4VFX12-12FF668C
更新时间：2024-10-30 03:06:05
品牌：XILINX
描述：Field Programmable Gate Array, 1368 CLBs, 1205MHz, 12312-Cell, CMOS, PBGA668, FBGA-668
概述
数据手册
替代型号XC4VFX12-12FF668C 概述
Field Programmable Gate Array, 1368 CLBs, 1205MHz, 12312-Cell, CMOS, PBGA668, FBGA-668 FPGA芯片
XC4VFX12-12FF668C 数据手册
通过下载XC4VFX12-12FF668C数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载`
0
R
Virtex-4 Family Overview
0
0
DS112 (v3.1) August 30, 2010
Product Specification
General Description
Combining Advanced Silicon Modular Block (ASMBL™) architecture with a wide variety of flexible features, the Virtex®-4
family from Xilinx greatly enhances programmable logic design capabilities, making it a powerful alternative to ASIC
technology. Virtex-4 FPGAs comprise three platform families—LX, FX, and SX—offering multiple feature choices and
combinations to address all complex applications. The wide array of Virtex-4 FPGA hard-IP core blocks includes the
PowerPC® processors (with a new APU interface), tri-mode Ethernet MACs, 622 Mb/s to 6.5 Gb/s serial transceivers,
dedicated DSP slices, high-speed clock management circuitry, and source-synchronous interface blocks. The basic Virtex-4
FPGA building blocks are enhancements of those found in the popular Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and
Virtex-II Pro X product families, so previous-generation designs are upward compatible. Virtex-4 devices are produced on a
state-of-the-art 90 nm copper process using 300 mm (12-inch) wafer technology.
Summary of Virtex-4 Family Features
•
Three Families — LX/SX/FX
•
SelectIO™ Technology
-
-
Virtex-4 LX: High-performance logic applications solution
Virtex-4 SX: High-performance solution for digital signal
processing (DSP) applications
Virtex-4 FX: High-performance, full-featured solution for
embedded platform applications
-
-
-
-
1.5V to 3.3V I/O operation
Built-in ChipSync™ source-synchronous technology
Digitally controlled impedance (DCI) active termination
Fine grained I/O banking (configuration in one bank)
-
•
•
•
•
•
Flexible Logic Resources
•
•
•
Xesium™ Clock Technology
Secure Chip AES Bitstream Encryption
90 nm Copper CMOS Process
1.2V Core Voltage
Flip-Chip Packaging including Pb-Free Package
Choices
-
-
-
Digital clock manager (DCM) blocks
Additional phase-matched clock dividers (PMCD)
Differential global clocks
XtremeDSP™ Slice
-
-
-
18 x 18, two’s complement, signed Multiplier
Optional pipeline stages
Built-in Accumulator (48-bit) and Adder/Subtracter
•
•
RocketIO™ 622 Mb/s to 6.5 Gb/s Multi-Gigabit
Transceiver (MGT) [FX only]
Smart RAM Memory Hierarchy
-
IBM PowerPC RISC Processor Core [FX only]
Distributed RAM
-
Dual-port 18-Kbit RAM blocks
-
-
PowerPC 405 (PPC405) Core
Auxiliary Processor Unit Interface (User Coprocessor)
·
·
Optional pipeline stages
Optional programmable FIFO logic automatically
remaps RAM signals as FIFO signals
•
Multiple Tri-Mode Ethernet MACs [FX only]
-
High-speed memory interface supports DDR and DDR-2
SDRAM, QDR-II, and RLDRAM-II.
Table 1: Virtex-4 FPGA Family Members
(1)
Block RAM
Max
Configurable Logic Blocks (CLBs)
Max
PowerPC
Processor Ethernet Transceiver
RocketIO
Total Max
I/O User
Banks I/O
(3)
Array
Logic
Cells
Distributed XtremeDSP 18 Kb
Slices RAM (Kb)
Block
Slices(2) Blocks RAM (Kb)
Blocks
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
MACs
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Blocks
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Device
DCMs PMCDs
Row x Col
32
48
64
64
80
96
96
96
XC4VLX15
XC4VLX25
XC4VLX40
XC4VLX60
XC4VLX80
64 x 24
96 x 28
13,824 6,144
24,192 10,752
96
168
288
416
560
768
1056
1392
48
72
864
4
8
0
4
4
4
8
8
8
8
9
320
448
640
640
768
960
960
960
1,296
1,728
2,880
3,600
4,320
5,184
6,048
11
13
13
15
17
17
17
128 x 36 41,472 18,432
128 x 52 59,904 26,624
160 x 56 80,640 35,840
96
8
160
200
240
288
336
8
12
12
12
12
XC4VLX100 192 x 64 110,592 49,152
XC4VLX160 192 x 88 152,064 67,584
XC4VLX200 192 x 116 200,448 89,088
© Copyright 2004–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. The PowerPC name and logo are registered trademarks of IBM Corp. and used under license. All other trademarks are the property of their respective owners.
DS112 (v3.1) August 30, 2010
www.xilinx.com
Product Specification
1
R
Virtex-4 Family Overview
Table 1: Virtex-4 FPGA Family Members (Continued)
(1)
Block RAM
Max
Configurable Logic Blocks (CLBs)
Max
PowerPC
Processor Ethernet Transceiver
Blocks
RocketIO
Total Max
I/O User
Banks I/O
(3)
Array
Logic
Cells
Distributed XtremeDSP 18 Kb
Slices RAM (Kb)
Block
Slices(2) Blocks RAM (Kb)
MACs
N/A
N/A
N/A
2
Blocks
N/A
N/A
N/A
N/A
8
Device
DCMs PMCDs
Row x Col
128
192
512
32
XC4VSX25
XC4VSX35
XC4VSX55
XC4VFX12
XC4VFX20
XC4VFX40
XC4VFX60
64 x 40
96 x 40
23,040 10,240
34,560 15,360
160
240
384
86
128
192
320
36
2,304
3,456
5,760
648
4
8
0
4
4
0
0
4
8
8
8
N/A
N/A
N/A
1
9
320
448
640
320
320
448
576
768
896
11
13
9
128 x 48 55,296 24,576
8
64 x 24
64 x 36
96 x 52
12,312 5,472
19,224 8,544
41,904 18,624
4
32
134
291
395
659
987
68
1,224
2,592
4,176
6,768
9,936
4
1
2
9
48
144
232
376
552
8
2
4
12
11
13
15
17
128
160
192
128 x 52 56,880 25,280
12
12
20
2
4
16
XC4VFX100 160 x 68 94,896 42,176
XC4VFX140 192 x 84 142,128 63,168
Notes:
2
4
20
2
4
24
1.
2.
3.
One CLB = Four Slices = Maximum of 64 bits.
Each XtremeDSP slice contains one 18 x 18 multiplier, an adder, and an accumulator
Some of the row/column array is used by the processors in the FX devices.
System Blocks Common to All Virtex-4 Families
Xesium Clock Technology
500 MHz XtremeDSP Slices
•
Dedicated 18-bit x 18-bit multiplier,
multiply-accumulator, or multiply-adder blocks
Optional pipeline stages for enhanced performance
Optional 48-bit accumulator for multiply accumulate
(MACC) operation
Integrated adder for complex-multiply or multiply-add
operation
Cascadeable Multiply or MACC
•
Up to twenty Digital Clock Manager (DCM) modules
-
-
-
Precision clock deskew and phase shift
Flexible frequency synthesis
Dual operating modes to ease performance trade-off
decisions
•
•
-
-
-
-
-
-
Improved maximum input/output frequency
Improved phase shifting resolution
Reduced output jitter
Low-power operation
Enhanced phase detectors
•
•
•
Up to 100% speed improvement over previous
generation devices.
Wide phase shift range
•
•
Companion Phase-Matched Clock Divider (PMCD)
blocks
Differential clocking structure for optimized low-jitter
clocking and precise duty cycle
500 MHz Integrated Block Memory
•
•
•
Up to 10 Mb of integrated block memory
Optional pipeline stages for higher performance
Multi-rate FIFO support logic
•
•
32 Global Clock networks
Regional I/O and Local clocks
-
-
-
Full and Empty Flag support
Fully programmable AF and AE Flags
Synchronous/ Asynchronous Operation
•
•
Dual-port architecture
Independent read and write port width selection (RAM
only)
18 Kbit blocks (memory and parity/sideband memory
support)
Configurations from 16K x 1 to 512 x 36
(4K x 4 to 512 x 36 for FIFO operation)
Byte-write capability (connection to PPC405, etc.)
Dedicated cascade routing to form 32K x 1 memory
without using FPGA routing
Flexible Logic Resources
•
Up to 40% speed improvement over previous
generation devices
•
•
•
Up to 200,000 logic cells including:
-
Up to 178,176 internal registers with clock enable
(XC4VLX200)
-
-
Up to 178,176 look-up tables (LUTs)
Logic expanding multiplexers and I/O registers
•
•
•
Cascadable variable shift registers or distributed
memory capability
•
Up to 100% speed improvement over previous
generation devices.
DS112 (v3.1) August 30, 2010
www.xilinx.com
Product Specification
2
R
Virtex-4 Family Overview
SelectIO Technology
Digitally Controlled Impedance (DCI)
Active I/O Termination
•
•
•
Up to 960 user I/Os
Wide selections of I/O standards from 1.5V to 3.3V
Extremely high-performance
•
•
Optional series or parallel termination
Temperature compensation
-
-
600 Mb/s HSTL & SSTL (on all single-ended I/O)
1 Gb/s LVDS (on all differential I/O pairs)
Configuration
•
•
True differential termination
Selected low-capacitance I/Os for improved signal
integrity
Same edge capture at input and output I/Os
Memory interface support for DDR and DDR-2
SDRAM, QDR-II, and RLDRAM-II.
•
256-bit AES bitstream decryption provides intellectual
property (IP) security
Improved bitstream error detection/correction capability
Fast SelectMAP configuration
JTAG support
•
•
•
•
•
•
Readback capability
90 nm Copper CMOS Process
1.2V Core Voltage
ChipSync Technology
•
•
•
Integrated with SelectIO technology to simplify
source-synchronous interfaces
Per-bit deskew capability built in all I/O blocks (variable
input delay line)
Dedicated I/O and regional clocking resources (pin and
trees)
Flip-Chip Packaging
•
Pb-Free packages available with production devices.
•
•
Built in data serializer/deserializer logic in all I/O and
clock dividers
Memory/Networking/Telecommunication interfaces up
to 1 Gb/s+ DDR
System Blocks Specific to the Virtex-4 FX Family
•
Auxiliary Processor Unit (APU) Interface for direct
connection from PPC405 to coprocessors in fabric
RocketIO Multi-Gigabit Transceiver (MGT)
•
Full-duplex serial transceiver (MGT) capable of
622 Mb/s to 6.5 Gb/s baud rates
-
-
-
-
APU can run at different clock rates
Supports autonomous instructions: no pipeline stalls
32-bit instruction and 64-bit data
•
8B/10B, 64B/66B, user-defined FPGA logic, or no data
encoding/decoding
4-cycle cache line transfer
•
•
•
•
•
•
•
•
•
Channel bonding support
CRC generation and checking
Tri-Mode Ethernet Media Access Controller
Programmable TX pre-emphasis or pre-equalization
Programmable RX continuous time equalization
Programmable RX decision feedback equalization
On-chip RX AC coupling
RX signal detect and loss of signal indicator
TX driver electrical idle mode
•
•
•
•
•
IEEE 802.3 compliant
Operates at 10, 100, and 1,000 Mb/s
Supports tri-mode auto-detect
Receive address filter
Fully monolithic 1000Base-X solution with RocketIO
MGT
Implements SGMII through RocketIO MGT to external
PHY device
Supports multiple PHY (MII, GMII, etc.) interfaces
through an I/O resource
Receive and transmit statistics available through
separate interfaces
Separate host and client interfaces
Support for jumbo frames
User dynamic reconfiguration using secondary
configuration bus
•
•
•
PowerPC 405 Processor RISC Core
•
Embedded PowerPC 405 processor (PPC405) core
-
-
-
-
-
Up to 450 MHz operation
Five-stage data path pipeline
16 KB instruction cache
16 KB data cache
Enhanced instruction and data on-chip memory
(OCM) controllers
•
•
•
Flexible, user-configurable host interface
-
Additional frequency ratio options between
PPC405 and Processor Local Bus
DS112 (v3.1) August 30, 2010
www.xilinx.com
Product Specification
3
R
Virtex-4 Family Overview
Architectural Description: Virtex-4 FPGA Array Overview
Virtex-4 devices are user-programmable gate arrays with
various configurable elements and embedded cores opti-
mized for high-density and high-performance system
designs. Virtex-4 devices implement the following function-
ality:
•
Digital Clock Manager (DCM) blocks provide
self-calibrating, fully digital solutions for clock
distribution delay compensation, clock
multiplication/division, and coarse-/fine-grained clock
phase shifting.
•
I/O blocks provide the interface between package pins
and the internal configurable logic. Most popular and
leading-edge I/O standards are supported by
programmable I/O blocks (IOBs). The IOBs are
enhanced for source-synchronous applications.
Source-synchronous optimizations include per-bit
deskew, data serializer/deserializer, clock dividers, and
dedicated local clocking resources.
Additionally, FX devices support the following embedded
system functionality:
•
Integrated high-speed serial transceivers enable data
rates up to 6.5 Gb/s per channel.
•
Embedded IBM PowerPC 405 Processor RISC CPU
(up to 450 MHz) with the auxiliary processor unit
interface
•
10/100/1000 Ethernet media-access control (EMAC)
cores.
•
•
Configurable Logic Blocks (CLBs), the basic logic
elements for Xilinx FPGAs, provide combinatorial and
synchronous logic as well as distributed memory and
SRL16 shift register capability.
Block RAM modules provide flexible 18Kbit true
dual-port RAM, that are cascadable to form larger
memory blocks. In addition, Virtex-4 FPGA block RAMs
contain optional programmable FIFO logic for
increased device utilization.
The general routing matrix (GRM) provides an array of rout-
ing switches between each component. Each programma-
ble element is tied to a switch matrix, allowing multiple
connections to the general routing matrix. The overall pro-
grammable interconnection is hierarchical and designed to
support high-speed designs.
All programmable elements, including the routing
resources, are controlled by values stored in static memory
cells. These values are loaded in the memory cells during
configuration and can be reloaded to change the functions
of the programmable elements.
•
Cascadable embedded XtremeDSP slices with 18-bit x
18-bit dedicated multipliers, integrated Adder, and
48-bit accumulator.
Virtex-4 FPGA Features
This section briefly describes the features of the Virtex-4 family of FPGAs.
•
•
HSTL 1.5V and 1.8V (Class I, II, III, and IV)
SSTL 1.8V and 2.5V (Class I and II)
Input/Output (SelectIO) Blocks
IOBs are programmable and can be categorized as follows:
The DCI I/O feature can be configured to provide on-chip
termination for each single-ended I/O standard and some
differential I/O standards.
•
Programmable single-ended or differential (LVDS)
operation
Input block with an optional single data rate (SDR) or
double data rate (DDR) register
Output block with an optional SDR or DDR register
Bidirectional block
Per-bit deskew circuitry
•
The IOB elements also support the following differential sig-
naling I/O standards:
•
•
•
•
•
•
•
•
•
•
•
LVDS and Extended LVDS (2.5V only)
BLVDS (Bus LVDS)
ULVDS
Hypertransport™
Differential HSTL 1.5V and 1.8V (Class II)
Differential SSTL 1.8V and 2.5V (Class II)
Dedicated I/O and regional clocking resources
Built in data serializer/deserializer
The IOB registers are either edge-triggered D-type flip-flops
or level-sensitive latches.
Two adjacent pads are used for each differential pair. Two or
four IOB blocks connect to one switch matrix to access the
routing resources.
IOBs support the following single-ended standards:
•
•
•
•
•
LVTTL
LVCMOS (3.3V, 2.5V, 1.8V, and 1.5V)
PCI (33 and 66 MHz)
PCI-X
Per-bit deskew circuitry allows for programmable signal
delay internal to the FPGA. Per-bit deskew flexibly provides
fine-grained increments of delay to carefully produce a
GTL and GTLP
DS112 (v3.1) August 30, 2010
www.xilinx.com
Product Specification
4
R
Virtex-4 Family Overview
range of signal delays. This is especially useful for synchro-
nizing signal edges in source synchronous interfaces.
XtremeDSP Slices
The XtremeDSP slices contain a dedicated 18 x 18-bit 2’s
complement signed multiplier, adder logic, and a 48-bit
accumulator. Each multiplier or accumulator can be used
independently. These blocks are designed to implement
extremely efficient and high-speed DSP applications.
General purpose I/O in select locations (four per bank) are
designed to be “regional clock capable” I/O by adding spe-
cial hardware connections for I/O in the same locality. These
regional clock inputs are distributed within a limited region
to minimize clock skew between IOBs. Regional I/O clock-
ing supplements the global clocking resources.
The block DSP feature in Virtex-4 devices are further dis-
cussed in XtremeDSP Design Considerations.
Data serializer/deserializer capability is added to every I/O
to support source synchronous interfaces. A serial-to-paral-
lel converter with associated clock divider is included in the
input path, and a parallel-to-serial converter in the output
path.
Global Clocking
The DCM and global-clock multiplexer buffers provide a
complete solution for designing high-speed clock networks.
Up to twenty DCM blocks are available. To generate
deskewed internal or external clocks, each DCM can be
used to eliminate clock distribution delay. The DCM also
provides 90°, 180°, and 270° phase-shifted versions of the
output clocks. Fine-grained phase shifting offers higher res-
olution phase adjustment with fraction of the clock period
increments. Flexible frequency synthesis provides a clock
output frequency equal to a fractional or integer multiple of
the input clock frequency.
An in-depth guide to the Virtex-4 FPGA IOB is discussed in
the Virtex-4 FPGA User Guide.
Configurable Logic Blocks (CLBs)
A CLB resource is made up of four slices. Each slice is
equivalent and contains:
•
•
•
•
•
Two function generators (F & G)
Two storage elements
Arithmetic logic gates
Large multiplexers
Fast carry look-ahead chain
Virtex-4 devices have 32 global-clock MUX buffers. The
clock tree is designed to be differential. Differential clocking
helps reduce jitter and duty cycle distortion.
The function generators F & G are configurable as 4-input
look-up tables (LUTs). Two slices in a CLB can have their
LUTs configured as 16-bit shift registers, or as 16-bit distrib-
uted RAM. In addition, the two storage elements are either
edge-triggered D-type flip-flops or level sensitive latches.
Each CLB has internal fast interconnect and connects to a
switch matrix to access general routing resources.
Routing Resources
All components in Virtex-4 devices use the same intercon-
nect scheme and the same access to the global routing
matrix. Timing models are shared, greatly improving the
predictability of the performance for high-speed designs.
Boundary-Scan
The Virtex-4 FPGA CLBs are further discussed in the
Virtex-4 FPGA User Guide.
Boundary-Scan instructions and associated data registers
support a standard methodology for accessing and config-
uring Virtex-4 devices, complying with IEEE standards
1149.1 and 1532.
Block RAM
The block RAM resources are 18 Kb true dual-port RAM
blocks, programmable from 16K x 1 to 512 x 36, in various
depth and width configurations. Each port is totally synchro-
nous and independent, offering three “read-during-write”
modes. Block RAM is cascadable to implement large
embedded storage blocks. Additionally, back-end pipeline
registers, clock control circuitry, built-in FIFO support, and
byte write enable are new features supported in the Virtex-4
FPGA.
Configuration
Virtex-4 devices are configured by loading the bitstream into
internal configuration memory using one of the following
modes:
•
•
•
•
•
Slave-serial mode
Master-serial mode
Slave SelectMAP mode
Master SelectMAP mode
Boundary-Scan mode (IEEE-1532)
The block RAM feature in Virtex-4 devices is further dis-
cussed in the Virtex-4 FPGA User Guide.
Optional 256-bit AES decryption is supported on-chip (with
software bitstream encryption) providing Intellectual Prop-
erty security.
DS112 (v3.1) August 30, 2010
www.xilinx.com
Product Specification
5
R
Virtex-4 Family Overview
Virtex-4 FX Family
This section briefly describes blocks available only in FX devices.
RocketIO Multi-Gigabit Transceiver
One or Two PowerPC 405 Processor Cores
•
•
•
32-bit Harvard Architecture
5-Stage Execution Pipeline
Integrated 16KB Level 1 Instruction Cache and 16KB
Level 1 Data Cache
Integrated Level 1 Cache Parity Generation and
Checking
CoreConnect™ Bus Architecture
Efficient, high-performance on-chip memory (OCM)
interface to block RAM
PLB Synchronization Logic (Enables Non-Integer
CPU-to-PLB Clock Ratios)
Auxiliary Processor Unit (APU) Interface and Integrated
APU Controller
8 – 24 Channels RocketIO Multi-Gigabit Serial Transceivers
(MGTs) capable of running 622 Mb/s – 6.5 Gb/s
•
•
•
Full Clock and Data Recovery
32-bit or 40-bit datapath support
Optional 8B/10B, 64B/66B, or FPGA-based
encode/decode
•
•
•
•
•
•
•
Integrated FIFO/Elastic Buffer
Support for Channel Bonding
Embedded 32-bit CRC generation/checking
Integrated Comma-detect or programmable A1/A2,
A1A1/A2A2 detection
•
•
•
Programmable pre-emphasis (AKA transmitter
equalization)
-
-
Optimized FPGA-based Coprocessor connection
Automatic decode of PowerPC floating-point instructions
— allows custom instructions (decode for up to eight
instructions)
•
•
Programmable receiver equalization
Embedded support for:
-
-
Out of Band (OOB) Signalling: Serial ATA
Beaconing and Electrical Idle: PCI-Express™
-
Extremely efficient microcontroller-style interfacing
•
On-chip bypassable AC coupling for receiver
Two or Four Tri-Mode (10/100/1000 Mb/s) Ethernet Media Access Control (MAC) Cores
•
•
IEEE 802.3-2000 Compliant
MII/GMII Interface or SGMII (when used with RocketIO
Transceivers)
•
•
•
Half- or Full-Duplex
Supports Jumbo Frames
1000Base-X PCS/PMA: When used with RocketIO
MGT can provide complete 1000Base-X
implementation on-chip
•
Can Operate Independent of PowerPC processor
Industry leading connectivity and networking IP cores
include the electronics industry's first Advanced Switching
product, leading-edge PCI Express, Serial RapidIO, Fibre
Channel, and 10Gb Ethernet cores that include Virtex-4
FPGA RocketIO multi-gigabit serial interfaces. The Xilinx
SPI-4.2 IP core utilizes the Virtex-4 FPGA embedded
ChipSync technology to implement dynamic phase align-
ment for high-performance source-synchronous operation.
Intellectual Property Cores
Xilinx offers IP cores for commonly used complex functions
including DSP, bus interfaces, processors, and processor
peripherals. Using Xilinx LogiCORE™ products and cores
from third party AllianceCORE participants, customers can
shorten development time, reduce design risk, and obtain
superior performance for their designs. Additionally, our
CORE Generator™ system allows customers to implement
IP cores into Virtex-4 FPGAs with predictable and repeat-
able performance. It offers a simple user interface to gener-
ate parameter-based cores optimized for our FPGAs.
MicroBlaze™ processor 32-bit core provides the industry's
fastest soft processing solution for building complex sys-
tems for the networking, telecommunication, data communi-
cation, embedded and consumer markets. The MicroBlaze
processor features a RISC architecture with Harvard-style
separate 32-bit instruction and data busses running at full
speed to execute programs and access data from both
on-chip and external memory. A standard set of peripherals
are also CoreConnect™ enabled to offer MicroBlaze pro-
cessor designers compatibility and reuse.
The System Generator for DSP tool allows system archi-
tects to quickly model and implement DSP functions using
handcrafted IP, and features an interface to third-party sys-
tem level DSP design tools. System Generator for DSP
implements many of the high-performance DSP cores sup-
porting Virtex-4 FPGAs including the Xilinx Forward Error
Correction
Solution
with
Interleaver/De-interleaver,
All IP cores for Virtex-4 FPGAs are found on the Xilinx IP
Center Internet portal presenting the latest intellectual prop-
erty cores and reference designs via Smart Search for
faster access.
Reed-Solomon encoder/decoders, and Viterbi decoders.
These are ideal for creating highly-flexible, concatenated
codecs to support the communications market.
DS112 (v3.1) August 30, 2010
www.xilinx.com
Product Specification
6
R
Virtex-4 Family Overview
Application Notes and Reference Designs
Application notes and reference designs written specifically for the Virtex-4 family are available on the Xilinx web site at
http://www.xilinx.com/support/documentation/virtex-4.htm.
Virtex-4 Device and Package Combinations and Maximum I/Os
Table 2: Virtex-4 Device and Package Combinations and Maximum Available I/Os
SF363
SFG363
FF668
FFG668
FF672
FFG672
FF676
FFG676
FF1148
FFG1148
FF1152
FFG1152
FF1513
FFG1513
FF1517
FFG1517
Package(1,2)
Size
Device
17 x 17
27 x 27
27 x 27
27 x 27
35 x 35
35 x 35
40 x 40
40 x 40
MGTs
I/O
240
240
MGTs
I/O
320
448
448
448
MGTs
I/O
MGTs
N/A
I/O
MGTs
I/O
MGTs
I/O
MGTs
I/O
MGTs
I/O
XC4VLX15
XC4VLX25
XC4VLX40
XC4VLX60
XC4VLX80
XC4VLX100
XC4VLX160
XC4VLX200
XC4VSX25
XC4VSX35
XC4VSX55
XC4VFX12
XC4VFX20
XC4VFX40
XC4VFX60
XC4VFX100
XC4VFX140
N/A
N/A
N/A
N/A
N/A
N/A
320
N/A
N/A
N/A
N/A
N/A
640
640
768
768
768
N/A
N/A
N/A
960
960
960
N/A
N/A
320
448
N/A
640
N/A
240
N/A
320
8
320
352
352
12
12
12
16
20
448
576
576
20
24
768
768
Notes:
1. All packages are also available in Pb-Free versions (SFG/FFG).
2. Pinouts on all packages (except SF363/SFG363 and FF668/FFG668) are configured using the new, improved SparseChevron pin
layout for superior signal integrity.
Virtex-4 FPGA Ordering Information
Virtex-4 FPGA ordering information shown in Figure 1 applies to all packages including Pb-Free.
Example: XC4VLX25-10FFG668CS2
Step Identification Version(1)
Device Type
Speed Grade
Temperature Range:
(-10, -11, -12(2))
C = Commercial (TJ = 0°C to +85°C)
I = Industrial(2) (TJ = –40°C to +100°C)
Number of Pins
Pb-Free
Package Type
Notes:
1) The step identification version is optional and is not specified unless
a particular device stepping is required. Refer to the Virtex-4 Data
Sheet (DS302) for additional information on step ordering codes.
2) -12 devices not available in Industrial grade.
DS112_01_112806
Figure 1: Virtex-4 FPGA Ordering Information
DS112 (v3.1) August 30, 2010
www.xilinx.com
Product Specification
7
R
Virtex-4 Family Overview
Virtex-4 Documentation
Complete and up-to-date documentation of the Virtex-4
family of FPGAs is available on the Xilinx web site. In addi-
tion to the most recent Virtex-4 Family Overview, the follow-
ing files are also available for download:
Virtex-4 FPGA Configuration Guide
This all-encompassing configuration guide includes chap-
ters on configuration interfaces (serial and SelectMAP), bit-
stream encryption, Boundary-Scan and JTAG configuration,
and reconfiguration techniques.
Virtex-4 FPGA Data Sheet: DC and Switching
Characteristics
Virtex-4 FPGA Packaging and Pinout Specification
This data sheet contains the DC and Switching Characteris-
tic specifications for the Virtex-4 family.
This specification includes the tables for device/package
combinations and maximum I/Os, pin definitions, pinout
tables, pinout diagrams, mechanical drawings, and thermal
specifications.
Virtex-4 FPGA User Guide
This guide includes chapters on:
Virtex-4 FPGA PCB Designer’s Guide
•
•
•
•
•
•
•
•
Clocking Resources
This guide describes PCB guidelines for the Virtex-4 family.
It covers SelectIO signaling, RocketIO signaling, power dis-
tribution systems, PCB breakout, and parts placement.
Digital Clock Manager (DCM)
Phase-Matched Clock Dividers (PMCD)
Block RAM and FIFO memory
Configurable Logic Blocks (CLBs)
SelectIO Resources
Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide
This guide describes the RocketIO Multi-Gigabit Transceiv-
ers available in the Virtex-4 FX family.
SelectIO Logic Resources
Advanced SelectIO Logic Resources
Virtex-4 FPGA Embedded Tri-Mode Ethernet MAC User
Guide
XtremeDSP for Virtex-4 FPGAs User Guide
This guide describes the Embedded Tri-Mode Ethernet
Media Access Controller available in the Virtex-4 FX family.
This guide describes the DSP48 slice and includes refer-
ence designs for using DSP48 math functions and various
FIR filters.
PowerPC 405 Processor Block Reference Guide
This guide is updated to include the PowerPC 405 proces-
sor block available in the Virtex-4 FX family.
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revision
08/02/04
09/10/04
12/08/04
Initial Xilinx release. Printed Handbook version.
Typographical edits.
1.1
1.2
•
•
Removed System Monitor and ADC references.
Edited Ethernet MAC section.
03/26/05
1.3
•
•
•
Removed legacy CLB reference and typographical edits.
Edited serial transceiver sections.
In Table 2 added FFG Pb-Free packages.
06/17/05
02/10/06
1.4
1.5
Added note to Table 2 for SparseChevron pinouts.
•
•
•
•
Removed FCRAM-II support.
Added note 3 to Table 1.
Revised the CLB numbers for XC4VFX40 devices in Table 1.
Added stepping to order information example in Figure 1.
10/10/06
01/23/07
1.6
2.0
•
•
Changed maximum transceiver rate to 6.5 Gb/s.
Removed FF1760 package from Table 2.
Revision number jumped to 2.0 to correlate to data sheet (DS302) major revision.
•
•
Table 1: Corrected typo: XC4VFX40 number of slices = 18,624.
Table 2: Added column for FF676 package. Rewrote table footnotes.
DS112 (v3.1) August 30, 2010
www.xilinx.com
Product Specification
8
R
Virtex-4 Family Overview
Date
Version
Revision
03/12/07
2.1
Table 2: Corrected to remove FF676 package offerings in XC4VLX40, XC4VLX60,
XC4VSX25, XC4VSX35, and XC4VFX12 devices.
09/28/07
08/30/10
3.0
3.1
All Virtex-4 devices released to Production status. See DS302, Virtex-4 Data Sheet, for full
particulars. No changes in this document from previous revision.
See XCN09028, Product Discontinuation Notice Virtex-4 LX25 FPGA FF(G)676 Devices for
detailed product revisions. In Table 2, removed XC4VLX25 devices in the FF676/FFG676
package column.
DS112 (v3.1) August 30, 2010
www.xilinx.com
Product Specification
9
XC4VFX12-12FF668C 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| XC4VFX12-11FFG668C | XILINX | Field Programmable Gate Array, 1368 CLBs, 1181MHz, 12312-Cell, CMOS, PBGA668, LEAD FREE, F | 完全替代 |
|
XC4VFX12-12FF668C 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| XC4VFX12-12FF668CS1 | XILINX | Field Programmable Gate Array, 1181MHz, 12312-Cell, CMOS, PBGA668, | 获取价格 |
|
| XC4VFX12-12FF676C | XILINX | Field Programmable Gate Array, 12312-Cell, CMOS, PBGA676, | 获取价格 |
|
| XC4VFX12-12FFG676C | XILINX | Field Programmable Gate Array, 12312-Cell, CMOS, PBGA676, | 获取价格 |
|
| XC4VFX12-12SFG363CS1 | XILINX | Field Programmable Gate Array, 1181MHz, 12312-Cell, CMOS, PBGA363, | 获取价格 |
|
| XC4VFX140 | XILINX | Virtex-4⑩ Family / newest generation FPGA | 获取价格 |
|
| XC4VFX140-10FF1517C | XILINX | Field Programmable Gate Array, 15792 CLBs, 1028MHz, 142128-Cell, CMOS, PBGA1517, FBGA-1517 | 获取价格 |
|
| XC4VFX140-10FFG1517CS1 | XILINX | Field Programmable Gate Array, 1028MHz, 142128-Cell, CMOS, PBGA1517, | 获取价格 |
|
| XC4VFX140-11FF1517C | XILINX | Field Programmable Gate Array, 15792 CLBs, 1181MHz, 142128-Cell, CMOS, PBGA1517, FBGA-1517 | 获取价格 |
|
| XC4VFX140-11FF1517CS1 | XILINX | Field Programmable Gate Array, 1181MHz, 142128-Cell, CMOS, PBGA1517, | 获取价格 |
|
| XC4VFX140-11FFG1517C | XILINX | Field Programmable Gate Array, 15792 CLBs, 1181MHz, 142128-Cell, CMOS, PBGA1517, LEAD FREE, FBGA-1517 | 获取价格 |
|
XC4VFX12-12FF668C 相关文章
HARTING(浩亭)圆形连接器产品选型手册
- 2024-10-31
- 6
HYCON(宏康科技)产品选型手册
- 2024-10-31
- 6
GREEGOO整流二极管和晶闸管产品选型手册
- 2024-10-31
- 7
西门子豪掷106亿美元，战略收购工程软件巨头Altair
- 2024-10-31
- 8
