XC6VSX315T-1FF1156I [XILINX]
Field Programmable Gate Array, 1098MHz, 314880-Cell, CMOS, PBGA1156, FBGA-1156;
| 型号： | XC6VSX315T-1FF1156I |
| 厂家： | 
XILINX, INC |
| 描述： | Field Programmable Gate Array, 1098MHz, 314880-Cell, CMOS, PBGA1156, FBGA-1156 时钟 栅 可编程逻辑 |
| 文件： | 总65页 (文件大小：1429K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Virtex-6 FPGA Data Sheet:
DC and Switching Characteristics
DS152 (v3.6) March 18, 2014
Product Specification
Virtex-6 FPGA Electrical Characteristics
Virtex®-6 FPGAs are available in -3, -2, -1, and -1L speed grades, with -3 having the highest performance. Virtex-6 FPGA
DC and AC characteristics are specified in commercial, extended, industrial, and military temperature ranges. Unless noted,
the Virtex-6Q FPGA DC and AC characteristics are equivalent to the commercial specifications. Except for the operating
temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed
grade (that is, the timing characteristics of a -1 speed grade industrial device are the same as for a -1 speed grade
commercial device). However, only selected speed grades and/or devices are available in the extended, industrial, or military
temperature ranges.
All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters
included are common to popular designs and typical applications.
Available device and package combinations can be found at:
•
•
DS150: Virtex-6 Family Overview
DS155: Defense-Grade Virtex-6Q Family Overview
This Virtex-6 FPGA data sheet, part of an overall set of documentation on the Virtex-6 FPGAs, is available on the Xilinx
website at: www.xilinx.com/support/index.html/content/xilinx/en/supportNav/silicon_devices/fpga/virtex-6.html.
Virtex-6 FPGA DC Characteristics
(1)
Table 1: Absolute Maximum Ratings
Symbol
Description
Internal supply voltage relative to GND
Range
–0.5 to 1.1
–0.5 to 1.0
–0.5 to 3.0
–0.5 to 3.0
–0.5 to 3.0
–0.5 to 3.0
–0.5 to 3.0
–0.5 to VCCO + 0.5
–0.5 to VCCO + 0.5
–65 to 150
+220
Units
V
VCCINT
For -1L devices: Internal supply voltage relative to GND
Auxiliary supply voltage relative to GND
V
VCCAUX
VCCO
VBATT
VFS
V
Output drivers supply voltage relative to GND
Key memory battery backup supply
V
V
External voltage supply for eFUSE programming(2)
Input reference voltage
V
VREF
V
VIN
2.5V or below I/O input voltage relative to GND(4) (user and dedicated I/Os)
Voltage applied to 3-state 2.5V or below output(4) (user and dedicated I/Os)
Storage temperature (ambient)
V
(3)
VTS
TSTG
TSOL
Tj
V
°C
°C
°C
Maximum soldering temperature(5)
Maximum junction temperature(5)
+125
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
2. When not programming eFUSE, connect V to GND.
FS
3. 2.5V I/O absolute maximum limit applied to DC and AC signals.
4. For I/O operation, refer to UG361:Virtex-6 FPGA SelectIO Resources User Guide.
5. For soldering guidelines and thermal considerations, see UG365:Virtex-6 FPGA Packaging and Pinout Specification.
© 2009–2014 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Zynq, Artix, Kintex, Spartan, ISE, Vivado and other designated brands included herein are trademarks of Xilinx in the
United States and other countries. All other trademarks are the property of their respective owners.
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
1
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 2: Recommended Operating Conditions
Symbol
VCCINT
VCCAUX
Description
Min
0.95
0.87
Max
1.05
0.93
Units
Internal supply voltage relative to GND for all devices except -1L devices.
V
V
For -1L commercial temperature range devices: internal supply voltage relative
to GND, Tj = 0°C to +85°C
For -1L industrial temperature range devices: internal supply voltage relative to GND,
Tj = –40°C to +100°C
0.91
0.97
V
Auxiliary supply voltage relative to GND
Supply voltage relative to GND
2.375
1.14
2.625
2.625
2.625
V
V
(1)(2)(3)
VCCO
2.5V supply voltage relative to GND
2.5V and below supply voltage relative to GND
GND – 0.20
V
VIN
GND – 0.20 VCCO + 0.2
V
Maximum current through any pin in a powered or unpowered bank when forward
biasing the clamp diode.
–
10
mA
(5)
IIN
(6)
VBATT
Battery voltage relative to GND
1.0
2.375
0
2.5
2.625
85
V
(7)
VFS
External voltage supply for eFUSE programming
V
Junction temperature operating range for commercial (C) temperature devices
Junction temperature operating range for extended (E) temperature devices
Junction temperature operating range for industrial (I) temperature devices
Junction temperature operating range for military (M) temperature devices
°C
°C
°C
°C
0
100
100
125
Tj
–40
–55
Notes:
1. Configuration data is retained even if V
drops to 0V.
CCO
2. Includes V
of 1.2V, 1.5V, 1.8V, and 2.5V.
CCO
3. The configuration supply voltage V
4. All voltages are relative to ground.
is also known as V
.
CC_CONFIG
CCO_0
5. A total of 100 mA per bank should not be exceeded.
6. is required only when using bitstream encryption. If battery is not used, connect V
V
to either ground or V
.
BATT
BATT
CCAUX
7. During eFUSE programming, V must be within the recommended operating range and Tj = +15°C to +85°C. Otherwise, V can be
FS
FS
connected to GND.
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
2
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
(1)(2)
Table 3: DC Characteristics Over Recommended Operating Conditions
Symbol Description
VDRINT Data retention VCCINT voltage (below which configuration data might be lost)
Min
0.75
2.0
–
Typ
Max
–
Units
V
–
VDRI
IREF
IL
Data retention VCCAUX voltage (below which configuration data might be lost)
VREF leakage current per pin
–
–
V
–
10
10
8
µA
µA
pF
µA
µA
µA
µA
µA
nA
n
Input or output leakage current per pin (sample-tested)
Die input capacitance at the pad
–
–
(3)
CIN
–
–
Pad pull-up (when selected) @ VIN = 0V, VCCO = 2.5V
Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.8V
Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.5V
Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.2V
Pad pull-down (when selected) @ VIN = 2.5V
Battery supply current
20
8
–
80
40
30
20
80
150
–
–
IRPU
5
–
1
–
IRPD
3
–
IBATT
–
–
1.0002
5
n
r
Temperature diode ideality factor
–
Series resistance
–
–
Ω
Notes:
1. Typical values are specified at nominal voltage, 25°C.
2. Maximum value specified for worst case process at 25°C.
3. This measurement represents the die capacitance at the pad, not including the package.
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
3
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Important Note
Typical values for quiescent supply current are specified at nominal voltage, 85°C junction temperatures (T). Xilinx
j
recommends analyzing static power consumption at T = 85°C because the majority of designs operate near the high end of
j
the commercial temperature range. Quiescent supply current is specified by speed grade for Virtex-6 devices. Use the Xilinx
Power Estimator (XPE) spreadsheet tool (download at http://www.xilinx.com/power) to calculate static power consumption
for conditions other than those specified in Table 4.
Table 4: Typical Quiescent Supply Current
Speed and Temperature Grade
Symbol
Description
Device
Units
(2)
(1)
-3 (C)
927
-2 (C, E, & I) -1 (C & I) -1 (I & M)
-1L (C) -1L (I)
ICCINTQ Quiescent VCCINT
supply current
XC6VLX75T
927
927
1563
2059
2478
3001
4515
5094
3476
5227
2906
2746
4160
5207
N/A
N/A
N/A
656
1102
1441
1733
2092
3147
3471
2409
3622
N/A
741
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
XC6VLX130T
XC6VLX195T
XC6VLX240T
XC6VLX365T
XC6VLX550T(3)
XC6VLX760(3)
XC6VSX315T
XC6VSX475T(3)
XC6VHX250T
XC6VHX255T
XC6VHX380T(4)
XC6VHX565T(5)
XQ6VLX130T
XQ6VLX240T
XQ6VLX550T(7)
XQ6VSX315T
XQ6VSX475T(7)
1563
2059
2478
3001
N/A
1563
2059
2478
3001
4515
5094
3476
5227
2906
2746
4160
5207
1563
2478
N/A
1245
1628
1957
2363
3555
3921
2721
4091
N/A
N/A
N/A
N/A
N/A
N/A
N/A
3476
N/A
N/A
N/A
2906
2746
4160
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1563
2478
4515
3476
5227
N/A
1245
1957
3555
2721
4091
N/A
N/A
N/A
N/A
N/A
N/A
N/A
3476
N/A
N/A
N/A
N/A
N/A
N/A
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
4
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 4: Typical Quiescent Supply Current (Cont’d)
Speed and Temperature Grade
Units
Symbol
Description
Device
(2)
(1)
-3 (C)
1
-2 (C, E, & I) -1 (C & I) -1 (I & M)
-1L (C) -1L (I)
ICCOQ
Quiescent VCCO
supply current
XC6VLX75T
1
1
1
1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1
1
1
1
1
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
XC6VLX130T
XC6VLX195T
XC6VLX240T
XC6VLX365T
XC6VLX550T(3)
XC6VLX760(3)
XC6VSX315T
XC6VSX475T(3)
XC6VHX250T
XC6VHX255T
XC6VHX380T(4)
XC6VHX565T(5)
XQ6VLX130T
XQ6VLX240T
XQ6VLX550T(7)
XQ6VSX315T
XQ6VSX475T(7)
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
N/A
N/A
2
3
3
3
3
3
3
3
3
2
2
2
2
N/A
1
2
2
2
2
1
1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1
1
1
1
2
2
2
N/A
N/A
N/A
N/A
N/A
N/A
2
2
1
N/A
N/A
N/A
N/A
N/A
2
2
2
N/A
2
3
3
2
2
N/A
2
2
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
5
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 4: Typical Quiescent Supply Current (Cont’d)
Speed and Temperature Grade
Units
Symbol
Description
Device
(2)
(1)
-3 (C)
45
-2 (C, E, & I) -1 (C & I) -1 (I & M)
-1L (C) -1L (I)
ICCAUXQ Quiescent VCCAUX
supply current
XC6VLX75T
45
45
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
75
45
45
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
XC6VLX130T
XC6VLX195T
XC6VLX240T
XC6VLX365T
XC6VLX550T(3)
XC6VLX760(3)
XC6VSX315T
XC6VSX475T(3)
XC6VHX250T
XC6VHX255T
XC6VHX380T(4)
XC6VHX565T(5)
XQ6VLX130T(6)
XQ6VLX240T(6)
XQ6VLX550T(7)
XQ6VSX315T(6)
XQ6VSX475T(7)
75
75
75
75
75
113
135
191
N/A
N/A
186
N/A
152
152
227
N/A
N/A
N/A
N/A
N/A
N/A
113
135
191
286
387
186
279
152
152
227
315
75
113
135
191
286
387
186
279
152
152
227
315
N/A
N/A
N/A
N/A
N/A
113
135
191
286
387
186
279
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
113
135
191
286
387
186
279
N/A
N/A
N/A
N/A
75
135
N/A
186
N/A
135
286
186
279
135
286
186
279
Notes:
1. Typical values are specified at nominal voltage, 85°C junction temperatures (T ). -1 and -2 industrial (I) grade devices have the same typical
j
values as commercial (C) grade devices at 85°C, but higher values at 100°C. Use the XPE tool to calculate 100°C values. -1L industrial
temperature range devices have the values specified in this column.
2. Use the XPE tool to calculate 125°C values for -1M temperature range devices.
3. The -2E extended temperature range (T = 0°C to +100°C) is only available in these devices. The -2I temperature range (T = –40°C to
j
j
+100°C) is available for all other devices except the XC6VHX565T.
4. The XC6VHX380T is available with both -2E and -2I temperature ranges.
5. The XC6VHX565T is only available in the following temperature ranges: -1C, -1I, -2C, and -2E.
6. The XQ6VLX130T, XQ6VLX240T, and XQ6VSX315T are available in -2I, -1I, -1M, and -1LI temperature ranges.
7. The XQ6VLX550T and the XQ6VSX475T are only available in -1I and -1LI temperature ranges.
8. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and
floating.
9. If DCI or differential signaling is used, more accurate quiescent current estimates can be obtained by using the XPE or XPower Analyzer
(XPA) tools.
Power-On Power Supply Requirements
Xilinx FPGAs require a certain amount of supply current during power-on to insure proper device initialization. The actual
current consumed depends on the power-on sequence and ramp rate of the power supply.
The recommended power-on sequence for Virtex-6 devices is V
, V
, and V
to meet the power-up current
CCO
CCINT CCAUX
requirements listed in Table 5. V
can be powered up or down at any time, but power up current specifications can vary
CCINT
from Table 5. The device will have no physical damage or reliability concerns if V
be followed.
, V
, and V
sequence cannot
CCINT CCAUX
CCO
If the recommended power-up sequence cannot be followed and the I/Os must remain 3-stated throughout configuration,
then V must be powered prior to V or V and V must be powered by the same supply. Similarly, for power-
CCAUX
CCO
CCAUX
CCO
down, the reverse V
and V
sequence is recommended if the I/Os are to remain 3-stated.
CCAUX
CCO
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
6
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
The GTH transceiver supplies must be powered using a MGTHAVCC, MGTHAVCCRX, MGTHAVCCPLL, and MGTHAVTT
sequence. There are no sequencing requirement for these supplies with respect to the other FPGA supply voltages. For
more detail see Table 27: GTH Transceiver Power Supply Sequencing. There are no sequencing requirements for the GTX
transceivers power supplies.
Table 5 shows the minimum current, in addition to I
, that are required by Virtex-6 devices for proper power-on and
CCQ
configuration. If the current minimums shown in Table 4 and Table 5 are met, the device powers on after all three supplies
have passed through their power-on reset threshold voltages. The FPGA must be configured after applying V
, V
,
CCINT CCAUX
and V
for the appropriate configuration banks. Once initialized and configured, use the XPE tools to estimate current
CCO
drain on these supplies.
Table 5: Power-On Current for Virtex-6 Devices
ICCINTMIN
ICCAUXMIN
Typ(1)
ICCOMIN
Typ(1)
Device
Units
Typ(1)
XC6VLX75T
See ICCINTQ in Table 4
See ICCINTQ in Table 4
See ICCINTQ in Table 4
See ICCINTQ in Table 4
See ICCINTQ in Table 4
See ICCINTQ in Table 4
See ICCINTQ in Table 4
See ICCINTQ in Table 4
See ICCINTQ in Table 4
See ICCINTQ in Table 4
See ICCINTQ in Table 4
See ICCINTQ in Table 4
See ICCINTQ in Table 4
See ICCINTQ in Table 4
See ICCINTQ in Table 4
See ICCINTQ in Table 4
See ICCINTQ in Table 4
See ICCINTQ in Table 4
ICCAUXQ + 10
ICCAUXQ + 10
ICCAUXQ + 40
ICCAUXQ + 40
ICCAUXQ + 40
ICCAUXQ + 40
ICCAUXQ + 40
ICCAUXQ + 40
ICCAUXQ + 50
ICCAUXQ + 40
ICCAUXQ + 40
ICCAUXQ + 40
ICCAUXQ + 40
ICCAUXQ + 100
ICCAUXQ + 100
ICCAUXQ + 100
ICCAUXQ + 100
ICCAUXQ + 100
ICCOQ + 30 mA per bank
ICCOQ + 30 mA per bank
ICCOQ + 30 mA per bank
ICCOQ + 30 mA per bank
ICCOQ + 30 mA per bank
ICCOQ + 30 mA per bank
ICCOQ + 30 mA per bank
ICCOQ + 30 mA per bank
ICCOQ + 30 mA per bank
ICCOQ + 30 mA per bank
ICCOQ + 30 mA per bank
ICCOQ + 30 mA per bank
ICCOQ + 30 mA per bank
ICCOQ + 30 mA per bank
ICCOQ + 30 mA per bank
ICCOQ + 30 mA per bank
ICCOQ + 40 mA per bank
ICCOQ + 40 mA per bank
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
XC6VLX130T
XC6VLX195T
XC6VLX240T
XC6VLX365T
XC6VLX550T
XC6VLX760
XC6VSX315T
XC6VSX475T
XC6VHX250T
XC6VHX255T
XC6VHX380T
XC6VHX565T
XQ6VLX130T
XQ6VLX240T
XQ6VLX550T
XQ6VSX315T
XQ6VSX475T
Notes:
1. Typical values are specified at nominal voltage, 25°C.
2. Use the Xilinx Power Estimator (XPE) spreadsheet tool (download at http://www.xilinx.com/power) to calculate maximum power-on currents.
Table 6: Power Supply Ramp Time
Symbol
VCCINT
Description
Internal supply voltage relative to GND
Ramp Time
0.20 to 50.0
0.20 to 50.0
0.20 to 50.0
Units
ms
VCCO
Output drivers supply voltage relative to GND
Auxiliary supply voltage relative to GND
ms
VCCAUX
ms
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
7
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
SelectIO™ DC Input and Output Levels
Values for V and V are recommended input voltages. Values for I and I are guaranteed over the recommended
IL
IH
OL
OH
operating conditions at the V and V test points. Only selected standards are tested. These are chosen to ensure that
OL
OH
all standards meet their specifications. The selected standards are tested at a minimum V
with the respective V and
CCO
OL
V
voltage levels shown. Other standards are sample tested.
OH
Table 7: SelectIO DC Input and Output Levels
VIL
VIH
VOL
V, Max
0.4
VOH
IOL
IOH
mA
I/O Standard
V, Min
V, Max
V, Min
V, Max
V, Min
mA
LVCMOS25,
LVDCI25
–0.3
0.7
1.7
VCCO + 0.3
VCCO – 0.4
Note(3) Note(3)
Note(4) Note(4)
Note(4) Note(4)
Note(5) Note(5)
LVCMOS18,
LVDCI18
–0.3
–0.3
35% VCCO
35% VCCO
35% VCCO
65% VCCO
65% VCCO
VCCO + 0.3
VCCO + 0.3
0.45
VCCO – 0.45
75% VCCO
LVCMOS15,
LVDCI15
25% VCCO
LVCMOS12
HSTL I_12
HSTL I(2)
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
65% VCCO
VREF + 0.1
VREF + 0.1
VREF + 0.1
VREF + 0.1
VCCO + 0.3
VCCO + 0.3
VCCO + 0.3
VCCO + 0.3
VCCO + 0.3
25% VCCO
75% VCCO
75% VCCO
VCCO – 0.4
VCCO – 0.4
VCCO – 0.4
–
V
REF – 0.1
25% VCCO
6.3
8
–6.3
–8
VREF – 0.1
VREF – 0.1
VREF – 0.1
0.4
HSTL II(2)
0.4
16
24
–
–16
–8
HSTL III(2)
DIFF HSTL I(2)
DIFF HSTL II(2)
SSTL2 I
0.4
50% VCCO – 0.1 50% VCCO + 0.1 VCCO + 0.3
50% VCCO – 0.1 50% VCCO + 0.1 VCCO + 0.3
–
–
–
–
–
–
VREF – 0.15
VREF + 0.15
VREF + 0.15
VCCO + 0.3
VCCO + 0.3
VTT – 0.61
VTT – 0.81
–
VTT + 0.61
VTT + 0.81
–
8.1
16.2
–
–8.1
–16.2
–
SSTL2 II
VREF – 0.15
DIFF SSTL2 I
50%
50%
VCCO + 0.3
VCCO – 0.15
VCCO + 0.15
DIFF SSTL2 II
–0.3
50%
VCCO – 0.15
50%
VCCO + 0.15
VCCO + 0.3
–
–
–
–
SSTL18 I
–0.3
–0.3
–0.3
VREF – 0.125
VREF – 0.125
VREF + 0.125
VREF + 0.125
VCCO + 0.3
VCCO + 0.3
VTT – 0.47
VTT – 0.60
–
VTT + 0.47
VTT + 0.60
–
6.7
13.4
–
–6.7
–13.4
–
SSTL18 II
DIFF SSTL18 I
50%
VCCO – 0.125
50%
VCCO + 0.125
VCCO + 0.3
DIFF SSTL18 II
–0.3
50%
VCCO – 0.125
50%
VCCO + 0.125
VCCO + 0.3
VCCO + 0.3
–
–
–
–
SSTL15
–0.3
–0.3
VREF – 0.1
VREF + 0.1
VTT – 0.175
–
VTT + 0.175
–
14.3
–
–14.3
–
DIFF SSTL15
50% VCCO – 0.1 50% VCCO + 0.1 VCCO + 0.3
Notes:
1. Tested according to relevant specifications.
2. Applies to both 1.5V and 1.8V HSTL.
3. Using drive strengths of 2, 4, 6, 8, 12, 16, or 24 mA.
4. Using drive strengths of 2, 4, 6, 8, 12, or 16 mA.
5. Supported drive strengths of 2, 4, 6, or 8 mA.
6. For detailed interface specific DC voltage levels, see UG361:Virtex-6 FPGA SelectIO Resources User Guide.
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
8
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
HT DC Specifications (HT_25)
Table 8: HT DC Specifications
Symbol
VCCO
VOD
DC Parameter
Supply Voltage
Conditions
Min
2.38
480
480
–15
440
–15
200
–15
440
–15
Typ
2.5
600
600
–
Max
2.63
885
930
15
Units
V
Differential Output Voltage for XC devices RT = 100 Ω across Q and Q signals
Differential Output Voltage for XQ devices
mV
mV
mV
mV
mV
mV
mV
mV
mV
Δ VOD
Change in VOD Magnitude
VOCM
Output Common Mode Voltage
RT = 100 Ω across Q and Q signals
600
–
760
15
Δ VOCM Change in VOCM Magnitude
VID
Δ VID
VICM
Input Differential Voltage
Change in VID Magnitude
Input Common Mode Voltage
Change in VICM Magnitude
600
–
1000
15
600
–
780
15
Δ VICM
LVDS DC Specifications (LVDS_25)
Table 9: LVDS DC Specifications
Symbol
VCCO
VOH
DC Parameter
Conditions
Min
Typ
Max
Units
V
Supply Voltage
2.38
–
2.5
–
2.63
1.675
–
Output High Voltage for Q and Q
Output Low Voltage for Q and Q
RT = 100 Ω across Q and Q signals
RT = 100 Ω across Q and Q signals
RT = 100 Ω across Q and Q signals
V
VOL
0.825
247
–
V
VODIFF
Differential Output Voltage (Q – Q),
Q = High (Q – Q), Q = High
350
600
mV
VOCM
Output Common-Mode Voltage for XC devices RT = 100 Ω across Q and Q signals
1.075
1.000
100
1.250
1.250
350
1.425
1.425
600
V
V
Output Common-Mode Voltage for XQ devices
VIDIFF
VICM
Differential Input Voltage (Q – Q),
Q = High (Q – Q), Q = High
mV
Input Common-Mode Voltage
0.3
1.2
2.2
V
Extended LVDS DC Specifications (LVDSEXT_25)
Table 10: Extended LVDS DC Specifications
Symbol
VCCO
VOH
DC Parameter
Conditions
Min
2.38
–
Typ
2.5
–
Max
2.63
1.785
–
Units
V
Supply Voltage
Output High Voltage for Q and Q
Output Low Voltage for Q and Q
RT = 100 Ω across Q and Q signals
RT = 100 Ω across Q and Q signals
RT = 100 Ω across Q and Q signals
V
VOL
0.715
350
–
V
VODIFF
Differential Output Voltage (Q – Q),
Q = High (Q – Q), Q = High
for XC devices
–
840
mV
Differential Output Voltage (Q – Q),
Q = High (Q – Q), Q = High
for XQ devices
350
–
850
mV
VOCM
Output Common-Mode Voltage for XC devices RT = 100 Ω across Q and Q signals
1.075
1.000
100
1.250
1.250
–
1.425
1.425
1000
V
V
Output Common-Mode Voltage for XQ devices
VIDIFF
VICM
Differential Input Voltage (Q – Q),
Q = High (Q – Q), Q = High
Common-mode input
voltage = 1.25V
mV
Input Common-Mode Voltage
Differential input voltage = 350 mV
0.3
1.2
2.2
V
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
9
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
LVPECL DC Specifications (LVPECL_25)
These values are valid when driving a 100Ω differential load only, i.e., a 100Ω resistor between the two receiver pins. The
levels are 200 mV below standard LVPECL levels and are compatible with devices tolerant of lower common-mode
V
OH
ranges. Table 11 summarizes the DC output specifications of LVPECL. For more information on using LVPECL, see UG361:
Virtex-6 FPGA SelectIO Resources User Guide.
Table 11: LVPECL DC Specifications
Symbol
VOH
DC Parameter
Output High Voltage
Min
VCC – 1.025
VCC – 1.81
0.6
Typ
1.545
0.795
–
Max
VCC – 0.88
VCC – 1.62
2.2
Units
V
V
V
V
VOL
Output Low Voltage
VICM
VIDIFF
Input Common-Mode Voltage
Differential Input Voltage(1)(2)
0.100
–
1.5
Notes:
1. Recommended input maximum voltage not to exceed V
+ 0.2V.
CCAUX
2. Recommended input minimum voltage not to go below –0.5V.
eFUSE Read Endurance
Table 12 lists the maximum number of read cycle operations expected. For more information, see UG360:Virtex-6 FPGA
Configuration User Guide.
Table 12: eFUSE Read Endurance
Speed Grade
Symbol
Description
Units
-3
-2
-1
-1L
DNA_CYCLES
Number of DNA_PORT READ operations or JTAG ISC_DNA read
command operations. Unaffected by SHIFT operations.
Read
Cycles
30,000,000
30,000,000
AES_CYCLES
Number of JTAG FUSE_KEY or FUSE_CNTL read command
operations. Unaffected by SHIFT operations.
Read
Cycles
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
10
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
GTX Transceiver Specifications
GTX Transceiver DC Characteristics
(1)
Table 13: Absolute Maximum Ratings for GTX Transceivers
Symbol
Description
Min
Max
Units
Analog supply voltage for the GTX transmitter and receiver circuits relative to
GND
–0.5
1.1
V
MGTAVCC
Analog supply voltage for the GTX transmitter and receiver termination circuits
relative to GND
–0.5
–0.5
1.32
1.32
V
V
MGTAVTT
Analog supply voltage for the resistor calibration circuit of the GTX transceiver
column
MGTAVTTRCAL
VIN
Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage
Reference clock absolute input voltage
–0.5
–0.5
1.32
1.32
V
V
VMGTREFCLK
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
(1)(2)
Table 14: Recommended Operating Conditions for GTX Transceivers
Speed
Grade
PLL
Frequency
Symbol
Description
Min
Typ
Max
Units
-3, -2(3)
-3, -2(3)
-1
> 2.7 GHz
≤ 2.7 GHz
≤ 2.7 GHz
≤ 2.7 GHz
1.0
1.03
1.0
1.06
1.06
1.06
1.05
V
V
V
V
0.95
0.95
0.95
Analog supply voltage for the GTX transmitter
and receiver circuits relative to GND
MGTAVCC
1.0
-1L
1.0
Analog supply voltage for the GTX transmitter
and receiver termination circuits relative to GND
MGTAVTT
All
All
–
–
1.14
1.14
1.2
1.2
1.26
1.26
V
V
Analog supply voltage for the resistor calibration
circuit of the GTX transceiver column
MGTAVTTRCAL
Notes:
1. Each voltage listed requires the filter circuit described in UG366:Virtex-6 FPGA GTX Transceivers User Guide.
2. Voltages are specified for the temperature range of T = –40°C to +100°C for all XC devices and T = –55°C to +125°C for the XQ devices
j
j
3. If a GTX Quad contains transceivers operating with a mixture of PLL frequencies above and below 2.7 GHz, the MGTAVCC voltage supply
must be in the range of 1.0V to 1.06V.
(1)(2)
Table 15: GTX Transceiver Supply Current (per Lane)
Symbol
IMGTAVTT
Description
Typ
55.9
56.1
Max
Units
mA
mA
Ω
MGTAVTT supply current for one GTX transceiver
MGTAVCC supply current for one GTX transceiver
Precision reference resistor for internal calibration termination
Note 2
IMGTAVCC
MGTRREF
100.0 1% tolerance
Notes:
1. Typical values are specified at nominal voltage, 25°C, with a 3.125 Gb/s line rate.
2. Values for currents of other transceiver configurations and conditions can be obtained by using the Xilinx Power Estimator (XPE) or XPower
Analyzer (XPA) tools.
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
11
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
(1)(2)(3)
Table 16: GTX Transceiver Quiescent Supply Current (per Lane)
Symbol
IMGTAVTTQ
IMGTAVCCQ
Description
Typ(4)
0.9
Max
Units
mA
Quiescent MGTAVTT supply current for one GTX transceiver
Quiescent MGTAVCC supply current for one GTX transceiver
Note 2
3.5
mA
Notes:
1. Device powered and unconfigured.
2. Currents for conditions other than values specified in this table can be obtained by using the XPE or XPA tools.
3. GTX transceiver quiescent supply current for an entire device can be calculated by multiplying the values in this table by the number of
available GTX transceivers.
4. Typical values are specified at nominal voltage, 25°C.
GTX Transceiver DC Input and Output Levels
Table 17 summarizes the DC output specifications of the GTX transceivers in Virtex-6 FPGAs. Consult UG366:Virtex-6
FPGA GTX Transceivers User Guide for further details.
Table 17: GTX Transceiver DC Specifications
Symbol
DC Parameter
Conditions
Min
125
Typ
–
Max
2000
Units
mV
Differential peak-to-peak input External AC coupled ≤ 4.25 Gb/s
DVPPIN
voltage
External AC coupled > 4.25 Gb/s
175
–
2000
mV
Absolute input voltage
DC coupled
MGTAVTT = 1.2V
–400
–
MGTAVTT
mV
VIN
Common mode input voltage
DC coupled
MGTAVTT = 1.2V
–
–
2/3 MGTAVTT
–
–
mV
mV
mV
VCMIN
Differential peak-to-peak output Transmitter output swing is set to
1000
DVPPOUT
VCMOUTDC
voltage(1)
maximum setting
DC common mode output
voltage.
Equation based
MGTAVTT – DVPPOUT/4
RIN
Differential input resistance
Differential output resistance
80
80
–
100
100
2
130
120
8
Ω
Ω
ROUT
TOSKEW
CEXT
Transmitter output pair (TXP and TXN) intra-pair skew
Recommended external AC coupling capacitor(2)
ps
nF
–
100
–
Notes:
1. The output swing and preemphasis levels are programmable using the attributes discussed in UG366:Virtex-6 FPGA GTX Transceivers User
Guide and can result in values lower than reported in this table.
2. Other values can be used as appropriate to conform to specific protocols and standards.
X-Ref Target - Figure 1
+V
0
P
N
Single-Ended
Voltage
ds152_01_121509
Figure 1: Single-Ended Peak-to-Peak Voltage
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
12
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
X-Ref Target - Figure 2
+V
0
Differential
Voltage
P–N
–V
ds152_02_121509
Figure 2: Differential Peak-to-Peak Voltage
Table 18 summarizes the DC specifications of the clock input of the GTX transceiver. Consult UG366:Virtex-6 FPGA GTX
Transceivers User Guide for further details.
Table 18: GTX Transceiver Clock DC Input Level Specification
Symbol
VIDIFF
DC Parameter
Differential peak-to-peak input voltage
Min
210
90
Typ
800
100
100
Max
2000
130
–
Units
mV
Ω
RIN
Differential input resistance
CEXT
Required external AC coupling capacitor(1)
–
nF
Notes:
1. Other values can be used as appropriate to conform to specific protocols and standards.
GTX Transceiver Switching Characteristics
Consult UG366:Virtex-6 FPGA GTX Transceivers User Guide for further information.
Table 19: GTX Transceiver Performance
Speed Grade
Symbol
Description
Units
-3
6.6
-2
6.6
-1
-1L
5.0
2.7
1.2
FGTXMAX
FGPLLMAX
FGPLLMIN
Maximum GTX transceiver data rate
Maximum PLL frequency
5.0
2.7
1.2
Gb/s
GHz
GHz
3.3(1)
1.2
3.3(1)
1.2
Minimum PLL frequency
Notes:
1. See Table 14 for MGTAVCC requirements when PLL frequency is greater than 2.7 GHz.
Table 20: GTX Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics
Speed Grade
Symbol
Description
Units
-3
-2
-1
-1L
FGTXDRPCLK
GTXDRPCLK maximum frequency
150
150
125
100
MHz
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
13
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 21: GTX Transceiver Reference Clock Switching Characteristics
All Speed Grades
Symbol
Description
Conditions
Units
Min
62.5
–
Typ
–
Max
650
–
FGCLK
TRCLK
TFCLK
TDCREF
Reference clock frequency range
Reference clock rise time
Reference clock fall time
MHz
ps
20% – 80%
200
200
50
–
80% – 20%
–
–
ps
Reference clock duty cycle
Transceiver PLL only
45
–
55
1
%
Clock recovery frequency acquisition
time
ms
TLOCK
Initial PLL lock
Lock to data after PLL has locked
to the reference clock
–
–
200
µs
TPHASE
Clock recovery phase acquisition time
X-Ref Target - Figure 3
TRCLK
80%
20%
TFCLK
ds152_05_042109
Figure 3: Reference Clock Timing Parameters
(1)
Table 22: GTX Transceiver User Clock Switching Characteristics
Speed Grade
Symbol
Description
Conditions
Units
-3
-2
-1
-1L
250
250
250
250
250
250
250
125
250
250
250
125
Internal 20-bit data path
Internal 16-bit data path
Internal 20-bit data path
Internal 16-bit data path
330
330
250
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
FTXOUT
TXOUTCLK maximum frequency
412.5
330
412.5
330
312.5
250
FRXREC
TRX
RXRECCLK maximum frequency
RXUSRCLK maximum frequency
412.5
412.5(2)
376
412.5
412.5(2)
376
312.5
312.5
312.5
312.5
156.25
312.5
312.5
312.5
156.25
1 byte interface
TRX2
RXUSRCLK2 maximum frequency 2 byte interface
4 byte interface
406.25
206.25
412.5(3)
376
406.25
206.25
412.5(3)
376
TTX
TXUSRCLK maximum frequency
1 byte interface
TTX2
TXUSRCLK2 maximum frequency 2 byte interface
4 byte interface
406.25
206.25
406.25
206.25
Notes:
1. Clocking must be implemented as described in UG366:Virtex-6 FPGA GTX Transceivers User Guide.
2. 406.25 MHz when the RX elastic buffer is bypassed.
3. 406.25 MHz when the TX buffer is bypassed.
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
14
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 23: GTX Transceiver Transmitter Switching Characteristics
Symbol
Description
Serial data rate range
Condition
Min
Typ
–
Max
FGTXMAX
–
Units
Gb/s
ps
ps
ps
mV
ns
UI
FGTXTX
TRTX
0.480
–
TX Rise time
20%–80%
80%–20%
120
120
–
TFTX
TX Fall time
–
–
TLLSKEW
TX lane-to-lane skew(1)
Electrical idle amplitude
Electrical idle transition time
Total Jitter(2)(3)
Deterministic Jitter(2)(3)
Total Jitter(2)(3)
Deterministic Jitter(2)(3)
Total Jitter(2)(3)
Deterministic Jitter(2)(3)
Total Jitter(2)(3)
Deterministic Jitter(2)(3)
Total Jitter(2)(3)
Deterministic Jitter(2)(3)
Total Jitter(2)(3)
Deterministic Jitter(2)(3)
Total Jitter(2)(3)
Deterministic Jitter(2)(3)
Total Jitter(2)(3)
–
350
15
VTXOOBVDPP
TTXOOBTRANSITION
TJ6.5
–
–
–
–
75
–
–
0.33
0.17
0.33
0.15
0.33
0.14
0.34
0.16
0.2
6.5 Gb/s
5.0 Gb/s
DJ6.5
–
–
UI
TJ5.0
–
–
UI
DJ5.0
–
–
UI
TJ4.25
–
–
UI
4.25 Gb/s
3.75 Gb/s
3.125 Gb/s
3.125 Gb/s(4)
2.5 Gb/s(5)
1.25 Gb/s(6)
600 Mb/s
DJ4.25
–
–
UI
TJ3.75
–
–
UI
DJ3.75
–
–
UI
TJ3.125
DJ3.125
TJ3.125L
DJ3.125L
TJ2.5
–
–
UI
–
–
0.1
UI
–
–
0.35
0.16
0.20
0.08
0.15
0.06
0.1
UI
–
–
UI
–
–
UI
DJ2.5
–
–
UI
TJ1.25
–
–
UI
DJ1.25
Deterministic Jitter(2)(3)
Total Jitter(2)(3)
Deterministic Jitter(2)(3)
Total Jitter(2)(3)
–
–
UI
TJ600
–
–
UI
DJ600
–
–
0.03
0.1
UI
TJ480
–
–
UI
480 Mb/s
DJ480
Deterministic Jitter(2)(3)
–
–
0.03
UI
Notes:
1. Using same REFCLK input with TXENPMAPHASEALIGN enabled for up to 12 consecutive transmitters (three fully populated GTX Quads).
2. Using PLL_DIVSEL_FB = 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.
-12
3. All jitter values are based on a bit-error ratio of 1e
4. PLL frequency at 1.5625 GHz and OUTDIV = 1.
5. PLL frequency at 2.5 GHz and OUTDIV = 2.
6. PLL frequency at 2.5 GHz and OUTDIV = 4.
.
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
15
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 24: GTX Transceiver Receiver Switching Characteristics
Symbol Description
RX oversampler not enabled
RX oversampler enabled
Min
0.600
0.480
–
Typ
–
Max
FGTXMAX
0.600
–
Units
Gb/s
Gb/s
ns
FGTXRX
Serial data rate
–
TRXELECIDLE
RXOOBVDPP
Time for RXELECIDLE to respond to loss or restoration of data
OOB detect threshold peak-to-peak
75
–
60
150
mV
Receiver spread-spectrum
Modulated @ 33 KHz
tracking(1)
–5000
–
0
ppm
RXSST
RXRL
Run length (CID)
Internal AC capacitor bypassed
CDR 2nd-order loop disabled
CDR 2nd-order loop enabled
–
–
–
–
512
200
UI
–200
–2000
ppm
ppm
Data/REFCLK PPM offset
tolerance
RXPPMTOL
2000
SJ Jitter Tolerance(2)
JT_SJ6.5
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
6.5 Gb/s
0.44
0.44
0.44
0.44
0.45
0.45
0.5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
JT_SJ5.0
5.0 Gb/s
JT_SJ4.25
4.25 Gb/s
3.75 Gb/s
3.125 Gb/s
3.125 Gb/s(4)
2.5 Gb/s(5)
1.25 Gb/s(6)
600 Mb/s
JT_SJ3.75
JT_SJ3.125
JT_SJ3.125L
JT_SJ2.5
JT_SJ1.25
0.5
JT_SJ600
0.4
JT_SJ480
480 Mb/s
0.4
SJ Jitter Tolerance with Stressed Eye(2)
3.125 Gb/s
5.0 Gb/s
0.70
0.70
0.1
–
–
–
–
–
–
–
–
UI
UI
UI
UI
JT_TJSE3.125
Total Jitter with Stressed Eye(7)
3.125 Gb/s
5.0 Gb/s
Sinusoidal Jitter with Stressed
Eye(7)
JT_SJSE3.125
0.1
Notes:
1. Using PLL_RXDIVSEL_OUT = 1, 2, and 4.
2. All jitter values are based on a bit error ratio of 1e
–12
.
3. The frequency of the injected sinusoidal jitter is 80 MHz.
4. PLL frequency at 1.5625 GHz and OUTDIV = 1.
5. PLL frequency at 2.5 GHz and OUTDIV = 2.
6. PLL frequency at 2.5 GHz and OUTDIV = 4.
7. Composite jitter with RX equalizer enabled. DFE disabled.
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
16
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
GTH Transceiver Specifications
GTH Transceiver DC Characteristics
(1)
Table 25: Absolute Maximum Ratings for GTH Transceivers
Symbol
Description
Min
Max
Units
Analog supply voltage for the GTH transmitter, receiver, and common analog
circuits
–0.5
1.125
V
MGTHAVCC
MGTHAVCCRX
MGTHAVTT
Analog supply voltage for the GTH receiver circuits and common analog circuits
Analog supply voltage for the GTH transmitter termination circuits
–0.5
–0.5
–0.5
–0.5
–0.5
1.125
1.32
V
V
V
V
V
MGTHAVCCPLL Analog supply voltage for the GTH receiver and PLL circuits
1.935
1.125
1.935
VIN
Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage
Reference clock absolute input voltage
VMGTREFCLK
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
(1)(2)
Table 26: Recommended Operating Conditions for GTH Transceivers
Symbol
Description
Min
Typ
Max
Units
Analog supply voltage for the GTH transmitter, receiver, and common analog
circuits
1.075
1.1
1.125
V
MGTHAVCC
Analog supply voltage for the GTH receiver circuits and common analog
circuits
1.075
1.1
1.125
V
MGTHAVCCRX
MGTHAVTT
Analog supply voltage for the GTH transmitter termination circuits
1.140
1.710
1.2
1.8
1.26
1.89
V
V
MGTHAVCCPLL Analog supply voltage for the GTH receiver and PLL circuit
Notes:
1. Each voltage listed requires the filter circuit described in UG371:Virtex-6 FPGA GTH Transceivers User Guide.
2. Voltages are specified for the temperature range of T = –40°C to +100°C.
j
(1)(2)(3)
Table 27: GTH Transceiver Power Supply Sequencing
Symbol
Description
Min
Max
Units
Maximum time between powering MGTHAVCC to when MGTHAVCCRX
must be powered.
THAVCC2HAVCCRX
0
5
–
–
ms
Minimum time between powering MGTHAVCCRX to when
MGTHAVCCPLL can be powered.
THAVCCRX2HAVCCPLL
THAVCCRX2HAVTT
10
10
µs
µs
Minimum time between powering MGTHAVCCRX to when MGTHAVTT
can be powered.
Notes:
1. MGTHAVCCRX must be powered simultaneously or within T
of MGTHAVCC, but it must not precede MGTHAVCC.
HAVCC2HAVCCRX
2. MGTHAVCC and MGTHAVCCRX must be powered before MGTHAVCCPLL and MGTHAVTT. This minimum time is defined by
and T
T
.
HAVCCRX2HAVTT
HAVCCRX2HAVCCPLL
3. At any time, the condition of MGTHAVCC being present and MGTHAVCCRX not being present should not occur for more than the maximum
T
.
HAVCC2HAVCCRX
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
17
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Figure 4 shows the timing parameters in Table 27.
X-Ref Target - Figure 4
MGTHAVCC
(1.1V DC)
THAVCC2HAVCCRX
MGTHAVCCRX
(1.1V DC)
THAVCCRX2HAVCCPLL
MGTHAVCCPLL
(1.8V DC)
THAVCCRX2HAVTT
MGTHAVTT
(1.2V DC)
DS152_04_051110
Figure 4: GTH Transceiver Power Supply Power-On Sequencing
Table 28: GTH Transceiver Supply Current
(1)
Symbol
Description
Typ
Max
Units
mA
mA
mA
mA
Ω
IMGTHAVCC
IMGTHAVCCRX
IMGTHAVTT
MGTHAVCC supply current for one GTH Quad (4 lanes)
MGTHAVCCRX supply current for a GTH Quad (4 lanes)
MGTHAVTT supply current for one GTH Quad (4 lanes)
MGTHAVCCPLL supply current for one GTH Quad (4 lanes)
Precision reference resistor for internal calibration termination
571
Note 2
Note 2
Note 2
Note 2
254
93
IMGTHAVCCPLL
MGTRREF
219
1000.0 1% tolerance
Notes:
1. Typical values are specified at nominal voltage, 25°C, with a 10.3125 Gb/s line rate.
2. Values for currents other than the values specified in this table can be obtained by using the Xilinx Power Estimator (XPE) or XPower
Analyzer (XPA) tools.
(1)(2)
Table 29: GTH Transceiver Quiescent Supply Current
(3)
Symbol
Description
Typ
65
17
1
Max
Units
mA
IMGTHAVCCQ
Quiescent MGTHAVCC Supply Current for one GTH Quad (4 lanes)
Note 4
Note 4
Note 4
Note 4
IMGTHAVCCRXQ Quiescent MGTHAVCCRX Supply Current for one GTH Quad (4 lanes)
IMGTHAVTTQ Quiescent MGTHAVTT Supply Current for one GTH Quad (4 lanes)
mA
mA
IMGTHAVCCPLLQ Quiescent MGTHAVCCPLL Supply Current for one GTH Quad (4 lanes)
1
mA
Notes:
1. Device powered and unconfigured.
2. GTH transceiver quiescent supply current for an entire device can be calculated by multiplying the values in this table by the number of
available GTH transceivers.
3. Typical values are specified at nominal voltage, 25°C.
4. Currents for conditions other than values specified in this table can be obtained by using the XPE or XPA tools.
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
18
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
GTH Transceiver DC Input and Output Levels
Table 30 summarizes the DC output specifications of the GTH transceivers in Virtex-6 FPGAs. Consult UG371:Virtex-6
FPGA GTH Transceivers User Guide for further details.
Table 30: GTH Transceiver DC Specifications
Symbol
DVPPIN
DC Parameter
Conditions
Min
175
800
Typ
–
Max
1200
1200
Units
mV
Differential peak-to-peak input voltage External AC coupled
Differential peak-to-peak output
voltage(1)
Transmitter output swing is set to
maximum setting
–
mV
DVPPOUT
RIN
Differential input resistance
Differential output resistance
80
80
–
100
100
2
120
120
–
Ω
Ω
ROUT
TOSKEW
CEXT
Transmitter output pair (TXP and TXN) intra-pair skew
Recommended external AC coupling capacitor(2)
ps
nF
–
100
–
Notes:
1. The output swing and preemphasis levels are programmable using the attributes discussed in UG371:Virtex-6 FPGA GTH Transceivers User
Guide and can result in values lower than reported in this table.
2. Other values can be used as appropriate to conform to specific protocols and standards.
Table 31 summarizes the DC specifications of the clock input of the GTH transceiver. Consult UG371:Virtex-6 FPGA GTH
Transceivers User Guide for further details.
Table 31: GTH Transceiver Clock DC Input Level Specification
Symbol
DC Parameter
Conditions
≤ 600 MHz
Min
500
600
80
Typ
–
Max
1600
1600
120
–
Units
mV
mV
Ω
VIDIFF
Differential peak-to-peak input voltage
> 600 MHz
–
RIN
Differential input resistance
100
100
CEXT
Required external AC coupling capacitor
–
nF
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
19
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
GTH Transceiver Switching Characteristics
Consult UG371:Virtex-6 FPGA GTH Transceivers User Guide for further information.
Table 32: GTH Transceiver Maximum Data Rate and PLL Frequency Range
Speed Grade
-2
Symbol
Description
Conditions
Units
-3
-1
PLL Output Divider = 1
PLL Output Divider = 4
PLL Output Divider = 1
PLL Output Divider = 4
11.182
2.795
9.92
11.182
2.795
9.92
10.32
2.58
9.92
2.48
5.16
4.96
Gb/s
Gb/s
Gb/s
Gb/s
GHz
GHz
FGTHMAX
Maximum GTH transceiver data rate
Minimum GTH transceiver data rate(1)
FGTHMIN
2.48
2.48
FGPLLMAX
FGPLLMIN
Maximum GTH PLL frequency
Minimum GTH PLL frequency
5.591
4.96
5.591
4.96
Notes:
1. Lower data rates can be achieved using FPGA logic based oversampling designs.
Table 33: GTH Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics
Speed Grade
Symbol
Description
GTHDRPCLK maximum frequency
Units
-3
-2
-1
FGTHDRPCLK
70
70
60
MHz
Table 34: GTH Transceiver Reference Clock Switching Characteristics
All Speed Grades
Symbol
Description
Conditions
Units
Min
150
150
–
Typ
–
Max
645
700
–
-1 speed grade
MHz
MHz
ps
FGCLK
Reference clock frequency range
-2 and -3 speed grades
20% – 80%
–
TRCLK
TFCLK
TDCREF
Reference clock rise time
Reference clock fall time
Reference clock duty cycle
200
200
50
–
80% – 20%
–
–
ps
CLK
45
–
55
2
%
Clock recovery frequency acquisition
time
Initial PLL lock
ms
TLOCK
Lock to data after PLL has locked
to the reference clock
–
–
20
µs
TPHASE
Clock recovery phase acquisition time
X-Ref Target - Figure 5
TRCLK
80%
20%
TFCLK
ds152_05_042109
Figure 5: Reference Clock Timing Parameters
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
20
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
(1)
Table 35: GTH Transceiver User Clock Switching Characteristics
Speed Grade
-2
Symbol
Description
Conditions
Units
-3
-1
FTXOUT
FRXOUT
TXUSERCLKOUT maximum frequency
RXUSERCLKOUT maximum frequency
350
350
350
280
350
280
175
140
170
350
280
350
280
175
140
170
350
323
323
323
258
323
258
162
129
157
323
258
323
258
162
129
157
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
350
16-bit data path
350
20-bit data path
32-bit data path
40-bit data path
64-bit data path
80-bit data path
64B/66B-bit data path
16-bit data path
20-bit data path
32-bit data path
40-bit data path
64-bit data path
80-bit data path
64B/66B-bit data path
280
350
FTXIN
TXUSERCLKIN maximum frequency
280
175
140
170
350
280
350
FRXIN
RXUSERCLKIN maximum frequency
280
175
140
170
Notes:
1. Clocking must be implemented as described in UG371:Virtex-6 FPGA GTH Transceivers User Guide.
Table 36: GTH Transceiver Transmitter Switching Characteristics
Symbol
Description
TX Rise time
Condition
20%–80%
Min
–
Typ
50(3)
50(3)
–
Max
–
Units
ps
TRTX
TFTX
TX Fall time
80%–20%
–
–
ps
TLLSKEW
Transmitter Output Jitter(1)(2)
TX lane-to-lane skew
within one GTH Quad
–
300
ps
TJ11.18
DJ11.18
TJ10.3125
DJ10.3125
TJ9.953
DJ9.953
TJ2.667
DJ2.667
TJ2.488
DJ2.488
Total Jitter
11.181 Gb/s
10.3125 Gb/s
9.953 Gb/s
2.667 Gb/s
2.488 Gb/s
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0.280
0.170
0.280
0.170
0.280
0.170
0.110
0.060
0.110
0.060
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
Deterministic Jitter
Total Jitter
Deterministic Jitter
Total Jitter
Deterministic Jitter
Total Jitter
Deterministic Jitter
Total Jitter
Deterministic Jitter
Notes:
1. These values are NOT intended for protocol specific compliance determinations.
-12
2. All jitter values are based on a bit-error ratio of 1e
.
3. Rise and fall times are specified at the transmitter package balls.
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
21
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 37: GTH Transceiver Receiver Switching Characteristics
Symbol Description
Min
8000
–200
Typ
–
Max
–
Units
UI
RXRL
RXPPMTOL
SJ Jitter Tolerance(1)(2)(3)(4)
Run length (CID)
Data/REFCLK PPM offset tolerance
–
200
ppm
JT_SJ11.18
JT_SJ10.32
JT_SJ9.95
JT_SJ2.667
JT_SJ2.48
Sinusoidal Jitter
11.18 Gb/s
10.32 Gb/s
9.95 Gb/s
2.667 Gb/s
2.48 Gb/s
0.3
0.3
0.3
0.5
0.5
–
–
–
–
–
–
–
–
–
–
UI
UI
UI
UI
UI
Sinusoidal Jitter
Sinusoidal Jitter
Sinusoidal Jitter
Sinusoidal Jitter
Notes:
1. These values are NOT intended for protocol specific compliance determinations.
–12
2. All jitter values are based on a bit error ratio of 1e
.
3. The frequency of the injected sinusoidal jitter is 80 MHz.
4. High-frequency jitter tolerance including 6 db of channel loss at a high frequency of the data rate divided by two.
Ethernet MAC Switching Characteristics
Consult UG368:Virtex-6 FPGA Embedded Tri-mode Ethernet MAC User Guide for further information.
Table 38: Maximum Ethernet MAC Performance
Speed Grade
Symbol
Description
Conditions
Units
-3
2.5(1)
25(2)
125
-2
2.5(1)
25(2)
125
-1
2.5(1)
25(2)
125
-1L
2.5(1)
25(2)
125
62.5
N/A
N/A
2.5
FTEMACCLIENT Client interface maximum
frequency
10 Mb/s – 8-bit width
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
100 Mb/s – 8-bit width
1000 Mb/s – 8-bit width
1000 Mb/s – 16-bit width
2000 Mb/s – 16-bit width
2500 Mb/s – 16-bit width
10 Mb/s – 4-bit width
62.5
125
62.5
125
62.5
125
156.25
2.5
156.25
2.5
156.25
2.5
FTEMACPHY
Physical interface maximum
frequency
100 Mb/s – 4-bit width
1000 Mb/s – 8-bit width
2000 Mb/s – 8-bit width
2500 Mb/s – 8-bit width
25
25
25
25
125
125
125
125
N/A
N/A
250
250
250
312.5
312.5
312.5
Notes:
1. When not using clock enable, the F
2. When not using clock enable, the F
is lowered to 1.25 MHz.
is lowered to 12.5 MHz.
MAX
MAX
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
22
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Integrated Interface Block for PCI Express Designs Switching Characteristics
More information and documentation on solutions for PCI Express designs can be found at:
http://www.xilinx.com/technology/protocols/pciexpress.htm
Table 39: Maximum Performance for PCI Express Designs
Speed Grade
Symbol
Description
Units
-3
-2
-1
-1L
250
250
250
FPIPECLK
FUSERCLK
FDRPCLK
Pipe clock maximum frequency
250
500
250
250
500
250
250
250
250
MHz
MHz
MHz
User clock maximum frequency
DRP clock maximum frequency
System Monitor Analog-to-Digital Converter Specification
Table 40: Analog-to-Digital Specifications
Parameter
Symbol
Comments/Conditions
Min
Typ
Max
Units
AVDD = 2.5V 5%, VREFP = 1.25V, VREFN = 0V, ADCCLK = 5.2 MHz, Tj = –55°C to 125°C M-Grade, Typical values at Tj=+35°C
DC Accuracy: All external input channels. Both unipolar and bipolar modes.
Resolution
10
–
–
–
–
–
Bits
Integral Nonlinearity
Differential Nonlinearity
INL
1
LSBs
LSBs
DNL
No missing codes (TMIN to TMAX
)
–
0.9
Guaranteed Monotonic
Unipolar Offset Error (1)
Bipolar Offset Error (1)
Gain Error
Uncalibrated
–
–
–
–
–
–
–
2
30
30
2
LSBs
LSBs
%
Uncalibrated measured in bipolar mode
Uncalibrated - External Reference
Uncalibrated - Internal Reference
Uncalibrated - External Reference
Uncalibrated - Internal Reference
2
0.2
2
–
%
Bipolar Gain Error (1)
0.2
2
2
%
–
%
Total Unadjusted Error
(Uncalibrated)
TUE
Deviation from ideal transfer function.
External 1.25V reference
10
–
LSBs
Deviation from ideal transfer function.
Internal reference
–
–
–
–
20
1
–
2
–
–
LSBs
LSBs
LSB/°C
dB
Total Unadjusted Error
(Calibrated)
TUE
Deviation from ideal transfer function.
External 1.25V reference
Calibrated Gain Temperature
Coefficient
Variation of FS code with temperature
0.01
70
DC Common-Mode Reject
CMRRDC
VN = VCM = 0.5V 0.5V,
VP – VN = 100mV
Conversion Rate(2)
Conversion Time - Continuous tCONV
Number of CLK cycles
Number of CLK cycles
Number of CLK cycles
DRP clock frequency
Derived from DCLK
26
–
–
–
–
–
–
–
32
21
–
Conversion Time - Event
T/H Acquisition Time
DRP Clock Frequency
ADC Clock Frequency
CLK Duty cycle
tCONV
tACQ
4
DCLK
ADCCLK
8
80
5.2
60
MHz
MHz
%
1
40
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
23
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 40: Analog-to-Digital Specifications (Cont’d)
Parameter
Analog Inputs(3)
Symbol
Comments/Conditions
Min
Typ
Max
Units
Dedicated Analog Inputs
Input Voltage Range
VP - VN
Unipolar Operation
0
–0.5
0
–
–
1
+0.5
+0.5
+0.6
–
Volts
Bipolar Operation
Unipolar Common Mode Range (FS input)
Bipolar Common Mode Range (FS input)
Bandwidth
–
+0.5
–
–
20
–
MHz
Volts
Auxiliary Analog Inputs
Input Voltage Range
Unipolar Operation
0
1
Bipolar Operation
–0.5
0
–
+0.5
+0.5
+0.6
–
V
AUXP[0] /VAUXN[0] to VAUXP[15]
/VAUXN[15]
Unipolar Common Mode Range (FS input)
Bipolar Common Mode Range (FS input)
Bandwidth
–
Tj = –55°C to 125°C
+0.5
–
–
10
1.0
10
–
kHz
µA
Input Leakage Current
Input Capacitance
A/D not converting, ADCCLK stopped
–
–
–
–
pF
On-chip Supply Monitor Error
V
CCINT and VCCAUX with calibration enabled.
–
1.0
% Reading
External 1.25V reference Tj = –55°C to 125°C.
V
CCINT and VCCAUX with calibration enabled.
–
–
–
2
–
–
4
–
% Reading
Internal reference Tj = –40°C to 100°C.(4)
On-chip Temperature Monitor
Error
Tj = –55°C to +125°C with calibration enabled.
External 1.25V reference.
°C
°C
Tj = –40°C to +100°C with calibration enabled.
Internal reference.(4)
5
External Reference Inputs(5)
Positive Reference Input
Voltage Range
VREFP
VREFN
IREF
Measured Relative to VREFN
Measured Relative to AGND
ADCCLK = 5.2 MHz
1.20
–50
–
1.25
0
1.30
100
100
Volts
mV
µA
Negative Reference Input
Voltage Range
Input current
–
Power Requirements
Analog Power Supply
Analog Supply Current
AVDD
AIDD
Measured Relative to AVSS
ADCCLK = 5.2 MHz
2.375
–
2.5
–
2.625
12
Volts
mA
Notes:
1. Offset errors are removed by enabling the System Monitor automatic gain calibration feature.
2. See "System Monitor Timing" in UG370:Virtex-6 FPGA System Monitor User Guide
3. See "Analog Inputs" in UG370:Virtex-6 FPGA System Monitor User Guide for a detailed description.
4. These internal references are not specified over the junction temperature operating range for military (M) temperature devices.
5. Any variation in the reference voltage from the nominal V = 1.25V and V = 0V will result in a deviation from the ideal transfer
REFP
REFN
function.This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for external
ratiometric type applications allowing reference to vary by 4% is permitted.
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
24
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Performance Characteristics
This section provides the performance characteristics of some common functions and designs implemented in
Virtex-6 devices. The numbers reported here are worst-case values; they have all been fully characterized. These values are
subject to the same guidelines as the Switching Characteristics, page 26.
Table 41: Interface Performances
Speed Grade
Description
-3
-2
-1
-1L
Networking Applications
SDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 8)
DDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 10)
SDR LVDS receiver (SFI-4.1)(1)
710 Mb/s
1.4 Gb/s
710 Mb/s
1.4 Gb/s
710 Mb/s
1.3 Gb/s
710 Mb/s
1.3 Gb/s
650 Mb/s
1.25 Gb/s
650 Mb/s
1.1 Gb/s
585 Mb/s
1.1 Gb/s
585 Mb/s
0.9 Gb/s
DDR LVDS receiver (SPI-4.2)(1)
Maximum Physical Interface (PHY) Rate for Memory Interfaces(2)(3)(4)
DDR2
800 Mb/s
800 Mb/s
1066 Mb/s
350 MHz
400 MHz
800 Mb/s
800 Mb/s
300 MHz
350 MHz
606 Mb/s
DDR3
1066 Mb/s
400 MHz
500 MHz
800 Mb/s
QDR II + SRAM
RLDRAM II
–
–
Notes:
1. LVDS receivers are typically bounded with certain applications where specific DPA algorithms dominate deterministic performance.
2. Verified on Xilinx memory characterization platforms designed according to the guidelines in UG:Virtex-6 FPGA Memory Interface Solutions
User Guide.
3. Consult DS186:Virtex-6 FPGA Memory Interface Solutions Data Sheet for performance and feature information on memory interface cores
(controller plus PHY).
4. Memory Interface data rates have not been tested over the junction temperature operating range for military (M) temperature devices.
Customers are responsible for specifying and testing their specific M temperature grade memory implementation.
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
25
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Switching Characteristics
All values represented in this data sheet are based on these
speed specifications: v1.17 for -3, -2, and -1; and v1.10 for
-1L. Switching characteristics are specified on a per-speed-
grade basis and can be designated as Advance,
Preliminary, or Production. Each designation is defined as
follows:
Since individual family members are produced at different
times, the migration from one category to another depends
completely on the status of the fabrication process for each
device.
Table 42 correlates the current status of each Virtex-6
device on a per speed grade basis.
Advance
Table 42: Virtex-6 Device Speed Grade Designations
These specifications are based on simulations only and are
typically available soon after device design specifications
are frozen. Although speed grades with this designation are
considered relatively stable and conservative, some under-
reporting might still occur.
Speed Grade Designations
Device
Advance
Preliminary Production
-3, -2, -1, -1L
-3, -2, -1, -1L
-3, -2, -1, -1L
-3, -2, -1, -1L
-3, -2, -1, -1L
-2, -1, -1L
XC6VLX75T
XC6VLX130T
XC6VLX195T
XC6VLX240T
XC6VLX365T
XC6VLX550T
XC6VLX760
Preliminary
These specifications are based on complete ES
(engineering sample) silicon characterization. Devices and
speed grades with this designation are intended to give a
better indication of the expected performance of production
silicon. The probability of under-reporting delays is greatly
reduced as compared to Advance data.
-2, -1, -1L
XC6VSX315T
XC6VSX475T
XC6VHX250T
XC6VHX255T
XC6VHX380T
XC6VHX565T
XQ6VLX130T
XQ6VLX240T
XQ6VLX550T
XQ6VSX315T
XQ6VSX475T
-3, -2, -1, -1L
-2, -1, -1L
Production
These specifications are released once enough production
silicon of a particular device family member has been
characterized to provide full correlation between
specifications and devices over numerous production lots.
There is no under-reporting of delays, and customers
receive formal notification of any subsequent changes.
Typically, the slowest speed grades transition to Production
before faster speed grades.
-3, -2, -1
-3, -2, -1
-3, -2, -1
-2, -1
-2, -1, -1L
-2, -1, -1L
-1, -1L
All specifications are always representative of worst-case
supply voltage and junction temperature conditions.
-2, -1, -1L
-1, -1L
Testing of Switching Characteristics
All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed
below are representative values.
For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and
back-annotate to the simulation net list. Unless otherwise noted, values apply to all Virtex-6 devices.
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
26
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Production Silicon and ISE Software Status
In some cases, a particular family member (and speed grade) is released to production before a speed specification is
released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent
speed specification releases.
Table 43 lists the production released Virtex-6 family member, speed grade, and the minimum corresponding supported
speed specification version and ISE software revisions. The ISE® software and speed specifications listed are the minimum
releases required for production. All subsequent releases of software and speed specifications are valid.
Table 43: Virtex-6 Device Production Software and Speed Specification Release
Speed Grade Designations
Device
-3
-2
-1
-1L
XC6VLX75T
ISE 12.2 v1.08
ISE 11.5 v1.05(2)
ISE 12.1 v1.06
ISE 11.4.1 v1.04(2)
ISE 12.2 v1.08
ISE 12.3 v1.07 Patch
ISE 12.2 v1.05
ISE 12.2 v1.04
ISE 12.2 v1.04
ISE 12.2 v1.04
ISE 12.2 v1.04
ISE 12.3 v1.07 Patch
ISE 12.3 v1.07 Patch
ISE 12.3 v1.07 Patch
N/A
XC6VLX130T
XC6VLX195T
XC6VLX240T
XC6VLX365T
XC6VLX550T
XC6VLX760
ISE 12.1 v1.06
ISE 12.1 v1.06
ISE 12.1 v1.06
ISE 11.5 v1.05(2)
ISE 12.1 v1.06
ISE 11.4.1 v1.04(2)
N/A
N/A
ISE 12.2 v1.07
ISE 12.2 v1.08
ISE 12.1 v1.06
ISE 12.2 v1.08
XC6VSX315T
XC6VSX475T
XC6VHX250T
XC6VHX255T
XC6VHX380T
XC6VHX565T
XQ6VLX130T
XQ6VLX240T
XQ6VLX550T
XQ6VSX315T
XQ6VSX475T
ISE 12.2 v1.08
N/A
ISE 12.4 v1.10
ISE 13.1 v1.14 using the ISE 13.1 software update
ISE 12.4 v1.10
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
ISE 13.1 v1.14 using the ISE 13.1 software update
N/A
ISE 13.3 v1.17 Patch
ISE 13.3 v1.17 Patch
ISE 13.3 v1.10
ISE 13.3 v1.10
ISE 13.3 v1.10
ISE 13.3 v1.10
ISE 13.3 v1.10
N/A
N/A
ISE 13.3 v1.17 Patch
ISE 13.3 v1.17 Patch
ISE 13.3 v1.17 Patch
Notes:
1. Blank entries indicate a device and/or speed grade in advance or preliminary status.
2. Designs utilizing the GTX transceivers must use the software version ISE 12.1 v1.06 or later.
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
27
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
IOB Pad Input/Output/3-State Switching Characteristics
Table 44 (for commercial (XC) Virtex-6 devices) and Table 45 (for the Defense-grade (XQ) Virtex-6 devices) summarizes the
values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state
delays.
T
is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies depending
IOPI
on the capability of the SelectIO input buffer.
T
is described as the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies
IOOP
depending on the capability of the SelectIO output buffer.
T
is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is
IOTP
disabled. The delay varies depending on the SelectIO capability of the output buffer.
Table 46 summarizes the value of T . T is described as the delay from the T pin to the IOB pad through the
IOTPHZ IOTPHZ
output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state).
Table 44: IOB Switching Characteristics for the Commercial (XC) Virtex-6 Devices
TIOPI
TIOOP
TIOTP
I/O Standard
Speed Grade
Speed Grade
Speed Grade
Units
-3
-2
-1
-1L
-3
-2
-1
-1L
-3
-2
-1
-1L
LVDS_25
0.85 0.94 1.09 1.08 1.45 1.54 1.68 1.62 1.45 1.54 1.68 1.62
0.85 0.94 1.09 1.08 1.53 1.65 1.84 1.73 1.53 1.65 1.84 1.73
0.85 0.94 1.09 1.08 1.51 1.62 1.78 1.69 1.51 1.62 1.78 1.69
0.85 0.94 1.09 1.08 1.39 1.50 1.67 1.65 1.39 1.50 1.67 1.65
0.85 0.94 1.09 1.08 1.45 1.54 1.68 1.62 1.45 1.54 1.68 1.62
0.81 0.91 1.06 1.06 1.45 1.56 1.73 1.71 1.45 1.56 1.73 1.71
0.81 0.91 1.06 1.06 1.44 1.56 1.74 1.72 1.44 1.56 1.74 1.72
0.81 0.91 1.06 1.06 1.42 1.54 1.71 1.69 1.42 1.54 1.71 1.69
0.81 0.91 1.06 1.06 1.47 1.58 1.75 1.72 1.47 1.58 1.75 1.72
0.81 0.91 1.06 1.06 1.50 1.62 1.81 1.78 1.50 1.62 1.81 1.78
0.81 0.91 1.06 1.06 1.42 1.54 1.71 1.69 1.42 1.54 1.71 1.69
0.81 0.91 1.06 1.06 1.49 1.60 1.77 1.74 1.49 1.60 1.77 1.74
0.81 0.91 1.06 1.06 1.42 1.54 1.72 1.71 1.42 1.54 1.72 1.71
0.81 0.91 1.06 1.06 1.42 1.54 1.71 1.69 1.42 1.54 1.71 1.69
0.51 0.57 0.66 0.70 5.09 5.46 6.01 5.63 5.09 5.46 6.01 5.63
0.51 0.57 0.66 0.70 3.30 3.49 3.79 3.65 3.30 3.49 3.79 3.65
0.51 0.57 0.66 0.70 2.62 2.81 3.08 2.95 2.62 2.81 3.08 2.95
0.51 0.57 0.66 0.70 2.21 2.41 2.72 2.59 2.21 2.41 2.72 2.59
0.51 0.57 0.66 0.70 1.80 1.95 2.17 2.10 1.80 1.95 2.17 2.10
0.51 0.57 0.66 0.70 1.89 2.05 2.29 2.21 1.89 2.05 2.29 2.21
0.51 0.57 0.66 0.70 1.68 1.82 2.02 1.98 1.68 1.82 2.02 1.98
0.51 0.57 0.66 0.70 5.12 5.49 6.04 5.62 5.12 5.49 6.04 5.62
0.51 0.57 0.66 0.70 3.28 3.50 3.82 3.65 3.28 3.50 3.82 3.65
0.51 0.57 0.66 0.70 2.56 2.73 2.99 2.88 2.56 2.73 2.99 2.88
0.51 0.57 0.66 0.70 2.11 2.33 2.65 2.53 2.11 2.33 2.65 2.53
0.51 0.57 0.66 0.70 1.74 1.88 2.08 2.03 1.74 1.88 2.08 2.03
0.51 0.57 0.66 0.70 1.77 1.92 2.13 2.08 1.77 1.92 2.13 2.08
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVDSEXT_25
HT_25
BLVDS_25
RSDS_25 (point to point)
HSTL_I
HSTL_II
HSTL_III
HSTL_I_18
HSTL_II_18
HSTL_III_18
SSTL2_I
SSTL2_II
SSTL15
LVCMOS25, Slow, 2 mA
LVCMOS25, Slow, 4 mA
LVCMOS25, Slow, 6 mA
LVCMOS25, Slow, 8 mA
LVCMOS25, Slow, 12 mA
LVCMOS25, Slow, 16 mA
LVCMOS25, Slow, 24 mA
LVCMOS25, Fast, 2 mA
LVCMOS25, Fast, 4 mA
LVCMOS25, Fast, 6 mA
LVCMOS25, Fast, 8 mA
LVCMOS25, Fast, 12 mA
LVCMOS25, Fast, 16 mA
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
28
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 44: IOB Switching Characteristics for the Commercial (XC) Virtex-6 Devices (Cont’d)
TIOPI
TIOOP
TIOTP
I/O Standard
Speed Grade
Speed Grade
Speed Grade
Units
-3
-2
-1
-1L
-3
-2
-1
-1L
-3
-2
-1
-1L
LVCMOS25, Fast, 24 mA
LVCMOS18, Slow, 2 mA
LVCMOS18, Slow, 4 mA
LVCMOS18, Slow, 6 mA
LVCMOS18, Slow, 8 mA
LVCMOS18, Slow, 12 mA
LVCMOS18, Slow, 16 mA
LVCMOS18, Fast, 2 mA
LVCMOS18, Fast, 4 mA
LVCMOS18, Fast, 6 mA
LVCMOS18, Fast, 8 mA
LVCMOS18, Fast, 12 mA
LVCMOS18, Fast, 16 mA
LVCMOS15, Slow, 2 mA
LVCMOS15, Slow, 4 mA
LVCMOS15, Slow, 6 mA
LVCMOS15, Slow, 8 mA
LVCMOS15, Slow, 12 mA
LVCMOS15, Slow, 16 mA
LVCMOS15, Fast, 2 mA
LVCMOS15, Fast, 4 mA
LVCMOS15, Fast, 6 mA
LVCMOS15, Fast, 8 mA
LVCMOS15, Fast, 12 mA
LVCMOS15, Fast, 16 mA
LVCMOS12, Slow, 2 mA
LVCMOS12, Slow, 4 mA
LVCMOS12, Slow, 6 mA
LVCMOS12, Slow, 8 mA
LVCMOS12, Fast, 2 mA
LVCMOS12, Fast, 4 mA
LVCMOS12, Fast, 6 mA
LVCMOS12, Fast, 8 mA
LVDCI_25
0.51 0.57 0.66 0.70 1.66 1.79 1.99 1.96 1.66 1.79 1.99 1.96
0.55 0.61 0.71 0.73 4.21 4.47 4.87 4.30 4.21 4.47 4.87 4.30
0.55 0.61 0.71 0.73 2.79 2.96 3.21 2.94 2.79 2.96 3.21 2.94
0.55 0.61 0.71 0.73 2.30 2.43 2.64 2.47 2.30 2.43 2.64 2.47
0.55 0.61 0.71 0.73 2.01 2.11 2.27 2.24 2.01 2.11 2.27 2.24
0.55 0.61 0.71 0.73 1.88 1.99 2.15 2.10 1.88 1.99 2.15 2.10
0.55 0.61 0.71 0.73 1.84 1.95 2.11 2.04 1.84 1.95 2.11 2.04
0.55 0.61 0.71 0.73 4.00 4.23 4.57 4.08 4.00 4.23 4.57 4.08
0.55 0.61 0.71 0.73 2.62 2.76 2.97 2.74 2.62 2.76 2.97 2.74
0.55 0.61 0.71 0.73 2.15 2.28 2.46 2.32 2.15 2.28 2.46 2.32
0.55 0.61 0.71 0.73 1.90 1.99 2.13 2.14 1.90 1.99 2.13 2.14
0.55 0.61 0.71 0.73 1.69 1.80 1.97 1.88 1.69 1.80 1.97 1.88
0.55 0.61 0.71 0.73 1.63 1.74 1.91 1.88 1.63 1.74 1.91 1.88
0.64 0.73 0.85 0.85 3.43 3.77 4.29 3.91 3.43 3.77 4.29 3.91
0.64 0.73 0.85 0.85 2.58 2.79 3.10 2.93 2.58 2.79 3.10 2.93
0.64 0.73 0.85 0.85 2.08 2.32 2.68 2.50 2.08 2.32 2.68 2.50
0.64 0.73 0.85 0.85 1.81 1.98 2.23 2.24 1.81 1.98 2.23 2.24
0.64 0.73 0.85 0.85 1.76 1.91 2.13 2.07 1.76 1.91 2.13 2.07
0.64 0.73 0.85 0.85 1.69 1.83 2.04 1.98 1.69 1.83 2.04 1.98
0.64 0.73 0.85 0.85 3.44 3.77 4.28 3.91 3.44 3.77 4.28 3.91
0.64 0.73 0.85 0.85 2.37 2.53 2.78 2.66 2.37 2.53 2.78 2.66
0.64 0.73 0.85 0.85 1.80 2.05 2.42 2.16 1.80 2.05 2.42 2.16
0.64 0.73 0.85 0.85 1.76 1.90 2.11 2.04 1.76 1.90 2.11 2.04
0.64 0.73 0.85 0.85 1.64 1.77 1.97 1.90 1.64 1.77 1.97 1.90
0.64 0.73 0.85 0.85 1.62 1.76 1.96 1.92 1.62 1.76 1.96 1.92
0.72 0.81 0.93 0.95 3.14 3.39 3.75 3.54 3.14 3.39 3.75 3.54
0.72 0.81 0.93 0.95 2.43 2.63 2.93 2.79 2.43 2.63 2.93 2.79
0.72 0.81 0.93 0.95 1.92 2.11 2.41 2.26 1.92 2.11 2.41 2.26
0.72 0.81 0.93 0.95 1.87 2.02 2.25 2.17 1.87 2.02 2.25 2.17
0.72 0.81 0.93 0.95 2.71 2.98 3.39 3.11 2.71 2.98 3.39 3.11
0.72 0.81 0.93 0.95 1.93 2.16 2.51 2.31 1.93 2.16 2.51 2.31
0.72 0.81 0.93 0.95 1.75 1.89 2.11 2.05 1.75 1.89 2.11 2.05
0.72 0.81 0.93 0.95 1.69 1.82 2.02 1.98 1.69 1.82 2.02 1.98
0.51 0.57 0.66 0.70 2.05 2.14 2.26 2.26 2.05 2.14 2.26 2.26
0.55 0.61 0.71 0.73 2.07 2.23 2.47 2.38 2.07 2.23 2.47 2.38
0.64 0.73 0.85 0.85 1.85 2.01 2.24 2.18 1.85 2.01 2.24 2.18
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVDCI_18
LVDCI_15
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
29
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 44: IOB Switching Characteristics for the Commercial (XC) Virtex-6 Devices (Cont’d)
TIOPI
TIOOP
TIOTP
I/O Standard
Speed Grade
Speed Grade
Speed Grade
Units
-3
-2
-1
-1L
-3
-2
-1
-1L
-3
-2
-1
-1L
LVDCI_DV2_25
0.51 0.57 0.66 0.70 1.71 1.83 2.01 2.00 1.71 1.83 2.01 2.00
0.55 0.61 0.71 0.73 1.69 1.81 2.00 1.98 1.69 1.81 2.00 1.98
0.64 0.73 0.85 0.85 1.68 1.77 1.91 1.98 1.68 1.77 1.91 1.98
0.85 0.94 1.09 1.08 1.38 1.49 1.65 1.64 1.38 1.49 1.65 1.64
0.81 0.91 1.06 1.06 1.48 1.60 1.78 1.74 1.48 1.60 1.78 1.74
0.81 0.91 1.06 1.06 1.40 1.50 1.66 1.64 1.40 1.50 1.66 1.64
0.81 0.91 1.06 1.06 1.37 1.49 1.68 1.66 1.37 1.49 1.68 1.66
0.81 0.91 1.06 1.06 1.40 1.50 1.66 1.64 1.40 1.50 1.66 1.64
0.81 0.91 1.06 1.06 1.34 1.45 1.62 1.61 1.34 1.45 1.62 1.61
0.81 0.91 1.06 1.06 1.42 1.53 1.68 1.66 1.42 1.53 1.68 1.66
0.81 0.91 1.06 1.06 1.36 1.46 1.62 1.59 1.36 1.46 1.62 1.59
0.81 0.91 1.06 1.06 1.42 1.53 1.68 1.66 1.42 1.53 1.68 1.66
0.81 0.91 1.06 1.06 1.43 1.54 1.69 1.67 1.43 1.54 1.69 1.67
0.85 0.94 1.09 1.08 1.47 1.58 1.75 1.72 1.47 1.58 1.75 1.72
0.85 0.94 1.09 1.08 1.42 1.53 1.68 1.66 1.42 1.53 1.68 1.66
0.85 0.94 1.09 1.08 1.45 1.56 1.73 1.71 1.45 1.56 1.73 1.71
0.85 0.94 1.09 1.08 1.40 1.50 1.66 1.64 1.40 1.50 1.66 1.64
0.85 0.94 1.09 1.08 1.50 1.62 1.81 1.78 1.50 1.62 1.81 1.78
0.85 0.94 1.09 1.08 1.36 1.46 1.62 1.59 1.36 1.46 1.62 1.59
0.85 0.94 1.09 1.08 1.42 1.53 1.68 1.66 1.42 1.53 1.68 1.66
0.85 0.94 1.09 1.08 1.44 1.56 1.74 1.72 1.44 1.56 1.74 1.72
0.85 0.94 1.09 1.08 1.37 1.49 1.68 1.66 1.37 1.49 1.68 1.66
0.81 0.91 1.06 1.06 1.42 1.53 1.70 1.68 1.42 1.53 1.70 1.68
0.81 0.91 1.06 1.06 1.39 1.50 1.67 1.69 1.39 1.50 1.67 1.69
0.81 0.91 1.06 1.06 1.42 1.53 1.70 1.68 1.42 1.53 1.70 1.68
0.81 0.91 1.06 1.06 1.47 1.58 1.75 1.73 1.47 1.58 1.75 1.73
0.81 0.91 1.06 1.06 1.39 1.50 1.67 1.66 1.39 1.50 1.67 1.66
0.81 0.91 1.06 1.06 1.40 1.51 1.67 1.65 1.40 1.51 1.67 1.65
0.81 0.91 1.06 1.06 1.36 1.47 1.63 1.62 1.36 1.47 1.63 1.62
0.81 0.91 1.06 1.06 1.40 1.51 1.67 1.65 1.40 1.51 1.67 1.65
0.81 0.91 1.06 1.06 1.41 1.52 1.68 1.66 1.41 1.52 1.68 1.66
0.81 0.91 1.06 1.06 1.41 1.52 1.68 1.66 1.41 1.52 1.68 1.66
0.85 0.94 1.09 1.08 1.49 1.60 1.77 1.74 1.49 1.60 1.77 1.74
0.85 0.94 1.09 1.08 1.42 1.53 1.70 1.68 1.42 1.53 1.70 1.68
0.85 0.94 1.09 1.08 1.42 1.54 1.72 1.71 1.42 1.54 1.72 1.71
0.85 0.94 1.09 1.08 1.39 1.50 1.67 1.69 1.39 1.50 1.67 1.69
0.85 0.94 1.09 1.08 1.42 1.53 1.70 1.68 1.42 1.53 1.70 1.68
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVDCI_DV2_18
LVDCI_DV2_15
LVPECL_25
HSTL_I_12
HSTL_I_DCI
HSTL_II_DCI
HSTL_II_T_DCI
HSTL_III_DCI
HSTL_I_DCI_18
HSTL_II_DCI_18
HSTL_II _T_DCI_18
HSTL_III_DCI_18
DIFF_HSTL_I_18
DIFF_HSTL_I_DCI_18
DIFF_HSTL_I
DIFF_HSTL_I_DCI
DIFF_HSTL_II_18
DIFF_HSTL_II_DCI_18
DIFF_HSTL_II _T_DCI_18
DIFF_HSTL_II
DIFF_HSTL_II_DCI
SSTL2_I_DCI
SSTL2_II_DCI
SSTL2_II_T_DCI
SSTL18_I
SSTL18_II
SSTL18_I_DCI
SSTL18_II_DCI
SSTL18_II_T_DCI
SSTL15_T_DCI
SSTL15_DCI
DIFF_SSTL2_I
DIFF_SSTL2_I_DCI
DIFF_SSTL2_II
DIFF_SSTL2_II_DCI
DIFF_SSTL2_II_T_DCI
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
30
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 44: IOB Switching Characteristics for the Commercial (XC) Virtex-6 Devices (Cont’d)
TIOPI
TIOOP
TIOTP
I/O Standard
Speed Grade
Speed Grade
Speed Grade
Units
-3
-2
-1
-1L
-3
-2
-1
-1L
-3
-2
-1
-1L
DIFF_SSTL18_I
0.85 0.94 1.09 1.08 1.47 1.58 1.75 1.73 1.47 1.58 1.75 1.73
0.85 0.94 1.09 1.08 1.40 1.51 1.67 1.65 1.40 1.51 1.67 1.65
0.85 0.94 1.09 1.08 1.39 1.50 1.67 1.66 1.39 1.50 1.67 1.66
0.85 0.94 1.09 1.08 1.36 1.47 1.63 1.62 1.36 1.47 1.63 1.62
0.85 0.94 1.09 1.08 1.40 1.51 1.67 1.65 1.40 1.51 1.67 1.65
0.81 0.91 1.06 1.06 1.42 1.54 1.71 1.69 1.42 1.54 1.71 1.69
0.81 0.91 1.06 1.06 1.41 1.52 1.68 1.66 1.41 1.52 1.68 1.66
0.81 0.91 1.06 1.06 1.41 1.52 1.68 1.66 1.41 1.52 1.68 1.66
ns
ns
ns
ns
ns
ns
ns
ns
DIFF_SSTL18_I_DCI
DIFF_SSTL18_II
DIFF_SSTL18_II_DCI
DIFF_SSTL18_II_T_DCI
DIFF_SSTL15
DIFF_SSTL15_DCI
DIFF_SSTL15_T_DCI
Table 45: IOB Switching Characteristics for the Defense-grade (XQ) Virtex-6 Devices
TIOPI
Speed Grade
-1
TIOOP
Speed Grade
-1
TIOTP
Speed Grade
-1
I/O Standard
Units
-2
-1L
-2
-1L
-2
-1L
LVDS_25
LVDSEXT_25
HT_25
0.94
0.94
0.94
0.94
0.94
0.91
0.91
0.91
0.91
0.91
0.91
0.91
0.91
0.91
0.57
0.57
0.57
0.57
0.57
0.57
0.57
0.57
0.57
0.57
0.57
0.57
1.09
1.08
1.08
1.08
1.08
1.08
1.06
1.06
1.06
1.06
1.06
1.06
1.06
1.06
1.06
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
1.54
1.65
1.62
1.50
1.54
1.56
1.56
1.54
1.58
1.62
1.54
1.60
1.54
1.54
5.46
3.49
2.81
2.41
1.95
2.05
1.82
5.49
3.50
2.73
2.33
1.88
2.16
1.62
1.73
1.69
1.65
1.62
1.71
1.72
1.69
1.72
1.78
1.69
1.74
1.71
1.69
5.63
3.65
2.95
2.59
2.10
2.21
1.98
5.62
3.65
2.88
2.53
2.03
1.54
1.65
1.62
1.50
1.54
1.56
1.56
1.54
1.58
1.62
1.54
1.60
1.54
1.54
5.46
3.49
2.81
2.41
1.95
2.05
1.82
5.49
3.50
2.73
2.33
1.88
2.16
1.62
1.73
1.69
1.65
1.62
1.71
1.72
1.69
1.72
1.78
1.69
1.74
1.71
1.69
5.63
3.65
2.95
2.59
2.10
2.21
1.98
5.62
3.65
2.88
2.53
2.03
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.09
2.20
2.20
1.09
2.20
3.18
2.20
BLVDS_25
1.09
3.18
RSDS_25 (point to point)
HSTL_I
1.09
2.22
2.22
1.06
2.44
2.44
HSTL_II
1.06
2.21
2.21
HSTL_III
1.06
1.06
2.50
2.50
HSTL_I_18
2.43
2.43
HSTL_II_18
1.06
2.30
2.30
HSTL_III_18
1.06
1.06
2.49
2.49
SSTL2_I
2.50
2.50
SSTL2_II
1.06
1.06
0.66
0.66
0.66
0.66
0.66
2.49
2.49
SSTL15
2.07
2.07
LVCMOS25, Slow, 2 mA
LVCMOS25, Slow, 4 mA
LVCMOS25, Slow, 6 mA
LVCMOS25, Slow, 8 mA
LVCMOS25, Slow, 12 mA
LVCMOS25, Slow, 16 mA
LVCMOS25, Slow, 24 mA
LVCMOS25, Fast, 2 mA
LVCMOS25, Fast, 4 mA
LVCMOS25, Fast, 6 mA
LVCMOS25, Fast, 8 mA
LVCMOS25, Fast, 12 mA
6.01
6.01
3.79
3.79
3.08
3.08
2.72
2.72
2.23
2.23
0.66
2.29
2.29
0.66
2.24
2.24
0.66
0.66
0.66
0.66
0.66
6.04
6.04
3.82
3.82
2.99
2.99
2.65
2.65
2.08
2.08
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
31
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 45: IOB Switching Characteristics for the Defense-grade (XQ) Virtex-6 Devices (Cont’d)
TIOPI
Speed Grade
-1
TIOOP
Speed Grade
-1
TIOTP
Speed Grade
-1
I/O Standard
Units
-2
-1L
-2
-1L
-2
-1L
LVCMOS25, Fast, 16 mA
0.57
0.57
0.61
0.61
0.61
0.61
0.61
0.61
0.61
0.61
0.61
0.61
0.61
0.61
0.73
0.73
0.73
0.73
0.73
0.73
0.73
0.73
0.73
0.73
0.73
0.73
0.81
0.81
0.81
0.81
0.81
0.81
0.81
0.81
0.57
0.61
0.73
0.57
0.66
0.66
0.71
0.71
0.71
0.71
0.71
0.71
0.71
0.71
0.71
0.71
0.71
0.71
0.85
0.85
0.85
0.85
0.85
0.85
0.85
0.85
0.85
0.85
0.85
0.85
0.93
0.93
0.93
0.93
0.93
0.93
0.93
0.93
0.70
0.71
0.85
0.70
0.70
0.70
0.73
0.73
0.73
0.73
0.73
0.73
0.73
0.73
0.73
0.73
0.73
0.73
0.85
0.85
0.85
0.85
0.85
0.85
0.85
0.85
0.85
0.85
0.85
0.85
0.95
0.95
0.95
0.95
0.95
0.95
0.95
0.95
0.70
0.73
0.85
0.70
1.92
1.79
4.47
2.96
2.43
2.11
1.99
1.95
4.23
2.76
2.28
1.99
1.80
1.74
3.77
2.79
2.32
1.98
1.91
1.83
3.77
2.53
2.05
1.90
1.77
1.76
3.39
2.63
2.11
2.02
2.98
2.16
1.89
1.82
2.14
2.23
2.01
1.83
2.15
2.15
4.87
3.21
2.64
2.41
2.30
2.30
4.57
2.97
2.46
2.34
2.19
2.18
4.29
3.10
2.68
2.29
2.23
2.23
4.28
2.78
2.42
2.20
2.11
2.11
3.75
2.93
2.67
2.25
3.39
2.70
2.34
2.10
2.82
2.78
2.75
2.37
2.08
1.96
4.30
2.94
2.47
2.24
2.10
2.04
4.08
2.74
2.32
2.14
1.88
1.88
3.91
2.93
2.50
2.24
2.07
1.98
3.91
2.66
2.16
2.04
1.90
1.92
3.54
2.79
2.26
2.17
3.11
2.31
2.05
1.98
2.26
2.38
2.18
2.00
1.92
1.79
4.47
2.96
2.43
2.11
1.99
1.95
4.23
2.76
2.28
1.99
1.80
1.74
3.77
2.79
2.32
1.98
1.91
1.83
3.77
2.53
2.05
1.90
1.77
1.76
3.39
2.63
2.11
2.02
2.98
2.16
1.89
1.82
2.14
2.23
2.01
1.83
2.15
2.15
4.87
3.21
2.64
2.41
2.30
2.30
4.57
2.97
2.46
2.34
2.19
2.18
4.29
3.10
2.68
2.29
2.23
2.23
4.28
2.78
2.42
2.20
2.11
2.11
3.75
2.93
2.67
2.25
3.39
2.70
2.34
2.10
2.82
2.78
2.75
2.37
2.08
1.96
4.30
2.94
2.47
2.24
2.10
2.04
4.08
2.74
2.32
2.14
1.88
1.88
3.91
2.93
2.50
2.24
2.07
1.98
3.91
2.66
2.16
2.04
1.90
1.92
3.54
2.79
2.26
2.17
3.11
2.31
2.05
1.98
2.26
2.38
2.18
2.00
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVCMOS25, Fast, 24 mA
LVCMOS18, Slow, 2 mA
LVCMOS18, Slow, 4 mA
LVCMOS18, Slow, 6 mA
LVCMOS18, Slow, 8 mA
LVCMOS18, Slow, 12 mA
LVCMOS18, Slow, 16 mA
LVCMOS18, Fast, 2 mA
LVCMOS18, Fast, 4 mA
LVCMOS18, Fast, 6 mA
LVCMOS18, Fast, 8 mA
LVCMOS18, Fast, 12 mA
LVCMOS18, Fast, 16 mA
LVCMOS15, Slow, 2 mA
LVCMOS15, Slow, 4 mA
LVCMOS15, Slow, 6 mA
LVCMOS15, Slow, 8 mA
LVCMOS15, Slow, 12 mA
LVCMOS15, Slow, 16 mA
LVCMOS15, Fast, 2 mA
LVCMOS15, Fast, 4 mA
LVCMOS15, Fast, 6 mA
LVCMOS15, Fast, 8 mA
LVCMOS15, Fast, 12 mA
LVCMOS15, Fast, 16 mA
LVCMOS12, Slow, 2 mA
LVCMOS12, Slow, 4 mA
LVCMOS12, Slow, 6 mA
LVCMOS12, Slow, 8 mA
LVCMOS12, Fast, 2 mA
LVCMOS12, Fast, 4 mA
LVCMOS12, Fast, 6 mA
LVCMOS12, Fast, 8 mA
LVDCI_25
LVDCI_18
LVDCI_15
LVDCI_DV2_25
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
32
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 45: IOB Switching Characteristics for the Defense-grade (XQ) Virtex-6 Devices (Cont’d)
TIOPI
Speed Grade
-1
TIOOP
Speed Grade
-1
TIOTP
Speed Grade
-1
I/O Standard
Units
-2
-1L
-2
-1L
-2
-1L
LVDCI_DV2_18
LVDCI_DV2_15
LVPECL_25
0.61
0.73
0.94
0.91
0.91
0.91
0.91
0.91
0.91
0.91
0.91
0.91
0.94
0.94
0.94
0.94
0.94
0.94
0.94
0.94
0.94
0.91
0.91
0.91
0.91
0.91
0.91
0.91
0.91
0.91
0.91
0.94
0.94
0.94
0.94
0.94
0.94
0.94
0.72
0.85
1.09
1.06
1.06
1.06
1.06
1.06
1.06
1.06
1.06
1.06
1.09
1.09
1.09
1.09
1.09
1.09
1.09
1.09
1.09
1.06
1.06
1.06
1.06
1.06
1.06
1.06
1.06
1.06
1.06
1.09
1.09
1.09
1.09
1.09
1.09
1.09
0.73
0.85
1.08
1.06
1.06
1.06
1.06
1.06
1.06
1.06
1.06
1.06
1.08
1.08
1.08
1.08
1.08
1.08
1.08
1.08
1.08
1.06
1.06
1.06
1.06
1.06
1.06
1.06
1.06
1.06
1.06
1.08
1.08
1.08
1.08
1.08
1.08
1.08
1.81
1.77
1.49
1.60
1.50
1.49
1.50
1.45
1.53
1.46
1.53
1.54
1.58
1.53
1.56
1.50
1.62
1.46
1.53
1.56
1.49
1.53
1.50
1.53
1.58
1.50
1.51
1.47
1.51
1.52
1.52
1.60
1.53
1.54
1.50
1.53
1.58
1.51
2.36
2.30
2.68
2.48
2.43
2.39
2.43
2.48
2.44
2.41
2.43
2.50
2.30
2.21
2.28
2.28
2.33
2.18
2.22
2.29
2.26
2.51
2.50
2.52
2.48
2.46
2.49
2.41
2.49
2.48
2.48
2.34
2.25
2.29
2.23
2.26
2.22
2.30
1.98
1.98
1.64
1.74
1.64
1.66
1.64
1.61
1.66
1.59
1.66
1.67
1.72
1.66
1.71
1.64
1.78
1.59
1.66
1.72
1.66
1.68
1.69
1.68
1.73
1.66
1.65
1.62
1.65
1.66
1.66
1.74
1.68
1.71
1.69
1.68
1.73
1.65
1.81
1.77
1.49
1.60
1.50
1.49
1.50
1.45
1.53
1.46
1.53
1.54
1.58
1.53
1.56
1.50
1.62
1.46
1.53
1.56
1.49
1.53
1.50
1.53
1.58
1.50
1.51
1.47
1.51
1.52
1.52
1.60
1.53
1.54
1.50
1.53
1.58
1.51
2.36
2.30
2.68
2.48
2.43
2.39
2.43
2.48
2.44
2.41
2.43
2.50
2.30
2.21
2.28
2.28
2.33
2.18
2.22
2.29
2.26
2.51
2.50
2.52
2.48
2.46
2.49
2.41
2.49
2.48
2.48
2.34
2.25
2.29
2.23
2.26
2.22
2.30
1.98
1.98
1.64
1.74
1.64
1.66
1.64
1.61
1.66
1.59
1.66
1.67
1.72
1.66
1.71
1.64
1.78
1.59
1.66
1.72
1.66
1.68
1.69
1.68
1.73
1.66
1.65
1.62
1.65
1.66
1.66
1.74
1.68
1.71
1.69
1.68
1.73
1.65
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
HSTL_I_12
HSTL_I_DCI
HSTL_II_DCI
HSTL_II_T_DCI
HSTL_III_DCI
HSTL_I_DCI_18
HSTL_II_DCI_18
HSTL_II _T_DCI_18
HSTL_III_DCI_18
DIFF_HSTL_I_18
DIFF_HSTL_I_DCI_18
DIFF_HSTL_I
DIFF_HSTL_I_DCI
DIFF_HSTL_II_18
DIFF_HSTL_II_DCI_18
DIFF_HSTL_II _T_DCI_18
DIFF_HSTL_II
DIFF_HSTL_II_DCI
SSTL2_I_DCI
SSTL2_II_DCI
SSTL2_II_T_DCI
SSTL18_I
SSTL18_II
SSTL18_I_DCI
SSTL18_II_DCI
SSTL18_II_T_DCI
SSTL15_T_DCI
SSTL15_DCI
DIFF_SSTL2_I
DIFF_SSTL2_I_DCI
DIFF_SSTL2_II
DIFF_SSTL2_II_DCI
DIFF_SSTL2_II_T_DCI
DIFF_SSTL18_I
DIFF_SSTL18_I_DCI
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
33
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 45: IOB Switching Characteristics for the Defense-grade (XQ) Virtex-6 Devices (Cont’d)
TIOPI
Speed Grade
-1
TIOOP
Speed Grade
-1
TIOTP
Speed Grade
-1
I/O Standard
Units
-2
-1L
-2
-1L
1.66
1.62
1.65
1.69
1.66
1.66
-2
-1L
1.66
1.62
1.65
1.69
1.66
1.66
DIFF_SSTL18_II
0.94
0.94
0.94
0.91
0.91
0.91
1.09
1.08
1.08
1.08
1.06
1.06
1.06
1.50
1.47
1.51
1.54
1.52
1.52
2.27
1.50
1.47
1.51
1.54
1.52
1.52
2.27
ns
ns
ns
ns
ns
ns
DIFF_SSTL18_II_DCI
DIFF_SSTL18_II_T_DCI
DIFF_SSTL15
1.09
2.20
2.20
1.09
2.30
2.30
1.06
2.25
2.25
DIFF_SSTL15_DCI
DIFF_SSTL15_T_DCI
1.06
2.25
2.25
1.06
2.25
2.25
Table 46: IOB 3-state ON Output Switching Characteristics (T
)
IOTPHZ
Speed Grade
Symbol
Description
Units
-3
-2
-1
-1L
0.99
TIOTPHZ
T input to Pad high-impedance
0.86
0.92
0.99
ns
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
34
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table 47 shows the test setup parameters used for measuring input delay.
Table 47: Input Delay Measurement Methodology
VMEAS
VREF
(1)(2)
(1)(2)
Description
I/O Standard Attribute
VL
VH
(1)(4)(5)
(1)(3)(5)
LVCMOS, 2.5V
LVCMOS, 1.8V
LVCMOS, 1.5V
LVCMOS25
0
0
0
2.5
1.8
1.25
0.9
–
–
LVCMOS18
LVCMOS15
1.5
0.75
VREF
–
HSTL (High-Speed Transceiver Logic),
Class I & II
HSTL_I, HSTL_II
V
REF – 0.5
VREF + 0.5
0.75
HSTL, Class III
HSTL_III
VREF – 0.5
REF – 0.5
VREF – 0.5
VREF + 0.5
VREF + 0.5
VREF + 0.5
VREF + 1.00
VREF
VREF
VREF
VREF
0.90
0.90
1.08
1.5
HSTL, Class I & II, 1.8V
HSTL, Class III 1.8V
HSTL_I_18, HSTL_II_18
HSTL_III_18
V
SSTL (Stub Terminated Transceiver Logic),
Class I & II, 3.3V
SSTL3_I, SSTL3_II
VREF – 1.00
SSTL, Class I & II, 2.5V
SSTL2_I, SSTL2_II
SSTL18_I, SSTL18_II
LVDS_25
V
REF – 0.75
VREF + 0.75
VREF + 0.5
1.2 + 0.125
1.2 + 0.125
0.6 + 0.125
VREF
VREF
0(6)
1.25
0.90
–
SSTL, Class I & II, 1.8V
VREF – 0.5
LVDS (Low-Voltage Differential Signaling), 2.5V
LVDSEXT (LVDS Extended Mode), 2.5V
HT (HyperTransport), 2.5V
1.2 – 0.125
1.2 – 0.125
0.6 – 0.125
LVDSEXT_25
LDT_25
0(6)
–
0(6)
–
Notes:
1. The input delay measurement methodology parameters for LVDCI are the same for LVCMOS standards of the same voltage. Input delay
measurement methodology parameters for HSLVDCI are the same as for HSTL_II standards of the same voltage. Parameters for all other
DCI standards are the same for the corresponding non-DCI standards.
2. Input waveform switches between V and V .
L
H
3. Measurements are made at typical, minimum, and maximum V
values listed are typical.
values. Reported delays reflect worst case of these measurements. V
REF
REF
4. Input voltage level from which measurement starts.
5. This is an input voltage reference that bears no relation to the V
6. The value given is the differential input voltage.
/ V
parameters found in IBIS models and/or noted in Figure 6.
REF
MEAS
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
35
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Output Delay Measurements
X-Ref Target - Figure 7
FPGA Output
Output delays are measured using a Tektronix P6245
TDS500/600 probe (< 1 pF) across approximately 4" of FR4
microstrip trace. Standard termination was used for all
testing. The propagation delay of the 4" trace is
+
CREF
RREF VMEAS
characterized separately and subtracted from the final
measurement, and is therefore not included in the
generalized test setups shown in Figure 6 and Figure 7.
–
ds152_07_042109
X-Ref Target - Figure 6
Figure 7: Differential Test Setup
VREF
Measurements and test conditions are reflected in the IBIS
models except where the IBIS format precludes it.
Parameters V
, R
, C
, and V
fully describe
REF
REF
REF
MEAS
RREF
FPGA Output
the test conditions for each I/O standard. The most accurate
prediction of propagation delay in any given application can
be obtained through IBIS simulation, using the following
method:
VMEAS
(voltage level when taking
delay measurement)
1. Simulate the output driver of choice into the generalized
test setup, using values from Table 48.
CREF
(probe capacitance)
2. Record the time to V
.
MEAS
ds152_06_042109
3. Simulate the output driver of choice into the actual PCB
trace and load, using the appropriate IBIS model or
capacitance value to represent the load.
Figure 6: Single Ended Test Setup
4. Record the time to V
.
MEAS
5. Compare the results of steps 2 and 4. The increase or
decrease in delay yields the actual propagation delay of
the PCB trace.
Table 48: Output Delay Measurement Methodology
(1)
I/O Standard
Attribute
RREF CREF
VMEAS VREF
Description
(Ω)
1M
1M
1M
1M
50
(pF)
0
(V)
1.25
0.9
(V)
LVCMOS, 2.5V
LVCMOS25
0
LVCMOS, 1.8V
LVCMOS18
LVCMOS15
LVCMOS12
HSTL_I
0
0
LVCMOS, 1.5V
0
0.75
0.75
VREF
VREF
0.9
0
LVCMOS, 1.2V
0
0
HSTL (High-Speed Transceiver Logic), Class I
HSTL, Class II
0
0.75
0.75
1.5
0.9
0.9
1.8
0.9
0.9
1.25
1.25
1.2
1.2
0
HSTL_II
25
0
HSTL, Class III
HSTL_III
50
0
HSTL, Class I, 1.8V
HSTL_I_18
HSTL_II_18
HSTL_III_18
SSTL18_I
SSTL18_II
SSTL2_I
50
0
VREF
VREF
1.1
HSTL, Class II, 1.8V
25
0
HSTL, Class III, 1.8V
50
0
SSTL (Stub Series Terminated Logic), Class I, 1.8V
SSTL, Class II, 1.8V
50
0
VREF
VREF
VREF
VREF
0(2)
25
0
SSTL, Class I, 2.5V
50
0
SSTL, Class II, 2.5V
SSTL2_II
LVDS_25
LVDS_25
BLVDS_25
25
0
LVDS (Low-Voltage Differential Signaling), 2.5V
LVDSEXT (LVDS Extended Mode), 2.5V
BLVDS (Bus LVDS), 2.5V
100
100
100
0
0
0(2)
0
0(2)
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
36
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 48: Output Delay Measurement Methodology (Cont’d)
(1)
I/O Standard
Attribute
RREF CREF
VMEAS VREF
Description
HT (HyperTransport), 2.5V
(Ω)
100
100
(pF)
(V)
0(2)
0(2)
(V)
0.6
0
LDT_25
0
0
LVPECL (Low-Voltage Positive Emitter-Coupled Logic),
2.5V
LVPECL_25
LVDCI/HSLVDCI, 2.5V
LVDCI/HSLVDCI, 1.8V
LVDCI/HSLVDCI, 1.5V
LVDCI_25, HSLVDCI_25
LVDCI_18, HSLVDCI_18
LVDCI_15, HSLVDCI_15
1M
1M
1M
50
50
50
50
50
50
0
0
0
0
0
0
0
0
0
1.25
0.9
0
0
0.75
VREF
0.9
0
HSTL (High-Speed Transceiver Logic), Class I & II, with DCI HSTL_I_DCI, HSTL_II_DCI
0.75
1.5
0.9
1.8
0.9
1.25
HSTL, Class III, with DCI
HSTL_III_DCI
HSTL, Class I & II, 1.8V, with DCI
HSTL, Class III, 1.8V, with DCI
HSTL_I_DCI_18, HSTL_II_DCI_18
HSTL_III_DCI_18
VREF
1.1
SSTL (Stub Series Termi.Logic), Class I & II, 1.8V, with DCI SSTL18_I_DCI, SSTL18_II_DCI
VREF
VREF
SSTL, Class I & II, 2.5V, with DCI
SSTL2_I_DCI, SSTL2_II_DCI
Notes:
1.
C
is the capacitance of the probe, nominally 0 pF.
REF
2. The value given is the differential output voltage.
Input/Output Logic Switching Characteristics
Table 49: ILOGIC Switching Characteristics
Speed Grade
Symbol
Description
Units
-3
-2
-1
-1L
Setup/Hold
TICE1CK/TICKCE1
TISRCK/TICKSR
TIDOCK/TIOCKD
CE1 pin Setup/Hold with respect to CLK
0.21/
0.03
0.25/
0.04
0.27/
0.04
0.31/
0.05
ns
ns
ns
ns
SR pin Setup/Hold with respect to CLK
0.66/
–0.08
0.78/
–0.08
0.96/
–0.08
1.09/
–0.11
D pin Setup/Hold with respect to CLK without Delay
DDLY pin Setup/Hold with respect to CLK (using IODELAY)
0.07/
0.41
0.08/
0.46
0.10/
0.54
0.11/
0.64
T
IDOCKD/TIOCKDD
0.10/
0.32
0.12/
0.36
0.14/
0.42
0.16/
0.50
Combinatorial
TIDI
D pin to O pin propagation delay, no Delay
0.15
0.19
0.17
0.22
0.20
0.25
0.23
0.28
ns
ns
TIDID
DDLY pin to O pin propagation delay (using IODELAY)
Sequential Delays
TIDLO
D pin to Q1 pin using flip-flop as a latch without Delay
DDLY pin to Q1 pin using flip-flop as a latch (using IODELAY)
CLK to Q outputs
0.48
0.52
0.54
0.85
7.60
0.54
0.58
0.61
0.97
7.60
0.64
0.68
0.70
1.15
10.51
0.73
0.78
0.93
1.32
10.51
ns
ns
ns
ns
ns
TIDLOD
TICKQ
TRQ_ILOGIC
TGSRQ_ILOGIC
Set/Reset
TRPW_ILOGIC
SR pin to OQ/TQ out
Global Set/Reset to Q outputs
Minimum Pulse Width, SR inputs
0.78
0.95
1.20
1.30
ns, Min
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
37
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 50: OLOGIC Switching Characteristics
Speed Grade
Units
Symbol
Description
-3
-2
-1 (XC)
-1 (XQ)
-1L
Setup/Hold
TODCK/TOCKD
D1/D2 pins Setup/Hold with respect to CLK
OCE pin Setup/Hold with respect to CLK
SR pin Setup/Hold with respect to CLK
T1/T2 pins Setup/Hold with respect to CLK
TCE pin Setup/Hold with respect to CLK
0.45/
–0.08
0.50/
–0.08
0.54/
–0.08
0.54/
–0.08
0.69/
–0.11
ns
ns
ns
ns
ns
TOOCECK/TOCKOCE
0.17/
–0.03
0.20/
–0.03
0.22/
–0.03
0.27/
–0.05
0.27/
–0.04
TOSRCK/TOCKSR
0.59/
–0.24
0.62/
–0.24
0.54/
–0.08
0.54/
–0.08
0.79/
–0.35
TOTCK/TOCKT
0.44/
–0.07
0.51/
–0.07
0.56/
–0.07
0.60/
–0.10
0.68/
–0.13
TOTCECK/TOCKTCE
0.15/
–0.04
0.19/
–0.04
0.21/
–0.04
0.27/
–0.05
0.29/
–0.05
Combinatorial
TDOQ
D1 to OQ out or T1 to TQ out
0.78
0.87
1.01
1.01
1.15
ns
Sequential Delays
TOCKQ
CLK to OQ/TQ out
0.54
0.80
7.60
0.61
0.90
7.60
0.71
1.05
0.71
1.05
0.80
1.19
ns
ns
ns
TRQ
SR pin to OQ/TQ out
TGSRQ
Global Set/Reset to Q outputs
10.51
10.51
10.51
Set/Reset
TRPW
Minimum Pulse Width, SR inputs
0.78
0.95
1.20
1.20
1.30
ns, Min
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
38
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Input Serializer/Deserializer Switching Characteristics
Table 51: ISERDES Switching Characteristics
Speed Grade
Symbol
Description
Units
-3
-2
-1 (XC) -1 (XQ)
-1L
Setup/Hold for Control Lines
TISCCK_BITSLIP/ TISCKC_BITSLIP BITSLIP pin Setup/Hold with respect to
CLKDIV
0.07/
0.15
0.08/
0.16
0.09/
0.17
0.09/
0.17
0.14/
0.17
ns
ns
ns
(2)
TISCCK_CE / TISCKC_CE
CE pin Setup/Hold with respect to CLK
(for CE1)
0.20/
0.03
0.25/
0.04
0.27/
0.04
0.27/
0.04
0.31/
0.05
(2)
T
ISCCK_CE2 / TISCKC_CE2
CE pin Setup/Hold with respect to CLKDIV
(for CE2)
0.01/
0.27
0.01
0.29
0.01/
0.31
0.01/
0.31
–0.05/
0.35
Setup/Hold for Data Lines
TISDCK_D /TISCKD_D
D pin Setup/Hold with respect to CLK
0.07/
0.08
0.08/
0.09
0.09/
0.11
0.09/
0.11
0.11/
0.19
ns
ns
ns
ns
TISDCK_DDLY /TISCKD_DDLY
DDLY pin Setup/Hold with respect to CLK
(using IODELAY)(1)
0.10/
0.05
0.12/
0.06
0.14/
0.07
0.14/
0.07
0.16/
0.15
TISDCK_D_DDR /TISCKD_D_DDR
D pin Setup/Hold with respect to CLK at
DDR mode
0.07/
0.08
0.08/
0.09
0.09/
0.11
0.09/
0.11
0.11/
0.19
TISDCK_DDLY_DDR
TISCKD_DDLY_DDR
D pin Setup/Hold with respect to CLK at
DDR mode (using IODELAY)(1)
0.10/
0.05
0.12/
0.06
0.14/
0.07
0.14/
0.07
0.16/
0.15
Sequential Delays
TISCKO_Q
CLKDIV to out at Q pin
D input to DO output pin
0.57
0.19
0.66
0.22
0.75
0.25
0.80
0.25
0.88
0.28
ns
ns
Propagation Delays
TISDO_DO
Notes:
1. Recorded at 0 tap value.
2.
T
and T
are reported as T
/T
in TRACE report.
ISCCK_CE2
ISCKC_CE2
ISCCK_CE ISCKC_CE
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
39
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Output Serializer/Deserializer Switching Characteristics
Table 52: OSERDES Switching Characteristics
Speed Grade
Symbol Description
Units
-3
-2
-1 (XC) -1 (XQ)
-1L
Setup/Hold
TOSDCK_D/TOSCKD_D
D input Setup/Hold with respect to CLKDIV
T input Setup/Hold with respect to CLK
T input Setup/Hold with respect to CLKDIV
OCE input Setup/Hold with respect to CLK
0.23/
–0.10
0.28/
–0.10
0.31/
–0.10
0.35/
–0.10
0.36/
–0.15
ns
ns
ns
ns
ns
ns
(1)
TOSDCK_T/TOSCKD_T
0.44/
–0.10
0.51/
–0.09
0.56/
–0.08
0.60/
–0.08
0.68/
–0.15
(1)
T
OSDCK_T2/TOSCKD_T2
TOSCCK_OCE/TOSCKC_OCE
TOSCCK_S
OSCCK_TCE/TOSCKC_TCE
0.25/
–0.10
0.27/
–0.09
0.31/
–0.08
0.31/
–0.08
0.47/
–0.15
0.17/
–0.03
0.20/
–0.03
0.22/
–0.03
0.27/
–0.03
0.27/
–0.04
SR (Reset) input Setup with respect to
CLKDIV
0.07
0.07
0.07
0.07
0.08
T
TCE input Setup/Hold with respect to CLK
0.15/
–0.04
0.19/
–0.04
0.21/
–0.04
0.27/
–0.04
0.29/
–0.05
Sequential Delays
TOSCKO_OQ
Clock to out from CLK to OQ
Clock to out from CLK to TQ
0.63
0.63
0.71
0.71
0.82
0.82
0.82
0.82
0.93
0.93
ns
ns
TOSCKO_TQ
Combinatorial
TOSDO_TTQ
T input to TQ Out
0.76
0.84
0.97
0.97
1.11
ns
Notes:
1.
T
and T
are reported as T
/T
in TRACE report.
OSDCK_T2
OSCKD_T2
OSDCK_T OSCKD_T
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
40
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Input/Output Delay Switching Characteristics
Table 53: Input/Output Delay Switching Characteristics
Speed Grade
Symbol
Description
Units
-3
-2
-1
-1L
IDELAYCTRL
TDLYCCO_RDY
Reset to Ready for IDELAYCTRL
REFCLK frequency = 200.0(1)
REFCLK frequency = 300.0(1)
REFCLK precision
3.00
200
3.00
200
3.00
200
–
3.25
200
–
µs
FIDELAYCTRL_REF
MHz
MHz
MHz
ns
300
300
IDELAYCTRL_REF_PRECISION
TIDELAYCTRL_RPW
10
10
10
10
Minimum Reset pulse width
50.00
50.00
50.00
52.50
IODELAY
TIDELAYRESOLUTION
IODELAY Chain Delay Resolution
1/(32 x 2 x FREF
)
ps
Pattern dependent period jitter in delay
chain for clock pattern.(2)
0
5
0
0
0
5
ps
per tap
Pattern dependent period jitter in delay
chain for random data pattern
(PRBS 23).(3)
5
5
ps
per tap
TIDELAYPAT_JIT
Pattern dependent period jitter in delay
chain for random data pattern
(PRBS 23).(4)
9
9
9
9
ps
per tap
TIODELAY_CLK_MAX
Maximum frequency of CLK input to
IODELAY
500.00
420.00
300.00
300.00
MHz
ns
TIODCCK_CE / TIODCKC_CE
CE pin Setup/Hold with respect to CK
INC pin Setup/Hold with respect to CK
RST pin Setup/Hold with respect to CK
0.45/
–0.09
0.53/
–0.09
0.65/
–0.09
0.84/
–0.14
T
IODCK_INC/ TIODCKC_INC
TIODCCK_RST/ TIODCKC_RST
TIODDO_T
0.23/
–0.02
0.27/
–0.01
0.31/
0.00
0.27/
–0.04
ns
0.57/
–0.08
0.62/
–0.08
0.69/
–0.08
0.74/
–0.13
ns
TSCONTROL delay to MUXE/MUXF
switching and through IODELAY
Note 5
Note 5
Note 5
Note 5
ps
TIODDO_IDATAIN
TIODDO_ODATAIN
Propagation delay through IODELAY
Propagation delay through IODELAY
Note 5
Note 5
Note 5
Note 5
Note 5
Note 5
Note 5
Note 5
ps
ps
Notes:
1. Average Tap Delay at 200 MHz = 78 ps, at 300 MHz = 52 ps.
2. When HIGH_PERFORMANCE mode is set to TRUE or FALSE.
3. When HIGH_PERFORMANCE mode is set to TRUE
4. When HIGH_PERFORMANCE mode is set to FALSE.
5. Delay depends on IODELAY tap setting. See TRACE report for actual values.
CLB Switching Characteristics
Table 54: CLB Switching Characteristics
Speed Grade
Symbol
Description
Units
-3
-2
-1
-1L
Combinatorial Delays
TILO
An – Dn LUT address to A
0.06
0.18
0.28
0.07
0.20
0.31
0.07
0.22
0.36
0.09
0.25
0.40
ns, Max
ns, Max
ns, Max
An – Dn LUT address to AMUX/CMUX
An – Dn LUT address to BMUX_A
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
41
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 54: CLB Switching Characteristics (Cont’d)
Speed Grade
Units
Symbol
Description
-3
-2
-1
-1L
TITO
An – Dn inputs to A – D Q outputs
AX inputs to AMUX output
AX inputs to BMUX output
AX inputs to CMUX output
AX inputs to DMUX output
BX inputs to BMUX output
BX inputs to DMUX output
CX inputs to CMUX output
CX inputs to DMUX output
DX inputs to DMUX output
An input to COUT output
Bn input to COUT output
Cn input to COUT output
Dn input to COUT output
AX input to COUT output
BX input to COUT output
CX input to COUT output
DX input to COUT output
CIN input to COUT output
CIN input to AMUX output
CIN input to BMUX output
CIN input to CMUX output
CIN input to DMUX output
0.59
0.31
0.35
0.39
0.42
0.30
0.38
0.26
0.30
0.30
0.32
0.32
0.27
0.25
0.25
0.22
0.15
0.14
0.06
0.21
0.23
0.23
0.25
0.67
0.35
0.39
0.44
0.47
0.34
0.43
0.29
0.34
0.33
0.36
0.36
0.30
0.28
0.28
0.24
0.17
0.16
0.07
0.24
0.25
0.26
0.29
0.79
0.42
0.47
0.52
0.55
0.39
0.50
0.34
0.40
0.38
0.41
0.41
0.34
0.32
0.33
0.28
0.20
0.19
0.08
0.28
0.29
0.30
0.33
0.85
0.44
0.50
0.56
0.60
0.44
0.55
0.37
0.44
0.43
0.47
0.47
0.40
0.37
0.36
0.31
0.22
0.21
0.09
0.30
0.31
0.33
0.36
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
TAXA
TAXB
TAXC
TAXD
TBXB
TBXD
TCXC
TCXD
TDXD
TOPCYA
TOPCYB
TOPCYC
TOPCYD
TAXCY
TBXCY
TCXCY
TDXCY
TBYP
TCINA
TCINB
TCINC
TCIND
Sequential Delays
TCKO
Clock to AQ – DQ outputs
0.29
0.36
0.33
0.40
0.39
0.47
0.44
0.53
ns, Max
ns, Max
TSHCKO
Clock to AMUX – DMUX outputs
Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK
T
DICK/TCKDI
A – D input to CLK on A – D Flip Flops
CE input to CLK on A – D Flip Flops
0.30/0.17 0.36/0.18 0.43/0.20 0.44/0.25
0.20/0.00 0.25/0.00 0.32/0.00 0.32/0.01
ns, Min
ns, Min
TCECK_CLB
/
TCKCE_CLB
TSRCK/TCKSR
CINCK/TCKCIN
SR input to CLK on A – D Flip Flops
CIN input to CLK on A – D Flip Flops
0.39/–0.07 0.44/–0.07 0.52/–0.07 0.58/–0.08
0.16/0.12 0.19/0.14 0.24/0.16 0.23/0.22
ns, Min
ns, Min
T
Set/Reset
TSRMIN
TRQ
SR input minimum pulse width
0.90
0.52
0.90
0.58
0.97
0.68
0.80
0.77
ns, Min
ns, Max
ns, Max
MHz
Delay from SR input to AQ – DQ flip-flops
Delay from CE input to AQ – DQ flip-flops
Toggle frequency (for export control)
TCEO
0.41
0.48
0.59
0.61
FTOG
1412.00
1286.40
1098.00
1098.00
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but if a “0” is
listed, there is no positive hold time.
2. These items are of interest for Carry Chain applications.
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
42
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
CLB Distributed RAM Switching Characteristics (SLICEM Only)
Table 55: CLB Distributed RAM Switching Characteristics
Speed Grade
Symbol
Description
Units
-3
-2
-1
-1L
Sequential Delays
TSHCKO
Clock to A – B outputs
0.92
1.19
1.10
1.40
1.36
1.71
1.49
1.87
ns, Max
ns, Max
TSHCKO_1
Clock to AMUX – BMUX outputs
Setup and Hold Times Before/After Clock CLK
T
DS/TDH
TAS/TAH
WS/TWH
A – D inputs to CLK
Address An inputs to clock
WE input to clock
0.62/0.18
0.19/0.52
0.27/0.00
0.28/–0.01
0.72/0.20
0.22/0.59
0.32/0.00
0.34/–0.01
0.88/0.22
0.27/0.66
0.40/0.00
0.41/–0.01
0.98/0.23
0.30/0.75
0.47/–0.03
0.48/–0.05
ns, Min
ns, Min
ns, Min
ns, Min
T
TCECK/TCKCE
Clock CLK
TMPW
CE input to CLK
Minimum pulse width
Minimum clock period
0.70
1.40
0.82
1.64
1.00
2.00
1.04
2.08
ns, Min
ns, Min
TMCP
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case”, but if a “0” is
listed, there is no positive hold time.
2.
T
also represents the CLK to XMUX output. Refer to TRACE report for the CLK to XMUX path.
SHCKO
CLB Shift Register Switching Characteristics (SLICEM Only)
Table 56: CLB Shift Register Switching Characteristics
Speed Grade
Symbol
Description
Units
-3
-2
-1
-1L
Sequential Delays
TREG
Clock to A – D outputs
1.11
1.37
1.08
1.30
1.60
1.27
1.58
1.93
1.55
1.74
2.12
1.74
ns, Max
ns, Max
ns, Max
TREG_MUX
TREG_M31
Clock to AMUX – DMUX output
Clock to DMUX output via M31 output
Setup and Hold Times Before/After Clock CLK
T
WS/TWH
TCECK/TCKCE
DS/TDH
WE input
0.05/0.00
0.07/0.00
0.09/0.00
0.11/0.03
ns, Min
ns, Min
ns, Min
CE input to CLK
A – D inputs to CLK
0.06/–0.01 0.08/–0.01 0.10/–0.01 0.12/0.02
T
0.64/0.18
0.60
0.76/0.21
0.70
0.94/0.24
0.85
1.07/0.23
0.89
Clock CLK
TMPW
Minimum pulse width
ns, Min
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case”, but if a “0” is
listed, there is no positive hold time.
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
43
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Block RAM and FIFO Switching Characteristics
Table 57: Block RAM and FIFO Switching Characteristics
Speed Grade
Symbol
Description
Units
-3
-2
-1
-1L
Block RAM and FIFO Clock-to-Out Delays
(1)
TRCKO_DO and TRCKO_DO_REG
Clock CLK to DOUT output
(without output register)(2)(3)
1.60
0.60
2.62
0.71
2.49
1.29
1.79
0.66
2.89
0.77
2.77
1.41
2.08
0.75
3.30
0.86
3.18
1.58
2.36
0.83
3.73
0.94
3.61
1.79
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
Clock CLK to DOUT output
(with output register)(4)(5)
T
RCKO_DO_ECC and
Clock CLK to DOUT output with ECC
(without output register)(2)(3)
TRCKO_DO_ECC_REG
Clock CLK to DOUT output with ECC
(with output register)(4)(5)
TRCKO_CASC and
TRCKO_CASC_REG
Clock CLK to DOUT output with Cascade
(without output register)(2)
Clock CLK to DOUT output with Cascade
(with output register)(4)
TRCKO_FLAGS
Clock CLK to FIFO flags outputs(6)
0.74
0.90
0.62
2.21
0.86
0.81
0.98
0.68
2.46
0.94
0.91
1.09
0.76
2.84
1.06
0.98
1.21
0.82
3.23
1.18
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
TRCKO_POINTERS
Clock CLK to FIFO pointers outputs(7)
Clock CLK to BITERR (with output register)
Clock CLK to BITERR (without output register)
T
RCKO_SDBIT_ECC and
TRCKO_SDBIT_ECC_REG
TRCKO_PARITY_ECC
Clock CLK to ECCPARITY in ECC encode only
mode
TRCKO_RDADDR_ECC and
TRCKO_RDADDR_ECC_REG
Clock CLK to RDADDR output with ECC
(without output register)
0.73
0.76
0.79
0.82
0.90
0.92
1.00
1.02
ns, Max
ns, Max
Clock CLK to RDADDR output with ECC
(with output register)
Setup and Hold Times Before/After Clock CLK
T
RCCK_ADDR/TRCKC_ADDR
ADDR inputs(8)
0.47/
0.27
0.53/
0.29
0.62/
0.32
0.66/
0.34
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
T
RDCK_DI/TRCKD_DI
DIN inputs(9)
0.84/
0.30
0.95/
0.32
1.11/
0.34
1.26/
0.36
TRDCK_DI_ECC/TRCKD_DI_ECC
DIN inputs with block RAM ECC in standard mode(9) 0.47/
0.30
0.52/
0.32
0.59/
0.34
0.68/
0.36
DIN inputs with block RAM ECC encode only(9)
DIN inputs with FIFO ECC in standard mode(9)
Inject single/double bit error in ECC mode
Block RAM Enable (EN) input
0.68/
0.30
0.75/
0.32
0.85/
0.34
0.97/
0.36
0.77/
0.30
0.87/
0.32
1.02/
0.34
1.16/
0.36
TRCCK_CLK/TRCKC_CLK
0.90/
0.27
1.02/
0.28
1.20/
0.29
1.56/
0.29
TRCCK_RDEN/TRCKC_RDEN
0.31/
0.26
0.35/
0.27
0.41/
0.30
0.44/
0.31
T
RCCK_REGCE/TRCKC_REGCE
TRCCK_RSTREG/TRCKC_RSTREG
RCCK_RSTRAM/TRCKC_RSTRAM
CE input of output register
0.18/
0.25
0.19/
0.27
0.22/
0.31
0.24/
0.33
Synchronous RSTREG input
0.22/
0.23
0.24/
0.24
0.28/
0.26
0.31/
0.27
T
Synchronous RSTRAM input
0.32/
0.23
0.36/
0.24
0.41/
0.27
0.46/
0.29
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
44
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 57: Block RAM and FIFO Switching Characteristics (Cont’d)
Speed Grade
Symbol
Description
Units
-3
-2
-1
-1L
TRCCK_WE/TRCKC_WE
Write Enable (WE) input (Block RAM only)
0.44/
0.19
0.47/
0.25
0.52/
0.35
0.67/
0.24
ns, Min
TRCCK_WREN/TRCKC_WREN
WREN FIFO inputs
RDEN FIFO inputs
0.47/
0.26
0.50/
0.27
0.55/
0.30
0.68/
0.31
ns, Min
ns, Min
T
RCCK_RDEN/TRCKC_RDEN
0.46/
0.26
0.50/
0.27
0.55/
0.30
0.67/
0.31
Reset Delays
TRCO_FLAGS
Reset RST to FIFO Flags/Pointers(10)
FIFO reset timing(11)
0.90
0.98
1.10
1.23
ns, Max
ns, Min
T
RCCK_RSTREG/TRCKC_RSTREG
0.22/
0.23
0.24/
0.24
0.28/
0.26
0.31/
0.27
Maximum Frequency
FMAX
Block RAM in TDP and SDP modes
(Write First and No Change modes)
600
540
450
340
MHz
Block RAM (Read First mode)
Block RAM (SDP mode)(12)
525
525
550
475
475
490
400
400
400
275
275
300
MHz
MHz
MHz
FMAX_CASCADE
Block RAM Cascade
(Write First and No Change modes)
Block RAM Cascade (Read First mode)
FIFO in all modes
475
600
450
425
540
400
350
450
325
235
340
250
MHz
MHz
MHz
FMAX_FIFO
FMAX_ECC
Block RAM and FIFO in ECC configuration
Notes:
1. TRACE will report all of these parameters as T
.
RCKO_DO
2.
3. These parameters also apply to synchronous FIFO with DO_REG = 0.
4. includes T as well as the B port equivalent timing parameters.
5. These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG = 1.
T
includes T
, T
, and T
as well as the B port equivalent timing parameters.
RCKO_DOR
RCKO_DOW RCKO_DOPR
RCKO_DOPW
T
RCKO_DO
RCKO_DOP
6.
7.
T
T
includes the following parameters: T
, T , T , T , T , T
RCKO_FLAGS
RCKO_AEMPTY RCKO_AFULL RCKO_EMPTY RCKO_FULL RCKO_RDERR RCKO_WRERR.
includes both T
and T
RCKO_POINTERS
RCKO_RDCOUNT
RCKO_WRCOUNT.
8. The ADDR setup and hold must be met when EN is asserted (even when WE is deasserted). Otherwise, block RAM data corruption is
possible.
9.
T
includes both A and B inputs as well as the parity inputs of A and B.
RCKO_DI
10. T
includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT.
RCO_FLAGS
11. The FIFO reset must be asserted for at least three positive clock edges.
12. When using ISE software v12.4 or later, if the RDADDR_COLLISION_HWCONFIG attribute is set to PERFORMANCE or the block RAM is
in single-port operation, then the faster F
for WRITE_FIRST/NO_CHANGE modes apply.
MAX
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
45
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
DSP48E1 Switching Characteristics
Table 58: DSP48E1 Switching Characteristics
Speed Grade
Symbol
Description
Units
-1
(XC)
-1
(XQ)
-3
-2
-1L
Setup and Hold Times of Data/Control Pins to the Input Register Clock
{A, ACIN, B, BCIN} input to
{A, B} register CLK
0.25/ 0.29/ 0.35/
0.27 0.30 0.34
0.36/ 0.46/
0.34 0.39
ns
T
T
/
DSPDCK_{A, ACIN; B, BCIN}_{AREG; BREG}
DSPCKD_{A, ACIN; B, BCIN}_{AREG; BREG}
C input to C register CLK
0.16/ 0.19/ 0.22/
0.20 0.22 0.24
0.25/ 0.33/
0.24 0.30
ns
ns
T
/T
DSPDCK_C_CREG DSPCKD_C_CREG
D input to D register CLK
0.07/ 0.10/ 0.15/
0.31 0.34 0.39
0.16/ 0.24/
0.39 0.45
T
/T
DSPDCK_D_DREG DSPCKD_D_DREG
Setup and Hold Times of Data Pins to the Pipeline Register Clock
TDSPDCK_{A, ACIN, B, BCIN}_MREG_MULT
TDSPCKD_{A, ACIN, B, BCIN}_MREG_MULT
/
{A, ACIN, B, BCIN} input to
M register CLK
2.36/ 2.70/ 3.21/
0.04 0.04 0.04
3.21/ 3.66/
0.04 0.02
ns
ns
TDSPDCK_{A, D}_ADREG
/
{A, D} input to AD register CLK
1.24/ 1.42/ 1.69/
0.10 0.12 0.13
1.69/ 1.91/
0.13 0.16
TDSPCKD_{A, D}_ADREG
Setup and Hold Times of Data/Control Pins to the Output Register Clock
{A, ACIN, B, BCIN} input to
P register CLK using multiplier
3.83/ 4.37/ 5.20/
–0.13 –0.13 –0.13 –0.13 –0.24
5.20/ 5.94/
ns
T
T
/
DSPDCK_{A, ACIN, B, BCIN}_PREG_MULT
DSPCKD_{A, ACIN, B, BCIN}_PREG_MULT
D input to P register CLK
3.62/ 4.13/ 4.90/
–0.47 –0.47 –0.47 –0.47 –0.77
4.90/ 5.61/
ns
ns
T
/ T
DSPDCK_D_PREG_MULT DSPCKD_D_PREG_MULT
{A, ACIN, B, BCIN} input to
P register CLK not using
multiplier
1.59/ 1.81/ 2.15/ 2.15/ 2.44/
–0.13 –0.13 –0.13 –0.13 –0.24
T
T
/
DSPDCK_{A, ACIN, B, BCIN}_PREG
DSPCKD_{A, ACIN, B, BCIN}_PREG
C input to P register CLK
1.42/ 1.61/ 1.91/
–0.10 –0.10 –0.10 –0.10 –0.19
1.91/ 2.16/
ns
ns
T
/ T
DSPDCK_C_PREG DSPCKD_C_PREG
TDSPDCK_{PCIN, CARRYCASCIN, MULTSIGNIN}_PREG
TDSPCKD_{PCIN, CARRYCASCIN, MULTSIGNIN}_PREG
/
{PCIN, CARRYCASCIN,
MULTSIGNIN} input to
P register CLK
1.23/ 1.41/ 1.67/ 1.67/ 1.91/
–0.02 –0.02 –0.02 –0.02 –0.07
Setup and Hold Times of the CE Pins
{CEA; CEB} input to {A; B}
register CLK
0.14/ 0.17/ 0.22/
0.19 0.22 0.25
0.22/ 0.30/
0.25 0.28
ns
ns
ns
ns
ns
T
T
/
DSPDCK_{CEA; CEB}_{AREG; BREG}
DSPCKD_{CEA; CEB}_{AREG; BREG}
CEC input to C register CLK
CED input to D register CLK
CEM input to M register CLK
CEP input to P register CLK
0.15/ 0.18/ 0.24/
0.18 0.20 0.23
0.24/ 0.31/
0.23 0.26
T
T
T
T
/ T
DSPDCK_CEC_CREG DSPCKD_CEC_CREG
0.20/ 0.24/ 0.31/
0.12 0.13 0.14
0.31/ 0.43/
0.14 0.16
/ T
DSPDCK_CED_DREG DSPCKD_CED_DREG
0.16/ 0.20/ 0.26/
0.19 0.21 0.25
0.26/ 0.32/
0.25 0.28
/ T
DSPDCK_CEM_MREG DSPCKD_CEM_MREG
0.32/ 0.38/ 0.46/
0.02 0.02 0.03
0.46/ 0.54/
0.03 0.04
/ T
DSPDCK_CEP_PREG DSPCKD_CEP_PREG
Setup and Hold Times of the RST Pins
{RSTA, RSTB} input to {A, B}
register CLK
0.27/ 0.31/ 0.38/
0.17 0.19 0.22
0.38/ 0.41/
0.22 0.25
ns
ns
ns
ns
T
T
/
DSPDCK_{RSTA; RSTB}_{AREG; BREG}
DSPCKD_{RSTA; RSTB}_{AREG; BREG}
RSTC input to C register CLK
RSTD input to D register CLK
RSTM input to M register CLK
0.18/ 0.20/ 0.23/
0.08 0.08 0.09
0.23/ 0.27/
0.09 0.11
T
T
T
/ T
DSPDCK_RSTC_CREG DSPCKD_RSTC_CREG
0.28/ 0.32/ 0.38/
0.15 0.16 0.19
0.38/ 0.45/
0.19 0.21
/ T
DSPDCK_RSTD_DREG DSPCKD_RSTD_DREG
0.20/ 0.23/ 0.26/
0.24 0.26 0.30
0.26/ 0.29/
0.30 0.34
/ T
DSPDCK_RSTM_MREG DSPCKD_RSTM_MREG
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
46
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Speed Grade
Table 58: DSP48E1 Switching Characteristics (Cont’d)
Symbol
Description
Units
-1
(XC)
-1
(XQ)
-3
-2
-1L
RSTP input to P register CLK
0.26/ 0.30/ 0.35/
0.35/ 0.43/
ns
T
/ T
DSPDCK_RSTP_PREG DSPCKD_RSTP_PREG
0.04 0.04
0.05
0.05
0.06
Combinatorial Delays from Input Pins to Output Pins
TDSPDO_{A, B}_{P, CARRYOUT}_MULT
{A, B} input to {P, CARRYOUT}
output using multiplier
3.76 4.29
3.57 4.07
1.55 1.76
1.38 1.56
5.08
4.82
2.07
1.83
5.08
4.82
2.07
1.83
5.87
5.57
2.41
2.13
ns
ns
ns
ns
TDSPDO_D_{P, CARRYOUT}_MULT
TDSPDO_{A, B}_{P, CARRYOUT}
D input to {P, CARRYOUT}
output using multiplier
{A, B} input to {P, CARRYOUT}
output not using multiplier
TDSPDO_{C, CARRYIN}_{P, CARRYOUT}
{C, CARRYIN} input to {P,
CARRYOUT} output
Combinatorial Delays from Input Pins to Cascading Output Pins
TDSPDO_{A; B}_{ACOUT; BCOUT}
{A, B} input to {ACOUT, BCOUT} 0.49 0.56
output
0.65
5.24
0.65
5.24
0.73
6.09
ns
ns
TDSPDO_{A, B}_{PCOUT, CARRYCASCOUT,
MULTSIGNOUT}_MULT
{A, B} input to {PCOUT,
CARRYCASCOUT,
MULTSIGNOUT} output using
multiplier
3.87 4.42
3.66 4.17
1.64 1.86
TDSPDO_D_{PCOUT, CARRYCASCOUT,
MULTSIGNOUT}_MULT
D input to {PCOUT,
CARRYCASCOUT,
MULTSIGNOUT} output using
multiplier
4.94
2.19
1.95
4.94
2.19
1.95
5.76
2.60
2.32
ns
ns
ns
TDSPDO_{A, B}_{PCOUT, CARRYCASCOUT, MULTSIGNOUT}
{A, B} input to {PCOUT,
CARRYCASCOUT,
MULTSIGNOUT} output not
using multiplier
TDSPDO__{C, CARRYIN}_{PCOUT,
CARRYCASCOUT,MULTSIGNOUT}
{C, CARRYIN} input to {PCOUT, 1.46 1.66
CARRYCASCOUT,
MULTSIGNOUT} output
Combinatorial Delays from Cascading Input Pins to All Output Pins
TDSPDO_{ACIN, BCIN}_{P, CARRYOUT}_MULT
TDSPDO_{ACIN, BCIN}_{P, CARRYOUT
TDSPDO_{ACIN; BCIN}_{ACOUT; BCOUT}
{ACIN, BCIN} input to {P,
CARRYOUT} output using
multiplier
3.67 4.19
1.43 1.63
4.97
1.92
4.97
1.92
5.75
2.25
ns
ns
{ACIN, BCIN} input to {P,
CARRYOUT} output not using
multiplier
{ACIN, BCIN} input to {ACOUT,
BCOUT} output
0.36 0.42
3.76 4.29
0.49
5.10
0.49
5.10
0.56
5.94
ns
ns
TDSPDO_{ACIN, BCIN}_{PCOUT, CARRYCASCOUT,
MULTSIGNOUT}_MULT
{ACIN, BCIN} input to {PCOUT,
CARRYCASCOUT,
MULTSIGNOUT} output using
multiplier
TDSPDO_{ACIN, BCIN}_{PCOUT, CARRYCASCOUT,
MULTSIGNOUT}
{ACIN, BCIN} input to {PCOUT,
CARRYCASCOUT,
MULTSIGNOUT} output not
using multiplier
1.52 1.73
1.19 1.35
2.05
1.60
2.05
1.60
2.44
1.87
ns
ns
TDSPDO_{PCIN, CARRYCASCIN, MULTSIGNIN}_
{P, CARRYOUT}
{PCIN, CARRYCASCIN,
MULTSIGNIN} input to {P,
CARRYOUT} output
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
47
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Speed Grade
Table 58: DSP48E1 Switching Characteristics (Cont’d)
Symbol
Description
Units
-1
(XC)
-1
(XQ)
-3
-2
-1L
TDSPDO_{PCIN, CARRYCASCIN, MULTSIGNIN}_
{PCOUT, CARRYCASCOUT, MULTSIGNOUT}
{PCIN, CARRYCASCIN,
MULTSIGNIN} input to {PCOUT,
CARRYCASCOUT,
1.28 1.46
1.72
1.72
2.06
ns
MULTSIGNOUT} output
Clock to Outs from Output Register Clock to Output Pins
TDSPCKO_{P, CARRYOUT}_PREG
CLK (PREG) to {P, CARRYOUT} 0.38 0.43
output
0.50
0.66
0.50
0.66
0.57
0.76
ns
ns
TDSPCKO_{PCOUT, CARRYCASCOUT, MULTSIGNOUT}_PREG CLK (PREG) to
{CARRYCASCOUT, PCOUT,
MULTSIGNOUT} output
0.50 0.56
Clock to Outs from Pipeline Register Clock to Output Pins
TDSPCKO_{P, CARRYOUT}_MREG
CLK (MREG) to {P, CARRYOUT} 1.72 1.96
output
2.30
2.43
2.30
2.43
2.69
2.88
ns
ns
TDSPCKO_{PCOUT, CARRYCASCOUT, MULTSIGNOUT}_MREG CLK (MREG) to {PCOUT,
1.81 2.06
CARRYCASCOUT,
MULTSIGNOUT} output
TDSPCKO_{P, CARRYOUT}_ADREG_MULT
CLK (ADREG) to {P,
CARRYOUT} output
2.79 3.16
2.87 3.26
3.72
3.84
3.72
3.84
4.32
4.51
ns
ns
TDSPCKO_{PCOUT, CARRYCASCOUT,
MULTSIGNOUT}_ADREG_MULT
CLK (ADREG) to {PCOUT,
CARRYCASCOUT,
MULTSIGNOUT} output
Clock to Outs from Input Register Clock to Output Pins
TDSPCKO_{P, CARRYOUT}_{AREG, BREG}_MULT CLK (AREG, BREG) to {P,
3.97 4.52
1.70 1.93
5.36
2.27
5.36
2.27
6.20
2.65
ns
ns
CARRYOUT} output using
multiplier
TDSPCKO_{P, CARRYOUT}_{AREG, BREG}
CLK (AREG, BREG) to {P,
CARRYOUT} output not using
multiplier
TDSPCKO_{P, CARRYOUT}_CREG
CLK (CREG) to {P, CARRYOUT} 1.70 1.93
output
2.27
5.25
2.27
5.25
2.80
6.07
ns
ns
TDSPCKO_{P, CARRYOUT}_DREG_MULT
CLK (DREG) to {P, CARRYOUT} 3.89 4.44
output
Clock to Outs from Input Register Clock to Cascading Output Pins
TDSPCKO_{ACOUT; BCOUT}_{AREG; BREG}
CLK (AREG, BREG) to {P,
CARRYOUT} output
0.66 0.76
0.89
5.49
0.89
5.49
1.01
6.39
ns
ns
TDSPCKO_{PCOUT, CARRYCASCOUT,
MULTSIGNOUT}_{AREG, BREG}_MULT
CLK (AREG, BREG) to {PCOUT, 4.05 4.63
CARRYCASCOUT,
MULTSIGNOUT} output using
multiplier
TDSPCKO_{PCOUT, CARRYCASCOUT,
MULTSIGNOUT}_{AREG, BREG}
CLK (AREG, BREG) to {PCOUT, 1.79 2.03
CARRYCASCOUT,
MULTSIGNOUT} output not
using multiplier
2.40
5.38
2.40
2.40
5.38
2.40
2.84
6.26
2.99
ns
ns
ns
TDSPCKO_{PCOUT, CARRYCASCOUT,
MULTSIGNOUT}_DREG_MULT
CLK (DREG) to {PCOUT,
CARRYCASCOUT,
MULTSIGNOUT} output using
multiplier
3.98 4.54
1.78 2.03
TDSPCKO_{PCOUT, CARRYCASCOUT, MULTSIGNOUT}_CREG CLK (CREG) to {PCOUT,
CARRYCASCOUT,
MULTSIGNOUT} output
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
48
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Speed Grade
Table 58: DSP48E1 Switching Characteristics (Cont’d)
Symbol
Description
Units
-1
(XC)
-1
(XQ)
-3
-2
-1L
Maximum Frequency
FMAX
With all registers used
With pattern detector
600
551
356
540
483
311
450
408
262
450
408
262
410 MHz
356 MHz
224 MHz
FMAX_PATDET
FMAX_MULT_NOMREG
Two register multiply without
MREG
FMAX_MULT_NOMREG_PATDET
Two register multiply without
MREG with pattern detect
327
286
241
241
211 MHz
FMAX_PREADD_MULT_NOADREG
Without ADREG
398
398
347
347
292
292
292
292
254 MHz
254 MHz
FMAX_PREADD_MULT_NOADREG_PATDET
Without ADREG with pattern
detect
FMAX_NOPIPELINEREG
Without pipeline registers
(MREG, ADREG)
266
250
233
219
196
184
196
184
171 MHz
160 MHz
FMAX_NOPIPELINEREG_PATDET
Without pipeline registers
(MREG, ADREG) with pattern
detect
Configuration Switching Characteristics
Table 59: Configuration Switching Characteristics
Speed Grade
Symbol
Description
Units
-3
-2
-1
-1L
Power-up Timing Characteristics
(1)
TPL
Program Latency
Power-on-Reset
5
5
5
5
ms, Max
(1)
TPOR
15/55
400
15/55
400
15/55
400
15/60 ms, Min/Max
TICCK
CCLK (output) delay
Program Pulse Width
400
250
ns, Min
ns, Min
TPROGRAM
250
250
250
Master/Slave Serial Mode Programming Switching
TDCCK/TCCKD
DSCCK/TSCCKD
DIN Setup/Hold, slave mode
DIN Setup/Hold, master mode
DOUT at 2.5V
4.0/0.0 4.0/0.0 4.0/0.0 4.5/0.0
4.0/0.0 4.0/0.0 4.0/0.0 5.0/0.0
ns, Min
ns, Min
ns, Max
ns, Max
MHz, Max
%
T
TCCO
6
6
6
6
6
6
7
7
DOUT at 1.8V
FMCCK
Maximum CCLK frequency, serial modes
105
55
105
55
105
55
70
60
FMCCKTOL
Frequency Tolerance, master mode with respect to
nominal CCLK.
FMSCCK
Slave mode external CCLK
100
100
100
100
MHz
SelectMAP Mode Programming Switching
TSMDCCK/TSMCCKD
SelectMAP Data Setup/Hold
4.0/0.0 4.0/0.0 4.0/0.0 5.5/0.0
4.0/0.0 4.0/0.0 4.0/0.0 5.5/0.0
10.0/0.0 10.0/0.0 10.0/0.0 16.0/0.0
ns, Min
ns, Min
ns, Min
ns, Max
TSMCSCCK/TSMCCKCS
CSI_B Setup/Hold
T
SMCCKW/TSMWCCK
RDWR_B Setup/Hold
TSMCKCSO
CSO_B clock to out
6
6
6
7
(330 Ω pull-up resistor required)
TSMCO
CCLK to DATA out in readback at 2.5V
CCLK to DATA out in readback at 1.8V
6
6
6
6
6
6
7
7
ns, Max
ns, Max
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
49
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 59: Configuration Switching Characteristics (Cont’d)
Speed Grade
Symbol
Description
Units
-3
6
-2
6
-1
6
-1L
7
TSMCKBY
CCLK to BUSY out in readback at 2.5V
CCLK to BUSY out in readback at 1.8V
Maximum Frequency with respect to nominal CCLK
ns, Max
ns, Max
6
6
6
7
FSMCCK
FRBCCK
100
100
100
100
100
100
70
60
MHz, Max
MHz, Max
Maximum Readback Frequency with respect to
nominal CCLK
FMCCKTOL
Frequency tolerance, master mode with
respect to nominal CCLK
55
55
55
60
%
Boundary-Scan Port Timing Specifications
TMS and TDI Setup time before TCK/ Hold time
TTAPTCK/TTCKTAP
3.0/2.0 3.0/2.0 3.0/2.0 4.0/2.0
ns, Min
after TCK
TTCKTDO
TCK falling edge to TDO output valid at 2.5V
TCK falling edge to TDO output valid at 1.8V
Maximum configuration TCK clock frequency
6
6
6
6
6
6
7
7
ns, Max
ns, Max
FTCK
66
15
66
15
66
15
33
15
MHz, Max
MHz, Min
FTCKB_MIN
Minimum boundary-scan TCK clock frequency
when using IEEE Std 1149.6 (AC-JTAG). Minimum
operating temperature for IEEE Std 1149.6 is 0°C.
FTCKB
Maximum boundary-scan TCK clock frequency
66
66
66
33
MHz, Max
BPI Master Flash Mode Programming Switching
(2)
TBPICCO
ADDR[25:0], RS[1:0], FCS_B, FOE_B, FWE_B
outputs valid after CCLK rising edge at 2.5V
6
6
6
6
6
6
7
7
ns
ns
ADDR[25:0], RS[1:0], FCS_B, FOE_B, FWE_B
outputs valid after CCLK rising edge at 1.8V
T
BPIDCC/TBPICCD
Setup/Hold on D[15:0] data input pins
4.0/0.0 4.0/0.0 4.0/0.0 5.0/0.0
ns
TINITADDR
Minimum period of initial ADDR[25:0] address
cycles
3
3
3
3
CCLK cycles
SPI Master Flash Mode Programming Switching
TSPIDCC/TSPIDCCD DIN Setup/Hold before/after the rising CCLK edge 3.0/0.0 3.0/0.0 3.0/0.0 3.5/0.0
TSPICCM
ns
ns
ns
ns
ns
µs
MOSI clock to out at 2.5V
6
6
6
6
2
6
6
6
6
2
6
6
6
6
2
7
7
7
7
2
MOSI clock to out at 1.8V
TSPICCFC
FCS_B clock to out at 2.5V
FCS_B clock to out at 1.8V
T
FSINIT/TFSINITH
FS[2:0] to INIT_B rising edge Setup and Hold
CCLK Output (Master Modes)
TMCCKL
Master CCLK clock Low time duty cycle
45/55
45/55
45/55
45/55
45/55
45/55
40/60
40/60
%, Min/Max
%, Min/Max
TMCCKH
Master CCLK clock High time duty cycle
CCLK Input (Slave Modes)
TSCCKL
TSCCKH
Slave CCLK clock minimum Low time
Slave CCLK clock minimum High time
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
ns, Min
ns, Min
Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK
FDCK
Maximum frequency for DCLK
DADDR Setup/Hold
200
200
200
200
MHz
ns
TMMCMDCK_DADDR
TMMCMCKD_DADDR
/
1.25/
0.00
1.40/
0.00
1.63/
0.00
1.64/
0.00
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
50
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 59: Configuration Switching Characteristics (Cont’d)
Symbol Description
Speed Grade
Units
-3
-2
-1
-1L
TMMCMDCK_DI
TMMCMCKD_DI
/
DI Setup/Hold
1.25/
0.00
1.40/
0.00
1.63/
0.00
1.64/
0.00
ns
TMMCMDCK_DEN
/
DEN Setup/Hold time
DWE Setup/Hold time
1.25/
0.00
1.40/
0.00
1.63/
0.00
1.64/
0.00
ns
ns
TMMCMCKD_DEN
TMMCMDCK_DWE
TMMCMCKD_DWE
/
1.25/
0.00
1.40/
0.00
1.63/
0.00
1.64/
0.00
TMMCMCKO_DO
CLK to out of DO(3)
CLK to out of DRDY
2.60
0.32
3.02
0.34
3.64
0.38
3.68
0.38
ns
ns
TMMCMCKO_DRDY
Notes:
1. To support longer delays in configuration, use the design solutions described in UG360:Virtex-6 FPGA Configuration User Guide.
2. Only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the I/O.
3. DO will hold until next DRP operation.
Clock Buffers and Networks
Table 60: Global Clock Switching Characteristics (Including BUFGCTRL)
Speed Grade
Symbol
Description
CE pins Setup/Hold
Devices
Units
-3
-2
-1
-1L
(1)
TBCCCK_CE/TBCCKC_CE
All
0.11/
0.00
0.13/
0.00
0.16/
0.00
0.13/
0.00
ns
(1)
TBCCCK_S/TBCCKC_S
S pins Setup/Hold
All
All
0.11/
0.00
0.13/
0.00
0.16/
0.00
0.13/
0.00
ns
ns
(2)
TBCCKO_O
BUFGCTRL delay from I0/I1 to O
0.07
0.08
0.10
0.10
Maximum Frequency
All except LX760
LX760
800
N/A
750
700
700
700
667
667
MHz
MHz
FMAX
Global clock tree (BUFG)
Notes:
1.
T
and T
must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These
BCCCK_CE
BCCKC_CE
parameters do not apply to the BUFGMUX_VIRTEX4 primitive that assures glitch-free operation. The other global clock setup and hold
times are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching
between clocks.
2.
T
(BUFG delay from I0 to O) values are the same as T
values.
BCCKO_O
BGCKO_O
Table 61: Input/Output Clock Switching Characteristics (BUFIO)
Symbol Description
TBIOCKO_O Clock to out delay from I to O
Speed Grade
Units
-3
-2
-1
-1L
0.14
0.16
0.18
0.21
ns
Maximum Frequency
FMAX
I/O clock tree (BUFIO)
800
800
710
710
MHz
Table 62: Regional Clock Switching Characteristics (BUFR)
Symbol Description
Clock to out delay from I to O
Speed Grade
Units
-3
-2
-1
-1L
0.82
0.41
TBRCKO_O
0.56
0.28
0.62
0.31
0.73
0.36
ns
ns
Clock to out delay from I to O with Divide Bypass attribute
set
TBRCKO_O_BYP
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
51
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 62: Regional Clock Switching Characteristics (BUFR) (Cont’d)
Speed Grade
Symbol
Description
Units
-3
-2
-1
-1L
TBRDO_O
Propagation delay from CLR to O
0.69
0.74
0.80
1.12
ns
Maximum Frequency
(1)
FMAX
Regional clock tree (BUFR)
500
420
300
300
MHz
Notes:
1. The maximum input frequency to the BUFR is the BUFIO F
frequency.
MAX
Table 63: Horizontal Clock Buffer Switching Characteristics (BUFH)
Symbol Description
BUFH delay from I to O
Speed Grade
Units
-3
-2
-1
-1L
TBHCKO_O
BHCCK_CE/TBHCKC_CE
0.10
0.11
0.13
0.15
ns
ns
0.04/
0.04
0.04/
0.04
0.05/
0.05
0.04/
0.04
T
CE pin Setup and Hold
Maximum Frequency
FMAX
Horizontal clock buffer (BUFH)
800
750
700
667
MHz
MMCM Switching Characteristics
Table 64: MMCM Specification
Speed Grade
Symbol
Description
Units
-3
800
10
-2
750
10
-1
700
10
-1L
700
10
FINMAX
FINMIN
FINJITTER
Maximum Input Clock Frequency(1)
Minimum Input Clock Frequency
MHz
MHz
Maximum Input Clock Period Jitter
< 20% of clock input period or 1 ns Max
(2)
FINDUTY
Allowable Input Duty Cycle: 10—49 MHz
Allowable Input Duty Cycle: 50—199 MHz
Allowable Input Duty Cycle: 200—399 MHz
Allowable Input Duty Cycle: 400—499 MHz
Allowable Input Duty Cycle: >500 MHz
Minimum Dynamic Phase Shift Clock Frequency
Maximum Dynamic Phase Shift Clock Frequency
Minimum MMCM VCO Frequency
25/75
30/70
35/65
40/60
45/55
%
%
%
%
%
FMIN_PSCLK
FMAX_PSCLK
FVCOMIN
0.01
550
0.01
500
0.01
450
0.01
450
MHz
MHz
MHz
MHz
MHz
MHz
ns
600
600
600
600
FVCOMAX
Maximum MMCM VCO Frequency
1600
1.00
4.00
0.12
1440
1.00
4.00
0.12
1200
1.00
4.00
0.12
Note 3
0.20
100
1200
1.00
4.00
0.12
FBANDWIDTH
Low MMCM Bandwidth at Typical(3)
High MMCM Bandwidth at Typical(3)
Static Phase Offset of the MMCM Outputs(4)
MMCM Output Jitter(5)
TSTATPHAOFFSET
TOUTJITTER
TOUTDUTY
TLOCKMAX
FOUTMAX
MMCM Output Clock Duty Cycle Precision(6)
MMCM Maximum Lock Time
0.15
100
800
4.69
0.20
100
750
4.69
0.20
100
700
4.69
ns
µs
MMCM Maximum Output Frequency
MMCM Minimum Output Frequency(7)(8)
External Clock Feedback Variation
700
MHz
MHz
FOUTMIN
4.69
TEXTFDVAR
< 20% of clock input period or 1 ns Max
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
52
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 64: MMCM Specification (Cont’d)
Speed Grade
Units
Symbol
Description
-3
-2
-1
-1L
1.5
RSTMINPULSE
FPFDMAX
Minimum Reset Pulse Width
1.5
550
1.5
500
1.5
450
ns
Maximum Frequency at the Phase Frequency
450
MHz
Detector with Bandwidth Set to High or Optimized(9)
Maximum Frequency at the Phase Frequency
Detector with Bandwidth Set to Low
300
135
10
300
135
10
300
135
10
300
135
10
MHz
MHz
MHz
FPFDMIN
Minimum Frequency at the Phase Frequency
Detector with Bandwidth Set to High or Optimized
Minimum Frequency at the Phase Frequency
Detector with Bandwidth Set to Low
TFBDELAY
Maximum Delay in the Feedback Path
Setup and Hold of Phase Shift Enable
3 ns Max or one CLKIN cycle
TMMCMDCK_PSEN
TMMCMCKD_PSEN
/
1.04
0.00
1.04
0.00
1.04
0.00
1.04
0.00
ns
ns
ns
TMMCMDCK_PSINCDEC
TMMCMCKD_PSINCDEC
/
Setup and Hold of Phase Shift Increment/Decrement
Phase Shift Clock-to-Out of PSDONE
1.04
0.00
1.04
0.00
1.04
0.00
1.04
0.00
TMMCMCKO_PSDONE
0.32
0.34
0.38
0.38
Notes:
1. When DIVCLK_DIVIDE = 3 or 4, F
is 315 MHz.
INMAX
2. This duty cycle specification does not apply to the GTH_QUAD (GTH) to MMCM connection. The GTH transceivers drive the MMCMs at the
following maximum frequencies: 323 MHz for -1 speed grade devices, 350 MHz for -2 speed grade devices, or 350 MHz for -3 speed grade
devices.
3. The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.
4. The static offset is measured between any MMCM outputs with identical phase.
5. Values for this parameter are available in the Clocking Wizard.
See http://www.xilinx.com/products/intellectual-property/clocking_wizard.htm.
6. Includes global clock buffer.
7. Calculated as F
/128 assuming output duty cycle is 50%.
VCO
8. When CLKOUT4_CASCADE = TRUE, F
is 0.036 MHz.
OUTMIN
9. In ISE software 12.3 (or earlier versions supporting the Virtex-6 family), the phase frequency detector Optimized bandwidth setting is
equivalent to the High bandwidth setting. Starting with ISE software 12.4, the Optimized bandwidth setting is automatically adjusted to Low
when the software can determine that the phase frequency detector input is less than 135 MHz.
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
53
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Virtex-6 Device Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are
listed in Table 65. Values are expressed in nanoseconds unless otherwise noted.
Table 65: Global Clock Input to Output Delay Without MMCM
Speed Grade
Symbol
Description
Device
Units
-3
-2
-1
-1L
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, without MMCM.
TICKOF
Global Clock input and OUTFF without
MMCM
XC6VLX75T
4.91
4.89
5.02
5.02
5.30
N/A
N/A
5.40
N/A
5.18
5.20
5.38
N/A
N/A
N/A
N/A
N/A
N/A
5.32
5.33
5.46
5.46
5.75
6.02
6.26
5.85
6.01
5.63
5.66
5.84
6.03
5.33
5.46
N/A
5.88
6.00
6.13
6.13
6.43
6.72
6.97
6.54
6.71
6.30
6.34
6.53
6.71
6.00
6.13
6.72
6.54
6.71
6.02
6.13
6.27
6.27
6.37
6.60
6.87
6.49
6.61
N/A
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XC6VLX130T
XC6VLX195T
XC6VLX240T
XC6VLX365T
XC6VLX550T
XC6VLX760
XC6VSX315T
XC6VSX475T
XC6VHX250T
XC6VHX255T
XC6VHX380T
XC6VHX565T
XQ6VLX130T
XQ6VLX240T
XQ6VLX550T
XQ6VSX315T
XQ6VSX475T
N/A
N/A
N/A
6.13
6.27
6.60
6.49
6.61
5.85
N/A
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
54
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 66: Global Clock Input to Output Delay With MMCM
Speed Grade
Symbol
Description
Device
Units
-3
-2
-1
-1L
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with MMCM.
TICKOFMMCMGC
Global Clock Input and OUTFF with
MMCM
XC6VLX75T
2.34
2.35
2.36
2.36
2.37
N/A
N/A
2.35
N/A
2.36
2.46
2.39
N/A
N/A
N/A
N/A
N/A
N/A
2.50
2.51
2.52
2.52
2.53
2.55
2.54
2.51
2.43
2.53
2.63
2.59
2.54
2.51
2.52
N/A
2.77
2.78
2.79
2.79
2.79
2.82
2.82
2.79
2.70
2.80
2.91
2.83
2.81
2.78
2.79
2.82
2.79
2.70
2.85
2.87
2.88
2.88
2.89
2.93
2.92
2.87
2.79
N/A
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XC6VLX130T
XC6VLX195T
XC6VLX240T
XC6VLX365T
XC6VLX550T
XC6VLX760
XC6VSX315T
XC6VSX475T
XC6VHX250T
XC6VHX255T
XC6VHX380T
XC6VHX565T
XQ6VLX130T
XQ6VLX240T
XQ6VLX550T
XQ6VSX315T
XQ6VSX475T
N/A
N/A
N/A
2.87
2.88
2.93
2.87
2.79
2.51
N/A
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. MMCM output jitter is already included in the timing calculation.
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
55
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 67: Clock-Capable Clock Input to Output Delay With MMCM
Speed Grade
-2 -1
LVCMOS25 Clock-capable Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with MMCM.
Symbol
Description
Device
Units
-3
-1L
TICKOFMMCMCC
Clock-capable Clock Input and OUTFF
with MMCM
XC6VLX75T
2.22
2.24
2.24
2.24
2.25
N/A
N/A
2.23
N/A
2.25
2.35
2.27
N/A
N/A
N/A
N/A
N/A
N/A
2.38
2.39
2.40
2.40
2.42
2.43
2.42
2.38
2.30
2.41
2.51
2.43
2.41
2.39
2.40
N/A
2.63
2.65
2.65
2.65
2.65
2.68
2.69
2.65
2.57
2.67
2.78
2.69
2.68
2.65
2.65
2.68
2.65
2.57
2.72
2.74
2.75
2.75
2.76
2.80
2.79
2.73
2.66
N/A
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XC6VLX130T
XC6VLX195T
XC6VLX240T
XC6VLX365T
XC6VLX550T
XC6VLX760
XC6VSX315T
XC6VSX475T
XC6VHX250T
XC6VHX255T
XC6VHX380T
XC6VHX565T
XQ6VLX130T
XQ6VLX240T
XQ6VLX550T
XQ6VSX315T
XQ6VSX475T
N/A
N/A
N/A
2.74
2.75
2.80
2.73
2.66
2.38
N/A
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. MMCM output jitter is already included in the timing calculation.
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
56
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Virtex-6 Device Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are
listed in Table 68. Values are expressed in nanoseconds unless otherwise noted.
Table 68: Global Clock Input Setup and Hold Without MMCM
Speed Grade
Symbol
Description
Device
Units
-3
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1)
-2
-1
-1L
TPSFD/ TPHFD
Full Delay (Legacy Delay or Default Delay)
Global Clock Input and IFF(2) without MMCM
XC6VLX75T
1.33/
0.03
1.44/
0.03
1.75/
0.03
2.18/
–0.22
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XC6VLX130T
XC6VLX195T
XC6VLX240T
XC6VLX365T
XC6VLX550T
XC6VLX760
1.31/
–0.08
1.54/
–0.08
1.88/
–0.08
2.31/
–0.12
1.36/
–0.11
1.60/
–0.11
1.97/
–0.11
2.40/
–0.25
1.36/
–0.11
1.60/
–0.11
1.97/
–0.11
2.40/
–0.25
1.79/
–0.28
1.87/
–0.28
2.17/
–0.28
2.48/
–0.24
N/A
2.22/
–0.12
2.36/
–0.12
2.77/
–0.26
N/A
2.19/
–0.24
2.35/
–0.24
2.71/
–0.21
XC6VSX315T
XC6VSX475T
XC6VHX250T
XC6VHX255T
XC6VHX380T
XC6VHX565T
XQ6VLX130T
XQ6VLX240T
XQ6VLX550T
XQ6VSX315T
XQ6VSX475T
1.75/
–0.09
1.85/
–0.09
2.06/
–0.09
2.47/
–0.24
N/A
2.14/
–0.14
2.31/
–0.14
2.71/
–0.30
1.93/
–0.22
2.04/
–0.22
2.25/
–0.22
N/A
N/A
N/A
N/A
1.81/
–0.33
2.11/
–0.33
2.56/
–0.33
1.93/
–0.11
2.04/
–0.11
2.25/
–0.11
N/A
N/A
N/A
N/A
N/A
N/A
2.20/
–0.12
2.39/
–0.12
1.54/
–0.08
1.88/
–0.08
2.31/
–0.12
1.60/
–0.11
1.97/
–0.11
2.40/
–0.25
N/A
2.36/
–0.12
2.77/
–0.26
1.85/
–0.09
2.06/
–0.09
2.47/
–0.24
N/A
2.31/
2.71/
–0.14
–0.30
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage.
2. IFF = Input Flip-Flop or Latch
3. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0"
is listed, there is no positive hold time.
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
57
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 69: Global Clock Input Setup and Hold With MMCM
Speed Grade
Symbol
Description
Device
Units
-3
-2
-1
-1L
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1)
TPSMMCMGC
/
No Delay Global Clock Input and IFF(2) XC6VLX75T
with MMCM
1.45/
–0.18
1.57/
–0.18
1.72/
–0.18
1.78/
–0.08
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TPHMMCMGC
XC6VLX130T
XC6VLX195T
XC6VLX240T
XC6VLX365T
XC6VLX550T
XC6VLX760
1.53/
–0.18
1.65/
–0.18
1.81/
–0.18
1.87/
–0.07
1.54/
–0.17
1.66/
–0.17
1.82/
–0.17
1.87/
–0.08
1.54/
–0.17
1.66/
–0.17
1.82/
–0.17
1.87/
–0.08
1.55/
–0.18
1.67/
–0.18
1.83/
–0.18
1.87/
–0.07
N/A
1.84/
–0.17
2.02/
–0.17
2.06/
–0.06
N/A
2.26/
–0.13
2.49/
–0.13
2.06/
–0.03
XC6VSX315T
XC6VSX475T
XC6VHX250T
XC6VHX255T
XC6VHX380T
XC6VHX565T
XQ6VLX130T
XQ6VLX240T
XQ6VLX550T
XQ6VSX315T
XQ6VSX475T
1.56/
–0.18
1.68/
–0.18
1.84/
–0.18
1.89/
–0.08
N/A
1.85/
–0.23
2.03/
–0.23
2.07/
–0.13
1.52/
–0.17
1.64/
–0.17
1.80/
–0.17
N/A
N/A
N/A
N/A
1.52/
–0.12
1.64/
–0.12
1.85/
–0.12
1.68/
–0.16
1.81/
–0.16
1.99/
–0.16
N/A
N/A
N/A
N/A
N/A
N/A
1.81/
–0.01
1.99/
–0.01
1.65/
–0.18
1.81/
–0.18
1.87/
–0.07
1.66/
–0.17
1.82/
–0.17
1.87/
–0.08
N/A
2.02/
–0.17
2.06/
–0.06
1.68/
–0.18
1.84/
–0.18
1.89/
–0.08
N/A
2.03/
2.07/
–0.23
–0.13
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage.
2. IFF = Input Flip-Flop or Latch
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
58
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 70: Clock-Capable Clock Input Setup and Hold With MMCM
Speed Grade
Symbol
Description
Device
Units
-3
-2
-1
-1L
Input Setup and Hold Time Relative to Clock-capable Clock Input Signal for LVCMOS25 Standard.(1)
TPSMMCMCC
/
No Delay Clock-capable Clock Input and XC6VLX75T
IFF(2) with MMCM
1.56/
–0.25
1.69/
–0.25
1.86/
–0.25
1.91/
–0.15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TPHMMCMCC
XC6VLX130T
XC6VLX195T
XC6VLX240T
XC6VLX365T
XC6VLX550T
XC6VLX760
1.64/
–0.25
1.78/
–0.25
1.95/
–0.25
2.00/
–0.14
1.65/
–0.24
1.79/
–0.24
1.96/
–0.24
2.01/
–0.15
1.65/
–0.24
1.79/
–0.24
1.96/
–0.24
2.01/
–0.15
1.66/
–0.25
1.79/
–0.25
1.97/
–0.25
2.02/
–0.15
N/A
1.97/
–0.24
2.16/
–0.24
2.19/
–0.14
N/A
2.39/
–0.20
2.63/
–0.20
2.21/
–0.10
XC6VSX315T
XC6VSX475T
XC6VHX250T
XC6VHX255T
XC6VHX380T
XC6VHX565T
XQ6VLX130T
XQ6VLX240T
XQ6VLX550T
XQ6VSX315T
XQ6VSX475T
1.67/
–0.25
1.80/
–0.25
1.98/
–0.25
2.03/
–0.16
N/A
1.98/
–0.29
2.17/
–0.29
2.21/
–0.20
1.63/
–0.24
1.76/
–0.24
1.94/
–0.24
N/A
N/A
N/A
N/A
1.63/
–0.19
1.76/
–0.19
1.99/
–0.19
1.80/
–0.23
1.94/
–0.23
2.13/
–0.23
N/A
N/A
N/A
N/A
N/A
N/A
1.94/
–0.08
2.13/
–0.08
1.78/
–0.25
1.95/
–0.25
2.00/
–0.14
1.79/
–0.24
1.96/
–0.24
2.01/
–0.15
N/A
2.16/
–0.24
2.19/
–0.14
1.80/
–0.25
1.98/
–0.25
2.03/
–0.16
N/A
2.17/
2.21/
–0.29
–0.20
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage.
2. IFF = Input Flip-Flop or Latch
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
59
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Clock Switching Characteristics
The parameters in this section provide the necessary values for calculating timing budgets for Virtex-6 FPGA clock
transmitter and receiver data-valid windows.
Table 71: Duty Cycle Distortion and Clock-Tree Skew
Speed Grade
Symbol
Description
Device
Units
-3
-2
-1
-1L
0.12
0.17
0.28
0.30
0.30
0.31
0.54
0.56
0.30
0.42
N/A
TDCD_CLK
Global Clock Tree Duty Cycle Distortion(1)
Global Clock Tree Skew(2)
All
0.12
0.15
0.25
0.26
0.26
0.28
N/A
N/A
0.27
N/A
0.25
0.35
0.45
N/A
N/A
N/A
N/A
N/A
N/A
0.08
0.03
0.10
0.15
0.12
0.16
0.26
0.27
0.27
0.29
0.50
0.51
0.28
0.39
0.26
0.37
0.47
0.46
0.26
0.27
N/A
0.12
0.18
0.29
0.31
0.31
0.31
0.54
0.56
0.32
0.44
0.29
0.41
0.52
0.51
0.29
0.31
0.54
0.32
0.44
0.08
0.03
0.23
0.15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCKSKEW
XC6VLX75T
XC6VLX130T
XC6VLX195T
XC6VLX240T
XC6VLX365T
XC6VLX550T
XC6VLX760
XC6VSX315T
XC6VSX475T
XC6VHX250T
XC6VHX255T
XC6VHX380T
XC6VHX565T
XQ6VLX130T
XQ6VLX240T
XQ6VLX550T
XQ6VSX315T
XQ6VSX475T
All
N/A
N/A
N/A
0.28
0.30
0.54
0.30
0.42
0.08
0.02
0.12
0.15
0.28
N/A
TDCD_BUFIO
TBUFIOSKEW
TBUFIOSKEW2
TDCD_BUFR
I/O clock tree duty cycle distortion
0.08
0.03
0.12
0.15
I/O clock tree skew across one clock region
I/O clock tree skew across three clock regions
Regional clock tree duty cycle distortion
All
All
All
Notes:
1. These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For cases
where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical
rise/fall times.
2. The T
value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree
CKSKEW
skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor
and Timing Analyzer tools to evaluate clock skew specific to your application.
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
60
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 72: Package Skew
Symbol
Description
Package Skew(1)
Device
XC6VLX75T
Package
FF484
Value
95
Units
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
TPKGSKEW
FF784
146
95
FF484
XC6VLX130T
XC6VLX195T
XC6VLX240T
XC6VLX365T
FF784
146
165
145
182
146
182
187
189
184
196
249
236
168
190
168
204
166
168
228
159
172
227
220
232
197
146
165
165
146
182
182
187
196
168
168
190
168
168
204
FF1156
FF784
FF1156
FF784
FF1156
FF1759
FF1156
FF1759
FF1759
FF1760
FF1760
FF1156
FF1759
FF1156
FF1759
FF1154
FF1155
FF1923
FF1154
FF1155
FF1923
FF1924
FF1923
FF1924
RF784
XC6VLX550T
XC6VLX760
XC6VSX315T
XC6VSX475T
XC6VHX250T
XC6VHX255T
XC6VHX380T
XC6VHX565T
XQ6VLX130T
RF1156
FFG1156
RF784
XQ6VLX240T
RF1156
FFG1156
RF1759
RF1759
RF1156
FFG1156
RF1759
RF1156
FFG1156
RF1759
XQ6VLX550T
XQ6VSX315T
XQ6VSX475T
Notes:
1. These values represent the worst-case skew between any two SelectIO resources in the package: shortest flight time to longest flight time
from Pad to Ball (7.0 ps per mm).
2. Package trace length information is available for these device/package combinations. This information can be used to deskew the package.
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
61
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Speed Grade
Table 73: Sample Window
Symbol
Description
Device
Units
-3
-2
-1
-1L
670
440
TSAMP
Sampling Error at Receiver Pins(1)
All
All
510
300
560
350
610
400
ps
ps
TSAMP_BUFIO
Sampling Error at Receiver Pins using BUFIO(2)
Notes:
1. This parameter indicates the total sampling error of Virtex-6 FPGA DDR input registers, measured across voltage, temperature, and
process. The characterization methodology uses the MMCM to capture the DDR input registers’ edges of operation. These measurements
include:
- CLK0 MMCM jitter
- MMCM accuracy (phase offset)
- MMCM phase shift resolution
These measurements do not include package or clock tree skew.
2. This parameter indicates the total sampling error of Virtex-6 FPGA DDR input registers, measured across voltage, temperature, and
process. The characterization methodology uses the BUFIO clock network and IODELAY to capture the DDR input registers’ edges of
operation. These measurements do not include package or clock tree skew.
Table 74: Pin-to-Pin Setup/Hold and Clock-to-Out
Speed Grade
Symbol
Description
Units
-3
Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO
PSCS/TPHCS Setup/Hold of I/O clock –0.28/1.09 –0.28/1.16 –0.28/1.33 –0.18/1.79
Pin-to-Pin Clock-to-Out Using BUFIO
-2
-1
-1L
T
ns
ns
TICKOFCS
Clock-to-Out of I/O clock
4.22
4.59
5.22
5.63
Revision History
The following table shows the revision history for this document:
Date
Version
1.0
Description of Revisions
06/24/2009
07/16/2009
Initial Xilinx release.
1.1
Revised the maximum VCCAUX and VIN numbers in Table 2, page 2. Removed empty column from
Table 3, page 3. Revised specifications on Table 20, page 13. Updated Table 38, page 22 and added
notes 1 and 2. Revised TDLYCCO_RDY, TIDELAYCTRL_RPW, and TIDELAYPAT_JIT in Table 53, page 41.
Updated Table 58, page 46 to more closely match the DSP48E1 speed specifications. Updated
TTAPTCK/TTCKTAP in Table 59, page 49. Updated XC6VLX130T parameters in Table 68 through
Table 70, page 59.
08/19/2009
09/16/2009
1.2
2.0
Added values for -1L voltages and speed grade in all pertinent tables. Added VFS and notes to Table 1
and Table 2. Removed DVPPIN from the example in Figure 2. Added networking applications to
Table 41, page 25. Changed and added to the block RAM FMAX section in Table 57, page 44 including
removing Note 12. Changed FPFDMAX values and corrected units for TSTATPHAOFFSET and TOUTDUTY
in Table 64, page 52. Updated Table 71, page 60.
Added Virtex-6 HXT devices to entire document including GTH Transceiver Specifications. Updated
speed specifications as described in Switching Characteristics, includes changes in Table 51,
Table 57, Table 58, and Table 66 through Table 70. Comprehensive changes to Table 14, Table 15, and
Table 16. Added conditions to DVPPOUT and revised description of TOSKEW in Table 17. Removed VISE
specification and note from Table 18. Added note 3 to Table 23. Updated note 3 in Table 24. Updated
LVCMOS25 delays in Table 44. Updated specification for TIOTPHZ in Table 46. Removed TBUFHSKEW
from Table 71, page 60 and added values for TBUFIOSKEW. Added values in Table 74.
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
62
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Description of Revisions
Date
Version
01/18/2010
2.1
Changed absolute maximum ratings for both VIN and VTS in Table 1. Added data to Table 3. Added
data to Table 5. Updated SSTL15 in Table 7. Updated VOCM and VOD values in Table 8. Added eFUSE
endurance Table 12. Added values to VMGTREFCLK and VIN in Table 13, page 11. Added values and
updated tables in the GTX Transceiver Specifications and GTH Transceiver Specifications sections.
Added Table 27 and Figure 4. Revised parameters and values in Table 39. Updated Table 40, page 23.
Added data to Table 41. Updated speed specification to v1.04 with appropriate changes to Table 42
and Table 43 including production release of the XC6VLX240T for -1 and -2 speed grades. Speed
specification changes and numerous updates also made to Table 44, and Table 49 through Table 71.
Added data to Table 73 and Table 74.
02/09/2010
04/12/2010
2.2
2.3
Revised description of CIN in Table 3. Clarified values in Table 5. Fixed SDR LVDS unit error in
Table 41.
Added note 3 and update value of n in Table 3. Clarified simultaneous power-down in Power-On Power
Supply Requirements. Updated external reference junction temperatures in Table 40, Analog-to-Digital
Specifications. Updated speed specification to v1.05 with appropriate changes to Table 42 and
Table 43 including production release of the XC6VLX130T for -1 and -2 speed grades. Fixed note 4 in
Table 48. Increased the -2 specification for FIDELAYCTRL_REF and clarified units for TIDELAYPAT_JIT in
Table 53. Added note 1 to Table 62.
05/11/2010
05/26/2010
2.4
2.5
Updated FRXREC in Table 22. Revised FIDELAYCTRL_REF in Table 53. Removed TRCKO_PARITY_ECC:
Clock CLK to ECCPARITY in standard ECC mode row in Table 57. Added XC6VLX130T values to
Table 72.
Added XC6VLX195T data to Table 5. Updated values in Table 22 including adding note 2 and note 3.
Updated speed specification to v1.06 with appropriate changes to Table 42 and Table 43 including
production release of the XC6VLX195T for -1 and -2 speed grades. Added XC6VLX195T values to
Table 72.
07/16/2010
07/23/2010
2.6
2.7
Changed Table 42 and Table 43 to production status on the -3 speed grade XC6VLX130T,
XC6VLX195T, and XC6VLX240T devices. Added XC6VHX250Tdata to Table 4 and Table 72. Added
Note 6 to Table 64.
Changed Table 42 and Table 43 to production status on the XC6VLX75T, XC6VLX365T, XC6VLX550T,
XC6VLX760, XC6VSX315T, and XC6VSX475T devices using ISE 12.2 software with speed
specification v1.08. Updated VCMOUTDC equation to MGTAVTT – DVPPOUT/4 in Table 17. Updated
some -3, -2, -1 specifications in Table 65 through Table 72. Added and updated -1L specifications to
Table 41 and for most switching characteristics tables.
07/30/2010
2.8
Changed Table 42 and Table 43 to production status on the -1L speed grade for the XC6VLX130T,
XC6VLX195T, XC6VLX240T, XC6VLX365T, and XC6VLX550T devices using ISE 12.2 software with
current speed specifications. Also updated the speed specifications for XC6VLX75T, XC6VLX550T,
and XC6VSX315T. Updated VCCINT specifications for -1L speed grade industrial temperature range
devices in Table 2.
09/20/2010
10/18/2010
2.9
In Table 32, changed FGPLLMAX specification in -3 column from 5.951 to 5.591. In Table 40, changed
F
MAX for the DCLK from 250 MHz to 80 MHz.
2.10
The specification change in version 2.9, Table 40 is described in XCN10032, Virtex-6 FPGA: GTX
Transceiver User Guide, Family Data Sheet (SYSMON DCLK), and JTAG ID Changes
In this version (2.10), -1L(I) data is added to Table 4 and clarified in Note 2. Changed Table 42 and
Table 43 to production status on the -1L speed grade XC6VLX75T, XC6VLX760, XC6VSX315T, and
XC6VSX475T devices using ISE 12.3 software with current speed specifications. Revised the
XC6VLX760 -1L speed specification for TPHMMCMGC in Table 69 and TPHMMCMCC in Table 70.
01/17/2011
2.11
Changed in Table 42 and Table 43 to production status on the XC6VHX250T devices using ISE 12.4
software with current speed specifications.
Added industrial temperature range (Tj) recommended specifications to Table 2; including specific
ranges for the -2I XC6VSX475T, XC6VLX550T, XC6VLX760, and XC6VHX565Tdevices. Added
note 3 to Table 36 and maximum total jitter values. Added note 4 to Table 37 and maximum sinusoidal
jitter values. Added note 2 to Table 43. Revised FMAX descriptions in Table 57 and added note 12.
Added note 8 to FPFDMIN in Table 64.
The following revisions are due to specification changes as described in XCN11009, Virtex-6 FPGA:
Data Sheet, User Guides, and JTAG ID Updates.
In Table 59:Configuration Switching Characteristics, page 49, revised -1L specifications for TPOR
MCCK, FMCCKTOL, TSMCSCCK, TSMCCKW, FRBCCK, FTCK, FTCKB, TMCCKL, and TMCCKH. In Table 64:
MMCM Specification, added bandwidth settings to FPFDMIN and added note 1.
,
F
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
63
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Description of Revisions
Date
Version
02/08/2011
2.12
Removed note 1 from Table 4 as the larger devices (XC6VLX550T, XC6VLX760, XC6VSX475T, and
XC6VHX565T) are now offered in -2I. Updated Table 4 and Table 5 with data for the XC6VHX380T in
the FF(G)1154 package. In Table 41, updated -1L specification for DDR3. Added Note 1 to Table 42.
Moved the XC6VHX380Tdevices in the FF(G)1154 package to production release in Table 43 using
ISE 12.4 software with current speed specifications. Updated description for FINDUTY in Table 64.
02/25/2011
3.0
Designated the data sheet as Preliminary for all devices not already labeled production in Table 42.
Changed the XC6VHX380T devices in all packages to production status in Table 42 and Table 43.
Removed note 1 from Table 42.
Added maximum specifications to Table 25. Updated THAVCC2HAVCCRX in Table 27. Updated the
typical values and notes in Table 28 and Table 29. Added values to Table 30 and Table 31. In Table 34,
added values for TLOCK and TPHASE. Updated the values in Table 36 and added note 3. Updated
Table 37 and added note 4.
03/21/2011
04/01/2011
3.1
3.2
Updated Table 2 including Note 7. In Table 4, added Note 3 and -2E, extended temperature range to
the XC6VLX550T, XC6VLX760, XC6VSX475T, and XC6VHX380T devices, and added Note 5 for the
XC6VHX565T. Updated Table 28 typical values. Updated the description for FIDELAYCTRL_REF in
Table 53. Updated FMCCK in Table 59.
Added Tj values for C, E, and I temperature ranges to Table 2. Updated the ICCQ values in Table 4.
Updated FGCLK in Table 34.
Designated the data sheet as Production for all devices not already labeled production in Table 42.
Changed the XC6VHX255T and XC6VHX565T devices in all packages to production status in Table 42
and Table 43. This included updates to the Virtex-6 Device Pin-to-Pin Output Parameter Guidelines
and Virtex-6 Device Pin-to-Pin Input Parameter Guidelines for these devices. Production speed
specifications for these devices are available using the speed specification v1.14 in the ISE 13.1
software update.
Updated and added package skew values to Table 72; these values are correct with regards to
previous production released speed specifications in software. Updated copyright page 1 and Notice
of Disclaimer.
12/08/2011
3.3
Production release of the Defense-grade XQ devices in Table 42 and Table 43 using ISE v13.3 v1.17
Patch for -2 and -1 speed specifications; and v1.10 for -1L speed specifications. Added the
XQ6VLX130T, XQ6VLX240T, XQ6VLX550T, XQ6VSX315T, and XQ6VSX475T to the data sheet
which included adding Table 45. Updated Tj in Table 2. In Table 40, updated Tj for most specifications
and added Note 4. Added Note 4 to Table 41. Added -1(XQ) speed specification columns only to
Table 50, Table 51, Table 52, and Table 58.
Updated VOD in Table 8, VOCM in Table 9, and VOCM and VDIFF in Table 10. Updated the Power-On
Power Supply Requirements section. In Table 27, updated maximum specification for
THAVCC2HAVCCRX and added Note 3. Updated Tj in Table 40. In Table 41, increased the DDR LVDS
receiver (SPI-4.2) -1 speed grade performance value from 1.0 Gb/s to 1.1 Gb/s. In Table 60, updated
the FMAX to add a separate row for the LX760 device values. The speed specifications in the software
tools have always matched these values for the LX760, the data sheet is now correct. Updated the
notes for TOUTJITTER in Table 64.
01/12/2012
05/17/2013
03/18/2014
3.4
3.5
3.6
Added the temperature range -2E to Note 5 in Table 4.
Added the DIFF_SSTL15 I/O standard to Table 7. Added Note 1 to Table 18.
Updated Note 8 in Table 64. Updated Notice of Disclaimer.
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
64
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Notice of Disclaimer
The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the
maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL
WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
(whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related
to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special,
incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of
any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility
of the same. Xilinx assumes no obligation to correct any errors contained in the Materials, or to advise you of any corrections or update.
You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to
the terms and conditions of Xilinx’s limited warranty, please refer to Xilinx’s Terms of Sale which can be viewed at
www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx
products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and
liability for use of Xilinx products in such critical applications, please refer to Xilinx’s Terms of Sale which can be viewed at
www.xilinx.com/legal.htm#tos.
AUTOMOTIVE APPLICATIONS DISCLAIMER
XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-
SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A
VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN
THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III)
USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY
USE OF XILINX PRODUCTS IN SUCH APPLICATIONS.
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
65
相关型号：
XC6VSX315T-1FF1759I
Field Programmable Gate Array, 1098MHz, 314880-Cell, CMOS, PBGA1759, FBGA-1759
XILINX
XC6VSX315T-1FFG1156C
Field Programmable Gate Array, 1098MHz, 314880-Cell, CMOS, PBGA1156, 35 X 35 MM, LEAD FREE, FBGA-1156
XILINX
XC6VSX315T-1FFG1156I
Field Programmable Gate Array, 1098MHz, 314880-Cell, CMOS, PBGA1156, 35 X 35 MM, LEAD FREE, FBGA-1156
XILINX
XC6VSX315T-1FFG1759C
Field Programmable Gate Array, 1098MHz, 314880-Cell, CMOS, PBGA1759, 42.50 X 42.50 MM, LEAD FREE, FBGA-1759
XILINX
XC6VSX315T-1FFG1759I
Field Programmable Gate Array, 1098MHz, 314880-Cell, CMOS, PBGA1759, 42.50 X 42.50 MM, LEAD FREE, FBGA-1759
XILINX
XC6VSX315T-2FF1156C
Field Programmable Gate Array, 1286MHz, 314880-Cell, CMOS, PBGA1156, FBGA-1156
XILINX
XC6VSX315T-2FF1156I
Field Programmable Gate Array, 1286MHz, 314880-Cell, CMOS, PBGA1156, FBGA-1156
XILINX
XC6VSX315T-2FF1759E
Field Programmable Gate Array, 1286MHz, 314880-Cell, CMOS, PBGA1759, FBGA-1759
XILINX
©2020 ICPDF网 联系我们和版权申明