XC7A350T-2FBG484C [XILINX]
Field Programmable Gate Array, 1286MHz, 348480-Cell, CMOS, PBGA484;
| 型号： | XC7A350T-2FBG484C |
| 厂家： | 
XILINX, INC |
| 描述： | Field Programmable Gate Array, 1286MHz, 348480-Cell, CMOS, PBGA484 时钟 栅 可编程逻辑 |
| 文件： | 总45页 (文件大小：1034K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Artix-7 FPGAs Data Sheet:
DC and Switching Characteristics
DS181 (v1.2) February 13, 2012
Advance Product Specification
Artix-7 FPGA Electrical Characteristics
Artix™-7 FPGAs are available in -3, -2, -1, and -2L speed
grades, with -3 having the highest performance. The -2L
characteristics of a -1 speed grade industrial device are the
same as for a -1 speed grade commercial device). However,
only selected speed grades and/or devices are available in
each temperature range.
devices can operate at either of two V
voltages, 0.9V
CCINT
and 1.0V and are screened for lower maximum static power.
When operated at V = 1.0V, the speed specification of
CCINT
All supply voltage and junction temperature specifications
are representative of worst-case conditions. The
parameters included are common to popular designs and
typical applications.
a -2L device is the same as the -2 speed grade. When
operated at V = 0.9V, the -2L static and dynamic
CCINT
power is reduced.
Artix-7 FPGA DC and AC characteristics are specified in
commercial, extended, and industrial temperature ranges.
Except the operating temperature range or unless
otherwise noted, all the DC and AC electrical parameters
are the same for a particular speed grade (that is, the timing
This Artix-7 FPGA data sheet, part of an overall set of
documentation on the 7 series FPGAs, is available on the
Xilinx website at www.xilinx.com/7.
All specifications are subject to change without notice.
Artix-7 FPGA DC Characteristics
(1)
Table 1: Absolute Maximum Ratings
Symbol
VCCINT
VCCAUX
VCCO
Description
Internal supply voltage relative to GND
Units
–0.5 to 1.1
–0.5 to 2.0
–0.5 to 3.6
–0.5 to 1.1
–0.5 to 2.0
–0.5 to 2.0
–0.5 to 2.0
–0.5 to 2.0
–0.5 to VCCO + 0.5
–0.5 to VCCO + 0.5
–65 to 150
+220
V
V
Auxiliary supply voltage relative to GND
Output drivers supply voltage relative to GND for 3.3V HR I/O banks
Supply voltage for the block RAM memories
XADC supply relative to GNDADC
V
V
VCCBRAM
VCCADC
VCCBATT
VREF
V
Key memory battery backup supply
V
Input reference voltage
V
XADC reference input relative to GNDADC
I/O input voltage relative to GND(3) (user and dedicated I/Os)
Voltage applied to 3-state 3.3V or below output(3) (user and dedicated I/Os)
Storage temperature (ambient)
V
VREFP
(2)
V
VIN
V
VTS
TSTG
TSOL
Tj
°C
°C
°C
Maximum soldering temperature(4)
Maximum junction temperature(4)
+125
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
2. The 3.3V I/O absolute maximum limit applied to DC and AC signals.
3. For I/O operation, refer to UG471: 7 Series FPGAs SelectIO Resources User Guide.
4. For soldering guidelines and thermal considerations, see UG475: 7 Series FPGA Packaging and Pinout Specification.
© 2011– 2012 Xilinx, Inc. XILINX, the Xilinx logo, Artix, Virtex, Kintex, Zynq, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United
States and other countries. All other trademarks are the property of their respective owners.
DS181 (v1.2) February 13, 2012
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Advance Product Specification
1
Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
(1)
Table 2: Recommended Operating Conditions
Symbol Description
Internal supply voltage relative to GND
Min
0.95
0.87
1.71
1.14
0.95
1.0
Max
1.05
0.93
1.89
3.465
1.05
1.89
Units
V
VCCINT
For -2L (0.9V) devices: internal supply voltage relative to GND
Auxiliary supply voltage relative to GND
Supply voltage for 3.3V HR I/O banks relative to GND
Block RAM supply voltage
V
VCCAUX
V
(2)(4)
VCCO
V
VCCBRAM
V
(3)
VCCBATT
VIN
Battery voltage relative to GND
V
I/O input voltage relative to GND
GND – 0.20 VCCO + 0.2
V
Maximum current through any pin in a powered or unpowered bank when forward
biasing the clamp diode.
–
10
mA
(5)
IIN
Junction temperature operating range for commercial (C) temperature devices
Junction temperature operating range for extended (E) temperature devices
Junction temperature operating range for industrial (I) temperature devices
0
0
85
°C
°C
°C
Tj
100
100
–40
Notes:
1. All voltages are relative to ground.
2. Configuration data is retained even if V
drops to 0V.
CCO
3.
V
is required only when using bitstream encryption. If battery is not used, connect V
to either ground or V
.
CCAUX
CCBATT
CCBATT
4. Includes V
of 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V.
CCO
5. A total of 100 mA per bank should not be exceeded.
Table 3: DC Characteristics Over Recommended Operating Conditions
Symbol
VDRINT
VDRI
Description
Data retention VCCINT voltage (below which configuration data might be lost)
Data retention VCCAUX voltage (below which configuration data might be lost)
VREF leakage current per pin
Min
Typ(1)
Max
Units
V
V
IREF
µA
µA
pF
µA
µA
µA
µA
µA
µA
µA
nA
–
IL
Input or output leakage current per pin (sample-tested)
Die input capacitance at the pad
(2)
CIN
Pad pull-up (when selected) @ VIN = 0V, VCCO = 3.3V
Pad pull-up (when selected) @ VIN = 0V, VCCO = 2.5V
Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.8V
Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.5V
Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.2V
Pad pull-down (when selected) @ VIN = 3.3V
Pad pull-down (when selected) @ VIN = 1.8V
Battery supply current
IRPU
IRPD
(3)
IBATT
150
1.0002
2
n
r
Temperature diode ideality factor
Series resistance
Notes:
1. Typical values are specified at nominal voltage, 25°C.
2. This measurement represents the die capacitance at the pad, not including the package.
3. Maximum value specified for worst case process at 25°C.
DS181 (v1.2) February 13, 2012
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Advance Product Specification
2
Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
Static Power Consumption
Table 4: Typical Quiescent Supply Current
Speed Grade
Symbol
Description
Device
1.0V
0.9V
-2L
Units
-3
-2/-2L
-1
ICCINTQ
Quiescent VCCINT supply current
XC7A100T
XC7A200T
XC7A350T
XC7A100T
XC7A200T
XC7A350T
XC7A100T
XC7A200T
XC7A350T
XC7A100T
XC7A200T
XC7A350T
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
ICCOQ
Quiescent VCCO supply current
Quiescent VCCAUX supply current
ICCAUXQ
ICCBRAMQ Quiescent VCCBRAM supply current
Notes:
1. Typical values are specified at nominal voltage, 85°C junction temperatures (T ) with single-ended SelectIO resources.
j
2. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and
floating.
3. Use the XPower™ Estimator (XPE) spreadsheet tool (download at http://www.xilinx.com/power) to calculate static power consumption for
conditions other than those specified.
DS181 (v1.2) February 13, 2012
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Advance Product Specification
3
Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
Power-On/Off Power Supply Sequencing
The recommended power-on sequence is V
, V
, V
, and V
to achieve minimum current draw and
CCO
CCINT CCBRAM
CCAUX
ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the power-on
sequence. If V and V have the same recommended voltage levels then both can be powered by the same
CCINT
CCBRAM
supply and ramped simultaneously. If V
and V
have the same recommended voltage levels then both can be
CCAUX
CCO
powered by the same supply and ramped simultaneously.
For V voltages of 3.3V in HR I/O banks and configuration bank 0:
CCO
•
•
The voltage difference between V
power-on/off cycle to maintain device reliability levels.
and V
must not exceed 2.625V for longer than T
for each
CCO
CCAUX
VCCO2VCCAUX
The T time can be allocated in any percentage between the power-on and power-off ramps.
VCCO2VCCAUX
There are no sequencing requirements for the GTP transceiver supplies with respect to the other FPGA supply voltages.
Table 5 shows the minimum current, in addition to I , that are required by Artix-7 devices for proper power-on and
CCQ
configuration. If the current minimums shown in Table 4 and Table 5 are met, the device powers on after all four supplies
have passed through their power-on reset threshold voltages. The FPGA must not be configured until after V
applied.
is
CCINT
Once initialized and configured, use the XPOWER tools to estimate current drain on these supplies.
Table 5: Power-On Current for Artix-7 Devices
ICCINTMIN
Typ(1)
ICCAUXMIN
Typ(1)
ICCOMIN
Typ(1)
ICCBRAM
Typ(1)
Device
Units
XC7A100T
XC7A200T
XC7A350T
mA
mA
mA
Notes:
1. Typical values are specified at nominal voltage, 25°C.
2. Use the XPOWER™ Estimator (XPE) spreadsheet tool (download at http://www.xilinx.com/power) to calculate maximum power-on currents.
Table 6: Power Supply Ramp Time
Symbol
TVCCINT
Description
Ramp time from GND to 90% of VCCINT
Ramp time from GND to 90% of VCCO
Ramp time from GND to 90% of VCCAUX
Ramp time from GND to 90% of VCCBRAM
Conditions
Min
0.2
0.2
0.2
0.2
–
Max
50
Units
ms
TVCCO
50
ms
TVCCAUX
TVCCBRAM
50
ms
50
ms
TJ = 100°C(1)
TJ = 85°C(1)
500
800
50
TVCCO2VCCAUX
Allowed time per power cycle for VCCO – VCCAUX 2.625V
ms
–
TMGTAVCC
TMGTAVTT
Ramp time from GND to 90% of MGTAVCC
Ramp time from GND to 90% of MGTAVTT
0.2
0.2
ms
ms
50
Notes:
1. Based on 240,000 power cycles with nominal V
of 3.3V or 36,500 power cycles with worst case V
of 3.465V.
CCO
CCO
DS181 (v1.2) February 13, 2012
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Advance Product Specification
4
Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
SelectIO™ DC Input and Output Levels
Values for V and V are recommended input voltages. Values for I and I are guaranteed over the recommended
IL
IH
OL
OH
operating conditions at the V and V test points. Only selected standards are tested. These are chosen to ensure that
OL
OH
all standards meet their specifications. The selected standards are tested at a minimum V
with the respective V and
CCO
OL
V
voltage levels shown. Other standards are sample tested.
OH
(1)(2)
Table 7: SelectIO DC Input and Output Levels
VIL
VIH
VOL
V, Max
0.400
VOH
IOL
mA
8
IOH
mA
–8
I/O Standard
V, Min
–0.300
–0.300
–0.300
–0.300
–0.300
–0.300
–0.300
–0.300
–0.300
–0.300
–0.300
–0.300
–0.300
–0.500
–0.300
–0.300
–0.300
–0.300
–0.300
–0.300
–0.300
V, Max
V, Min
V, Max
V, Min
HSTL_I
VREF – 0.100
VREF – 0.100
VREF – 0.100
VREF + 0.100 VCCO + 0.300
VCCO – 0.400
75% VCCO
HSTL_I_12
HSTL_I_18
HSTL_II
VREF + 0.100 VCCO + 0.300 25% VCCO
6.3
8
–6.3
–8
VREF + 0.100 VCCO + 0.300
VREF + 0.100 VCCO + 0.300
VREF + 0.100 VCCO + 0.300
0.400
0.400
0.400
VCCO – 0.400
VCCO – 0.400
VCCO – 0.400
V
REF – 0.100
VREF – 0.100
REF – 0.120
16
16
–16
–16
HSTL_II_18
HSUL_12
LVCMOS12
LVCMOS15
LVCMOS18
LVCMOS25
LVCMOS33
LVTTL
V
VREF + 0.120 VCCO + 0.300 VREF – 0.120 VREF + 0.120
35% VCCO
30% VCCO
35% VCCO
0.700
65% VCCO
70% VCCO
65% VCCO
1.700
VCCO + 0.300
0.400
VCCO – 0.400
75% VCCO
VCCO – 0.450
VCCO – 0.400
VCCO – 0.400
2.400
Note 3
Note 4
Note 5
Note 4
Note 4
Note 5
0.1
Note 3
Note 4
Note 5
Note 4
Note 4
Note 5
–0.1
VCCO + 0.300 25% VCCO
VCCO + 0.300
0.450
0.400
0.400
0.400
V
CCO + 0.300
3.450
0.800
2.000
0.800
2.000
3.450
MOBILE_DDR
PCI33_3
20% VCCO
30% VCCO
VREF – 0.100
80% VCCO
50% VCCO
VCCO + 0.300 10% VCCO
VCCO + 0.500 10% VCCO
90% VCCO
90% VCCO
1.5
–0.5
SSTL12
VREF + 0.100 VCCO + 0.300 VREF – 0.150 VREF + 0.150
VREF + 0.900 VCCO + 0.300 VREF – 0.150 VREF + 0.150
VREF + 0.900 VCCO + 0.300 VREF – 0.150 VREF + 0.150
SSTL135
VREF – 0.900
SSTL135_R
SSTL15
VREF – 0.900
VREF – 0.100
VREF + 0.100 VCCO + 0.300 VTT – 0.175
VREF + 0.100 VCCO + 0.300 VTT – 0.175
VREF + 0.125 VCCO + 0.300 VTT – 0.470
VREF + 0.125 VCCO + 0.300 VTT – 0.600
VTT + 0.175
VTT + 0.175
VTT + 0.470
VTT + 0.600
17.8
–17.8
SSTL15_R
SSTL18_I
SSTL18_II
V
REF – 0.100
VREF – 0.125
REF – 0.125
8
–8
V
13.4
–13.4
Notes:
1. Tested according to relevant specifications.
2. 3.3V and 2.5V standards are only supported in 3.3V I/O banks.
3. Supported drive strengths of 4, 8, or 12 mA in HR I/O banks.
4. Supported drive strengths of 4, 8, 12, or 16 mA in HR I/O banks.
5. Supported drive strengths of 4, 8, 12, 16, or 24 mA in HR I/O banks.
6. For detailed interface specific DC voltage levels, see UG471: 7 Series FPGAs SelectIO Resources User Guide.
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Advance Product Specification
5
Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
Table 8: Differential SelectIO DC Input and Output Levels
(1)
(2)
(3)
(4)
VICM
V, Min V, Typ V, Max V, Min V, Typ V, Max
MINI_LVDS_25 0.300 1.200 VCCAUX 0.200 0.400 0.600
VID
VOCM
VOD
I/O Standard
V, Min
1.000
0.500
1.000
V, Typ
1.200
0.950
1.200
V, Max
1.400
1.400
1.400
V, Min V, Typ V, Max
0.300 0.450 0.600
0.100 0.250 0.400
0.100 0.350 0.600
PPDS_25
RSDS_25
TMDS_33
0.200 0.900 VCCAUX 0.100 0.250 0.400
0.300 0.900
2.700 2.965
1.500
3.230
0.100 0.350 0.600
0.150 0.675 1.200
V
CCO–0.405 VCCO–0.300 VCCO–0.190 0.400 0.600 0.800
Notes:
1.
2.
3.
4.
V
V
V
V
is the input common mode voltage.
is the input differential voltage (Q – Q).
ICM
ID
is the output common mode voltage.
OCM
is the output differential voltage (Q – Q).
OD
5. LVDS_25 is specified in Table 10.
Table 9: Complementary Differential SelectIO DC Input and Output Levels
(1)
(2)
(3)
(4)
(5)
(6)
(7)
VICM
VID
VOCM
VOD
VOX
VOL
VOH
I/O Standard
V, V,
V,
V, V, V, V, V,
V, V, V, V, V, V,
V,
V, Max
V, Min
Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ Max
1.250
0.750
0.900
0.750
0.900
0.900
0.600
0.675
0.750
0.900
0.900
0.100
0.100
0.100
0.100
0.100
0.100
0.100
0.100
0.100
0.100
0.100
1.250
0.750
0.900
0.750
0.900
0.900
0.600
0.675
0.750
0.900
0.900
BLVDS_25
N/A N/A N/A
0.750
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
DIFF_HSTL_I
0.900
DIFF_HSTL_I_18
DIFF_HSTL_II
0.750
0.900
DIFF_HSTL_II_18
DIFF_MOBILE_DDR
DIFF_SSTL12
0.900
0.600
0.675
(VCCO/2) – 0.160 (VCCO/2) + 0.160
(VCCO/2) – 0.175 (VCCO/2) + 0.175
DIFF_SSTL135
DIFF_SSTL15
0.750
0.900
DIFF_SSTL18_I
DIFF_SSTL18_II
N/A
N/A
N/A
N/A
0.900
Notes:
1.
2.
3.
4.
5.
6.
7.
V
V
V
V
V
V
V
is the input common mode voltage.
is the input differential voltage (Q – Q).
ICM
ID
is the output common mode voltage.
OCM
is the output differential voltage (Q – Q).
is the output crossing voltage (see JEDEC specifications for SSTL)
is the single-ended low-output voltage.
OD
OX
OL
OH
is the single-ended high-output voltage.
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
LVDS DC Specifications (LVDS_25)
See UG471: 7 Series FPGAs SelectIO Resources User Guide for more information on the LVDS_25 standard in the HR I/O
banks.
Table 10: LVDS_25 DC Specifications
Symbol
VCCO
VOH
DC Parameter
Supply Voltage
Conditions
Min
2.375
–
Typ
2.500
–
Max
2.625
1.675
–
Units
V
Output High Voltage for Q and Q
Output Low Voltage for Q and Q
RT = 100 across Q and Q signals
RT = 100 across Q and Q signals
RT = 100 across Q and Q signals
V
VOL
0.825
247
–
V
VODIFF
Differential Output Voltage (Q – Q),
Q = High (Q – Q), Q = High
350
600
mV
VOCM
VIDIFF
Output Common-Mode Voltage
RT = 100 across Q and Q signals
1.000
100
1.250
350
1.425
600
V
Differential Input Voltage (Q – Q),
Q = High (Q – Q), Q = High
mV
VICM
Input Common-Mode Voltage
0.300
1.200
1.425
V
eFUSE Programming Conditions
Table 11 lists the programming conditions specifically for eFUSE. For more information, see UG470: 7 Series FPGA
Configuration User Guide.
(1)
Table 11: eFUSE Programming Conditions
Symbol
Description
Min
–
Typ
–
Max
115
125
Units
mA
IFS
t j
Notes:
1. The FPGA must not be configured during eFUSE programming.
VCCAUX supply current
Temperature range
15
–
°C
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
GTP Transceiver Specifications
GTP Transceiver DC Characteristics
(1)
Table 12: Absolute Maximum Ratings for GTP Transceivers
Symbol
Description
Min
Max
Units
Analog supply voltage for the GTP transmitter and receiver circuits relative to
GND
–0.5
1.1
V
MGTAVCC
Analog supply voltage for the GTP transmitter and receiver termination circuits
relative to GND
–0.5
1.32
V
MGTAVTT
VIN
Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage
Reference clock absolute input voltage
–0.5
–0.5
1.26
1.32
V
V
VMGTREFCLK
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
(1)(2)
Table 13: Recommended Operating Conditions for GTP Transceivers
Symbol
Description
Min
Typ
Max
Units
Analog supply voltage for the GTP transmitter and receiver circuits relative to
GND
MGTAVCC
0.97
1.0
1.03
V
Analog supply voltage for the GTP transmitter and receiver termination circuits
relative to GND
MGTAVTT
1.17
1.2
1.23
V
Notes:
1. Each voltage listed requires the filter circuit described in UG482: 7 Series FPGAs GTP Transceiver User Guide.
2. Voltages are specified for the temperature range of T = 0°C to +85°C.
j
Table 14: GTP Transceiver Current Supply
Symbol
IMGTAVCC
Description
MGTAVCC supply current for one GTP Quad (4 lanes)
MGTAVTT supply current for one GTP Quad (4 lanes)
Typ(1)
Max
Units
mA
Note 2
IMGTAVTT
mA
Notes:
1. Typical values are specified at nominal voltage, 25°C, at the maximum line rate.
2. Values for currents of other transceiver configurations and conditions can be obtained by using the XPOWER Estimator (XPE) or XPOWER Analyzer
(XPA) tools.
(1)(2)
Table 15: GTP Transceiver Quiescent Supply Current
Symbol
IMGTAVCCQ
IMGTAVTTQ
Description
Typ(4)
Max
Units
mA
Quiescent MGTAVCC supply current for one GTP Quad (4 lanes)
Quiescent MGTAVTT supply current for one GTP Quad (4 lanes)
Note 3
mA
Notes:
1. Device powered and unconfigured.
2. GTP transceiver quiescent supply current for an entire device can be calculated by multiplying the values in this table by the number of available GTP
transceivers.
3. Currents for conditions other than values specified in this table can be obtained by using the XPOWER Estimator (XPE) or XPOWER Analyzer (XPA)
tools.
4. Typical values are specified at nominal voltage, 25°C.
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
GTP Transceiver DC Input and Output Levels
Table 16 summarizes the DC output specifications of the GTP transceivers in Artix-7 FPGAs. Consult UG482: 7 Series
FPGAs GTP Transceiver User Guide for further details.
Table 16: GTP Transceiver DC Specifications
Symbol
DC Parameter
Conditions
Min
Typ
Max
Units
Differential peak-to-peak input External AC coupled
voltage
–
2000
mV
DVPPIN
VIN
Absolute input voltage
DC coupled MGTAVTT = 1.2V
DC coupled MGTAVTT = 1.2V
–200
–
MGTAVTT
mV
mV
mV
VCMIN
Common mode input voltage
–
–
2/3 MGTAVTT
–
–
Differential peak-to-peak output Transmitter output swing is set to
1000
DVPPOUT
voltage(1)
maximum setting
DC common mode output
voltage
Equation based
MGTAVTT – DVPPOUT/4
mV
VCMOUTDC
VCMOUTAC
RIN
Common mode output voltage: AC coupled
Differential input resistance
1/2 MGTAVTT
mV
100
100
–
ROUT
Differential output resistance
Transmitter output pair (TXP and TXN) intra-pair skew
(Flip-chip packages)
–
–
–
10
12
–
ps
TOSKEW
Transmitter output pair (TXP and TXN) intra-pair skew
(Wire-bond packages)
–
ps
CEXT
Recommended external AC coupling capacitor(2)
100
nF
Notes:
1. The output swing and preemphasis levels are programmable using the attributes discussed in UG482: 7 Series FPGAs GTP Transceiver
User Guide and can result in values lower than reported in this table.
2. Other values can be used as appropriate to conform to specific protocols and standards.
X-Ref Target - Figure 1
+V
0
P
N
Single-Ended
Voltage
ds181_01_062811
Figure 1: Single-Ended Peak-to-Peak Voltage
X-Ref Target - Figure 2
+V
0
Differential
Voltage
P–N
–V
ds181_02_062811
Figure 2: Differential Peak-to-Peak Voltage
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
Table 17 summarizes the DC specifications of the clock input of the GTP transceiver. Consult UG482: 7 Series FPGAs GTP
Transceiver User Guide for further details.
Table 17: GTP Transceiver Clock DC Input Level Specification
Symbol
VIDIFF
DC Parameter
Differential peak-to-peak input voltage
Min
Typ
Max
Units
mV
250
2000
RIN
Differential input resistance
100
100
CEXT
Required external AC coupling capacitor
–
–
nF
GTP Transceiver Switching Characteristics
Consult UG482: 7 Series FPGAs GTP Transceiver User Guide for further information.
Table 18: GTP Transceiver Performance
Speed Grade
Output
Divider
Symbol
Description
1.0V
0.9V
-2L
Units
-3(1)
6.6
-2/-2L(1)
6.6
-1
FGTPMAX
Maximum GTP transceiver data rate
Minimum GTP transceiver data rate
3.75
3.75
Gb/s
Gb/s
Gb/s
Gb/s
Gb/s
Gb/s
GHz
FGTPMIN
0.500
0.500
0.500
0.500
1
2
4
8
3.2–6.6
1.6–3.3
0.8–1.65
0.5–0.825
1.6–3.3
3.2–6.6
1.6–3.3
0.8–1.65
0.5–0.825
1.6–3.3
3.2–3.75
1.6–3.2
0.8–1.6
0.5–0.8
1.6–3.3
3.2–3.75
1.6–3.2
0.8–1.6
0.5–0.8
1.6–3.3
FGTPRANGE
PLL line rate range
FGTPPLLRANGE GTP transceiver PLL frequency range
Notes:
1.
F
is limited to 5.4 Gb/s in wire bond packages.
GTPMAX
Table 19: GTP Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics
Speed Grade
1.0V
Symbol
Description
0.9V
-2L
Units
-3
-2/-2L
-1
FGTPDRPCLK
GTPDRPCLK maximum frequency
156
156
125
125
MHz
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
Table 20: GTP Transceiver Reference Clock Switching Characteristics
All Speed Grades
Symbol
Description
Conditions
Units
Min
60
–
Typ
–
Max
660
–
FTXOUT
TRCLK
TXUSERCLKOUT maximum frequency
Reference clock rise time
MHz
ps
20% – 80%
200
200
–
TFCLK
Reference clock fall time
80% – 20%
–
–
ps
TDCREF
Reference clock duty cycle
Transceiver PLL only
40
–
60
%
Clock recovery frequency acquisition
time
–
ms
TLOCK
Initial PLL lock
Lock to data after PLL has locked
to the reference clock
–
–
µs
TPHASE
Clock recovery phase acquisition time
X-Ref Target - Figure 3
TRCLK
80%
20%
TFCLK
ds181_03_062811
Figure 3: Reference Clock Timing Parameters
(1)
Table 21: GTP Transceiver User Clock Switching Characteristics
Speed Grade
Symbol
Description
Conditions
1.0V
0.9V
-2L
Units
-3
-2/-2L
412.5
412.5
412.5
412.5
-1
FTXOUT
FRXOUT
FTXIN
TXOUTCLK maximum frequency
RXOUTCLKT maximum frequency
TXUSRCLK maximum frequency
RXUSRCLK maximum frequency
412.5
412.5
412.5
412.5
234.375
234.375
234.375
234.375
234.375
234.375
234.375
234.375
MHz
MHz
MHz
MHz
16-bit data path
16-bit data path
FRXIN
Notes:
1. Clocking must be implemented as described in UG482: 7 Series FPGAs GTP Transceiver User Guide.
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
Integrated Interface Block for PCI Express Designs Switching Characteristics
More information and documentation on solutions for PCI Express designs can be found at:
http://www.xilinx.com/technology/protocols/pciexpress.htm
Table 22: Maximum Performance for PCI Express Designs
Speed Grade
Symbol
Description
1.0V
-2/-2L
250
0.9V
-2L
Units
-3
-1
FPIPECLK
Pipe clock maximum frequency
250
250
250
250
250
250
250
250
250
250
250
250
MHz
MHz
MHz
MHz
FUSERCLK
FUSERCLK2
FDRPCLK
User clock maximum frequency
User clock 2 maximum frequency
DRP clock maximum frequency
250
250
250
XADC Specifications
Table 23: XADC Specifications
Parameter
Symbol
Comments/Conditions
Min
Typ
Max
Units
VCCADC = 1.8V 5%, VREFP = 1.25V, VREFN = 0V, ADCCLK = 26 MHz, Tj = –40°C to 100°C, Typical values at Tj=+40°C
ADC Accuracy(1)
Resolution
12
–
–
–
–
–
–
–
–
Bits
LSBs
LSBs
LSBs
%
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
2
DNL
No missing codes, guaranteed monotonic
–
1
4
Calibrated
Calibrated
–
Gain Error
–
0.4
10
Channel Matching
Based on two individual ADC instances with
calibration enabled
–
LSBs
Sample Rate
0.1
60
–
–
–
–
3
–
1
–
2
–
–
MS/s
dB
Signal to Noise Ratio
RMS Code Noise
SNR
THD
FSAMPLE = 500KS/s, FIN = 20KHz
External 1.25V reference
On-chip reference
LSBs
LSBs
dB
–
Total Harmonic Distortion
FSAMPLE = 500KS/s, FIN = 20KHz
75
ADC Accuracy at Extended Temperatures (-55°C to 125°C)
Resolution
10
–
–
–
–
–
1
1
Bits
Integral Nonlinearity
Differential Nonlinearity
Analog Inputs(2)
INL
LSB
(at 10 bits)
DNL
No missing codes, guaranteed monotonic
–
ADC Input Ranges
Unipolar operation
0
–
–
–
–
–
1
V
V
V
V
V
Bipolar operation
–0.5
0
+0.5
Unipolar common mode range (FS input)
Bipolar common mode range (FS input)
+0.5
+0.5
–0.1
+0.6
Maximum External Channel
Input Ranges
Adjacent channels set within these ranges
should not corrupt measurements on adjacent
channels
VCCADC
Auxiliary Channel Full
Resolution Bandwidth
FRBW
250
–
–
KHz
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
Table 23: XADC Specifications (Cont’d)
Parameter Symbol
On-Chip Sensors
Comments/Conditions
Min
Typ
Max
Units
Temperature Sensor Error
Tj = –40°C to 100°C.
–
–
–
–
–
–
4
6
1
°C
°C
%
Tj = –55°C to +125°C
Supply Sensor Error
Measurement range of VCCAUX 1.8V 5%
Tj = –40°C to +100°C
Measurement range of VCCAUX 1.8V 5%
Tj = –55°C to +125°C
–
–
2
%
Conversion Rate(3)
Conversion Time - Continuous tCONV
Number of ADCCLK cycles
Number of CLK cycles
DRP clock frequency
Derived from DCLK
26
–
–
–
–
–
–
32
21
Conversion Time - Event
DRP Clock Frequency
ADC Clock Frequency
DCLK Duty Cycle
tCONV
DCLK
8
250
26
MHz
MHz
%
ADCCLK
1
40
60
XADC Reference(4)
External Reference
On-Chip Reference
VREFP
Externally supplied reference voltage
1.20
1.25
1.30
V
V
Ground VREFP pin to AGND,
Tj = –40°C to 100°C
1.2375 1.25
1.2625
Power Requirements
Analog Power Supply
Analog Supply Current
VCCADC
ICCADC
1.71
–
1.8
–
1.89
25
V
Analog circuits in powered up state
mA
Notes:
1. Offset and gain errors are removed by enabling the XADC automatic gain calibration feature. All values provided are with this feature
enabled.
2. See the ADC chapter in UG480: 7 Series FPGAs XADC User Guide for a detailed description.
3. See the Timing chapter in UG480: 7 Series FPGAs XADC User Guide for a detailed description.
4. Any variation in the reference voltage from the nominal V
= 1.25V and V
= 0V will result in a deviation from the ideal transfer
REFP
REFN
function. This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for external
ratiometric type applications allowing reference to vary by 4% is permitted. On-chip reference variation is 1%.
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
Performance Characteristics
This section provides the performance characteristics of some common functions and designs implemented in Artix-7
devices. The numbers reported here are worst-case values; they have all been fully characterized. These values are subject
to the same guidelines as the Switching Characteristics, page 15.
Table 24: Networking Applications Interface Performances
Speed Grade
Description
1.0V
-2/-2L
710
0.9V
-2L
Units
-3
-1
SDR LVDS transmitter
(using OSERDES; DATA_WIDTH = 4 to 8)
710
625
Mb/s
Mb/s
DDR LVDS transmitter
1250(2) 1152(3) 1250(2) 1152(3)
950(2)
800(3)
(using OSERDES; DATA_WIDTH = 4 to 14)
SDR LVDS receiver (SFI-4.1)(1)
DDR LVDS receiver (SPI-4.2)(1)
710
710
625
950
Mb/s
Mb/s
1250
1250
Notes:
1. LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) algorithms dominate
deterministic performance.
2. Some DDR LVDS transmitter frequencies are bounded by the performance of the TX interface to provide a clock with 5% DCD. The values
in this column show the maximum rate that the LVDS can drive a clock at 5% DCD.
3. Some DDR LVDS transmitter frequencies are bounded by the performance of the TX interface to provide a clock with 10% DCD. The values
in this column show the maximum rate that the LVDS can drive a clock at 10% DCD.
(1)
Table 25: Maximum Physical Interface (PHY) Rate for Memory Interfaces
Speed Grade
Memory Standard
1.0V
-2/-2L
800
0.9V
-2L
Units
-3
-1
DDR3
1066
800
800
667
800
667
667
533
Mb/s
Mb/s
Mb/s
Mb/s
DDR3L
DDR2
800
800
LPDDR2
667
Notes:
1. Advance performance numbers pending characterization on Xilinx memory platforms designed according to the guidelines in the 7 Series
FPGAs Memory Interface Solutions User Guide.
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
Switching Characteristics
All values represented in this data sheet are based on the advance speed specifications in ISE® software 13.4 v1.02 for the
-3, -2, and -1 speed grades and v1.00 for the -2L speed grade.
Switching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or
Production. Each designation is defined as follows:
Advance
These specifications are based on simulations only and are typically available soon after device design specifications are
frozen. Although speed grades with this designation are considered relatively stable and conservative, some under-
reporting might still occur.
Preliminary
These specifications are based on complete ES (engineering sample) silicon characterization. Devices and speed grades
with this designation are intended to give a better indication of the expected performance of production silicon. The
probability of under-reporting delays is greatly reduced as compared to Advance data.
Production
These specifications are released once enough production silicon of a particular device family member has been
characterized to provide full correlation between specifications and devices over numerous production lots. There is no
under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest
speed grades transition to Production before faster speed grades.
All specifications are always representative of worst-case supply voltage and junction temperature conditions.
Since individual family members are produced at different times, the migration from one category to another depends
completely on the status of the fabrication process for each device. Table 26 correlates the current status of each Artix-7
device on a per speed grade basis.
Table 26: Artix-7 Device Speed Grade Designations
Speed Grade Designations
Device
Advance
Preliminary
Production
XC7A100T
XC7A200T
XC7A350T
-3, -2, -2L (1.0V), -1, -2L (0.9V)
-3, -2, -2L (1.0V), -1, -2L (0.9V)
-3, -2, -2L (1.0V), -1, -2L (0.9V)
Testing of Switching Characteristics
All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed
below are representative values.
For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and
back-annotate to the simulation net list. Unless otherwise noted, values apply to all Artix-7 devices.
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
Production Silicon and ISE Software Status
In some cases, a particular family member (and speed grade) is released to production before a speed specification is
released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent
speed specification releases.
Table 27 lists the production released Artix-7 device, speed grade, and the minimum corresponding supported speed
specification version and ISE software revisions. The ISE software and speed specifications listed are the minimum releases
required for production. All subsequent releases of software and speed specifications are valid.
Table 27: Artix-7 Device Production Software and Speed Specification Release
Speed Grade
Device
1.0V
0.9V
-2L
-3
-2/-2L
-1
XC7A100T
XC7A200T
XC7A350T
Notes:
1. Blank entries indicate a device and/or speed grade in advance or preliminary status.
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
IOB Pad Input/Output/3-State Switching Characteristics
Table 28 summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based
on standard) and 3-state delays.
T
is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies depending
IOPI
on the capability of the SelectIO input buffer.
T
is described as the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies
IOOP
depending on the capability of the SelectIO output buffer.
T
is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is
IOTP
disabled. The delay varies depending on the SelectIO capability of the output buffer.
Table 29 summarizes the value of T . T is described as the delay from the T pin to the IOB pad through the
IOTPHZ IOTPHZ
output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state).
Table 28: 3.3V IOB High Range (HR) Switching Characteristics
TIOPI
Speed Grade
1.0V
TIOOP
Speed Grade
1.0V
TIOTP
Speed Grade
1.0V
I/O Standard
Units
0.9V
-2L
0.9V
-2L
0.9V
-2L
-3 -2/-2L -1
-3 -2/-2L -1
-3 -2/-2L -1
LVTTL_S4
LVTTL_S8
LVTTL_S12
LVTTL_S16
LVTTL_S24
LVTTL_F4
LVTTL_F8
LVTTL_F12
LVTTL_F16
LVTTL_F24
LVDS_25
1.58 1.72 1.93 1.65 5.85 6.33 7.06 5.80 5.85 6.33 7.06 5.80
1.58 1.72 1.93 1.65 5.85 6.33 7.06 5.06 5.85 6.33 7.06 5.06
1.58 1.72 1.93 1.65 4.68 4.92 5.29 5.06 4.68 4.92 5.29 5.06
1.58 1.72 1.93 1.65 4.65 4.90 5.27 4.13 4.65 4.90 5.27 4.13
1.58 1.72 1.93 1.65 3.64 4.08 4.72 4.22 3.64 4.08 4.72 4.22
1.58 1.72 1.93 1.65 5.86 6.28 6.89 5.16 5.86 6.28 6.89 5.16
1.58 1.72 1.93 1.65 5.75 6.20 6.89 4.27 5.75 6.20 6.89 4.27
1.58 1.72 1.93 1.65 4.56 4.80 5.15 4.25 4.56 4.80 5.15 4.25
1.58 1.72 1.93 1.65 4.56 4.79 5.14 3.04 4.56 4.79 5.14 3.04
1.58 1.72 1.93 1.65 2.66 3.44 4.60 2.83 2.66 3.44 4.60 2.83
0.72 0.78 0.87 0.83 1.41 1.50 1.65 1.44 1.41 1.50 1.65 1.44
0.71 0.77 0.85 0.81 1.41 1.50 1.65 1.44 1.41 1.50 1.65 1.44
0.72 0.79 0.89 0.84 1.93 2.13 2.41 2.02 1.93 2.13 2.41 2.02
0.71 0.78 0.88 0.83 1.41 1.50 1.65 1.44 1.41 1.50 1.65 1.44
0.74 0.80 0.90 0.85 1.38 1.50 1.68 1.50 1.38 1.50 1.68 1.50
0.85 0.93 1.06 0.91 1.47 1.57 1.71 1.50 1.47 1.57 1.71 1.50
1.55 1.69 1.91 1.64 2.97 3.28 3.75 2.92 2.97 3.28 3.75 2.92
0.66 0.70 0.76 0.75 2.34 2.66 3.14 2.35 2.34 2.66 3.14 2.35
0.63 0.68 0.76 0.75 1.96 2.19 2.54 2.05 1.96 2.19 2.54 2.05
0.67 0.72 0.79 0.77 1.54 1.67 1.86 1.68 1.54 1.67 1.86 1.68
0.67 0.72 0.79 0.77 1.14 1.22 1.34 1.24 1.14 1.22 1.34 1.24
0.68 0.72 0.79 0.79 1.32 1.43 1.59 1.42 1.32 1.43 1.59 1.42
0.68 0.72 0.79 0.79 1.20 1.29 1.42 1.24 1.20 1.29 1.42 1.24
0.72 0.76 0.83 0.81 1.43 1.54 1.71 1.52 1.43 1.54 1.71 1.52
0.72 0.76 0.83 0.81 1.10 1.18 1.29 1.21 1.10 1.18 1.29 1.21
0.73 0.78 0.86 0.83 1.26 1.35 1.50 1.35 1.26 1.35 1.50 1.35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MINI_LVDS_25
BLVDS_25
RSDS_25 (point to point)
PPDS_25
TMDS_33
PCI33_3
HSUL_12
DIFF_HSUL_12
HSTL_I_S
HSTL_II_S
HSTL_I_18_S
HSTL_II_18_S
DIFF_HSTL_I_S
DIFF_HSTL_II_S
DIFF_HSTL_I_18_S
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
Table 28: 3.3V IOB High Range (HR) Switching Characteristics (Cont’d)
TIOPI
Speed Grade
1.0V
TIOOP
Speed Grade
1.0V
TIOTP
Speed Grade
1.0V
I/O Standard
Units
0.9V
-2L
0.9V
-2L
0.9V
-2L
-3 -2/-2L -1
-3 -2/-2L -1
-3 -2/-2L -1
DIFF_HSTL_II_18_S
0.73 0.78 0.86 0.83 1.10 1.18 1.29 1.21 1.10 1.18 1.29 1.21
0.67 0.72 0.79 0.77 1.10 1.19 1.33 1.22 1.10 1.19 1.33 1.22
0.67 0.72 0.79 0.77 0.99 1.08 1.21 1.13 0.99 1.08 1.21 1.13
0.68 0.72 0.79 0.79 1.07 1.16 1.30 1.20 1.07 1.16 1.30 1.20
0.68 0.72 0.79 0.79 1.00 1.09 1.22 1.11 1.00 1.09 1.22 1.11
0.72 0.76 0.83 0.81 1.04 1.13 1.26 1.15 1.04 1.13 1.26 1.15
0.72 0.76 0.83 0.81 0.97 1.05 1.17 1.09 0.97 1.05 1.17 1.09
0.73 0.78 0.86 0.83 1.03 1.12 1.24 1.14 1.03 1.12 1.24 1.14
0.73 0.78 0.86 0.83 0.96 1.04 1.16 1.07 0.96 1.04 1.16 1.07
1.79 1.91 2.10 1.66 5.68 6.09 6.70 5.79 5.68 6.09 6.70 5.79
1.79 1.91 2.10 1.66 4.82 5.27 5.95 5.06 4.82 5.27 5.95 5.06
1.79 1.91 2.10 1.66 3.88 4.29 4.90 4.12 3.88 4.29 4.90 4.12
1.79 1.91 2.10 1.66 3.33 3.72 4.30 3.65 3.33 3.72 4.30 3.65
1.79 1.91 2.10 1.66 5.07 5.38 5.85 5.15 5.07 5.38 5.85 5.15
1.79 1.91 2.10 1.66 4.31 4.61 5.06 4.25 4.31 4.61 5.06 4.25
1.79 1.91 2.10 1.66 2.74 3.45 4.52 3.04 2.74 3.45 4.52 3.04
1.79 1.91 2.10 1.66 2.62 2.88 3.29 2.88 2.62 2.88 3.29 2.88
1.50 1.60 1.74 1.39 4.98 5.47 6.21 4.82 4.98 5.47 6.21 4.82
1.50 1.60 1.74 1.39 3.91 4.35 5.01 4.07 3.91 4.35 5.01 4.07
1.50 1.60 1.74 1.39 3.10 3.65 4.49 3.14 3.10 3.65 4.49 3.14
1.50 1.60 1.74 1.39 3.55 3.99 4.65 3.64 3.55 3.99 4.65 3.64
1.50 1.60 1.74 1.39 4.72 5.08 5.63 4.33 4.72 5.08 5.63 4.33
1.50 1.60 1.74 1.39 2.75 3.31 4.14 2.95 2.75 3.31 4.14 2.95
1.50 1.60 1.74 1.39 2.75 3.30 4.14 2.69 2.75 3.30 4.14 2.69
1.50 1.60 1.74 1.39 2.20 2.54 3.06 2.20 2.20 2.54 3.06 2.20
0.79 0.84 0.90 0.78 3.74 3.96 4.28 3.45 3.74 3.96 4.28 3.45
0.79 0.84 0.90 0.78 2.94 3.29 3.83 2.94 2.94 3.29 3.83 2.94
0.79 0.84 0.90 0.78 2.94 3.29 3.83 2.94 2.94 3.29 3.83 2.94
0.79 0.84 0.90 0.78 2.03 2.28 2.66 2.05 2.03 2.28 2.66 2.05
0.79 0.84 0.90 0.78 1.89 2.09 2.37 1.94 1.89 2.09 2.37 1.94
0.79 0.84 0.90 0.78 3.60 3.77 4.02 3.33 3.60 3.77 4.02 3.33
0.79 0.84 0.90 0.78 2.14 2.48 2.98 2.15 2.14 2.48 2.98 2.15
0.79 0.84 0.90 0.78 2.14 2.48 2.98 2.15 2.14 2.48 2.98 2.15
0.79 0.84 0.90 0.78 1.62 1.79 2.05 1.69 1.62 1.79 2.05 1.69
0.79 0.84 0.90 0.78 1.37 1.50 1.69 1.47 1.37 1.50 1.69 1.47
0.81 0.87 0.96 0.81 4.17 4.42 4.80 3.82 4.17 4.42 4.80 3.82
0.81 0.87 0.96 0.81 2.53 2.87 3.38 2.67 2.53 2.87 3.38 2.67
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
HSTL_I_F
HSTL_II_F
HSTL_I_18_F
HSTL_II_18_F
DIFF_HSTL_I_F
DIFF_HSTL_II_F
DIFF_HSTL_I_18_F
DIFF_HSTL_II_18_F
LVCMOS33_S4
LVCMOS33_S8
LVCMOS33_S12
LVCMOS33_S16
LVCMOS33_F4
LVCMOS33_F8
LVCMOS33_F12
LVCMOS33_F16
LVCMOS25_S4
LVCMOS25_S8
LVCMOS25_S12
LVCMOS25_S16
LVCMOS25_F4
LVCMOS25_F8
LVCMOS25_F12
LVCMOS25_F16
LVCMOS18_S4
LVCMOS18_S8
LVCMOS18_S12
LVCMOS18_S16
LVCMOS18_S24
LVCMOS18_F4
LVCMOS18_F8
LVCMOS18_F12
LVCMOS18_F16
LVCMOS18_F24
LVCMOS15_S4
LVCMOS15_S8
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
Table 28: 3.3V IOB High Range (HR) Switching Characteristics (Cont’d)
TIOPI
Speed Grade
1.0V
TIOOP
Speed Grade
1.0V
TIOTP
Speed Grade
1.0V
I/O Standard
Units
0.9V
-2L
0.9V
-2L
0.9V
-2L
-3 -2/-2L -1
-3 -2/-2L -1
-3 -2/-2L -1
LVCMOS15_S12
0.81 0.87 0.96 0.81 2.03 2.25 2.60 2.06 2.03 2.25 2.60 2.06
0.81 0.87 0.96 0.81 1.93 2.13 2.45 1.97 1.93 2.13 2.45 1.97
0.81 0.87 0.96 0.81 3.98 4.21 4.55 3.65 3.98 4.21 4.55 3.65
0.81 0.87 0.96 0.81 1.87 2.12 2.50 1.97 1.87 2.12 2.50 1.97
0.81 0.87 0.96 0.81 1.45 1.60 1.82 1.55 1.45 1.60 1.82 1.55
0.81 0.87 0.96 0.81 1.42 1.56 1.77 1.52 1.42 1.56 1.77 1.52
0.91 0.97 1.05 0.85 4.69 5.09 5.69 4.27 4.69 5.09 5.69 4.27
0.91 0.97 1.05 0.85 3.19 3.68 4.41 3.01 3.19 3.68 4.41 3.01
0.91 0.97 1.05 0.85 2.34 2.66 3.14 2.35 2.34 2.66 3.14 2.35
0.91 0.97 1.05 0.85 4.14 4.44 4.89 3.77 4.14 4.44 4.89 3.77
0.91 0.97 1.05 0.85 1.99 2.62 3.57 2.10 1.99 2.62 3.57 2.10
0.91 0.97 1.05 0.85 1.65 1.85 2.15 1.73 1.65 1.85 2.15 1.73
0.67 0.70 0.75 0.73 1.13 1.21 1.34 1.28 1.13 1.21 1.34 1.28
0.67 0.72 0.79 0.77 1.13 1.21 1.34 1.24 1.13 1.21 1.34 1.24
0.68 0.72 0.79 0.79 1.58 1.71 1.91 1.71 1.58 1.71 1.91 1.71
0.68 0.72 0.79 0.79 1.12 1.21 1.33 1.24 1.12 1.21 1.33 1.24
0.65 0.72 0.82 0.75 1.13 1.21 1.34 1.28 1.13 1.21 1.34 1.28
0.72 0.76 0.83 0.81 1.13 1.21 1.34 1.24 1.13 1.21 1.34 1.24
0.73 0.78 0.86 0.83 1.53 1.66 1.85 1.61 1.53 1.66 1.85 1.61
0.73 0.78 0.86 0.83 1.09 1.17 1.28 1.19 1.09 1.17 1.28 1.19
0.67 0.70 0.75 0.73 1.01 1.09 1.22 1.12 1.01 1.09 1.22 1.12
0.67 0.72 0.79 0.77 1.00 1.08 1.21 1.13 1.00 1.08 1.21 1.13
0.68 0.72 0.79 0.79 1.10 1.19 1.32 1.22 1.10 1.19 1.32 1.22
0.68 0.72 0.79 0.79 0.99 1.07 1.19 1.11 0.99 1.07 1.19 1.11
0.65 0.72 0.82 0.75 1.01 1.09 1.22 1.12 1.01 1.09 1.22 1.12
0.72 0.76 0.83 0.81 1.00 1.08 1.21 1.13 1.00 1.08 1.21 1.13
0.73 0.78 0.86 0.83 1.06 1.14 1.27 1.17 1.06 1.14 1.27 1.17
0.73 0.78 0.86 0.83 0.96 1.04 1.16 1.08 0.96 1.04 1.16 1.08
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVCMOS15_S16
LVCMOS15_F4
LVCMOS15_F8
LVCMOS15_F12
LVCMOS15_F16
LVCMOS12_S4
LVCMOS12_S8
LVCMOS12_S12
LVCMOS12_F4
LVCMOS12_F8
LVCMOS12_F12
SSTL135_S
SSTL15_S
SSTL18_I_S
SSTL18_II_S
DIFF_SSTL135_S
DIFF_SSTL15_S
DIFF_SSTL18_I_S
DIFF_SSTL18_II_S
SSTL135_F
SSTL15_F
SSTL18_I_F
SSTL18_II_F
DIFF_SSTL135_F
DIFF_SSTL15_F
DIFF_SSTL18_I_F
DIFF_SSTL18_II_F
Table 29: IOB 3-state ON Output Switching Characteristics (T
)
IOTPHZ
Speed Grade
1.0V
Symbol
Description
0.9V
-2L
Units
-3
-2/-2L
-1
TIOTPHZ
T input to Pad high-impedance
2.39
2.56
2.80
2.03
ns
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
Input/Output Logic Switching Characteristics
Table 30: ILOGIC Switching Characteristics
Speed Grade
1.0V
Symbol
Description
0.9V
-2L
Units
-3
-2/-2L
-1
Setup/Hold
TICE1CK/TICKCE1
CE1 pin Setup/Hold with respect to CLK
0.36/
0.07
0.42/
0.08
0.51/
0.10
0.40/
–0.07
ns
ns
ns
ns
TISRCK/TICKSR
IDOCK/TIOCKD
SR pin Setup/Hold with respect to CLK
1.17/
–0.14
1.36/
–0.14
1.64/
–0.14
0.88/
–0.35
T
D pin Setup/Hold with respect to CLK without Delay
DDLY pin Setup/Hold with respect to CLK (using IDELAY)
0.13/
0.31
0.15/
0.35
0.18/
0.40
0.01/
0.33
TIDOCKD/TIOCKDD
0.17/
0.31
0.19/
0.35
0.24/
0.40
0.01/
0.33
Combinatorial
TIDI
D pin to O pin propagation delay, no Delay
0.22
0.25
0.24
0.29
0.28
0.33
0.14
0.15
ns
ns
TIDID
DDLY pin to O pin propagation delay (using IDELAY)
Sequential Delays
TIDLO
D pin to Q1 pin using flip-flop as a latch without Delay
DDLY pin to Q1 pin using flip-flop as a latch (using IDELAY)
CLK to Q outputs
0.57
0.60
0.64
1.32
7.60
0.63
0.67
0.71
1.52
7.60
0.73
0.78
0.82
1.81
10.51
0.54
0.55
0.71
1.32
11.39
ns
ns
ns
ns
ns
TIDLOD
TICKQ
TRQ_ILOGIC
TGSRQ_ILOGIC
Set/Reset
TRPW_ILOGIC
SR pin to OQ/TQ out
Global Set/Reset to Q outputs
Minimum Pulse Width, SR inputs
0.74
0.78
0.84
0.68
ns, Min
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
Speed Grade
Table 31: OLOGIC Switching Characteristics
Symbol
Description
1.0V
0.9V
-2L
Units
-3
-2/-2L
-1
Setup/Hold
TODCK/TOCKD
D1/D2 pins Setup/Hold with respect to CLK
OCE pin Setup/Hold with respect to CLK
SR pin Setup/Hold with respect to CLK
T1/T2 pins Setup/Hold with respect to CLK
TCE pin Setup/Hold with respect to CLK
0.65/
–0.22
0.72/
–0.22
0.83/
–0.22
0.60/
–0.18
ns
ns
ns
ns
ns
TOOCECK/TOCKOCE
0.15/
–0.06
0.18/
–0.06
0.22/
–0.06
0.21/
–0.10
TOSRCK/TOCKSR
0.63/
–0.20
0.75/
–0.20
0.94/
–0.20
0.62/
–0.25
TOTCK/TOCKT
0.62/
–0.21
0.70/
–0.21
0.82/
–0.21
0.60/
–0.18
TOTCECK/TOCKTCE
0.14/
–0.05
0.16/
–0.05
0.20/
–0.05
0.22/
–0.10
Combinatorial
TODQ
D1 to OQ out or T1 to TQ out
0.92
1.04
1.22
1.18
ns
Sequential Delays
TOCKQ
CLK to OQ/TQ out
0.37
0.66
7.60
0.42
0.76
7.60
0.49
0.90
0.63
1.12
ns
ns
ns
TRQ_OLOGIC
TGSRQ_OLOGIC
Set/Reset
SR pin to OQ/TQ out
Global Set/Reset to Q outputs
10.51
11.39
TRPW_OLOGIC
Minimum Pulse Width, SR inputs
0.74
0.78
0.84
0.68
ns, Min
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
Input Serializer/Deserializer Switching Characteristics
Table 32: ISERDES Switching Characteristics
Speed Grade
1.0V
Symbol
Description
0.9V
-2L
Units
-3
-2/-2L
-1
Setup/Hold for Control Lines
TISCCK_BITSLIP/ TISCKC_BITSLIP BITSLIP pin Setup/Hold with respect to CLKDIV
0.01/
0.12
0.02/
0.13
0.02/
0.15
0.02/
0.21
ns
ns
ns
(2)
TISCCK_CE / TISCKC_CE
CE pin Setup/Hold with respect to CLK (for CE1)
0.26/
–0.03
0.30/
–0.03
0.37/
–0.03
0.35/
–0.11
(2)
T
ISCCK_CE2 / TISCKC_CE2
CE pin Setup/Hold with respect to CLKDIV (for
CE2)
–0.12/
0.23
–0.12/
0.26
–0.12/
0.30
–0.17/
0.40
Setup/Hold for Data Lines
TISDCK_D /TISCKD_D
D pin Setup/Hold with respect to CLK
0.03/
0.14
0.03/
0.16
0.04/
0.20
–0.04/
0.19
ns
ns
ns
ns
TISDCK_DDLY /TISCKD_DDLY
DDLY pin Setup/Hold with respect to CLK (using
IDELAY)(1)
0.06/
0.11
0.07/
0.12
0.09/
0.14
–0.03/
0.19
TISDCK_D_DDR /TISCKD_D_DDR
D pin Setup/Hold with respect to CLK at DDR
mode
0.03/
0.14
0.03/
0.16
0.04/
0.20
–0.04/
0.19
TISDCK_DDLY_DDR
/
D pin Setup/Hold with respect to CLK at DDR
mode (using IDELAY)(1)
0.11/
0.11
0.12/
0.12
0.14/
0.14
0.19/
0.19
TISCKD_DDLY_DDR
Sequential Delays
TISCKO_Q
CLKDIV to out at Q pin
D input to DO output pin
0.43
0.26
0.47
0.29
0.53
0.32
0.67
0.25
ns
ns
Propagation Delays
TISDO_DO
Notes:
1. Recorded at 0 tap value.
2.
T
and T
are reported as T
/T
in TRACE report.
ISCCK_CE2
ISCKC_CE2
ISCCK_CE ISCKC_CE
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
Output Serializer/Deserializer Switching Characteristics
Table 33: OSERDES Switching Characteristics
Speed Grade
1.0V
Symbol
Description
0.9V
-2L
Units
-3
-2/-2L
-1
Setup/Hold
TOSDCK_D/TOSCKD_D
D input Setup/Hold with respect to CLKDIV
T input Setup/Hold with respect to CLK
T input Setup/Hold with respect to CLKDIV
OCE input Setup/Hold with respect to CLK
0.26/
–0.15
0.29/
–0.15
0.34/
–0.15
0.44/
–0.25
ns
ns
ns
ns
(1)
TOSDCK_T/TOSCKD_T
0.62/
–0.15
0.70/
–0.15
0.82/
–0.15
0.60/
–0.25
(1)
TOSDCK_T2/TOSCKD_T2
0.27/
–0.15
0.30/
–0.15
0.34/
–0.15
0.46/
–0.25
TOSCCK_OCE/TOSCKC_OCE
0.15/
–0.06
0.18/
–0.06
0.22/
–0.06
0.21/
–0.15
TOSCCK_S
SR (Reset) input Setup with respect to CLKDIV
TCE input Setup/Hold with respect to CLK
0.41
0.46
0.53
0.70
ns
ns
TOSCCK_TCE/TOSCKC_TCE
0.14/
–0.05
0.16/
–0.05
0.20/
–0.05
0.22/
–0.15
Sequential Delays
TOSCKO_OQ
Clock to out from CLK to OQ
Clock to out from CLK to TQ
0.33
0.33
0.37
0.37
0.44
0.44
0.54
0.63
ns
ns
TOSCKO_TQ
Combinatorial
TOSDO_TTQ
T input to TQ Out
0.92
1.03
1.21
1.18
ns
Notes:
1.
T
and T
are reported as T
/T
in TRACE report.
OSDCK_T2
OSCKD_T2
OSDCK_T OSCKD_T
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
Input/Output Delay Switching Characteristics
Table 34: Input/Output Delay Switching Characteristics
Speed Grade
1.0V
Symbol
Description
0.9V
-2L
Units
-3
-2/-2L
-1
IDELAYCTRL
TDLYCCO_RDY
Reset to Ready for IDELAYCTRL
Attribute REFCLK frequency = 200.0(1)
Attribute REFCLK frequency = 300.0(1)
REFCLK precision
3.83
200
3.83
200
3.83
200
N/A
3.22
200
N/A
10
µs
FIDELAYCTRL_REF
MHz
MHz
MHz
ns
300
300
IDELAYCTRL_REF_PRECISION
TIDELAYCTRL_RPW
IDELAY
10
10
10
Minimum Reset pulse width
61.95
61.95
61.95
52.00
TIDELAYRESOLUTION
IDELAY chain delay resolution
1/(32 x 2 x FREF
)
ps
Pattern dependent period jitter in delay
chain for clock pattern.(2)
0
6
0
0
0
5
ps
per tap
Pattern dependent period jitter in delay
chain for random data pattern
(PRBS 23)(3)
6
6
ps
per tap
TIDELAYPAT_JIT
Pattern dependent period jitter in delay
chain for random data pattern
(PRBS 23)(4)
11
11
11
9
ps
per tap
TIDELAY_CLK_MAX
Maximum frequency of CLK input to
IDELAY
560
560
495
800
MHz
ns
TIDCCK_CE / TIDCKC_CE
CE pin Setup/Hold with respect to C
INC pin Setup/Hold with respect to C
RST pin Setup/Hold with respect to C
Propagation delay through IDELAY
–0.02/
0.24
–0.02/
0.29
–0.02/
0.35
0.14/
0.16
T
IDCCK_INC/ TIDCKC_INC
0.11/
0.29
0.13/
0.33
0.14/
0.40
0.10/
0.23
ns
TIDCCK_RST/ TIDCKC_RST
0.12/
0.31
0.14/
0.36
0.16/
0.45
0.22
0.19
ns
TIDDO_IDATAIN
Note 5
Note 5
Note 5
Note 5
ps
Notes:
1. Average Tap Delay at 200 MHz = 78 ps, at 300 MHz = 52 ps.
2. When HIGH_PERFORMANCE mode is set to TRUE or FALSE.
3. When HIGH_PERFORMANCE mode is set to TRUE.
4. When HIGH_PERFORMANCE mode is set to FALSE.
5. Delay depends on IDELAY tap setting. See TRACE report for actual values.
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
I/O FIFO Switching Characteristics
Table 35: IO_FIFO Switching Characteristics
Speed Grade
Symbol
Description
1.0V
0.9V
-2L
Units
-3
-2/-2L
-1
IO_FIFO Clock to Out Delays
TOFFCKO_DO
RDCLK to Q outputs
0.35
0.44
0.45
0.58
0.45
0.58
0.45
0.55
ns
ns
TCKO_FLAGS
Clock to IO_FIFO Flags
Setup/Hold
T
CCK_D/TCKC_D
D inputs to WRCLK
0.64/
–0.09
0.80/
–0.08
0.80/
–0.08/
0.76/
–0.05
ns
ns
ns
TIFFCCK_WREN /TIFFCKC_WREN WREN to WRCLK
OFFCCK_RDEN/TOFFCKC_RDEN RDEN to RDCLK
0.53/
–0.07
0.69/
–0.07
0.69/
–0.07
0.70/
–0.05
T
0.63/
–0.03
0.80/
–0.03
0.80/
–0.03
0.79/
–0.02
Minimum Pulse Width
TPWH_IO_FIFO
RESET, RDCLK, WRCLK
RESET, RDCLK, WRCLK
1.62
1.62
2.15
2.15
2.15
2.15
1.29
1.29
ns
ns
TPWL_IO_FIFO
Maximum Frequency
FMAX
RDCLK and WRCLK
266
200
200
200
MHz
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
CLB Switching Characteristics
Table 36: CLB Switching Characteristics
Speed Grade
Symbol
Description
1.0V
0.9V
-2L
Units
-3
-2/-2L
-1
Combinatorial Delays
TILO
An – Dn LUT address to A
An – Dn LUT address to AMUX/CMUX
An – Dn LUT address to BMUX_A
An – Dn inputs to A – D Q outputs
AX inputs to AMUX output
AX inputs to BMUX output
AX inputs to CMUX output
AX inputs to DMUX output
BX inputs to BMUX output
BX inputs to DMUX output
CX inputs to CMUX output
CX inputs to DMUX output
DX inputs to DMUX output
An input to COUT output
Bn input to COUT output
Cn input to COUT output
Dn input to COUT output
AX input to COUT output
BX input to COUT output
CX input to COUT output
DX input to COUT output
CIN input to COUT output
CIN input to AMUX output
CIN input to BMUX output
CIN input to CMUX output
CIN input to DMUX output
0.10
0.27
0.42
0.94
0.62
0.58
0.60
0.68
0.51
0.62
0.42
0.53
0.52
0.53
0.51
0.42
0.42
0.45
0.39
0.30
0.30
0.10
0.41
0.37
0.33
0.38
0.11
0.30
0.46
1.05
0.69
0.66
0.68
0.75
0.57
0.69
0.48
0.59
0.58
0.60
0.57
0.48
0.48
0.50
0.43
0.34
0.33
0.10
0.45
0.43
0.37
0.43
0.13
0.36
0.55
1.27
0.84
0.83
0.82
0.90
0.69
0.82
0.58
0.71
0.70
0.73
0.70
0.59
0.59
0.60
0.52
0.41
0.40
0.12
0.55
0.53
0.44
0.52
0.15
0.41
0.65
1.51
1.01
0.98
0.98
1.08
0.82
0.99
0.69
0.86
0.84
0.87
0.84
0.70
0.70
0.73
0.64
0.50
0.49
0.15
0.66
0.63
0.53
0.62
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
TILO_2
TILO_3
TITO
TAXA
TAXB
TAXC
TAXD
TBXB
TBXD
TCXC
TCXD
TDXD
TOPCYA
TOPCYB
TOPCYC
TOPCYD
TAXCY
TBXCY
TCXCY
TDXCY
TBYP
TCINA
TCINB
TCINC
TCIND
Sequential Delays
TCKO
Clock to AQ – DQ outputs
0.40
0.47
0.44
0.53
0.53
0.66
0.62
0.73
ns, Max
ns, Max
TSHCKO
Clock to AMUX – DMUX outputs
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
Speed Grade
Table 36: CLB Switching Characteristics (Cont’d)
Symbol
Description
1.0V
0.9V
-2L
Units
-3
-2/-2L
-1
Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK
T
AS/TAH
AN – DN input to CLK on A – D Flip Flops
0.09/
0.14
0.11/
0.16
0.14
0.20
0.15
0.22
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
T
DICK/TCKDI
AX – DX input to CLK on A – D Flip Flops
0.06/
0.19
0.07/
0.21
0.09/
0.26
0.09/
0.31
AX – DX input through MUXs and/or carry logic to
CLK on A – D Flip Flops
0.59/
0.08
0.66/
0.09
0.81/
0.11
0.97/
0.12
TCECK_CLB
TCKCE_CLB
/
CE input to CLK on A – D Flip Flops
SR input to CLK on A – D Flip Flops
CIN input to CLK on A – D Flip Flops
0.15/
0.00
0.17/
0.00
0.21/
0.01
0.34/
–0.01
TSRCK/TCKSR
TCINCK/TCKCIN
0.38/
0.03
0.43/
0.04
0.53/
0.05
0.62/
0.05
0.28/
0.17
0.31/
0.19
0.38/
0.23
0.45/
0.27
Set/Reset
TSRMIN
TRQ
SR input minimum pulse width
0.52
0.53
0.52
1412
0.78
0.59
0.58
1286
1.04
0.71
0.70
1098
0.95
0.83
0.83
1286
ns, Min
ns, Max
ns, Max
MHz
Delay from SR input to AQ – DQ flip-flops
Delay from CE input to AQ – DQ flip-flops
Toggle frequency (for export control)
TCEO
FTOG
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
CLB Distributed RAM Switching Characteristics (SLICEM Only)
Table 37: CLB Distributed RAM Switching Characteristics
Speed Grade
1.0V
Symbol
Description
0.9V
-2L
Units
-3
-2/-2L
-1
Sequential Delays
TSHCKO
Clock to A – B outputs
Clock to AMUX – BMUX outputs
0.98
1.37
1.09
1.53
1.32
1.86
1.54
2.18
ns, Max
ns, Max
TSHCKO_1
Setup and Hold Times Before/After Clock CLK
DS_LRAM/TDH_LRAM A – D inputs to CLK
T
0.54/
0.28
0.60/
0.30
0.72/
0.35
0.96/
0.40
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
TAS_LRAM/TAH_LRAM
Address An inputs to clock
0.27/
0.55
0.30/
0.60
0.37/
0.70
0.43/
0.71
Address An inputs through MUXs and/or carry
logic to clock
0.69/
0.18
0.77/
0.21
0.94/
0.26
1.11/
0.29
T
WS_LRAM/TWH_LRAM WE input to clock
0.38/
0.10
0.43/
0.10
0.53/
0.12
0.62/
0.13
TCECK_LRAM
/
CE input to CLK
0.39/
0.10
0.44/
0.10
0.53/
0.11
0.63/
0.12
TCKCE_LRAM
Clock CLK
TMPW_LRAM
TMCP
Minimum pulse width
Minimum clock period
0.70
1.40
0.82
1.64
1.00
2.00
0.82
1.64
ns, Min
ns, Min
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time.
2. also represents the CLK to XMUX output. Refer to TRACE report for the CLK to XMUX path.
T
SHCKO
CLB Shift Register Switching Characteristics (SLICEM Only)
Table 38: CLB Shift Register Switching Characteristics
Speed Grade
Symbol
Description
1.0V
0.9V
-2L
Units
-3
-2/-2L
-1
Sequential Delays
TREG
Clock to A – D outputs
1.19
1.58
1.09
1.21
1.65
1.14
1.30
1.84
1.27
1.89
2.53
1.68
ns, Max
ns, Max
ns, Max
TREG_MUX
TREG_M31
Clock to AMUX – DMUX output
Clock to DMUX output via M31 output
Setup and Hold Times Before/After Clock CLK
TWS_SHFREG
/
WE input
0.37/
0.10
0.37/
0.11
0.37/
0.13
0.59/
0.13
ns, Min
ns, Min
ns, Min
TWH_SHFREG
TCECK_SHFREG
TCKCE_SHFREG
/
CE input to CLK
A – D inputs to CLK
0.37/
0.10
0.37/
0.11
0.37/
0.13
0.60/
0.12
TDS_SHFREG
/
0.33/
0.34
0.35/
0.35
0.40/
0.39
0.54/
0.47
TDH_SHFREG
Clock CLK
TMPW_SHFREG
Minimum pulse width
0.60
0.70
0.85
1.04
ns, Min
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time.
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
Block RAM and FIFO Switching Characteristics
Table 39: Block RAM and FIFO Switching Characteristics
Speed Grade
1.0V
Symbol
Description
0.9V
-2L
Units
-3
-2/-2L
-1
Block RAM and FIFO Clock-to-Out Delays
TRCKO_DO and
TRCKO_DO_REG
Clock CLK to DOUT output (without output
register)(2)(3)
2.10
2.33
2.68
3.24
ns, Max
(1)
Clock CLK to DOUT output (with output register)(4)(5) 0.73
0.81
3.20
0.94
3.84
1.11
5.30
ns, Max
ns, Max
TRCKO_DO_ECC and
TRCKO_DO_ECC_REG
Clock CLK to DOUT output with ECC (without output
register)(2)(3)
2.77
0.73
2.61
1.16
Clock CLK to DOUT output with ECC (with output
register)(4)(5)
0.81
2.88
1.28
0.94
3.30
1.46
1.11
3.76
1.56
ns, Max
ns, Max
ns, Max
T
RCKO_DO_CASCOUT and
Clock CLK to DOUT output with Cascade (without
output register)(2)
TRCKO_DO_CASCOUT_REG
Clock CLK to DOUT output with Cascade (with output
register)(4)
TRCKO_FLAGS
Clock CLK to FIFO flags outputs(6)
Clock CLK to FIFO pointers outputs(7)
0.76
0.94
0.83
1.02
0.85
2.95
0.76
0.83
0.92
1.15
0.94
3.55
0.89
0.94
1.02
1.30
1.10
4.90
1.05
1.15
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
TRCKO_POINTERS
TRCKO_PARITY_ECC
RCKO_SDBIT_ECC and
TRCKO_SDBIT_ECC_REG
Clock CLK to ECCPARITY in ECC encode only mode 0.78
T
Clock CLK to BITERR (without output register)
Clock CLK to BITERR (with output register)
2.56
0.68
0.75
T
RCKO_RDADDR_ECC and
Clock CLK to RDADDR output with ECC (without
output register)
TRCKO_RDADDR_ECC_REG
Clock CLK to RDADDR output with ECC (with output
register)
0.84
0.93
1.08
1.29
ns, Max
Setup and Hold Times Before/After Clock CLK
TRCCK_ADDRA/TRCKC_ADDRA
ADDR inputs(8)
0.45/
0.26
0.49/
0.28
0.57/
0.31
0.77/
0.36
ns, Min
ns, Min
TRDCK_DI_WF_NC
/
Data input setup/hold time when block RAM is
configured in WRITE_FIRST or NO_CHANGE
mode(9)
0.58/
0.26
0.65/
0.28
0.74/
0.30
0.92/
0.32
TRCKD_DI_WF_NC
TRDCK_DI_RF/TRCKD_DI_RF
RDCK_DI_ECC/TRCKD_DI_ECC
Data input setup/hold time when block RAM is
configured in READ_FIRST mode(9)
0.20/
0.26
0.22/
0.28
0.25/
0.30
0.29/
0.32
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
T
DIN inputs with block RAM ECC in standard mode(9) 0.50/
0.29
0.55
0.31
0.63/
0.33
0.78/
0.37
TRDCK_DI_ECCW/TRCKD_DI_ECCW DIN inputs with block RAM ECC encode only(9)
0.93/
0.29
1.02/
0.31
1.17/
0.33
1.38/
0.37
TRDCK_DI_ECC_FIFO
/
DIN inputs with FIFO ECC in standard mode(9)
Inject single/double bit error in ECC mode
Block RAM Enable (EN) input
1.04/
0.29
1.15/
0.31
1.32/
0.33
1.55/
0.37
TRCKD_DI_ECC_FIFO
TRCCK_INJECTBITERR
/
0.58/
0.24
0.64/
0.25
0.74/
0.26
0.92/
0.29
TRCKC_INJECTBITERR
TRCCK_EN/TRCKC_EN
RCCK_REGCE/TRCKC_REGCE
0.35/
0.20
0.39/
0.21
0.45/
0.23
0.57/
0.26
T
CE input of output register
0.24/
0.07
0.29/
0.07
0.36/
0.08
0.34/
0.07
TRCCK_RSTREG/TRCKC_RSTREG
Synchronous RSTREG input(10)
0.29/
0.04
0.32/
0.04
0.35/
0.04
0.41/
0.03
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
Table 39: Block RAM and FIFO Switching Characteristics (Cont’d)
Speed Grade
1.0V
Symbol
Description
0.9V
-2L
Units
-3
-2/-2L
-1
TRCCK_RSTRAM/TRCKC_RSTRAM
TRCCK_WEA/TRCKC_WEA
RCCK_WREN/TRCKC_WREN
Synchronous RSTRAM input
0.32/
0.16
0.33/
0.18
0.36/
0.19
0.40/
0.21
ns, Min
ns, Min
ns, Min
ns, Min
Write Enable (WE) input (Block RAM only)
WREN FIFO inputs
0.44/
0.18
0.48/
0.19
0.54/
0.20
0.64/
0.23
T
0.52/
0.20
0.57/
0.21
0.66/
0.23
0.77/
0.26
TRCCK_RDEN/TRCKC_RDEN
RDEN FIFO inputs
0.49/
0.13
0.54/
0.13
0.62/
0.14
0.71/
0.14
Reset Delays (Flags)
TRCO_RST
Reset RST to FIFO Flags/Pointers(11)
0.90
0.98
1.10
1.25
ns, Max
Maximum Frequency
FMAX_BRAM_WF_NC
Block RAM (Write first and No change modes)
When not in SDP RF mode
509
509
461
461
388
388
315
315
MHz
MHz
FMAX_BRAM_RF_PERFORMANCE
Block RAM (Read first, Performance mode)
When in SDP RF mode but no address overlap
between port A and port B
FMAX_BRAM_RF_DELAYED_WRITE
Block RAM (Read first, Delayed_write mode)
447
404
339
268
MHz
When in SDP RF mode and there is possibility of
overlap between port A and port B addresses
FMAX_CAS_WF_NC
Block RAM Cascade (Write first, No change mode)
When cascade but not in RF mode
467
467
418
418
345
345
273
273
MHz
MHz
FMAX_CAS_RF_PERFORMANCE
Block RAM Cascade (Read first, Performance mode)
When in cascade with RF mode and no possibility of
address overlap/one port is disabled
FMAX_CAS_RF_DELAYED_WRITE
When in cascade RF mode and there is a possibility
of address overlap between port A and port B
405
362
297
226
MHz
FMAX_FIFO
FMAX_ECC
FIFO in all modes without ECC
509
410
461
365
388
297
315
215
MHz
MHz
Block RAM and FIFO in ECC configuration
Notes:
1. TRACE will report all of these parameters as T
.
RCKO_DO
2.
3. These parameters also apply to synchronous FIFO with DO_REG = 0.
4. includes T as well as the B port equivalent timing parameters.
5. These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG = 1.
T
includes T
, T
, and T
as well as the B port equivalent timing parameters.
RCKO_DOR
RCKO_DOW RCKO_DOPR
RCKO_DOPW
T
RCKO_DO
RCKO_DOP
6.
7.
T
T
includes the following parameters: T
, T , T , T , T , T
RCKO_FLAGS
RCKO_AEMPTY RCKO_AFULL RCKO_EMPTY RCKO_FULL RCKO_RDERR RCKO_WRERR.
includes both T
and T
RCKO_POINTERS
RCKO_RDCOUNT
RCKO_WRCOUNT.
8. The ADDR setup and hold must be met when EN is asserted (even when WE is deasserted). Otherwise, block RAM data corruption is
possible.
9.
T
includes both A and B inputs as well as the parity inputs of A and B.
RCKO_DI
10. RDEN and WREN must be held Low prior to and during reset. The FIFO reset must be asserted for at least five positive clock edges of the
slowest clock (WRCLK or RDCLK).
11. T
includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT.
RCO_FLAGS
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
DSP48E1 Switching Characteristics
Table 40: DSP48E1 Switching Characteristics
Speed Grade
Symbol
Description
1.0V
0.9V
-2L
Units
-3
-2/-2L
-1
Setup and Hold Times of Data/Control Pins to the Input Register Clock
A input to A register CLK
B input to B register CLK
C input to C register CLK
D input to D register CLK
ACIN input to A register CLK
BCIN input to B register CLK
0.26/
0.12
0.30/
0.13
0.37/
0.14
0.45/
0.14
ns
ns
ns
ns
ns
ns
T
T
T
T
T
T
/ T
DSPDCK_A_AREG DSPCKD_A_AREG
0.33/
0.15
0.38/
0.16
0.45/
0.18
0.60/
0.19
/T
DSPDCK_B_BREG DSPCKD_B_BREG
0.17/
0.17
0.20/
0.19
0.24/
0.21
0.34/
0.29
/T
DSPDCK_C_CREG DSPCKD_C_CREG
0.25/
0.18
0.32/
0.20
0.42/
0.22
0.54/
0.23
/T
DSPDCK_D_DREG DSPCKD_D_DREG
0.23/
0.12
0.27/
0.13
0.32/
0.14
0.36/
0.14
/T
DSPDCK_ACIN_AREG DSPCKD_ACIN_AREG
0.25/
0.15
0.29/
0.16
0.36/
0.18
0.41/
0.19
/T
DSPDCK_BCIN_BREG DSPCKD_BCIN_BREG
Setup and Hold Times of Data Pins to the Pipeline Register Clock
TDSPDCK_ A, B _MREG_MULT
/
{A, B} input to M register CLK using
multiplier
2.40/
2.76/
3.29/
4.31/
ns
ns
{
}
TDSPCKD_B_MREG_MULT
–0.01 –0.01 –0.01 –0.07
TDSPDCK_ A, B _ADREG/ TDSPCKD_ D_ADREG
{A, D} input to AD register CLK
1.29/ 1.48/ 1.76/ 2.29/
–0.02 –0.02 –0.02 –0.27
{
}
Setup and Hold Times of Data/Control Pins to the Output Register Clock
{A, B} input to P register CLK using
multiplier
4.02/
4.60/
5.48/
6.95/
ns
ns
ns
ns
ns
T
T
/
A, B
A, B
DSPDCK_{
DSPCKD_{
}_PREG_MULT
} _PREG_MULT
–0.28 –0.28 –0.28 –0.48
D input to P register CLK using
multiplier
3.93/ 4.50/ 5.35/ 6.73/
–0.73 –0.73 –0.73 –1.68
T
T
/
DSPDCK_D_PREG_MULT
DSPCKD_D_PREG_MULT
A or B input to P register CLK not using 1.73/
multiplier
1.98/ 2.35/ 2.80/
T
T
/
A, B
A, B
DSPDCK_{
DSPCKD_{
} _PREG
} _PREG
–0.28 –0.28 –0.28 –0.48
C input to P register CLK not using
multiplier
1.54/ 1.76/ 2.10/ 2.54/
T
T
/
DSPDCK_C_PREG
DSPCKD_C_PREG
–0.26 –0.26 –0.26 –0.45
1.32/ 1.51/ 1.80/ 2.13/
TDSPDCK_PCIN_PREG
TDSPCKD_PCIN_PREG
/
PCIN input to P register CLK
–0.15 –0.15 –0.15 –0.23
Setup and Hold Times of the CE Pins
{CEA; CEB} input to {A; B} register CLK 0.35/
0.06
0.42/
0.08
0.52/
0.11
0.64/
0.11
ns
ns
ns
ns
ns
T
T
/
DSPDCK_{CEA;CEB}_{AREG;BREG}
DSPCKD_{CEA;CEB}_{AREG;BREG}
CEC input to C register CLK
CED input to D register CLK
CEM input to M register CLK
CEP input to P register CLK
0.28/
0.10
0.34/
0.11
0.42/
0.13
0.49/
0.16
T
T
T
T
/ T
DSPDCK_CEC_CREG DSPCKD_CEC_CREG
0.36/
0.43/
0.52/
0.68/
0.14
/ T
DSPDCK_CED_DREG DSPCKD_CED_DREG
–0.03 –0.03 –0.03
0.17/
0.18
0.21/
0.20
0.27/
0.23
0.31/
0.29
/ T
DSPDCK_CEM_MREG DSPCKD_CEM_MREG
0.36/
0.01
0.43/
0.01
0.53/
0.01
0.63/
0.00
/ T
DSPDCK_CEP_PREG DSPCKD_CEP_PREG
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
Speed Grade
Table 40: DSP48E1 Switching Characteristics (Cont’d)
Symbol
Description
1.0V
0.9V
-2L
Units
-3
-2/-2L
-1
Setup and Hold Times of the RST Pins
{RSTA, RSTB} input to {A, B} register
CLK
0.41/
0.11
0.46/
0.13
0.55/
0.15
0.63/
0.40
ns
ns
ns
ns
ns
T
T
/
DSPDCK_{RSTA; RSTB}_{AREG; BREG}
DSPCKD_{RSTA; RSTB}_{AREG; BREG}
RSTC input to C register CLK
RSTD input to D register CLK
RSTM input to M register CLK
RSTP input to P register CLK
0.07/
0.10
0.08/
0.11
0.09/
0.12
0.13/
0.11
T
T
T
T
/ T
DSPDCK_RSTC_CREG DSPCKD_RSTC_CREG
0.44/
0.07
0.50/
0.08
0.59/
0.09
0.67/
0.08
/ T
DSPDCK_RSTD_DREG DSPCKD_RSTD_DREG
0.21/
0.22
0.23/
0.24
0.27/
0.28
0.28/
0.35
/ T
DSPDCK_RSTM_MREG DSPCKD_RSTM_MREG
0.27/
0.01
0.30/
0.01
0.35/
0.01
0.43/
0.00
/ T
DSPDCK_RSTP_PREG DSPCKD_RSTP_PREG
Combinatorial Delays from Input Pins to Output Pins
TDSPDO_A_CARRYOUT_MULT
A input to CARRYOUT output using
multiplier
3.79
4.35
5.18
6.61
ns
TDSPDO_D_P_MULT
TDSPDO_B_P
D input to P output using multiplier
B input to P output not using multiplier
C input to P output
3.72
1.53
1.33
4.26
1.75
1.53
5.07
2.08
1.82
6.41
2.48
2.22
ns
ns
ns
TDSPDO_C_P
Combinatorial Delays from Input Pins to Cascading Output Pins
TDSPDO_{A; B}_{ACOUT; BCOUT}
{A, B} input to {ACOUT, BCOUT} output 0.55
0.63
4.65
0.74
5.54
0.87
7.03
ns
ns
TDSPDO_{A, B}_CARRYCASCOUT_MULT
{A, B} input to CARRYCASCOUT
output using multiplier
4.06
3.97
1.77
1.58
TDSPDO_D_CARRYCASCOUT_MULT
TDSPDO_{A, B}_CARRYCASCOUT
TDSPDO_C_CARRYCASCOUT
D input to CARRYCASCOUT output
using multiplier
4.54
2.03
1.81
5.40
2.41
2.15
6.81
2.88
2.62
ns
ns
ns
{A, B} input to CARRYCASCOUT
output not using multiplier
C input to CARRYCASCOUT output
Combinatorial Delays from Cascading Input Pins to All Output Pins
TDSPDO_ACIN_P_MULT ACIN input to P output using multiplier
TDSPDO_ACIN_P
3.65
1.37
4.19
1.57
5.00
1.88
6.40
2.44
ns
ns
ACIN input to P output not using
multiplier
TDSPDO_ACIN_ACOUT
ACIN input to ACOUT output
0.38
3.90
0.44
4.47
0.53
5.33
0.63
6.79
ns
ns
TDSPDO_ACIN_CARRYCASCOUT_MULT
ACIN input to CARRYCASCOUT output
using multiplier
TDSPDO_ACIN_CARRYCASCOUT
ACIN input to CARRYCASCOUT output
not using multiplier
1.61
1.11
1.85
2.21
2.84
ns
TDSPDO_PCIN_P
PCIN input to P output
1.28
1.56
1.52
1.85
1.82
2.21
ns
ns
TDSPDO_PCIN_CARRYCASCOUT
PCIN input to CARRYCASCOUT output 1.36
Clock to Outs from Output Register Clock to Output Pins
TDSPCKO_P_PREG
CLK PREG to P output
0.33
0.52
0.37
0.59
0.44
0.69
0.54
0.84
ns
ns
TDSPCKO_CARRYCASCOUT_PREG
CLK PREG to CARRYCASCOUT
output
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
Speed Grade
Table 40: DSP48E1 Switching Characteristics (Cont’d)
Symbol
Description
1.0V
0.9V
-2L
Units
-3
-2/-2L
-1
Clock to Outs from Pipeline Register Clock to Output Pins
TDSPCKO_P_MREG
CLK MREG to P output
1.68
1.92
1.93
2.21
2.31
2.64
2.73
3.12
ns
ns
TDSPCKO_CARRYCASCOUT_MREG
CLK MREG to CARRYCASCOUT
output
TDSPCKO_P_ADREG_MULT
CLK ADREG to P output using
multiplier
2.72
2.96
3.10
3.38
3.69
4.02
4.60
4.99
ns
ns
TDSPCKO_CARRYCASCOUT_ADREG_MULT
CLK ADREG to CARRYCASCOUT
output using multiplier
Clock to Outs from Input Register Clock to Output Pins
TDSPCKO_P_AREG_MULT CLK AREG to P output using multiplier
TDSPCKO_P_BREG
3.94
1.64
4.51
1.87
5.37
2.22
6.84
2.65
ns
ns
CLK BREG to P output not using
multiplier
TDSPCKO_P_CREG
CLK CREG to P output not using
multiplier
1.69
3.91
1.93
4.48
2.30
5.32
2.81
6.77
ns
ns
TDSPCKO_P_DREG_MULT
CLK DREG to P output using multiplier
Clock to Outs from Input Register Clock to Cascading Output Pins
TDSPCKO_{ACOUT; BCOUT}_{AREG; BREG}
CLK (ACOUT, BCOUT) to {A,B} register
output
0.64
4.19
0.73
4.79
0.87
5.70
1.02
7.24
ns
ns
TDSPCKO_CARRYCASCOUT_{AREG, BREG}_MULT
CLK (AREG, BREG) to
CARRYCASCOUT output using
multiplier
TDSPCKO_CARRYCASCOUT_ BREG
TDSPCKO_CARRYCASCOUT_ DREG_MULT
TDSPCKO_CARRYCASCOUT_ CREG
CLK BREG to CARRYCASCOUT
output not using multiplier
1.88
4.16
1.94
2.15
4.76
2.21
2.55
5.65
2.63
3.04
7.17
3.20
ns
ns
ns
CLK DREG to CARRYCASCOUT
output using multiplier
CLK CREG to CARRYCASCOUT
output
Maximum Frequency
FMAX
With all registers used
628
531
349
317
550
465
305
277
464
392
257
233
363
309
210
191
MHz
MHz
MHz
MHz
FMAX_PATDET
With pattern detector
FMAX_MULT_NOMREG
FMAX_MULT_NOMREG_PATDET
Two register multiply without MREG
Two register multiply without MREG
with pattern detect
FMAX_PREADD_MULT_NOADREG
FMAX_PREADD_MULT_NOADREG_PATDET
FMAX_NOPIPELINEREG
Without ADREG
397
397
260
346
346
227
290
290
190
223
223
150
MHz
MHz
MHz
Without ADREG with pattern detect
Without pipeline registers (MREG,
ADREG)
FMAX_NOPIPELINEREG_PATDET
Without pipeline registers (MREG,
ADREG) with pattern detect
241
211
177
140
MHz
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
Configuration Switching Characteristics
Table 41: Configuration Switching Characteristics
Speed Grade
Symbol
Description
1.0V
0.9V
-2L
Units
-3
-2/-2L
-1
Power-up Timing Characteristics
(1)
TPL
Program latency
5
5
5
5
ms, Max
(1)
TPOR
Power-on reset (50ms ramp rate time)
Power-on reset (1ms ramp rate time)
Program pulse width
10/50
10/35
250
10/50
10/35
250
10/50
10/35
250
10/50 ms, Min/Max
10/35 ms, Min/Max
TPROGRAM
CCLK Output (Master Mode)
250
ns, Min
TICCK
Master CCLK output delay
150
40/60
40/60
100
50
150
40/60
40/60
100
50
150
40/60
40/60
100
50
150
ns, Min
TMCCKL
TMCCKH
FMCCK
Master CCLK clock Low time duty cycle
Master CCLK clock High time duty cycle
Master CCLK frequency
40/60 %, Min/Max
40/60 %, Min/Max
70
50
3
MHz, Max
MHz, Max
MHz, Typ
%, Max
Master CCLK frequency for AES encrypted x16
Master CCLK frequency at start of configuration
FMCCK_START
FMCCKTOL
3
3
3
Frequency tolerance, master mode with respect to
nominal CCLK
50
50
50
50
CCLK Input (Slave Modes)
TSCCKL
TSCCKH
FSCCK
Slave CCLK clock minimum Low time
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
70
ns, Min
ns, Min
Slave CCLK clock minimum High time
Slave CCLK frequency
100
100
100
MHz, Max
EMCCLK Input (Master Mode)
TEMCCKL
TEMCCKH
FEMCCK
External master CCLK Low time
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
70
ns, Min
ns, Min
External master CCLK High time
External master CCLK frequency
100
100
100
MHz, Max
Master/Slave Serial Mode Programming Switching
TDCCK/TCCKD
TCCO
DIN Setup/Hold
4.0/0.0 4.0/0.0 4.0/0.0 5.0/0.0
8.0 8.0 8.0 9.0
ns, Min
ns, Max
DOUT clock to out
SelectMAP Mode Programming Switching
TSMDCCK/TSMCCKD D[31:00] Setup/Hold
SMCSCCK/TSMCCKCS CSI_B Setup/Hold
4.0/0.0 4.0/0.0 4.0/0.0 4.5/0.0
4.0/0.0 4.0/0.0 4.0/0.0 5.0/0.0
10.0/0.0 10.0/0.0 10.0/0.0 12.0/0.0
ns, Min
ns, Min
T
TSMWCCK/TSMCCKW
TSMCKCSO
TSMCO
RDWR_B Setup/Hold
ns, Min
CSO_B clock to out (330 pull-up resistor required)
D[31:00] clock to out in readback
Readback frequency
7.0
8.0
7.0
8.0
7.0
8.0
100
8.0
10.0
70
ns, Max
ns, Max
MHz, Max
FRBCCK
100
100
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
Table 41: Configuration Switching Characteristics (Cont’d)
Speed Grade
1.0V
Symbol
Description
0.9V
-2L
Units
-3
-2/-2L
-1
Boundary-Scan Port Timing Specifications
TTAPTCK/TTCKTAP
TTCKTDO
TMS and TDI Setup/Hold
TCK falling edge to TDO output
TCK frequency
3.0/2.0 3.0/2.0 3.0/2.0 3.0/2.0
ns, Min
ns, Max
7.0
66
7.0
66
7.0
66
8.5
50
FTCK
MHz, Max
BPI Master Flash Mode Programming Switching
(2)
TBPICCO
A[28:00], RS[1:0], FCS_B, FOE_B, FWE_B, ADV_B
clock to out
8.5
8.5
8.5
10.0
ns, Max
ns, Min
TBPIDCC/TBPICCD
D[15:00] Setup/Hold
4.0/0.0 4.0/0.0 4.0/0.0 4.5/0.0
SPI Master Flash Mode Programming Switching
TSPIDCC/TSPICCD
TSPICCM
D[03:00] Setup/Hold
MOSI clock to out
FCS_B clock to out
3.0/0.0 3.0/0.0 3.0/0.0 3.0/0.0
ns, Min
ns, Max
ns, Max
8.0
8.0
8.0
8.0
8.0
8.0
9.0
9.0
TSPICCFC
Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK
TMMCMDCK_DADDR
TMMCMCKD_DADDR
/
DADDR Setup/Hold
1.25/
0.15
1.40/
0.15
1.63/
0.15
1.43/
0.00
ns, Min
ns, Min
ns, Min
ns, Min
TMMCMDCK_DI
TMMCMCKD_DI
/
DI Setup/Hold
1.25/
0.15
1.40/
0.15
1.63/
0.15
1.43/
0.00
TMMCMDCK_DEN
/
DEN Setup/Hold
DWE Setup/Hold
1.76/
0.00
1.97/
0.00
2.29/
0.00
2.40/
0.00
TMMCMCKD_DEN
TMMCMDCK_DWE
/
1.25/
0.15
1.40/
0.15
1.63/
0.15
1.43/
0.00
TMMCMCKD_DWE
TMMCMCKO_DO
CLK to out of DO(3)
CLK to out of DRDY
DCLK frequency
0.55
0.65
200
0.62
0.72
200
0.74
0.99
200
0.70
0.70
200
ns, Max
ns, Max
TMMCMCKO_DRDY
FDCK
MHz, Max
Notes:
1. To support longer delays in configuration, use the design solutions described in UG470: 7 Series FPGA Configuration User Guide.
2. Only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the I/O.
3. DO will hold until next DRP operation.
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
Clock Buffers and Networks
Table 42: Global Clock Switching Characteristics (Including BUFGCTRL)
Speed Grade
1.0V
Symbol
Description
0.9V
-2L
Units
-3
-2/-2L
-1
(1)
TBCCCK_CE/TBCCKC_CE
CE pins Setup/Hold
0.14/
0.24
0.16/
0.27
0.20/
0.32
0.31/
0.17
ns
ns
ns
(1)
T
BCCCK_S/TBCCKC_S
S pins Setup/Hold
0.14/
0.24
0.16/
0.27
0.20/
0.32
0.31/
0.17
(2)
TBCCKO_O
BUFGCTRL delay from I0/I1 to O
0.10
0.11
0.14
0.14
Maximum Frequency
FMAX_BUFG
Global clock tree (BUFG)
628
550
464
363
MHz
Notes:
1.
T
and T
must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These
BCCCK_CE
BCCKC_CE
parameters do not apply to the BUFGMUX primitive that assures glitch-free operation. The other global clock setup and hold times are
optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between
clocks.
2.
T
(BUFG delay from I0 to O) values are the same as T
values.
BCCKO_O
BGCKO_O
Table 43: Input/Output Clock Switching Characteristics (BUFIO)
Speed Grade
1.0V
Symbol
Description
Clock to out delay from I to O
I/O clock tree (BUFIO)
0.9V
-2L
Units
ns
-3
-2/-2L
-1
TBIOCKO_O
1.35
1.52
1.79
1.50
Maximum Frequency
FMAX_BUFIO
680
680
600
600
MHz
Table 44: Regional Clock Buffer Switching Characteristics (BUFR)
Speed Grade
1.0V
Symbol
Description
0.9V
-2L
Units
-3
-2/-2L
-1
Clock to out delay from
I to O
0.91
1.03
1.21
1.08
ns
ns
ns
TBRCKO_O
Clock to out delay from I to O with Divide Bypass
attribute set
0.46
0.79
0.52
0.90
0.62
1.05
0.57
0.96
TBRCKO_O_BYP
TBRDO_O
Propagation delay from CLR to O
Maximum Frequency
(1)
FMAX_BUFR
Regional clock tree (BUFR)
420
375
315
315
MHz
Notes:
1. The maximum input frequency to the BUFR is the BUFIO F
frequency.
MAX
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
Table 45: Horizontal Clock Buffer Switching Characteristics (BUFH)
Speed Grade
1.0V
Symbol
Description
0.9V
-2L
Units
-3
-2/-2L
-1
TBHCKO_O
BHCCK_CE/TBHCKC_CE
BUFH delay from I to O
0.11
0.12
0.15
0.16
ns
ns
0.21/
0.14
0.25/
0.16
0.28/
0.22
0.35/
0.08
T
CE pin Setup and Hold
Maximum Frequency
FMAX_BUFH
Horizontal clock buffer (BUFH)
628
550
464
394
MHz
MMCM Switching Characteristics
Table 46: MMCM Specification
Speed Grade
1.0V
Symbol
Description
0.9V
-2L
800
10
Units
-3
800
10
-2/-2L
800
-1
800
10
MMCM_FINMAX
MMCM_FINMIN
MMCM_FINJITTER
MMCM_FINDUTY
Maximum Input Clock Frequency
MHz
MHz
Minimum Input Clock Frequency
10
Maximum Input Clock Period Jitter
Allowable Input Duty Cycle: 10—49 MHz
Allowable Input Duty Cycle: 50—199 MHz
Allowable Input Duty Cycle: 200—399 MHz
Allowable Input Duty Cycle: 400—499 MHz
Allowable Input Duty Cycle: >500 MHz
Minimum Dynamic Phase Shift Clock Frequency
Maximum Dynamic Phase Shift Clock Frequency
Minimum MMCM VCO Frequency
< 20% of clock input period or 1 ns Max
25
30
25
30
25
30
25
30
%
%
35
35
35
35
%
40
40
40
40
%
45
45
45
45
%
MMCM_FMIN_PSCLK
MMCM_FMAX_PSCLK
MMCM_FVCOMIN
0.01
550
600
1600
1.00
4.00
0.12
0.01
500
600
1440
1.00
4.00
0.12
0.01
450
600
1200
1.00
4.00
0.12
Note 1
0.20
100
800
4.69
0.01
450
600
1200
1.00
4.00
0.12
MHz
MHz
MHz
MHz
MHz
MHz
ns
MMCM_FVCOMAX
MMCM_FBANDWIDTH
Maximum MMCM VCO Frequency
Low MMCM Bandwidth at Typical(1)
High MMCM Bandwidth at Typical(1)
Static Phase Offset of the MMCM Outputs(2)
MMCM Output Jitter(3)
MMCM_TSTATPHAOFFSET
MMCM_TOUTJITTER
MMCM_TOUTDUTY
MMCM_TLOCKMAX
MMCM_FOUTMAX
MMCM Output Clock Duty Cycle Precision(4)
MMCM Maximum Lock Time
0.20
100
800
4.69
0.20
100
800
4.69
0.25
100
800
4.69
ns
µs
MMCM Maximum Output Frequency
MMCM Minimum Output Frequency(5)(6)
External Clock Feedback Variation
Minimum Reset Pulse Width
MHz
MHz
MMCM_FOUTMIN
MMCM_TEXTFDVAR
MMCM_RSTMINPULSE
MMCM_FPFDMAX
< 20% of clock input period or 1 ns Max
5.00
550
5.00
500
5.00
450
5.00
450
ns
Maximum Frequency at the Phase Frequency
Detector with Bandwidth Set to High or Optimized
MHz
Maximum Frequency at the Phase Frequency
Detector with Bandwidth Set to Low
300
10
300
10
300
10
300
10
MHz
MHz
MMCM_FPFDMIN
MMCM_TFBDELAY
Minimum Frequency at the Phase Frequency
Detector
Maximum Delay in the Feedback Path
3 ns Max or one CLKIN cycle
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
Speed Grade
Table 46: MMCM Specification (Cont’d)
Symbol
Description
1.0V
0.9V
-2L
Units
-3
-2/-2L
-1
MMCM Switching Characteristics Setup and Hold
TMMCMDCK_PSEN
TMMCMCKD_PSEN
/
Setup and Hold of Phase Shift Enable
1.04/
0.00
1.04/
0.00
1.04/
0.00
1.04/
0.00
ns
ns
ns
TMMCMDCK_PSINCDEC
TMMCMCKD_PSINCDEC
/
Setup and Hold of Phase Shift
Increment/Decrement
1.04/
0.00
1.04/
0.00
1.04/
0.00
1.04/
0.00
TMMCMCKO_PSDONE
Phase Shift Clock-to-Out of PSDONE
0.59
0.68
0.81
0.78
Notes:
1. The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.
2. The static offset is measured between any MMCM outputs with identical phase.
3. Values for this parameter are available in the Clocking Wizard.
See http://www.xilinx.com/products/intellectual-property/clocking_wizard.htm.
4. Includes global clock buffer.
5. Calculated as F
/128 assuming output duty cycle is 50%.
VCO
6. When CLKOUT4_CASCADE = TRUE, MMCM_F
is 0.036 MHz.
OUTMIN
PLL Switching Characteristics
Table 47: PLL Specification
Speed Grade
1.0V
Symbol
Description
0.9V
-2L
800
19
Units
-3
800
19
-2/-2L
800
-1
800
19
PLL_FINMAX
Maximum Input Clock Frequency
Minimum Input Clock Frequency
Maximum Input Clock Period Jitter
Allowable Input Duty Cycle: 19—49 MHz
Allowable Input Duty Cycle: 50—199 MHz
Allowable Input Duty Cycle: 200—399 MHz
Allowable Input Duty Cycle: 400—499 MHz
Allowable Input Duty Cycle: >500 MHz
Minimum PLL VCO Frequency
MHz
MHz
PLL_FINMIN
19
PLL_FINJITTER
PLL_FINDUTY
< 20% of clock input period or 1 ns Max
25
30
25
30
25
30
25
30
%
%
35
35
35
35
%
40
40
40
40
%
45
45
45
45
%
PLL_FVCOMIN
800
2133
1.00
4.00
0.12
800
1866
1.00
4.00
0.12
800
1600
1.00
4.00
0.12
Note 1
0.20
100
800
6.25
800
1600
1.00
4.00
0.12
MHz
MHz
MHz
MHz
ns
PLL_FVCOMAX
PLL_FBANDWIDTH
Maximum PLL VCO Frequency
Low PLL Bandwidth at Typical(1)
High PLL Bandwidth at Typical(1)
Static Phase Offset of the PLL Outputs(2)
PLL Output Jitter(3)
PLL_TSTATPHAOFFSET
PLL_TOUTJITTER
PLL_TOUTDUTY
PLL_TLOCKMAX
PLL_FOUTMAX
PLL Output Clock Duty Cycle Precision(4)
PLL Maximum Lock Time
0.20
100
800
6.25
0.20
100
800
6.25
0.25
100
800
6.25
ns
µs
PLL Maximum Output Frequency
PLL Minimum Output Frequency(5)
External Clock Feedback Variation
Minimum Reset Pulse Width
MHz
MHz
PLL_FOUTMIN
PLL_TEXTFDVAR
PLL_RSTMINPULSE
< 20% of clock input period or 1 ns Max
5.00 5.00 5.00 5.00
ns
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
Speed Grade
Table 47: PLL Specification (Cont’d)
Symbol
Description
1.0V
-2/-2L
500
0.9V
-2L
Units
-3
-1
PLL_FPFDMAX
Maximum Frequency at the Phase Frequency
Detector with Bandwidth Set to High or Optimized
550
450
450
MHz
MHz
MHz
Maximum Frequency at the Phase Frequency
Detector with Bandwidth Set to Low
300
19
300
19
300
19
300
19
PLL_FPFDMIN
PLL_TFBDELAY
Minimum Frequency at the Phase Frequency
Detector
Maximum Delay in the Feedback Path
3 ns Max or one CLKIN cycle
PLL Switching Characteristics Setup and Hold
TPLLCCK_DEN
/
Setup and Hold of D enable
Setup and Hold of D address
Setup and Hold of D input
1.76/
0.00
1.97/
0.00
2.29/
0.00
2.40/
0.00
ns
ns
ns
ns
TPLLCKC_DEN
TPLLCCK_DADDR
TPLLCKC_DADDR
/
1.25/
0.15
1.40/
0.15
1.63/
0.15
1.43/
0.00
TPLLCCK_DI
/
1.25/
0.15
1.40/
0.15
1.63/
0.15
1.43/
0.00
TPLLCKC_DI
TPLLCCK_DWE
TPLLCKC_DWE
/
Setup and Hold of D write enable
1.25/
0.15
1.40/
0.15
1.63/
0.15
1.43/
0.00
Notes:
1. The PLL does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.
2. The static offset is measured between any PLL outputs with identical phase.
3. Values for this parameter are available in the Clocking Wizard.
See http://www.xilinx.com/products/intellectual-property/clocking_wizard.htm.
4. Includes global clock buffer.
5. Calculated as F
/128 assuming output duty cycle is 50%.
VCO
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
Artix-7 Device Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. Values are expressed in nanoseconds unless otherwise noted.
Table 48: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Near Clock Region)
Speed Grade
Symbol
Description
Device
1.0V
0.9V
-2L
Units
-3
-2/-2L
-1
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM/PLL.
TICKOF
Clock-capable clock input and OUTFF
without MMCM/PLL (near clock region)
XC7A100T
XC7A200T
XC7A350T
6.68
7.24
6.46
7.55
8.04
7.31
8.89
9.51
8.62
ns
ns
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
Table 49: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Far Clock Region)
Speed Grade
Symbol
Description
Device
1.0V
0.9V
-2L
Units
-3
-2/-2L
-1
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM/PLL.
TICKOFFAR
Clock-capable clock input and OUTFF
without MMCM/PLL (far clock region)
XC7A100T
XC7A200T
XC7A350T
7.02
7.93
7.15
7.92
8.83
8.07
9.32
10.44
9.49
ns
ns
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
Table 50: Clock-Capable Clock Input to Output Delay With MMCM
Speed Grade
Symbol
Description
Device
1.0V
0.9V
-2L
Units
-3
-2/-2L
-1
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with MMCM.
TICKOFMMCMCC
Clock-capable clock input and OUTFF
with MMCM
XC7A100T
XC7A200T
XC7A350T
2.80
3.09
2.89
3.11
3.35
3.21
3.48
3.58
3.59
ns
ns
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. MMCM output jitter is already included in the timing calculation.
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
Table 51: Clock-Capable Clock Input to Output Delay With PLL
Speed Grade
1.0V
Symbol
Description
Device
0.9V
-2L
Units
-3
-2/-2L
-1
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with PLL.
TICKOFPLLCC
Clock-capable clock input and OUTFF
with PLL
XC7A100T
XC7A200T
XC7A350T
2.36
2.61
2.45
2.71
2.83
2.81
3.12
3.49
3.24
ns
ns
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. PLL output jitter is already included in the timing calculation.
Artix-7 Device Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. Values are expressed in nanoseconds unless otherwise noted.
Table 52: Global Clock Input Setup and Hold Without MMCM/PLL with ZHOLD_DELAY on HR I/O Banks
Speed Grade
Symbol
Description
Device
1.0V
0.9V
-2L
Units
-3
Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.(1)
-2/-2L
-1
TPSFD/ TPHFD
Full Delay (Legacy Delay or Default
Delay)
XC7A100T
XC7A200T
XC7A350T
3.66/
–0.29
4.01/
–0.29
4.50/
–0.29
ns
ns
ns
Global Clock Input and IFF(2) without
MMCM/PLL with ZHOLD_DELAY on
HR I/O Banks
4.05/
–0.21
4.59/
–0.21
5.11/
–0.08
5.16/
5.68/
6.43/
–0.87
–0.87
–0.87
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage.
2. IFF = Input Flip-Flop or Latch
3. A Zero "0" Hold Time listing indicates no hold time or a negative hold time.
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
Table 53: Clock-Capable Clock Input Setup and Hold With MMCM
Speed Grade
1.0V
Symbol
Description
Device
0.9V
-2L
Units
-3
Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.(1)
-2/-2L
-1
TPSMMCMCC
TPHMMCMCC
/
No Delay clock-capable clock input and XC7A100T
IFF(2) with MMCM
2.19/
–0.06
2.48/
–0.06
2.97/
–0.06
ns
ns
ns
XC7A200T
2.33/
0.17
2.70/
0.17
3.15/
0.17
XC7A350T
2.25/
2.54/
3.04/
–0.02
–0.02
–0.02
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage.
2. IFF = Input Flip-Flop or Latch
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
Table 54: Clock-Capable Clock Input Setup and Hold With PLL
Speed Grade
Symbol
Description
Device
1.0V
0.9V
-2L
Units
-3
-2/-2L
-1
Input Setup and Hold Time Relative to Clock-Capable Clock Input Signal for SSTL15 Standard.(1)
TPSPLLCC
TPHPLLCC
/
No Delay clock-capable clock input and XC7A100T
IFF(2) with PLL
2.56/
–0.34
2.88/
–0.34
3.35/
–0.34
ns
ns
ns
XC7A200T
2.71/
–0.17
3.14/
–0.17
3.53/
–0.17
XC7A350T
2.62/
2.94/
3.42/
–0.29
–0.29
–0.29
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage.
2. IFF = Input Flip-Flop or Latch
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
Clock Switching Characteristics
The parameters in this section provide the necessary values for calculating timing budgets for Artix-7 FPGA clock transmitter
and receiver data-valid windows.
Table 55: Duty Cycle Distortion and Clock-Tree Skew
Speed Grade
Symbol
Description
Device
1.0V
-2/-2L
0.20
0.9V
-2L
Units
-3
-1
TDCD_CLK
Global Clock Tree Duty Cycle
Distortion(1)
All
0.20
0.20
ns
TCKSKEW
Global Clock Tree Skew(2)
XC7A100T
XC7A200T
XC7A350T
All
0.20
0.41
0.36
0.10
0.04
0.21
0.45
0.39
0.10
0.04
0.24
0.58
0.44
0.10
0.03
ns
ns
ns
ns
ns
TDCD_BUFIO
TBUFIOSKEW
I/O clock tree duty cycle distortion
I/O clock tree skew across one clock
region
All
TDCD_BUFR
Regional clock tree duty cycle distortion All
0.18
0.18
0.18
ns
Notes:
1. These parameters represent the worst-case duty cycle distortion observable at the I/O flip flops. For all I/O standards, IBIS can be used to
calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times.
2. The T
value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree
CKSKEW
skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor
and Timing Analyzer tools to evaluate clock skew specific to your application.
Table 56: Package Skew
Symbol
TPKGSKEW
Description
Package Skew(1)
Device
XC7A100T
Package
CSG324
FTG256
FGG484
FGG676
FBG484
FBG676
FFG1156
FBG484
FBG676
FFG1156
Value
Units
ps
ps
ps
ps
ps
XC7A200T
XC7A350T
ps
ps
ps
ps
ps
Notes:
1. These values represent the worst-case skew between any two SelectIO resources in the package: shortest flight time to longest flight time
from Pad to Ball (7.0 ps per mm).
2. Package trace length information is available for these device/package combinations. This information can be used to deskew the package.
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
Speed Grade
Table 57: Sample Window
Symbol
Description
1.0V
-2/-2L
0.67
0.9V
-2L
Units
-3
-1
TSAMP
Sampling Error at Receiver Pins(1)
0.61
0.36
0.72
0.48
ns
ns
TSAMP_BUFIO
Sampling Error at Receiver Pins using BUFIO(2)
0.42
Notes:
1. This parameter indicates the total sampling error of the Artix-7 FPGAs DDR input registers, measured across voltage, temperature, and
process. The characterization methodology uses the MMCM to capture the DDR input registers’ edges of operation. These measurements
include:
- CLK0 MMCM jitter
- MMCM accuracy (phase offset)
- MMCM phase shift resolution
These measurements do not include package or clock tree skew.
2. This parameter indicates the total sampling error of the Artix-7 FPGAs DDR input registers, measured across voltage, temperature, and
process. The characterization methodology uses the BUFIO clock network and IDELAY to capture the DDR input registers’ edges of
operation. These measurements do not include package or clock tree skew.
Table 58: Pin-to-Pin Setup/Hold and Clock-to-Out
Speed Grade
Symbol
Description
1.0V
0.9V
-2L
Units
-3
Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO
-2/-2L
-1
T
PSCS/TPHCS
Setup/Hold of I/O clock
–0.28/
2.03
–0.28/
2.26
–0.28/
2.60
ns
ns
Pin-to-Pin Clock-to-Out Using BUFIO
TICKOFCS
Clock-to-Out of I/O clock
6.88
7.80
9.19
Revision History
The following table shows the revision history for this document:
Date
Version
1.0
Description
09/26/11
11/07/11
Initial Xilinx release.
1.1
Revised the VOCM specification in Table 10. Updated the Switching Characteristics based upon the ISE
13.3 software v1.02 speed specification throughout document including Table 26 and Table 27. Added
MMCM_TFBDELAY while adding MMCM_ to the symbol names of a few specifications in Table 46 and
PLL to the symbol names in Table 47. In Table 48 through Table 54, updated the pin-to-pin description
with the SSTL15 standard. Updated units in Table 57.
02/13/12
1.2
Updated the Artix-7 family of devices listed throughout the entire data sheet. Updated the Switching
Characteristics based upon the ISE 13.4 software v1.03 for the -3, -2, and -1 speed grades and v1.00
for the -2L speed grade.
Updated summary description on page 1. In Table 2, revised VCCO for the 3.3V HR I/O banks and
updated Tj. Updated the notes in Table 4. Added MGTAVCC and MGTAVTT power supply ramp times
to Table 6. Rearranged Table 7, added Mobile_DDR, HSTL_I_18, HSTL_II_18, HSUL_12,
SSTL135_R, SSTL15_R, and SSTL12 and removed DIFF_SSTL135, DIFF_SSTL18_I,
DIFF_SSTL18_II, DIFF_HSTL_I, and DIFF_HSTL_II. Added Table 8 and Table 9. Revised the
specifications in Table 10. Revised VIN in Table 16. Updated the eFUSE Programming Conditions
section and removed the endurance table. Added the I/O FIFO Switching Characteristics table.
Revised FTXIN and FRXIN in Table 21. Revised ICCADC and updated Note 1 in Table 23. Revised DDR
LVDS transmitter data width in Table 24. Removed notes from Table 36 as they are no longer
applicable. Updated specifications in Table 41. Updated Note 1 in Table 55.
DS181 (v1.2) February 13, 2012
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
Notice of Disclaimer
The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the
maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL
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XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-
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