XC95144XV-5TQG144I [XILINX]
Flash PLD, 4ns, PQFP144, PLASTIC, TQFP-144;
| 型号： | XC95144XV-5TQG144I |
| 厂家： | 
XILINX, INC |
| 描述： | Flash PLD, 4ns, PQFP144, PLASTIC, TQFP-144 |
| 文件： | 总9页 (文件大小：80K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0
R
XC95144XV High-Performance
CPLD
0
1
DS051 (v2.0) January 25, 2001
Advance Product Specification
Features
Power Estimation
•
144 macrocells with 3,200 usable gates
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XV device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
•
Available in small footprint packages
-
-
-
100-pin TQFP (81 user I/O pins)
144-pin TQFP (117 user I/O pins)
144-pin CSP (117 user I/O pins)
•
•
Optimized for high-performance 2.5V systems
-
-
Low power operation
Multi-voltage operation
For a general estimate of I , the following equation may be
CC
used:
Advanced system features
I
(mA) = MC (0.5) + MC (0.3) + MC(0.0045 mA/MHz) f
HP LP
CC
-
-
-
In-system programmable
Two separate output banks
Where:
MC = Macrocells in high-performance (default) mode
Superior pin-locking and routability with
FastCONNECT II™ switch matrix
Extra wide 54-input Function Blocks
Up to 90 product-terms per macrocell with
individual product-term allocation
HP
MC = Macrocells in low-power mode
LP
-
-
MC = Total number of macrocells used
f = Clock frequency (MHz)
-
Local clock inversion with three global and one
product-term clocks
Individual output enable per output pin
Input hysteresis on all user and boundary-scan pin
inputs
This calculation is based on typical operating conditions
using a pattern of 16-bit up/down counters in each Function
-
-
Block with no output loading. The actual I
value varies
CC
with the design application and should be verified during
normal system operation.
-
-
Bus-hold ciruitry on all user pin inputs
Full IEEE Standard 1149.1 boundary-scan (JTAG)
Figure 1 shows the above estimation in a graphical form.
•
•
•
•
Fast concurrent programming
200
200 MHz
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
150
-
Endurance exceeding 10,000 program/erase
cycles
120 MHz
100
-
-
20 year data retention
ESD protection exceeding 2,000V
50
Description
The XC95144XV is a 2.5V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
cations and computing systems. It is comprised of eight
54V18 Function Blocks, providing 3,200 usable gates with
propagation delays of 4 ns.
0
80
120
200
40
160
Clock Frequency (MHz)
DS051_01_012501
Figure 1: Typical I vs. Frequency for XC95144XV
CC
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS051 (v2.0) January 25, 2001
www.xilinx.com
1
Advance Product Specification
1-800-255-7778
R
XC95144XV High-Performance CPLD
3
JTAG
In-System Programming Controller
1
JTAG Port
Controller
54
Function
18
18
18
18
Block 1
I/O
Macrocells
1 to 18
I/O
I/O
I/O
54
54
54
Function
Block 2
Macrocells
1 to 18
I/O
Blocks
I/O
I/O
Function
Block 3
Macrocells
1 to 18
I/O
I/O
3
I/O/GCK
I/O/GSR
I/O/GTS
Function
Block 4
1
4
Macrocells
1 to 18
54
Function
Block 8
18
Macrocells
1 to 18
DS051_02_041000
Figure 2: XC95144XV Architecture
Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.
2
www.xilinx.com
DS051 (v2.0) January 25, 2001
1-800-255-7778
Advance Product Specification
R
XC95144XV High-Performance CPLD
Absolute Maximum Ratings
Symbol
Description
Supply voltage relative to GND
Value
–0.5 to 2.7
–0.5 to 3.6
–0.5 to 3.6
–0.5 to 3.6
–65 to +150
+260
Units
V
V
V
V
V
CC
V
Supply voltage for output drivers
CCIO
(1)
V
Input voltage relative to GND
IN
(1)
V
Voltage applied to 3-state output
Storage temperature (ambient)
TS
o
T
T
C
STG
SOL
o
Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm)
Junction temperature
C
o
T
+150
C
J
Notes:
1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the
device pins may undershoot to –2.0V or overshoot to +3.6V, provided this over- or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Recommended Operation Conditions
Symbol
Parameter
Commercial T = 0 C to +70 C
Min
2.4
2.4
3.1
2.4
1.7
0
Max
2.6
2.6
3.5
2.6
1.9
0.8
3.6
Units
o
o
V
Supply voltage for internal logic
and input buffers
V
CCINT
A
o
o
Industrial T = –40 C to +85 C
A
V
Supply voltage for output drivers for 3.3V operation
Supply voltage for output drivers for 2.5V operation
Supply voltage for output drivers for 1.8V operation
Low-level input voltage
V
V
V
V
V
V
CCIO
V
IL
V
High-level input voltage
1.7
0
IH
V
Output voltage
V
CCIO
O
Quality and Reliability Characteristics
Symbol
Parameter
Min
20
Max
Units
T
Data retention
-
-
-
Years
Cycles
Volts
DR
N
Program/Erase cycles (endurance)
Electrostatic Discharge (ESD)
10,000
2,000
PE
V
ESD
DS051 (v2.0) January 25, 2001
www.xilinx.com
3
Advance Product Specification
1-800-255-7778
R
XC95144XV High-Performance CPLD
DC Characteristics (Over Recommended Operating Conditions)
Symbol
Parameter
Output high voltage for 3.3V outputs
Output high voltage for 2.5V outputs
Output high voltage for 1.8V outputs
Output low voltage for 3.3V outputs
Output low voltage for 2.5V outputs
Output low voltage for 1.8V outputs
Input leakage current
Test Conditions
Min
2.4
2.0
Max
-
Units
V
V
I
I
I
I
I
I
= –4.0 mA
= –1.0 mA
= –100 µA
= 8.0 mA
= 1.0 mA
= 100 µA
OH
OH
OH
OH
OL
OL
OL
-
V
90% V
-
V
CCIO
V
-
-
-
-
0.4
0.4
0.4
10
V
OL
V
V
I
V
V
V
= 2.6V
µA
IL
CC
CCIO
= 3.6V
= GND or 3.6V
IN
I
I/O high-Z leakage current
I/O capacitance
V
V
V
= 2.0V
-
-
10
10
µA
IH
CC
= 3.6V
CCIO
= GND or 3.6V
IN
C
V
= GND
pF
IN
IN
f = 1.0 MHz
I
Operating Supply Current
(low power mode, active)
V = GND, No load
f = 1.0 MHz
29
mA
CC
I
AC Characteristics
XC95144XV-4
XC95144XV-5
XC95144XV-7
Symbol
Parameter
Min
Max
4.0
-
Min
Max
5.0
-
Min
Max
7.5
-
Units
ns
T
T
I/O to output valid
-
3.1
0
-
3.7
0
-
4.8
0
PD
SU
I/O setup time before GCK
I/O hold time after GCK
GCK to output valid
ns
T
-
-
-
ns
H
T
-
2.0
250.0
-
2.5
222.2
-
4.5
125.0
ns
CO
f
Multiple FB internal operating
frequency
-
-
-
MHz
SYSTEM
T
I/O setup time before p-term clock
input
0.5
-
0.7
-
1.6
-
ns
PSU
T
I/O hold time after p-term clock input
P-term clock output valid
1.8
-
2.0
-
5.5
3.0
3.0
7.0
7.0
10.0
10.5
-
3.2
-
7.7
5.0
5.0
9.5
9.5
12.0
12.6
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PH
T
-
4.6
2.5
2.5
5.5
5.5
7.7
8.5
-
-
-
PCO
T
GTS to output valid
-
-
-
OE
OD
T
GTS to output disable
-
-
-
T
T
Product term OE to output enabled
Product term OE to output disabled
GSR to output valid
-
-
-
-
-
-
POE
POD
T
-
-
-
AO
T
P-term S/R to output valid
-
-
-
PAO
WLH
T
GCK pulse width (High or Low)
P-term clock pulse width (High or Low)
2.0
5.0
2.2
5.0
4.0
6.5
T
-
-
-
PLH
Advance Information
Notes:
1. Please contact Xilinx for up-to-date information on advance specifications.
4
www.xilinx.com
DS051 (v2.0) January 25, 2001
1-800-255-7778
Advance Product Specification
R
XC95144XV High-Performance CPLD
V
TEST
R
1
Output Type
V
V
R
R
C
L
CCIO
TEST
1
2
Device Output
3.3V
2.5V
1.8V
3.3V
2.5V
1.8V
320Ω
250Ω
10KΩ
360Ω
660Ω
14KΩ
35 pF
35 pF
35 pF
R
C
L
2
DS051_03_0601000
Figure 3: AC Load Circuit
Internal Timing Parameters
XC95144XV-4
XC95144XV-5
XC95144XV-7
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Units
Buffer Delays
T
T
T
T
T
T
Input buffer delay
GCK buffer delay
GSR buffer delay
GTS buffer delay
-
-
-
-
-
-
1.2
0.2
1.2
2.5
1.6
0
-
-
-
-
-
-
1.5
0.3
2.0
3.0
2.0
0
-
-
-
-
-
-
2.3
1.5
3.1
5.0
2.5
0
ns
ns
ns
ns
ns
ns
IN
GCK
GSR
GTS
OUT
EN
Output buffer delay
Output buffer enable/disable delay
Product Term Control Delays
T
T
T
Product term clock delay
Product term set/reset delay
Product term 3-state delay
-
-
-
1.6
0.8
4.3
-
-
-
1.8
1.0
5.5
-
-
-
2.4
1.4
7.2
ns
ns
ns
PTCK
PTSR
PTTS
Internal Register and Combinatorial Delays
T
T
T
T
T
T
Combinatorial logic propagation delay
Register setup time
-
1.3
1.0
1.3
1.0
-
0.4
-
1.5
1.2
1.5
1.2
-
0.5
-
2.6
2.2
2.6
2.2
-
1.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PDI
-
-
-
-
-
-
SUI
Register hold time
HI
Register clock enable setup time
Register clock enable hold time
Register clock to output valid time
Register async. S/R to output delay
Register async. S/R recover before clock
Internal logic delay
-
-
-
ECSU
ECHO
COI
-
-
-
0.2
4.9
0.2
6.0
0.5
6.4
T
-
-
-
AOI
T
4.0
-
5.0
-
7.5
-
RAI
T
T
0.8
3.8
1.0
5.0
1.4
6.4
LOGI
LOGILP
Internal low power logic delay
-
-
-
Feedback Delays
FastCONNECT II™ feedback delay
Time Adders
T
-
1.7
-
1.8
-
3.5
ns
F
T
T
T
Incremental product term allocator delay
Adjacent macrocell p-term allocator delay
Slew-rate limited delay
-
-
-
0.6
0.2
2.5
-
-
-
0.7
0.3
3.0
-
-
-
0.8
0.3
4.0
ns
ns
ns
PTA
PTA2
SLEW
Advance Information
Notes:
1. Please contact Xilinx for up-to-date information on advance specifications.
DS051 (v2.0) January 25, 2001
www.xilinx.com
5
Advance Product Specification
1-800-255-7778
R
XC95144XV High-Performance CPLD
XC95144XV I/O Pins
Function Macro-
BScan
TQ100 TQ144 CS144 Order Bank
Function Macro-
BScan
TQ100 TQ144 CS144 Order Bank
Block
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
cell
Block
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
cell
1
-
23
16
17
25
19
20
-
H3
F1
G2
J1
G3
G4
-
429
426
423
420
417
414
411
408
405
402
399
396
393
390
387
384
381
378
375
372
369
366
363
360
357
354
351
348
345
342
339
336
333
330
327
324
1
1
1
1
1
1
-
1
-
39
M3
321
318
315
312
309
306
303
300
297
294
291
288
285
282
279
276
273
270
267
264
261
258
255
252
249
246
243
240
237
234
231
228
225
222
219
216
1
1
1
1
1
1
1
1
1
1
1
1
-
(1)
(1)
(1)
2
11
12
-
2
23
32
L1
3
3
-
-
41
44
33
34
46
K4
N4
L2
L3
L5
4
4
5
13
14
-
5
24
25
-
6
6
7
7
(1)
(1)
(1)
8
15
16
-
21
22
31
24
26
-
H1
H2
K3
H4
J2
-
1
1
1
1
1
-
8
27
38
N2
9
9
28
-
40
48
N3
N5
M4
K5
-
10
11
12
13
14
15
16
17
18
1
10
11
12
13
14
15
16
17
18
1
17
18
-
29
30
-
43
45
-
19
20
-
27
28
35
J3
J4
M1
1
1
1
1
-
32
33
-
49
K6
L6
-
1
1
-
50
-
(1)
(1)
(1)
22
30
K2
34
-
51
M6
-
1
-
-
-
-
-
-
142
C3
2
2
-
-
118
126
133
-
C9
A7
A5
-
2
2
2
-
(1)
(1)
(1)
2
99
-
143
A2
2
87
-
3
-
-
3
4
-
4
C1
2
2
2
-
4
-
(1)
(1)
(1)
5
1
2
2
B1
C2
-
5
89
90
-
128
129
-
D7
A6
-
2
2
-
(1)
(1)
(1)
6
3
6
7
-
-
7
(1)
(1)
(1)
(1)
8
3
4
5
6
D4
D3
2
2
2
2
2
2
2
2
2
2
-
8
91
92
-
130
131
135
132
134
137
136
138
139
140
-
B6
C6
C5
D6
B5
A4
D5
B4
C4
A3
-
2
2
2
2
2
2
2
2
2
2
-
(1)
(1)
9
9
10
11
12
13
14
15
16
17
18
-
7
D2
10
11
12
13
14
15
16
17
18
6
7
-
9
E4
E3
E1
E2
F4
F3
F2
-
93
94
-
10
12
11
13
14
15
-
8
9
-
95
96
-
10
-
97
-
Notes:
1. Global control pin.
6
www.xilinx.com
DS051 (v2.0) January 25, 2001
1-800-255-7778
Advance Product Specification
R
XC95144XV High-Performance CPLD
Function Macro-
BScan
Function
Block
BScan
Macro-
cell
Block
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
cell
TQ100 TQ144 CS144 Order Bank
TQ100 TQ144 CS144 Order Bank
1
-
35
-
-
-
N6
L8
213
210
207
204
201
198
195
192
189
186
183
180
177
174
171
168
165
162
159
156
153
150
147
144
141
138
135
132
129
126
123
120
117
114
111
108
-
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
1
2
-
50
-
-
71
75
-
-
105
102
99
96
93
90
87
84
81
78
75
72
69
66
63
60
57
54
51
48
45
42
39
36
33
30
27
24
21
18
15
12
9
-
2
52
59
-
1
1
-
N12
L12
-
1
1
-
3
3
4
-
-
4
-
5
36
37
-
53
54
66
56
57
68
58
60
70
61
64
-
M7
N7
M10
K7
N8
N11
M8
K8
L11
N9
K9
-
1
1
1
1
1
1
1
1
1
1
1
-
5
52
53
-
74
76
77
78
80
79
82
85
81
86
87
83
88
-
M13
L13
K10
K11
K13
K12
J11
H10
J10
H11
H12
J12
H13
-
1
1
1
1
1
1
1
1
1
1
1
1
1
-
6
6
7
7
8
39
40
-
8
54
55
-
9
9
10
11
12
13
14
15
16
17
18
1
10
11
12
13
14
15
16
17
18
1
41
42
-
56
58
-
43
46
-
59
60
-
49
-
69
-
M11
-
1
-
61
-
-
-
-
-
-
-
-
-
2
74
-
106
-
C11
-
2
-
2
63
-
91
95
97
92
93
-
G11
F11
E13
G10
F13
-
2
2
2
2
2
-
3
3
4
-
111
110
112
-
B11
A12
A11
-
2
2
2
-
4
-
5
76
77
-
5
64
65
-
6
6
7
7
8
78
79
-
113
116
115
119
120
-
D10
A10
B10
B9
A9
-
2
2
2
2
2
-
8
66
67
-
94
96
101
98
100
103
102
104
107
105
-
F12
F10
D13
E12
E10
D11
D12
C13
B13
C12
-
2
2
2
2
2
2
2
2
2
2
-
9
9
10
11
12
13
14
15
16
17
18
10
11
12
13
14
15
16
17
18
80
81
-
68
70
-
82
85
-
121
124
117
125
-
D8
A8
D9
B7
-
2
2
2
2
-
71
72
-
6
86
-
73
-
3
0
DS051 (v2.0) January 25, 2001
www.xilinx.com
7
Advance Product Specification
1-800-255-7778
R
XC95144XV High-Performance CPLD
XC95144XV Global, JTAG and Power Pins
Pin Type
I/O/GCK1
I/O/GCK2
I/O/GCK3
I/O/GTS1
I/O/GTS2
I/O/GTS3
I/O/GTS4
I/O/GSR
TCK
TQ100
TQ144
CS144
22
30
K2
23
32
L1
27
38
N2
3
5
D4
4
6
D3
1
2
B1
2
3
143
C2
99
48
A2
L10
67
TDI
45
63
L9
TDO
83
122
C8
TMS
47
65
N10
V
CCINT 2.5V
5, 57, 98
26, 38, 51
88
8, 42, 84, 141
37, 55, 73
1, 109, 127
B3, D1, J13, L4
L7, N1, N13
A1, A13, C7
VCCIO
1
2
VCCIO
GND
21, 31, 44, 62, 69, 75, 84,
100
18, 29, 36, 47, 62, 72, 89, 90, B2, B8, B12, C10, E11, G1,
99, 108, 114, 123, 144
G12, G13, K1, M2, M5, M9,
M12
No Connects
-
-
-
8
www.xilinx.com
1-800-255-7778
DS051 (v2.0) January 25, 2001
Advance Product Specification
R
XC95144XV High-Performance CPLD
Ordering Information
Example:
XC95144XV -7 TQ 100 C
Device Type
Temperature Range
Number of Pins
Package Type
Speed Grade
Device Ordering Options
Speed
Package
Temperature
-7 7.5 ns pin-to-pin delay
-5 5 ns pin-to-pin delay
-4 4 ns pin-to-pin delay
TQ100 100-pin Thin Quad Flat Pack (TQFP)
TQ144 144-pin Thin Quad Flat Pack (TQFP)
CS144 144-ball Chip Scale Package (CSP)
C = Commercial T = 0°C to +70°C
A
I = Industrial
T = –40°C to +85°C
A
Component Availability
Pins
Type
Code
100
144
144
Plastic TQFP
Plastic TQFP
Plastic CSP
TQ100
C, I
TQ144
C, I
CS144
XC95144XV
-7
C
(C)
-
-5
-4
(C)
(C)
(C)
(C)
Notes:
o
o
o
o
1. C = Commercial (T = 0 C to +70 C); I = Industrial (T = –40 C to +85 C).
A
A
2. ( ) Parenthesis indicate future planned products. Please contact Xilinx for up-to-date information.
Revision History
The following table shows the revision history for this document..
Date
Version
1.0
Revision
06/28/00
01/25/01
Initial Xilinx release. Advance information specification.
2.0
Added -4 performance specifications.Updated I vs. Frequency Figure 1.
CC
DS051 (v2.0) January 25, 2001
www.xilinx.com
9
Advance Product Specification
1-800-255-7778
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