XC95144_09 [XILINX]
In-System Programmable CPLD; 在系统可编程CPLD
| 型号： | XC95144_09 |
| 厂家： | 
XILINX, INC |
| 描述： | In-System Programmable CPLD |
| 文件： | 总10页 (文件大小：274K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0
R
XC95144 In-System
Programmable CPLD
0
5
DS067 (v5.7) May 28, 2009
Product Specification
Features
Description
•
•
•
•
•
7.5 ns pin-to-pin logic delays on all pins
The XC95144 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of eight
36V18 Function Blocks, providing 3,200 usable gates with
propagation delays of 7.5 ns. See Figure 2 for the architec-
ture overview.
fCNT to 111 MHz
144 macrocells with 3,200 usable gates
Up to 133 user I/O pins
5V in-system programmable
-
-
Endurance of 10,000 program/erase cycles
Program/erase over full commercial voltage and
temperature range
Power Management
Power dissipation can be reduced in the XC95144 by con-
figuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.
•
•
Enhanced pin-locking architecture
Flexible 36V18 Function Block (FB)
-
90 product terms drive any or all of 18 macrocells
within Function Block
Operating current for each design can be approximated for
specific operating conditions using the following equation:
-
Global and product term clocks, output enables,
set and reset signals
I
CC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
Where:
MCHP = Macrocells in high-performance mode
•
•
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
•
•
•
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design
protection
Figure 1 shows a typical calculation for the XC95144
device.
•
•
•
•
High-drive 24 mA outputs
3.3V or 5V I/O capability
Advanced CMOS 5V FastFLASH technology
Supports parallel programming of more than one
XC9500 concurrently
Available in 100-pin PQFP, 100-pin TQFP, and 160-pin
PQFP packages
600
(480)
•
400
(320)
(300)
200
(160)
0
50
100
Clock Frequency (MHz)
DS067_01_110101
Figure 1: Typical I vs. Frequency for XC95144
CC
© 2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries.
All other trademarks are the property of their respective owners.
DS067 (v5.7) May 28, 2009
www.xilinx.com
Product Specification
1
R
XC95144 In-System Programmable CPLD
3
JTAG
In-System Programming Controller
1
JTAG Port
Controller
36
Function
18
18
18
18
Block 1
I/O
Macrocells
1 to 18
I/O
I/O
I/O
36
36
36
Function
Block 2
Macrocells
1 to 18
I/O
Blocks
I/O
I/O
Function
Block 3
Macrocells
1 to 18
I/O
I/O
3
I/O/GCK
I/O/GSR
I/O/GTS
Function
Block 4
1
2
Macrocells
1 to 18
36
Function
Block 8
18
Macrocells
1 to 18
DS067_02_110101
Figure 2: XC95144 Architecture
Function block outputs (indicated by the bold line) drive the I/O blocks directly.
DS067 (v5.7) May 28, 2009
www.xilinx.com
Product Specification
2
R
XC95144 In-System Programmable CPLD
Absolute Maximum Ratings
Symbol
Description
Value
Units
V
Supply voltage relative to GND
–0.5 to 7.0
V
V
V
CC
V
Input voltage relative to GND
Voltage applied to 3-state output
Storage temperature (ambient)
Junction temperature
–0.5 to V + 0.5
CC
IN
V
–0.5 to V + 0.5
TS
CC
o
T
–65 to +150
+150
C
STG
o
T
C
J
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Recommended Operation Conditions
Symbol
Parameter
Commercial T = 0 C to 70 C
Min
4.75
4.5
4.75
4.5
3.0
0
Max
5.25
5.5
Units
o
o
V
Supply voltage for internal logic
and input buffers
V
CCINT
A
o
o
Industrial T = –40 C to +85 C
A
o
o
V
Supply voltage for output drivers
for 5V operation
Commercial T = 0 C to 70 C
5.25
5.5
V
CCIO
A
o
o
Industrial T = –40 C to +85 C
A
Supply voltage for output drivers for 3.3V operation
Low-level input voltage
3.6
V
0.80
V
V
V
IL
V
High-level input voltage
2.0
0
V
+ 0.5
CCINT
IH
V
Output voltage
V
CCIO
O
Quality and Reliability Characteristics
Symbol
Parameter
Min
20
Max
Units
T
Data Retention
Program/Erase Cycles (Endurance)
-
-
Years
DR
N
10,000
Cycles
PE
DC Characteristic Over Recommended Operating Conditions
Symbol
Parameter
Test Conditions
Min
Max
-
Units
V
Output high voltage for 5V outputs
Output high voltage for 3.3V outputs
Output low voltage for 5V outputs
Output low voltage for 3.3V outputs
Input leakage current
I
I
I
I
= –4.0 mA, V = Min
2.4
V
V
OH
OH
OH
OL
OL
CC
= –3.2 mA, V = Min
2.4
-
CC
V
= 24 mA, V = Min
-
-
-
0.5
0.4
10
V
OL
CC
= 10 mA, V = Min
V
CC
I
V
V
= Max
CC
μA
IL
= GND or V
IN
CC
CC
I
I/O high-Z leakage current
I/O capacitance
V
V
= Max
= GND or V
-
-
10
10
μA
pF
IH
CC
IN
C
V
= GND
IN
IN
f = 1.0 MHz
I
Operating supply current
(low power mode, active)
V = GND, No load
f = 1.0 MHz
160 (Typical)
mA
CC
I
DS067 (v5.7) May 28, 2009
www.xilinx.com
Product Specification
3
R
XC95144 In-System Programmable CPLD
AC Characteristics
XC95144-7
XC95144-10
XC95144-15
Symbol
Parameter
I/O to output valid
Min
Max
7.5
-
Min
Max
Min
Max
Units
ns
T
T
-
-
10.0
-
8.0
0
15.0
PD
SU
I/O setup time before GCK
I/O hold time after GCK
4.5
6.0
-
-
ns
T
0
-
0
-
-
ns
H
T
GCK to output valid
-
4.5
-
-
6.0
-
8.0
ns
CO
(1)
f
16-bit counter frequency
125.0
111.1
-
95.2
55.6
4.0
4.0
-
-
MHz
MHz
ns
CNT
(2)
f
Multiple FB internal operating frequency
I/O setup time before p-term clock input
I/O hold time after p-term clock input
P-term clock output valid
83.3
-
66.7
-
-
-
-
SYSTEM
T
0.5
-
2.0
PSU
T
4.0
-
4.0
-
-
ns
PH
T
-
8.5
5.5
5.5
9.5
9.5
-
-
10.0
6.0
6.0
10.0
10.0
-
12.0
11.0
11.0
14.0
14.0
-
ns
PCO
T
GTS to output valid
-
-
-
-
-
ns
OE
T
GTS to output disable
-
ns
OD
T
T
Product term OE to output enabled
Product term OE to output disabled
GCK pulse width (High or Low)
-
-
-
ns
POE
POD
WLH
-
-
-
ns
T
4.0
7.0
4.5
7.5
5.5
8.0
ns
T
Asynchronous preset/reset pulse width
(High or Low)
-
-
-
ns
APRPW
Notes:
1. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable.
fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG
2. fSYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs.
.
V
TEST
R
1
2
Output Type
V
V
R
R
C
L
CCIO
TEST
1
2
Device Output
5.0V
3.3V
5.0V
3.3V
160Ω
260Ω
120Ω
360Ω
35 pF
35 pF
C
R
L
DS067_03_110101
Figure 3: AC Load Circuit
DS067 (v5.7) May 28, 2009
www.xilinx.com
Product Specification
4
R
XC95144 In-System Programmable CPLD
Internal Timing Parameters
XC95144-7
XC95144-10
XC95144-15
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Units
Buffer Delays
T
Input buffer delay
-
-
-
-
-
-
2.5
1.5
4.5
5.5
2.5
0
-
-
-
-
-
-
3.5
2.5
6.0
6.0
3.0
0
-
-
-
-
-
-
4.5
3.0
7.5
11.0
4.5
0
ns
ns
ns
ns
ns
ns
IN
T
GCK buffer delay
GCK
GSR
T
GSR buffer delay
T
GTS buffer delay
GTS
T
Output buffer delay
Output buffer enable/disable delay
OUT
T
EN
Product Term Control Delays
T
T
Product term clock delay
Product term set/reset delay
Product term 3-state delay
-
-
-
3.0
2.0
4.5
-
-
-
3.0
2.5
3.5
-
-
-
2.5
3.0
5.0
ns
ns
ns
PTCK
PTSR
T
PTTS
Internal Register and Combinatorial Delays
T
T
Combinatorial logic propagation delay
Register setup time
-
1.5
3.0
-
0.5
-
-
1.0
-
-
3.0
-
ns
ns
ns
ns
ns
ns
ns
ns
PDI
SUI
2.5
3.5
T
Register hold time
-
3.5
-
4.5
-
HI
T
Register clock to output valid time
Register async. S/R to output delay
Register async. S/R recover before clock
Internal logic delay
0.5
6.5
-
-
0.5
7.0
-
-
0.5
8.0
-
COI
T
-
-
-
AOI
T
7.5
-
10.0
10.0
RAI
T
2.0
10.0
-
-
2.5
11.0
-
-
3.0
11.5
LOGI
T
Internal low power logic delay
-
LOGILP
Feedback Delays
T
FastCONNECT feedback delay
-
-
8.0
4.0
-
-
9.5
3.5
-
-
11.0
3.5
ns
ns
F
T
Function block local feedback delay
LF
Time Adders
(1)
T
Incremental product term allocator delay
Slew-rate limited delay
-
-
1.0
4.0
-
-
1.0
4.5
-
-
1.0
5.0
ns
ns
PTA
T
SLEW
Notes:
1. TPTA is multiplied by the span of the function as defined in the XC9500 family data sheet.
DS067 (v5.7) May 28, 2009
www.xilinx.com
Product Specification
5
R
XC95144 In-System Programmable CPLD
XC95144 I/O Pins
Function Macro-
BScan
TQ100 PQ100 PQ160 Order
Function Macro-
BScan
Block
cell
Block
cell
TQ100 PQ100 PQ160 Order
1
1
–
–
25
18
19
27
21
22
32
23
24
34
26
28
38
29
30
39
429
426
423
420
417
414
411
408
405
402
399
396
393
390
387
384
3
1
–
–
43
321
[1]
[1]
[1]
[1]
1
2
11
12
–
13
14
–
3
2
23
25
35
318
1
3
3
3
–
–
–
–
45
48
36
37
50
315
312
309
306
303
1
4
3
4
1
5
13
14
–
15
16
–
3
5
24
25
–
26
27
–
1
6
3
6
1
7
3
7
[1]
[1]
[1]
[1]
1
8
15
16
–
17
18
–
3
8
27
29
42
300
1
9
3
9
28
–
30
–
44
52
297
294
291
288
285
282
279
276
273
270
267
264
261
258
255
252
249
246
243
240
237
234
231
228
225
222
219
216
1
10
11
12
13
14
15
16
17
18
1
3
10
11
12
13
14
15
16
17
18
1
1
17
18
–
19
20
–
3
29
30
–
31
32
–
47
1
3
49
1
3
53
1
19
20
–
21
22
–
3
32
33
–
34
35
–
54
1
3
56
1
3
55
[1]
[1]
[1]
[1]
1
22
24
33
381
3
34
–
36
–
57
1
–
–
–
–
378
3
–
2
–
158
375
4
–
–
132
140
147
149
142
143
150
144
145
151
146
148
153
152
154
155
156
–
[1]
[1]
[1]
[1]
2
2
99
1
159
372
4
2
87
–
89
–
2
3
–
–
3
369
4
3
2
4
–
–
5
366
4
4
–
–
[1]
[1]
[1]
[1]
2
5
1
3
2
363
360
4
5
89
90
–
91
92
–
[1]
[1]
[1]
[1]
2
6
2
4
4
4
6
2
7
–
–
7
357
4
7
[1]
[1]
[1]
[1]
2
8
3
5
6
354
351
4
8
91
92
–
93
94
–
[1]
[1]
[1]
[1]
2
9
4
6
8
4
9
2
10
11
12
13
14
15
16
17
18
–
6
–
8
9
348
4
10
11
12
13
14
15
16
17
18
2
11
12
14
13
15
16
17
–
345
342
339
336
333
330
327
324
4
93
94
–
95
96
–
2
7
9
4
2
–
–
4
2
8
10
11
–
4
95
96
–
97
98
–
2
9
4
2
–
4
2
10
–
12
–
4
97
–
99
–
2
4
Notes:
1. Global control pin.
Macrocell outputs to package pins subject to change, contact factory for latest information. Power, GND, JTAG, and Global Signals are
fixed.
DS067 (v5.7) May 28, 2009
www.xilinx.com
Product Specification
6
R
XC95144 In-System Programmable CPLD
XC95144 I/O Pins (Continued)
Function Macro-
BScan
TQ100 PQ100 PQ160 Order
Function Macro-
BScan
Block
cell
Block
cell
TQ100 PQ100 PQ160 Order
5
1
–
35
–
–
37
–
65
58
213
210
207
204
201
198
195
192
189
186
183
180
177
174
171
168
165
162
159
156
153
150
147
144
141
138
135
132
129
126
123
120
117
114
111
108
7
1
–
50
–
–
52
–
–
105
102
99
96
93
90
87
84
81
78
75
72
69
66
63
60
57
54
51
48
45
42
39
36
33
30
27
24
21
18
15
12
9
5
2
7
2
79
5
3
66
7
3
84
5
4
–
–
67
7
4
–
–
85
5
5
36
37
–
38
39
–
59
7
5
52
53
–
54
55
–
82
5
6
60
7
6
86
5
7
74
7
7
87
5
8
39
40
–
41
42
–
62
7
8
54
55
–
56
57
–
88
5
9
63
7
9
90
5
10
11
12
13
14
15
16
17
18
1
76
7
10
11
12
13
14
15
16
17
18
1
89
5
41
42
–
43
44
–
64
7
56
58
–
58
60
–
92
5
68
7
95
5
78
7
91
5
43
46
–
45
48
–
69
7
59
60
–
61
62
–
96
5
72
7
97
5
83
7
93
5
49
–
51
–
77
7
61
–
63
–
98
5
–
7
–
6
–
–
–
8
–
–
–
6
2
74
–
76
–
117
119
123
122
124
125
126
129
128
133
134
130
135
138
131
139
–
8
2
63
–
65
–
101
105
107
102
103
109
104
106
112
108
111
114
113
115
118
116
–
6
3
8
3
6
4
–
–
8
4
–
–
6
5
76
77
–
78
79
–
8
5
64
65
–
66
67
–
6
6
8
6
6
7
8
7
6
8
78
79
–
80
81
–
8
8
66
67
–
68
69
–
6
9
8
9
6
10
11
12
13
14
15
16
17
18
8
10
11
12
13
14
15
16
17
18
6
80
81
–
82
83
–
8
68
70
–
70
72
–
6
8
6
8
6
82
85
–
84
87
–
8
71
72
–
73
74
–
6
8
6
8
6
6
86
–
88
–
8
73
–
75
–
3
6
8
0
Notes:
1. Global control pin.
Macrocell outputs to package pins subject to change, contact factory for latest information. Power, GND, JTAG, and Global Signals are
fixed.
DS067 (v5.7) May 28, 2009
www.xilinx.com
Product Specification
7
R
XC95144 In-System Programmable CPLD
XC95144 Global, JTAG, and Power Pins
Pin Type
I/O/GCK1
I/O/GCK2
I/O/GCK3
I/O/GTS1
I/O/GTS2
I/O/GTS3
I/O/GTS4
I/O/GSR
TCK
TQ100
PQ100
PQ160
22
24
33
23
25
35
27
29
42
3
5
6
4
6
8
1
3
2
2
4
4
99
1
159
48
50
75
TDI
45
83
47
85
71
TDO
136
73
TMS
47
49
V
CCINT 5V
5, 57, 98
26, 38, 51, 88
7, 59, 100
28, 40, 53, 90
10, 46, 94, 157
1, 41, 61, 81, 121, 141
V
CCIO 3.3V/5V
GND
100, 21, 31, 44, 62, 69, 75, 2, 23, 33, 46, 64, 71, 77, 86
84
20, 31, 40, 51, 70, 80, 99,
100, 110, 120, 127, 137, 160
No Connects
–
–
–
DS067 (v5.7) May 28, 2009
www.xilinx.com
Product Specification
8
R
XC95144 In-System Programmable CPLD
Device Part Marking and Ordering Combination Information
R
Device Type
Package
XC95xxx
TQ144
This line not
related to device
part number
Speed
7C
Operating Range
1
Sample package with part marking.
Speed
(pin-to-pin
delay)
Device Ordering and
Part Marking Number
Pkg.
Symbol
No. of
Pins
Operating
Range
(1)
Package Type
XC95144-7PQ100C
XC95144-7PQG100C
XC95144-7TQ100C
XC95144-7TQG100C
XC95144-7PQ160C
XC95144-7PQG160C
XC95144-10PQ100C
XC95144-10PQG100C
XC95144-10TQ100C
XC95144-10TQG100C
XC95144-10PQ160C
XC95144-10PQG160C
XC95144-10PQ100I
XC95144-10PQG100I
XC95144-10TQ100I
XC95144-10TQG100I
XC95144-10PQ160I
XC95144-10PQG160I
XC95144-15PQ100C
XC95144-15PQG100C
XC95144-15TQ100C
XC95144-15TQG100C
XC95144-15PQ160C
XC95144-15PQG160C
XC95144-15PQ100I
XC95144-15PQG100I
XC95144-15TQ100I
XC95144-15TQG100I
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
15 ns
15 ns
15 ns
15 ns
15 ns
15 ns
15 ns
15 ns
15 ns
15 ns
PQ100 100-pin
PQG100 100-pin
TQ100 100-pin
TQG100 100-pin
PQ160 160-pin
PQG160 160-pin
PQ100 100-pin
PQG100 100-pin
TQ100 100-pin
TQG100 100-pin
PQ160 160-pin
PQG160 160-pin
PQ100 100-pin
PQG100 100-pin
TQ100 100-pin
TQG100 100-pin
PQ160 160-pin
PQG160 160-pin
PQ100 100-pin
PQG100 100-pin
TQ100 100-pin
TQG100 100-pin
PQ160 160-pin
PQG160 160-pin
PQ100 100-pin
PQG100 100-pin
TQ100 100-pin
TQG100 100-pin
Plastic Quad Flat Pack (PQFP)
C
C
C
C
C
C
C
C
C
C
C
C
I
Plastic Quad Flat Pack (PQFP); Pb-Free
Thin Quad Flat Pack (TQFP)
Thin Quad Flat Pack (TQFP); Pb-Free
Plastic Quad Flat Pack (PQFP)
Plastic Quad Flat Pack (PQFP); Pb-Free
Plastic Quad Flat Pack (PQFP)
Plastic Quad Flat Pack (PQFP); Pb-Free
Thin Quad Flat Pack (TQFP)
Thin Quad Flat Pack (TQFP); Pb-Free
Plastic Quad Flat Pack (PQFP)
Plastic Quad Flat Pack (PQFP); Pb-Free
Plastic Quad Flat Pack (PQFP)
Plastic Quad Flat Pack (PQFP); Pb-Free
Thin Quad Flat Pack (TQFP)
I
I
Thin Quad Flat Pack (TQFP); Pb-Free
Plastic Quad Flat Pack (PQFP)
I
I
Plastic Quad Flat Pack (PQFP); Pb-Free
Plastic Quad Flat Pack (PQFP)
I
C
C
C
C
C
C
I
Plastic Quad Flat Pack (PQFP); Pb-Free
Thin Quad Flat Pack (TQFP)
Thin Quad Flat Pack (TQFP); Pb-Free
Plastic Quad Flat Pack (PQFP)
Plastic Quad Flat Pack (PQFP); Pb-Free
Plastic Quad Flat Pack (PQFP)
Plastic Quad Flat Pack (PQFP); Pb-Free
Thin Quad Flat Pack (TQFP)
I
I
Thin Quad Flat Pack (TQFP); Pb-Free
I
DS067 (v5.7) May 28, 2009
www.xilinx.com
Product Specification
9
R
XC95144 In-System Programmable CPLD
Speed
(pin-to-pin
delay)
Device Ordering and
Part Marking Number
Pkg.
Symbol
No. of
Pins
Operating
Range
(1)
Package Type
XC95144-15PQ160I
XC95144-15PQG160I
Notes:
15 ns
15 ns
PQ160 160-pin
PQG160 160-pin
Plastic Quad Flat Pack (PQFP)
Plastic Quad Flat Pack (PQFP); Pb-Free
I
I
1. C = Commercial: TA = 0° to +70°C; I = Industrial: TA = –40° to +85°C
Additional Information
XC9500 data sheets and application notes.
Packages
Revision History
The following table shows the revision history for this document.
Date
Version
4.0
Revision
Update AC characteristics and internal parameters.
Updated format.
12/04/98
06/18/03
08/21/03
11/06/03
02/16/04
5.0
5.1
Updated Package Device Marking Pin 1 orientation.
Update pin count on PQ160 packages.
5.2
5.3
Correct GTS pin information by removing rows on GTS3 GTS4 from table on page 8. Add
links to additional information.
04/15/05
01/03/06
04/03/06
05/28/09
5.4
5.5
5.6
5.7
Added asynchronous preset/reset pulse width specification (T
).
APRPW
Added GTS3 and GTS4 pins to table on page 8.
Added Warranty Disclaimer. Added Pb-Free package ordering information.
Removed table note reference from Function Block 2, Macrocell 3 in XC95144 I/O Pins.
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE
TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT
http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN
AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED IN THE XILINX DATA
SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR
INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS
LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE
POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT
TO APPLICABLE LAWS AND REGULATIONS.
DS067 (v5.7) May 28, 2009
www.xilinx.com
Product Specification
10
相关型号：
©2020 ICPDF网 联系我们和版权申明