XC95288XV_07 [XILINX]
High-Performance CPLD; 高性能CPLD
| 型号： | XC95288XV_07 |
| 厂家： | 
XILINX, INC |
| 描述： | High-Performance CPLD |
| 文件： | 总14页 (文件大小：134K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
u
0
R
XC95288XV High-Performance
CPLD
0
5
DS050 (v3.0) June 25, 2007
Product Specification
Note: This product is being discontinued. You cannot
order parts after May 14, 2008. Xilinx recommends replac-
ing XC95288XV devices with equivalent XC95288XL
devices in all designs as soon as possible. Recommended
replacements are pin compatible, however require a VCC
change to 3.3V, and a recompile of the design file. In addi-
tion, there is no 1.8V I/O support, and only one output bank
is supported. See XCN07010 for details regarding this dis-
continuation, including device replacement recomendations
for the XC95288XV CPLD.
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XV device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
For a general estimate of ICC, the following equation may be
used:
P
TOTAL = PINT + PIO = ICCINT x VCCINT + PIO
Features
Separating internal and I/O power here is convenient
because XC9500XV CPLDs also separate the correspond-
ing power pins. PIO is a strong function of the load capaci-
tance driven, so it is handled by I = CVf. ICCINT is another
situation that reflects the actual design considered and the
internal switching speeds. An estimation expression for
•
•
288 macrocells with 6,400 usable gates
Available in small footprint packages
-
-
-
-
144-pin TQFP (117 user I/O pins)
208-pin PQFP (168 user I/O pins)
280-pin CSP (192 user I/O pins)
256-pin FBGA (192 user I/O pins)
I
CCINT (taken from simulation) is:
•
•
Optimized for high-performance 2.5V systems
I
CCINT(mA) = MCHS(0.122 X PTHS + 0.238) + MCLP(0.042 x
PTLP + 0.171) + 0.04(MCHS + MCLP) x fMAX x MCTOG
-
-
Low power operation
Multi-voltage operation
Advanced system features
where:
-
-
-
In-system programmable
Four separate output banks
MCHS = # macrocells used in high speed mode
MCLP = #macrocells used in low power mode
Superior pin-locking and routability with
Fast CONNECT™ II switch matrix
Extra wide 54-input Function Blocks
Up to 90 product-terms per macrocell with
individual product-term allocation
Local clock inversion with three global and one
product-term clocks
PTHS = average p-terms used per high speed macrocell
PTLP = average p-terms used over low power macrocell
-
-
f
MAX = max clocking frequency in the device
MCTOG = % macrocells toggling on each clock (12% is
frequently a good estimate
-
This calculation was derived from laboratory measurements
of an XC9500XV part filled with 16-bit counters and allowing
a single output (the LSB) to be enabled. The actual ICC
value varies with the design application and should be veri-
fied during normal system operation. Figure 1 shows the
above estimation in a graphical form. For a more detailed
discussion of power consumption in this device, see Xilinx
-
-
Individual output enable per output pin
Input hysteresis on all user and boundary-scan pin
inputs
-
-
Bus-hold ciruitry on all user pin inputs
Full IEEE Standard 1149.1 boundary-scan (JTAG)
•
•
•
•
Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
-
-
20 year data retention
ESD protection exceeding 2,000V
Description
The XC95288XV is a 2.5V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
cations and computing systems. It is comprised of 16
54V18 Function Blocks, providing 6,400 usable gates with
propagation delays of 6 ns.
© 2005, 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS050 (v3.0) June 25, 2007
www.xilinx.com
1
Product Specification
R
XC95288XV High-Performance CPLD
application note XAPP361, “Planning for High Speed
XC9500XV Designs.”
450
400
350
ance
m
300
250
200
for
r
e
P
gh
Hi
150
100
50
0
50
100
lock
150
cy
200
250
C
F
r
e
que
n
(MHz)
DS050_01_041405
Figure 1: Typical ICC vs. Frequency for XC95288XV
2
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DS050 (v3.0) June 25, 2007
Product Specification
R
XC95288XV High-Performance CPLD
3
JTAG
In-System Programming Controller
1
JTAG Port
Controller
54
54
54
54
Function
Block 1
18
18
18
18
I/O
Macrocells
1 to 18
I/O
I/O
I/O
Function
Block 2
Macrocells
1 to 18
I/O
Blocks
I/O
I/O
Function
Block 3
Macrocells
1 to 18
I/O
I/O
3
I/O/GCK
I/O/GSR
I/O/GTS
Function
Block 4
1
4
Macrocells
1 to 18
54
Function
Block 16
18
Macrocells
1 to 18
DS055_02_101300
Figure 2: XC95288XV Architecture
(Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.)
DS050 (v3.0) June 25, 2007
www.xilinx.com
3
Product Specification
R
XC95288XV High-Performance CPLD
The LVTTL I/O standard is a general purpose EIA/JEDEC
standard for 3.3V applications that use an LVTTL input
buffer and Push-Pull output buffer. The LVCMOS2 standard
is used in 2.5V applications.
Supported I/O Standards
Table 1: IOSTANDARD Options
IOSTANDARD
LVTTL
VCCIO
3.3V
2.5V
1.8V
XC9500XV CPLDs are also 1.8V I/O compatible. The
X25TO18 setting is provided for generating 1.8V compatible
outputs from a CPLD normally operating in a 2.5V environ-
ment. The ISE software automatically groups outputs with
matching IOSTANDARD settings into the same VCCIO bank
when no location constraints are specified. The default I/O
Standard for pads without IOSTANDARD attributes is
LVTTL for XC9500XV devices.
LVCMOS2
X25TO18
The XC95288XV CPLD features both LVCMOS and LVTTL
I/O implementations. See Table 1 for I/O standard voltages.
Absolute Maximum Ratings
Symbol
VCC
Description
Supply voltage relative to GND
Value
–0.5 to 2.7
–0.5 to 3.6
–0.5 to 3.6
–0.5 to 3.6
–65 to +150
+150
Units
V
VCCIO
VIN
Supply voltage for output drivers
Input voltage relative to GND(1)
Voltage applied to 3-state output(1)
Storage temperature (ambient)
Junction temperature
V
V
VTS
V
TSTG
TJ
oC
oC
Notes:
1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the
device pins may undershoot to –2.0V or overshoot to +3.6V, provided this over- or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
3. For solder specifications, see Xilinx Packaging.
Recommended Operation Conditions
Symbol
Parameter
Min
2.37
2.37
3.0
2.37
1.71
0
Max
2.62
2.62
3.6
Units
VCCINT
Supply voltage for internal logic
and input buffers
Commercial TA = 0oC to +70oC
Industrial TA = –40oC to +85oC
V
VCCIO
Supply voltage for output drivers for 3.3V operation
Supply voltage for output drivers for 2.5V operation
Supply voltage for output drivers for 1.8V operation
Low-level input voltage
V
V
V
V
V
V
2.62
1.89
0.8
VIL
VIH
VO
High-level input voltage
1.7
0
3.6
Output voltage
VCCIO
4
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DS050 (v3.0) June 25, 2007
Product Specification
R
XC95288XV High-Performance CPLD
Quality and Reliability Characteristics
Symbol
TDR
Parameter
Min
20
Max
Units
Years
Cycles
Volts
Data retention
-
-
-
NPE
Program/Erase cycles (endurance)
Electrostatic Discharge (ESD)
1,000
2,000
VESD
DC Characteristics Over Recommended Operating Conditions
Symbol
Parameter
Test Conditions
IOH = –4.0 mA
Min
2.4
2.0
Max
-
Units
VOH
Output high voltage for 3.3V outputs
Output high voltage for 2.5V outputs
Output high voltage for 1.8V outputs
Output low voltage for 3.3V outputs
Output low voltage for 2.5V outputs
Output low voltage for 1.8V outputs
Input leakage current
V
V
I
I
OH = –1.0 mA
-
OH = –100 μA
90% VCCIO
-
V
VOL
IOL = 8.0 mA
-
-
-
-
0.4
0.4
0.4
±10
V
I
I
OL = 1.0 mA
V
OL = 100 μA
V
IIL
VCC = 2.62V
μA
VCCIO = 3.6V
VIN = GND or 3.6V
IIH
Input high-Z leakage current
VCC = 2.62V
-
±10
μA
VCCIO = 3.6V
VIN = GND or 3.6V
VCC min < VIN < 3.6V
-
-
±150
10
μA
CIN
ICC
I/O capacitance
VIN = GND
f = 1.0 MHz
pF
Operating supply current
(low power mode, active)
VI = GND, No load
f = 1.0 MHz
59
mA
AC Characteristics
XC95288XV-6
Min Max
6.0
XC95288XV-7
XC95288XV-10
Symbol
TPD
Parameter
Min
Max
7.5
-
Min
Max
10
Units
ns
I/O to output valid
-
-
4.8
0
-
6.5
0
TSU
I/O setup time before GCK
I/O hold time after GCK
GCK to output valid
4.0
-
-
ns
TH
0
-
-
-
-
ns
TCO
3.8
208
-
4.5
125.0
-
5.8
100.0
ns
fSYSTEM Multiple FB internal operating
frequency
-
-
-
MHz
TPSU
I/O setup time before p-term clock
input
1.0
-
1.6
-
2.1
-
ns
TPH
TPCO
TOE
I/O hold time after p-term clock input
P-term clock output valid
2.6
-
3.2
-
4.4
-
ns
ns
ns
ns
ns
ns
-
-
-
-
-
6.8
4.5
4.5
8.4
8.4
-
-
-
-
-
7.7
5.0
5.0
9.5
9.5
-
-
-
-
-
10.2
7.0
GTS to output valid
TOD
GTS to output disable
7.0
TPOE
TPOD
Product term OE to output enabled
Product term OE to output disabled
11.0
11.0
DS050 (v3.0) June 25, 2007
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5
Product Specification
R
XC95288XV High-Performance CPLD
XC95288XV-6
Min Max
XC95288XV-7
XC95288XV-10
Symbol
TAO
Parameter
GSR to output valid
Min
-
Max
Min
-
Max
Units
ns
-
10.8
12.0
14.5
TPAO
TWLH
TPLH
P-term S/R to output valid
-
11.8
-
12.6
-
15.3
ns
GCK pulse width (High or Low)
P-term clock pulse width (High or Low)
2.4
6.0
6.0
-
-
-
4.0
6.5
6.5
-
-
-
5.0
7.0
7.0
-
-
-
ns
ns
TAPRPW Asynchronouspreset/reset pulsewidth
(High or Low)
ns
6
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DS050 (v3.0) June 25, 2007
Product Specification
R
XC95288XV High-Performance CPLD
V
TEST
R
1
Output Type
V
V
R
R
C
L
CCIO
TEST
1
2
Device Output
3.3V
2.5V
1.8V
3.3V
2.5V
1.8V
320Ω
250Ω
10KΩ
360Ω
660Ω
14KΩ
35 pF
35 pF
35 pF
R
C
L
2
DS050_03_110101
Figure 3: AC Load Circuit
Internal Timing Parameters
XC95288XV-6
XC95288XV-7 XC95288XV-10
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Units
Buffer Delays
TIN
Input buffer delay
GCK buffer delay
-
-
-
-
-
-
2.2
1.2
2.2
4.5
2.4
0
-
-
-
-
-
-
2.3
1.5
3.1
5.0
2.5
0
-
-
-
-
-
-
3.5
1.8
4.5
7.0
3.0
0
ns
ns
ns
ns
ns
ns
TGCK
TGSR
TGTS
TOUT
TEN
GSR buffer delay
GTS buffer delay
Output buffer delay
Output buffer enable/disable delay
Product Term Control Delays
TPTCK
TPTSR
TPTTS
Product term clock delay
Product term set/reset delay
Product term 3-state delay
-
-
-
2.0
1.0
6.2
-
-
-
2.4
1.4
7.2
-
-
-
2.7
1.8
7.5
ns
ns
ns
Internal Register and Combinatorial Delays
TPDI
Combinatorial logic propagation delay
Register setup time
-
2.0
1.6
2.0
1.6
-
0.4
-
-
2.6
2.2
2.6
2.2
-
1.3
-
3.0
3.5
3.0
3.5
-
1.7
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TSUI
-
-
THI
Register hold time
-
-
TECSU
TECHO
TCOI
TAOI
Register clock enable setup time
Register clock enable hold time
Register clock to output valid time
Register async. S/R to output delay
Register async. S/R recover before clock
Internal logic delay
-
-
-
-
-
-
0.2
6.2
-
0.5
6.4
1.0
7.0
-
-
-
-
TRAI
6.0
-
7.5
-
10.0
-
TLOGI
1.0
5.5
1.4
6.4
1.8
7.3
TLOGILP Internal low power logic delay
-
-
-
Feedback Delays
TF
Fast CONNECT II feedback delay
-
1.6
-
3.5
-
4.2
ns
Time Adders
TPTA
Incremental product term allocator delay
-
-
-
0.8
0.3
3.5
-
-
-
0.8
0.3
4.0
-
-
-
1.0
0.4
4.5
ns
ns
ns
TPTA2
TSLEW
Adjacent macrocell p-term allocator delay
Slew-rate limited delay
DS050 (v3.0) June 25, 2007
www.xilinx.com
7
Product Specification
R
XC95288XV High-Performance CPLD
XC95288XV I/O Pins
Function Macro-
BScan
TQ144 PQ208 FG256 CS280 Order Bank
Function Macro-
BScan
Block
cell
Block
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
cell
TQ144 PQ208 FG256 CS280 Order Bank
1
1
-
-
-
28
29
-
-
-
K2
K3
-
861
858
855
852
849
846
843
840
837
834
831
828
825
822
819
816
813
810
807
804
801
798
795
792
789
786
783
780
777
774
771
768
765
762
759
756
-
1
1
-
1
-
28
-
-
-
-
753
750
747
744
741
738
735
732
729
-
1
1
-
1
2
H1
H5
-
2
38
39
-
L2
L5
-
N2
P1
-
1
3
-
3
1
4
-
4
-
1
5
20
21
-
30
31
-
J1
J5
-
K4
L1
-
1
1
-
5
-
40
41
-
M1
L4
-
P2
P3
-
1
1
-
1
6
6
-
1
7
7
-
1
8
22
-
32
-
J2
J3
K1
J4
K2
-
L2
L3
L4
M1
M2
-
1
1
1
1
1
-
8
-
43
N1
P4
1
1
1
1
1
-
1
9
9
-
-
L3
R1
1
10
11
12
13
14
15
16
17
18
1
23
-
33
-
10
11
12
13
14
15
16
17
18
1
30(1) 44(1) M2(1) R3(1) 726
1
-
31
-
-
45
-
M4
P1
-
R2
R4
-
723
720
717
1
24
-
34
-
1
1
25
26
-
35
36
-
K5
L1
-
M3
M4
-
1
1
-
32(1) 46(1) M3(1) T1(1) 714
1
1
-
1
33
47
-
N2
T2
-
711
708
705
702
699
1
-
-
N4
-
1
27
-
37
-
K3
-
N1
-
1
-
-
48
-
T3
-
1
-
1
-
2
-
-
-
-
-
-
-
-
-
-
2
2
9
15
16
-
D1
G4
-
G3
G2
-
2
2
-
2
2(1)
3(1) D3(1) C2(1) 696
2
2
-
2
3
10
-
3
-
4
-
D2
-
B1
-
693
690
2
4
4
-
2
5
11
12
-
17
18
-
E1
G3
-
G1
G4
-
2
2
-
5
3(1)
5(1) E3(1) C1(1) 687
2
2
-
2
6
6
4
6
-
C2
-
D4
-
684
681
2
7
7
-
2
8
13
-
19
-
G2
F5
F1
G5
H2
-
H1
H3
H2
H4
J1
-
2
2
2
2
2
-
8
5(1)
7(1) D4(1) D3(1) 678
2
2
2
2
2
-
2
9
9
-
-
8
-
B1
E4
C1
D2
D1
E3
675
672
669
2
10
11
12
13
14
15
16
17
18
14
-
20
-
10
11
12
13
14
15
16
17
18
-
2
-
2
15
-
21
-
6(1)
9(1) E5(1) E2(1) 666
2
-
7
-
-
10
12
-
-
E2
F2
-
-
E4
F3
-
663
660
657
654
651
648
2
16
17
-
22
23
-
H4
G1
-
J2
J3
-
2
2
-
2
2
-
2
2
-
2
2
19
-
25
-
H3
-
J4
-
2
-
-
14
-
E6
-
F4
-
2
-
-
Notes:
1. Global control pin
8
www.xilinx.com
DS050 (v3.0) June 25, 2007
Product Specification
R
XC95288XV High-Performance CPLD
XC95288XV I/O Pins (continued)
Function Macro-
BScan
TQ144 PQ208 FG256 CS280 Order Bank
Function Macro-
BScan
Block
cell
Block
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
cell
TQ144 PQ208 FG256 CS280 Order Bank
5
1
-
34
-
-
-
-
645
642
639
636
633
630
627
-
1
1
-
1
-
-
62
63
-
-
R3
M6
-
-
W5
U6
-
537
534
531
528
525
522
519
516
513
510
507
504
501
498
495
492
489
486
483
480
477
474
471
468
465
462
459
456
453
450
447
444
441
438
435
432
-
1
1
-
5
2
49
50
-
R1
N3
-
U1
V1
-
2
-
5
3
3
45
5
4
-
4
-
5
5
35
-
51
54
-
P2
P4
-
U2
V3
-
1
1
-
5
46
64
66
-
T3
T4
-
V6
W6
-
1
1
-
5
6
6
-
5
7
-
7
-
5
8
38(1) 55(1) P5(1) W2(1) 624
1
1
1
1
1
-
8
-
67
-
P7
T5
N7
R7
M7
-
U7
V7
W7
T7
W8
-
1
1
1
1
1
-
5
9
-
39
-
-
56
-
T2
N5
R4
M5
-
W3
T4
U4
V4
-
621
618
615
612
609
606
603
600
597
594
591
588
585
582
579
576
573
570
567
564
561
558
555
552
9
-
5
10
11
12
13
14
15
16
17
18
1
10
11
12
13
14
15
16
17
18
1
-
69
-
5
-
5
40
-
57
-
48
70
-
5
-
5
41
43
-
58
60
-
R5
R6
-
W4
V5
-
1
1
-
-
71
72
-
T6
N8
-
U8
V8
-
1
1
-
5
49
5
-
5
44
-
61
-
N6
-
T5
-
1
-
-
73
-
T7
-
T8
-
1
-
5
-
6
-
-
-
-
-
-
-
-
-
-
6
2
135
136
-
197
198
-
A5
D6
-
D7
A6
-
2
2
-
2
130
186
187
-
E11 B10
2
2
-
6
3
3
131
A8
-
C10
-
6
4
4
-
6
5
137
138
-
199
200
-
B5
C6
-
B6
C6
-
2
2
-
5
132
188
189
-
C8
B8
-
D10
A9
-
2
2
-
6
6
6
-
6
7
7
-
6
8
139
-
201
-
A4
E7
A3
C5
A2
-
D6
A5
C5
B5
D5
-
2
2
2
2
2
-
8
133
191
-
D8
A7
E9
B7
D7
-
B9
C9
D9
A8
B8
-
2
2
2
2
2
-
6
9
9
-
6
10
11
12
13
14
15
16
17
18
140
-
202
-
10
11
12
13
14
15
16
17
18
134
192
-
6
-
-
-
-
-
-
-
-
6
-
203
-
193
-
6
-
6
142
205
B4
B4
2
2
-
194
195
-
A6
B6
-
C8
B7
-
2
2
-
6
143(1) 206(1) C4(1) C4(1) 549
6
-
-
-
-
208
-
-
B3
-
-
A3
-
546
543
540
6
6
2
-
196
-
E8
-
C7
-
2
-
Notes:
1. Global control pin
DS050 (v3.0) June 25, 2007
www.xilinx.com
9
Product Specification
R
XC95288XV High-Performance CPLD
XC95288XV I/O Pins (continued)
Function Macro-
BScan
TQ144 PQ208 FG256 CS280 Order Bank
Function Macro-
BScan
Block
cell
Block
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
cell
TQ144 PQ208 FG256 CS280 Order Bank
9
1
-
50
51
-
-
-
-
429
426
423
420
-
3
3
-
1
-
-
-
-
321
-
3
3
-
9
2
74
75
-
R8
P8
-
U9
T9
-
2
-
87
88
-
P10 W13 318
T12 V13 315
9
3
3
60
9
4
4
-
-
-
312
9
5
52
53
-
76
77
-
T8
M8
-
W10 417
V10 414
3
3
-
5
61
89
90
-
N10 U13 309
3
3
-
9
6
6
-
T13 T13
306
303
9
7
-
411
7
-
-
-
9
8
54
-
78
-
T9
P9
R9
M9
U10 408
W11 405
V11 402
U11 399
3
3
3
3
3
-
8
-
91
-
M11 W14 300
N11 T14 297
3
3
3
3
3
-
9
9
9
-
9
10
11
12
13
14
15
16
17
18
1
-
80
82
83
-
10
11
12
13
14
15
16
17
18
1
64
95
97
99
-
T14 W15 294
R12 V15 291
T15 W16 288
9
56
57
-
66
9
T10 T11 396
393
68
9
-
-
-
-
-
285
9
58
-
84
85
-
M10 W12 390
R10 V12 387
3
3
-
69
100 R14 U16 282
101 N13 W17 279
3
3
-
9
-
9
-
-
-
384
-
-
-
-
276
9
59
-
86
-
T11 T12 381
3
-
70
102 R13 W18 273
3
-
9
-
-
-
-
378
375
-
-
-
-
-
-
-
270
267
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
-
-
-
-
-
2
117 170 B11 C14 372
118 171 D11 B14 369
4
4
-
2
110
158 B13 B19 264
159 B14 B18 261
4
4
-
3
3
111
4
-
-
-
-
366
4
-
-
-
-
258
5
119 173 A11 A14 363
120 174 D10 C13 360
4
4
-
5
112
160 C13 B17 255
161 A15 A18 252
4
4
-
6
6
-
7
-
-
-
-
357
121 175 B10 B13 354
E12 A13 351
124 178 F12 A12 348
7
-
-
-
-
249
162 C12 A17 246
B12 D16 243
8
4
4
4
4
4
-
8
113
4
4
4
4
4
-
9
-
-
9
-
-
10
11
12
13
14
15
16
17
18
10
11
12
13
14
15
16
17
18
115
164 D13 C16 240
165 A14 B16 237
166 E13 A16 234
125 179
126 180
B9
C9
-
C12 345
B12 342
-
116
-
-
-
339
-
-
-
-
-
-
-
-
-
231
128 182
A9
D9
-
B11 336
C11 333
4
4
-
167 A13 C15 228
168 C11 B15 225
4
4
-
-
-
183
-
-
330
-
-
-
222
169 A12 D15 219
216
129 185 E10 A10 327
324
4
-
4
-
-
-
-
-
-
-
-
10
www.xilinx.com
DS050 (v3.0) June 25, 2007
Product Specification
R
XC95288XV High-Performance CPLD
XC95288XV I/O Pins (continued)
Function Macro-
BScan
TQ144 PQ208 FG256 CS280 Order Bank
Function Macro-
BScan
Block
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
cell
Block
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
cell
TQ144 PQ208 FG256 CS280 Order Bank
1
-
-
-
-
213
210
-
3
3
-
1
-
79
80
-
-
-
-
105
102
99
96
93
90
87
84
81
78
75
72
69
66
63
60
57
54
51
48
45
42
39
36
33
30
27
24
21
18
15
12
9
-
3
3
-
2
71
103 P13 V17
2
117 M12 P16
118 M16 P19
3
-
106 P15 U18 207
3
4
-
-
-
-
204
201
4
-
-
-
5
-
107 N14 V19
3
3
-
5
-
119 K14
N17
N18
-
3
3
-
6
-
109 R16 U19 198
6
-
120
-
L16
-
7
-
-
-
-
195
192
189
186
183
7
-
8
74
110 N15 T16
M15 T17
3
3
3
3
3
-
8
81
-
121 K13
N19
N16
M19
3
3
3
3
3
-
9
-
-
9
-
K15
L12
10
11
12
13
14
15
16
17
18
1
-
111 M13 T18
112 P16 T19
10
11
12
13
14
15
16
17
18
1
82
83
85
-
122
75
123 K16 M17
-
113 N16 R18 180
177
114 M14 R16 174
125
J14
M16
-
-
-
-
-
-
126
127
-
-
J15
J13
-
76
3
3
-
86
87
-
L19
L18
-
3
3
-
77
115
L15 R19 171
-
-
-
-
168
165
162
159
78
116
L13
P17
3
-
88
-
128
-
J16
-
L17
-
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2
-
100
-
144 F15 G19 156
145 E15 G16 153
4
4
-
2
91
92
-
131 K12
L16
K18
-
4
4
-
3
3
133
-
J12
-
4
-
-
-
150
147
144
141
138
135
132
129
126
123
120
117
114
111
108
4
5
101
102
-
146 F13
F19
4
4
-
5
93
94
-
134 H15
135 H14
K17
K16
-
4
4
-
6
147 D16 F18
6
7
-
-
-
7
-
-
8
103
-
148 F14
F17
4
4
4
4
4
-
8
95
-
136 G16
H13
J19
J18
J17
J16
H19
-
4
4
4
4
4
-
9
-
C16 F16
9
-
10
11
12
13
14
15
16
17
18
104
105
-
149 E14 E19
150 D15 E17
151 G12 E18
10
11
12
13
14
15
16
17
18
96
97
98
-
137 G15
138 H16
139 F16
-
-
-
-
-
-
106
107
-
152 C15 E16
154 D14 D18
4
4
-
-
140 H12 H18
4
4
-
-
142 E16
H17
-
-
-
-
-
-
-
6
-
155 B16 D17
4
-
-
143 G14 H16
3
4
-
-
-
-
-
-
-
-
-
0
DS050 (v3.0) June 25, 2007
www.xilinx.com
11
Product Specification
R
XC95288XV High-Performance CPLD
XC95288XV Global, JTAG and Power Pins
Pin Type
I/O/GCK1
I/O/GCK2
I/O/GCK3
I/O/GTS1
I/O/GTS2
I/O/GTS3
I/O/GTS4
I/O/GSR
TCK
TQ144
PQ208
44
46
55
7
FG256
M2
CS280
30
R3
32
M3
T1
38
P5
W2
5
D4
D3
6
9
E5
E2
2
3
D3
C2
3
5
E3
C1
143
206
98
94
176
96
C4
C4
67
P12
R11
A10
N12
T15
TDI
TDO(1)
63
122
U14
D13
U15
TMS
65
VCCINT 2.5V
8, 42, 84, 141
11, 59, 124, 153, 204 F4, G6, H6, J6, K6, F7, L7,
E1, F2, N3, U5, W9, V9,
F8., L8, F9, L9, F10, L10, U12, V16, R17, M18, G18,
G11, H11, J11, K11
D19, C18, A15, A11, D8,
A4
VCCIO1
VCCIO2
VCCIO3
VCCIO4
37
1
53, 65
1, 26
K4, L6, P6
N4, V2, T6
A7, C3, F1, K1
C7, D5, F3, F6
55, 73
109, 127
79, 92, 105
L11, L14, N9, P11
C10, F11, D12, G13
T10, V14, V18, P18
132, 157, 172, 181,
184
K19, G17, C19, D14, D12,
D11
GND
18, 29, 36, 47, 62, 72, 2, 13, 24, 27, 42, 52,
A1, T1, B2, R2, C3, P3, E5, F5, G5, H5, J5, K5, L5,
89, 90, 99, 108, 114,
123, 144
68, 81, 93, 104, 108,
129, 130, 141, 156,
163, 177, 190, 207
G7, H7, J7, K7, G8, H8,
J8, K8, G9, H9, J9, K9,
G10, H10, J10, K10, C14, R13, R14, R15, P15, N15,
P14, B15, R15, A16, T16 M15, L15, K15, J15, H15,
G15, F15, E15, E14, E13,
M5, N5, P5, R5, R6, R7,
R8, R9, R10, R11, R12,
E12, E11, E10, E9, E8, E7,
E6
No Connects
-
-
-
A1, W1, U3, W19, U17,
A19, C17, A2, B3, B2
Notes:
1. TDO voltage is controlled by VCCIO4
.
12
www.xilinx.com
DS050 (v3.0) June 25, 2007
Product Specification
R
XC95288XV High-Performance CPLD
Device Part Marking and Ordering Combination Information
R
Device Type
Package
XC95xxxXV
TQ144
This line not
related to device
part number
Speed
7C
Operating Range
1
Sample package with part marking.
Speed
Device Ordering and
(pin-to-pin
delay)
Pkg.
Symbol
No. of
Pins
Operating
Range(1)
Part Marking Number
XC95288XV-6TQ144C
XC95288XV-6PQ208C
XC95288XV-6FG256C
XC95288XV-6CS280C
XC95288XV-7TQ144C
XC95288XV-7PQ208C
XC95288XV-7FG256C
XC95288XV-7CS280C
XC95288XV-7TQ144I
XC95288XV-7PQ208I
XC95288XV-7FG256I
XC95288XV-7CS280I
XC95288XV-10TQ144C
XC95288XV-10PQ208C
XC95288XV-10FG256C
XC95288XV-10CS280C
XC95288XV-10TQ144I
XC95288XV-10PQ208I
XC95288XV-10FG256I
XC95288XV-10CS280I
Notes:
Package Type
6 ns
6 ns
TQ144 144-pin
PQ208 208-pin
FG256 256-ball
CS280 280-ball
TQ144 144-pin
PQ208 208-pin
FG256 256-ball
CS280 280-pin
TQ144 144-pin
PQ208 208-pin
FG256 256-ball
CS280 280-pin
TQ144 144-pin
PQ208 208-pin
FG256 256-ball
CS280 280-ball
TQ144 144-pin
PQ208 208-pin
FG256 256-ball
CS280 280-ball
Thin Quad Flat Pack
Plastic Quad Flat Package
Plastic Fineline Ball Grid Array
Chipscale Package
C
C
C
C
C
C
C
C
I
6 ns
6 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
Thin Quad Flat Pack
Plastic Quad Flat Package
Plastic Fineline Ball Grid Array
Chipscale Package
Thin Quad Flat Pack
Plastic Quad Flat Package
Plastic Fineline Ball Grid Array
Chipscale Package
I
I
I
Thin Quad Flat Pack
C
C
C
C
I
Plastic Quad Flat Package
Plastic Fineline Ball Grid Array
Chipscale Package
Thin Quad Flat Pack
Plastic Quad Flat Package
Plastic Fineline Ball Grid Array
Chipscale Package
I
I
I
1. C = Commercial: TA = 0° to +70°C; I = Industrial: TA = –40° to +85°C
2. Some packages available in Pb-free option. See Xilinx Packaging for more information.
DS050 (v3.0) June 25, 2007
www.xilinx.com
13
Product Specification
R
XC95288XV High-Performance CPLD
Revision History
Date
Version
1.0
Revision
09/28/98
12/10/98
2/5/99
Original creation of data sheet.
Revision of tables.
1.1
1.2
Updated pinouts to reflect BG256 (replaces BG352).
Add -7 speed and CS280 package.
6/7/99
1.3
4/11/00
01/29/01
1.4
Updated AC specifications, added bank information to pinout tables.
2.0
Added -5 performance specification, deleted -6; changed BG256 package to FG256 package.
Updated ICC vs. Frequency Figure 1.
05/15/01
08/27/01
06/24/02
2.1
2.2
2.3
Updated ICC formula, Recommended Operation Conditions, -5 AC Characteristics and Internal
Timing Parameters
Changed VCCIO 3.3V from 3.13 to 3.0 (min), 3.46 to 3.60 (max); DC characteristics: IIL - added
"low" current, IIH - changed to "Input leakage high current"; Internal Timing: -5 TAOI from 6.5 to 5.9.
Updated ICC equation on page 1. Updated Figure 3: AC Load Circuit 1.8V parameters. Added
second test condition and max measurement to IIH DC Characteristics. Added Part Marking
Information to Ordering Information. Changed to Preliminary. Changed -5 speed to -6 speed;
added -7 Industrial.
05/27/03
08/21/03
04/15/05
06/25/07
2.4
2.5
2.6
3.0
Updated TSOL from 260 to 220oC. Updated Device Part Marking.
Updated Package Device Marking Pin 1 orientation.
Added TAPRPW specification to AC Characteristics. Added IOSTANDARD information.
Notice of discontinuance.
14
www.xilinx.com
DS050 (v3.0) June 25, 2007
Product Specification
相关型号：
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