XC9536-7VQ44C [XILINX]
XC9536 In-System Programmable CPLD; XC9536在系统可编程CPLD
| 型号： | XC9536-7VQ44C |
| 厂家： | 
XILINX, INC |
| 描述： | XC9536 In-System Programmable CPLD |
| 文件： | 总7页 (文件大小：63K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
9
1
XC9536 In-System Programmable
CPLD
1
1*
December 4, 1998 (Version 5.0)
Product Specification
Features
Power Management
•
•
5 ns pin-to-pin logic delays on all pins
to 100 MHz
Power dissipation can be reduced in the XC9536 by config-
uring macrocells to standard or low-power modes of opera-
tion. Unused macrocells are turned off to minimize power
dissipation.
f
CNT
•
•
•
36 macrocells with 800 usable gates
Up to 34 user I/O pins
5 V in-system programmable (ISP)
Operating current for each design can be approximated for
specific operating conditions using the following equation:
-
-
Endurance of 10,000 program/erase cycles
Program/erase over full commercial voltage and
temperature range
I
(mA) =
CC
MC
•
•
Enhanced pin-locking architecture
Flexible 36V18 Function Block
(1.7) + MC (0.9) + MC (0.006 mA/MHz) f
HP LP
Where:
-
90 product terms drive any or all of 18 macrocells
within Function Block
MC
= Macrocells in high-performance mode
HP
-
Global and product term clocks, output enables, set
and reset signals
MC = Macrocells in low-power mode
LP
MC = Total number of macrocells used
f = Clock frequency (MHz)
•
•
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
Figure 1 shows a typical calculation for the XC9536 device.
•
•
•
•
•
•
•
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design protection
High-drive 24 mA outputs
(83)
3.3 V or 5 V I/O capability
Advanced CMOS 5V FastFLASH technology
Supports parallel programming of more than one
XC9500 concurrently
(50)
(50)
•
Available in 44-pin PLCC, 44-pin VQFP, and 48-pin
CSP packages
(30)
Description
The XC9536 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of two
36V18 Function Blocks, providing 800 usable gates with
propagation delays of 5 ns. See Figure 2 for the architec-
ture overview.
0
50
100
Clock Frequency (MHz)
X5920
Figure 1: Typical I
vs. Frequency For XC9536
CC
December 4, 1998 (Version 5.0)
1
XC9536 In-System Programmable CPLD
3
JTAG
In-System Programming Controller
1
JTAG Port
Controller
36
Function
18
18
Block 1
I/O
Macrocells
1 to 18
I/O
I/O
I/O
36
Function
Block 2
Macrocells
1 to 18
I/O
Blocks
I/O
I/O
I/O
I/O
3
I/O/GCK
I/O/GSR
I/O/GTS
1
2
X5919
Figure 2: XC9536 Architecture
Note: Function Block outputs (indicated by the bold line) drive the I/O Blocks directly
2
December 4, 1998 (Version 5.0)
XC9536 In-System Programmable CPLD
Absolute Maximum Ratings
Symbol
Parameter
Value
Units
V
V
V
V
Supply voltage relative to GND
-0.5 to 7.0
CC
IN
DC input voltage relative to GND
-0.5 to V
+ 0.5
V
CC
Voltage applied to 3-state output with respect to GND
Storage temperature
-0.5 to V
+ 0.5
V
TS
CC
T
T
-65 to +150
+260
°C
°C
STG
SOL
Max soldering temperature (10 s @ 1/16 in = 1.5 mm)
Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods
of time may affect device reliability.
1
Recommended Operating Conditions
Symbol
CCINT
Parameter
Min
Max
Units
V
V
Supply voltage for internal logic and input buffer
4.75
(4.5)
5.25
(5.5)
V
Supply voltage for output drivers for 5 V operation
Supply voltage for output drivers for 3.3 V operation
Low-level input voltage
4.75 (4.5)
5.25 (5.5)
3.6
V
V
V
V
V
CCIO
3.0
0
V
V
V
0.80
IL
IH
O
High-level input voltage
2.0
0
V
+0.5
CCINT
V
Output voltage
CCIO
Note 1. Numbers in parenthesis are for industrial-temperature range versions.
Endurance Characteristics
Symbol
Parameter
Min
20
Max
Units
Data Retention
Program/Erase Cycles
-
-
Years
t
DR
10,000
Cycles
N
PE
December 4, 1998 (Version 5.0)
3
XC9536 In-System Programmable CPLD
DC Characteristics Over Recommended Operating Conditions
Symbol
OH
Parameter
Test Conditions
Min
Max
Units
V
Output high voltage for 5 V operation
I
V
= -4.0 mA
= Min
2.4
V
OH
CC
Output high voltage for 3.3 V operation I
= -3.2 mA
= Min
2.4
V
V
OH
V
CC
V
Output low voltage for 5 V operation
Output low voltage for 3.3 V operation
Input leakage current
I
V
= 24 mA
= Min
0.5
0.4
OL
OL
CC
I
= 10 mA
= Min
V
OL
V
V
V
V
V
V
CC
I
I
= Max
CC
±10.0
±10.0
10.0
µA
µA
pF
mA
IL
IH
= GND or V
IN
CC
CC
I/O high-Z leakage current
I/O capacitance
= Max
CC
= GND or V
IN
C
= GND
IN
IN
f = 1.0 MHz
I
Operating Supply Current
(low power mode, active)
V = GND, No load
f = 1.0 MHz
CC
I
30 (Typ)
AC Characteristics
XC9536-5 XC9536-6 XC9536-7 XC9536-10 XC9536-15
Min Max Min Max Min Max Min Max Min Max
Symbol
Parameter
Units
t
t
t
t
f
f
t
t
t
t
t
t
t
t
I/O to output valid
5.0
6.0
7.5
10.0
15.0 ns
PD
SU
H
I/O setup time before GCK
I/O hold time after GCK
GCK to output valid
3.5
0.0
3.5
0.0
4.5
0.0
6.0
0.0
8.0
0.0
ns
ns
4.0
4.0
4.5
6.0
8.0
ns
CO
1
16-bit counter frequency
100.0
100.0
100.0
0.5
83.3
83.3
0.5
66.7
66.7
2.0
55.6
55.6
4.0
MHz
MHz
ns
CNT
2
Multiple FB internal operating frequency 100.0
I/O setup time before p-term clock input 0.5
SYSTEM
PSU
PH
I/O hold time after p-term clock input
P-term clock to output valid
GTS to output valid
3.0
3.0
4.0
4.0
4.0
ns
7.0
5.0
5.0
9.0
9.0
7.0
5.0
5.0
9.0
9.0
8.5
5.5
5.5
9.5
9.5
10.0
6.0
12.0 ns
11.0 ns
11.0 ns
14.0 ns
14.0 ns
ns
PCO
OE
GTS to output disable
6.0
OD
Product term OE to output enabled
Product term OE to output disabled
GCK pulse width (High or Low)
10.0
10.0
POE
POD
WLH
4.0
4.0
4.0
4.5
5.5
Note: 1. fCNT is the fastest 16-bit counter frequency available.
fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG
2. fSYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs.
.
4
December 4, 1998 (Version 5.0)
XC9536 In-System Programmable CPLD
V
TEST
R
1
Output Type
V
V
R
R
C
L
CCIO
TEST
1
2
Device Output
5.0 V
3.3 V
5.0 V
3.3 V
160 Ω
260 Ω
120 Ω
360 Ω
35 pF
35 pF
R
C
L
2
X5906
Figure 3: AC Load Circuit
Internal Timing Parameters
XC9536-5 XC9536-6 XC9536-7 XC9536-10 XC9536-15
Min Max Min Max Min Max Min Max Min Max
Symbol
Parameter
Units
Buffer Delays
t
t
t
t
t
t
Input buffer delay
GCK buffer delay
1.5
1.5
4.0
5.0
2.0
0.0
1.5
1.5
4.0
5.0
2.0
0.0
2.5
1.5
4.5
5.5
2.5
0.0
3.5
2.5
6.0
6.0
3.0
0.0
4.5
3.0
7.5
ns
ns
ns
IN
GCK
GSR
GTS
OUT
EN
GSR buffer delay
GTS buffer delay
11.0 ns
Output buffer delay
4.5
0.0
ns
ns
Output buffer enable/disable delay
Product Term Control Delays
t
t
t
Product term clock delay
Product term set/reset delay
Product term 3-state delay
3.0
1.0
5.5
3.0
1.0
5.5
3.0
2.0
4.5
3.0
2.5
3.5
2.5
3.0
5.0
ns
ns
ns
PTCK
PTSR
PTTS
Internal Register and Combinatorial delays
t
t
t
t
t
t
t
Combinatorial logic propagation delay
Register setup time
0.5
1.5
0.5
1.0
3.0
ns
ns
ns
ns
ns
ns
ns
PDI
SUI
HI
2.5
1.0
2.5
1.0
1.5
3.0
2.5
3.5
3.5
4.5
Register hold time
Register clock to output valid time
Register async. S/R to output delay
0.5
6.0
0.5
6.0
0.5
6.5
0.5
7.0
0.5
8.0
COI
AOI
RAI
LOGI
Register async. S/R recovery before clock 5.0
Internal logic delay
5.0
7.5
10.0
10.0
1.0
9.0
1.0
9.0
2.0
2.5
3.0
tLOGILP Internal low power logic delay
10.0
11.0
11.5 ns
Feedback Delays
t
FastCONNECT matrix feeback delay
6.0
6.0
8.0
9.5
11.0 ns
F
Time Adders
3
t
t
Incremental Product Term Allocator delay
Slew-rate limited delay
0.8
3.5
0.8
3.5
1.0
4.0
1.0
4.5
1.0
5.0
ns
ns
PTA
SLEW
Note: 3. tPTA is multiplied by the span of the function as defined in the family data sheet.
December 4, 1998 (Version 5.0)
5
XC9536 In-System Programmable CPLD
XC9536 I/O Pins
Function
Block
BScan
Order
Function
Block
BScan
Order
Macrocell PC44 VQ44 CS48
Notes
Macrocell PC44 VQ44 CS48
Notes
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
3
40
41
43
42
44
2
D6
C7
B7
C6
B6
A6
A7
C5
B5
A4
B4
A3
B2
B1
C2
C3
D2
-
105
102
99
96
93
90
87
84
81
78
75
72
69
66
63
60
57
54
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
2
1
39
38
36
37
34
33
32
31
30
29
28
27
23
22
21
20
19
-
D7
E5
E6
E7
F6
G7
G6
F5
G5
F4
G4
E3
F2
G1
F1
E2
E1
-
51
48
45
42
39
36
33
30
27
24
21
18
15
12
9
44
42
43
40
39
38
37
36
35
34
33
29
28
27
26
25
-
3
5
[1]
[1]
[1]
3
[1]
4
4
4
5
6
5
[1]
[1]
6
8
6
7
7
1
7
8
9
3
8
9
11
12
13
14
18
19
20
22
24
–
5
9
10
11
12
13
14
15
16
17
18
6
10
11
12
13
14
15
16
17
18
7
8
12
13
14
16
18
–
6
3
0
Note: [1] Global control pin
Note: [1] Global control pin
XC9536 Global, JTAG and Power Pins
Pin Type
I/O/GCK1
I/O/GCK2
I/O/GCK3
I/O/GTS1
I/O/GTS2
I/O/GSR
TCK
PC44
VQ44
43
CS48
B7
5
6
44
B6
7
1
A7
42
36
E6
40
34
F6
39
33
G7
17
11
A1
TDI
15
9
B3
TDO
30
24
G2
TMS
16
10
A2
V
5 V
21,41
32
15,35
26
C1,F7
G3
CCINT
3.3 V/5 V
V
CCIO
GND
23,10,31
—
17,4,25
—
A5, D1, F3
No Connects
C4, D3, D4, E4
6
December 4, 1998 (Version 5.0)
XC9536 In-System Programmable CPLD
Ordering Information
XC9536 -5 PC 44 C
Device Type
Temperature Range
Number of Pins
Package Type
Speed
Speed Options
Packaging Options
-15
-10
-7
-6
-5
15 ns pin-to-pin delay
10 ns pin-to-pin delay
7.5 ns pin-to-pin delay
6 ns pin-to-pin delay
5 ns pin-to-pindelay
PC44 44-Pin Plastic Leaded Chip Carrier (PLCC)
VQ44 44-Pin Thin Quad Pack (VQFP)
CS48 48-Pin Chip Scale Package (CSP)
Temperature Options
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
Component Availability
Pins
Type
Code
44
48
Plastic
PLCC
Plastic
VQFP
Plastic
CSP
PC44
C,I
C,I
C,I
C
VQ44
C,I
C,I
C,I
C
CS48
–15
–10
–7
-
C
C
-
XC9536
–6
–5
C
C
C
C = Commercial (0°C to +70°C), I = Industrial (–40°C to +85°C)
Revision Control
Date
Reason
6/3/98
11/2/98
12/04/98
Revise datasheet to reflect new CSP package pinouts & ordering code.
Revise datasheet to reflect new AC characteristics and Internal Timing Parameters.
Revise datasheet to remove PCI compliancy statement and remove tLF
.
December 4, 1998 (Version 5.0)
7
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