XC9536XL-10VQG44Q [XILINX]
Flash PLD, 10ns, CMOS, PQFP44, PLASTIC, VQFP-44;
| 型号： | XC9536XL-10VQG44Q |
| 厂家： | 
XILINX, INC |
| 描述： | Flash PLD, 10ns, CMOS, PQFP44, PLASTIC, VQFP-44 |
| 文件： | 总22页 (文件大小：183K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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XC9500XL High-Performance
CPLD Automotive IQ Product
Family
R
0
0
DS108 (v1.0) June 17, 2002
Advance Product Specification
Features
Description
•
Guaranteed to meet full electrical specifications over
TA = –40°C to +125°C
The XC9500XL 3.3V CPLD Automotive IQ product family is
targeted for leading-edge, high-performance, low-voltage
automotive (–40°C to +125°C) applications.
•
•
•
System frequency up to 100 MHz (10 ns)
Available in small footprint packages
Power Estimation
Optimized for high-performance 3.3V systems
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in the XC9500XL device can be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
-
5V tolerant I/O pins accept 5V, 3.3V, and 2.5V
signals — ideal for multi-voltage system interfacing
and level shifting
-
Technology: 0.35µm CMOS process
•
Advanced system features
-
In-system programmable enabling higher system
reliability through reduced handling and reducing
production programming times
For a general estimate of ICC, the following equation may be
used:
-
Superior pin-locking and routability with
FastCONNECT™ II switch matrix allowing for
multiple design iterations without board re-spins
Input hysteresis on all user and boundary-scan pin
inputs to reduce noise on input signals
Bus-hold circuitry on all user pin inputs which
reduces cost associated with pull-up resistors and
reduces bus loading
ICC (mA) = MCHP(0.5) + MCLP(0.3) + MC(0.0045 mA/MHz) f
where:
-
-
MCHP = Macrocells in high-performance (default)
mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
-
Full IEEE Standard 1149.1 boundary-scan (JTAG)
for in-system device testing
·
Fast concurrent programming
This calculation is based on typical operating conditions
using a pattern of 16-bit up/down counters in each Function
Block with no output loading. The actual ICC value varies
with the design application and should be verified during
normal system operation.
•
Slew rate control on individual outputs for reducing EMI
generation
.
Table 1: XC9500XL Device Family
Device
Macrocells
Usable Gates
800
Registers
fSYSTEM (MHz)
XC9536XL
XC9572XL
36
72
36
72
100
100
1,600
Table 2: XC9500XL Packages and User I/O Pins (not including four dedicated JTAG pins)
Device
VQ44
VQ64
36
TQ100
XC9536XL
XC9572XL
34
-
-
52
72
© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
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3
JTAG
In-System Programming Controller
54
JTAG Port
Controller
Function
Block 1
18
18
18
18
I/O
I/O
I/O
I/O
Macrocells
1 to 18
54
54
54
Function
Block 2
Macrocells
1 to 18
I/O
Blocks
I/O
I/O
I/O
I/O
Function
Block 3
Macrocells
1 to 18
3
I/O/GCK
Function
Block N
1
I/O/GSR
Macrocells
1 to 18
2 or 4
I/O/GTS
DS054_01_042001
Figure 1: XC9500XL Architecture
Note: Function block outputs (indicated by the bold lines) drive the I/O blocks directly.
tion across multiple density options in a given package
footprint.
Family Overview
The FastFLASH XC9500XL family is a 3.3V CPLD family
targeted for high-performance applications in leading-edge
communications, computing, and automotive systems,
where high device reliability and low power dissipation is
important. Each XC9500XL device supports in-system pro-
gramming (ISP) and the full IEEE 1149.1 (JTAG) bound-
ary-scan, allowing superior debug and design iteration
capability for small form-factor packages. The XC9500XL
family is designed to work closely with the Xilinx Virtex,
Spartan-XL and XC4000XL FPGA families, allowing system
designers to partition logic optimally between fast interface
circuitry and high-density general purpose logic. As shown
in Table 1, logic density of the XC9500XL devices ranges
from 800 to 1,600 usable gates with 36 to 72 registers,
respectively. Multiple package options and associated I/O
capacity are shown in Table 1. The XC9500XL family mem-
bers are fully pin-compatible, allowing easy design migra-
The XC9500XL architectural features address the require-
ments of in-system programmability. Enhanced pin-locking
capability avoids costly board rework. In-system program-
ming throughout the full commercial operating range and a
high programming endurance rating provide worry-free
reconfigurations of system field upgrades. Extended data
retention supports longer and more reliable system operat-
ing life.
Advanced system features include output slew rate control
and user-programmable ground pins to help reduce system
noise. Each user pin is compatible with 5V, 3.3V, and 2.5V
inputs, and the outputs may be configured for 3.3V or 2.5V
operation. The XC9500XL devices exhibit symmetric full
3.3V output voltage swing to allow balanced rise and fall
times.
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XC9500XL High-Performance CPLD Automotive IQ Product Family
Function Block
Architecture Description
Each XC9500XL device is a subsystem consisting of multi-
ple Function Blocks (FBs) and I/O Blocks (IOBs) fully inter-
connected by the FastCONNECT II switch matrix. The IOB
provides buffering for device inputs and outputs. Each FB
provides programmable logic capability with extra wide 54
inputs and 18 outputs. The FastCONNECT II switch matrix
connects all FB outputs and input signals to the FB inputs.
For each FB, up to 18 outputs (depending on package
pin-count) and associated output enable signals drive
directly to the IOBs. See Figure 1
Each Function Block, as shown in Figure 2 is comprised of
18 independent macrocells, each capable of implementing
a combinatorial or registered function. The FB also receives
global clock, output enable, and set/reset signals. The FB
generates 18 outputs that drive the FastCONNECT switch
matrix. These 18 outputs and their corresponding output
enable signals also drive the IOB.
Logic within the FB is implemented using a sum-of-products
representation. Fifty-four inputs provide 108 true and com-
plement signals into the programmable AND-array to form
90 product terms. Any number of these product terms, up to
the 90 available, can be allocated to each macrocell by the
product term allocator.
Macrocell 1
Product
Term
Allocators
Programmable
AND-Array
18
To FastCONNECT II
Switch Matrix
From
FastCONNECT II
Switch Matrix
54
18
OUT
To I/O Blocks
18
PTOE
Macrocell 18
1
3
Global Global
Set/Reset Clocks
DS054_02_042101
Figure 2: XC9500XL Function Block
The product term allocator associated with each macrocell
selects how the five direct terms are used.
Macrocell
Each XC9500XL macrocell may be individually configured
for a combinatorial or registered function. The macrocell
and associated FB logic is shown in Figure 3.
The macrocell register can be configured as a D-type or
T-type flip-flop, or it may be bypassed for combinatorial
operation. Each register supports both asynchronous set
and reset operations. During power-up, all user registers
are initialized to the user-defined preload state (default to 0
if unspecified)
Five direct product terms from the AND-array are available
for use as primary data inputs (to the OR and XOR gates) to
implement combinatorial functions, or as control inputs
including clock, clock enable, set/reset, and output enable.
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XC9500XL High-Performance CPLD Automotive IQ Product Family
.
54
Global
Global
Set/Reset Clocks
3
Additional
Product
Terms
(from other
macrocells)
Product Term Set
1
0
To
FastCONNECTII
Switch Matrix
S
D/T
Q
CE
Product
Term
Allocator
Product Term Clock Enable
R
Product Term Clock
Product Term Reset
OUT
To
I/O Blocks
PTOE
Product Term OE
Additional
Product
Terms
(from other
macrocells)
DS054_03_042101
Figure 3: XC9500XL Macrocell Within Function Block
All global control signals are available to each individual
macrocell, including clock, set/reset, and output enable sig-
nals. As shown in Figure 4, the macrocell register clock
originates from either of three global clocks or a product
term clock. Both true and complement polarities of the
selected clock source can be used within each macrocell. A
GSR input is also provided to allow user registers to be set
to a user-defined state.
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Macrocell
Product Term Set
S
D/T
CE
Product Term Clock
Product Term Reset
R
I/O/GSR
Global Set/Reset
I/O/GCK1
I/O/GCK2
Global Clock 1
Global Clock 2
I/O/GCK3
Global Clock 3
DS05404_042101
Figure 4: Macrocell Clock and Set/Reset Capability
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Note that the incremental delay affects only the product
terms in other macrocells. The timing of the direct product
terms is not changed.
Product Term Allocator
The product term allocator controls how the five direct prod-
uct terms are assigned to each macrocell. For example, all
five direct terms can drive the OR function as shown in
Figure 5.
Product Term
Allocator
Product Term
Allocator
Macrocell
Product Term
Logic
Product Term
Allocator
DS054_05_042101
Figure 5: Macrocell Logic Using Direct Product Term
The product term allocator can re-assign other product
terms within the FB to increase the logic capacity of a mac-
rocell beyond five direct terms. Any macrocell requiring
additional product terms can access uncommitted product
terms in other macrocells within the FB. Up to 15 product
terms can be available to a single macrocell with only a
small incremental delay of tPTA, as shown in Figure 6.
Macrocell Logic
With 15
Product Terms
Product Term
Allocator
DS054_06_042101
Figure 6: Product Term Allocation With 15 Product
Terms
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The product term allocator can re-assign product terms
from any macrocell within the FB by combining partial sums
of products over several macrocells, as shown in Figure 7.
In this example, the incremental delay is only 2*TPTA. All 90
product terms are available to any macrocell, with a maxi-
mum incremental delay of 8*TPTA.
Product Term
Allocator
Macrocell Logic
With 2
Product Terms
Product Term
Allocator
Product Term
Allocator
Macrocell Logic
With 18
Product Terms
Product Term
Allocator
DS054_07 _042101
Figure 7: Product Term Allocation Over Several
Macrocells
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XC9500XL High-Performance CPLD Automotive IQ Product Family
The internal logic of the product term allocator is shown in
Figure 8.
From Upper
Macrocell
To Upper
Macrocell
Product Term
Allocator
Product Term Set
Global Set/Reset
1
0
S
D/T
CE
Q
Global Clocks
R
Product Term Clock
Product Term Reset
Global Set/Reset
Product Term OE
From Lower
Macrocell
To Lower
Macrocell
DS054_08_042101
Figure 8: Product Term Allocator Logic
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sponding to user pin inputs) and all FB outputs drive the
FastCONNECT II matrix. Any of these (up to a fan-in limit of
54) may be selected to drive each FB with a uniform delay.
FastCONNECT II Switch Matrix
The FastCONNECT II Switch Matrix connects signals to the
FB inputs, as shown in Figure 9. All IOB outputs (corre-
FastCONNECT II
Switch Matrix
Function Block
I/O Block
(54)
18
D/T Q
I/O
Function Block
I/O Block
(54)
18
D/T Q
I/O
DS054_09_042101
Figure 9: FastCONNECT II Switch Matrix
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buffer, output driver, output enable selection multiplexer,
and user programmable ground control. See Figure 10 for
details.
I/O Block
The I/O Block (IOB) interfaces between the internal logic
and the device user I/O pins. Each IOB includes an input
To other
Macrocells
I/O Block
To Fast CONNECT
Switch Matrix
Macrocell
Bus-Hold
I/O
OUT
(Inversion in
AND-array)
User-
Programmable
Ground
1
0
Product Term OE
PTOE
Slew Rate
Control
I/O/GTS1
Global OE 1
Global OE 2
I/O/GTS2
DS108_10_053102
Figure 10: I/O Block and Output Enable Capability
The input buffer is compatible with 5V CMOS, 5V TTL, 3.3V
CMOS, and 2.5V CMOS signals. The input buffer uses the
internal 3.3V voltage supply (VCCINT) to ensure that the
input thresholds are constant and do not vary with the
VCCIO voltage. Each input buffer provides input hysteresis
(50 mV typical) to help reduce system noise for input signals
with slow rise or fall edges.
Each output driver can also be configured for slew-rate lim-
ited operation. Output edge rates may be slowed down to
reduce system noise (with an additional time delay of tSLEW
)
under user control. See Figure 12.
The output enable may be generated from one of four
options: a product term signal from the macrocell, any of the
global output enable signals (GTS), always “1,” or always
“0.” There are two global output enables for devices with 72
or fewer macrocells, and four global output enables for
devices with 144 or more macrocells. Any selected output
enable signal may be inverted locally at each pin output to
provide maximal design flexibility.
Each output driver is designed to provide fast switching with
minimal power noise. All output drivers in the device may be
configured for driving either 3.3V CMOS levels (which are
compatible with 5V TTL levels as well) or 2.5V CMOS levels
by connecting the device output voltage supply (VCCIO) to a
3.3V or 2.5V voltage supply. Figure 11 shows how the
XC9500XL device can be used in 3.3V only systems and
mixed voltage systems with any combination of 5V, 3.3V
and 2.5V power supplies.
Each IOB provides user programmable ground pin capabil-
ity. This allows device I/O pins to be configured as additional
ground pins in order to force otherwise unused pins to a low
voltage state, as well as provide for additional device
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XC9500XL High-Performance CPLD Automotive IQ Product Family
grounding capability. This grounding of the pin is achieved
by internal logic that forces a logic low output regardless of
the internal macrocell signal, so the internal macrocell logic
is unaffected by the programmable ground pin capability.
drive no higher than VCCIO to prevent overdriving signals
when interfacing to 2.5V components.
When the device is not in valid user operation, the bus-hold
circuit defaults to an equivalent 50k ohm pull-up resistor in
order to provide a known repeatable device state. This
occurs when the device is in the erased state, in program-
ming mode, in JTAG INTEST mode, or during initial
power-up. A pull-down resistor (1k ohm) may be externally
added to any pin to override the default RBH resistance to
force a low state during power-up or any of these other
modes.
Each IOB also provides for bus-hold circuitry (also called a
“keeper”)that is active during valid user operation. The
bus-hold feature eliminates the need to tie unused pins
either high or low by holding the last known state of the input
until the next input signal is present. The bus-hold circuit
drives back the same state via a nominal resistance (RBH
)
of 50k ohms. See Figure 13. Note the bus-hold output will
5V CMOS
5V CMOS
5V
5V
3.3V
3.3V
2.5V
0V
0V
5V TTL or
5V TTL or
5V
V
V
V
V
CCIO
CCINT
CCIO
CCINT
5V
2.5V CMOS
2.5V
3.3V CMOS, 5V TTL
3.3V
XC9500XL
CPLD
XC9500XL
CPLD
0V
3.3V CMOS or
3.3V
0V
3.3V CMOS or
3.3V
OUT
IN
IN
OUT
0V
0V
0V
0V
GND
GND
2.5V CMOS
2.5V
2.5V CMOS
2.5V
0V
0V
(a)
(b)
DS054_11_042101
Figure 11: XC9500XL Devices in (a) 3.3V only and (b) Mixed 5V/3.3V/2.5V Systems
ture to adapt to unexpected changes. The XC9500XL
devices incorporate architectural features that enhance the
ability to accept design changes while maintaining the same
pinout.
5V Tolerant I/Os
The I/Os on each XC9500XL device are fully 5V tolerant
even though the core power supply is 3.3 volts. This allows
5V CMOS signals to connect directly to the XC9500XL
inputs without damage. In addition, the 3.3V VCCINT power
supply can be applied before or after 5V signals are applied
to the I/Os. In mixed 5V/3.3V/2.5V systems, the user pins,
the core power supply (VCCINT), and the output power sup-
ply (VCCIO) may have power applied in any order. This
makes the XC9500XL devices immune to power supply
sequencing problems.
The XC9500XL architecture provides for superior pin-lock-
ing characteristics with a combination of large number of
routing switches in the FastCONNECT II switch matrix, a
54-wide input Function Block, and flexible, bi-directional
product term allocation within each macrocell. These fea-
tures address design changes that require adding or chang-
ing internal routing, including additional signals into existing
equations, or increasing equation complexity, respectively.
Xilinx proprietary ESD circuitry and high impedance initial
state permit hot plugging cards using these devices.
For extensive design changes requiring higher logic capac-
ity than is available in the initially chosen device, the new
design may be able to fit into a larger pin-compatible device
using the same pin assignments. The same board may be
Pin-Locking Capability
The capability to lock the user defined pin assignments dur-
ing design iteration depends on the ability of the architec-
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XC9500XL High-Performance CPLD Automotive IQ Product Family
used with a higher density device without the expense of
board rework.
Output
Voltage
Output
Voltage
V
CCIO
Standard
T
Slew-Rate Limited
Slew-Rate Limited
T
SLEW
SLEW
1.5V
1.5V
Standard
Time
Time
0
0
(b)
(a)
DS054_12_042101
Figure 12: Output Slew-Rate Control For (a) Rising and (b) Falling Outputs
External Programming
Set to PIN
XC9500XL devices can also be programmed by the Xilinx
HW-130 device programmer as well as third-party program-
mers. This provides the added flexibility of using pre-pro-
grammed devices during manufacturing, with an in-system
programmable option for future enhancements and design
changes.
during valid user
operation
Drive to
Level
V
CCIO
0
PIN
R
BH
Reliability and Endurance
All XC9500XL CPLDs provide a minimum endurance level
of 10,000 in-system program/erase cycles and a minimum
data retention of 20 years. Each device meets all functional,
performance, and data retention specifications within this
endurance limit.
I/O
DS054_13_042101
IEEE 1149.1 Boundary-Scan (JTAG)
Figure 13: Bus-Hold Logic
XC9500XL devices fully support IEEE 1149.1 bound-
ary-scan (JTAG). EXTEST, SAMPLE/PRELOAD, BYPASS,
USERCODE, INTEST, IDCODE, HIGHZ and CLAMP
instructions are supported in each device. Additional
instructions are included for in-system programming opera-
tions.
In-System Programming
One or more XC9500XL devices can be daisy chained
together and programmed in-system via a standard 4-pin
JTAG protocol, as shown in Figure 14. In-system program-
ming offers quick and efficient design iterations and elimi-
nates package handling. The Xilinx development system
provides the programming data sequence using a Xilinx
download cable, a third-party JTAG development system,
JTAG-compatible board tester, or a simple microprocessor
interface that emulates the JTAG instruction sequence.
Design Security
XC9500XL devices incorporate advanced data security fea-
tures which fully protect the programming data against
unauthorized reading or inadvertent device erasure/repro-
gramming. Table 3 shows the four different security settings
available.
All I/Os are 3-stated and pulled high by the bus-hold cir-
cuitry during in-system programming. If a particular signal
must remain low during this time, then a pulldown resistor
may be added to the pin.
The read security bits can be set by the user to prevent the
internal programming pattern from being read or copied.
When set, they also inhibit further program operations but
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allow device erase. Erasing the entire device is the only way
to reset the read security bit.
vated when the device needs to be reprogrammed with a
valid pattern with a specific sequence of JTAG instructions.
The write security bits provide added protection against
accidental device erasure or reprogramming when the
JTAG pins are subject to noise, such as during system
power-up. Once set, the write-protection may be deacti-
Table 3: Data Security Options
Read Security
Default
Set
Read Allowed
Read Inhibited
Default
Set
Program/Erase
Allowed
Program Inhibited
Erase Allowed
Read Allowed
Read Inhibited
Program/Erase
Allowed
Program/Erase
Inhibited
(a)
(b)
X5902
Figure 14: System Programming Operation (a) Solder Device to PCB and (b) Program Using Download Cable
Low Power Mode
Timing Model
All XC9500XL devices offer a low-power mode for individual
macrocells or across all macrocells. This feature allows the
device power to be significantly reduced.
The uniformity of the XC9500XL architecture allows a sim-
plified timing model for the entire device. The basic timing
model, shown in Figure 15, is valid for macrocell functions
that use the direct product terms only, with standard power
setting, and standard slew rate setting. Table 4 shows how
each of the key timing parameters is affected by the product
term allocator (if needed), low-power setting, and slew-lim-
ited setting.
Each individual macrocell may be programmed in
low-power mode by the user. Performance-critical parts of
the application can remain in standard power mode, while
other parts of the application may be programmed for
low-power operation to reduce the overall power dissipation.
Macrocells programmed for low-power mode incur addi-
tional delay (tLP) in pin-to-pin combinatorial delay as well as
register setup time. Product term clock to output and prod-
uct term output enable delays are unaffected by the macro-
cell power-setting.
The product term allocation time depends on the logic span
of the macrocell function, which is defined as one less than
the maximum number of allocators in the product term path.
If only direct product terms are used, then the logic span is
0. The example in Figure 6 shows that up to 15 product
terms are available with a span of 1. In the case of Figure 7,
the 18 product term function has a span of 2.
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Detailed timing information may be derived from the full tim-
ing model shown in Figure 16. The values and explanations
for each parameter are given in the individual device data
sheets.
Combinatorial
Logic
Combinatorial
D/T Q
Logic
T
CO
Setup Time = T
Clock to Out Time = T
Propagation Delay = T
PD
SU
(b)
CO
(a)
T
PSU
Combinatorial
Logic
D/T Q
Combinatorial
Logic
P-Term Clock
Path
D/T Q
T
PCO
Setup Time = T
Clock to Out Time = T
Internal System Cycle Time = T
SYSTEM
PSU
PCO
(c)
(d)
DS054_15_042101
Figure 15: Basic Timing Model
T
F
T
S*T
PTA
T
LOGILP
SLEW
T
PDI
T
T
LOGI
IN
D/T
Q
T
OUT
T
T
SUI COI
T
HI
T
T
PTCK
PTSR
CE
T
AOI
RAI
T
T
EN
T
GCK
GSR
SR
T
T
PTTS
Macrocell
T
GTS
DS054_16_042101
Figure 16: Detailed Timing Model
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XC9500XL family as well as other CPLD and FPGA fami-
lies.
Power-Up Characteristics
The XC9500XL devices are well behaved under all operat-
ing conditions. During power-up each XC9500XL device
employs internal circuitry which keeps the device in the qui-
escent state until the VCCINT supply voltage is at a safe level
(approximately 2.5V). During this time, all device pins and
JTAG pins are disabled and all device outputs are disabled
with the pins weakly pulled high, as shown in Table 5. When
the supply voltage reaches a safe level, all user registers
become initialized (typically within 200 µs), and the device is
immediately available for operation, as shown in Figure 17.
The Alliance Series includes CPLD and FPGA implementa-
tion technology as well as all necessary libraries and inter-
faces for Alliance partner EDA solutions.
FastFLASH Technology
A 0.35 micron feature size CMOS Flash process is used to fabri-
cate all XC9500XL devices. The FastFLASH process provides
high performance logic capability, fast programming times,
and superior reliability and endurance ratings.
If the device is in the erased state (before any user pattern
is programmed), the device outputs remain disabled with
weak pull-up. The JTAG pins are enabled to allow the device
to be programmed at any time. All devices are shipped in
the erased state from the factory.
V
CCINT
2.5V
(Typ)
If the device is programmed, the device inputs and outputs
take on their configured states for normal operation. The
JTAG pins are enabled to allow device erasure or bound-
ary-scan tests at any time.
0V
Development System Support
No
Power
Quiescent
State
Quiescent
State
No
Power
User Operation
The XC9500XL family and associated in-system program-
ming capabilities are fully supported in either software solu-
tions available from Xilinx.
Initialization of User Registers
DS054_17_042101
Figure 17: Device Behavior During Power-up
The Foundation Series is an all-in-one development system
containing schematic entry, HDL (VHDL, Verilog, and
ABEL), and simulation capabilities. It supports the
Table 4: Timing Model Parameters
Output
Product Term
Macrocell
Low-Power Setting
Slew-Limited
Setting
Parameter
TPD
Description
Propagation Delay
Allocator(1)
+ TPTA * S
+ TPTA * S
-
+ TLP
+ TLP
-
+ TSLEW
TSU
Global Clock Setup Time
–
TCO
Global Clock-to-output
+ TSLEW
TPSU
Product Term Clock Setup Time
Product Term Clock-to-output
Internal System Cycle Period
+ TPTA * S
-
+ TLP
-
-
TPCO
+ TSLEW
-
TSYSTEM
Notes:
+ TPTA * S
+ TLP
1. S = the logic span of the function, as defined in the text.
Table 5: XC9500XL Device Characteristics
Device Circuitry
IOB Bus-Hold
Quiescent State
Pull-up
Erased Device Operation
Valid User Operation
Bus-Hold
Pull-up
Disabled
Disabled
Disabled
Enabled
Device Outputs
Disabled
As Configured
As Configured
As Configured
Enabled
Device Inputs and Clocks
Function Block
Disabled
Disabled
JTAG Controller
Disabled
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XC9500XL High-Performance CPLD Automotive IQ Product Family
(1)
Absolute Maximum Ratings
Symbol
VCC
VIN
Description
Min.
–0.5
–0.5
–0.5
–65
-
Max.
4.0
Units
V
Supply voltage relative to GND
Input voltage relative to GND(2)
Voltage applied to 3-state output(2)
Storage temperature (ambient)
Junction temperature
5.5
V
VTS
5.5
V
TSTG
TJ
+150
+150
oC
oC
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
2. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the
device pins may undershoot to –2.0 V or overshoot to +7.0V, provided this over- or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA.
3. For soldering guidelines, see the Package Infomation on the Xilinx website.
Recommended Operating Conditions
Symbol
Parameter
Min
–40
3.0
3.0
2.3
0
Max
+125
3.6
Units
°C
V
TA
Ambient temperature
VCCINT
VCCIO
Supply voltage for internal logic and input buffers
Supply voltage for output drivers for 3.3V operation
Supply voltage for output drivers for 2.5V operation
Low-level input voltage
3.6
V
2.7
V
VIL
VIH
VO
0.80
5.5
V
High-level input voltage
2.0
0
V
Output voltage
VCCIO
V
Quality and Reliability Characteristics
Symbol
Parameter
Min
20
Max
Units
TDR
Data Retention
Program/Erase Cycles (Endurance)
-
-
Years
NPE
10,000
Cycles
DC Characteristic Over Recommended Operating Conditions
Symbol
Parameter
Test Conditions
IOH = –4.0 mA
OH = –500 µA
Min
Max
Units
V
VOH
Output high voltage for 3.3V outputs
Output high voltage for 2.5V outputs
Output low voltage for 3.3V outputs
Output low voltage for 2.5V outputs
Input leakage current
2.4
-
I
90% VCCIO
-
V
VOL
IOL = 8.0 mA
-
-
-
-
-
0.4
0.4
±10
±10
10
V
IOL = 500 µA
V
IIL
IIH
VCC = Max, VIN = GND or VCC
VCC = Max, VIN = GND or VCC
VIN = GND, f = 1.0 MHz
µA
µA
pF
mA
mA
I/O high-Z leakage current
I/O capacitance
CIN
ICC
Operating supply current
(low power mode, active)
VI = GND, No load
f = 1.0 MHz
XC9536XL
XC9572XL
10 (Typical)
20 (Typical)
16
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XC9500XL High-Performance CPLD Automotive IQ Product Family
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XL device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
PTHS = average number of high-speed product terms
per macrocell
MCLP = # macrocells in low power configuration
PTLP = average number of low power product terms per
macrocell
f = maximum clock frequency
MCTOG = average % of flip-flops toggling per clock
(~12%)
For a general estimate of ICC, the following equation may be
used:
This calculation was derived from laboratory measurements
of an XC9500XL part filled with 16-bit counters and allowing
a single output (the LSB) to be enabled. The actual ICC
value varies with the design application and should be veri-
fied during normal system operation.
ICC(mA) = MCHS(0.175*PTHS + 0.345) + MCLP(0.052*PTLP
+ 0.272) + 0.04 * MCTOG(MCHS +MCLP)* f
where:
MCHS = # macrocells in high-speed configuration
AC Characteristics
-10
Symbol
Parameter
Min
Max
10.0
-
Units
ns
TPD
TSU
TH
I/O to output valid
-
I/O setup time before GCK
I/O hold time after GCK
GCK to output valid
6.5
ns
0
-
ns
TCO
-
5.8
100.0
-
ns
fSYSTEM Multiple FB internal operating frequency
-
MHz
ns
TPSU
TPH
I/O setup time before p-term clock input
I/O hold time after p-term clock input
P-term clock output valid
2.1
4.4
-
ns
TPCO
TOE
-
10.2
7.0
7.0
11.0
11.0
14.5
15.3
-
ns
GTS to output valid
-
ns
TOD
GTS to output disable
-
ns
TPOE
TPOD
TAO
Product term OE to output enabled
Product term OE to output disabled
GSR to output valid
-
-
ns
ns
-
ns
TPAO
TWLH
TPLH
P-term S/R to output valid
-
ns
GCK pulse width (High or Low)
P-term clock pulse width (High or Low)
4.5
7.0
ns
-
ns
V
TEST
R
1
Output Type
V
CCIO
V
R
1
R
2
C
TEST
L
Device Output
3.3V
2.5V
3.3V
2.5V
320 Ω
250 Ω
360 Ω
660 Ω
35 pF
35 pF
C
L
R
2
DS058_03_081500
Figure 18: AC Load Circuit
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XC9500XL High-Performance CPLD Automotive IQ Product Family
Internal Timing Parameters
-10
Symbol
Parameter
Min
Max
Units
Buffer Delays
TIN
Input buffer delay
-
-
-
-
-
-
3.5
1.8
4.5
7.0
3.0
0
ns
ns
ns
ns
ns
ns
TGCK
TGSR
TGTS
TOUT
TEN
GCK buffer delay
GSR buffer delay
GTS buffer delay
Output buffer delay
Output buffer enable/disable delay
Product Term Control Delays
TPTCK
TPTSR
TPTTS
Product term clock delay
-
-
-
2.7
1.8
7.5
ns
ns
ns
Product term set/reset delay
Product term 3-state delay
Internal Register and Combinatorial Delays
TPDI
TSUI
Combinatorial logic propagation delay
Register setup time
-
3.0
3.5
3.0
3.5
-
1.7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
THI
Register hold time
TECSU
TECHO
TCOI
Register clock enable setup time
Register clock enable hold time
Register clock to output valid time
Register async. S/R to output delay
Register async. S/R recover before clock
Internal logic delay
-
-
1.0
7.0
TAOI
-
TRAI
10.0
-
TLOGI
TLOGILP
1.8
7.3
Internal low power logic delay
-
Feedback Delays
TF
Fast CONNECT II feedback delay
-
4.2
ns
Time Adders
TPTA
Incremental product term allocator delay
Slew-rate limited delay
-
-
1.0
4.5
ns
ns
TSLEW
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XC9500XL High-Performance CPLD Automotive IQ Product Family
XC9536XL I/O Pins
Function
Block
Macro-
cell
BScan
Order
Function
Block
Macro-
cell
BScan
Order
VQ44
40
41
43(1)
42
44(1)
2
VQ64
9
VQ44
39
VQ64
8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
105
102
99
96
93
90
87
84
81
78
75
72
69
66
63
60
57
54
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
2
51
48
45
42
39
36
33
30
27
24
21
18
15
12
9
10
15(1)
38
36(1)
7
5(1)
3
3
4
11
4
37
6
5
16(1)
19
17(1)
5
34(1)
33(1)
32
2(1)
64(1)
63
62
61
60
57
56
50
48
45
44
43
49
6
6
7
1(1)
7
8
3
20
8
31
9
5
22
9
30
10
11
12
13
14
15
16
17
18
6
24
10
11
12
13
14
15
16
17
18
29
7
25
28
8
27
27
12
13
14
16
18
-
33
23
35
22
36
21
38
20
6
42
19
3
39
-
0
Notes:
1. Global control pin.
XC9536XL Global, JTAG and Power Pins
Pin Type
I/O/GCK1
I/O/GCK2
I/O/GCK3
I/O/GTS1
I/O/GTS2
I/O/GSR
TCK
VQ44
VQ64
43
15
44
16
1
17
36
5
34
2
64
33
11
30
TDI
9
24
28
TDO
53
TMS
10
29
V
CCINT 3.3V
CCIO 2.5V/3.3V
GND
15, 35
26
3, 37
55
V
4, 17, 25
-
21, 41, 54
No Connects
1, 4, 12, 13, 14, 18, 23, 26, 31, 32, 34, 40, 46, 47, 51, 52, 58, 59
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XC9500XL High-Performance CPLD Automotive IQ Product Family
XC9572XL I/O Pins
Function
Block
BScan
Order
Function
Block
BScan
Order
Macrocell
VQ64
-
TQ100
16
Macrocell
VQ64
-
TQ100
41
32
49
50
35
53
54
37
42
60
52
61
63
55
56
64
58
59
65
67
71
72
68
76
77
70
66
81
74
82
85
78
89
86
90
79
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
2
213
210
207
204
201
198
195
192
189
186
183
180
177
174
171
168
165
162
159
156
153
150
147
144
141
138
135
132
129
126
123
120
117
114
111
108
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
1
2
105
102
99
96
93
90
87
84
81
78
75
72
69
66
63
60
57
54
51
48
45
42
39
36
33
30
27
24
21
18
15
12
9
8
13
22
31
32
24
34
-
3
12
13
9
18
3
4
20
4
5
14
5
6
10
-
15
6
7
25
7
8
11
15(1)
18
16(1)
23
-
17(1)
19
-
17
22(1)
8
25
27
39
33
40
-
9
9
10
11
12
13
14
15
16
17
18
1
28
10
11
12
13
14
15
16
17
18
1
23(1)
33
36
27(1)
35
36
42
38
-
29
39
20
-
30
40
-
87
-
2
60
58
59
61
62
-
94
2
43
46
47
44
49
-
3
91
3
4
93
4
5
95
5
6
96
3(2)
6
7
7
8
63
64(1)
1
97
8
45
-
9
99(1)
1
4(1)
9
10
11
12
13
14
15
16
17
18
10
11
12
13
14
15
16
17
18
51
48
52
-
2(1)
4
6
-
8
9(3)
5(3)
50
56
-
6
11
-
10
6
7
12
57
-
3
-
92
0
Notes:
1. Global control pin.
2. GTS1 for TQ100.
3. GTS1 VQ64.
20
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XC9500XL High-Performance CPLD Automotive IQ Product Family
XC9572XL Global, JTAG and Power Pins
Pin Type
I/O/GCK1
I/O/GCK2
I/O/GCK3
I/O/GTS1
I/O/GTS2
I/O/GSR
TCK
VQ64
TQ100
15
22
16
23
17
27
5
3
2
4
64
99
30
48
TDI
28
45
TDO
53
83
47
TMS
29
3, 37
V
CCINT 3.3V
CCIO 2.5V/3.3V
GND
5, 57, 98
V
26, 55
14, 21, 41, 54
-
26, 38, 51, 88
21, 31, 44, 62, 69, 75, 84, 100
2, 7, 19, 24, 34, 43, 46, 73, 80
No Connects
Component Availability
Pins
Type
Code
44
64
100
Plastic VQFP
Plastic VQFP
Plastic TQFP
VQ44
VQ64
Q
TQ100
XC9536XL
XC9572XL
-10
-10
Q
-
-
Q
Q
Notes:
1. Q = Automotive IQ (TA = –40°C to +125°C).
Ordering Information
Example:
Device Type
Speed Grade
XC9572XL -10 TQ 100 Q
Temperature Range
Number of Pins
Package Type
Device Ordering Options
Device
Speed
Package
Temperature
XC9536XL -10 10 ns pin-to-pin delay VQ44 44-pin Quad Flat Pack (VQFP)
Q = Automotive IQ TA = –40°C to +125°C
XC9572XL
VQ64 64-pin Quad Flat Pack (VQFP)
TQ100 100-pin Thin Quad Flat Pack (TQFP)
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Revision History
The following table shows the revision history for this document.
Date
Version
Revision
06/17/02
1.0
Initial Xilinx release
22
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Advance Product Specification
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