XC9536XL-7VQ64C [XILINX]
XC9536XL High PerformanceCPLD; XC9536XL高PerformanceCPLD
| 型号： | XC9536XL-7VQ64C |
| 厂家： | 
XILINX, INC |
| 描述： | XC9536XL High PerformanceCPLD |
| 文件： | 总7页 (文件大小：312K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
R
XC9536XL High Performance
CPLD
DS058 (v1.2) June 25, 2001
Preliminary Product Specification
cations and computing systems. It is comprised of two
54V18 Function Blocks, providing 800 usable gates with
propagation delays of 5 ns. See Figure 2 for architecture
overview.
Features
•
•
•
•
5 ns pin-to-pin logic delays
System frequency up to 178 MHz
36 macrocells with 800 usable gates
Available in small footprint packages
Power Estimation
-
-
-
-
44-pin PLCC (34 user I/O pins)
44-pin VQFP (34 user I/O pins)
48-pin CSP (36 user I/O pins)
64-pin VQFP (36 user I/O pins)
Power dissipation in CPLDs can vary substantially depend•
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XL device may be configured for low-power
mode (from the default high-performance mode). In addi•
tion, unused product-terms and macrocells are automati•
cally deactivated by the software to further conserve power.
•
•
Optimized for high-performance 3.3V systems
-
-
Low power operation
5V tolerant I/O pins accept 5 V, 3.3V, and 2.5V
signals
For a general estimate of I , the following equation may be
CC
-
-
3.3V or 2.5V output capability
Advanced 0.35 micron feature size CMOS
FastFLASH™ technology
used:
I
(mA) = MC (0.5) + MC (0.3) + MC(0.0045 mA/MHz) f
HP LP
CC
Where:
MC = Macrocells in high-performance (default) mode
Advanced system features
-
-
In-system programmable
HP
Superior pin-locking and routability with
FastCONNECT II™ switch matrix
Extra wide 54-input Function Blocks
Up to 90 product-terms per macrocell with
individual product-term allocation
Local clock inversion with three global and one
product-term clocks
MC = Macrocells in low-power mode
LP
MC = Total number of macrocells used
f = Clock frequency (MHz)
-
-
This calculation is based on typical operating conditions
using a pattern of 16-bit up/down counters in each Function
-
Block with no output loading. The actual I
value varies
CC
-
-
Individual output enable per output pin
Input hysteresis on all user and boundary-scan pin
inputs
with the design application and should be verified during
normal system operation.
Figure 1 shows the above estimation in a graphical form.
-
-
Bus-hold circuitry on all user pin inputs
Full IEEE Standard 1149.1 boundary-scan (JTAG)
60
•
•
•
•
Fast concurrent programming
178 MHz
50
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
40
30
-
Endurance exceeding 10,000 program/erase
cycles
125 MHz
-
-
20 year data retention
ESD protection exceeding 2,000V
20
•
Pin-compatible with 5V-core XC9536 device in the
44-pin PLCC package and the 48-pin CSP package
10
Description
0
100
200
250
50
150
The XC9536XL is a 3.3V CPLD targeted for high-perfor•
mance, low-voltage applications in leading-edge communi•
Clock Frequency (MHz)
DS058_01_061101
Figure 1: Typical I vs. Frequency for XC9536XL
CC
© 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS058 (v1.2) June 25, 2001
www.xilinx.com
1
Preliminary Product Specification
1-800-255-7778
R
XC9536XL High Performance CPLD
3
JTAG
In-System Programming Controller
1
JTAG Port
Controller
54
Function
18
18
Block 1
I/O
Macrocells
1 to 18
I/O
I/O
I/O
54
Function
Block 2
Macrocells
1 to 18
I/O
Blocks
I/O
I/O
I/O
I/O
3
I/O/GCK
I/O/GSR
I/O/GTS
1
2
DS058_02_081500
Figure 2: XC9536XL Architecture
Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.
2
www.xilinx.com
DS058 (v1.2) June 25, 2001
1-800-255-7778
Preliminary Product Specification
R
XC9536XL High Performance CPLD
Absolute Maximum Ratings
Symbol
Description
Value
–0.5 to 4.0
–0.5 to 5.5
–0.5 to 5.5
–65 to +150
+260
Units
V
Supply voltage relative to GND
V
V
V
CC
(1)
V
Input voltage relative to GND
IN
(1)
V
Voltage applied to 3-state output
Storage temperature (ambient)
TS
o
T
T
C
STG
o
Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm)
Junction temperature
C
SOL
o
T
+150
C
J
Notes:
1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the
device pins may undershoot to –2.0 V or overshoot to +7.0V, provided this over- or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Recommended Operation Conditions
Symbol
Parameter
Min
3.0
3.0
3.0
2.3
0
Max
3.6
Units
o
o
V
Supply voltage for internal logic
and input buffers
Commercial T = 0 C to 70 C
V
V
V
V
V
V
V
CCINT
A
o
o
Industrial T = –40 C to +85 C
3.6
A
V
Supply voltage for output drivers for 3.3V operation
Supply voltage for output drivers for 2.5V operation
Low-level input voltage
3.6
CCIO
2.7
V
0.80
5.5
IL
V
High-level input voltage
2.0
0
IH
V
Output voltage
V
CCIO
O
Quality and Reliability Characteristics
Symbol
Parameter
Min
20
Max
Units
T
Data Retention
-
-
-
Years
Cycles
Volts
DR
N
Program/Erase Cycles (Endurance)
Electrostatic Discharge (ESD)
10,000
2,000
PE
V
ESD
DC Characteristic Over Recommended Operating Conditions
Symbol
Parameter
Output high voltage for 3.3V outputs
Output high voltage for 2.5V outputs
Output low voltage for 3.3V outputs
Output low voltage for 2.5V outputs
Input leakage current
Test Conditions
Min
2.4
90%
Max
Units
V
I
I
I
I
= –4.0 mA
= –500 µA
= 8.0 mA
= 500 µA
V
V
OH
OH
OH
OL
OL
V
CCIO
V
-
-
-
0.4
0.4
V
OL
V
I
V
V
= Max
CC
±10
µA
IL
= GND or V
IN
CC
CC
I
I/O high-Z leakage current
I/O capacitance
V
V
= Max
-
-
±10
10
µA
pF
IH
CC
= GND or V
IN
C
V
= GND
IN
IN
f = 1.0 MHz
I
Operating supply current
(low power mode, active)
V = GND, No load
f = 1.0 MHz
10 (Typical)
mA
CC
I
DS058 (v1.2) June 25, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
3
R
XC9536XL High Performance CPLD
AC Characteristics
XC9536XL-5
XC9536XL-7
XC9536XL-10
Symbol
Parameter
Min
Max
5.0
-
Min
Max
7.5
-
Min
Max Units
T
T
I/O to output valid
-
-
-
10.0
-
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PD
SU
I/O setup time before GCK
I/O hold time after GCK
3.7
4.8
6.5
T
0
-
0
-
0
-
H
T
GCK to output valid
-
3.5
178.6
-
-
4.5
125
-
-
5.8
100
-
CO
f
Multiple FB internal operating frequency
I/O setup time before p-term clock input
I/O hold time after p-term clock input
P-term clock output valid
-
-
-
SYSTEM
T
1.7
1.6
2.1
PSU
T
2.0
-
3.2
-
4.4
-
PH
T
-
5.5
4.0
4.0
7.0
7.0
10.0
10.5
-
-
7.7
5.0
5.0
9.5
9.5
12.0
12.6
-
-
10.2
7.0
7.0
11.0
11.0
14.5
15.3
-
PCO
T
GTS to output valid
-
-
-
OE
OD
T
GTS to output disable
-
-
-
T
T
Product term OE to output enabled
Product term OE to output disabled
GSR to output valid
-
-
-
-
-
-
POE
POD
T
-
-
-
AO
T
P-term S/R to output valid
GCK pulse width (High or Low)
P-term clock pulse width (High or Low)
-
-
-
PAO
WLH
T
2.8
5.0
4.0
6.5
4.5
7.0
T
-
-
-
PLH
V
TEST
R
1
Output Type
V
V
TEST
R
1
R
2
C
CCIO
L
Device Output
3.3V
2.5V
3.3V
2.5V
320 Ωꢀ
250 Ωꢀ
360 Ωꢀ
660 Ωꢀ
35 pF
35 pF
C
L
R
2
DS058_03_081500
Figure 3: AC Load Circuit
4
www.xilinx.com
DS058 (v1.2) June 25, 2001
1-800-255-7778
Preliminary Product Specification
R
XC9536XL High Performance CPLD
Internal Timing Parameters
XC9536XL-5
XC9536XL-7
XC9536XL-10
Symbol
Parameter
Min
Max
Min
Max
Min
Max Units
Buffer Delays
T
Input buffer delay
GCK buffer delay
GSR buffer delay
GTS buffer delay
-
-
-
-
-
-
1.5
1.1
2.0
4.0
2.0
0
-
-
-
-
-
-
2.3
1.5
3.1
5.0
2.5
0
-
-
-
-
-
-
3.5
1.8
4.5
7.0
3.0
0
ns
ns
ns
ns
ns
ns
IN
T
GCK
GSR
GTS
OUT
T
T
T
Output buffer delay
T
Output buffer enable/disable delay
EN
Product Term Control Delays
T
T
T
Product term clock delay
Product term set/reset delay
Product term 3-state delay
-
-
-
1.6
1.0
5.5
-
-
-
2.4
1.4
7.2
-
-
-
2.7
1.8
7.5
ns
ns
ns
PTCK
PTSR
PTTS
Internal Register and Combinatorial Delays
T
T
Combinatorial logic propagation delay
Register setup time
-
2.3
1.4
2.3
1.4
-
0.5
-
2.6
2.2
2.6
2.2
-
1.3
-
3.0
3.5
3.0
3.5
-
1.7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PDI
SUI
-
-
-
-
-
-
T
Register hold time
HI
T
T
Register clock enable setup time
Register clock enable hold time
Register clock to output valid time
Register async. S/R to output delay
Register async. S/R recover before clock
Internal logic delay
-
-
-
ECSU
ECHO
-
-
-
T
0.4
6.0
0.5
6.4
1.0
7.0
COI
T
-
-
-
AOI
T
5.0
-
7.5
-
10.0
-
RAI
T
1.0
5.0
1.4
6.4
1.8
7.3
LOGI
T
Internal low power logic delay
-
-
-
LOGILP
Feedback Delays
FastCONNECT II feedback delay
Time Adders
T
-
1.9
-
3.5
-
4.2
ns
F
T
Incremental product term allocator delay
Slew-rate limited delay
-
-
0.7
3.0
-
-
0.8
4.0
-
-
1.0
4.5
ns
ns
PTA
T
SLEW
DS058 (v1.2) June 25, 2001
www.xilinx.com
5
Preliminary Product Specification
1-800-255-7778
R
XC9536XL High Performance CPLD
XC9536XL I/O Pins
Function Macro
BScan
PC44 VQ44 CS48 VQ64 Order
Function Macro
BScan
Block
cell
Block
cell
PC44 VQ44 CS48 VQ64 Order
1
1
2
40
41
D6
C7
9
105
102
99
96
93
90
87
84
81
78
75
72
69
66
63
60
57
54
2
1
1
39
38
D7
E5
8
51
48
45
42
39
36
33
30
27
24
21
18
15
12
9
1
2
3
10
2
2
44
7
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
1
3
5
43
42
B7
C6
15
11
2
3
42
43
36
37
E6
E7
5
1
4
4
2
4
6
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
1
5
6
44
B6
A6
16
19
2
5
40
39
34
33
F6
2
(1)
(1)
(1)
(1)
1
6
8
2
2
6
G7
64
63
(1)
(1)
(1)
(1)
1
7
7
1
A7
17
2
7
38
32
G6
1
8
9
3
5
C5
B5
A4
B4
A3
B2
B1
C2
C3
D2
D3
20
22
24
25
27
33
35
36
38
42
39
2
8
37
36
35
34
33
29
28
27
26
25
-
31
30
29
28
27
23
22
21
20
19
-
F5
G5
F4
G4
E3
F2
G1
F1
E2
E1
E4
62
61
60
57
56
50
48
45
44
43
49
1
9
11
12
13
14
18
19
20
22
24
-
2
9
1
10
11
12
13
14
15
16
17
18
6
2
10
11
12
13
14
15
16
17
18
1
7
2
1
8
2
1
12
13
14
16
18
-
2
1
2
1
2
1
2
6
1
2
3
1
2
0
Notes:
1. Global control pin.
XC9536XL Global, JTAG and Power Pins
Pin Type
I/O/GCK1
I/O/GCK2
I/O/GCK3
I/O/GTS1
I/O/GTS2
I/O/GSR
TCK
PC44
VQ44
43
CS48
B7
VQ64
5
15
6
44
B6
16
7
1
A7
17
42
36
E6
5
40
34
F6
2
64
39
33
G7
17
11
A1
30
TDI
15
9
B3
28
TDO
30
24
G2
53
TMS
16
21, 41
32
10
A2
29
VCCINT 3.3V
VCCIO 2.5V/3.3V
GND
15, 35
26
C1, F7
G3
3, 37
55
10, 23, 31
-
4, 17, 25
-
A5, D1, F3
C4, D4
21, 41, 54
No Connects
1, 4, 12, 13, 14, 18,
23, 26, 31, 32, 34, 40,
46, 47, 51, 52, 58, 59
6
www.xilinx.com
1-800-255-7778
DS058 (v1.2) June 25, 2001
Preliminary Product Specification
R
XC9536XL High Performance CPLD
Ordering Information
Example:
XC9536XL -5 PC 44 C
Device Type
Temperature Range
Number of Pins
Package Type
Speed Grade
Device Ordering Options
Speed
Package
Temperature
-10 10 ns pin-to-pin delay
-7 7.5 ns pin-to-pin delay
-5 5 ns pin-to-pin delay
-4 4 ns pin-to-pin delay
PC44 44-pin Plastic Lead Chip Carrier (PLCC)
VQ44 44-pin Quad Flat Pack (VQFP)
CS48 48-pin Chip Scale Package
VQ64 64-pin Quad Flat Pack (VQFP)
C = Commercial
I = Industrial
T = 0°C to +70°C
A
T = –40°C to +85°C
A
Component Availability
Pins
44
Plastic
PLCC
PC44
C, I
44
Plastic
VQFP
VQ44
C, I
48
64
Plastic
CSP
CS48
C, I
Plastic
VQFP
VQ64
C, I
Type
Code
XC9536XL
-10
-7
C, I
C, I
C, I
C, I
-5
C
C
C
C
Notes:
o
o
o
o
1. C = Commercial (T = 0 C to +70 C); I = Industrial (T = –40 C to +85 C).
A
A
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revision
09/28/98
08/28/00
06/25/01
Initial Xilinx release.
1.1
Added VQ44 package.
1.2
Removed -4 device. Added C4 and D4 pins to CS48 No Connects in pinout table. Added
industrial availability to -7 device.
DS058 (v1.2) June 25, 2001
www.xilinx.com
7
Preliminary Product Specification
1-800-255-7778
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