XC9572-7PQ100C [XILINX]
XC9572 In-System Programmable CPLD; XC9572在系统可编程CPLD
| 型号： | XC9572-7PQ100C |
| 厂家： | 
XILINX, INC |
| 描述： | XC9572 In-System Programmable CPLD |
| 文件： | 总8页 (文件大小：67K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1
XC9572 In-System Programmable
CPLD
1
1*
December 4, 1998 (Version 3.0)
Product Specification
Features
Power Management
•
•
7.5 ns pin-to-pin logic delays on all pins
to 125 MHz
Power dissipation can be reduced in the XC9572 by config-
uring macrocells to standard or low-power modes of opera-
tion. Unused macrocells are turned off to minimize power
dissipation.
f
CNT
•
•
•
72 macrocells with 1,600 usable gates
Up to 72 user I/O pins
5 V in-system programmable (ISP)
Operating current for each design can be approximated for
specific operating conditions using the following equation:
-
-
Endurance of 10,000 program/erase cycles
Program/erase over full commercial voltage and
temperature range
I
(mA) =
CC
MC
•
•
Enhanced pin-locking architecture
Flexible 36V18 Function Block
(1.7) + MC (0.9) + MC (0.006 mA/MHz) f
HP LP
Where:
-
90 product terms drive any or all of 18 macrocells
within Function Block
MC
= Macrocells in high-performance mode
HP
-
Global and product term clocks, output enables, set
and reset signals
MC = Macrocells in low-power mode
LP
MC = Total number of macrocells used
f = Clock frequency (MHz)
•
•
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
Figure 1 shows a typical calculation for the XC9572 device.
•
•
•
•
•
•
•
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design protection
High-drive 24 mA outputs
200
3.3 V or 5 V I/O capability
Advanced CMOS 5V FastFLASH technology
Supports parallel programming of more than one
XC9500 concurrently
Available in 44-pin PLCC, 84-pin PLCC, 100-pin PQFP
and 100-pin TQFP packages
(160)
(125)
•
100
(100)
Description
(65)
The XC9572 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of four
36V18 Function Blocks, providing 1,600 usable gates with
propagation delays of 7.5 ns. See Figure 2 for the architec-
ture overview.
0
50
100
Clock Frequency (MHz)
Figure 1: Typical ICC vs. Frequency for XC9572
December 4, 1998 (Version 3.0)
1
XC9572 In-System Programmable CPLD
3
JTAG
In-System Programming Controller
1
JTAG Port
Controller
36
Function
18
18
18
18
Block 1
I/O
Macrocells
1 to 18
I/O
I/O
I/O
36
36
36
Function
Block 2
Macrocells
1 to 18
I/O
Blocks
I/O
I/O
Function
Block 3
Macrocells
1 to 18
I/O
I/O
3
I/O/GCK
I/O/GSR
I/O/GTS
Function
Block 4
1
2
Macrocells
1 to 18
X5921
Figure 2: XC9572 Architecture
Note: Function Block outputs (indicated by the bold line) drive the I/O Blocks directly
2
December 4, 1998 (Version 3.0)
XC9572 In-System Programmable CPLD
Absolute Maximum Ratings
Symbol
CC
Parameter
Value
Units
V
V
V
V
Supply voltage relative to GND
-0.5 to 7.0
DC input voltage relative to GND
-0.5 to V
+ 0.5
V
IN
CC
CC
Voltage applied to 3-state output with respect to GND
Storage temperature
-0.5 to V
+ 0.5
V
TS
T
T
-65 to +150
°C
°C
STG
SOL
Max soldering temperature (10 s @ 1/16 in = 1.5 mm)
+260
Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods
of time may affect device reliability.
1
Recommended Operation Conditions
Symbol
Parameter
Min
Max
Units
V
V
Supply voltage for internal logic and input buffer
4.75
(4.5)
5.25
(5.5)
V
CCINT
Supply voltage for output drivers for 5 V operation
Supply voltage for output drivers for 3.3 V operation
Low-level input voltage
4.75 (4.5)
5.25 (5.5)
3.6
V
V
V
V
V
CCIO
3.0
0
V
V
V
0.80
IL
IH
O
High-level input voltage
2.0
0
V
+0.5
CCINT
Output voltage
V
CCIO
Note: 1. Numbers in parenthesis are for industrial temperature range versions.
Endurance Characteristics
Symbol
Parameter
Min
20
Max
Units
Years
Cycles
Data Retention
Program/Erase Cycles
-
-
t
DR
10,000
N
PE
December 4, 1998 (Version 3.0)
3
XC9572 In-System Programmable CPLD
DC Characteristics Over Recommended Operating Conditions
Symbol
Parameter
Test Conditions
Min
Max
Units
V
Output high voltage for 5 V operation
I
V
= -4.0 mA
= Min
2.4
V
OH
OH
CC
Output high voltage for 3.3 V operation
Output low voltage for 5 V operation
Output low voltage for 3.3 V operation
Input leakage current
I
V
= -3.2 mA
= Min
2.4
V
V
OH
CC
V
I
V
= 24 mA
= Min
0.5
0.4
OL
OL
CC
I
= 10 mA
= Min
V
OL
V
V
V
V
V
V
CC
I
I
= Max
CC
±10.0
±10.0
10.0
µA
µA
pF
ma
IL
IH
= GND or V
IN
CC
CC
I/O high-Z leakage current
= Max
CC
= GND or V
IN
C
I/O capacitance
= GND
IN
IN
f = 1.0 MHz
I
Operating Supply Current
(low power mode, active)
V = GND, No load
f = 1.0 MHz
65 (Typ)
CC
I
AC Characteristics
XC9572-7
XC9572-10
XC9572-15
Symbol
Parameter
Units
Min Max Min Max Min Max
t
t
t
t
f
f
t
t
t
t
t
t
t
t
I/O to output valid
7.5
4.5
10.0
6.0
15.0
8.0
ns
ns
PD
I/O setup time before GCK
I/O hold time after GCK
4.5
0.0
6.0
0.0
8.0
0.0
SU
H
ns
GCK to output valid
ns
CO
CNT
1
16-bit counter frequency
125.0
83.3
0.5
111.1
66.7
2.0
95.2
55.6
4.0
MHz
MHz
ns
2
Multiple FB internal operating frequency
I/O setup time before p-term clock input
I/O hold time after p-term clock input
P-term clock to output valid
GTS to output valid
SYSTEM
PSU
PH
4.0
4.0
4.0
ns
8.5
5.5
5.5
9.5
9.5
10.0
6.0
12.0
11.0
11.0
14.0
14.0
ns
PCO
OE
ns
GTS to output disable
6.0
ns
OD
Product term OE to output enabled
Product term OE to output disabled
GCK pulse width (High or Low)
10.0
10.0
ns
POE
POD
WLH
ns
4.0
4.5
5.5
ns
Note: 1. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable.
fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG
.
2. f
is the internal operating frequency for general purpose system designs spanning multiple FBs.
SYSTEM
V
TEST
R
1
Output Type
V
V
R
R
C
L
CCIO
TEST
1
2
Device Output
5.0 V
3.3 V
5.0 V
3.3 V
160 Ω
260 Ω
120 Ω
360 Ω
35 pF
35 pF
R
C
L
2
X5906
Figure 3: AC Load Circuit
4
December 4, 1998 (Version 3.0)
XC9572 In-System Programmable CPLD
Internal Timing Parameters
XC9572-7
XC9572-10
XC9572-15
Symbol
Parameter
Units
Min Max Min Max Min Max
Buffer Delays
t
t
t
t
t
t
Input buffer delay
GCK buffer delay
2.5
1.5
4.5
5.5
2.5
0.0
3.5
2.5
6.0
6.0
3.0
0.0
4.5
3.0
ns
ns
ns
ns
ns
ns
IN
GCK
GSR
GTS
OUT
EN
GSR buffer delay
7.5
GTS buffer delay
11.0
4.5
Output buffer delay
Output buffer enable/disable delay
0.0
Product Term Control Delays
t
t
t
Product term clock delay
Product term set/reset delay
Product term 3-state delay
3.0
2.0
4.5
3.0
2.5
3.5
2.5
3.0
5.0
ns
ns
ns
PTCK
PTSR
PTTS
Internal Register and Combinatorial delays
t
t
t
t
t
t
t
Combinatorial logic propagation delay
Register setup time
0.5
1.0
3.0
ns
ns
ns
ns
ns
ns
ns
ns
PDI
SUI
HI
1.5
3.0
2.5
3.5
3.5
4.5
Register hold time
Register clock to output valid time
Register async. S/R to output delay
0.5
6.5
0.5
7.0
0.5
8.0
COI
AOI
RAI
LOGI
Register async. S/R recovery before clock 7.5
Internal logic delay
10.0
10.0
2.0
2.5
3.0
tLOGILP
Internal low power logic delay
10.0
11.0
11.5
Feedback Delays
t
t
FastCONNECT matrix feedback delay
Function Block local feeback delay
8.0
4.0
9.5
3.5
11.0
3.5
ns
ns
F
LF
Time Adders
3
t
t
Incremental Product Term Allocator delay
Slew-rate limited delay
1.0
4.0
1.0
4.5
1.0
5.0
ns
ns
PTA
SLEW
Note: 3. tPTA is multiplied by the span of the function as defined in the family data sheet.
December 4, 1998 (Version 3.0)
5
XC9572 In-System Programmable CPLD
XC9572 I/O Pins
Function
Block
PC
44
PC
84
PQ
100 100
TQ BScan
Function
Block
PC
44
PC
84
PQ
100 100
TQ BScan
Macrocell
Notes
Macrocell
Notes
Order
213
210
207
204
201
198
195
192
189
186
183
180
177
174
171
168
165
162
159
156
153
150
147
144
141
138
135
132
129
126
123
120
117
114
111
108
Order
105
102
99
96
93
90
87
84
81
78
75
72
69
66
63
60
57
54
51
48
45
42
39
36
33
30
27
24
21
18
15
12
9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
2
–
1
4
18
15
20
22
16
17
27
19
24
30
25
35
38
29
31
41
32
42
89
96
93
95
97
98
5
16
13
18
20
14
15
25
17
22
28
23
33
36
27
29
39
30
40
87
94
91
93
95
96
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
1
2
–
11
–
25
17
31
32
19
34
35
21
26
40
33
41
43
36
37
45
39
–
43
34
51
52
37
55
56
39
44
62
54
63
65
57
58
67
60
61
68
66
73
74
69
78
79
70
72
83
76
84
87
80
91
88
92
81
41
32
49
50
35
53
54
37
42
60
52
61
63
55
56
65
58
59
66
64
71
72
67
76
77
68
70
81
74
82
85
78
89
86
90
79
1
3
–
6
3
4
–
7
4
–
5
2
2
5
12
–
6
3
3
6
7
–
11
5
7
–
8
4
8
13
14
–
9
5
9
[1]
[1]
9
10
11
12
13
14
15
16
17
18
1
–
13
10
18
20
12
14
23
15
24
63
69
67
68
70
71
76
72
74
75
77
79
80
81
83
82
84
–
10
11
12
13
14
15
16
17
18
1
6
18
–
–
–
–
7
[1]
19
20
–
8
–
9
22
–
–
–
–
46
44
51
52
47
54
55
48
50
57
53
58
61
56
65
62
66
–
2
35
–
2
24
–
3
3
4
–
4
–
5
36
37
–
5
25
–
6
6
7
[2]
[1]
[1]
7
–
8
38
39
–
99
1
97
99
1
8
26
27
–
9
9
10
11
12
13
14
15
16
17
18
3
10
11
12
13
14
15
16
17
18
40
–
6
4
28
–
8
6
–
10
11
13
12
14
94
8
–
42
43
–
9
[3]
29
33
–
11
10
12
92
6
44
–
34
–
3
0
Notes: [1] Global control pin
[2] Global control pin GTS1 for PC84, PQ100, and TQ100
[3] Global control pin GTS1 for PC44
6
December 4, 1998 (Version 3.0)
XC9572 In-System Programmable CPLD
XC9572 Global, JTAG and Power Pins
Pin Type
PC44
PC84
PQ100
TQ100
I/O/GCK1
I/O/GCK2
I/O/GCK3
I/O/GTS1
I/O/GTS2
I/O/GSR
TCK
5
6
7
9
10
12
76
77
74
30
28
59
24
25
29
5
6
1
50
47
85
22
23
27
3
4
99
48
45
83
42
40
39
17
15
30
16
21,41
32
TDI
TDO
TMS
29
49
47
VCCINT 5 V
VCCIO 3.3 V/5 V
38,73,78
22,64
8,16,27,42,
49,60
7,59,100
28,40,53,90
2,23,33,46,64,71,
77,86
5,57,98
26,38,51,88
100,21,31,44,62,69,
75, 84
GND
10,23,31
4,9,21,26,36,45,48,
75, 82
2,7,19,24,34,43,46,
73, 80
No Connects
—
–
December 4, 1998 (Version 3.0)
7
XC9572 In-System Programmable CPLD
Ordering Information
XC9572 -7 PQ 100 C
Device Type
Speed
Temperature Range
Number of Pins
Package Type
Speed Options
-15 15 ns pin-to-pin delay
Packaging Options
PC44 44-Pin Plastic Leaded Chip Carrier (PLCC)
PC84 84-Pin Plastic Leaded Chip Carrier (PLCC)
PQ100 100-Pin Plastic Quad Flat Pack (PQFP)
TQ100 100-Pin Very Thin Quad Flat Pack (TQFP)
-10 10 ns pin-to-pin delay
-7 7.5 ns pin-to-pin delay
Temperature Options
C
I
Commercial0°C to +70°C
Industrial–40°C to +85°C
Component Availability
Pins
Type
Code
44
84
100
Plastic
PLCC
Plastic
PLCC
Plastic
PQFP
Plastic
TQFP
PC44
C(I)
C(I)
C
PC84
C(I)
C(I)
C
PQ100
C(I)
C(I)
C
TQ100
C(I)
C(I)
C
–15
–10
–7
XC9572
C = Commercial = 0° to +70°C I = Industrial = –40° to +85°C
Revision Control
Date
Revision
Update AC Characteristics and Internal Parameters
12/04/98
8
December 4, 1998 (Version 3.0)
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