XC9572XV-5TQG100C [XILINX]
Flash PLD, 5ns, 72-Cell, CMOS, PQFP100, TQFP-100;
| 型号： | XC9572XV-5TQG100C |
| 厂家： | 
XILINX, INC |
| 描述： | Flash PLD, 5ns, 72-Cell, CMOS, PQFP100, TQFP-100 |
| 文件： | 总9页 (文件大小：84K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Product Obsolete/Under Obsolescence
0
R
XC9572XV High-performance
CPLD
0
5
DS052 (v3.0) June 25, 2007
Product Specification
Note: This product is being discontinued. You cannot
order parts after May 14, 2008. Xilinx recommends replac-
ing XC9572XV devices with equivalent XC9572XL devices
in all designs as soon as possible. Recommended replace-
ments are pin compatible, however require a VCC change to
3.3V, and a recompile of the design file. In addition, there is
no 1.8V I/O support. See XCN07010 for details regarding
this discontinuation, including device replacement
recomendations for the XC9572XV CPLD.
in a XC9500XV device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
For a general estimate of ICC, the following equation may be
used:
PTOTAL = PINT + PIO = ICCINT x VCCINT + PIO
Separating internal and I/O power here is convenient
because XC9500XV CPLDs also separate the correspond-
ing power pins. PIO is a strong function of the load capaci-
tance driven, so it is handled by I = CVf. ICCINT is another
situation that reflects the actual design considered and the
internal switching speeds. An estimation expression for
ICCINT (taken from simulation) is:
Features
•
•
72 macrocells with 1,600 usable gates
Available in small footprint packages
-
-
44-pin VQFP (34 user I/O pins)
100-pin TQFP (72-user I/O pins)
•
•
Optimized for high-performance 2.5V systems
I
CCINT(mA) = MCHS(0.122 X PTHS + 0.238) + MCLP(0.042 x
-
-
Low power operation
Multi-voltage operation
PTLP + 0.171) + 0.04(MCHS + MCLP) x fMAX x MCTOG
where:
Advanced system features
-
-
In-system programmable
MCHS = # macrocells used in high speed mode
MCLP = #macrocells used in low power mode
PTHS = average p-terms used per high speed macrocell
PTLP = average p-terms used over low power macrocell
fMAX = max clocking frequency in the device
Superior pin-locking and routability with
Fast CONNECT™ II switch matrix
Extra wide 54-input Function Blocks
Up to 90 product-terms per macrocell with
individual product-term allocation
Local clock inversion with three global and one
product-term clocks
-
-
MCTOG = % macrocells toggling on each clock (12% is
frequently a good estimate
-
-
-
Individual output enable per output pin
Input hysteresis on all user and boundary-scan pin
inputs
Bus-hold ciruitry on all user pin inputs
Full IEEE Standard 1149.1 boundary-scan (JTAG)
This calculation was derived from laboratory measurements
of an XC9500XV part filled with 16-bit counters and allowing
a single output (the LSB) to be enabled. The actual ICC
value varies with the design application and should be veri-
fied during normal system operation. Figure 1 shows the
above estimation in a graphical form. For a more detailed
discussion of power consumption in this device, see Xilinx
application note XAPP361, “Planning for High Speed
XC9500XV Designs.”
-
-
•
•
•
•
Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
-
-
20 year data retention
ESD protection exceeding 2,000V
110
90
Description
70
50
30
10
The XC9572XV is a 2.5V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
cations and computing systems. It is comprised of four
54V18 Function Blocks, providing 1,600 usable gates with
propagation delays of 5 ns.
Power Estimation
0
50
100
qu
150
200
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
C
lock
F
r
e
e
ncy
(MH
z)
DS052_01_041405
© 2006, 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS052 (v3.0) June 25, 2007
www.xilinx.com
1
Product Specification
Product Obsolete/Under Obsolescence
R
XC9572XV High-performance CPLD
Figure 1: Typical ICC vs. Frequency for XC9572XV
3
JTAG
In-System Programming Controller
1
JTAG Port
Controller
54
Function
18
18
18
18
Block 1
I/O
Macrocells
1 to 18
I/O
I/O
I/O
54
54
54
Function
Block 2
Macrocells
1 to 18
I/O
Blocks
I/O
I/O
Function
Block 3
Macrocells
1 to 18
I/O
I/O
3
I/O/GCK
I/O/GSR
I/O/GTS
Function
Block 4
1
Macrocells
1 to 18
2
DS052_02_041200
Figure 2: XC9572XV Architecture (Function Block outputs (indicated by the bold line) drive the I/O Blocks directly)
The LVTTL I/O standard is a general purpose EIA/JEDEC
standard for 3.3V applications that use an LVTTL input
buffer and Push-Pull output buffer. The LVCMOS2 standard
is used in 2.5V applications.
Supported I/O Standards
Table 1: IOSTANDARD Options
IOSTANDARD
LVTTL
VCCIO
3.3V
2.5V
1.8V
XC9500XV CPLDs are also 1.8V I/O compatible. The
X25TO18 setting is provided for generating 1.8V compatible
outputs from a CPLD normally operating in a 2.5V environ-
ment. The default I/O Standard for pads without IOSTAN-
DARD attributes is LVTTL for XC9500XV devices.
LVCMOS2
X25TO18
The XC9572XV CPLD features both LVCMOS and LVTTL
I/O implementations. See Table 1 for I/O standard voltages.
2
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DS052 (v3.0) June 25, 2007
Product Specification
Product Obsolete/Under ObsolesXcCe9n57c2XeV High-performance CPLD
R
Absolute Maximum Ratings
Symbol
Description
Supply voltage relative to GND
Supply voltage for output drivers
Value
–0.5 to 2.7
–0.5 to 3.6
–0.5 to 3.6
–0.5 to 3.6
–65 to +150
+150
Units
V
VCC
VCCIO
VIN
V
Input voltage relative to GND(1)
Voltage applied to 3-state output(1)
Storage temperature (ambient)
Junction temperature
V
VTS
V
TSTG
TJ
oC
oC
Notes:
1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the
device pins may undershoot to –2.0V or overshoot to +3.6V, provided this over- or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
3. For solder specifications, see Xilinx Packaging .
Recommended Operation Conditions
Symbol
Parameter
Min
2.37
2.37
3.0
2.37
1.71
0
Max
2.62
2.62
3.6
Units
VCCINT
Supply voltage for internal logic
and input buffers
Commercial TA = 0oC to +70oC
Industrial TA = –40oC to +85oC
V
VCCIO
Supply voltage for output drivers for 3.3V operation
Supply voltage for output drivers for 2.5V operation
Supply voltage for output drivers for 1.8V operation
Low-level input voltage
V
V
V
V
V
V
2.62
1.89
0.8
VIL
VIH
VO
High-level input voltage
1.7
0
3.6
Output voltage
VCCIO
Quality and Reliability Characteristics
Symbol
TDR
Parameter
Min
20
Max
Units
Data retention
-
-
-
Years
Cycles
Volts
NPE
Program/Erase cycles (endurance)
Electrostatic Discharge (ESD)
1,000
2,000
VESD
DS052 (v3.0) June 25, 2007
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3
Product Specification
Product Obsolete/Under Obsolescence
R
XC9572XV High-performance CPLD
DC Characteristics (Over Recommended Operating Conditions)
Symbol
Parameter
Test Conditions
IOH = –4.0 mA
Min
Max
-
Units
V
VOH
Output high voltage for 3.3V outputs
Output high voltage for 2.5V outputs
Output high voltage for 1.8V outputs
Output low voltage for 3.3V outputs
Output low voltage for 2.5V outputs
Output low voltage for 1.8V outputs
Input leakage current
2.4
I
I
OH = –1.0 mA
OH = –100 μA
2.0
-
V
90% VCCIO
-
V
VOL
IOL = 8.0 mA
-
-
-
-
0.4
0.4
0.4
±10
V
IOL = 1.0 mA
V
IOL = 100 μA
V
IIL
VCC = 2.62V
VCCIO = 3.6V
μA
VIN = GND or 3.6V
IIH
Input high-Z leakage current
VCC = 2.62V
VCCIO = 3.6V
-
±10
μA
VIN = GND or 3.6V
V
CC min < VIN < 3.6V
-
-
±150
10
μA
pF
CIN
ICC
I/O capacitance
VIN = GND
f = 1.0 MHz
Operating Supply Current
(low power mode, active)
VI = GND, No load
f = 1.0 MHz
14
mA
AC Characteristics
XC9572XV-5
XC9572XV-7
Symbol
Parameter
Min
Max
5.0
-
Min
Max
7.5
Units
ns
TPD
TSU
TH
I/O to output valid
-
-
I/O setup time before GCK
I/O hold time after GCK
GCK to output valid
3.5
4.8
-
-
ns
0
-
0
ns
TCO
-
3.5
222.2
-
-
4.5
125.0
-
ns
fSYSTEM Multiple FB internal operating frequency
-
1.0
2.5
-
-
1.6
3.2
-
MHz
ns
TPSU
TPH
I/O setup time before p-term clock input
I/O hold time after p-term clock input
P-term clock output valid
-
-
ns
TPCO
TOE
6.0
4.0
4.0
7.0
7.0
10.0
10.7
-
7.7
5.0
5.0
9.5
9.5
12.0
12.6
-
ns
GTS to output valid
-
-
ns
TOD
GTS to output disable
-
-
ns
TPOE
TPOD
TAO
Product term OE to output enabled
Product term OE to output disabled
GSR to output valid
-
-
ns
-
-
ns
-
-
ns
TPAO
TWLH
TPLH
P-term S/R to output valid
-
-
ns
GCK pulse width (High or Low)
P-term clock pulse width (High or Low)
2.2
5.0
5.0
4.0
6.5
6.5
ns
-
-
ns
TAPRPW Asynchronous preset/reset pulse width (High or Low)
-
-
ns
4
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DS052 (v3.0) June 25, 2007
Product Specification
Product Obsolete/Under ObsolesXcCe9n57c2XeV High-performance CPLD
R
Internal Timing Parameters
V
TEST
R
1
Output Type
V
V
R
R
C
L
CCIO
TEST
1
2
Device Output
3.3V
2.5V
1.8V
3.3V
2.5V
1.8V
320Ω
250Ω
10KΩ
360Ω
660Ω
14KΩ
35 pF
35 pF
35 pF
R
C
L
2
DS051_03_0601000
Figure 3: AC Load Circuit
XC9572XV-5
XC9572XV-7
Symbol
Parameter
Min
Max
Min
Max
Units
Buffer Delays
TIN
Input buffer delay
GCK buffer delay
GSR buffer delay
GTS buffer delay
Output buffer delay
-
-
-
-
-
-
2.0
1.2
2.0
4.0
2.1
0
-
-
-
-
-
-
2.3
1.5
3.1
5.0
2.5
0
ns
ns
ns
ns
ns
ns
TGCK
TGSR
TGTS
TOUT
TEN
Output buffer enable/disable delay
Product Term Control Delays
TPTCK
TPTSR
TPTTS
Product term clock delay
-
-
-
1.7
0.7
5.0
-
-
-
2.4
1.4
7.2
ns
ns
ns
Product term set/reset delay
Product term 3-state delay
Internal Register and Combinatorial Delays
TPDI
Combinatorial logic propagation delay
Register setup time
-
2.0
1.5
2.0
1.5
-
0.2
-
2.6
2.2
2.6
2.2
-
1.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TSUI
-
-
-
-
THI
Register hold time
TECSU
TECHO
TCOI
Register clock enable setup time
Register clock enable hold time
Register clock to output valid time
Register async. S/R to output delay
Register async. S/R recover before clock
Internal logic delay
-
-
-
-
0.2
5.9
0.5
6.4
TAOI
-
-
TRAI
5.0
-
7.5
-
TLOGI
TLOGILP
0.7
5.7
1.4
6.4
Internal low power logic delay
-
-
Feedback Delays
TF
Fast CONNECT II feedback delay
-
1.6
-
3.5
ns
Time Adders
TPTA
Incremental product term allocator delay
Adjacent macrocell p-term allocator delay
Slew-rate limited delay
-
-
-
0.7
0.3
3.0
-
-
-
0.8
0.3
4.0
ns
ns
ns
TPTA2
TSLEW
DS052 (v3.0) June 25, 2007
www.xilinx.com
5
Product Specification
Product Obsolete/Under Obsolescence
R
XC9572XV High-performance CPLD
XC9572XV I/O Pins
Function
Block
Macro-
cell
BScan
Order
Function
Block
Macro-
cell
BScan
Order
VQ44
TQ100
16
VQ44
TQ100
41
32
49
50
35
53
54
37
42
60
52
61
63
55
56
64
58
59
65
67
71
72
68
76
77
70
66
81
74
82
85
78
89
86
90
79
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
2
-
213
210
207
204
201
198
195
192
189
186
183
180
177
174
171
168
165
162
159
156
153
150
147
144
141
138
135
132
129
126
123
120
117
114
111
108
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
1
2
-
5
105
102
99
96
93
90
87
84
81
78
75
72
69
66
63
60
57
54
51
48
45
42
39
36
33
30
27
24
21
18
15
12
9
39
13
3
-
18
3
-
4
-
20
4
-
5
40
14
5
6
6
41
15
6
-
7
-
25
7
-
8
42
43(1)
17
22(1)
8
7
9
9
8
10
11
12
13
14
15
16
17
18
1
-
28
10
11
12
13
14
15
16
17
18
1
-
44(1)
23(1)
33
12
-
-
-
36
27(1)
-
1(1)
13
14
18
16
-
2
29
-
39
3
30
-
40
-
87
-
2
29
94
2
19
-
3
-
91
3
4
-
30
31
-
93
4
-
5
95
5
20
-
6
96
3(2)
6
7
7
-
8
32
33(1)
-
97
8
21
-
9
99(1)
1
4(1)
9
10
11
12
13
14
15
16
17
18
10
11
12
13
14
15
16
17
18
-
34(1)
22
-
-
6
-
8
9(3)
-
36(3)
37
-
23
27
-
11
10
6
38
-
12
28
-
3
92
0
Notes:
1. Global control pin.
2. GTS1 for TQ100
3. GTS1 for VQ44
6
www.xilinx.com
DS052 (v3.0) June 25, 2007
Product Specification
Product Obsolete/Under ObsolesXcCe9n57c2XeV High-performance CPLD
R
XC9572XV Global, JTAG and Power Pins
Pin Type
I/O/GCK1
I/O/GCK2
I/O/GCK3
I/O/GTS1
I/O/GTS2
I/O/GSR
TCK
VQ44
TQ100
43
44
22
23
1
27
36
3
34
4
33
99
11
48
TDI
9
45
83
TDO
24
TMS
10
47
V
CCINT 2.5V
CCIO 1.8/2.5V/3.3V
GND
15, 35
26
5, 57, 98
26, 38, 51, 88
V
4, 17, 25
21, 31, 44, 62, 69, 75,
84, 100
No Connects
-
2, 7, 19, 24, 34, 43, 46,
73, 80
DS052 (v3.0) June 25, 2007
www.xilinx.com
7
Product Specification
Product Obsolete/Under Obsolescence
R
XC9572XV High-performance CPLD
Device Part Marking and Ordering Combination Information
R
Device Type
Package
XC95xxxXV
TQ144
This line not
related to device
part number
Speed
7C
Operating Range
1
Sample package with part marking.
Notes:
1. Due to the small size of chip scale packages, part marking on these packages does not follow the above
sample and the complete part number cannot be included in the marking. Part marking on chip scale
packages by line:
·
·
·
·
Line 1 = X (Xilinx logo), then truncated part number (no XC), i.e., 95xxxXV.
Line 2 = Not related to device part number.
Line 3 = Not related to device part number.
Line 4 = Package code, speed, operating temperature, three digits not related to device
part number. Package code: C1 = CS48.
Speed
Device Ordering and
Part Marking Number
(pin-to-pin
delay)
Pkg.
Symbol
No. of
Pins
Operating
Range(1)
Package Type
XC9572XV-5VQ44C
XC9572XV-5TQ100C
XC9572XV-7VQ44C
XC9572XV-7TQ100C
XC9572XV-7VQ44I
XC9572XV-7TQ100I
Notes:
5 ns
5 ns
VQ44
44-pin
Quad Flat Pack (VQFP)
Thin Quad Flat Pack (TQFP)
Quad Flat Pack (VQFP)
Thin Quad Flat Pack (TQFP)
Quad Flat Pack (VQFP)
Thin Quad Flat Pack (TQFP)
C
C
C
C
I
TQ100 100-pin
VQ44 44-pin
TQ100 100-pin
VQ44 44-pin
TQ100 100-pin
7.5 ns
7.5 ns
7.5 ns
7.5 ns
I
1. C = Commercial: TA = 0° to +70°C; I = Industrial: TA = –40° to +85°C
2. Some packages available in Pb-free option. See Xilinx Packaging for more information.
8
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DS052 (v3.0) June 25, 2007
Product Specification
Product Obsolete/Under ObsolesXcCe9n57c2XeV High-performance CPLD
R
Revision History
Date
Revision No.
1.1
Description
02/01/00
01/29/01
Initial Xilinx release. Advance information specification.
2.0
2.1
2.2
Added -4 performance specification and VQ44 pagkage. Deleted VQ64 package.
Updated ICC vs. Frequency Figure 1.
05/15/01
08/27/01
Updated ICC formula, Recommended Operation Conditions, -4 and -5 AC
Characteristics and Internal Timing Parameters
Changed VCCIO 3.3V from 3.13 to 3.0 (min), 3.46 to 3.60 (max); DC characteristics: IIL
- added "low" current, IIH - changed to "Input leakage high current"; Internal Timing: -5
TAOI from 6.5 to 5.9.
05/31/02
2.3
Updated ICC equation on page 1. Updated Component Availability Chart. Changed to
Preliminary. Added second test condition and max measurement to IIH DC
Characteristics. Added Part Marking Information to Ordering Information. Removed the
-4 device.
06/18/03
08/21/03
04/15/05
01/16/06
06/25/07
2.4
2.5
2.6
2.7
3.0
Updated TSOL from 260 to 220oC. Updated Device Part Marking.
Updated Package Device Marking Pin 1 orientation.
Added TAPRPW specification to AC Characteristics. Added IOSTANDARD information.
Removed PC44 and CS48 packages as per XCN05020.
Notice of discontinuance.
DS052 (v3.0) June 25, 2007
www.xilinx.com
9
Product Specification
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