XCF32PVO48M_技术文档

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QPro Extended Temperature Platform Flash

In-System Programmable Configuration PROM

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DS541 (v1.0) November 27, 2006

Product Specification

Features

•

In-System Programmable PROM for Configuration of

Xilinx FPGAs

•

I/O Pins Compatible with Voltage Levels Ranging From

1.5V to 3.3V

•

Low-Power Advanced CMOS NOR FLASH Process

Endurance of 20,000 Program/Erase Cycles

Design Support Using the Xilinx Alliance ISE™ and

Foundation ISE Series Software Packages

XQF32P

Operation over Full Military Temperature Range

(–55°C to +125°C)

♦

1.8V Supply Voltage

Serial or Parallel FPGA Configuration Interface

(up to 33 MHz)

•

IEEE Standard 1149.1/1532 Boundary-Scan (JTAG)

Support for Programming, Prototyping, and Testing

♦

Available in Small-Footprint VO48 Package

JTAG Command Initiation of Standard FPGA

Configuration

Design Revision Technology Enables Storing and

Accessing Multiple Design Revisions for

Configuration

•

Cascadable for Storing Longer or Multiple Bitstreams

Dedicated Boundary-Scan (JTAG) I/O Power Supply

♦

Built-In Data Decompressor Compatible with Xilinx

Advanced Compression Technology

(V

)

CCJ

Table 1: Xilinx QPro Platform Flash PROM Features

Program

In-system

via JTAG

Serial

Parallel

Design

Device

Density

V_CCINTV_CCORange V_CCJRange

Packages

Compression

Config. Config. Revisioning

XQF32P 32 Mbit

1.8V 1.5V – 3.3V 2.5V – 3.3V

VO48

✓

Description

Xilinx introduces the QPro version of the Platform Flash

series of in-system programmable configuration PROMs.

Available in 32 Megabit (Mbit) density, this PROM provides

an easy-to-use, cost-effective, and reprogrammable method

for storing large Xilinx FPGA configuration bitstreams. The

32-Mbit PROM supports Master Serial, Slave Serial, Master

SelectMAP, and Slave SelectMAP FPGA configuration

modes (Figure 1).

CLK

CE

EN_EXT_SEL

OE/RESET BUSY

OSC

CLKOUT

Decompressor

Control

and

JTAG

Serial

TCK

TMS

TDI

CEO

Data

or

Parallel

Interface

Memory

DATA (D0)

(Serial/Parallel Mode)

Address

TDO

Interface

Data

D[1:7]

(Parallel Mode)

DS541_01_111706

CF

REV_SEL [1:0]

Figure 1: XQF32P Platform Flash PROM Block Diagram

PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS541 (v1.0) November 27, 2006

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Product Specification

1

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QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM

When the FPGA is in Master Serial mode, it generates a

configuration clock that drives the PROM. With CF High, a

short access time after CE and OE are enabled, data is

available on the PROM DATA (D0) pin that is connected to

the FPGA DIN pin. New data is available a short access

time after each rising clock edge. The FPGA generates the

appropriate number of clock pulses to complete the

configuration.

Table 2: Xilinx FPGAs and Compatible Platform Flash PROMs

Configuration

Bitstream

FPGA

Platform Flash PROM⁽¹⁾

Virtex™-5 LX Family

XC5VLX50

12,556,672

XCF32P

XC5VLX330

Virtex-4 LX Family

XC4VLX25

79,704,832 XCF32P+XCF32P+XCF32P

7,819,904

12,259,712

51,367,808

XCF32P

XCF16P

When the FPGA is in Slave Serial mode, the PROM and the

FPGA are both clocked by an external clock source, or

optionally, the PROM can be used to drive the FPGA’s

configuration clock.

XC4VLX40

XC4VLX200

Virtex-4 FX Family

XC4VFX60

XCF32P+XCF32P

The XQF32P QPro version of the Platform Flash PROM

also supports Master SelectMAP and Slave SelectMAP (or

Slave Parallel) FPGA configuration modes. When the FPGA

is in Master SelectMAP mode, the FPGA generates a

configuration clock that drives the PROM. When the FPGA

is in Slave SelectMAP Mode, either an external oscillator

generates the configuration clock that drives the PROM and

the FPGA, or optionally, the XQF32P PROM can be used to

drive the FPGA’s configuration clock. With BUSY Low and

CF High, after CE and OE are enabled, data is available on

the PROM DATA (D0-D7) pins. New data is available a short

access time after each rising clock edge. The data is

clocked into the FPGA on the following rising edge of the

CCLK. A free-running oscillator can be used in the Slave

Parallel /Slave SelecMAP mode.

21,002,880

47,856,896

XCF32P

XC4VFX140

Virtex-4 SX Family

XC4VSX55

XCF32P+XCF32P

22,749,184

XCF32P

Virtex-II Pro Family

XC2VP40

15,868,192

26,098,976

XCF16P

XCF32P

XC2VP70

Virtex-II ⁽²⁾Family

XC2V2000

7,492,000

10,494,368

21,849,504

XQF32P

XC2V3000

XC2V6000

Virtex-E Family

XCV600E

3,961,632

6,587,520

10,159,648

XCF04S

XCF08P

XCF16P

The XQF32P QPro version of the Platform Flash PROM

provides additional advanced features. A built-in data

decompressor supports utilizing compressed PROM files,

and design revisioning allows multiple design revisions to

be stored on a single PROM or stored across several

PROMs. For design revisioning, external pins or internal

control bits are used to select the active design revision.

XCV1000E

XCV2000E

Virtex Family

XCV100

781,216

1,751,808

3,607,968

6,127,744

1,335,840

XCF01S

XCF02S

XCF04S

XCF08P

XCF02S

XCV300

XCV600

Multiple Platform Flash PROM devices can be cascaded to

support the larger configuration files required when

targeting larger FPGA devices or targeting multiple FPGAs

daisy chained together. When utilizing the advanced

features for the XQF32P Platform Flash PROM, such as

design revisioning, programming files which span cascaded

PROM devices can only be created for cascaded chains

containing only XQF32P PROMs.

XCV1000

XC2S200

Notes:

1. Assumes compression used.

2. The largest possible Virtex-II bitstream sizes are specified. Refer

to the UG002, Virtex-II Platform FPGA User Guide for

information on bitgen options which affect bitstream size.

The Platform Flash PROMs are compatible with all of the

existing FPGA device families. A reference list of Xilinx

FPGAs and the respective compatible Platform Flash

PROMs is given in Table 2.

DS541 (v1.0) November 27, 2006

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Product Specification

2

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QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM

External Programming

Programming

Xilinx reprogrammable PROMs can also be programmed by

In-System Programming

the Xilinx MultiPRO Desktop Tool or a third-party device

programmer. This provides the added flexibility of using

pre-programmed devices with an in-system programmable

option for future enhancements and design changes.

In-System Programmable PROMs can be programmed

individually, or two or more can be daisy-chained together

and programmed in-system via the standard 4-pin JTAG

protocol as shown in Figure 2. In-system programming

offers quick and efficient design iterations and eliminates

unnecessary package handling or socketing of devices. The

programming data sequence is delivered to the device

using either Xilinx iMPACT software and a Xilinx download

cable, a third-party JTAG development system, a

JTAG-compatible board tester, or a simple microprocessor

interface that emulates the JTAG instruction sequence. The

iMPACT software also outputs serial vector format (SVF)

files for use with any tools that accept SVF format, including

automatic test equipment. During in-system programming,

the CEO output is driven High. All other outputs are held in

a high-impedance state or held at clamp levels during

in-system programming. In-system programming is fully

supported across the recommended operating voltage and

temperature ranges.

Reliability and Endurance

Xilinx in-system programmable products provide a

guaranteed endurance level of 20,000 in-system

program/erase cycles and a minimum data retention of 20

years. Each device meets all functional, performance, and

data retention specifications within this endurance limit.

Design Security

The Xilinx in-system programmable Platform Flash PROM

devices incorporate advanced data security features to fully

protect the FPGA programming data against unauthorized

reading via JTAG. The XQF32P PROMs can also be

programmed to prevent inadvertent writing via JTAG.

Table 3 shows the security settings available for the

XQF32P PROM.

Read Protection

The read protect security bit can be set by the user to

prevent the internal programming pattern from being read or

copied via JTAG. Read protection does not prevent write

operations. For the XQF32P PROM the read protect

security bit can be set for individual design revisions, and

resetting the read protect bit requires erasing the particular

design revision.

Write Protection

(a)

(b)

DS541_02_111706

Figure 2: JTAG In-System Programming Operation

(a) Solder Device to PCB

The XQF32P PROM device also allows the user to write

protect (or lock) a particular design revision to prevent

inadvertent erase or program operations. Once set, the

write protect security bit for an individual design revision

must be reset (using the UNLOCK command followed by

ISC_ERASE command) before an erase or program

operation can be performed.

(b) Program Using Download Cable

Table 3: XQF32P Design Revision Data Security Options

Read/Verify

Read Protect

Reset (default)

Write Protect

Program Inhibited

Erase Inhibited

Inhibited

Reset (default)

Set

–

✓

–

✓

–

Reset (default)

Set

Reset (default)

Set

✓

DS541 (v1.0) November 27, 2006

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Product Specification

3

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QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM

onto TDO (LSB first), while an instruction is shifted into the

instruction register from TDI.

IEEE 1149.1 Boundary-Scan (JTAG)

The Platform Flash PROM family is compatible with the IEEE

1149.1 boundary-scan standard and the IEEE 1532

in-system configuration standard. A Test Access Port (TAP)

and registers are provided to support all required boundary

scan instructions, as well as many of the optional

instructions specified by IEEE Std. 1149.1. In addition, the

JTAG interface is used to implement in-system programming

(ISP) to facilitate configuration, erasure, and verification

operations on the Platform Flash PROM device. Table 4,

page 4 lists the required and optional boundary-scan

instructions supported in the Platform Flash PROMs. Refer

to the IEEE Std. 1149.1 specification for a complete

description of boundary-scan architecture and the required

and optional instructions.

XQF32P Instruction Register (16 bits wide)

The Instruction Register (IR) for the XQF32P PROM is sixteen

bits wide and is connected between TDI and TDO during an

instruction scan sequence. The detailed composition of the

instruction capture pattern is illustrated in Table 5, page 5.

The instruction capture pattern shifted out of the XQF32P

device includes IR[15:0]. IR[15:9] are reserved bits and are

set to a logic 0. The ISC Error field, IR[8:7], contains a 10

when an ISC operation is a success; otherwise a 01 when

an In-System Configuration (ISC) operation fails. The

Erase/Program (ER/PROG) Error field, IR[6:5], contains a

10 when an erase or program operation is a success;

otherwise a 01 when an erase or program operation fails.

The Erase/Program (ER/PROG) Status field, IR[4], contains

a logic 0 when the device is busy performing an erase or

programming operation; otherwise, it contains a logic 1. The

ISC Status field, IR[3], contains logic 1 if the device is

currently in In-System Configuration (ISC) mode; otherwise,

it contains logic 0. The DONE field, IR[2], contains logic 1 if

the sampled design revision has been successfully

programmed; otherwise, a logic 0 indicates incomplete

programming. The remaining bits IR[1:0] are set to 01 as

defined by IEEE Std. 1149.1.

Caution! ^{The XQF32P JTAG TAP pause states are not fully compliant with}

the JTAG 1149.1 specification. If a temporary pause of a JTAG shift operation is

required, then stop the JTAG TCK clock and maintain the JTAG TAP within the

JTAG Shift-IR or Shift-DR TAP state. Do not transition the XQF32P JTAG TAP

through the JTAG Pause-IR or Pause-DR TAP state to temporarily pause a

JTAG shift operation.

Instruction Register

The Instruction Register (IR) for the Platform Flash PROM

is connected between TDI and TDO during an instruction

scan sequence. In preparation for an instruction scan

sequence, the instruction register is parallel loaded with a

fixed instruction capture pattern. This pattern is shifted out

Table 4: Platform Flash PROM Boundary Scan Instructions

XQF32P IR[15:0]

Boundary-Scan Command

(hex)

Instruction Description

Required Instructions

BYPASS

FFFF

0001

0000

Enables BYPASS.

SAMPLE/PRELOAD

EXTEST

Enables boundary-scan SAMPLE/PRELOAD operation.

Enables boundary-scan EXTEST operation.

Optional Instructions

CLAMP

00FA

00FC

00FE

00FD

Enables boundary-scan CLAMP operation.

Places all outputs in high-impedance state simultaneously.

Enables shifting out 32-bit IDCODE.

HIGHZ

IDCODE

USERCODE

Enables shifting out 32-bit USERCODE.

Platform Flash PROM

Specific Instructions

CONFIG

00EE

Initiates FPGA configuration by pulsing CF pin Low once (for the XQF32P, this

command also resets the selected design revision based on either the external

REV_SEL[1:0] pins or on the internal design revision selection bits).⁽¹⁾

Notes:

1. For more information see "Initiating FPGA Configuration," page 11.

DS541 (v1.0) November 27, 2006

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Product Specification

4

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QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM

Table 5: XQF32P Instruction Capture Values Loaded into IR as part of an Instruction Scan Sequence

IR[15:9]

IR[8:7]

IR[6:5]

IR[4]

IR[3]

IR[2]

IR[1:0]

TDI →

→ TDO

ER/PROG

Error

ER/PROG

Status

Reserved

ISC Error

ISC Status

DONE

0 1

USERCODE Register

Boundary Scan Register

The USERCODE instruction gives access to a 32-bit user

programmable scratch pad typically used to supply

information about the device's programmed contents. By

using the USERCODE instruction, a user-programmable

identification code can be shifted out for examination. This

code is loaded into the USERCODE register during

programming of the Platform Flash PROM. If the device is

blank or was not loaded during programming, the

USERCODE register contains FFFFFFFFh.

The boundary-scan register is used to control and observe the

state of the device pins during the EXTEST,

SAMPLE/PRELOAD, and CLAMP instructions. Each output

pin on the Platform Flash PROM has two register stages which

contribute to the boundary-scan register, while each input pin

has only one register stage. The bidirectional pins have a total

of three register stages which contribute to the boundary-scan

register. For each output pin, the register stage nearest to TDI

controls and observes the output state, and the second stage

closest to TDO controls and observes the High-Z enable state

of the output pin. For each input pin, a single register stage

controls and observes the input state of the pin. The

Customer Code Register

For the XQF32P Platform Flash PROM, in addition to the

USERCODE, a unique 32-byte Customer Code can be

assigned to each design revision enabled for the PROM.

The Customer Code is set during programming, and is

typically used to supply information about the design

revision contents. A private JTAG instruction is required to

read the Customer Code. If the PROM is blank, or the

Customer Code for the selected design revision was not

loaded during programming, or if the particular design

revision is erased, the Customer Code contains all ones.

bidirectional pin combines the three bits, the input stage bit is

first, followed by the output stage bit and finally the output

enable stage bit. The output enable stage bit is closest to TDO.

See the XQF32P Pin Names and Descriptions Tables in the

"Pinouts and Pin Descriptions," page 33 section for the

boundary-scan bit order for all connected device pins, or see

the appropriate BSDL file for the complete boundary-scan bit

order description under the "attribute

BOUNDARY_REGISTER" section in the BSDL file. The bit

assigned to boundary-scan cell 0 is the LSB in the

boundary-scan register, and is the register bit closest to TDO.

Platform Flash PROM TAP

Characteristics

Identification Registers

The Platform Flash PROM family performs both in-system

programming and IEEE 1149.1 boundary-scan (JTAG)

testing via a single 4-wire Test Access Port (TAP). This

simplifies system designs and allows standard Automatic

Test Equipment to perform both functions. The AC

characteristics of the Platform Flash PROM TAP are

described as follows.

IDCODE Register

The IDCODE is a fixed, vendor-assigned value that is used to

electrically identify the manufacturer and type of the device

being addressed. The IDCODE register is 32 bits wide. The

IDCODE register can be shifted out for examination by using

the IDCODE instruction. The IDCODE is available to any

other system component via JTAG.

TAP Timing

The IDCODE register has the following binary format:

vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1

where

Figure 3, page 6 shows the timing relationships of the TAP

signals. These TAP timing characteristics are identical for

both boundary-scan and ISP operations.

v = the die version number

f = the PROM family code

a = the specific Platform Flash PROM product ID

c = the Xilinx manufacturer's ID

The LSB of the IDCODE register is always read as logic 1

as defined by IEEE Std. 1149.1. The IDCODE register value

for the XQ32PPlatform Flash PROM is <v>5059093.

Note: The <v> in the IDCODE field represents the device’s

revision code (in hex) and can vary.

DS541 (v1.0) November 27, 2006

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Product Specification

5

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QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM

T

CKMIN

TCK

T

MSS

T

MSH

TMS

T

DIS

T

DIH

TDI

T

DOV

TDO

DS541_03_111706

Figure 3: Test Access Port Timing

TAP AC Parameters

Table 6 shows the timing parameters for the TAP waveforms shown in Figure 3.

Table 6: Test Access Port Timing Parameters

Symbol

T_CKMIN

Description

TCK minimum clock period when V_CCJ= 2.5V or 3.3V

TMS setup time when V_CCJ= 2.5V or 3.3V

TMS hold time when V_CCJ= 2.5V or 3.3V

TDI setup time when V_CCJ= 2.5V or 3.3V

TDI hold time when V_CCJ= 2.5V or 3.3V

TDO valid delay when V_CCJ= 2.5V or 3.3V

Min

100

10

25

10

25

–

Max

–

Units

ns

T_MSS

T_MSH

T_DIS

–

ns

–

ns

–

ns

T_DIH

–

ns

T_DOV

30

ns

The CLKOUT signal is enabled during programming, and is

active when CE is Low and OE/RESET is High. On CE

rising edge transition, if OE/RESET is High and the PROM

terminal count has not been reached, then CLKOUT

remains active for an additional eights clock cycles before

being disabled. On a OE/RESET falling edge transition,

CLKOUT is immediately disabled. When disabled, the

CLKOUT pin is put into a high-impedance state and should

be pulled High externally to provide a known state.

Additional Features for the XQF32P

Internal Oscillator

The 32-Mbit XQF32P Platform Flash PROMs include an

optional internal oscillator which can be used to drive the

CLKOUT and DATA pins on FPGA configuration interface.

The internal oscillator can be enabled when programming

the PROM, and the oscillator can be set to either the default

frequency or to a slower frequency ("XQF32P PROM as

Configuration Master with Internal Oscillator as Clock

Source," page 30).

When cascading Platform Flash PROMs with CLKOUT

enabled, after completing it's data transfer, the first PROM

disables CLKOUT and drives the CEO pin enabling the next

PROM in the PROM chain. The next PROM begins driving

the CLKOUT signal once that PROM is enabled and data is

available for transfer.

CLKOUT

The 32-Mbit XQF32P Platform Flash PROMs include the

programmable option to enable the CLKOUT signal which

allows the PROM to provide a source synchronous clock

aligned to the data on the configuration interface. The

CLKOUT signal is derived from one of two clock sources: the

CLK input pin or the internal oscillator. The input clock source

is selected during the PROM programming sequence.

Output data is available on the rising edge of CLKOUT.

During high-speed parallel configuration without

compression, the FPGA drives the BUSY signal on the

configuration interface. When BUSY is asserted High, the

PROMs internal address counter stops incrementing, and

the current data value is held on the data outputs. While

BUSY is High, the PROM continues driving the CLKOUT

signal to the FPGA, clocking the FPGA’s configuration logic.

DS541 (v1.0) November 27, 2006

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Product Specification

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QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM

When the FPGA deasserts BUSY, indicating that it is ready

to receive additional configuration data, the PROM begins

driving new data onto the configuration interface.

8-Mbit memory blocks, and any space remaining in the last

8-Mbit memory block is padded with all ones.

•

A single 32-Mbit PROM contains four 8-Mbit memory

blocks, and can therefore store up to four separate

design revisions: one 32-Mbit design revision, two

16-Mbit design revisions, three 8-Mbit design revisions,

four 8-Mbit design revisions, and so on.

Decompression

The 32-Mbit XQF32P Platform Flash PROMs include a

built-in data decompressor compatible with Xilinx advanced

compression technology. Compressed Platform Flash

PROM files are created from the target FPGA bitstream(s)

using the iMPACT software. Only Slave Serial and Slave

SelectMAP (parallel) configuration modes are supported for

FPGA configuration when using a XQF32P PROM

programmed with a compressed bitstream. Compression

rates vary depending on several factors, including the target

device family and the target design contents.

Because of the 8-Mbit minimum size requirement for

each revision, a single 16-Mbit PROM can only store

up to two separate design revisions: one 16-Mbit

design revision, one 8-Mbit design revision, or two

8-Mbit design revisions.

A single 8-Mbit PROM can store only one 8-Mbit

design revision.

Larger design revisions can be split over several cascaded

PROMs. For example, two 32-Mbit PROMs can store up to

four separate design revisions: one 64-Mbit design revision,

two 32-Mbit design revisions, three 16-Mbit design revisions,

four 16-Mbit design revisions, and so on.

The decompression option is enabled during the PROM

programming sequence. The PROM decompresses the

stored data before driving both clock and data onto the

FPGA's configuration interface. If Decompression is

enabled, then the Platform Flash clock output pin

(CLKOUT) must be used as the clock signal for the

configuration interface, driving the target FPGA's

configuration clock input pin (CCLK). Either the PROM's

CLK input pin or the internal oscillator must be selected as

the source for CLKOUT. Any target FPGA connected to the

PROM must operate as slave in the configuration chain,

with the configuration mode set to Slave Serial mode or

Slave SelectMap (parallel) mode.

See Figure 4, page 8 for a few basic examples of how

multiple revisions can be stored. The design revision

partitioning is handled automatically during file generation

in iMPACT.

During the PROM file creation, each design revision is

assigned a revision number:

Revision 0 = '00'

Revision 1 = '01'

Revision 2 = '10'

Revision 3 = '11'

When decompression is enabled, the CLKOUT signal

becomes a controlled clock output with a reduced maximum

frequency. When decompressed data is not ready, the

CLKOUT pin is put into a high-Z state and must be pulled

High externally to provide a known state.

After programming the Platform Flash PROM with a set of

design revisions, a particular design revision can be

selected using the external REV_SEL[1:0] pins or using the

internal programmable design revision control bits. The

EN_EXT_SEL pin determines if the external pins or internal

bits are used to select the design revision. When

The BUSY input is automatically disabled when

decompression is enabled.

EN_EXT_SEL is Low, design revision selection is controlled

by the external Revision Select pins, REV_SEL[1:0]. When

EN_EXT_SEL is High, design revision selection is

controlled by the internal programmable Revision Select

control bits. During power up, the design revision selection

inputs (pins or control bits) are sampled internally. After

power up, the design revision selection inputs are sampled

again when any of the following events occur:

Design Revisioning

Design Revisioning allows the user to create up to four

unique design revisions on a single PROM or stored across

multiple cascaded PROMs. Design Revisioning is supported

for the XQF32P Platform Flash PROM in both serial and

parallel modes. Design Revisioning can be used with

compressed PROM files, and also when the CLKOUT

feature is enabled. The PROM programming files along with

the revision information files (.cfi) are created using the

iMPACT software. The .cfi file is required to enable design

revision programming in iMPACT.

•

On the rising edge of CE

On the falling edge of OE/RESET (when CE is Low)

On the rising edge of CF (when CE is Low)

When reconfiguration is initiated by using the JTAG

CONFIG instruction.

A single design revision is composed of from 1 to n 8-Mbit

memory blocks. If a single design revision contains less

than 8 Mbits of data, then the remaining space is padded

with all ones. A larger design revision can span several

The data from the selected design revision is then

presented on the FPGA configuration interface.

DS541 (v1.0) November 27, 2006

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Product Specification

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QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM

PROM 0

REV 0

(8 Mbits)

REV 0

(16 Mbits)

REV 1

(8 Mbits)

REV 0

(32 Mbits)

REV 1

REV 2

(8 Mbits)

(24 Mbits)

REV 2

REV 1

(16 Mbits)

REV 3

(8 Mbits)

4 Design Revisions 3 Design Revisions

2 Design Revisions

1 Design Revision

(a) Design Revision storage examples for a single XQF32P PROM

PROM 0

REV 0

(16 Mbits)

REV 0

(32 Mbits)

REV 1

(16 Mbits)

PROM 1

REV 2

(16 Mbits)

REV 2

REV 1

REV 0

(32 Mbits)

REV 3

(16 Mbits)

4 Design Revisions 3 Design Revisions

2 Design Revisions

1 Design Revision

ds541_04_070906

(b) Design Revision storage examples spanning two XQF32P PROMs

Figure 4: Design Revision Storage Examples

PROM to FPGA Configuration Mode and Connections Summary

The FPGA's I/O, logical functions, and internal

interconnections are established by the configuration data

FPGA Master Serial Mode

In Master Serial mode, the FPGA automatically loads the

contained in the FPGA’s bitstream. The bitstream is loaded

into the FPGA either automatically upon power up, or on

command, depending on the state of the FPGA's mode

pins. Xilinx Platform Flash PROMs are designed to

download directly to the FPGA configuration interface.

FPGA configuration modes which are supported by the

XQF32P Platform Flash PROMs include: Master Serial,

Slave Serial, Master SelectMAP, and Slave SelectMAP.

Below is a short summary of the supported FPGA

configuration modes. See the respective FPGA data sheet

for device configuration details, including which

configuration modes are supported by the targeted FPGA

device.

configuration bitstream in bit-serial form from external

memory synchronized by the configuration clock (CCLK)

generated by the FPGA. Upon power-up or reconfiguration,

the FPGA's mode select pins are used to select the Master

Serial configuration mode. Master Serial Mode provides a

simple configuration interface. Only a serial data line, a

clock line, and two control lines (INIT and DONE) are

required to configure an FPGA. Data from the PROM is

read out sequentially on a single data line (DIN), accessed

via the PROM's internal address counter which is

incremented on every valid rising edge of CCLK. The serial

bitstream data must be set up at the FPGA’s DIN input pin a

short time before each rising edge of the FPGA's internally

generated CCLK signal.

DS541 (v1.0) November 27, 2006

www.xilinx.com

Product Specification

8

R

QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM

Typically, a wide range of frequencies can be selected for

the FPGA’s internally generated CCLK which always starts

at a slow default frequency. The FPGA’s bitstream contains

configuration bits which can switch CCLK to a higher

frequency for the remainder of the Master Serial

configuration sequence. The desired CCLK frequency is

selected during bitstream generation.

•

The PROM CLKOUT (for XQF32P only) or an external

clock source drives the FPGA's CCLK input.

The CEO output of a PROM drives the CE input of the

next PROM in a daisy chain (if any).

The OE/RESET pins of all PROMs are connected to

the INIT_B (or INIT) pins of all FPGA devices. This

connection assures that the PROM address counter is

reset before the start of any (re)configuration.

Connecting the FPGA device to the configuration PROM for

Master Serial Configuration Mode (Figure 5, page 12):

•

The PROM CE input can be driven from the DONE pin.

The CE input of the first (or only) PROM can be driven

by the DONE output of all target FPGA devices,

provided that DONE is not permanently grounded. CE

can also be permanently tied Low, but this keeps the

•

The DATA output of the PROM(s) drive the DIN input of

the lead FPGA device.

The Master FPGA CCLK output drives the CLK input(s)

of the PROM(s)

DATA output active and causes an unnecessary I

active supply current ("DC Characteristics Over

Operating Conditions," page 24).

CC

The CEO output of a PROM drives the CE input of the

next PROM in a daisy chain (if any).

The OE/RESET pins of all PROMs are connected to

the INIT_B pins of all FPGA devices. This connection

assures that the PROM address counter is reset before

the start of any (re)configuration.

•

The PROM CF pin is typically connected to the FPGA's

PROG_B (or PROGRAM) input. For the XQF32P only,

the CF pin is a bidirectional pin. If the XQF32P CF pin

is not connected to the FPGA's PROG_B (or

•

The PROM CE input can be driven from the DONE pin.

The CE input of the first (or only) PROM can be driven

by the DONE output of all target FPGA devices,

PROGRAM) input, then the pin should be tied High.

Serial Daisy Chain

provided that DONE is not permanently grounded. CE

can also be permanently tied Low, but this keeps the

Multiple FPGAs can be daisy-chained for serial

configuration from a single source. After a particular FPGA

has been configured, the data for the next device is routed

internally to the FPGA’s DOUT pin. Typically the data on the

DOUT pin changes on the falling edge of CCLK, although

for some devices the DOUT pin changes on the rising edge

of CCLK. Consult the respective device data sheets for

detailed information on a particular FPGA device. For

clocking the daisy-chained configuration, either the first

FPGA in the chain can be set to Master Serial, generating

the CCLK, with the remaining devices set to Slave Serial

(Figure 7, page 14), or all the FPGA devices can be set to

Slave Serial and an externally generated clock can be used

to drive the FPGA's configuration interface (Figure 6,

page 13 or Figure 11, page 18).

DATA output active and causes an unnecessary I

active supply current ("DC Characteristics Over

Operating Conditions," page 24).

CC

•

The PROM CF pin is typically connected to the FPGA's

PROG_B (or PROGRAM) input. For the XQF32P only,

the CF pin is a bidirectional pin. If the XQF32P CF pin

is not connected to the FPGA's PROG_B (or

PROGRAM) input, then the pin should be tied High.

FPGA Slave Serial Mode

In Slave Serial mode, the FPGA loads the configuration

bitstream in bit-serial form from external memory

synchronized by an externally supplied clock. Upon

power-up or reconfiguration, the FPGA's mode select pins

are used to select the Slave Serial configuration mode.

Slave Serial Mode provides a simple configuration interface.

Only a serial data line, a clock line, and two control lines

(INIT and DONE) are required to configure an FPGA. Data

from the PROM is read out sequentially on a single data line

(DIN), accessed via the PROM's internal address counter

which is incremented on every valid rising edge of CCLK.

The serial bitstream data must be set up at the FPGA’s DIN

input pin a short time before each rising edge of the

externally provided CCLK.

FPGA Master SelectMAP (Parallel) Mode

In Master SelectMAP mode, byte-wide data is written into

the FPGA, typically with a BUSY flag controlling the flow of

data, synchronized by the configuration clock (CCLK)

generated by the FPGA. Upon power-up or reconfiguration,

the FPGA's mode select pins are used to select the Master

SelectMAP configuration mode. The configuration interface

typically requires a parallel data bus, a clock line, and two

control lines (INIT and DONE). In addition, the FPGA’s Chip

Select, Write, and BUSY pins must be correctly controlled to

enable SelectMAP configuration. The configuration data is

read from the PROM byte by byte on pins [D0..D7],

Connecting the FPGA device to the configuration PROM for

Slave Serial Configuration Mode (Figure 6, page 13):

accessed via the PROM's internal address counter which is

incremented on every valid rising edge of CCLK. The

bitstream data must be set up at the FPGA’s [D0..D7] input

•

The DATA output of the PROM(s) drive the DIN input of

the lead FPGA device.

DS541 (v1.0) November 27, 2006

www.xilinx.com

Product Specification

9

R

QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM

pins a short time before each rising edge of the FPGA's

internally generated CCLK signal. If BUSY is asserted

(High) by the FPGA, the configuration data must be held

until BUSY goes Low. An external data source or external

pull-down resistors must be used to enable the FPGA's

active Low Chip Select (CS or CS_B) and Write (WRITE or

RDWR_B) signals to enable the FPGA's SelectMAP

configuration process.

FPGA Slave SelectMAP (Parallel) Mode

In Slave SelectMAP mode, byte-wide data is written into the

FPGA, typically with a BUSY flag controlling the flow of data,

synchronized by an externally supplied configuration clock

(CCLK). Upon power-up or reconfiguration, the FPGA's mode

select pins are used to select the Slave SelectMAP

configuration mode. The configuration interface typically

requires a parallel data bus, a clock line, and two control lines

(INIT and DONE). In addition, the FPGA’s Chip Select, Write,

and BUSY pins must be correctly controlled to enable

SelectMAP configuration. The configuration data is read from

the PROM byte by byte on pins [D0..D7], accessed via the

PROM's internal address counter which is incremented on

every valid rising edge of CCLK. The bitstream data must be

set up at the FPGA’s [D0..D7] input pins a short time before

each rising edge of the provided CCLK. If BUSY is asserted

(High) by the FPGA, the configuration data must be held until

BUSY goes Low. An external data source or external

pull-down resistors must be used to enable the FPGA's active

Low Chip Select (CS or CS_B) and Write (WRITE or

RDWR_B) signals to enable the FPGA's SelectMAP

configuration process.

The Master SelectMAP configuration interface is clocked by

the FPGA’s internal oscillator. Typically, a wide range of

frequencies can be selected for the internally generated

CCLK which always starts at a slow default frequency. The

FPGA’s bitstream contains configuration bits which can

switch CCLK to a higher frequency for the remainder of the

Master SelectMAP configuration sequence. The desired

CCLK frequency is selected during bitstream generation.

After configuration, the pins of the SelectMAP port can be

used as additional user I/O. Alternatively, the port can be

retained using the persist option.

Connecting the FPGA device to the configuration PROM for

Master SelectMAP (Parallel) Configuration Mode (Figure 8,

page 15):

After configuration, the pins of the SelectMAP port can be

used as additional user I/O. Alternatively, the port can be

retained using the persist option.

•

The DATA outputs of the PROM(s) drive the [D0..D7]

input of the lead FPGA device.

The Master FPGA CCLK output drives the CLK input(s)

of the PROM(s)

Connecting the FPGA device to the configuration PROM for

Slave SelectMAP (Parallel) Configuration Mode (Figure 9,

page 16):

The CEO output of a PROM drives the CE input of the

next PROM in a daisy chain (if any).

•

The DATA outputs of the PROM(s) drives the [D0..D7]

inputs of the lead FPGA device.

The OE/RESET pins of all PROMs are connected to

the INIT_B pins of all FPGA devices. This connection

assures that the PROM address counter is reset before

the start of any (re)configuration.

The PROM CLKOUT (for XQF32P only) or an external

clock source drives the FPGA's CCLK input.

The CEO output of a PROM drives the CE input of the

next PROM in a daisy chain (if any).

•

The PROM CE input can be driven from the DONE pin.

The CE input of the first (or only) PROM can be driven

by the DONE output of all target FPGA devices,

The OE/RESET pins of all PROMs are connected to

the INIT_B pins of all FPGA devices. This connection

assures that the PROM address counter is reset before

the start of any (re)configuration.

provided that DONE is not permanently grounded. CE

can also be permanently tied Low, but this keeps the

DATA output active and causes an unnecessary I

active supply current ("DC Characteristics Over

Operating Conditions," page 24).

CC

•

The PROM CE input can be driven from the DONE pin.

The CE input of the first (or only) PROM can be driven

by the DONE output of all target FPGA devices,

•

For high-frequency parallel configuration, the BUSY

pins of all PROMs are connected to the FPGA's BUSY

output. This connection assures that the next data

transition for the PROM is delayed until the FPGA is

ready for the next configuration data byte.

provided that DONE is not permanently grounded. CE

can also be permanently tied Low, but this keeps the

DATA output active and causes an unnecessary I

active supply current ("DC Characteristics Over

Operating Conditions," page 24).

CC

The PROM CF pin is typically connected to the FPGA's

PROG_B (or PROGRAM) input. For the XQF32P only,

the CF pin is a bidirectional pin. If the XQF32P CF pin

is not connected to the FPGA's PROG_B (or

•

For high-frequency parallel configuration, the BUSY

pins of all PROMs are connected to the FPGA's BUSY

output. This connection assures that the next data

transition for the PROM is delayed until the FPGA is

ready for the next configuration data byte.

PROGRAM) input, then the pin should be tied High.

DS541 (v1.0) November 27, 2006

www.xilinx.com

Product Specification

10

R

QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM

•

The PROM CF pin is typically connected to the FPGA's

PROG_B (or PROGRAM) input. For the XQF32P only,

the CF pin is a bidirectional pin. If the XQF32P CF pin

is not connected to the FPGA's PROG_B (or

from the first PROM is read, the first PROM asserts its CEO

output Low and drives its outputs to a high-impedance

state. The second PROM recognizes the Low level on its CE

input and immediately enables its outputs.

PROGRAM) input, then the pin should be tied High.

After configuration is complete, address counters of all

cascaded PROMs are reset if the PROM OE/RESET pin

goes Low or CE goes High.

FPGA SelectMAP (Parallel) Device Chaining

Multiple Virtex-II FPGAs can be configured using the

SelectMAP mode, and be made to start up simultaneously.

To configure multiple devices in this way, wire the individual

CCLK, DONE, INIT, Data ([D0..D7]), Write (WRITE or

RDWR_B), and BUSY pins of all the devices in parallel. If all

devices are to be configured with the same bitstream,

readback is not being used, and the CCLK frequency

selected does not require the use of the BUSY signal, the

CS_B pins can be connected to a common line so all of the

devices are configured simultaneously (Figure 9, page 16).

When utilizing the advanced features for the XQF32P

Platform Flash PROM, including the clock output (CLKOUT)

option, decompression option, or design revisioning,

programming files which span cascaded PROM devices

can only be created for cascaded chains containing only

XQF32P PROM.

Initiating FPGA Configuration

The options for initiating FPGA configuration via the

Platform Flash PROM include:

With additional control logic, the individual devices can be

loaded separately by asserting the CS_B pin of each device

in turn and then enabling the appropriate configuration data.

The PROM can also store the individual bitstreams for each

FPGA for SelectMAP configuration in separate design

revisions. When design revisioning is utilized, additional

control logic can be used to select the appropriate bitstream

by asserting the EN_EXT_SEL pin, and using the

REV_SEL[1:0] pins to select the required bitstream, while

asserting the CS_B pin for the FPGA the bitstream is

targeting (Figure 12, page 19).

•

Automatic configuration on power up

Applying an external PROG_B (or PROGRAM) pulse

Applying the JTAG CONFIG instruction

Following the FPGA’s power-on sequence or the assertion

of the PROG_B (or PROGRAM) pin the FPGA’s

configuration memory is cleared, the configuration mode is

selected, and the FPGA is ready to accept a new

configuration bitstream. The FPGA’s PROG_B pin can be

controlled by an external source, or alternatively, the

Platform Flash PROMs incorporate a CF pin that can be

tied to the FPGA’s PROG_B pin. Executing the CONFIG

instruction through JTAG pulses the CF output Low once for

300-500 ns, resetting the FPGA and initiating configuration.

The iMPACT software can issue the JTAG CONFIG

command to initiate FPGA configuration by setting the

"Load FPGA" option.

For clocking the parallel configuration chain, either the first

FPGA in the chain can be set to Master SelectMAP,

generating the CCLK, with the remaining devices set to

Slave SelectMAP, or all the FPGA devices can be set to

Slave SelectMAP and an externally generated clock can be

used to drive the configuration interface. Again, the

respective device data sheets should be consulted for

detailed information on a particular FPGA device, including

which configuration modes are supported by the targeted

FPGA device.

When using the XQF32P Platform Flash PROM with design

revisioning enabled, the CF pin should always be connected

to the PROG_B (or PROGRAM) pin on the FPGA to ensure

that the current design revision selection is sampled when

the FPGA is reset. The XQF32P PROM samples the current

design revision selection from the external REV_SEL pins

or the internal programmable Revision Select bits on the

rising edge of CF. When the JTAG CONFIG command is

executed, the XQF32P samples the new design revision

selection before initiating the FPGA configuration

Cascading Configuration PROMs

When configuring multiple FPGAs in a serial daisy chain,

configuring multiple FPGAs in a SelectMAP parallel chain,

or configuring a single FPGA requiring a larger

configuration bitstream, cascaded PROMs provide

additional memory (Figure 7, page 14, Figure 10, page 17,

Figure 11, page 18, and Figure 12, page 19). Multiple

Platform Flash PROMs can be concatenated by using the

CEO output to drive the CE input of the downstream device.

The clock signal and the data outputs of all Platform Flash

PROMs in the chain are interconnected. After the last data

sequence. When using the XQF32P Platform Flash PROM

without design revisioning, if the CF pin is not connected to

the FPGA PROG_B (or PROGRAM) pin, then the XQF32P

CF pin must be tied High.

DS541 (v1.0) November 27, 2006

www.xilinx.com

Product Specification

11

R

QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM

Configuration PROM to FPGA Device Interface Connection Diagrams

(2)

V

CCO

(1)

V

CCJ

V

CCO CCINT

(1)

V

D0

DIN

MODE PINS

CCINT

(2)

CCO

(2)

CCJ

DIN

CCLK

...OPTIONAL

Slave FPGAs

with identical

configurations

Xilinx FPGA

Master Serial

Platform Flash

PROM

DONE

INIT_B

PROG_B

CLK

CE

CCLK

DONE

...OPTIONAL

Daisy-chained

Slave FPGAs

with different

configurations

CEO

DOUT

DIN

CCLK

OE/RESET

INIT_B

(3)

TDI

CF

PROG_B

DONE

TMS

TCK

TDO

TMS

TCK

INIT_B

PROG_B

TDO

TDI

GND

TMS

TCK

TDO

GND

Notes:

1 For Mode pin connections and DONE pin pull-up value, refer to the appropriate FPGA data sheet.

2 For compatible voltages, refer to the appropriate data sheet.

3 For the XQF32P the CF pin is a bidirectional pin, and if CF is not connected to PROGB, then it must

be tied to V

via a 4.7 kΩ pull-up resistor.

CCO

ds541_05_070806

Figure 5: Configuring in Master Serial Mode

DS541 (v1.0) November 27, 2006

www.xilinx.com

Product Specification

12

R

QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM

(2)

V

CCO

(3)

External

Oscillator

(1)

V

CCJ CCO CCINT

(1)

V

D0

DIN

MODE PINS

CCINT

(2)

CCO

(2)

CCJ

DIN

CCLK

...OPTIONAL

Slave FPGAs

with identical

configurations

Xilinx FPGA

Slave Serial

Platform Flash

PROM

DONE

INIT_B

PROG_B

(3)

CLK

CCLK

DONE

CE

CEO

...OPTIONAL

Daisy-chained

Slave FPGAs

with different

configurations

DOUT

DIN

CCLK

OE/RESET

INIT_B

(4)

TDI

CF

PROG_B

DONE

TMS

TCK

TDO

TMS

TCK

INIT_B

PROG_B

TDO

TDI

GND

TMS

TCK

TDO

GND

Notes:

1 For Mode pin connections and DONE pin pull-up value, refer to the appropriate FPGA data sheet.

2 For compatible voltages, refer to the appropriate data sheet.

3 In Slave Serial mode, the configuration interface can be clocked by an external oscillator, or optionally the

CLKOUT signal can be used to drive the FPGA's configuration clock (CCLK). If the XQF32P PROM's

CLKOUT signal is used, then CLKOUT must be tied to a 4.7KΩ resistor pulled up to V

.

CCO

4 For the XQF32P the CF pin is a bidirectional pin, and if CF is not connected to PROGB, then must be tied

to V via a 4.7 kΩ pull-up resistor.

CCO

ds541_06_070806

Figure 6: Configuring in Slave Serial Mode

DS541 (v1.0) November 27, 2006

www.xilinx.com

Product Specification

13

R

QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM

(2)

V

CCJ

V

CCJ

V

CCO

CCINT

CCO

CCINT

(1)

MODE PINS

(1)

D0

V

DIN

MODE PINS

V

D0

CCINT

(2)

CCO

(2)

CCJ

CCINT

(2)

CCO

DOUT

DIN

(2)

CCJ

Platform Flash

PROM

Xilinx FPGA

Master Serial

Xilinx FPGA

Slave Serial

Platform Flash

PROM

First

PROM

(PROM 0)

Cascaded

PROM

(PROM 1)

CLK

CE

CCLK

DONE

CCLK

DONE

CLK

CE

CEO

OE/RESET

INIT_B

OE/RESET

(3)

CF

TDI

PROG_B

TDI

CF

TMS

TCK

TDO

TMS

TCK

TDI

TDO

TMS

TCK

TDO

TDI

TDO

TDI

TMS

TCK

TMS

TCK

GND

TDO

GND

Notes:

1 For Mode pin connections and DONE pin pull-up value, refer to the appropriate FPGA data sheet.

2 For compatible voltages, refer to the appropriate data sheet.

3 For the XQF32P the CF pin is a bidirectional pin, and if CF is not connected to PROGB, then must be

tied to V

via a 4.7 kΩ pull-up resistor.

CCO

ds541_07_070806

Figure 7: Configuring Multiple Devices in Master/Slave Serial Mode

DS541 (v1.0) November 27, 2006

www.xilinx.com

Product Specification

14

R

QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM

(2)

V

CCO

(1)

V

CCJ

V

CCO CCINT

(3)

I/O

(1)

MODE PINS

D[0:7]

V

D[0:7]

CCINT

(2)

CCO

(2)

CCJ

RDWR_B

CS_B

1KΩ

XQF32P

Xilinx FPGA

Platform Flash

Master SelectMAP

PROM

CLK

CCLK

DONE

CE

CEO

D[0:7]

CCLK

...OPTIONAL

Slave FPGAs

with identical

configurations

OE/RESET

INIT_B

DONE

(5)

CF

TDI

PROG_B

INIT_B

(4)

BUSY

TMS

TCK

TDO

TMS

TCK

BUSY

PROG_B

(4)

BUSY

TDO

TDI

GND

TMS

TCK

TDO

GND

Notes:

1 For Mode pin connections and DONE pin pull-up value, refer to the appropriate FPGA data sheet.

2 For compatible voltages, refer to the appropriate data sheet.

3 CS_B (or CS) and RDWR_B (or WRITE) must be either driven Low or pulled down exernally. One option is shown.

4 The BUSY pin is only available with the XQF32P Platform Flash PROM, and the connection is only required for

high-frequency SelectMAP mode configuration. For BUSY pin requirements, refer to the appropriate FPGA data sheet.

5 For the XQF32P the CF pin is a bidirectional pin, and if CF is not connected to PROGB, then must be tied to V

a 4.7 kΩ pull-up resistor.

via

CCO

ds541_08_070806

Figure 8: Configuring in Master SelectMAP Mode

DS541 (v1.0) November 27, 2006

www.xilinx.com

Product Specification

15

R

QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM

(2)

V

CCO

(5)

External

Oscillator

(1)

V

CCJ

V

CCO CCINT

(3)

I/O

(1)

MODE PINS

D[0:7]

V

D[0:7]

CCINT

(2)

CCO

(2)

CCJ

RDWR_B

CS_B

1KΩ

XQF32P

Xilinx FPGA

Platform Flash

Slave SelectMAP

PROM

(5)

CLK

CCLK

DONE

CE

CEO

D[0:7]

CCLK

...OPTIONAL

Slave FPGAs

with identical

configurations

OE/RESET

INIT_B

DONE

(6)

CF

TDI

PROG_B

INIT_B

(4)

BUSY

TMS

TCK

TDO

TMS

TCK

BUSY

PROG_B

(4)

BUSY

TDO

TDI

GND

TMS

TCK

TDO

GND

Notes:

1 For Mode pin connections and DONE pin pull-up value, refer to the appropriate FPGA data sheet.

2 For compatible voltages, refer to the appropriate data sheet.

3 CS_B (or CS) and RDWR_B (or WRITE) must be either driven Low or pulled down externally. One option is shown.

4 The BUSY pin is only available with the XQF32P Platform Flash PROM, and the connection is only required for

high-frequency SelectMAP mode configuration. For BUSY pin requirements, refer to the appropriate FPGA data sheet.

5 In Slave SelectMAP mode, the configuration interface can be clocked by an external oscillator, or, optionally, the

CLKOUT signal can be used to drive the FPGA's configuration clock (CCLK). If the XQF32P PROM's CLKOUT signal

is used, then CLKOUT must be tied to a 4.7 KΩ resistor pulled up to V

.

CCO

6 For the XQF32P the CF pin is a bidirectional pin, and if CF is not connected to PROGB, then must be tied to V

a 4.7 kΩ pull-up resistor.

via

CCO

ds541_09_080406

Figure 9: Configuring in Slave SelectMAP Mode

DS541 (v1.0) November 27, 2006

www.xilinx.com

Product Specification

16

R

QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM

(2)

V

CCO

V

CCINT

V

CCJ

V

CCO

V

CCINT

V

CCO

CCJ

(1)

V

D[0:7]

MODE PINS

D[0:7]

MODE PINS

V

D[0:7]

CCINT

(2)

CCINT

(2)

CCO

(3)

I/O

CCO

(2)

RDWR_B

CCJ

CS_B

XQF32P

Platform Flash

PROM

Platform Flash

PROM

Xilinx FPGA

Master SelectMAP

Xilinx FPGA

Slave SelectMAP

First

PROM

CLK

CCLK

DONE

CCLK

DONE

Cascaded

PROM

CLK

CE

(PROM 0)

(PROM 1)

CEO

OE/RESET

INIT_B

OE/RESET

(5)

TDI

TMS

TCK

TDO

CF

PROG_B

TDI

CF

(4)

BUSY

TMS

TCK

BUSY

TDI

TDO

TMS

TCK

GND

TDO

TDI

TMS

TCK

TMS

GND

TCK

TDO

GND

Notes:

1

2

3

For Mode pin connections and DONE pin pull-up value, refer to the appropriate FPGA data sheet.

For compatible voltages, refer to the appropriate data sheet.

CS_B (or CS) and RDWR_B (or WRITE) must be either driven Low or pulled down exernally. One option is shown.

4 The BUSY pin is only available with the XQF32P Platform Flash PROM, and the connection is only required for

high-frequency SelectMAP mode configuration. For BUSY pin requirements, refer to the appropriate FPGA data sheet.

5

For the XQF32P the CF pin is a bidirectional pin, and if CF is not connected to PROGB, then it must be tied to V

via a

CCO

4.7 kΩ pull-up resistor.

ds541_10_080406

Figure 10: Configuring Multiple Devices with Identical Patterns in Master/Slave SelectMAP Mode

DS541 (v1.0) November 27, 2006

www.xilinx.com

Product Specification

17

R

QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM

(2)

V

CCO

V

CCINT

V

CCJ

V

CCO

V

CCINT

V

CCO

CCJ

(1)

V

D[0:7]

MODE PINS

D[0:7]

MODE PINS

V

D[0:7]

CCINT

(2)

CCINT

(2)

CCO

(3)

I/O

CCO

(2)

RDWR_B

CCJ

CS_B

XQF32P

Platform Flash

PROM

Platform Flash

PROM

Xilinx FPGA

Master SelectMAP

Xilinx FPGA

Slave SelectMAP

First

PROM

CLK

CCLK

DONE

CCLK

DONE

Cascaded

PROM

CLK

CE

(PROM 0)

(PROM 1)

CEO

OE/RESET

INIT_B

OE/RESET

(5)

TDI

TMS

TCK

TDO

CF

PROG_B

TDI

CF

(4)

BUSY

TMS

TCK

BUSY

TDI

TDO

TMS

TCK

GND

TDO

TDI

TMS

TCK

TMS

GND

TCK

TDO

GND

Notes:

1

2

3

For Mode pin connections and DONE pin pull-up value, refer to the appropriate FPGA data sheet.

For compatible voltages, refer to the appropriate data sheet.

CS_B (or CS) and RDWR_B (or WRITE) must be either driven Low or pulled down exernally. One option is shown.

4 The BUSY pin is only available with the XQF32P Platform Flash PROM, and the connection is only required for

high-frequency SelectMAP mode configuration. For BUSY pin requirements, refer to the appropriate FPGA data sheet.

5

For the XQF32P the CF pin is a bidirectional pin, and if CF is not connected to PROGB, then it must be tied to V

via a

CCO

4.7 kΩ pull-up resistor.

ds541_11_080406

Figure 11: Configuring Multiple Devices with Design Revisioning in Slave Serial Mode

DS541 (v1.0) November 27, 2006

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Product Specification

18

R

QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM

(2)

V

CCJ

V

CCO

CCO CCINT

CCJ

CCO CCINT

(5)

External

Oscillator

(1)

VCCINT

(2)

V

D[0:7]

MODE PINS

D[0:7]

MODE PINS

CCINT

(2)

V

RDWR_B

CCO

(3)

I/O

(3)

(2)

I/O

V

CS_B

CCJ

XQF32P

Platform Flash

PROM

XQF32P

Platform Flash

PROM

Xilinx FPGA

Slave SelectMAP

Xilinx FPGA

Slave SelectMAP

(5)

First

PROM

(PROM 0)

Cascaded _CLK

PROM

(PROM 1)

CLK

CCLK

DONE

CCLK

DONE

CE

CEO

OE/RESET

INIT_B

(6)

TDI

CF

PROG_B

(4)

TMS

TCK

TDO

TMS

TCK

BUSY

TDI

TDO

TMS

TCK

TDO

TDI

TDO

TDI

TMS

TCK

TMS

EN_EXT_SEL

REV_SEL[1:0]

EN_EXT_SEL

REV_SEL[1:0]

TCK

TDO

GND

EN_EXT_SEL

REV_SEL[1:0]

CF

Design

Revision

Control

Logic

DONE

PROG_B

CS_B[1:0]

Notes:

1. For Mode pin connections and DONE pin pull-up value, refer to the appropriate FPGA data sheet.

2. For compatible voltages, refer to the appropriate data sheet.

3. RDWR_B (or WRITE) must be either driven Low or pulled down exernally. One option is shown.

4. The BUSY pin is only available with the XQF32P Platform Flash PROM, and the connection is only required for high

frequency SelectMAP mode configuration. For BUSY pin requirements, refer to the appropriate FPGA data sheet.

5. In Slave SelectMAP mode, the configuration interface can be clocked by an external oscillator, or optionally the

CLKOUT signal can be used to drive the FPGA's configuration clock (CCLK). If the XQF32P PROM's CLKOUT signal

is used, then it must be tied to a 4.7KΩ resistor pulled up to V

.

CCO

6

For the XQF32P the CF pin is a bidirectional pin, and if CF is not connected to PROGB, then must be tied to V

a 4.7 kΩ pull-up resistor

via

CCO

ds541_12_070906

Figure 12: Configuring Multiple Devices with Design Revisioning in Slave SelectMAP Mode

DS541 (v1.0) November 27, 2006

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Product Specification

19

R

QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM

Reset and Power-On Reset Activation

At power up, the device requires the V

power supply to

released, the FPGA’s INIT pin is pulled High allowing the

FPGA's configuration sequence to begin. If the power drops

CCINT

monotonically rise to the nominal operating voltage within

the specified V rise time. If the power supply cannot

below the power-down threshold (V

), the PROM resets

CCINT

CCPD

meet this requirement, then the device might not perform

power-on reset properly. During the power-up sequence,

OE/RESET is held Low by the PROM. Once the required

supplies have reached their respective POR (Power On

and OE/RESET is again held Low until the after the POR

threshold is reached. OE/RESET polarity is not

programmable. These power-up requirements are shown

graphically in Figure 13, page 20.

Reset) thresholds, the OE/RESET release is delayed (T

OER

For a fully powered Platform Flash PROM, a reset occurs

whenever OE/RESET is asserted (Low) or CE is

deasserted (High). The address counter is reset, CEO is

driven High, and the remaining outputs are placed in a

high-impedance state.

minimum) to allow more margin for the power supplies to

stabilize before initiating configuration. The OE/RESET pin

is connected to an external 4.7 kΩ pull-up resistor and also

to the target FPGA's INIT pin. For systems utilizing

slow-rising power supplies, an additional power monitoring

circuit can be used to delay the target configuration until the

system power reaches minimum operating voltages by

holding the OE/RESET pin Low. When OE/RESET is

Note: The XQF32P PROM requires both V_CCINTto rise above its

POR threshold and for V_CCOto reach the recommended operating

voltage level before releasing OE/RESET.

V_CCINT

Recommended Operating Range

Delay or Restart

Configuration

50 ms ramp

200 µs ramp

V_CCPOR

V_CCPD

A slow-ramping V

supply may still

CCINT

be below the minimum operating

voltage when OE/RESET is released.

In this case, the configuration

sequence must be delayed until both

V

and V

have reached their

CCINT

CCO

TIME (ms)

recommended operating conditions.

T_OER

T_RST

DS541_13_111706

Figure 13: Platform Flash PROM Power-Up Requirements

I/O Input Voltage Tolerance and Power Sequencing

The I/Os on each re-programmable Platform Flash PROM

are fully 3.3V tolerant. This allows 3V CMOS signals to

connect directly to the inputs without damage. The core

TDO must not be pulled Low, and TCK must be stopped

(High or Low).

When using the FPGA DONE signal to drive the PROM CE

pin High to reduce standby power after configuration, an

external pull-up resistor should be used. Typically a 330Ω

pull-up resistor is used, but refer to the appropriate FPGA

data sheet for the recommended DONE pin pull-up value. If

the DONE circuit is connected to an LED to indicate FPGA

configuration is complete, and is also connected to the

PROM CE pin to enable low-power standby mode, then an

external buffer should be used to drive the LED circuit to

ensure valid transitions on the PROM’s CE pin. If low-power

standby mode is not required for the PROM, then the CE pin

should be connected to ground.

power supply (V

), JTAG pin power supply (V

),

CCINT

CCJ

output power supply (V

), and external 3V CMOS I/O

CCO

signals can be applied in any order.

Standby Mode

The PROM enters a low-power standby mode whenever CE

is deasserted (High). In standby mode, the address counter

is reset, CEO is driven High, and the remaining outputs are

placed in a high-impedance state regardless of the state of

the OE/RESET input. For the device to remain in the

low-power standby mode, the JTAG pins TMS, TDI, and

DS541 (v1.0) November 27, 2006

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Product Specification

20

R

QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM

Table 7: Truth Table for XQF32P PROM Control Inputs

Control Inputs

Outputs

Internal Address

OE/RESET

CE

CF

BUSY⁽⁵⁾

DATA

CEO

CLKOUT

ICC

High

Low

High

Low

If address < TC⁽²⁾and

Active

High

Low

High

Active

address < EA⁽³⁾: increment

If address < TC⁽²⁾and

High-Z

Active

Reduced

Active

address = EA⁽³⁾: don't change

Else

If address = TC⁽²⁾: don't change

High

Low

High

Unchanged

Active and

Unchanged

High

Low

X

Low

High

¦

X⁽¹⁾

X

Reset⁽⁴⁾

Active

High-Z

High

Active

High-Z

Active

X

Held reset⁽⁴⁾

X

Standby

Notes:

1. X = don’t care.

2. TC = Terminal Count = highest address value.

3. For the XQF32P with Design Revisioning enabled, EA = end address (last address in the selected design revision).

4. For the XQF32P with Design Revisioning enabled, Reset = address reset to the beginning address of the selected bank. If Design

Revisioning is not enabled, then Reset = address reset to address 0.

5. The BUSY input is only enabled when the XQF32P is programmed for parallel data output and decompression is not enabled.

DS541 (v1.0) November 27, 2006

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Product Specification

21

R

QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM

DC Electrical Characteristics

Absolute Maximum Ratings

Symbol

Description

Internal supply voltage relative to GND

XQF32P

–0.5 to +2.7

–0.5 to +4.0

–0.5 to +3.6

–65 to +150

+125

Units

V

V_CCINT

V_CCO

V_CCJ

V_IN

I/O supply voltage relative to GND

JTAG I/O supply voltage relative to GND

Input voltage with respect to GND

V

V_CCO< 2.5V

V_CCO≥ 2.5V

V_CCO< 2.5V

V_CCO≥ 2.5V

V

V_TS

Voltage applied to High-Z output

V

T_STG

T_J

Storage temperature (ambient)

Junction temperature

°C

Notes:

1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device

pins can undershoot to –2.0V or overshoot to +7.0V, provided this over- or undershoot lasts less then 10 ns and with the forcing current being

limited to 200 mA.

2. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only,

and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.

Exposure to Absolute Maximum Ratings conditions for extended periods of time adversely affects device reliability.

3. For soldering guidelines, see the information on "Packaging and Thermal Characteristics" at www.xilinx.com.

Supply Voltage Requirements for Power-On Reset and Power-Down

XQF32P

Symbol

Description

Units

Min

0.2

0.5

–

Max

50

–

T_VCC

V_CCPOR

T_OER

V_CCINTrise time from 0V to nominal voltage⁽²⁾

POR threshold for the V_CCINTsupply

ms

V

OE/RESET release delay following POR⁽³⁾

30

0.5

–

ms

V

V_CCPD

T_RST

Power-down threshold for V_CCINTsupply

Time required to trigger a device reset when the V_CCINTsupply drops below the

maximum V_CCPDthreshold

10

ms

Notes:

1.

2. At power up, the device requires the V

V

, V

, and V

supplies can be applied in any order.

CCINT CCO

CCJ

power supply to monotonically rise to the nominal operating voltage within the specified T

CCINT

VCC

rise time. If the power supply cannot meet this requirement, then the device might not perform power-on-reset properly. See Figure 13,

page 20.

3. If the V

and V

supplies do not reach their respective recommended operating conditions before the OE/RESET pin is released,

CCINT

CCO

then the configuration data from the PROM is not be available at the recommended threshold levels. The configuration sequence must be

delayed until both V and V have reached their recommended operating conditions.

CCINT

CCO

DS541 (v1.0) November 27, 2006

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Product Specification

22

R

QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM

Recommended Operating Conditions

XQF32P

Typ

1.8

Symbol

Description

Units

Min

1.65

3.0

Max

2.0

V_CCINT

V_CCO

Internal voltage supply

V

Supply voltage for output drivers

3.3V Operation

2.5V Operation

1.8V Operation

1.5V Operation

3.3V Operation

3.3

3.6

2.3

2.5

2.7

1.7

1.8

1.9

TBD

3.0

1.5

TBD

3.6

V_CCJ

Supply voltage for JTAG output

drivers

3.3

2.5V Operation

2.3

2.5

–

2.7

0.8

V

ns

V

V_IL

Low-level input voltage

3.3V Operation

2.5V Operation

1.8V Operation

1.5V Operation

3.3V Operation

2.5V Operation

1.8V Operation

1.5V Operation

0

–

0.7

–

20% V_CCO

TBD

3.6

0

–

V_IH

High-level input voltage

2.0

–

1.7

–

3.6

70% V_CCO

–

3.6

TBD

–

3.6

T_IN

V_O

Input signal transition time⁽¹⁾

Output voltage

–

0

–

500

–

V_CCO

Notes:

1. Input signal transition time measured between 10% V

and 90% V

.

CCO

Quality and Reliability Characteristics

Symbol

T_DR

Description

Min

20

Max

Units

Years

Cycles

Volts

Data retention

–

N_PE

Program/erase cycles (Endurance)

Electrostatic discharge (ESD)

20,000

2,000

V_ESD

DS541 (v1.0) November 27, 2006

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Product Specification

23

R

QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM

DC Characteristics Over Operating Conditions

XQF32P

Min

Symbol

Description

Units

Test

Conditions

Max

V_OH

High-level output voltage for 3.3V outputs

High-level output voltage for 2.5V outputs

High-level output voltage for 1.8V outputs

High-level output voltage for 1.5V outputs

Low-level output voltage for 3.3V outputs

Low-level output voltage for 2.5V outputs

Low-level output voltage for 1.8V outputs

Low-level output voltage for 1.5V outputs

Internal voltage supply current, active mode

Output driver supply current, active serial mode

Output driver supply current, active parallel mode

JTAG supply current, active mode

I_OH= –4 mA

2.4

–

V

I_OH= –500 µA V_CCO– 0.4

I_OH= –50 µA V_CCO– 0.4

–

V

I_OH= TBD

I_OL= 4 mA

I_OL= 500 µA

I_OL= 50 µA

I_OL= TBD

33 MHz

TBD

–

V

V_OL

0.4

TBD

10

40

5

V

–

V

–

V

–

V

I_CCINT

–

mA

µA

(1)

I_CCO

33 MHz

–

33 MHz

–

I_CCJ

Note (2)

–

I_CCINTSInternal voltage supply current, standby mode

Note (3)

–

1

I_CCOS

I_CCJS

I_ILJ

Output driver supply current, standby mode

JTAG supply current, standby mode

Note (3)

–

1

Note (3)

–

1

JTAG pins TMS, TDI, and TDO pull-up current

V_CCJ= max

V_IN= GND

–

100

V_CCINT= max

I_IL

Input leakage current

–10

–

10

100

–

µA

V

_CCO= max

V

_IN= GND or

V_CCO

V_CCINT= max

_CCO= max

I_IH

Input and output High-Z leakage current

V

_IN= GND or

V_CCO

V_CCINT= max

_CCO= max

I_ILP

Source current through internal pull-ups on

EN_EXT_SEL, REV_SEL0, REV_SEL1

V

_IN= GND or

V_CCO

V_CCINT= max

_CCO= max

I_IHP

Sink current through internal pull-down on BUSY

-100

V

_IN= GND or

V_CCO

C_IN

Input capacitance

Output capacitance

V_IN= GND

f = 1.0 MHz

–

8

pF

C_OUT

V_IN= GND

f = 1.0 MHz

14

Notes:

1. Output driver supply current specification based on no load conditions.

2. TDI/TMS/TCK non-static (active).

3. CE High, OE Low, and TMS/TDI/TCK static.

DS541 (v1.0) November 27, 2006

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Product Specification

24

R

QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM

AC Electrical Characteristics

AC Characteristics Over Operating Conditions

XQF32P PROM as Configuration Slave with CLK Input Pin as Clock Source

T

SCE

CE

T

HCE

T

HOE

TCYC

OE/RESET

CLK

T

LC

T

HC

T

SB

T

HB

T

DF

OH

BUSY

T

OE

T

CAC

(optional)

T

CE

DATA

T

CF

OH

THCF

CF

EN_EXT_SEL

REV_SEL[1:0]

T

HXT

SXT

HXT

SXT

T

HRV

SRV

HRV

SRV

DS541_14_111706

XQF32P

Symbol

Description

Units

Min

Max

T_HCF

CF hold time to guarantee design revision selection is sampled when V_CCO= 3.3V or 2.5V⁽⁹⁾

CF hold time to guarantee design revision selection is sampled when V_CCO= 1.8V⁽⁹⁾

CF to data delay when VCCO = 3.3V or 2.5V⁽⁸⁾

300

–

ns

T_CF

T_OE

T_CE

T_CAC

T_OH

T_DF

25

30

–

CF to data delay when VCCO = 1.8V⁽⁸⁾

–

OE/RESET to data delay⁽⁶⁾when V_CCO= 3.3V or 2.5V

OE/RESET to data delay⁽⁶⁾when V_CCO= 1.8V

–

CE to data delay⁽⁵⁾when V_CCO= 3.3V or 2.5V

–

CE to data delay⁽⁵⁾when V_CCO= 1.8V

–

CLK to data delay⁽⁷⁾when V_CCO= 3.3V or 2.5V

–

CLK to data delay⁽⁷⁾when V_CCO= 1.8V

–

Data hold from CE, OE/RESET, CLK, or CF when V_CCO= 3.3V or 2.5V⁽⁸⁾

Data hold from CE, OE/RESET, CLK, or CF when V_CCO= 1.8V⁽⁸⁾

CE or OE/RESET to data float delay⁽²⁾when V_CCO= 3.3V or 2.5V

CE or OE/RESET to data float delay⁽²⁾when V_CCO= 1.8V

5

–

45

–

DS541 (v1.0) November 27, 2006

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Product Specification

25

R

QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM

XQF32P

Symbol

Description

Units

Min

30

Max

–

T_CYC

Clock period⁽⁶⁾(serial mode) when V_CCO= 3.3V or 2.5V

ns

Clock period⁽⁶⁾(serial mode) when V_CCO= 1.8V

30

Clock period⁽⁶⁾(parallel mode) when V_CCO= 3.3V or 2.5V

Clock period⁽⁶⁾(parallel mode) when V_CCO= 1.8V

35

T_LC

CLK Low time⁽³⁾when V_CCO= 3.3V or 2.5V

12

CLK Low time⁽³⁾when V_CCO= 1.8V

12

T_HC

CLK High time⁽³⁾when V_CCO= 3.3V or 2.5V

12

CLK High time⁽³⁾when V_CCO= 1.8V

12

T_SCE

T_HCE

T_HOE

T_SB

CE setup time to CLK (guarantees proper counting)⁽³⁾when V_CCO= 3.3V or 2.5V

CE setup time to CLK (guarantees proper counting)⁽³⁾when V_CCO= 1.8V

CE hold time (guarantees counters are reset)⁽⁵⁾when V_CCO= 3.3V or 2.5V

CE hold time (guarantees counters are reset)⁽⁵⁾when V_CCO= 1.8V

OE/RESET hold time (guarantees counters are reset)⁽⁶⁾when V_CCO= 3.3V or 2.5V

OE/RESET hold time (guarantees counters are reset)⁽⁶⁾when V_CCO= 1.8V

BUSY setup time to CLK when V_CCO= 3.3V or 2.5V⁽⁸⁾

30

2000

12

BUSY setup time to CLK when V_CCO= 1.8V⁽⁸⁾

12

T_HB

BUSY hold time to CLK when V_CCO= 3.3V or 2.5V⁽⁸⁾

8

BUSY hold time to CLK when V_CCO= 1.8V⁽⁸⁾

8

T_SXT

T_HXT

T_SRV

T_HRV

EN_EXT_SEL setup time to CF, CE or OE/RESET when V_CCO= 3.3V or 2.5V⁽⁸⁾

EN_EXT_SEL setup time to CF, CE or OE/RESET when V_CCO= 1.8V⁽⁸⁾

EN_EXT_SEL hold time from CF, CE or OE/RESET when V_CCO= 3.3V or 2.5V⁽⁸⁾

EN_EXT_SEL hold time from CF, CE or OE/RESET when V_CCO= 1.8V⁽⁸⁾

REV_SEL setup time to CF, CE or OE/RESET when V_CCO= 3.3V or 2.5V⁽⁸⁾

REV_SEL setup time to CF, CE or OE/RESET when V_CCO= 1.8V⁽⁸⁾

REV_SEL hold time from CF, CE or OE/RESET when V_CCO= 3.3V or 2.5V⁽⁸⁾

REV_SEL hold time from CF, CE or OE/RESET when V_CCO= 1.8V⁽⁸⁾

300

Notes:

1. AC test load = 30 pF for XQF32P.

2. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady-state active levels.

3. All AC parameters are measured with V = 0.0V and V = 3.0V.

IL

IH

4. If T

5. If T

High < 2 µs, T = 2 µs.

CE

HCE

Low < 2 µs, T = 2 µs.

HOE

OE

6. This is the minimum possible T

. Actual T

= T

+ FPGA Data setup time. Example: With the XCF32P in serial mode with V

CCO

at

CYC

CAC

3.3V, if FPGA data setup time = 15 ns, then the actual T

= 25 ns +15 ns = 40 ns.

CYC

7. Guaranteed by design; not tested.

8. CF, EN_EXT_SEL, REV_SEL[1:0], and BUSY are inputs.

9. When JTAG CONFIG command is issued, PROM drives CF Low for at least the T

minimum.

HCF

DS541 (v1.0) November 27, 2006

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Product Specification

26

R

QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM

XQF32P PROM as Configuration Master with CLK Input Pin as Clock Source

CE

T

HCE

T

HOE

OE/RESET

CLK

TCYCO

T

LC

HC

T

CLKO

CLKOUT

T

CECC

T

SB

T

HB

T

CCDD

DDC

OECC

T

CECF

T

COH

BUSY

T

OE

T

OECF

(optional)

T

CE

DATA

T

CF

T

EOH

T

CFCC

T

DF

THCF

CF

EN_EXT_SEL

REV_SEL[1:0]

T

HXT

SXT

HXT

SXT

T

HRV

SRV

HRV

SRV

Note: 8 CLKOUT cycles are output after CE rising edge, before CLKOUT

tristates, if OE/RESET remains high, and terminal count has not been reached.

DS541_15_111706

XQF32P

Symbol

Description

Units

300

Min

Max

T_HCF

CF hold time to guarantee design revision selection is sampled

when V_CCO= 3.3V or 2.5V⁽¹¹⁾

300

CF hold time to guarantee design revision selection is sampled

when V_CCO= 1.8V⁽¹¹⁾

300

T_CF

CF to data delay when VCCO = 3.3V or 2.5V

CF to data delay when VCCO = 1.8V

–

5

–

TBD

30

ns

T_OE

OE/RESET to data delay⁽⁶⁾when V_CCO= 3.3V or 2.5V

OE/RESET to data delay⁽⁶⁾when V_CCO= 1.8V

CE to data delay⁽⁵⁾when V_CCO= 3.3V or 2.5V

CE to data delay⁽⁵⁾when V_CCO= 1.8V

30

T_CE

30

T_EOH

Data hold from CE, OE/RESET, or CF when V_CCO= 3.3V or 2.5V

Data hold from CE, OE/RESET, or CF when V_CCO= 1.8V

CE or OE/RESET to data float delay⁽²⁾when V_CCO= 3.3V or 2.5V

CE or OE/RESET to data float delay⁽²⁾when V_CCO= 1.8V

OE/RESET to CLKOUT float delay⁽²⁾when V_CCO= 3.3V or 2.5V

OE/RESET to CLKOUT float delay⁽²⁾when V_CCO= 1.8V

CE to CLKOUT float delay⁽²⁾when V_CCO= 3.3V or 2.5V

CE to CLKOUT float delay⁽²⁾when V_CCO= 1.8V

–

T_DF

45

T_OECF

TBD

T_CECF

DS541 (v1.0) November 27, 2006

www.xilinx.com

Product Specification

27

R

QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM

XQF32P

Symbol

Description

Units

Min

30

Max

–

T_CYCO

Clock period⁽⁷⁾(serial mode) when V_CCO= 3.3V or 2.5V

Clock period⁽⁷⁾(serial mode) when V_CCO= 1.8V

ns

30

–

Clock period⁽⁷⁾(parallel mode) when V_CCO= 3.3V or 2.5V

Clock period⁽⁷⁾(parallel mode) when V_CCO= 1.8V

35

–

35

–

T_LC

CLK Low time⁽³⁾when V_CCO= 3.3V or 2.5V

12

–

CLK Low time⁽³⁾when V_CCO= 1.8V

12

–

T_HC

CLK High time⁽³⁾when V_CCO= 3.3V or 2.5V

12

–

CLK High time⁽³⁾when V_CCO= 1.8V

12

–

T_HCE

T_HOE

T_SB

CE hold time (guarantees counters are reset)⁽⁵⁾when V_CCO= 3.3V or 2.5V

CE hold time (guarantees counters are reset)⁽⁵⁾when V_CCO= 1.8V

OE/RESET hold time (guarantees counters are reset)⁽⁶⁾when V_CCO= 3.3V or 2.5V

OE/RESET hold time (guarantees counters are reset)⁽⁶⁾when V_CCO= 1.8V

BUSY setup time to CLKOUT when V_CCO= 3.3V or 2.5V

BUSY setup time to CLKOUT when V_CCO= 1.8V

2000

12

–

12

–

T_HB

BUSY hold time to CLKOUT when V_CCO= 3.3V or 2.5V

BUSY hold time to CLKOUT when V_CCO= 1.8V

8

–

8

–

T_CLKO

CLK input to CLKOUT output delay when V_CCO= 3.3V or 2.5V

CLK input to CLKOUT output delay when V_CCO= 1.8V

–

35

–

CLK input to CLKOUT output delay when V_CCO= 3.3V or 2.5V

with decompression⁽¹⁰⁾

–

CLK input to CLKOUT output delay when V_CCO= 1.8V with decompression⁽¹⁰⁾

CE to CLKOUT delay⁽⁸⁾when V_CCO= 3.3V or 2.5V

–

0

35

ns

–

T_CECC

2 CLK

cycles

CE to CLKOUT delay⁽⁸⁾when V_CCO= 1.8V

0

2 CLK

cycles

–

T_OECC

2 CLK

cycles

OE/RESET to CLKOUT delay⁽⁸⁾when V_CCO= 3.3V or 2.5V

OE/RESET to CLKOUT delay⁽⁸⁾when V_CCO= 1.8V

2 CLK

cycles

T_CFCC

T_CCDD

T_DDC

CF to CLKOUT delay⁽⁸⁾when V_CCO= 3.3V or 2.5V

0

TBD

32

–

CF to CLKOUT delay⁽⁸⁾when V_CCO= 1.8V

–

CLKOUT to data delay when V_CCO= 3.3V or 2.5V⁽⁹⁾

–

ns

CLKOUT to data delay when V_CCO= 1.8V⁽⁹⁾

–

32

Data setup time to CLKOUT when V_CCO= 3.3V or 2.5V with decompression^(9)(10)

Data setup time to CLKOUT when V_CCO= 1.8V with decompression^(9)(10)

Data hold from CLKOUT when V_CCO= 3.3V or 2.5V

5

T_COH

3

–

Data hold from CLKOUT when V_CCO= 1.8V

3

Data hold from CLKOUT when V_CCO= 3.3V or 2.5V with decompression⁽¹⁰⁾

Data hold from CLKOUT when V_CCO= 1.8V with decompression⁽¹⁰⁾

EN_EXT_SEL setup time to CF, CE, or OE/RESET when V_CCO= 3.3V or 2.5V

EN_EXT_SEL setup time to CF, CE, or OE/RESET when V_CCO= 1.8V

3

T_SXT

300

DS541 (v1.0) November 27, 2006

www.xilinx.com

Product Specification

28

R

QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM

XQF32P

Symbol

Description

Units

Min

300

Max

T_HXT

EN_EXT_SEL hold time from CF, CE, or OE/RESET when V_CCO= 3.3V or 2.5V

EN_EXT_SEL hold time from CF, CE, or OE/RESET when V_CCO= 1.8V

REV_SEL setup time to CF, CE, or OE/RESET when V_CCO= 3.3V or 2.5V

REV_SEL setup time to CF, CE, or OE/RESET when V_CCO= 1.8V

REV_SEL hold time from CF, CE, or OE/RESET when V_CCO= 3.3V or 2.5V

REV_SEL hold time from CF, CE, or OE/RESET when V_CCO= 1.8V

–

ns

T_SRV

T_HRV

Notes:

1. AC test load = 30 pF for XQF32P.

2. Float delays are measured with 5 pF AC loads.Transition is measured at 200 mV from steady-state active levels.

3. Guaranteed by design, not tested.

4. All AC parameters are measured with V = 0.0V and V = 3.0V.

IL

IH

5. If T

6. If T

High < 2 µs, T = 2 µs.

CE

HCE

Low < 2 µs, T = 2 µs.

HOE

OE

7. This is the minimum possible T

. Actual T

= T

+ FPGA Data setup time. Example: With the XQF32P in serial mode with V

CYCO

CCDD CCO

at 3.3V, if FPGA Data setup time = 15 ns, then the actual T

= 25 ns +15 ns = 40 ns.

CYCO

8. The delay before the enabled CLKOUT signal begins clocking data out of the device is dependent on the clocking configuration. The delay

before CLKOUT is enabled increases if decompression is enabled.

9. Slower CLK frequency option can be required to meet the FPGA data sheet setup time.

10. When decompression is enabled, the CLKOUT signal becomes a controlled clock output. When decompressed data is available, CLKOUT

toggles at ½ the source clock frequency (either ½ the selected internal clock frequency or ½ the external CLK input frequency). When

decompressed data is not available, the CLKOUT pin is parked High. If CLKOUT is used, then it must be pulled High externally using a 4.7kΩ

pull-up to V

.

CCO

11. When JTAG CONFIG command is issued, PROM drives CF Low for at least the T

minimum.

HCF

DS541 (v1.0) November 27, 2006

www.xilinx.com

Product Specification

29

R

QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM

XQF32P PROM as Configuration Master with Internal Oscillator as Clock Source

CE

T

HCE

T

HOE

OE/RESET

CLKOUT

T

CEC

T

HB

SB

T

DDC

T

CDD

COH

OEC

T

CECF

OECF

BUSY

T

OE

(optional)

T

CE

DATA

T

CF

T

EOH

T

CFC

HXT

T

DF

THCF

CF

EN_EXT_SEL

REV_SEL[1:0]

T

HXT

SXT

T

HRV

T

HRV

SRV

Note: 8 CLKOUT cycles are output after CE rising edge, before CLKOUT

tristates, if OE/RESET remains high, and terminal count has not been reached.

DS541_16_111706

XQF32P

Symbol

Description

Units

Min

Max

T_HCF

CF hold time to guarantee design revision selection is sampled

when V_CCO= 3.3V or 2.5V⁽¹²⁾

300

CF hold time to guarantee design revision selection is sampled

when V_CCO= 1.8V⁽¹²⁾

300

T_CF

CF to data delay when VCCO = 3.3V or 2.5V

–

5

–

TBD

30

–

ns

CF to data delay when VCCO = 1.8V

T_OE

OE/RESET to data delay⁽⁶⁾when V_CCO= 3.3V or 2.5V

OE/RESET to data delay⁽⁶⁾when V_CCO= 1.8V

CE to data delay⁽⁵⁾when V_CCO= 3.3V or 2.5V

CE to data delay⁽⁵⁾when V_CCO= 1.8V

T_CE

T_EOH

Data hold from CE, OE/RESET, or CF when V_CCO= 3.3V or 2.5V

Data hold from CE, OE/RESET, or CF when V_CCO= 1.8V

CE or OE/RESET to data float delay⁽²⁾when V_CCO= 3.3V or 2.5V

CE or OE/RESET to data float delay⁽²⁾when V_CCO= 1.8V

OE/RESET to CLKOUT float delay⁽²⁾when V_CCO= 3.3V or 2.5V

OE/RESET to CLKOUT float delay⁽²⁾when V_CCO= 1.8V

CE to CLKOUT float delay⁽²⁾when V_CCO= 3.3V or 2.5V

CE to CLKOUT float delay⁽²⁾when V_CCO= 1.8V

CE hold time (guarantees counters are reset)⁽⁵⁾when V_CCO= 3.3V or 2.5V

CE hold time (guarantees counters are reset)⁽⁵⁾when V_CCO= 1.8V

OE/RESET hold time (guarantees counters are reset)⁽⁶⁾when V_CCO= 3.3V or 2.5V

OE/RESET hold time (guarantees counters are reset)⁽⁶⁾when V_CCO= 1.8V

BUSY setup time to CLKOUT when V_CCO= 3.3V or 2.5V

–

T_DF

45

TBD

–

T_OECF

T_CECF

T_HCE

T_HOE

T_SB

2000

12

–

BUSY setup time to CLKOUT when V_CCO= 1.8V

12

–

DS541 (v1.0) November 27, 2006

www.xilinx.com

Product Specification

30

R

QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM

XQF32P

Symbol

Description

Units

Min

8

Max

–

T_HB

BUSY hold time to CLKOUT when V_CCO= 3.3V or 2.5V

BUSY hold time to CLKOUT when V_CCO= 1.8V

ns

8

–

T_CEC

T_OEC

T_CFC

T_CDD

T_DDC

T_COH

CE to CLKOUT delay⁽⁷⁾when V_CCO= 3.3V or 2.5V

CE to CLKOUT delay⁽⁷⁾when V_CCO= 1.8V

OE/RESET to CLKOUT delay⁽⁷⁾when V_CCO= 3.3V or 2.5V

OE/RESET to CLKOUT delay⁽⁷⁾when V_CCO= 1.8V

CF to CLKOUT delay⁽⁷⁾when V_CCO= 3.3V or 2.5V

CF to CLKOUT delay⁽⁷⁾when V_CCO= 1.8V

CLKOUT to data delay when V_CCO= 3.3V or 2.5V⁽⁸⁾

CLKOUT to data delay when V_CCO= 1.8V⁽⁸⁾

0

1

µs

0

1

µs

0

1

µs

0

1

µs

0

TBD

30

–

0

–

ns

–

ns

Data setup time to CLKOUT when V_CCO= 3.3V or 2.5V with decompression^(8)(11)

Data setup time to CLKOUT when V_CCO= 1.8V with decompression^(8)(11)

Data hold from CLKOUT when V_CCO= 3.3V or 2.5V

5

ns

5

ns

3

–

ns

Data hold from CLKOUT when V_CCO= 1.8V

3

ns

Data hold from CLKOUT when V_CCO= 3.3V or 2.5V with decompression⁽¹¹⁾

Data hold from CLKOUT when V_CCO= 1.8V with decompression⁽¹¹⁾

EN_EXT_SEL setup time to CF, CE, or OE/RESET when V_CCO= 3.3V or 2.5V

EN_EXT_SEL setup time to CF, CE, or OE/RESET when V_CCO= 1.8V

EN_EXT_SEL hold time from CF, CE, or OE/RESET when V_CCO= 3.3V or 2.5V

EN_EXT_SEL hold time from CF, CE, or OE/RESET when V_CCO= 1.8V

REV_SEL setup time to CF, CE, or OE/RESET when V_CCO= 3.3V or 2.5V

REV_SEL setup time to CF, CE, or OE/RESET when V_CCO= 1.8V

REV_SEL hold time from CF, CE, or OE/RESET when V_CCO= 3.3V or 2.5V

REV_SEL hold time from CF, CE, or OE/RESET when V_CCO= 1.8V

CLKOUT default (fast) frequency⁽⁹⁾

3

–

ns

3

–

ns

T_SXT

T_HXT

T_SRV

T_HRV

F_F

300

25

12.5

6

–

ns

–

ns

–

ns

–

ns

–

ns

–

ns

–

ns

–

ns

50

25

12.5

MHz

CLKOUT default (fast) frequency with decompression⁽¹¹⁾

CLKOUT alternate (slower) frequency⁽¹⁰⁾

CLKOUT alternate (slower) frequency with decompression⁽¹¹⁾

F_S

Notes:

1. AC test load = 30 pF for XQF32P.

2. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady-state active levels.

3. Guaranteed by design, not tested.

4. All AC parameters are measured with V = 0.0V and V = 3.0V.

IL

IH

5. If T

6. If T

High < 2 µs, T = 2 µs.

CE

HCE

Low < 2 µs, T = 2 µs.

HOE

OE

7. The delay before the enabled CLKOUT signal begins clocking data out of the device is dependent on the clocking configuration. The delay

before CLKOUT is enabled increases if decompression is enabled.

8. Slower CLK frequency option can be required to meet the FPGA data sheet setup time.

9. Typical CLKOUT default (fast) period = 25 ns (40 MHz)

10. Typical CLKOUT alternate (slower) period = 50 ns (20 MHz)

11. When decompression is enabled, the CLKOUT signal becomes a controlled clock output. When decompressed data is available, CLKOUT

toggles at ½ the source clock frequency (either ½ the selected internal clock frequency or ½ the external CLK input frequency). When

decompressed data is not available, the CLKOUT pin is parked High. If CLKOUT is used, then it must be pulled High externally using a 4.7kΩ

pull-up to V

.

CCO

12. When JTAG CONFIG command is issued, PROM drives CF Low for at least the T

minimum.

HCF

DS541 (v1.0) November 27, 2006

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Product Specification

31

R

QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM

AC Characteristics Over Operating Conditions When Cascading

OE/RESET

CE

CLK

CLKOUT

(optional)

T

CDF

CODF

DATA

CEO

Last Bit

First Bit

T

OCE

OOE

T

OCK

COCE

DS541_17_111706

XQF32P

Symbol

Description

Units

Min

–

Max

25

20

80

25

30

T_CDF

CLK to output float delay^(2,3)when V_CCO= 2.5V or 3.3V

CLK to output float delay^(2,3)when V_CCO= 1.8V

CLK to CEO delay^(3,5)when V_CCO= 2.5V or 3.3V

CLK to CEO delay^(3,5)when V_CCO= 1.8V

CE to CEO delay^(3,6)when V_CCO= 2.5V or 3.3V

CE to CEO delay^(3,6)when V_CCO= 1.8V

OE/RESET to CEO delay⁽³⁾when V_CCO= 2.5V or 3.3V

OE/RESET to CEO delay⁽³⁾when V_CCO= 1.8V

CLKOUT to CEO delay when V_CCO= 2.5V or 3.3V

CLKOUT to CEO delay when V_CCO= 1.8V

ns

–

T_OCK

–

T_OCE

–

T_OOE

–

T_COCE

–

T_CODF

CLKOUT to output float delay when V_CCO= 2.5V or 3.3V

CLKOUT to output float delay when V_CCO= 1.8V

–

Notes:

1. AC test load = 30 pF for XQF32P.

2. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels.

3. Guaranteed by design, not tested.

4. All AC parameters are measured with V_IL= 0.0V and V_IH= 3.0V.

5. For cascaded PROMs, if the FPGA’s dual-purpose configuration data pins are set to persist as configuration pins, the minimum

period is increased based on the CLK to CEO and CE to data propagation delays:

- T_CYCminimum = T_OCK+ T_CE+ FPGA Data setup time.

- T_CACmaximum = T_OCK+ T_CE

6. For cascaded PROMs, if the FPGA’s dual-purpose configuration data pins become general I/O pins after configuration; to allow for

the disable to propagate to the cascaded PROMs and to avoid contention on the data lines following configuration, the minimum

period is increased based on the CE to CEO and CE to data propagation delays:

- T_CYCminimum = T_OCE+ T_CE

- T_CACmaximum = T_OCK+ T_CE

DS541 (v1.0) November 27, 2006

www.xilinx.com

Product Specification

32

R

QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM

Pinouts and Pin Descriptions

XQF32P VO48 Pin Names and Descriptions

The XQF32P Platform Flash PROM is available in the VO48 package. Table 8 provides a list of the pin names and

descriptions for the XQF32P 48-pin VO48 plastic, thin, small outline package (TSOP).

Table 8: XQF32P Pin Names and Descriptions (VO48)

Boundary

Scan

Function

48-pin

TSOP

(VO48)

Boundary

Scan Order

Pin Name

Pin Description

D0

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

01

Data Out

Output Enable

Data Out

D0 is the DATA output pin to provide data for configuring an FPGA in

serial mode.

D0-D7 are the DATA output pins to provide parallel data for configuring a

Xilinx FPGA in SelectMap (parallel) mode.

The D0 output is set to a high-impedance state during ISPEN (when not

clamped).

The D1-D7 outputs are set to a high-impedance state during ISPEN

(when not clamped) and when serial mode is selected for configuration.

The D1-D7 pins can be left unconnected when the PROM is used in serial

mode.

28

29

32

33

43

44

47

48

12

D1

D2

D3

D4

D5

D6

D7

CLK

Output Enable

Data Out

Output Enable

Data Out

Output Enable

Data Out

Output Enable

Data Out

Output Enable

Data Out

Output Enable

Data Out

Output Enable

Data In

Configuration Clock Input. An internal programmable control bit selects

between the internal oscillator and the CLK input pin as the clock source

to control the configuration sequence. Each rising edge on the CLK input

increments the internal address counter if the CLK input is selected, CE

is Low, OE/RESET is High, BUSY is Low (parallel mode only), and CF is

High.

OE/RESET

04

03

02

Data In

Data Out

Output Enable/Reset (Open-Drain I/O).

11

When Low, this input holds the address counter reset and the DATA and

CLKOUT outputs are placed in a high-impedance state. This is a

bidirectional open-drain pin that is held Low while the PROM completes

the internal power-on reset sequence. Polarity is not programmable.

Output Enable

CE

CF

00

Data In

Chip Enable Input. When CE is High, the device is put into low-power

standby mode, the address counter is reset, and the DATA and CLKOUT

outputs are placed in a high-impedance state.

13

6

11

10

09

Data In

Data Out

Configuration Pulse (Open-Drain I/O). As an output, this pin allows the

JTAG CONFIG instruction to initiate FPGA configuration without

powering down the FPGA. This is an open-drain signal that is pulsed Low

by the JTAG CONFIG command. As an input, on the rising edge of CF,

the current design revision selection is sampled and the internal address

counter is reset to the start address for the selected revision. If unused,

the CF pin must be pulled High using an external 4.7 KΩpull-up to V_CCO

.

Output Enable

CEO

06

05

Data Out

Chip Enable Output. Chip Enable Output (CEO) is connected to the CE

input of the next PROM in the chain. This output is Low when CE is Low

and OE/RESET input is High, AND the internal address counter has been

incremented beyond its Terminal Count (TC) value. CEO returns to High

when OE/RESET goes Low or CE goes High.

10

Output Enable

DS541 (v1.0) November 27, 2006

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Product Specification

33

R

QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM

Table 8: XQF32P Pin Names and Descriptions (VO48) (Continued)

Boundary

48-pin

TSOP

(VO48)

Pin Name

Scan

Pin Description

Scan Order

Function

EN_EXT_SEL

31

Data In

Enable External Selection Input. When this pin is Low, design revision

selection is controlled by the Revision Select pins. When this pin is High,

design revision selection is controlled by the internal programmable

Revision Select control bits. EN_EXT_SEL has an internal 50KΩresistive

pull-up to V_CCOto provide a logic 1 to the device if the pin is not driven.

25

REV_SEL0

REV_SEL1

30

29

Data In

Revision Select[1:0] Inputs. When the EN_EXT_SEL is Low, the Revision

Select pins are used to select the design revision to be enabled,

overriding the internal programmable Revision Select control bits. The

Revision Select[1:0] inputs have an internal 50 KΩ resistive pull-up to

V_CCOto provide a logic 1 to the device if the pins are not driven.

26

27

BUSY

12

Data In

Busy Input. The BUSY input is enabled when parallel mode is selected

for configuration. When BUSY is High, the internal address counter stops

incrementing and the current data remains on the data pins. On the first

rising edge of CLK after BUSY transitions from High to Low, the data for

the next address is driven on the data pins. When serial mode or

decompression is enabled during device programming, the BUSY input

is disabled. BUSY has an internal 50 KΩ resistive pull-down to GND to

provide a logic 0 to the device if the pin is not driven.

5

CLKOUT

08

07

Data Out

Configuration Clock Output. An internal Programmable control bit

enables the CLKOUT signal, which is sourced from either the internal

oscillator or the CLK input pin. Each rising edge of the selected clock

source increments the internal address counter if data is available, CE is

Low, and OE/RESET is High. Output data is available on the rising edge

of CLKOUT. CLKOUT is disabled if CE is High or OE/RESET is Low. If

decompression is enabled, CLKOUT is parked High when decompressed

data is not ready. When CLKOUT is disabled, the CLKOUT pin is put into

a high-Z state. If CLKOUT is used, then it must be pulled High externally

9

Output Enable

using a 4.7 KΩ pull-up to V_CCO

.

TMS

Mode Select JTAG Mode Select Input. The state of TMS on the rising edge of TCK

determines the state transitions at the Test Access Port (TAP) controller.

TMS has an internal 50 KΩ resistive pull-up to V_CCJto provide a logic 1

to the device if the pin is not driven.

21

TCK

TDI

Clock

JTAG Clock Input. This pin is the JTAG test clock. It sequences the TAP

controller and all the JTAG test and programming electronics.

20

19

Data In

JTAG Serial Data Input. This pin is the serial input to all JTAG instruction

and data registers. TDI has an internal 50 KΩresistive pull-up to V_CCJto

provide a logic 1 to the device if the pin is not driven.

TDO

Data Out

JTAG Serial Data Output. This pin is the serial output for all JTAG

instruction and data registers. TDO has an internal 50KΩresistive pull-up

to V_CCJto provide a logic 1 to the system if the pin is not driven.

22

VCCINT

VCCO

+1.8V Supply. Positive 1.8V supply voltage for internal logic.

4, 15, 34

+3.3V, 2.5V, or 1.8V I/O Supply. Positive 3.3V, 2.5V, or 1.8V supply

voltage connected to the output voltage drivers and input buffers.

8, 30,

38, 45

VCCJ

GND

DNC

+3.3V or 2.5V JTAG I/O Supply. Positive 3.3V, 2.5V, or 1.8V supply

voltage connected to the TDO output voltage driver and TCK, TMS, and

TDI input buffers.

24

Ground

2, 7,

17, 23,

31, 36, 46

Do Not Connect. (These pins must be left unconnected.)

1, 3,

14, 16,

18, 35,37,

39, 40,41,

42

DS541 (v1.0) November 27, 2006

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Product Specification

34

R

QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM

XQF32P VO48 Pinout Diagram

DNC

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

D7

D6

GND

VCCO

D5

D4

DNC

VCCO

DNC

GND

DNC

VCCINT

D3

D2

GND

VCCO

D1

GND

2

DNC

3

VCCINT

4

BUSY

5

CF

6

GND

7

VCCO

8

CLKOUT

9

CEO

10

OE/RESET

11

VO48

Top

View

CLK

12

CE

13

DNC

14

VCCINT

15

DNC

16

GND

17

DNC

18

TDI

19

TCK

20

TMS

D0

21

TDO

REV_SEL1

REV_SEL0

EN_EXT_SEL

22

GND

23

VCCJ

24

ds541_18_111706

Figure 14: VO48 Pinout Diagram (Top View) with Pin Names

DS541 (v1.0) November 27, 2006

www.xilinx.com

Product Specification

35

R

QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM

Ordering Information

XQF32P VO48 M

Device Number

Operating Range/Processing

XQF32P

M = (T = –55° C to +125°C)

Package Type

VO48 = 48-pin TSOP Package

J

Valid Ordering Combinations

XCF32PVO48 M

Marking Information

XQF32P-V048

Device Number

Operating Range/Processing

XQF32P

M = (T = –55°C to +125°C)

Package Type

VO48 = 48-pin TSOP Package (VO48)

J

Revision History

The following table shows the revision history for this document.

Date

Version

Revision

11/27/06

1.0

Xilinx Initial Release.

DS541 (v1.0) November 27, 2006

www.xilinx.com

Product Specification

36


型号：	XCF32PVO48M
厂家：	XILINX, INC
描述：	Configuration Memory, 32MX1, Serial, CMOS, PDSO48, PLASTIC, TSOP-48 光电二极管内存集成电路
文件：	总36页 (文件大小：797K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

XCF32PVO48M [XILINX]

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