XCR22LV10-15SO24I [XILINX]
TotalCMOS, Universal PLD Device; TotalCMOS ，通用PLD器件
| 型号： | XCR22LV10-15SO24I |
| 厂家： | 
XILINX, INC |
| 描述： | TotalCMOS, Universal PLD Device |
| 文件： | 总14页 (文件大小：210K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0
R
XCR22LV10: 3V Zero Power,
TotalCMOS, Universal PLD Device
0
0*
DS047 (v1.1) February 10, 2000
Product Specification
Features
Description
•
Industry's first TotalCMOS™ SPLD - both CMOS
design and process technologies
Fast Zero Power (FZP™) design technique provides
ultra-low power and high speed
The XCR22LV10 is the first SPLD to combine high perfor-
mance with low power, without the need for "turbo bits" or
other power down schemes. To achieve this, Xilinx has
used their FZP design technique, which replaces conven-
tional sense amplifier methods for implementing product
terms (a technique that has been used in PLDs since the
bipolar era) with a cascaded chain of pure CMOS gates.
This results in the combination of low power and high
speed that has previously been unattainable in the PLD
arena. For 5V operation, Xilinx offers the XCR22V10 that
offers high speed and low power in a 5V implementation.
•
-
-
Static current of less than 45 µA
Dynamic current substantially below that of
competing devices
-
Pin-to-pin delay of only 10 ns
•
•
•
True Zero Power device with no turbo bits or power
down schemes
Function/JEDEC map compatible with Bipolar,
UVCMOS, EECMOS 22V10s
Multiple packaging options featuring PCB-friendly
flow-through pinouts (SOL and TSSOP)
The XCR22LV10 uses the familiar AND/OR logic array
structure, which allows direct implementation of
sum-of-products equations. This device has a programma-
ble AND array which drives a fixed OR array. The OR sum
of products feeds an "Output Macro Cell" (OMC), which can
be individually configured as a dedicated input, a combina-
torial output, or a registered output with internal feedback.
-
24-pin TSOIC–uses 93% less in-system space than
a 28-pin PLCC
-
-
24-pin SOIC
28-pin PLCC with standard JEDEC pinout
•
•
Available in commercial and industrial operating ranges
Supports mixed voltage systems—5V tolerant I/Os
Functional Description
The XCR22LV10 implements logic functions as
2
•
•
•
•
Advanced 0.5µ E CMOS process
1000 erase/program cycles guaranteed
20 years data retention guaranteed
Varied product term distribution with up to 16 product
terms per output for complex functions
Programmable output polarity
Synchronous preset/asynchronous reset capability
Security bit prevents unauthorized access
Electronic signature for identification
Design entry and verification using industry standard
CAE tools
sum-of-products expressions in
a
programmable-
AND/fixed-OR logic array. User-defined functions are cre-
ated by programming the connections of input signals into
the array. User-configurable output structures in the form of
I/O macrocells further increase logic flexibility (Figure 1).
•
•
•
•
•
•
Reprogrammable using industry standard device
programmers
DS047 (v1.1) February 10, 2000
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1
1-800-255-7778
.
CLK/I0
1
24
V
CC
0
3
4
7
8
11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 40 43
AR
0
1
1
1
0
0
0
1
0
1
AR
D
23 F9
22 F8
21 F7
20 F6
19 F5
18 F4
17 F3
16 F2
15 F1
14 F0
Q
Q
9
SP
0
1
10
20
1
1
0
0
0
1
0
1
AR
D
Q
Q
SP
0
1
I1
I2
I3
I4
I5
I6
I7
I8
2
3
4
5
6
7
8
9
21
1
1
0
0
0
1
0
1
AR
D
Q
Q
SP
33
34
0
1
1
1
0
0
0
1
0
1
AR
D
Q
Q
SP
48
49
0
1
1
1
0
0
0
1
0
1
AR
D
Q
Q
SP
65
66
0
1
1
1
0
0
0
1
0
1
AR
D
Q
Q
SP
82
83
0
1
1
1
0
0
0
1
0
1
AR
D
Q
Q
SP
97
98
0
1
1
1
0
0
0
1
0
1
AR
D
Q
Q
SP
110
0
1
111
121
1
1
0
0
0
1
0
1
AR
D
Q
Q
SP
0
1
122
130
1
1
0
0
0
1
0
1
AR
D
Q
Q
SP
0
1
I9 10
I10 11
SP
131
13 I11
0
3
4
7
8
11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 40 43
GND 12
NOTE:
SP00059
Figure 1: XCR22LV10 Logic Diagram
DS047 (v1.1) February 10, 2000
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XCR22LV10: 3V Zero Power, TotalCMOS, Universal PLD
44 input lines:
Architecture Overview
•
24 input lines carry the True and Complement of the
signals applied to the 12 input pins
The XCR22LV10 architecture is illustrated in Figure. Twelve
dedicated inputs and ten I/Os provide up to 22 inputs and
ten outputs for creation of logic functions. At the core of the
device is a programmable electrically-erasable AND array
which drives a fixed-OR array. With this structure, the
XCR22LV10 can implement up to ten sum-of-products logic
expressions.
•
20 additional lines carry the True and Complement
values of feedback or input signals from the ten I/Os
132 product terms:
120 product terms (arranged in two groups of 8, 10, 12,
14, and 16) used to form logical sums
•
•
•
•
•
Ten output enable terms (one for each I/O)
One global synchronous preset product term
One global asynchronous clear product term
Associated with each of the ten OR functions is an I/O mac-
rocell which can be independently programmed to one of
four different configurations. The programmable macrocells
allow each I/O to create sequential or combinatorial logic
functions with either active High or active Low polarity.
At each input-line/product-term intersection there is an
EEPROM memory cell which determines whether or not
there is a logical connection at that intersection. Each prod-
uct term is essentially a 44-input AND gate. A product term
which is connected to both the True and Complement of an
input signal will always be FALSE, and thus will not affect
the OR function that it drives. When all the connections on
a product term are opened, a Don't Care state exists and
that term will always be TRUE.
AND/OR Logic Array
The programmable AND array of the XCR22LV10 (shown
in the Logic Diagram, Figure 1) is formed by input lines
intersecting product terms. The input lines and product
terms are used as follows:
CLK/I0
I1 – I11
1
11
PROGRAMMABLE AND ARRAY
(44 ×
8
10
12
14
16
16
14
12
10
8
132)
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
SP00060A
Figure 2: Functional Diagram
tion of the XCR22LV10 to the precise requirements of their
designs.
Variable Product Term Distribution
The XCR22LV10 provides 120 product terms to drive the
ten OR functions. These product terms are distributed
among the outputs in groups of 8, 10, 12, 14, and 16 to
form logical sums (see Logic Diagram). This distribution
allows optimum use of device resources.
Macrocell Architecture
Each I/O macrocell, as shown in Figure 3 consists of a
D-type flip-flop and two signal-select multiplexers. The con-
figuration of each macrocell of the XCR22LV10 is deter-
mined by the two EEPROM bits controlling these
multiplexers. These bits determine output polarity, and out-
put type (registered or non-registered). Equivalent circuits
for the macrocell configurations are illustrated in Figure 4.
Programmable I/O Macrocell
The output macrocell provides complete control over the
architecture of each output. the ability to configure each
output independently permits users to tailor the configura-
3
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DS047 (v1.1) February 10, 2000
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XCR22LV10: 3V Zero Power, TotalCMOS, Universal PLD
.
S
S
OUTPUT CONFIGURATION
Registered/Active-LOW/Macrocell feedback
Registered/Active-HIGH/Macrocell feedback
Combinatorial/Active-LOW/Pin feedback
Combinatorial/Active-HIGH/Pin feedback
1
0
1
1
0
0
0
1
0
1
0
0
1
1
0
AR
1
0
1
D
Q
F
CLK
Q
0 = Unprogrammed fuse
1 = Programmed fuse
SP
S
1
S
0
0
1
SP00484
Figure 3: Output Macrocell Logic Diagram
S
S
= 0
= 0
S
S
= 0
= 1
0
1
0
1
AR
D
Q
F
F
CLK
Q
SP
a. Registered/Active-LOW
c. Combinatorial/Active-LOW
S
S
= 1
= 0
S
S
= 1
F
0
1
0
1
AR
D
Q
Q
F
CLK
SP
b. Registered/Active-HIGH
d. Combinatorial/Active-HIGH
SP00376
Figure 4: Output Macrocell Configurations
DS047 (v1.1) February 10, 2000
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XCR22LV10: 3V Zero Power, TotalCMOS, Universal PLD
can be used as a dedicated input, a dedicated output, or a
bi-directional I/O.
Output Type
The signal from the OR array can be fed directly to the out-
put pin (combinatorial function) or latched in the D-type
flip-flop (registered function). The D-type flip-flop latches
data on the rising edge of the clock and is controlled by the
global preset and clear terms. When the synchronous pre-
set term is satisfied, the Q output of the register will be set
High at the next rising edge of the clock input. Satisfying the
asynchronous clear term will set Q LOW, regardless of the
clock state. If both terms are satisfied simultaneously, the
clear will override the preset.
Power-On Reset
To ease system initialization, all flip-flops will power-up to a
reset condition and the Q output will be low. The actual out-
put of the XCR22LV10 will depend on the programmed out-
put polarity. The V rise must be monotonic.
CC
Design Security
The XCR22LV10 provides a special EEPROM security bit
that prevents unauthorized reading or copying of designs
programmed into the device. The security bit is set by the
PLD programmer, either at the conclusion of the program-
ming cycle or as a separate step, after the device has been
programmed. Once the security bit is set, it is impossible to
verify (read) or program the XCR22LV10 until the entire
device has first been erased with the bulk-erase function.
Program/Erase Cycles
The XCR22LV10 is 100% testable, erases/programs in
seconds, and guarantees 1000 program/erase erase
cycles.
Output Polarity
Each macrocell can be configured to implement active High
or active Low logic. Programmable polarity eliminates the
need for external inverters.
TotalCMOS Design Technique for Fast Zero
Power
Xilinx is the first to offer a TotalCMOS SPLD, both in pro-
cess technology and design technique. Xilinx employs a
cascade of CMOS gates to implement its Sum of Products
instead of the traditional sense amp approach. This CMOS
gate implementation allows Xilinx to offer SPLDs which are
both high performance and low power, breaking the para-
digm that to have low power, you must accept low perfor-
Output Enable
The output of each I/O macrocell can be enabled or dis-
abled under the control of its associated programmable
output enable product term. When the logical conditions
programmed on the output enable term are satisfied, the
output signal is propagated to the I/O pin. Otherwise, the
output buffer is driven into the high-impedance state.
mance. Refer to Figure 5 and Table 1 showing the I vs.
CC
Frequency of our XCR22LV10 TotalCMOS SPLD.
Under the control of the output enable term, the I/O pin can
function as a dedicated input, a dedicated output, or a bidi-
rectional I/O. Opening every connection on the output
enable term will permanently enable the output buffer and
yield a dedicated output. Conversely, if every connection is
intact, the enable term will always be logically FALSE and
the I/O will function as a dedicated input.
Table 1: Typical I vs. Frequency @ V = 3.3V, 25°C
CC
CC
Frequency (MHz)
Tupical I (mA)
CC
1
0.2
1.5
10
20
3.0
30
4.5
40
6.0
Register Feedback Select
50
7.4
When the I/O macrocell is configured to implement a regis-
tered function (S1=0) (Figure 4a or Figure 4b), the feed-
back signal to the AND array is taken from the Q output.
60
8.9
70
10.4
11.8
13.2
14.5
15.8
17.0
18.2
80
Bi-directional I/O Select
90
When configuring an I/O macrocell to implement a combi-
natorial function (S1=1) (Figure 4c or Figure 4d), the feed-
back signal is taken from the I/O pin. In this case, the pin
100
110
120
130
5
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DS047 (v1.1) February 10, 2000
R
XCR22LV10: 3V Zero Power, TotalCMOS, Universal PLD
30
TYPICAL
25
20
15
10
5
I
CC
(mA)
0
10
20
30
40
50
60
70
80
90
100
110
120
130
1
FREQUENCY (MHz)
SP00443
Figure 5: Typical I vs. Frequency @ V = 3.3V, 25°C (10-bit counter)
CC
CC
Absolute Maximum Ratings1
Symbol
Parameter
Min.
Max.
4.6
Unit
V
V
Supply voltage
–0.5
–0.5
–0.5
–30
–100
0
CC
I
2
V
V
Input voltage
5.5
5.5
V
2
Output voltage
V
OUT
I
I
Input current
30
100
75
mA
mA
°C
°C
°C
IN
OUT
Output current
T
T
T
Allowale thermal rise ambient to junction
Maximum junction temperature
Storage temperature
R
–40
–65
150
150
J
STG
Notes:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation
at these or any other condition above those indicated in the operational and programming specification is not implied..
2. Except F7, where max = VCC + 0.5V.
Operating Range
Product Grade
Commercial
Industrial
Temperature
0 to +70°C
–40 to +85°C
Voltage
3.3V ± ±10%
3.3V ± ±10%
DS047 (v1.1) February 10, 2000
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XCR22LV10: 3V Zero Power, TotalCMOS, Universal PLD
DC Electrical Characteristics For Commercial Grade Devices
Commercial: 0°C ≤ T
≤ +70°C; 3.03.6V ≤ V ≤±3.6V
AMB
CC
Symbol
Parameter
Test Conditions
= 3.0V
Min.
Typ.
Max.
0.8
Unit
V
V
Input voltage Low
Input voltage High
Input clamp voltage
Output voltage Low
Output voltage High
Input leakage current
V
V
V
V
V
V
V
V
V
V
V
V
IL
CC
CC
CC
CC
CC
V
V
V
V
= 3.6V
= 3.0V, I = –18 mA
2
V
IH
I
–1.2
V
IN
= 3.0V, I = 8 mA
0.5
V
OL
OH
OL
= 3.0V, I = –4 mA
2.4
–10
–10
–10
–10
V
OH
I
= 0V to V
CC
10
10
µA
I
IN
IN
IN
IN
2
= V to 5.5V
CC
I
3-stated output leakage current
= 0V to V
10
µA
OZL
CC
2
= V to 5.5V
10
CC
I
I
Standby current
Dynamic current
= 3.6V, T
= 0°C
= 0°C at 1 MHz
= 0°C at 50 MHz
25
0.5
10
45
µA
mA
mA
mA
CCQ
CC
CC
CC
AMB
AMB
AMB
1
= 3.6V, T
= 3.6V, T
2
CCD
15
I
Short circuit output current
One pin at a time for no longer than 1
second
–15
–100
OS
C
C
C
Input pin capacitance
Clock input capacitance
I/O pin capacitance
T
T
T
= 25°C, f = 1 MHz
= 25°C, f = 1 MHz
= 25°C, f = 1 MHz
8
pF
pF
pF
IN
AMB
AMB
AMB
5
12
10
CLK
I/O
Notes:
1. This parameter measured with a 10-bit, with all outputs enabled and unloaded. Inputs are tied to VCC or ground. This
parameter is not 100% tested, but is calculated at initial characterization and at any time the design is modified where
current may be affected.
2. Does not apply to F7.
7
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DS047 (v1.1) February 10, 2000
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XCR22LV10: 3V Zero Power, TotalCMOS, Universal PLD
AC Electrical Characteristics For Commercial Grade Devices
Commercial: 0°C ≤ T
≤ + 70°C; 3.0V ≤ V ≤ 3.6V
AMB
CC
-B
-D
Symbol
Parameter
Unit
Min.
Max.
Min.
Max.
t
Propagation delay time, input or feedback to non-registered output
Setup time from input, feedback or SP to Clock
Clock to output
15
10
ns
ns
PD
t
t
t
t
t
t
t
t
t
t
t
t
f
f
f
t
t
4.5
3.5
SU
10
6
9
4.5
0
ns
CO
CF
1
Clock to feedback
ns
Holt time
0
ns
H
Asynchronous Reset to registered output
Asynchronous Reset width
Asynchronous Reset recovery time
Synchronou Preset recovery time
Width of Clock Low
17
17
ns
AR
5
5
ns
ARW
ARR
SPF
WL
WH
R
6
6
6
6
ns
ns
3
3
3
3
µs
µs
ns
Width of Clock High
Input rise time
20
20
20
20
Input fall time
ns
F
2
Maximum FF toggle rate (1/t + t
)
95
69
125
80
MHz
MHz
MHz
ns
MAX1
MAX2
MAX3
EA
SU
CF
1
Maximum internal frequency (1/t + t
)
SU
CO
1
Maximum external frequency (1/t + t
)
167
167
WL
WH
Input to output enable
Input to output disable
9
9
9
9
ns
ER
Capacitance
C
C
Input pin capacitance
Output capacitance
10
10
10
10
pF
pF
IN
OUT
Notes:
1. This parameter is not 100% tested, but is calculated at initial characterization and at any time the design is modified where current may
be affected.
2. This parameter measured with a 10-bit, with all outputs enabled and unloaded. Inputs are tied to VCC or ground. This parameter is not
100% tested, but is calculated at initial characterization and at any time the design is modified where current may be affected.
DS047 (v1.1) February 10, 2000
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XCR22LV10: 3V Zero Power, TotalCMOS, Universal PLD
DC Electrical Characteristics For Industrial Grade Devices
Industrial: –40°C ≤ T
≤ +85°C; 3.0V ≤ V ≤±3.6V
AMB
CC
Symbol
Parameter
Test Conditions
= 3.0V
Min.
Typ.
Max.
0.8
Unit
V
V
Input voltage Low
Input voltage High
Input clamp voltage
Output voltage Low
Output voltage High
Input leakage current
V
V
V
V
V
V
V
V
V
V
V
V
IL
CC
CC
CC
CC
CC
V
V
V
V
= 3.6V
= 3.0V, I = –18 mA
2
V
IH
I
–1.2
V
IN
= 3.0V, I = 8 mA
0.5
V
OL
OH
OL
= 3.0V, I = –4 mA
2.4
–10
–10
–10
–10
V
OH
I
= 0V to V
CC
10
10
µA
I
IN
IN
IN
IN
2
= V to 5.5V
CC
I
3-stated output leakage current
= 0V to V
10
µA
OZL
CC
2
= V to 5.5V
10
CC
I
I
Standby current
Dynamic current
= 3.6V, T
= –40°C
= –40°C at 1 MHz
= –40°C at 50 MHz
30
0.5
10
45
µA
mA
mA
mA
CCQ
CC
CC
CC
AMB
AMB
AMB
1
= 3.6V, T
= 3.6V, T
3
CCD
20
I
Short circuit output current
One pin at a time for no longer than 1
second
–15
–100
OS
C
C
C
Input pin capacitance
Clock input capacitance
I/O pin capacitance
T
T
T
= 25°C, f = 1 MHz
= 25°C, f = 1 MHz
= 25°C, f = 1 MHz
8
pF
pF
pF
IN
AMB
AMB
AMB
5
12
10
CLK
I/O
Notes:
1. This parameter measured with a 10-bit, with all outputs enabled and unloaded. Inputs are tied to VCC or ground. This
parameter is not 100% tested, but is calculated at initial characterization and at any time the design is modified where
current may be affected.
2. Does not apply to F7.
9
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DS047 (v1.1) February 10, 2000
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XCR22LV10: 3V Zero Power, TotalCMOS, Universal PLD
AC Electrical Characteristics For Industrial Grade Devices
Industrial: –40°C ≤ T
≤ +85°C; 3.0V ≤ V ≤±3.6V
AMB
CC
Symbol
Parameter
Unit
Min.
Max.
t
Propagation delay time, input or feedback to non-registered output
Setup time from input, feedback or SP to Clock
Clock to output
15
ns
ns
PD
t
t
t
t
t
t
t
t
t
t
t
t
f
f
f
t
t
5
SU
10.5
6
ns
CO
CF
1
Clock to feedback
ns
Holt time
0
ns
H
Asynchronous Reset to registered output
Asynchronous Reset width
Asynchronous Reset recovery time
Synchronou Preset recovery time
Width of Clock Low
17
ns
AR
5
ns
ARW
ARR
SPF
WL
WH
R
6
6
ns
ns
3
3
µs
µs
ns
Width of Clock High
Input rise time
20
20
Input fall time
ns
F
2
Maximum FF toggle rate (1/t + t
)
91
65
MHz
MHz
MHz
ns
MAX1
MAX2
MAX3
EA
SU
CF
1
Maximum internal frequency (1/t + t
)
SU
CO
1
Maximum external frequency (1/t + t
)
167
WL
WH
Input to output enable
Input to output disable
11
11
ns
ER
Capacitance
C
C
Input pin capacitance
Output capacitance
10
12
pF
pF
IN
OUT
Notes:
1. This parameter is not 100% tested, but is calculated at initial characterization and at any time the design is modified
where current may be affected.
2. This parameter measured with a 10-bit, with all outputs enabled and unloaded. Inputs are tied to VCC or ground. This parameter is
not 100% tested, but is calculated at initial characterization and at any time the design is modified where current may be affected.
DS047 (v1.1) February 10, 2000
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XCR22LV10: 3V Zero Power, TotalCMOS, Universal PLD
Test Load Circuit
V
+3.3V
S
1
CC
C
C
2
R
1
1
I
0
F
0
C
R
L
2
DUT
INPUTS
F
I
n
n
OE
CK
GND
NOTE:
C
R
and C are to bypass V to GND.
1
1
2
CC
= 300Ω, R = 300Ω, C = 35pF.
2
L
SP00478
Thevenin Equivalent
= 1.65V
V
L
150Ω
DUT OUTPUT
35 pF
Voltage Waveform
+3.0V
90%
10%
0V
t
R
t
F
1.5ns
1.5ns
SP00368
MEASUREMENTS:
All circuit delays are measured at the +1.5V level of
inputs and outputs, unless otherwise specified.
Input Pulses
11
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DS047 (v1.1) February 10, 2000
R
XCR22LV10: 3V Zero Power, TotalCMOS, Universal PLD
Switching Waveforms
INPUT OR
FEEDBACK
INPUT OR
V
V
T
T
FEEDBACK
t
t
t
H
PD
S
COMBINATORIAL
OUTPUT
CLOCK
V
V
T
T
t
CO
REGISTERED
OUTPUT
V
T
Combinatorial Output
Registered Output
INPUT
V
T
t
WH
t
t
ER
EA
CLOCK
V
T
V
– 0.5V
OH
OUTPUT
V
T
V
+ 0.5V
OL
t
WL
Clock Width
Input to Output Disable/Enable
t
ARW
INPUT ASSERTING
ASYNCHRONOUS
RESET
INPUT ASSERTING
SYNCHRONOUS
PRESET
V
V
T
T
t
t
t
t
SPR
AR
S
H
REGISTERED
OUTPUT
CLOCK
V
V
V
T
T
T
t
t
ARR
CO
REGISTERED
OUTPUT
CLOCK
V
T
V
T
Asynchronous Reset
Synchronous Preset
NOTES:
1.
V = 1.5V.
T
2. Input pulse amplitude 0V to 3.0V.
3. Input rise and fall times 2.0 ns max.
SP00483
"AND" Array: (I,B)
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
P, D
P, D
P, D
P, D
STATE
CODE
STATE
TRUE
CODE
STATE
CODE
STATE
CODE
1
O
H
COMPLEMENT
L
DON’T CARE
—
INACTIVE
SP00008
DS047 (v1.1) February 10, 2000
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12
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R
XCR22LV10: 3V Zero Power, TotalCMOS, Universal PLD
Pin Descriptions
Pin Configurations
Pin Label
I1-I11
Description
Dedicated input
28-pin PLCC
NC
Not Connected
F0-F9
I0/CLK
Macrocell Input/Output
Dedicated Input/Clock Output
Supply Voltage
V
4
3
2
1
28 27 26
CC
GND
Ground
I3
I4
5
6
25 F7
24 F6
23 F5
22 NC
21 F4
20 F3
19 F2
I5
7
NC
I6
8
9
I7
10
11
I8
12 13 14 15 16 17 18
SP00474
24-pin SOIC and 24-pin TSOIC
IO/CLK
1
2
3
4
5
6
7
8
9
24 V
CC
I1
I2
I3
I4
I5
I6
I7
I8
23 F9
22 F8
21 F7
20 F6
19 F5
18 F4
17 F3
16 F2
15 F1
14 F0
13 I11
I9 10
I10 11
GND 12
AP00475
13
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DS047 (v1.1) February 10, 2000
R
XCR22LV10: 3V Zero Power, TotalCMOS, Universal PLD
Ordering Information
Example: XCR22LV10 -10 PC 28 C
Temperature Range
Number of Pins
Package Type
Device Type
Speed Options
Temperature Range
Speed Options
C = Commercial, T = 0°C to +70°C
-15: 15 ns pin-to-pin delay
-10: 10 ns pin-to-pin delay
A
I = Industrial, T = –40°C to +85°C
A
Packaging Options
SO24: 24-pin SOIC
VO24: 24-pin TSOIC
PC28: 28-pin PLCC
Component Availability
Pins
24
28
Plastic PLCC
PC28
Type
Plastic SOIC
SO24
Plastic Thin SOIC
Code
VO24
C, I
C
XCR22LV10
-15
-10
C, I
C
Revision History
Date
8/4/99
2/10/00
Version #
1.0
Revision
Initial Xilinx release.
1.1
Convert to Xilinx Format
DS047 (v1.1) February 10, 2000
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