XCR3032XL-10CSG48I [XILINX]
XCR3032XL 32 Macrocell CPLD; XCR3032XL 32宏单元CPLD
| 型号： | XCR3032XL-10CSG48I |
| 厂家： | 
XILINX, INC |
| 描述： | XCR3032XL 32 Macrocell CPLD |
| 文件： | 总9页 (文件大小：219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0
R
XCR3032XL 32 Macrocell CPLD
0
14
DS023 (v2.2) September 15, 2008
Product Specification
Features
Description
•
•
•
•
•
Low power 3.3V 32 macrocell CPLD
4.5 ns pin-to-pin logic delays
System frequencies up to 213 MHz
32 macrocells with 750 usable gates
Available in small footprint packages
The CoolRunner™ XPLA3 XCR3032XL device is a 3.3V,
32-macrocell CPLD targeted at power sensitive designs
that require leading edge programmable logic solutions. A
total of two function blocks provide 750 usable gates.
Pin-to-pin propagation delays are as fast as 4.5 ns with a
maximum system frequency of 213 MHz.
-
-
48-ball CS BGA (36 user I/O pins)
44-pin VQFP (36 user I/Os)
TotalCMOS Design Technique for Fast
Zero Power
•
Optimized for 3.3V systems
-
-
-
-
Ultra-low power operation
Typical Standby Current of 17 μA at 25°C
5V tolerant I/O pins with 3.3V core supply
Advanced 0.35 micron five layer metal EEPROM
process
CoolRunner XPLA3 CPLDs offer a TotalCMOS solution,
both in process technology and design technique. Xilinx®
CPLDs employ a cascade of CMOS gates to implement its
sum of products instead of the traditional sense amp
approach. This CMOS gate implementation allows Xilinx to
offer CPLDs that are both high performance and low power,
breaking the paradigm that to have low power, one must
have low performance. Refer to Figure 1 and Table 1 show-
-
-
Fast Zero Power (FZP) CMOS technology
3.3V PCI electrical specification compatible
outputs (no internal clamp diode on any input or
I/O, no minimum clock input capacitance)
ing the I vs. Frequency of the XCR3032XL TotalCMOS
CC
•
Advanced system features
CPLD (data taken with two resetable up/down, 16-bit
counters at 3.3V, 25° C).
-
-
-
-
-
-
-
-
In-system programming
Input registers
Predictable timing model
Up to 23 available clocks per function block
Excellent pin retention during design changes
Full IEEE Standard 1149.1 boundary-scan (JTAG)
Four global clocks
20
15
10
Eight product term control terms per function block
•
•
•
Fast ISP programming times
Port Enable pin for dual function of JTAG ISP pins
2.7V to 3.6V supply voltage at industrial temperature
range
5
0
•
•
•
Programmable slew rate control per macrocell
Security bit prevents unauthorized access
Refer to the CoolRunner XPLA3 family data sheet
0
20
40
60
80 100 120
140 160 180 200
(DS012) for architecture description
Frequency (MHz)
DS023_01_080101
Figure 1: I vs. Frequency at V = 3.3V, 25°C
CC
CC
Table 1: I vs. Frequency (V = 3.3V, 25°C)
CC
CC
Frequency (MHz)
0
1
5
10
20
50
100
10.26
200
Typical I (mA)
0.017
0.13
0.54
1.06
2.09
5.2
20.3
CC
© 2000–2008 Xilinx, Inc. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS023 (v2.2) September 15, 2008
Product Specification
www.xilinx.com
1
R
XCR3032XL 32 Macrocell CPLD
DC Electrical Characteristics Over Recommended Operating Conditions
(1)
Symbol
Parameter
Test Conditions
= 3.0V to 3.6V, I = –8 mA
Typical
Min.
2.4
Max. Unit
(2)
V
Output High voltage
V
V
I
-
-
-
V
V
OH
CC
CC
OH
= 2.7V to 3.0V, I = –8 mA
-
2.0
OH
(3)
= –500 μA
-
90% V
-
V
OH
CC
V
I
Output Low voltage
Input leakage current
I/O High-Z leakage current
Standby current
I
= 8 mA
OL
-
-
0.4
10
10
100
0.25
7.5
8
V
OL
(4)
V
V
V
= GND or V to 5.5V
-
–10
μA
μA
μA
mA
mA
pF
pF
pF
IL
IN
IN
CC
(4)
I
= GND or V to 5.5V
-
–10
IH
CC
(8)
I
I
= 3.6V
CC
24.5
-
-
-
-
-
-
CCSB
CC
(5,6)
Dynamic current
f = 1 MHz
f = 50 MHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
-
-
-
-
-
(7)
C
C
C
Input pin capacitance
IN
(7)
Clock input capacitance
12
10
CLK
(7)
I/O pin capacitance
I/O
Notes:
1. See the CoolRunner XPLA3 family data sheet (DS012) for recommended operating conditions.
2. See Figure 2 for output drive characteristics of the XPLA3 family.
3. This parameter guaranteed by design and characterization, not by testing.
4. Typical leakage current is less than 1 μA.
5. See Table 1, Figure 1 for typical values.
6. This parameter measured with a 16-bit, resetable up/down counter loaded into every function block, with all outputs disabled and
unloaded. Inputs are tied to VCC or ground. This parameter guaranteed by design and characterization, not testing.
7. Typical values, not tested.
8. Typical value at 70°C.
100
90
I
(3.3V)
OL
80
70
60
50
40
30
I
(3.3V)
OH
I
(2.7V)
OH
20
10
0
0
0.5
1
1.5
2
2.5
Volts
3
3.5
4
4.5
5
DS012_10_031802
Figure 2: Typical I/V Curve for the CoolRunner XPLA3 Family, 25°C
2
www.xilinx.com
DS023 (v2.2) September 15, 2008
Product Specification
R
XCR3032XL 32 Macrocell CPLD
AC Electrical Characteristics Over Recommended Operating Conditions
-5
-7
-10
(1, 2)
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Unit
T
Propagation delay time (single p-term)
4.5
5.0
3.5
-
-
-
7.0
7.5
5.0
-
-
9.1
10.0
6.5
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
μs
PD1
PD2
CO
(3)
T
T
T
T
T
T
T
T
Propagation delay time (OR array)
-
Clock to output (global synchronous pin clock)
Setup time (fast input register)
Setup time (single p-term)
Setup time (OR array)
-
2.5
3.0
3.0
SUF
SU1
SU2
(4)
3.0
-
4.3
-
5.4
-
3.5
-
4.8
-
6.3
-
(4)
Hold time
0
-
0
-
0
-
H
(4)
Global Clock pulse width (High or Low)
P-term clock pulse width
2.5
-
3.0
-
4.0
-
WLH
(4)
4.0
-
5.0
-
6.0
-
PLH
T
Asynchronous preset/reset pulse width (High or Low)
Input rise time
4.0
-
5.0
-
6.0
-
APRPW
(4)
T
-
-
-
-
-
-
-
-
-
20
20
213
30
30
7.2
7.2
6.0
6.5
-
-
-
-
-
-
-
-
-
20
20
119
30
30
9.3
9.3
8.3
9.3
-
-
-
-
-
-
-
-
-
20
20
95
30
30
11.2
11.2
10.7
11.2
R
(4)
T
Input fall time
L
(4)
(4)
f
Maximum system frequency
SYSTEM
(5)
T
T
T
T
T
T
Configuration time
CONFIG
(4)
ISP initialization time
μs
INIT
(4)
P-term OE to output enabled
ns
ns
ns
ns
POE
POD
PCO
(4)
(4)
(6)
P-term OE to output disabled
P-term clock to output
(4)
P-term set/reset to output valid
PAO
Notes:
1. Specifications measured with one output switching.
2. See CoolRunner XPLA3 family data sheet (DS012) for recommended operating conditions.
3. See Figure 4 for derating.
4. These parameters guaranteed by design and/or characterization, not testing.
5. Typical current draw during configuration is 3 mA at 3.6V.
6. Output CL = 5 pF.
DS023 (v2.2) September 15, 2008
www.xilinx.com
3
Product Specification
R
XCR3032XL 32 Macrocell CPLD
Internal Timing Parameters
-5
-7
-10
(1, 2)
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Buffer Delays
T
T
T
T
T
Input buffer delay
-
-
-
-
-
0.7
2.2
0.7
1.8
4.5
-
-
-
-
-
1.6
3.0
1.0
2.7
5.0
-
-
-
-
-
2.2
3.1
1.3
3.6
5.7
ns
ns
ns
ns
ns
IN
Fast Input buffer delay
Global Clock buffer delay
Output buffer delay
FIN
GCK
OUT
EN
Output buffer enable/disable delay
Internal Register, Product Term, and Combinatorial Delays
T
T
T
T
T
T
Latch transparent delay
-
1.0
0.3
2.0
3.0
-
1.3
-
-
1.0
0.5
2.5
4.5
-
1.6
-
-
1.2
0.7
3.0
5.5
-
2.0
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LDI
Register setup time
SUI
Register hold time
-
-
-
HI
Register clock enable setup time
Register clock enable hold time
Register clock to output delay
Register async. S/R to output delay
Register async. recovery
-
-
-
ECSU
ECHO
COI
-
-
-
1.0
2.0
3.5
2.5
2.0
2.5
1.3
2.3
5.0
2.7
2.7
3.2
1.6
2.1
6.0
3.3
3.3
4.2
T
-
-
-
AOI
T
-
-
-
RAI
T
T
T
Product term clock delay
-
-
-
PTCK
LOGI1
LOGI2
Internal logic delay (single p-term)
Internal logic delay (PLA OR term)
-
-
-
-
-
-
Feedback Delays
ZIA delay
Time Adders
T
-
0.2
-
2.9
-
3.5
ns
F
T
T
T
Foldback NAND delay
Universal delay
-
-
-
2.0
1.2
4.0
-
-
-
2.5
2.0
5.0
-
-
-
3.0
2.5
6.0
ns
ns
ns
LOGI3
UDA
Slew rate limited delay
SLEW
Notes:
1. These parameters guaranteed by design and characterization, not testing.
2. See the CoolRunner XPLA3 family data sheet (DS012) for timing model.
4
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DS023 (v2.2) September 15, 2008
Product Specification
R
XCR3032XL 32 Macrocell CPLD
Switching Characteristics
V
CC
S1
Component
Values
R1
R2
C1
390Ω
390Ω
35 pF
R1
V
IN
V
OUT
Measurement
S1
S2
Open
Closed
Closed
Closed
Open
Closed
T
T
(High)
POE
R2
C1
(Low)
POE
T
P
Note: For T
, C1 = 5 pF. Delay measured at
POD
output level of V + 300 mV, V
– 300 mV.
OH
OL
S2
DS023_03_102401
Figure 3: AC Load Circuit
4.5
+3.0V
0V
90%
10%
4.0
3.5
T
R
T
L
1.5 ns
1.5 ns
Measurements:
All circuit delays are measured at the +1.5V level of
inputs and outputs, unless otherwise specified.
3.0
1
2
4
8
16
DS023_06_042800
Outputs
Figure 5: Voltage Waveform
DS023_05_061101
Figure 4: Derating Curve for T
PD2
DS023 (v2.2) September 15, 2008
www.xilinx.com
5
Product Specification
R
XCR3032XL 32 Macrocell CPLD
Table 3: XCR3032XL I/O Pins
Pin Descriptions
Function
(1)
Block
Macrocell
PC44
31
VQ44
25
CS48
E7
Table 2: XCR3032XL User I/O Pins
(1)
2
2
2
2
2
2
2
10
11
12
13
14
15
16
PC44
VQ44
CS48
29
23
F7
Total User I/O Pins
36
36
36
28
22
G7
G6
F5
1. This is an obsolete package type. It remains here for legacy
support only.
27
21
Table 3: XCR3032XL I/O Pins
26
20
Function
Block
25
19
G5
F4
(1)
Macrocell
PC44
VQ44
42
CS48
A2
24
18
1
1
2
4
5
6
Notes:
1
43
A1
1. This is an obsolete package type. It remains here for legacy
support only.
2. JTAG pins.
1
3
44
C4
(2)
(2)
(2)
1
4
7
1
B1
1
5
8
9
2
3
5
6
C2
C1
D3
D1
Table 4: XCR3032XL Global, JTAG, Port Enable, Power,
and No Connect Pins
1
6
(1)
Pin Type
IN0 / CLK0
IN1 / CLK1
IN2 / CLK2
IN3 / CLK3
TCK
PC44
2
VQ44
40
39
38
37
26
1
CS48
A3
1
7
11
12
1
8
(2)
(2)
(2)
1
B4
1
9
13
14
7
D2
44
43
32
7
A4
1
10
11
12
13
14
15
16
1
8
E1
F1
G1
E4
F2
G2
F3
C5
A6
B6
B5
1
16
17
18
19
20
21
41
40
39
10
11
12
13
14
15
35
34
33
E5
1
TDI
B1
1
TDO
38
13
32
7
B7
1
TMS
D2
1
(2)
(2)
(2)
PORT_EN
10
4
C3
1
V
3, 15, 23,
35
9, 17, 29,
41
B3, C7, E2,
G4
2
CC
2
2
GND
22, 30, 42
-
16, 24, 36
-
A5, E3, E6
2
3
No Connects
A7, B2, F6,
G3
(2)
(2)
(2)
2
4
38
32
B7
2
5
37
36
34
33
31
30
28
27
D4
C6
D6
D7
Notes:
1. This is an obsolete package type. It remains here for legacy
2
6
support only.
2
7
2. Port Enable is brought High to enable JTAG pins when JTAG
pins are used as I/O. See family data sheet (DS012) for full
explanation.
2
8
(2)
(2)
(2)
2
9
32
26
E5
6
www.xilinx.com
DS023 (v2.2) September 15, 2008
Product Specification
R
XCR3032XL 32 Macrocell CPLD
Device Part Marking
R
Device Type
XCRxxxxXL
TQ144
Package
This line not
related to device
part number
Speed
7C
Operating Range
1
Sample package with part marking.
Notes:
1. Due to the small size of chip scale packages, part marking on these packages does not follow the above
sample and the complete part number cannot be included in the marking. Part marking on chip scale
packages by line:
·
·
·
·
Line 1 = X (Xilinx logo), then truncated part number (no XC), i.e., 3064XL.
Line 2 = Not related to device part number.
Line 3 = Not related to device part number.
Line 4 = Package code, speed, operating temperature, three digits not related to device
part number. Package codes; C1 = CS48, C2 = CSG48.
Ordering Combination Information
Speed
Device Ordering and
Part Marking Number
(pin-to-pin
delay)
Pkg.
Symbol
No. of
Pins
Operating
Range
(1)
Package Type
XCR3032XL-5VQ44C
XCR3032XL-5VQG44C
XCR3032XL-5CS48C
XCR3032XL-5CSG48C
XCR3032XL-7VQ44C
XCR3032XL-7VQG44C
XCR3032XL-7CS48C
XCR3032XL-7CSG48C
XCR3032XL-7VQ44I
XCR3032XL-7VQG44I
XCR3032XL-7CS48I
XCR3032XL-7CSG48I
XCR3032XL-10VQ44C
XCR3032XL-10VQG44C
XCR3032XL-10CS48C
XCR3032XL-10CSG48C
XCR3032XL-10VQ44I
5 ns
5 ns
VQ44
VQG44
CS48
44
44
48
48
44
44
48
48
44
44
48
48
44
44
48
48
44
Very Thin Quad Flat Pack (VQFP)
Very Thin Quad Flat Pack (VQFP); Pb-Free
Chip Scale Package (CSP)
C
C
C
C
C
C
C
C
I
5 ns
5 ns
CSG48
VQ44
Chip Scale Package (CSP); Pb-Free
Very Thin Quad Flat Pack (VQFP)
Very Thin Quad Flat Pack (VQFP); Pb-Free
Chip Scale Package (CSP)
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
10 ns
10 ns
10 ns
10 ns
10 ns
VQG44
CS48
CSG48
VQ44
Chip Scale Package (CSP); Pb-Free
Very Thin Quad Flat Pack (VQFP)
Very Thin Quad Flat Pack (VQFP); Pb-Free
Chip Scale Package (CSP)
VQG44
CS48
I
I
CSG48
VQ44
Chip Scale Package (CSP); Pb-Free
Very Thin Quad Flat Pack (VQFP)
Very Thin Quad Flat Pack (VQFP); Pb- Free
Chip Scale Package (CSP)
I
C
C
C
C
I
VQG44
CS48
CSG48
VQ44
Chip Scale Package (CSP); Pb-Free
Very Thin Quad Flat Pack (VQFP)
DS023 (v2.2) September 15, 2008
www.xilinx.com
7
Product Specification
R
XCR3032XL 32 Macrocell CPLD
Ordering Combination Information (Continued)
Speed
Device Ordering and
Part Marking Number
(pin-to-pin
delay)
Pkg.
Symbol
No. of
Pins
Operating
Range
(1)
Package Type
XCR3032XL-10VQG44I
XCR3032XL-10CS48I
XCR3032XL-10CSG48I
Notes:
10 ns
10 ns
10 ns
VQG44
CS48
44
48
48
Very Thin Quad Flat Pack (VQFP); Pb-Free
Chip Scale Package (CSP)
I
I
I
CSG48
Chip Scale Package (CSP); Pb-Free
1. C = Commercial: TA = 0° to +70°C; I = Industrial: TA = –40° to +85°C
8
www.xilinx.com
DS023 (v2.2) September 15, 2008
Product Specification
R
XCR3032XL 32 Macrocell CPLD
Warranty Disclaimer
THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED
AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE
PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE
THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE
AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF
LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
Additional Information
CoolRunner XPLA3 CPLD Data Sheets and Application
Notes
Device Packages
Device Package User Guide
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revision
11/18/00
02/05/01
04/11/01
Initial Xilinx release.
1.1
Removed Timing Model.
1.2
Update TSUF spec to meet UMC characterization data. Added Icc vs. Freq. numbers,
Table 1 and updated Figure 1. Added Typical I/V curve, Figure 2; added Table 2: Total User
I/O; changed V spec.
OH
04/19/01
08/27/01
1.3
1.4
Updated Typical I/V curve, Figure 2: added voltage levels.
Changed from Advance to Preliminary; updated DC Electrical Characteristics; AC Electrical
Characteristics; Internal Timing Parameters; added Derating Curve; added -10 industrial
packages. Added 200 MHz to Figure 1 and Table 1. changed -5 F
to 0.5 ns.
to 200 MHz, -5 T
SYSTEM
F
01/08/02
01/06/03
1.5
1.6
Updated T spec to correct a typo. Added single p-term setup time (T
) to AC Table,
SU1
HI
renamed T to T
for setup time through the OR array. Updated AC Load Circuit diagram
SU
SU2
to more closely resemble true test conditions, added note for T
delay
POD
measurement.Updated note 5 in AC Characteristics table lowering typical current draw
during configuration.
Added voltage and temperature to Figure 2. Increased -5 T
to 6.0 (from 5.5 ns) by
PCO
adding T
parameter to internal timing model. Increased -5 F
. Updated Ordering
PTCK
MAX
Information format.
07/15/03
08/21/03
02/13/04
1.7
1.8
1.9
Updated Device Part Marking. Updated test conditions for I and I .
IL
IH
Updated Package Device Marking Pin 1 orientation.
Add solder temperature specification. Add links to data sheets, application notes and
packages.
04/08/05
2.0
Added I
Typical and T
specifications. Removed T
specification. Added note
CCSB
APRPW
SOL
about Pb-free packages.
03/31/06
09/15/08
2.1
2.2
Added Warranty Disclaimer; Added Pb-Free ordering information.
Added notes to tables to indicate PC44 and PCG44 packages are obsolete. Removed part
number references to the obsolete PC44C and PCG44C packages in the Ordering
Combination Information. See Product Discontinuation Notice xcn07022.pdf.
DS023 (v2.2) September 15, 2008
www.xilinx.com
9
Product Specification
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